| 1 | /** @file
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| 2 | Platform TPM Profile Specification definition for TPM2.0.
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| 3 | It covers both FIFO and CRB interface.
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| 4 |
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| 5 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 7 |
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| 8 | **/
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| 9 |
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| 10 | #ifndef _TPM_PTP_H_
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| 11 | #define _TPM_PTP_H_
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| 12 |
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| 13 | //
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| 14 | // PTP FIFO definition
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| 15 | //
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| 16 |
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| 17 | //
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| 18 | // Set structure alignment to 1-byte
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| 19 | //
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| 20 | #pragma pack (1)
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| 21 |
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| 22 | //
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| 23 | // Register set map as specified in PTP specification Chapter 5
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| 24 | //
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| 25 | typedef struct {
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| 26 | ///
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| 27 | /// Used to gain ownership for this particular port.
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| 28 | ///
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| 29 | UINT8 Access; // 0
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| 30 | UINT8 Reserved1[7]; // 1
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| 31 | ///
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| 32 | /// Controls interrupts.
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| 33 | ///
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| 34 | UINT32 IntEnable; // 8
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| 35 | ///
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| 36 | /// SIRQ vector to be used by the TPM.
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| 37 | ///
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| 38 | UINT8 IntVector; // 0ch
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| 39 | UINT8 Reserved2[3]; // 0dh
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| 40 | ///
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| 41 | /// What caused interrupt.
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| 42 | ///
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| 43 | UINT32 IntSts; // 10h
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| 44 | ///
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| 45 | /// Shows which interrupts are supported by that particular TPM.
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| 46 | ///
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| 47 | UINT32 InterfaceCapability; // 14h
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| 48 | ///
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| 49 | /// Status Register. Provides status of the TPM.
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| 50 | ///
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| 51 | UINT8 Status; // 18h
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| 52 | ///
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| 53 | /// Number of consecutive writes that can be done to the TPM.
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| 54 | ///
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| 55 | UINT16 BurstCount; // 19h
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| 56 | ///
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| 57 | /// Additional Status Register.
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| 58 | ///
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| 59 | UINT8 StatusEx; // 1Bh
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| 60 | UINT8 Reserved3[8];
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| 61 | ///
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| 62 | /// Read or write FIFO, depending on transaction.
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| 63 | ///
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| 64 | UINT32 DataFifo; // 24h
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| 65 | UINT8 Reserved4[8]; // 28h
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| 66 | ///
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| 67 | /// Used to identify the Interface types supported by the TPM.
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| 68 | ///
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| 69 | UINT32 InterfaceId; // 30h
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| 70 | UINT8 Reserved5[0x4c]; // 34h
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| 71 | ///
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| 72 | /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
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| 73 | ///
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| 74 | UINT32 XDataFifo; // 80h
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| 75 | UINT8 Reserved6[0xe7c]; // 84h
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| 76 | ///
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| 77 | /// Vendor ID
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| 78 | ///
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| 79 | UINT16 Vid; // 0f00h
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| 80 | ///
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| 81 | /// Device ID
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| 82 | ///
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| 83 | UINT16 Did; // 0f02h
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| 84 | ///
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| 85 | /// Revision ID
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| 86 | ///
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| 87 | UINT8 Rid; // 0f04h
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| 88 | UINT8 Reserved[0xfb]; // 0f05h
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| 89 | } PTP_FIFO_REGISTERS;
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| 90 |
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| 91 | //
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| 92 | // Restore original structure alignment
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| 93 | //
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| 94 | #pragma pack ()
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| 95 |
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| 96 | //
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| 97 | // Define pointer types used to access TIS registers on PC
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| 98 | //
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| 99 | typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;
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| 100 |
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| 101 | //
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| 102 | // Define bits of FIFO Interface Identifier Register
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| 103 | //
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| 104 | typedef union {
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| 105 | struct {
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| 106 | UINT32 InterfaceType : 4;
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| 107 | UINT32 InterfaceVersion : 4;
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| 108 | UINT32 CapLocality : 1;
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| 109 | UINT32 Reserved1 : 2;
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| 110 | UINT32 CapDataXferSizeSupport : 2;
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| 111 | UINT32 CapFIFO : 1;
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| 112 | UINT32 CapCRB : 1;
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| 113 | UINT32 CapIFRes : 2;
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| 114 | UINT32 InterfaceSelector : 2;
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| 115 | UINT32 IntfSelLock : 1;
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| 116 | UINT32 Reserved2 : 4;
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| 117 | UINT32 Reserved3 : 8;
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| 118 | } Bits;
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| 119 | UINT32 Uint32;
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| 120 | } PTP_FIFO_INTERFACE_IDENTIFIER;
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| 121 |
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| 122 | //
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| 123 | // Define bits of FIFO Interface Capability Register
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| 124 | //
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| 125 | typedef union {
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| 126 | struct {
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| 127 | UINT32 DataAvailIntSupport : 1;
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| 128 | UINT32 StsValidIntSupport : 1;
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| 129 | UINT32 LocalityChangeIntSupport : 1;
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| 130 | UINT32 InterruptLevelHigh : 1;
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| 131 | UINT32 InterruptLevelLow : 1;
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| 132 | UINT32 InterruptEdgeRising : 1;
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| 133 | UINT32 InterruptEdgeFalling : 1;
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| 134 | UINT32 CommandReadyIntSupport : 1;
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| 135 | UINT32 BurstCountStatic : 1;
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| 136 | UINT32 DataTransferSizeSupport : 2;
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| 137 | UINT32 Reserved : 17;
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| 138 | UINT32 InterfaceVersion : 3;
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| 139 | UINT32 Reserved2 : 1;
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| 140 | } Bits;
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| 141 | UINT32 Uint32;
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| 142 | } PTP_FIFO_INTERFACE_CAPABILITY;
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| 143 |
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| 144 | ///
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| 145 | /// InterfaceVersion
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| 146 | ///
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| 147 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0
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| 148 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2
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| 149 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3
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| 150 |
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| 151 | //
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| 152 | // Define bits of ACCESS and STATUS registers
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| 153 | //
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| 154 |
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| 155 | ///
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| 156 | /// This bit is a 1 to indicate that the other bits in this register are valid.
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| 157 | ///
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| 158 | #define PTP_FIFO_VALID BIT7
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| 159 | ///
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| 160 | /// Indicate that this locality is active.
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| 161 | ///
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| 162 | #define PTP_FIFO_ACC_ACTIVE BIT5
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| 163 | ///
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| 164 | /// Set to 1 to indicate that this locality had the TPM taken away while
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| 165 | /// this locality had the TIS_PC_ACC_ACTIVE bit set.
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| 166 | ///
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| 167 | #define PTP_FIFO_ACC_SEIZED BIT4
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| 168 | ///
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| 169 | /// Set to 1 to indicate that TPM MUST reset the
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| 170 | /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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| 171 | /// locality that is writing this bit.
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| 172 | ///
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| 173 | #define PTP_FIFO_ACC_SEIZE BIT3
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| 174 | ///
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| 175 | /// When this bit is 1, another locality is requesting usage of the TPM.
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| 176 | ///
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| 177 | #define PTP_FIFO_ACC_PENDIND BIT2
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| 178 | ///
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| 179 | /// Set to 1 to indicate that this locality is requesting to use TPM.
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| 180 | ///
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| 181 | #define PTP_FIFO_ACC_RQUUSE BIT1
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| 182 | ///
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| 183 | /// A value of 1 indicates that a T/OS has not been established on the platform
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| 184 | ///
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| 185 | #define PTP_FIFO_ACC_ESTABLISH BIT0
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| 186 |
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| 187 | ///
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| 188 | /// This field indicates that STS_DATA and STS_EXPECT are valid
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| 189 | ///
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| 190 | #define PTP_FIFO_STS_VALID BIT7
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| 191 | ///
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| 192 | /// When this bit is 1, TPM is in the Ready state,
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| 193 | /// indicating it is ready to receive a new command.
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| 194 | ///
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| 195 | #define PTP_FIFO_STS_READY BIT6
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| 196 | ///
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| 197 | /// Write a 1 to this bit to cause the TPM to execute that command.
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| 198 | ///
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| 199 | #define PTP_FIFO_STS_GO BIT5
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| 200 | ///
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| 201 | /// This bit indicates that the TPM has data available as a response.
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| 202 | ///
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| 203 | #define PTP_FIFO_STS_DATA BIT4
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| 204 | ///
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| 205 | /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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| 206 | ///
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| 207 | #define PTP_FIFO_STS_EXPECT BIT3
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| 208 | ///
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| 209 | /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
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| 210 | ///
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| 211 | #define PTP_FIFO_STS_SELFTEST_DONE BIT2
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| 212 | ///
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| 213 | /// Writes a 1 to this bit to force the TPM to re-send the response.
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| 214 | ///
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| 215 | #define PTP_FIFO_STS_RETRY BIT1
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| 216 |
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| 217 | ///
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| 218 | /// TPM Family Identifier.
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| 219 | /// 00: TPM 1.2 Family
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| 220 | /// 01: TPM 2.0 Family
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| 221 | ///
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| 222 | #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
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| 223 | #define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
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| 224 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
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| 225 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
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| 226 | ///
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| 227 | /// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
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| 228 | /// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
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| 229 | ///
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| 230 | #define PTP_FIFO_STS_EX_CANCEL BIT0
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| 231 |
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| 232 | //
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| 233 | // PTP CRB definition
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| 234 | //
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| 235 |
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| 236 | //
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| 237 | // Set structure alignment to 1-byte
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| 238 | //
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| 239 | #pragma pack (1)
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| 240 |
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| 241 | //
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| 242 | // Register set map as specified in PTP specification Chapter 5
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| 243 | //
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| 244 | typedef struct {
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| 245 | ///
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| 246 | /// Used to determine current state of Locality of the TPM.
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| 247 | ///
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| 248 | UINT32 LocalityState; // 0
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| 249 | UINT8 Reserved1[4]; // 4
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| 250 | ///
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| 251 | /// Used to gain control of the TPM by this Locality.
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| 252 | ///
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| 253 | UINT32 LocalityControl; // 8
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| 254 | ///
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| 255 | /// Used to determine whether Locality has been granted or Seized.
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| 256 | ///
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| 257 | UINT32 LocalityStatus; // 0ch
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| 258 | UINT8 Reserved2[0x20]; // 10h
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| 259 | ///
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| 260 | /// Used to identify the Interface types supported by the TPM.
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| 261 | ///
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| 262 | UINT32 InterfaceId; // 30h
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| 263 | ///
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| 264 | /// Vendor ID
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| 265 | ///
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| 266 | UINT16 Vid; // 34h
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| 267 | ///
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| 268 | /// Device ID
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| 269 | ///
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| 270 | UINT16 Did; // 36h
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| 271 | ///
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| 272 | /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
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| 273 | ///
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| 274 | UINT64 CrbControlExtension; // 38h
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| 275 | ///
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| 276 | /// Register used to initiate transactions for the CRB interface.
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| 277 | ///
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| 278 | UINT32 CrbControlRequest; // 40h
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| 279 | ///
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| 280 | /// Register used by the TPM to provide status of the CRB interface.
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| 281 | ///
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| 282 | UINT32 CrbControlStatus; // 44h
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| 283 | ///
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| 284 | /// Register used by software to cancel command processing.
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| 285 | ///
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| 286 | UINT32 CrbControlCancel; // 48h
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| 287 | ///
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| 288 | /// Register used to indicate presence of command or response data in the CRB buffer.
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| 289 | ///
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| 290 | UINT32 CrbControlStart; // 4Ch
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| 291 | ///
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| 292 | /// Register used to configure and respond to interrupts.
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| 293 | ///
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| 294 | UINT32 CrbInterruptEnable; // 50h
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| 295 | UINT32 CrbInterruptStatus; // 54h
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| 296 | ///
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| 297 | /// Size of the Command buffer.
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| 298 | ///
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| 299 | UINT32 CrbControlCommandSize; // 58h
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| 300 | ///
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| 301 | /// Command buffer start address
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| 302 | ///
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| 303 | UINT32 CrbControlCommandAddressLow; // 5Ch
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| 304 | UINT32 CrbControlCommandAddressHigh; // 60h
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| 305 | ///
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| 306 | /// Size of the Response buffer
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| 307 | ///
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| 308 | UINT32 CrbControlResponseSize; // 64h
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| 309 | ///
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| 310 | /// Address of the start of the Response buffer
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| 311 | ///
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| 312 | UINT64 CrbControlResponseAddrss; // 68h
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| 313 | UINT8 Reserved4[0x10]; // 70h
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| 314 | ///
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| 315 | /// Command/Response Data may be defined as large as 3968 (0xF80).
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| 316 | ///
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| 317 | UINT8 CrbDataBuffer[0xF80]; // 80h
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| 318 | } PTP_CRB_REGISTERS;
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| 319 |
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| 320 | //
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| 321 | // Define pointer types used to access CRB registers on PTP
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| 322 | //
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| 323 | typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;
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| 324 |
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| 325 | //
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| 326 | // Define bits of CRB Interface Identifier Register
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| 327 | //
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| 328 | typedef union {
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| 329 | struct {
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| 330 | UINT32 InterfaceType : 4;
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| 331 | UINT32 InterfaceVersion : 4;
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| 332 | UINT32 CapLocality : 1;
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| 333 | UINT32 CapCRBIdleBypass : 1;
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| 334 | UINT32 Reserved1 : 1;
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| 335 | UINT32 CapDataXferSizeSupport : 2;
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| 336 | UINT32 CapFIFO : 1;
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| 337 | UINT32 CapCRB : 1;
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| 338 | UINT32 CapIFRes : 2;
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| 339 | UINT32 InterfaceSelector : 2;
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| 340 | UINT32 IntfSelLock : 1;
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| 341 | UINT32 Reserved2 : 4;
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| 342 | UINT32 Rid : 8;
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| 343 | } Bits;
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| 344 | UINT32 Uint32;
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| 345 | } PTP_CRB_INTERFACE_IDENTIFIER;
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| 346 |
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| 347 | ///
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| 348 | /// InterfaceType
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| 349 | ///
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| 350 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0
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| 351 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1
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| 352 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF
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| 353 |
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| 354 | ///
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| 355 | /// InterfaceVersion
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| 356 | ///
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| 357 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0
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| 358 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1
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| 359 |
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| 360 | ///
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| 361 | /// InterfaceSelector
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| 362 | ///
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| 363 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0
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| 364 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1
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| 365 |
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| 366 | //
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| 367 | // Define bits of Locality State Register
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| 368 | //
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| 369 |
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| 370 | ///
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| 371 | /// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
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| 372 | ///
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| 373 | #define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
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| 374 |
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| 375 | ///
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| 376 | /// 000 - Locality 0
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| 377 | /// 001 - Locality 1
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| 378 | /// 010 - Locality 2
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| 379 | /// 011 - Locality 3
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| 380 | /// 100 - Locality 4
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| 381 | ///
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| 382 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
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| 383 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
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| 384 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
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| 385 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
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| 386 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
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| 387 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
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| 388 |
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| 389 | ///
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| 390 | /// A 0 indicates to the host that no locality is assigned.
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| 391 | /// A 1 indicates a locality has been assigned.
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| 392 | ///
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| 393 | #define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
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| 394 |
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| 395 | ///
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| 396 | /// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
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| 397 | /// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
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| 398 | ///
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| 399 | #define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
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| 400 |
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| 401 | //
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| 402 | // Define bits of Locality Control Register
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| 403 | //
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| 404 |
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| 405 | ///
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| 406 | /// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.
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| 407 | ///
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| 408 | #define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3
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| 409 |
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| 410 | ///
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| 411 | /// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
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| 412 | ///
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| 413 | #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
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| 414 |
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| 415 | ///
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| 416 | /// Writes (1): The active Locality is done with the TPM.
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| 417 | ///
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| 418 | #define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
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| 419 |
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| 420 | ///
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| 421 | /// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
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| 422 | ///
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| 423 | #define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
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| 424 |
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| 425 | //
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| 426 | // Define bits of Locality Status Register
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| 427 | //
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| 428 |
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| 429 | ///
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| 430 | /// 0: A higher locality has not initiated a Seize arbitration process.
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| 431 | /// 1: A higher locality has Seized the TPM from this locality.
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| 432 | ///
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| 433 | #define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
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| 434 |
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| 435 | ///
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| 436 | /// 0: Locality has not been granted to the TPM.
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| 437 | /// 1: Locality has been granted access to the TPM
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| 438 | ///
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| 439 | #define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
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| 440 |
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| 441 | //
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| 442 | // Define bits of CRB Control Area Request Register
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| 443 | //
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| 444 |
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| 445 | ///
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| 446 | /// Used by Software to indicate transition the TPM to and from the Idle state
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| 447 | /// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle
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| 448 | /// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
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| 449 | /// TPM SHALL complete this transition within TIMEOUT_C.
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| 450 | ///
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| 451 | #define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
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| 452 |
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| 453 | ///
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| 454 | /// Used by Software to request the TPM transition to the Ready State.
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| 455 | /// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.
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| 456 | /// 0: Cleared to 0 by TPM to acknowledge the request.
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| 457 | /// TPM SHALL complete this transition within TIMEOUT_C.
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| 458 | ///
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| 459 | #define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
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| 460 |
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| 461 | //
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| 462 | // Define bits of CRB Control Area Status Register
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| 463 | //
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| 464 |
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| 465 | ///
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| 466 | /// Used by TPM to indicate it is in the Idle State
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| 467 | /// 1: Set by TPM when in the Idle State
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| 468 | /// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
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| 469 | /// SHALL be cleared by TIMEOUT_C.
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| 470 | ///
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| 471 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
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| 472 |
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| 473 | ///
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| 474 | /// Used by the TPM to indicate current status.
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| 475 | /// 1: Set by TPM to indicate a FATAL Error
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| 476 | /// 0: Indicates TPM is operational
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| 477 | ///
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| 478 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
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| 479 |
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| 480 | //
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| 481 | // Define bits of CRB Control Cancel Register
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| 482 | //
|
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| 483 |
|
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| 484 | ///
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|---|
| 485 | /// Used by software to cancel command processing Reads return correct value
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|---|
| 486 | /// Writes (0000 0001h): Cancel a command
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| 487 | /// Writes (0000 0000h): Clears field when command has been cancelled
|
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| 488 | ///
|
|---|
| 489 | #define PTP_CRB_CONTROL_CANCEL BIT0
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| 490 |
|
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| 491 | //
|
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| 492 | // Define bits of CRB Control Start Register
|
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| 493 | //
|
|---|
| 494 |
|
|---|
| 495 | ///
|
|---|
| 496 | /// When set by software, indicates a command is ready for processing.
|
|---|
| 497 | /// Writes (0000 0001h): TPM transitions to Command Execution
|
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| 498 | /// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
|
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| 499 | ///
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|---|
| 500 | #define PTP_CRB_CONTROL_START BIT0
|
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| 501 |
|
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| 502 | //
|
|---|
| 503 | // Restore original structure alignment
|
|---|
| 504 | //
|
|---|
| 505 | #pragma pack ()
|
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| 506 |
|
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| 507 | //
|
|---|
| 508 | // Default TimeOut value
|
|---|
| 509 | //
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| 510 | #define PTP_TIMEOUT_A (750 * 1000) // 750ms
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| 511 | #define PTP_TIMEOUT_B (2000 * 1000) // 2s
|
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| 512 | #define PTP_TIMEOUT_C (200 * 1000) // 200ms
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|---|
| 513 | #define PTP_TIMEOUT_D (30 * 1000) // 30ms
|
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| 514 |
|
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| 515 | #endif
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