PciCf8Lib.h@ 58459

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1	/** @file
2	Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
3
4	This library is identical to the PCI Library, except the access method for performing PCI
5	configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
6	access to PCI Segment #0.
7
8	Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
9	This program and the accompanying materials
10	are licensed and made available under the terms and conditions of the BSD License
11	which accompanies this distribution. The full text of the license may be found at
12	http://opensource.org/licenses/bsd-license.php
13
14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17	**/
18
19	#ifndef __PCI_CF8_LIB_H__
20	#define __PCI_CF8_LIB_H__
21
22
23	/**
24	Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
25	address that can be passed to the PCI Library functions.
26
27	Computes an address that is compatible with the PCI Library functions. The
28	unused upper bits of Bus, Device, Function and Register are stripped prior to
29	the generation of the address.
30
31	@param Bus PCI Bus number. Range 0..255.
32	@param Device PCI Device number. Range 0..31.
33	@param Function PCI Function number. Range 0..7.
34	@param Register PCI Register number. Range 0..255.
35
36	@return The encode PCI address.
37
38	**/
39	#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
40	(((Offset) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))
41
42	/**
43	Registers a PCI device so PCI configuration registers may be accessed after
44	SetVirtualAddressMap().
45
46	Registers the PCI device specified by Address so all the PCI configuration registers
47	associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
48
49	If Address > 0x0FFFFFFF, then ASSERT().
50	If the register specified by Address >= 0x100, then ASSERT().
51
52	@param Address Address that encodes the PCI Bus, Device, Function and
53	Register.
54
55	@retval RETURN_SUCCESS The PCI device was registered for runtime access.
56	@retval RETURN_UNSUPPORTED An attempt was made to call this function
57	after ExitBootServices().
58	@retval RETURN_UNSUPPORTED The resources required to access the PCI device
59	at runtime could not be mapped.
60	@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
61	complete the registration.
62
63	**/
64	RETURN_STATUS
65	EFIAPI
66	PciCf8RegisterForRuntimeAccess (
67	IN UINTN Address
68	);
69
70	/**
71	Reads an 8-bit PCI configuration register.
72
73	Reads and returns the 8-bit PCI configuration register specified by Address.
74	This function must guarantee that all PCI read and write operations are
75	serialized.
76
77	If Address > 0x0FFFFFFF, then ASSERT().
78	If the register specified by Address >= 0x100, then ASSERT().
79
80	@param Address Address that encodes the PCI Bus, Device, Function and
81	Register.
82
83	@return The read value from the PCI configuration register.
84
85	**/
86	UINT8
87	EFIAPI
88	PciCf8Read8 (
89	IN UINTN Address
90	);
91
92	/**
93	Writes an 8-bit PCI configuration register.
94
95	Writes the 8-bit PCI configuration register specified by Address with the
96	value specified by Value. Value is returned. This function must guarantee
97	that all PCI read and write operations are serialized.
98
99	If Address > 0x0FFFFFFF, then ASSERT().
100	If the register specified by Address >= 0x100, then ASSERT().
101
102	@param Address Address that encodes the PCI Bus, Device, Function and
103	Register.
104	@param Value The value to write.
105
106	@return The value written to the PCI configuration register.
107
108	**/
109	UINT8
110	EFIAPI
111	PciCf8Write8 (
112	IN UINTN Address,
113	IN UINT8 Value
114	);
115
116	/**
117	Performs a bitwise OR of an 8-bit PCI configuration register with
118	an 8-bit value.
119
120	Reads the 8-bit PCI configuration register specified by Address, performs a
121	bitwise OR between the read result and the value specified by
122	OrData, and writes the result to the 8-bit PCI configuration register
123	specified by Address. The value written to the PCI configuration register is
124	returned. This function must guarantee that all PCI read and write operations
125	are serialized.
126
127	If Address > 0x0FFFFFFF, then ASSERT().
128	If the register specified by Address >= 0x100, then ASSERT().
129
130	@param Address Address that encodes the PCI Bus, Device, Function and
131	Register.
132	@param OrData The value to OR with the PCI configuration register.
133
134	@return The value written back to the PCI configuration register.
135
136	**/
137	UINT8
138	EFIAPI
139	PciCf8Or8 (
140	IN UINTN Address,
141	IN UINT8 OrData
142	);
143
144	/**
145	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
146	value.
147
148	Reads the 8-bit PCI configuration register specified by Address, performs a
149	bitwise AND between the read result and the value specified by AndData, and
150	writes the result to the 8-bit PCI configuration register specified by
151	Address. The value written to the PCI configuration register is returned.
152	This function must guarantee that all PCI read and write operations are
153	serialized.
154
155	If Address > 0x0FFFFFFF, then ASSERT().
156	If the register specified by Address >= 0x100, then ASSERT().
157
158	@param Address Address that encodes the PCI Bus, Device, Function and
159	Register.
160	@param AndData The value to AND with the PCI configuration register.
161
162	@return The value written back to the PCI configuration register.
163
164	**/
165	UINT8
166	EFIAPI
167	PciCf8And8 (
168	IN UINTN Address,
169	IN UINT8 AndData
170	);
171
172	/**
173	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
174	value, followed a bitwise OR with another 8-bit value.
175
176	Reads the 8-bit PCI configuration register specified by Address, performs a
177	bitwise AND between the read result and the value specified by AndData,
178	performs a bitwise OR between the result of the AND operation and
179	the value specified by OrData, and writes the result to the 8-bit PCI
180	configuration register specified by Address. The value written to the PCI
181	configuration register is returned. This function must guarantee that all PCI
182	read and write operations are serialized.
183
184	If Address > 0x0FFFFFFF, then ASSERT().
185	If the register specified by Address >= 0x100, then ASSERT().
186
187	@param Address Address that encodes the PCI Bus, Device, Function and
188	Register.
189	@param AndData The value to AND with the PCI configuration register.
190	@param OrData The value to OR with the result of the AND operation.
191
192	@return The value written back to the PCI configuration register.
193
194	**/
195	UINT8
196	EFIAPI
197	PciCf8AndThenOr8 (
198	IN UINTN Address,
199	IN UINT8 AndData,
200	IN UINT8 OrData
201	);
202
203	/**
204	Reads a bit field of a PCI configuration register.
205
206	Reads the bit field in an 8-bit PCI configuration register. The bit field is
207	specified by the StartBit and the EndBit. The value of the bit field is
208	returned.
209
210	If Address > 0x0FFFFFFF, then ASSERT().
211	If the register specified by Address >= 0x100, then ASSERT().
212	If StartBit is greater than 7, then ASSERT().
213	If EndBit is greater than 7, then ASSERT().
214	If EndBit is less than StartBit, then ASSERT().
215
216	@param Address PCI configuration register to read.
217	@param StartBit The ordinal of the least significant bit in the bit field.
218	Range 0..7.
219	@param EndBit The ordinal of the most significant bit in the bit field.
220	Range 0..7.
221
222	@return The value of the bit field read from the PCI configuration register.
223
224	**/
225	UINT8
226	EFIAPI
227	PciCf8BitFieldRead8 (
228	IN UINTN Address,
229	IN UINTN StartBit,
230	IN UINTN EndBit
231	);
232
233	/**
234	Writes a bit field to a PCI configuration register.
235
236	Writes Value to the bit field of the PCI configuration register. The bit
237	field is specified by the StartBit and the EndBit. All other bits in the
238	destination PCI configuration register are preserved. The new value of the
239	8-bit register is returned.
240
241	If Address > 0x0FFFFFFF, then ASSERT().
242	If the register specified by Address >= 0x100, then ASSERT().
243	If StartBit is greater than 7, then ASSERT().
244	If EndBit is greater than 7, then ASSERT().
245	If EndBit is less than StartBit, then ASSERT().
246	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
247
248	@param Address PCI configuration register to write.
249	@param StartBit The ordinal of the least significant bit in the bit field.
250	Range 0..7.
251	@param EndBit The ordinal of the most significant bit in the bit field.
252	Range 0..7.
253	@param Value New value of the bit field.
254
255	@return The value written back to the PCI configuration register.
256
257	**/
258	UINT8
259	EFIAPI
260	PciCf8BitFieldWrite8 (
261	IN UINTN Address,
262	IN UINTN StartBit,
263	IN UINTN EndBit,
264	IN UINT8 Value
265	);
266
267	/**
268	Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
269	writes the result back to the bit field in the 8-bit port.
270
271	Reads the 8-bit PCI configuration register specified by Address, performs a
272	bitwise OR between the read result and the value specified by
273	OrData, and writes the result to the 8-bit PCI configuration register
274	specified by Address. The value written to the PCI configuration register is
275	returned. This function must guarantee that all PCI read and write operations
276	are serialized. Extra left bits in OrData are stripped.
277
278	If Address > 0x0FFFFFFF, then ASSERT().
279	If the register specified by Address >= 0x100, then ASSERT().
280	If StartBit is greater than 7, then ASSERT().
281	If EndBit is greater than 7, then ASSERT().
282	If EndBit is less than StartBit, then ASSERT().
283	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
284
285	@param Address PCI configuration register to write.
286	@param StartBit The ordinal of the least significant bit in the bit field.
287	Range 0..7.
288	@param EndBit The ordinal of the most significant bit in the bit field.
289	Range 0..7.
290	@param OrData The value to OR with the PCI configuration register.
291
292	@return The value written back to the PCI configuration register.
293
294	**/
295	UINT8
296	EFIAPI
297	PciCf8BitFieldOr8 (
298	IN UINTN Address,
299	IN UINTN StartBit,
300	IN UINTN EndBit,
301	IN UINT8 OrData
302	);
303
304	/**
305	Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
306	AND, and writes the result back to the bit field in the 8-bit register.
307
308	Reads the 8-bit PCI configuration register specified by Address, performs a
309	bitwise AND between the read result and the value specified by AndData, and
310	writes the result to the 8-bit PCI configuration register specified by
311	Address. The value written to the PCI configuration register is returned.
312	This function must guarantee that all PCI read and write operations are
313	serialized. Extra left bits in AndData are stripped.
314
315	If Address > 0x0FFFFFFF, then ASSERT().
316	If the register specified by Address >= 0x100, then ASSERT().
317	If StartBit is greater than 7, then ASSERT().
318	If EndBit is greater than 7, then ASSERT().
319	If EndBit is less than StartBit, then ASSERT().
320	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
321
322	@param Address PCI configuration register to write.
323	@param StartBit The ordinal of the least significant bit in the bit field.
324	Range 0..7.
325	@param EndBit The ordinal of the most significant bit in the bit field.
326	Range 0..7.
327	@param AndData The value to AND with the PCI configuration register.
328
329	@return The value written back to the PCI configuration register.
330
331	**/
332	UINT8
333	EFIAPI
334	PciCf8BitFieldAnd8 (
335	IN UINTN Address,
336	IN UINTN StartBit,
337	IN UINTN EndBit,
338	IN UINT8 AndData
339	);
340
341	/**
342	Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
343	bitwise OR, and writes the result back to the bit field in the
344	8-bit port.
345
346	Reads the 8-bit PCI configuration register specified by Address, performs a
347	bitwise AND followed by a bitwise OR between the read result and
348	the value specified by AndData, and writes the result to the 8-bit PCI
349	configuration register specified by Address. The value written to the PCI
350	configuration register is returned. This function must guarantee that all PCI
351	read and write operations are serialized. Extra left bits in both AndData and
352	OrData are stripped.
353
354	If Address > 0x0FFFFFFF, then ASSERT().
355	If the register specified by Address >= 0x100, then ASSERT().
356	If StartBit is greater than 7, then ASSERT().
357	If EndBit is greater than 7, then ASSERT().
358	If EndBit is less than StartBit, then ASSERT().
359	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
360	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
361
362	@param Address PCI configuration register to write.
363	@param StartBit The ordinal of the least significant bit in the bit field.
364	Range 0..7.
365	@param EndBit The ordinal of the most significant bit in the bit field.
366	Range 0..7.
367	@param AndData The value to AND with the PCI configuration register.
368	@param OrData The value to OR with the result of the AND operation.
369
370	@return The value written back to the PCI configuration register.
371
372	**/
373	UINT8
374	EFIAPI
375	PciCf8BitFieldAndThenOr8 (
376	IN UINTN Address,
377	IN UINTN StartBit,
378	IN UINTN EndBit,
379	IN UINT8 AndData,
380	IN UINT8 OrData
381	);
382
383	/**
384	Reads a 16-bit PCI configuration register.
385
386	Reads and returns the 16-bit PCI configuration register specified by Address.
387	This function must guarantee that all PCI read and write operations are
388	serialized.
389
390	If Address > 0x0FFFFFFF, then ASSERT().
391	If Address is not aligned on a 16-bit boundary, then ASSERT().
392	If the register specified by Address >= 0x100, then ASSERT().
393
394	@param Address Address that encodes the PCI Bus, Device, Function and
395	Register.
396
397	@return The read value from the PCI configuration register.
398
399	**/
400	UINT16
401	EFIAPI
402	PciCf8Read16 (
403	IN UINTN Address
404	);
405
406	/**
407	Writes a 16-bit PCI configuration register.
408
409	Writes the 16-bit PCI configuration register specified by Address with the
410	value specified by Value. Value is returned. This function must guarantee
411	that all PCI read and write operations are serialized.
412
413	If Address > 0x0FFFFFFF, then ASSERT().
414	If Address is not aligned on a 16-bit boundary, then ASSERT().
415	If the register specified by Address >= 0x100, then ASSERT().
416
417	@param Address Address that encodes the PCI Bus, Device, Function and
418	Register.
419	@param Value The value to write.
420
421	@return The value written to the PCI configuration register.
422
423	**/
424	UINT16
425	EFIAPI
426	PciCf8Write16 (
427	IN UINTN Address,
428	IN UINT16 Value
429	);
430
431	/**
432	Performs a bitwise OR of a 16-bit PCI configuration register with
433	a 16-bit value.
434
435	Reads the 16-bit PCI configuration register specified by Address, performs a
436	bitwise OR between the read result and the value specified by
437	OrData, and writes the result to the 16-bit PCI configuration register
438	specified by Address. The value written to the PCI configuration register is
439	returned. This function must guarantee that all PCI read and write operations
440	are serialized.
441
442	If Address > 0x0FFFFFFF, then ASSERT().
443	If Address is not aligned on a 16-bit boundary, then ASSERT().
444	If the register specified by Address >= 0x100, then ASSERT().
445
446	@param Address Address that encodes the PCI Bus, Device, Function and
447	Register.
448	@param OrData The value to OR with the PCI configuration register.
449
450	@return The value written back to the PCI configuration register.
451
452	**/
453	UINT16
454	EFIAPI
455	PciCf8Or16 (
456	IN UINTN Address,
457	IN UINT16 OrData
458	);
459
460	/**
461	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
462	value.
463
464	Reads the 16-bit PCI configuration register specified by Address, performs a
465	bitwise AND between the read result and the value specified by AndData, and
466	writes the result to the 16-bit PCI configuration register specified by
467	Address. The value written to the PCI configuration register is returned.
468	This function must guarantee that all PCI read and write operations are
469	serialized.
470
471	If Address > 0x0FFFFFFF, then ASSERT().
472	If Address is not aligned on a 16-bit boundary, then ASSERT().
473	If the register specified by Address >= 0x100, then ASSERT().
474
475	@param Address Address that encodes the PCI Bus, Device, Function and
476	Register.
477	@param AndData The value to AND with the PCI configuration register.
478
479	@return The value written back to the PCI configuration register.
480
481	**/
482	UINT16
483	EFIAPI
484	PciCf8And16 (
485	IN UINTN Address,
486	IN UINT16 AndData
487	);
488
489	/**
490	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
491	value, followed a bitwise OR with another 16-bit value.
492
493	Reads the 16-bit PCI configuration register specified by Address, performs a
494	bitwise AND between the read result and the value specified by AndData,
495	performs a bitwise OR between the result of the AND operation and
496	the value specified by OrData, and writes the result to the 16-bit PCI
497	configuration register specified by Address. The value written to the PCI
498	configuration register is returned. This function must guarantee that all PCI
499	read and write operations are serialized.
500
501	If Address > 0x0FFFFFFF, then ASSERT().
502	If Address is not aligned on a 16-bit boundary, then ASSERT().
503	If the register specified by Address >= 0x100, then ASSERT().
504
505	@param Address Address that encodes the PCI Bus, Device, Function and
506	Register.
507	@param AndData The value to AND with the PCI configuration register.
508	@param OrData The value to OR with the result of the AND operation.
509
510	@return The value written back to the PCI configuration register.
511
512	**/
513	UINT16
514	EFIAPI
515	PciCf8AndThenOr16 (
516	IN UINTN Address,
517	IN UINT16 AndData,
518	IN UINT16 OrData
519	);
520
521	/**
522	Reads a bit field of a PCI configuration register.
523
524	Reads the bit field in a 16-bit PCI configuration register. The bit field is
525	specified by the StartBit and the EndBit. The value of the bit field is
526	returned.
527
528	If Address > 0x0FFFFFFF, then ASSERT().
529	If Address is not aligned on a 16-bit boundary, then ASSERT().
530	If the register specified by Address >= 0x100, then ASSERT().
531	If StartBit is greater than 15, then ASSERT().
532	If EndBit is greater than 15, then ASSERT().
533	If EndBit is less than StartBit, then ASSERT().
534
535	@param Address PCI configuration register to read.
536	@param StartBit The ordinal of the least significant bit in the bit field.
537	Range 0..15.
538	@param EndBit The ordinal of the most significant bit in the bit field.
539	Range 0..15.
540
541	@return The value of the bit field read from the PCI configuration register.
542
543	**/
544	UINT16
545	EFIAPI
546	PciCf8BitFieldRead16 (
547	IN UINTN Address,
548	IN UINTN StartBit,
549	IN UINTN EndBit
550	);
551
552	/**
553	Writes a bit field to a PCI configuration register.
554
555	Writes Value to the bit field of the PCI configuration register. The bit
556	field is specified by the StartBit and the EndBit. All other bits in the
557	destination PCI configuration register are preserved. The new value of the
558	16-bit register is returned.
559
560	If Address > 0x0FFFFFFF, then ASSERT().
561	If Address is not aligned on a 16-bit boundary, then ASSERT().
562	If the register specified by Address >= 0x100, then ASSERT().
563	If StartBit is greater than 15, then ASSERT().
564	If EndBit is greater than 15, then ASSERT().
565	If EndBit is less than StartBit, then ASSERT().
566	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
567
568	@param Address PCI configuration register to write.
569	@param StartBit The ordinal of the least significant bit in the bit field.
570	Range 0..15.
571	@param EndBit The ordinal of the most significant bit in the bit field.
572	Range 0..15.
573	@param Value New value of the bit field.
574
575	@return The value written back to the PCI configuration register.
576
577	**/
578	UINT16
579	EFIAPI
580	PciCf8BitFieldWrite16 (
581	IN UINTN Address,
582	IN UINTN StartBit,
583	IN UINTN EndBit,
584	IN UINT16 Value
585	);
586
587	/**
588	Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
589	writes the result back to the bit field in the 16-bit port.
590
591	Reads the 16-bit PCI configuration register specified by Address, performs a
592	bitwise OR between the read result and the value specified by
593	OrData, and writes the result to the 16-bit PCI configuration register
594	specified by Address. The value written to the PCI configuration register is
595	returned. This function must guarantee that all PCI read and write operations
596	are serialized. Extra left bits in OrData are stripped.
597
598	If Address > 0x0FFFFFFF, then ASSERT().
599	If Address is not aligned on a 16-bit boundary, then ASSERT().
600	If the register specified by Address >= 0x100, then ASSERT().
601	If StartBit is greater than 15, then ASSERT().
602	If EndBit is greater than 15, then ASSERT().
603	If EndBit is less than StartBit, then ASSERT().
604	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
605
606	@param Address PCI configuration register to write.
607	@param StartBit The ordinal of the least significant bit in the bit field.
608	Range 0..15.
609	@param EndBit The ordinal of the most significant bit in the bit field.
610	Range 0..15.
611	@param OrData The value to OR with the PCI configuration register.
612
613	@return The value written back to the PCI configuration register.
614
615	**/
616	UINT16
617	EFIAPI
618	PciCf8BitFieldOr16 (
619	IN UINTN Address,
620	IN UINTN StartBit,
621	IN UINTN EndBit,
622	IN UINT16 OrData
623	);
624
625	/**
626	Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
627	AND, and writes the result back to the bit field in the 16-bit register.
628
629	Reads the 16-bit PCI configuration register specified by Address, performs a
630	bitwise AND between the read result and the value specified by AndData, and
631	writes the result to the 16-bit PCI configuration register specified by
632	Address. The value written to the PCI configuration register is returned.
633	This function must guarantee that all PCI read and write operations are
634	serialized. Extra left bits in AndData are stripped.
635
636	If Address > 0x0FFFFFFF, then ASSERT().
637	If Address is not aligned on a 16-bit boundary, then ASSERT().
638	If the register specified by Address >= 0x100, then ASSERT().
639	If StartBit is greater than 15, then ASSERT().
640	If EndBit is greater than 15, then ASSERT().
641	If EndBit is less than StartBit, then ASSERT().
642	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
643
644	@param Address PCI configuration register to write.
645	@param StartBit The ordinal of the least significant bit in the bit field.
646	Range 0..15.
647	@param EndBit The ordinal of the most significant bit in the bit field.
648	Range 0..15.
649	@param AndData The value to AND with the PCI configuration register.
650
651	@return The value written back to the PCI configuration register.
652
653	**/
654	UINT16
655	EFIAPI
656	PciCf8BitFieldAnd16 (
657	IN UINTN Address,
658	IN UINTN StartBit,
659	IN UINTN EndBit,
660	IN UINT16 AndData
661	);
662
663	/**
664	Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
665	bitwise OR, and writes the result back to the bit field in the
666	16-bit port.
667
668	Reads the 16-bit PCI configuration register specified by Address, performs a
669	bitwise AND followed by a bitwise OR between the read result and
670	the value specified by AndData, and writes the result to the 16-bit PCI
671	configuration register specified by Address. The value written to the PCI
672	configuration register is returned. This function must guarantee that all PCI
673	read and write operations are serialized. Extra left bits in both AndData and
674	OrData are stripped.
675
676	If Address > 0x0FFFFFFF, then ASSERT().
677	If Address is not aligned on a 16-bit boundary, then ASSERT().
678	If the register specified by Address >= 0x100, then ASSERT().
679	If StartBit is greater than 15, then ASSERT().
680	If EndBit is greater than 15, then ASSERT().
681	If EndBit is less than StartBit, then ASSERT().
682	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
683	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
684
685	@param Address PCI configuration register to write.
686	@param StartBit The ordinal of the least significant bit in the bit field.
687	Range 0..15.
688	@param EndBit The ordinal of the most significant bit in the bit field.
689	Range 0..15.
690	@param AndData The value to AND with the PCI configuration register.
691	@param OrData The value to OR with the result of the AND operation.
692
693	@return The value written back to the PCI configuration register.
694
695	**/
696	UINT16
697	EFIAPI
698	PciCf8BitFieldAndThenOr16 (
699	IN UINTN Address,
700	IN UINTN StartBit,
701	IN UINTN EndBit,
702	IN UINT16 AndData,
703	IN UINT16 OrData
704	);
705
706	/**
707	Reads a 32-bit PCI configuration register.
708
709	Reads and returns the 32-bit PCI configuration register specified by Address.
710	This function must guarantee that all PCI read and write operations are
711	serialized.
712
713	If Address > 0x0FFFFFFF, then ASSERT().
714	If Address is not aligned on a 32-bit boundary, then ASSERT().
715	If the register specified by Address >= 0x100, then ASSERT().
716
717	@param Address Address that encodes the PCI Bus, Device, Function and
718	Register.
719
720	@return The read value from the PCI configuration register.
721
722	**/
723	UINT32
724	EFIAPI
725	PciCf8Read32 (
726	IN UINTN Address
727	);
728
729	/**
730	Writes a 32-bit PCI configuration register.
731
732	Writes the 32-bit PCI configuration register specified by Address with the
733	value specified by Value. Value is returned. This function must guarantee
734	that all PCI read and write operations are serialized.
735
736	If Address > 0x0FFFFFFF, then ASSERT().
737	If Address is not aligned on a 32-bit boundary, then ASSERT().
738	If the register specified by Address >= 0x100, then ASSERT().
739
740	@param Address Address that encodes the PCI Bus, Device, Function and
741	Register.
742	@param Value The value to write.
743
744	@return The value written to the PCI configuration register.
745
746	**/
747	UINT32
748	EFIAPI
749	PciCf8Write32 (
750	IN UINTN Address,
751	IN UINT32 Value
752	);
753
754	/**
755	Performs a bitwise OR of a 32-bit PCI configuration register with
756	a 32-bit value.
757
758	Reads the 32-bit PCI configuration register specified by Address, performs a
759	bitwise OR between the read result and the value specified by
760	OrData, and writes the result to the 32-bit PCI configuration register
761	specified by Address. The value written to the PCI configuration register is
762	returned. This function must guarantee that all PCI read and write operations
763	are serialized.
764
765	If Address > 0x0FFFFFFF, then ASSERT().
766	If Address is not aligned on a 32-bit boundary, then ASSERT().
767	If the register specified by Address >= 0x100, then ASSERT().
768
769	@param Address Address that encodes the PCI Bus, Device, Function and
770	Register.
771	@param OrData The value to OR with the PCI configuration register.
772
773	@return The value written back to the PCI configuration register.
774
775	**/
776	UINT32
777	EFIAPI
778	PciCf8Or32 (
779	IN UINTN Address,
780	IN UINT32 OrData
781	);
782
783	/**
784	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
785	value.
786
787	Reads the 32-bit PCI configuration register specified by Address, performs a
788	bitwise AND between the read result and the value specified by AndData, and
789	writes the result to the 32-bit PCI configuration register specified by
790	Address. The value written to the PCI configuration register is returned.
791	This function must guarantee that all PCI read and write operations are
792	serialized.
793
794	If Address > 0x0FFFFFFF, then ASSERT().
795	If Address is not aligned on a 32-bit boundary, then ASSERT().
796	If the register specified by Address >= 0x100, then ASSERT().
797
798	@param Address Address that encodes the PCI Bus, Device, Function and
799	Register.
800	@param AndData The value to AND with the PCI configuration register.
801
802	@return The value written back to the PCI configuration register.
803
804	**/
805	UINT32
806	EFIAPI
807	PciCf8And32 (
808	IN UINTN Address,
809	IN UINT32 AndData
810	);
811
812	/**
813	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
814	value, followed a bitwise OR with another 32-bit value.
815
816	Reads the 32-bit PCI configuration register specified by Address, performs a
817	bitwise AND between the read result and the value specified by AndData,
818	performs a bitwise OR between the result of the AND operation and
819	the value specified by OrData, and writes the result to the 32-bit PCI
820	configuration register specified by Address. The value written to the PCI
821	configuration register is returned. This function must guarantee that all PCI
822	read and write operations are serialized.
823
824	If Address > 0x0FFFFFFF, then ASSERT().
825	If Address is not aligned on a 32-bit boundary, then ASSERT().
826	If the register specified by Address >= 0x100, then ASSERT().
827
828	@param Address Address that encodes the PCI Bus, Device, Function and
829	Register.
830	@param AndData The value to AND with the PCI configuration register.
831	@param OrData The value to OR with the result of the AND operation.
832
833	@return The value written back to the PCI configuration register.
834
835	**/
836	UINT32
837	EFIAPI
838	PciCf8AndThenOr32 (
839	IN UINTN Address,
840	IN UINT32 AndData,
841	IN UINT32 OrData
842	);
843
844	/**
845	Reads a bit field of a PCI configuration register.
846
847	Reads the bit field in a 32-bit PCI configuration register. The bit field is
848	specified by the StartBit and the EndBit. The value of the bit field is
849	returned.
850
851	If Address > 0x0FFFFFFF, then ASSERT().
852	If Address is not aligned on a 32-bit boundary, then ASSERT().
853	If the register specified by Address >= 0x100, then ASSERT().
854	If StartBit is greater than 31, then ASSERT().
855	If EndBit is greater than 31, then ASSERT().
856	If EndBit is less than StartBit, then ASSERT().
857
858	@param Address PCI configuration register to read.
859	@param StartBit The ordinal of the least significant bit in the bit field.
860	Range 0..31.
861	@param EndBit The ordinal of the most significant bit in the bit field.
862	Range 0..31.
863
864	@return The value of the bit field read from the PCI configuration register.
865
866	**/
867	UINT32
868	EFIAPI
869	PciCf8BitFieldRead32 (
870	IN UINTN Address,
871	IN UINTN StartBit,
872	IN UINTN EndBit
873	);
874
875	/**
876	Writes a bit field to a PCI configuration register.
877
878	Writes Value to the bit field of the PCI configuration register. The bit
879	field is specified by the StartBit and the EndBit. All other bits in the
880	destination PCI configuration register are preserved. The new value of the
881	32-bit register is returned.
882
883	If Address > 0x0FFFFFFF, then ASSERT().
884	If Address is not aligned on a 32-bit boundary, then ASSERT().
885	If the register specified by Address >= 0x100, then ASSERT().
886	If StartBit is greater than 31, then ASSERT().
887	If EndBit is greater than 31, then ASSERT().
888	If EndBit is less than StartBit, then ASSERT().
889	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
890
891	@param Address PCI configuration register to write.
892	@param StartBit The ordinal of the least significant bit in the bit field.
893	Range 0..31.
894	@param EndBit The ordinal of the most significant bit in the bit field.
895	Range 0..31.
896	@param Value New value of the bit field.
897
898	@return The value written back to the PCI configuration register.
899
900	**/
901	UINT32
902	EFIAPI
903	PciCf8BitFieldWrite32 (
904	IN UINTN Address,
905	IN UINTN StartBit,
906	IN UINTN EndBit,
907	IN UINT32 Value
908	);
909
910	/**
911	Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
912	writes the result back to the bit field in the 32-bit port.
913
914	Reads the 32-bit PCI configuration register specified by Address, performs a
915	bitwise OR between the read result and the value specified by
916	OrData, and writes the result to the 32-bit PCI configuration register
917	specified by Address. The value written to the PCI configuration register is
918	returned. This function must guarantee that all PCI read and write operations
919	are serialized. Extra left bits in OrData are stripped.
920
921	If Address > 0x0FFFFFFF, then ASSERT().
922	If Address is not aligned on a 32-bit boundary, then ASSERT().
923	If the register specified by Address >= 0x100, then ASSERT().
924	If StartBit is greater than 31, then ASSERT().
925	If EndBit is greater than 31, then ASSERT().
926	If EndBit is less than StartBit, then ASSERT().
927	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
928
929	@param Address PCI configuration register to write.
930	@param StartBit The ordinal of the least significant bit in the bit field.
931	Range 0..31.
932	@param EndBit The ordinal of the most significant bit in the bit field.
933	Range 0..31.
934	@param OrData The value to OR with the PCI configuration register.
935
936	@return The value written back to the PCI configuration register.
937
938	**/
939	UINT32
940	EFIAPI
941	PciCf8BitFieldOr32 (
942	IN UINTN Address,
943	IN UINTN StartBit,
944	IN UINTN EndBit,
945	IN UINT32 OrData
946	);
947
948	/**
949	Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
950	AND, and writes the result back to the bit field in the 32-bit register.
951
952	Reads the 32-bit PCI configuration register specified by Address, performs a
953	bitwise AND between the read result and the value specified by AndData, and
954	writes the result to the 32-bit PCI configuration register specified by
955	Address. The value written to the PCI configuration register is returned.
956	This function must guarantee that all PCI read and write operations are
957	serialized. Extra left bits in AndData are stripped.
958
959	If Address > 0x0FFFFFFF, then ASSERT().
960	If Address is not aligned on a 32-bit boundary, then ASSERT().
961	If the register specified by Address >= 0x100, then ASSERT().
962	If StartBit is greater than 31, then ASSERT().
963	If EndBit is greater than 31, then ASSERT().
964	If EndBit is less than StartBit, then ASSERT().
965	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
966
967	@param Address PCI configuration register to write.
968	@param StartBit The ordinal of the least significant bit in the bit field.
969	Range 0..31.
970	@param EndBit The ordinal of the most significant bit in the bit field.
971	Range 0..31.
972	@param AndData The value to AND with the PCI configuration register.
973
974	@return The value written back to the PCI configuration register.
975
976	**/
977	UINT32
978	EFIAPI
979	PciCf8BitFieldAnd32 (
980	IN UINTN Address,
981	IN UINTN StartBit,
982	IN UINTN EndBit,
983	IN UINT32 AndData
984	);
985
986	/**
987	Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
988	bitwise OR, and writes the result back to the bit field in the
989	32-bit port.
990
991	Reads the 32-bit PCI configuration register specified by Address, performs a
992	bitwise AND followed by a bitwise OR between the read result and
993	the value specified by AndData, and writes the result to the 32-bit PCI
994	configuration register specified by Address. The value written to the PCI
995	configuration register is returned. This function must guarantee that all PCI
996	read and write operations are serialized. Extra left bits in both AndData and
997	OrData are stripped.
998
999	If Address > 0x0FFFFFFF, then ASSERT().
1000	If Address is not aligned on a 32-bit boundary, then ASSERT().
1001	If the register specified by Address >= 0x100, then ASSERT().
1002	If StartBit is greater than 31, then ASSERT().
1003	If EndBit is greater than 31, then ASSERT().
1004	If EndBit is less than StartBit, then ASSERT().
1005	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1006	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1007
1008	@param Address PCI configuration register to write.
1009	@param StartBit The ordinal of the least significant bit in the bit field.
1010	Range 0..31.
1011	@param EndBit The ordinal of the most significant bit in the bit field.
1012	Range 0..31.
1013	@param AndData The value to AND with the PCI configuration register.
1014	@param OrData The value to OR with the result of the AND operation.
1015
1016	@return The value written back to the PCI configuration register.
1017
1018	**/
1019	UINT32
1020	EFIAPI
1021	PciCf8BitFieldAndThenOr32 (
1022	IN UINTN Address,
1023	IN UINTN StartBit,
1024	IN UINTN EndBit,
1025	IN UINT32 AndData,
1026	IN UINT32 OrData
1027	);
1028
1029	/**
1030	Reads a range of PCI configuration registers into a caller supplied buffer.
1031
1032	Reads the range of PCI configuration registers specified by StartAddress and
1033	Size into the buffer specified by Buffer. This function only allows the PCI
1034	configuration registers from a single PCI function to be read. Size is
1035	returned. When possible 32-bit PCI configuration read cycles are used to read
1036	from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1037	and 16-bit PCI configuration read cycles may be used at the beginning and the
1038	end of the range.
1039
1040	If StartAddress > 0x0FFFFFFF, then ASSERT().
1041	If the register specified by StartAddress >= 0x100, then ASSERT().
1042	If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1043	If Size > 0 and Buffer is NULL, then ASSERT().
1044
1045	@param StartAddress Starting address that encodes the PCI Bus, Device,
1046	Function and Register.
1047	@param Size Size in bytes of the transfer.
1048	@param Buffer Pointer to a buffer receiving the data read.
1049
1050	@return Size read from StartAddress.
1051
1052	**/
1053	UINTN
1054	EFIAPI
1055	PciCf8ReadBuffer (
1056	IN UINTN StartAddress,
1057	IN UINTN Size,
1058	OUT VOID *Buffer
1059	);
1060
1061	/**
1062	Copies the data in a caller supplied buffer to a specified range of PCI
1063	configuration space.
1064
1065	Writes the range of PCI configuration registers specified by StartAddress and
1066	Size from the buffer specified by Buffer. This function only allows the PCI
1067	configuration registers from a single PCI function to be written. Size is
1068	returned. When possible 32-bit PCI configuration write cycles are used to
1069	write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1070	8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1071	and the end of the range.
1072
1073	If StartAddress > 0x0FFFFFFF, then ASSERT().
1074	If the register specified by StartAddress >= 0x100, then ASSERT().
1075	If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1076	If Size > 0 and Buffer is NULL, then ASSERT().
1077
1078	@param StartAddress Starting address that encodes the PCI Bus, Device,
1079	Function and Register.
1080	@param Size Size in bytes of the transfer.
1081	@param Buffer Pointer to a buffer containing the data to write.
1082
1083	@return Size written to StartAddress.
1084
1085	**/
1086	UINTN
1087	EFIAPI
1088	PciCf8WriteBuffer (
1089	IN UINTN StartAddress,
1090	IN UINTN Size,
1091	IN VOID *Buffer
1092	);
1093
1094	#endif

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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Library/PciCf8Lib.h@ 58459

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