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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c@ 101297

Last change on this file since 101297 was 101291, checked in by vboxsync, 17 months ago

EFI/FirmwareNew: Make edk2-stable202308 build on all supported platforms (using gcc at least, msvc not tested yet), bugref:4643

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1/** @file
2 RISC-V specific functionality for cache.
3
4 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7**/
8
9#include <Base.h>
10#include <Library/BaseLib.h>
11#include <Library/DebugLib.h>
12
13/**
14 RISC-V invalidate instruction cache.
15
16**/
17VOID
18EFIAPI
19RiscVInvalidateInstCacheAsm (
20 VOID
21 );
22
23/**
24 RISC-V invalidate data cache.
25
26**/
27VOID
28EFIAPI
29RiscVInvalidateDataCacheAsm (
30 VOID
31 );
32
33/**
34 Invalidates the entire instruction cache in cache coherency domain of the
35 calling CPU.
36
37**/
38VOID
39EFIAPI
40InvalidateInstructionCache (
41 VOID
42 )
43{
44 RiscVInvalidateInstCacheAsm ();
45}
46
47/**
48 Invalidates a range of instruction cache lines in the cache coherency domain
49 of the calling CPU.
50
51 Invalidates the instruction cache lines specified by Address and Length. If
52 Address is not aligned on a cache line boundary, then entire instruction
53 cache line containing Address is invalidated. If Address + Length is not
54 aligned on a cache line boundary, then the entire instruction cache line
55 containing Address + Length -1 is invalidated. This function may choose to
56 invalidate the entire instruction cache if that is more efficient than
57 invalidating the specified range. If Length is 0, then no instruction cache
58 lines are invalidated. Address is returned.
59
60 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
61
62 @param Address The base address of the instruction cache lines to
63 invalidate. If the CPU is in a physical addressing mode, then
64 Address is a physical address. If the CPU is in a virtual
65 addressing mode, then Address is a virtual address.
66
67 @param Length The number of bytes to invalidate from the instruction cache.
68
69 @return Address.
70
71**/
72VOID *
73EFIAPI
74InvalidateInstructionCacheRange (
75 IN VOID *Address,
76 IN UINTN Length
77 )
78{
79 DEBUG (
80 (DEBUG_WARN,
81 "%a:RISC-V unsupported function.\n"
82 "Invalidating the whole instruction cache instead.\n", __func__)
83 );
84 InvalidateInstructionCache ();
85 return Address;
86}
87
88/**
89 Writes back and invalidates the entire data cache in cache coherency domain
90 of the calling CPU.
91
92 Writes back and invalidates the entire data cache in cache coherency domain
93 of the calling CPU. This function guarantees that all dirty cache lines are
94 written back to system memory, and also invalidates all the data cache lines
95 in the cache coherency domain of the calling CPU.
96
97**/
98VOID
99EFIAPI
100WriteBackInvalidateDataCache (
101 VOID
102 )
103{
104 DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
105}
106
107/**
108 Writes back and invalidates a range of data cache lines in the cache
109 coherency domain of the calling CPU.
110
111 Writes back and invalidates the data cache lines specified by Address and
112 Length. If Address is not aligned on a cache line boundary, then entire data
113 cache line containing Address is written back and invalidated. If Address +
114 Length is not aligned on a cache line boundary, then the entire data cache
115 line containing Address + Length -1 is written back and invalidated. This
116 function may choose to write back and invalidate the entire data cache if
117 that is more efficient than writing back and invalidating the specified
118 range. If Length is 0, then no data cache lines are written back and
119 invalidated. Address is returned.
120
121 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
122
123 @param Address The base address of the data cache lines to write back and
124 invalidate. If the CPU is in a physical addressing mode, then
125 Address is a physical address. If the CPU is in a virtual
126 addressing mode, then Address is a virtual address.
127 @param Length The number of bytes to write back and invalidate from the
128 data cache.
129
130 @return Address of cache invalidation.
131
132**/
133VOID *
134EFIAPI
135WriteBackInvalidateDataCacheRange (
136 IN VOID *Address,
137 IN UINTN Length
138 )
139{
140 DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
141 return Address;
142}
143
144/**
145 Writes back the entire data cache in cache coherency domain of the calling
146 CPU.
147
148 Writes back the entire data cache in cache coherency domain of the calling
149 CPU. This function guarantees that all dirty cache lines are written back to
150 system memory. This function may also invalidate all the data cache lines in
151 the cache coherency domain of the calling CPU.
152
153**/
154VOID
155EFIAPI
156WriteBackDataCache (
157 VOID
158 )
159{
160 DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
161}
162
163/**
164 Writes back a range of data cache lines in the cache coherency domain of the
165 calling CPU.
166
167 Writes back the data cache lines specified by Address and Length. If Address
168 is not aligned on a cache line boundary, then entire data cache line
169 containing Address is written back. If Address + Length is not aligned on a
170 cache line boundary, then the entire data cache line containing Address +
171 Length -1 is written back. This function may choose to write back the entire
172 data cache if that is more efficient than writing back the specified range.
173 If Length is 0, then no data cache lines are written back. This function may
174 also invalidate all the data cache lines in the specified range of the cache
175 coherency domain of the calling CPU. Address is returned.
176
177 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
178
179 @param Address The base address of the data cache lines to write back. If
180 the CPU is in a physical addressing mode, then Address is a
181 physical address. If the CPU is in a virtual addressing
182 mode, then Address is a virtual address.
183 @param Length The number of bytes to write back from the data cache.
184
185 @return Address of cache written in main memory.
186
187**/
188VOID *
189EFIAPI
190WriteBackDataCacheRange (
191 IN VOID *Address,
192 IN UINTN Length
193 )
194{
195 DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
196 return Address;
197}
198
199/**
200 Invalidates the entire data cache in cache coherency domain of the calling
201 CPU.
202
203 Invalidates the entire data cache in cache coherency domain of the calling
204 CPU. This function must be used with care because dirty cache lines are not
205 written back to system memory. It is typically used for cache diagnostics. If
206 the CPU does not support invalidation of the entire data cache, then a write
207 back and invalidate operation should be performed on the entire data cache.
208
209**/
210VOID
211EFIAPI
212InvalidateDataCache (
213 VOID
214 )
215{
216 RiscVInvalidateDataCacheAsm ();
217}
218
219/**
220 Invalidates a range of data cache lines in the cache coherency domain of the
221 calling CPU.
222
223 Invalidates the data cache lines specified by Address and Length. If Address
224 is not aligned on a cache line boundary, then entire data cache line
225 containing Address is invalidated. If Address + Length is not aligned on a
226 cache line boundary, then the entire data cache line containing Address +
227 Length -1 is invalidated. This function must never invalidate any cache lines
228 outside the specified range. If Length is 0, then no data cache lines are
229 invalidated. Address is returned. This function must be used with care
230 because dirty cache lines are not written back to system memory. It is
231 typically used for cache diagnostics. If the CPU does not support
232 invalidation of a data cache range, then a write back and invalidate
233 operation should be performed on the data cache range.
234
235 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
236
237 @param Address The base address of the data cache lines to invalidate. If
238 the CPU is in a physical addressing mode, then Address is a
239 physical address. If the CPU is in a virtual addressing mode,
240 then Address is a virtual address.
241 @param Length The number of bytes to invalidate from the data cache.
242
243 @return Address.
244
245**/
246VOID *
247EFIAPI
248InvalidateDataCacheRange (
249 IN VOID *Address,
250 IN UINTN Length
251 )
252{
253 DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
254 return Address;
255}
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