1 | /** @file
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2 | RISC-V specific functionality for cache.
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3 |
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4 | Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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5 |
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6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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7 | **/
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8 |
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9 | #include <Base.h>
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10 | #include <Library/BaseLib.h>
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11 | #include <Library/DebugLib.h>
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12 |
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13 | /**
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14 | RISC-V invalidate instruction cache.
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15 |
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16 | **/
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17 | VOID
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18 | EFIAPI
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19 | RiscVInvalidateInstCacheAsm (
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20 | VOID
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21 | );
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22 |
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23 | /**
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24 | RISC-V invalidate data cache.
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25 |
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26 | **/
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27 | VOID
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28 | EFIAPI
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29 | RiscVInvalidateDataCacheAsm (
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30 | VOID
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31 | );
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32 |
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33 | /**
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34 | Invalidates the entire instruction cache in cache coherency domain of the
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35 | calling CPU.
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36 |
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37 | **/
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38 | VOID
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39 | EFIAPI
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40 | InvalidateInstructionCache (
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41 | VOID
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42 | )
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43 | {
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44 | RiscVInvalidateInstCacheAsm ();
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45 | }
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46 |
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47 | /**
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48 | Invalidates a range of instruction cache lines in the cache coherency domain
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49 | of the calling CPU.
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50 |
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51 | Invalidates the instruction cache lines specified by Address and Length. If
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52 | Address is not aligned on a cache line boundary, then entire instruction
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53 | cache line containing Address is invalidated. If Address + Length is not
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54 | aligned on a cache line boundary, then the entire instruction cache line
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55 | containing Address + Length -1 is invalidated. This function may choose to
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56 | invalidate the entire instruction cache if that is more efficient than
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57 | invalidating the specified range. If Length is 0, then no instruction cache
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58 | lines are invalidated. Address is returned.
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59 |
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60 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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61 |
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62 | @param Address The base address of the instruction cache lines to
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63 | invalidate. If the CPU is in a physical addressing mode, then
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64 | Address is a physical address. If the CPU is in a virtual
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65 | addressing mode, then Address is a virtual address.
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66 |
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67 | @param Length The number of bytes to invalidate from the instruction cache.
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68 |
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69 | @return Address.
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70 |
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71 | **/
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72 | VOID *
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73 | EFIAPI
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74 | InvalidateInstructionCacheRange (
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75 | IN VOID *Address,
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76 | IN UINTN Length
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77 | )
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78 | {
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79 | DEBUG (
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80 | (DEBUG_WARN,
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81 | "%a:RISC-V unsupported function.\n"
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82 | "Invalidating the whole instruction cache instead.\n", __func__)
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83 | );
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84 | InvalidateInstructionCache ();
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85 | return Address;
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86 | }
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87 |
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88 | /**
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89 | Writes back and invalidates the entire data cache in cache coherency domain
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90 | of the calling CPU.
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91 |
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92 | Writes back and invalidates the entire data cache in cache coherency domain
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93 | of the calling CPU. This function guarantees that all dirty cache lines are
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94 | written back to system memory, and also invalidates all the data cache lines
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95 | in the cache coherency domain of the calling CPU.
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96 |
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97 | **/
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98 | VOID
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99 | EFIAPI
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100 | WriteBackInvalidateDataCache (
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101 | VOID
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102 | )
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103 | {
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104 | DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
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105 | }
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106 |
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107 | /**
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108 | Writes back and invalidates a range of data cache lines in the cache
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109 | coherency domain of the calling CPU.
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110 |
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111 | Writes back and invalidates the data cache lines specified by Address and
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112 | Length. If Address is not aligned on a cache line boundary, then entire data
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113 | cache line containing Address is written back and invalidated. If Address +
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114 | Length is not aligned on a cache line boundary, then the entire data cache
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115 | line containing Address + Length -1 is written back and invalidated. This
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116 | function may choose to write back and invalidate the entire data cache if
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117 | that is more efficient than writing back and invalidating the specified
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118 | range. If Length is 0, then no data cache lines are written back and
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119 | invalidated. Address is returned.
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120 |
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121 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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122 |
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123 | @param Address The base address of the data cache lines to write back and
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124 | invalidate. If the CPU is in a physical addressing mode, then
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125 | Address is a physical address. If the CPU is in a virtual
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126 | addressing mode, then Address is a virtual address.
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127 | @param Length The number of bytes to write back and invalidate from the
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128 | data cache.
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129 |
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130 | @return Address of cache invalidation.
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131 |
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132 | **/
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133 | VOID *
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134 | EFIAPI
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135 | WriteBackInvalidateDataCacheRange (
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136 | IN VOID *Address,
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137 | IN UINTN Length
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138 | )
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139 | {
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140 | DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
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141 | return Address;
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142 | }
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143 |
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144 | /**
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145 | Writes back the entire data cache in cache coherency domain of the calling
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146 | CPU.
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147 |
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148 | Writes back the entire data cache in cache coherency domain of the calling
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149 | CPU. This function guarantees that all dirty cache lines are written back to
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150 | system memory. This function may also invalidate all the data cache lines in
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151 | the cache coherency domain of the calling CPU.
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152 |
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153 | **/
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154 | VOID
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155 | EFIAPI
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156 | WriteBackDataCache (
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157 | VOID
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158 | )
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159 | {
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160 | DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
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161 | }
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162 |
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163 | /**
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164 | Writes back a range of data cache lines in the cache coherency domain of the
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165 | calling CPU.
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166 |
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167 | Writes back the data cache lines specified by Address and Length. If Address
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168 | is not aligned on a cache line boundary, then entire data cache line
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169 | containing Address is written back. If Address + Length is not aligned on a
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170 | cache line boundary, then the entire data cache line containing Address +
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171 | Length -1 is written back. This function may choose to write back the entire
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172 | data cache if that is more efficient than writing back the specified range.
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173 | If Length is 0, then no data cache lines are written back. This function may
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174 | also invalidate all the data cache lines in the specified range of the cache
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175 | coherency domain of the calling CPU. Address is returned.
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176 |
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177 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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178 |
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179 | @param Address The base address of the data cache lines to write back. If
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180 | the CPU is in a physical addressing mode, then Address is a
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181 | physical address. If the CPU is in a virtual addressing
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182 | mode, then Address is a virtual address.
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183 | @param Length The number of bytes to write back from the data cache.
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184 |
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185 | @return Address of cache written in main memory.
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186 |
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187 | **/
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188 | VOID *
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189 | EFIAPI
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190 | WriteBackDataCacheRange (
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191 | IN VOID *Address,
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192 | IN UINTN Length
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193 | )
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194 | {
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195 | DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
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196 | return Address;
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197 | }
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198 |
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199 | /**
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200 | Invalidates the entire data cache in cache coherency domain of the calling
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201 | CPU.
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202 |
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203 | Invalidates the entire data cache in cache coherency domain of the calling
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204 | CPU. This function must be used with care because dirty cache lines are not
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205 | written back to system memory. It is typically used for cache diagnostics. If
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206 | the CPU does not support invalidation of the entire data cache, then a write
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207 | back and invalidate operation should be performed on the entire data cache.
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208 |
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209 | **/
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210 | VOID
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211 | EFIAPI
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212 | InvalidateDataCache (
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213 | VOID
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214 | )
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215 | {
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216 | RiscVInvalidateDataCacheAsm ();
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217 | }
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218 |
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219 | /**
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220 | Invalidates a range of data cache lines in the cache coherency domain of the
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221 | calling CPU.
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222 |
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223 | Invalidates the data cache lines specified by Address and Length. If Address
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224 | is not aligned on a cache line boundary, then entire data cache line
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225 | containing Address is invalidated. If Address + Length is not aligned on a
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226 | cache line boundary, then the entire data cache line containing Address +
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227 | Length -1 is invalidated. This function must never invalidate any cache lines
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228 | outside the specified range. If Length is 0, then no data cache lines are
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229 | invalidated. Address is returned. This function must be used with care
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230 | because dirty cache lines are not written back to system memory. It is
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231 | typically used for cache diagnostics. If the CPU does not support
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232 | invalidation of a data cache range, then a write back and invalidate
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233 | operation should be performed on the data cache range.
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234 |
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235 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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236 |
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237 | @param Address The base address of the data cache lines to invalidate. If
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238 | the CPU is in a physical addressing mode, then Address is a
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239 | physical address. If the CPU is in a virtual addressing mode,
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240 | then Address is a virtual address.
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241 | @param Length The number of bytes to invalidate from the data cache.
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242 |
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243 | @return Address.
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244 |
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245 | **/
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246 | VOID *
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247 | EFIAPI
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248 | InvalidateDataCacheRange (
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249 | IN VOID *Address,
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250 | IN UINTN Length
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251 | )
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252 | {
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253 | DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
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254 | return Address;
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255 | }
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