| 1 | /** @file
|
|---|
| 2 | I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt
|
|---|
| 3 | Controller (IOAPIC), 1996.
|
|---|
| 4 |
|
|---|
| 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
|
|---|
| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent
|
|---|
| 7 |
|
|---|
| 8 | **/
|
|---|
| 9 |
|
|---|
| 10 | #ifndef __IO_APIC_H__
|
|---|
| 11 | #define __IO_APIC_H__
|
|---|
| 12 |
|
|---|
| 13 | ///
|
|---|
| 14 | /// I/O APIC Register Offsets
|
|---|
| 15 | ///
|
|---|
| 16 | #define IOAPIC_INDEX_OFFSET 0x00
|
|---|
| 17 | #define IOAPIC_DATA_OFFSET 0x10
|
|---|
| 18 |
|
|---|
| 19 | ///
|
|---|
| 20 | /// I/O APIC Indirect Register Indexes
|
|---|
| 21 | ///
|
|---|
| 22 | #define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00
|
|---|
| 23 | #define IO_APIC_VERSION_REGISTER_INDEX 0x01
|
|---|
| 24 | #define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10
|
|---|
| 25 |
|
|---|
| 26 | ///
|
|---|
| 27 | /// I/O APIC Interrupt Deliver Modes
|
|---|
| 28 | ///
|
|---|
| 29 | #define IO_APIC_DELIVERY_MODE_FIXED 0
|
|---|
| 30 | #define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
|
|---|
| 31 | #define IO_APIC_DELIVERY_MODE_SMI 2
|
|---|
| 32 | #define IO_APIC_DELIVERY_MODE_NMI 4
|
|---|
| 33 | #define IO_APIC_DELIVERY_MODE_INIT 5
|
|---|
| 34 | #define IO_APIC_DELIVERY_MODE_EXTINT 7
|
|---|
| 35 |
|
|---|
| 36 | #pragma pack(1)
|
|---|
| 37 |
|
|---|
| 38 | typedef union {
|
|---|
| 39 | struct {
|
|---|
| 40 | UINT32 Reserved0 : 24;
|
|---|
| 41 | UINT32 Identification : 4;
|
|---|
| 42 | UINT32 Reserved1 : 4;
|
|---|
| 43 | } Bits;
|
|---|
| 44 | UINT32 Uint32;
|
|---|
| 45 | } IO_APIC_IDENTIFICATION_REGISTER;
|
|---|
| 46 |
|
|---|
| 47 | typedef union {
|
|---|
| 48 | struct {
|
|---|
| 49 | UINT32 Version : 8;
|
|---|
| 50 | UINT32 Reserved0 : 8;
|
|---|
| 51 | UINT32 MaximumRedirectionEntry : 8;
|
|---|
| 52 | UINT32 Reserved1 : 8;
|
|---|
| 53 | } Bits;
|
|---|
| 54 | UINT32 Uint32;
|
|---|
| 55 | } IO_APIC_VERSION_REGISTER;
|
|---|
| 56 |
|
|---|
| 57 | typedef union {
|
|---|
| 58 | struct {
|
|---|
| 59 | UINT32 Vector : 8;
|
|---|
| 60 | UINT32 DeliveryMode : 3;
|
|---|
| 61 | UINT32 DestinationMode : 1;
|
|---|
| 62 | UINT32 DeliveryStatus : 1;
|
|---|
| 63 | UINT32 Polarity : 1;
|
|---|
| 64 | UINT32 RemoteIRR : 1;
|
|---|
| 65 | UINT32 TriggerMode : 1;
|
|---|
| 66 | UINT32 Mask : 1;
|
|---|
| 67 | UINT32 Reserved0 : 15;
|
|---|
| 68 | UINT32 Reserved1 : 24;
|
|---|
| 69 | UINT32 DestinationID : 8;
|
|---|
| 70 | } Bits;
|
|---|
| 71 | struct {
|
|---|
| 72 | UINT32 Low;
|
|---|
| 73 | UINT32 High;
|
|---|
| 74 | } Uint32;
|
|---|
| 75 | UINT64 Uint64;
|
|---|
| 76 | } IO_APIC_REDIRECTION_TABLE_ENTRY;
|
|---|
| 77 |
|
|---|
| 78 | #pragma pack()
|
|---|
| 79 |
|
|---|
| 80 | #endif
|
|---|
