| 1 | /** @file
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| 2 | Header file for Pci shell Debug1 function.
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| 3 |
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| 4 | Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
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| 5 | Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
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| 6 | This program and the accompanying materials
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| 7 | are licensed and made available under the terms and conditions of the BSD License
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| 8 | which accompanies this distribution. The full text of the license may be found at
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| 9 | http://opensource.org/licenses/bsd-license.php
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| 10 |
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| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 |
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| 14 | **/
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| 15 |
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| 16 | #ifndef _EFI_SHELL_PCI_H_
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| 17 | #define _EFI_SHELL_PCI_H_
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| 18 |
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| 19 | typedef enum {
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| 20 | PciDevice,
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| 21 | PciP2pBridge,
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| 22 | PciCardBusBridge,
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| 23 | PciUndefined
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| 24 | } PCI_HEADER_TYPE;
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| 25 |
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| 26 | #define HEADER_TYPE_MULTI_FUNCTION 0x80
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| 27 |
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| 28 | #define MAX_BUS_NUMBER 255
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| 29 | #define MAX_DEVICE_NUMBER 31
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| 30 | #define MAX_FUNCTION_NUMBER 7
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| 31 |
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| 32 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
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| 33 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
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| 34 |
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| 35 | #define CALC_EFI_PCI_ADDRESS(Bus, Dev, Func, Reg) \
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| 36 | ((UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + ((UINTN) Reg)))
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| 37 |
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| 38 | #define CALC_EFI_PCIEX_ADDRESS(Bus, Dev, Func, ExReg) ( \
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| 39 | (UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + (LShiftU64 ((UINT64) ExReg, 32))) \
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| 40 | );
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| 41 |
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| 42 | #define INDEX_OF(Field) ((UINT8 *) (Field) - (UINT8 *) mConfigSpace)
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| 43 |
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| 44 | #define PCI_BIT_0 0x00000001
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| 45 | #define PCI_BIT_1 0x00000002
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| 46 | #define PCI_BIT_2 0x00000004
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| 47 | #define PCI_BIT_3 0x00000008
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| 48 | #define PCI_BIT_4 0x00000010
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| 49 | #define PCI_BIT_5 0x00000020
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| 50 | #define PCI_BIT_6 0x00000040
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| 51 | #define PCI_BIT_7 0x00000080
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| 52 | #define PCI_BIT_8 0x00000100
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| 53 | #define PCI_BIT_9 0x00000200
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| 54 | #define PCI_BIT_10 0x00000400
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| 55 | #define PCI_BIT_11 0x00000800
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| 56 | #define PCI_BIT_12 0x00001000
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| 57 | #define PCI_BIT_13 0x00002000
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| 58 | #define PCI_BIT_14 0x00004000
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| 59 | #define PCI_BIT_15 0x00008000
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| 60 |
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| 61 | //
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| 62 | // PCIE device/port types
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| 63 | //
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| 64 | #define PCIE_PCIE_ENDPOINT 0
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| 65 | #define PCIE_LEGACY_PCIE_ENDPOINT 1
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| 66 | #define PCIE_ROOT_COMPLEX_ROOT_PORT 4
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| 67 | #define PCIE_SWITCH_UPSTREAM_PORT 5
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| 68 | #define PCIE_SWITCH_DOWNSTREAM_PORT 6
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| 69 | #define PCIE_PCIE_TO_PCIX_BRIDGE 7
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| 70 | #define PCIE_PCIX_TO_PCIE_BRIDGE 8
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| 71 | #define PCIE_ROOT_COMPLEX_INTEGRATED_PORT 9
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| 72 | #define PCIE_ROOT_COMPLEX_EVENT_COLLECTOR 10
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| 73 | #define PCIE_DEVICE_PORT_TYPE_MAX 11
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| 74 |
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| 75 | #define IS_PCIE_ENDPOINT(DevicePortType) \
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| 76 | ((DevicePortType) == PCIE_PCIE_ENDPOINT || \
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| 77 | (DevicePortType) == PCIE_LEGACY_PCIE_ENDPOINT || \
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| 78 | (DevicePortType) == PCIE_ROOT_COMPLEX_INTEGRATED_PORT)
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| 79 |
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| 80 | #define IS_PCIE_SWITCH(DevicePortType) \
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| 81 | ((DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) || \
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| 82 | (DevicePortType == PCIE_SWITCH_DOWNSTREAM_PORT))
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| 83 |
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| 84 | //
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| 85 | // Capabilities Register
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| 86 | //
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| 87 | #define PCIE_CAP_VERSION(PcieCapReg) \
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| 88 | ((PcieCapReg) & 0x0f)
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| 89 | #define PCIE_CAP_DEVICEPORT_TYPE(PcieCapReg) \
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| 90 | (((PcieCapReg) >> 4) & 0x0f)
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| 91 | #define PCIE_CAP_SLOT_IMPLEMENTED(PcieCapReg) \
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| 92 | (((PcieCapReg) >> 8) & 0x1)
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| 93 | #define PCIE_CAP_INT_MSG_NUM(PcieCapReg) \
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| 94 | (((PcieCapReg) >> 9) & 0x1f)
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| 95 | //
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| 96 | // Device Capabilities Register
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| 97 | //
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| 98 | #define PCIE_CAP_MAX_PAYLOAD(PcieDeviceCap) \
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| 99 | ((PcieDeviceCap) & 0x7)
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| 100 | #define PCIE_CAP_PHANTOM_FUNC(PcieDeviceCap) \
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| 101 | (((PcieDeviceCap) >> 3) & 0x3)
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| 102 | #define PCIE_CAP_EXTENDED_TAG(PcieDeviceCap) \
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| 103 | (((PcieDeviceCap) >> 5) & 0x1)
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| 104 | #define PCIE_CAP_L0SLATENCY(PcieDeviceCap) \
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| 105 | (((PcieDeviceCap) >> 6) & 0x7)
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| 106 | #define PCIE_CAP_L1LATENCY(PcieDeviceCap) \
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| 107 | (((PcieDeviceCap) >> 9) & 0x7)
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| 108 | #define PCIE_CAP_ERR_REPORTING(PcieDeviceCap) \
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| 109 | (((PcieDeviceCap) >> 15) & 0x1)
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| 110 | #define PCIE_CAP_SLOT_POWER_VALUE(PcieDeviceCap) \
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| 111 | (((PcieDeviceCap) >> 18) & 0x0ff)
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| 112 | #define PCIE_CAP_SLOT_POWER_SCALE(PcieDeviceCap) \
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| 113 | (((PcieDeviceCap) >> 26) & 0x3)
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| 114 | #define PCIE_CAP_FUNC_LEVEL_RESET(PcieDeviceCap) \
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| 115 | (((PcieDeviceCap) >> 28) & 0x1)
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| 116 | //
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| 117 | // Device Control Register
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| 118 | //
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| 119 | #define PCIE_CAP_COR_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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| 120 | ((PcieDeviceControl) & 0x1)
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| 121 | #define PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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| 122 | (((PcieDeviceControl) >> 1) & 0x1)
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| 123 | #define PCIE_CAP_FATAL_ERR_REPORTING_ENABLE(PcieDeviceControl) \
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| 124 | (((PcieDeviceControl) >> 2) & 0x1)
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| 125 | #define PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE(PcieDeviceControl) \
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| 126 | (((PcieDeviceControl) >> 3) & 0x1)
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| 127 | #define PCIE_CAP_RELAXED_ORDERING_ENABLE(PcieDeviceControl) \
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| 128 | (((PcieDeviceControl) >> 4) & 0x1)
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| 129 | #define PCIE_CAP_MAX_PAYLOAD_SIZE(PcieDeviceControl) \
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| 130 | (((PcieDeviceControl) >> 5) & 0x7)
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| 131 | #define PCIE_CAP_EXTENDED_TAG_ENABLE(PcieDeviceControl) \
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| 132 | (((PcieDeviceControl) >> 8) & 0x1)
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| 133 | #define PCIE_CAP_PHANTOM_FUNC_ENABLE(PcieDeviceControl) \
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| 134 | (((PcieDeviceControl) >> 9) & 0x1)
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| 135 | #define PCIE_CAP_AUX_PM_ENABLE(PcieDeviceControl) \
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| 136 | (((PcieDeviceControl) >> 10) & 0x1)
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| 137 | #define PCIE_CAP_NO_SNOOP_ENABLE(PcieDeviceControl) \
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| 138 | (((PcieDeviceControl) >> 11) & 0x1)
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| 139 | #define PCIE_CAP_MAX_READ_REQ_SIZE(PcieDeviceControl) \
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| 140 | (((PcieDeviceControl) >> 12) & 0x7)
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| 141 | #define PCIE_CAP_BRG_CONF_RETRY(PcieDeviceControl) \
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| 142 | (((PcieDeviceControl) >> 15) & 0x1)
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| 143 | //
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| 144 | // Device Status Register
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| 145 | //
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| 146 | #define PCIE_CAP_COR_ERR_DETECTED(PcieDeviceStatus) \
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| 147 | ((PcieDeviceStatus) & 0x1)
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| 148 | #define PCIE_CAP_NONFAT_ERR_DETECTED(PcieDeviceStatus) \
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| 149 | (((PcieDeviceStatus) >> 1) & 0x1)
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| 150 | #define PCIE_CAP_FATAL_ERR_DETECTED(PcieDeviceStatus) \
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| 151 | (((PcieDeviceStatus) >> 2) & 0x1)
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| 152 | #define PCIE_CAP_UNSUP_REQ_DETECTED(PcieDeviceStatus) \
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| 153 | (((PcieDeviceStatus) >> 3) & 0x1)
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| 154 | #define PCIE_CAP_AUX_POWER_DETECTED(PcieDeviceStatus) \
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| 155 | (((PcieDeviceStatus) >> 4) & 0x1)
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| 156 | #define PCIE_CAP_TRANSACTION_PENDING(PcieDeviceStatus) \
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| 157 | (((PcieDeviceStatus) >> 5) & 0x1)
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| 158 | //
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| 159 | // Link Capabilities Register
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| 160 | //
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| 161 | #define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \
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| 162 | ((PcieLinkCap) & 0x0f)
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| 163 | #define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
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| 164 | (((PcieLinkCap) >> 4) & 0x3f)
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| 165 | #define PCIE_CAP_ASPM_SUPPORT(PcieLinkCap) \
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| 166 | (((PcieLinkCap) >> 10) & 0x3)
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| 167 | #define PCIE_CAP_L0S_LATENCY(PcieLinkCap) \
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| 168 | (((PcieLinkCap) >> 12) & 0x7)
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| 169 | #define PCIE_CAP_L1_LATENCY(PcieLinkCap) \
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| 170 | (((PcieLinkCap) >> 15) & 0x7)
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| 171 | #define PCIE_CAP_CLOCK_PM(PcieLinkCap) \
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| 172 | (((PcieLinkCap) >> 18) & 0x1)
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| 173 | #define PCIE_CAP_SUP_DOWN_ERR_REPORTING(PcieLinkCap) \
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| 174 | (((PcieLinkCap) >> 19) & 0x1)
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| 175 | #define PCIE_CAP_LINK_ACTIVE_REPORTING(PcieLinkCap) \
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| 176 | (((PcieLinkCap) >> 20) & 0x1)
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| 177 | #define PCIE_CAP_LINK_BWD_NOTIF_CAP(PcieLinkCap) \
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| 178 | (((PcieLinkCap) >> 21) & 0x1)
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| 179 | #define PCIE_CAP_PORT_NUMBER(PcieLinkCap) \
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| 180 | (((PcieLinkCap) >> 24) & 0x0ff)
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| 181 | //
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| 182 | // Link Control Register
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| 183 | //
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| 184 | #define PCIE_CAP_ASPM_CONTROL(PcieLinkControl) \
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| 185 | ((PcieLinkControl) & 0x3)
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| 186 | #define PCIE_CAP_RCB(PcieLinkControl) \
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| 187 | (((PcieLinkControl) >> 3) & 0x1)
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| 188 | #define PCIE_CAP_LINK_DISABLE(PcieLinkControl) \
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| 189 | (((PcieLinkControl) >> 4) & 0x1)
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| 190 | #define PCIE_CAP_COMMON_CLK_CONF(PcieLinkControl) \
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| 191 | (((PcieLinkControl) >> 6) & 0x1)
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| 192 | #define PCIE_CAP_EXT_SYNC(PcieLinkControl) \
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| 193 | (((PcieLinkControl) >> 7) & 0x1)
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| 194 | #define PCIE_CAP_CLK_PWR_MNG(PcieLinkControl) \
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| 195 | (((PcieLinkControl) >> 8) & 0x1)
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| 196 | #define PCIE_CAP_HW_AUTO_WIDTH_DISABLE(PcieLinkControl) \
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| 197 | (((PcieLinkControl) >> 9) & 0x1)
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| 198 | #define PCIE_CAP_LINK_BDW_MNG_INT_EN(PcieLinkControl) \
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| 199 | (((PcieLinkControl) >> 10) & 0x1)
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| 200 | #define PCIE_CAP_LINK_AUTO_BDW_INT_EN(PcieLinkControl) \
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| 201 | (((PcieLinkControl) >> 11) & 0x1)
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| 202 | //
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| 203 | // Link Status Register
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| 204 | //
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| 205 | #define PCIE_CAP_CUR_LINK_SPEED(PcieLinkStatus) \
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| 206 | ((PcieLinkStatus) & 0x0f)
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| 207 | #define PCIE_CAP_NEGO_LINK_WIDTH(PcieLinkStatus) \
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| 208 | (((PcieLinkStatus) >> 4) & 0x3f)
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| 209 | #define PCIE_CAP_LINK_TRAINING(PcieLinkStatus) \
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| 210 | (((PcieLinkStatus) >> 11) & 0x1)
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| 211 | #define PCIE_CAP_SLOT_CLK_CONF(PcieLinkStatus) \
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| 212 | (((PcieLinkStatus) >> 12) & 0x1)
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| 213 | #define PCIE_CAP_DATA_LINK_ACTIVE(PcieLinkStatus) \
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| 214 | (((PcieLinkStatus) >> 13) & 0x1)
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| 215 | #define PCIE_CAP_LINK_BDW_MNG_STAT(PcieLinkStatus) \
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| 216 | (((PcieLinkStatus) >> 14) & 0x1)
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| 217 | #define PCIE_CAP_LINK_AUTO_BDW_STAT(PcieLinkStatus) \
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| 218 | (((PcieLinkStatus) >> 15) & 0x1)
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| 219 | //
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| 220 | // Slot Capabilities Register
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| 221 | //
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| 222 | #define PCIE_CAP_ATT_BUT_PRESENT(PcieSlotCap) \
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| 223 | ((PcieSlotCap) & 0x1)
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| 224 | #define PCIE_CAP_PWR_CTRLLER_PRESENT(PcieSlotCap) \
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| 225 | (((PcieSlotCap) >> 1) & 0x1)
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| 226 | #define PCIE_CAP_MRL_SENSOR_PRESENT(PcieSlotCap) \
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| 227 | (((PcieSlotCap) >> 2) & 0x1)
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| 228 | #define PCIE_CAP_ATT_IND_PRESENT(PcieSlotCap) \
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| 229 | (((PcieSlotCap) >> 3) & 0x1)
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| 230 | #define PCIE_CAP_PWD_IND_PRESENT(PcieSlotCap) \
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| 231 | (((PcieSlotCap) >> 4) & 0x1)
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| 232 | #define PCIE_CAP_HOTPLUG_SUPPRISE(PcieSlotCap) \
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| 233 | (((PcieSlotCap) >> 5) & 0x1)
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| 234 | #define PCIE_CAP_HOTPLUG_CAPABLE(PcieSlotCap) \
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| 235 | (((PcieSlotCap) >> 6) & 0x1)
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| 236 | #define PCIE_CAP_SLOT_PWR_LIMIT_VALUE(PcieSlotCap) \
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| 237 | (((PcieSlotCap) >> 7) & 0x0ff)
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| 238 | #define PCIE_CAP_SLOT_PWR_LIMIT_SCALE(PcieSlotCap) \
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| 239 | (((PcieSlotCap) >> 15) & 0x3)
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| 240 | #define PCIE_CAP_ELEC_INTERLOCK_PRESENT(PcieSlotCap) \
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| 241 | (((PcieSlotCap) >> 17) & 0x1)
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| 242 | #define PCIE_CAP_NO_COMM_COMPLETED_SUP(PcieSlotCap) \
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| 243 | (((PcieSlotCap) >> 18) & 0x1)
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| 244 | #define PCIE_CAP_PHY_SLOT_NUM(PcieSlotCap) \
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| 245 | (((PcieSlotCap) >> 19) & 0x1fff)
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| 246 | //
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| 247 | // Slot Control Register
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| 248 | //
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| 249 | #define PCIE_CAP_ATT_BUT_ENABLE(PcieSlotControl) \
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| 250 | ((PcieSlotControl) & 0x1)
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| 251 | #define PCIE_CAP_PWR_FLT_DETECT_ENABLE(PcieSlotControl) \
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| 252 | (((PcieSlotControl) >> 1) & 0x1)
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| 253 | #define PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE(PcieSlotControl) \
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| 254 | (((PcieSlotControl) >> 2) & 0x1)
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| 255 | #define PCIE_CAP_PRES_DETECT_CHANGE_ENABLE(PcieSlotControl) \
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| 256 | (((PcieSlotControl) >> 3) & 0x1)
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| 257 | #define PCIE_CAP_COMM_CMPL_INT_ENABLE(PcieSlotControl) \
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| 258 | (((PcieSlotControl) >> 4) & 0x1)
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| 259 | #define PCIE_CAP_HOTPLUG_INT_ENABLE(PcieSlotControl) \
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| 260 | (((PcieSlotControl) >> 5) & 0x1)
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| 261 | #define PCIE_CAP_ATT_IND_CTRL(PcieSlotControl) \
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| 262 | (((PcieSlotControl) >> 6) & 0x3)
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| 263 | #define PCIE_CAP_PWR_IND_CTRL(PcieSlotControl) \
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| 264 | (((PcieSlotControl) >> 8) & 0x3)
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| 265 | #define PCIE_CAP_PWR_CTRLLER_CTRL(PcieSlotControl) \
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| 266 | (((PcieSlotControl) >> 10) & 0x1)
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| 267 | #define PCIE_CAP_ELEC_INTERLOCK_CTRL(PcieSlotControl) \
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| 268 | (((PcieSlotControl) >> 11) & 0x1)
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| 269 | #define PCIE_CAP_DLINK_STAT_CHANGE_ENABLE(PcieSlotControl) \
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| 270 | (((PcieSlotControl) >> 12) & 0x1)
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| 271 | //
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| 272 | // Slot Status Register
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| 273 | //
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| 274 | #define PCIE_CAP_ATT_BUT_PRESSED(PcieSlotStatus) \
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| 275 | ((PcieSlotStatus) & 0x1)
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| 276 | #define PCIE_CAP_PWR_FLT_DETECTED(PcieSlotStatus) \
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| 277 | (((PcieSlotStatus) >> 1) & 0x1)
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| 278 | #define PCIE_CAP_MRL_SENSOR_CHANGED(PcieSlotStatus) \
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| 279 | (((PcieSlotStatus) >> 2) & 0x1)
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| 280 | #define PCIE_CAP_PRES_DETECT_CHANGED(PcieSlotStatus) \
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| 281 | (((PcieSlotStatus) >> 3) & 0x1)
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| 282 | #define PCIE_CAP_COMM_COMPLETED(PcieSlotStatus) \
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| 283 | (((PcieSlotStatus) >> 4) & 0x1)
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| 284 | #define PCIE_CAP_MRL_SENSOR_STATE(PcieSlotStatus) \
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| 285 | (((PcieSlotStatus) >> 5) & 0x1)
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| 286 | #define PCIE_CAP_PRES_DETECT_STATE(PcieSlotStatus) \
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| 287 | (((PcieSlotStatus) >> 6) & 0x1)
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| 288 | #define PCIE_CAP_ELEC_INTERLOCK_STATE(PcieSlotStatus) \
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| 289 | (((PcieSlotStatus) >> 7) & 0x1)
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| 290 | #define PCIE_CAP_DLINK_STAT_CHANGED(PcieSlotStatus) \
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| 291 | (((PcieSlotStatus) >> 8) & 0x1)
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| 292 | //
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| 293 | // Root Control Register
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| 294 | //
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| 295 | #define PCIE_CAP_SYSERR_ON_CORERR_EN(PcieRootControl) \
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| 296 | ((PcieRootControl) & 0x1)
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| 297 | #define PCIE_CAP_SYSERR_ON_NONFATERR_EN(PcieRootControl) \
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| 298 | (((PcieRootControl) >> 1) & 0x1)
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| 299 | #define PCIE_CAP_SYSERR_ON_FATERR_EN(PcieRootControl) \
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| 300 | (((PcieRootControl) >> 2) & 0x1)
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| 301 | #define PCIE_CAP_PME_INT_ENABLE(PcieRootControl) \
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| 302 | (((PcieRootControl) >> 3) & 0x1)
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| 303 | #define PCIE_CAP_CRS_SW_VIS_ENABLE(PcieRootControl) \
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| 304 | (((PcieRootControl) >> 4) & 0x1)
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| 305 | //
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| 306 | // Root Capabilities Register
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| 307 | //
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| 308 | #define PCIE_CAP_CRS_SW_VIS(PcieRootCap) \
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| 309 | ((PcieRootCap) & 0x1)
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| 310 | //
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| 311 | // Root Status Register
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| 312 | //
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| 313 | #define PCIE_CAP_PME_REQ_ID(PcieRootStatus) \
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| 314 | ((PcieRootStatus) & 0x0ffff)
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| 315 | #define PCIE_CAP_PME_STATUS(PcieRootStatus) \
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| 316 | (((PcieRootStatus) >> 16) & 0x1)
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| 317 | #define PCIE_CAP_PME_PENDING(PcieRootStatus) \
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| 318 | (((PcieRootStatus) >> 17) & 0x1)
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| 319 |
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| 320 | #pragma pack(1)
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| 321 | //
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| 322 | // Common part of the PCI configuration space header for devices, P2P bridges,
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| 323 | // and cardbus bridges
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| 324 | //
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| 325 | typedef struct {
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| 326 | UINT16 VendorId;
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| 327 | UINT16 DeviceId;
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| 328 |
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| 329 | UINT16 Command;
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| 330 | UINT16 Status;
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| 331 |
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| 332 | UINT8 RevisionId;
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| 333 | UINT8 ClassCode[3];
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| 334 |
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| 335 | UINT8 CacheLineSize;
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| 336 | UINT8 PrimaryLatencyTimer;
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| 337 | UINT8 HeaderType;
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| 338 | UINT8 Bist;
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| 339 |
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| 340 | } PCI_COMMON_HEADER;
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| 341 |
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| 342 | //
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| 343 | // PCI configuration space header for devices(after the common part)
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| 344 | //
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| 345 | typedef struct {
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| 346 | UINT32 Bar[6]; // Base Address Registers
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| 347 | UINT32 CardBusCISPtr; // CardBus CIS Pointer
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| 348 | UINT16 SubVendorId; // Subsystem Vendor ID
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| 349 | UINT16 SubSystemId; // Subsystem ID
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| 350 | UINT32 ROMBar; // Expansion ROM Base Address
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| 351 | UINT8 CapabilitiesPtr; // Capabilities Pointer
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| 352 | UINT8 Reserved[3];
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| 353 |
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| 354 | UINT32 Reserved1;
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| 355 |
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| 356 | UINT8 InterruptLine; // Interrupt Line
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| 357 | UINT8 InterruptPin; // Interrupt Pin
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| 358 | UINT8 MinGnt; // Min_Gnt
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| 359 | UINT8 MaxLat; // Max_Lat
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| 360 | } PCI_DEVICE_HEADER;
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| 361 |
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| 362 | //
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| 363 | // PCI configuration space header for pci-to-pci bridges(after the common part)
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| 364 | //
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| 365 | typedef struct {
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| 366 | UINT32 Bar[2]; // Base Address Registers
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| 367 | UINT8 PrimaryBus; // Primary Bus Number
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| 368 | UINT8 SecondaryBus; // Secondary Bus Number
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| 369 | UINT8 SubordinateBus; // Subordinate Bus Number
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| 370 | UINT8 SecondaryLatencyTimer; // Secondary Latency Timer
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| 371 | UINT8 IoBase; // I/O Base
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| 372 | UINT8 IoLimit; // I/O Limit
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| 373 | UINT16 SecondaryStatus; // Secondary Status
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| 374 | UINT16 MemoryBase; // Memory Base
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| 375 | UINT16 MemoryLimit; // Memory Limit
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| 376 | UINT16 PrefetchableMemBase; // Pre-fetchable Memory Base
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| 377 | UINT16 PrefetchableMemLimit; // Pre-fetchable Memory Limit
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| 378 | UINT32 PrefetchableBaseUpper; // Pre-fetchable Base Upper 32 bits
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| 379 | UINT32 PrefetchableLimitUpper; // Pre-fetchable Limit Upper 32 bits
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| 380 | UINT16 IoBaseUpper; // I/O Base Upper 16 bits
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| 381 | UINT16 IoLimitUpper; // I/O Limit Upper 16 bits
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| 382 | UINT8 CapabilitiesPtr; // Capabilities Pointer
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| 383 | UINT8 Reserved[3];
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| 384 |
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| 385 | UINT32 ROMBar; // Expansion ROM Base Address
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| 386 | UINT8 InterruptLine; // Interrupt Line
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| 387 | UINT8 InterruptPin; // Interrupt Pin
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| 388 | UINT16 BridgeControl; // Bridge Control
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| 389 | } PCI_BRIDGE_HEADER;
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| 390 |
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| 391 | //
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| 392 | // PCI configuration space header for cardbus bridges(after the common part)
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| 393 | //
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| 394 | typedef struct {
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| 395 | UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
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| 396 | // Address Register
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| 397 | //
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| 398 | UINT8 CapabilitiesPtr; // 14h in pci-cardbus bridge.
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| 399 | UINT8 Reserved;
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| 400 | UINT16 SecondaryStatus; // Secondary Status
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| 401 | UINT8 PciBusNumber; // PCI Bus Number
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| 402 | UINT8 CardBusBusNumber; // CardBus Bus Number
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| 403 | UINT8 SubordinateBusNumber; // Subordinate Bus Number
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| 404 | UINT8 CardBusLatencyTimer; // CardBus Latency Timer
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| 405 | UINT32 MemoryBase0; // Memory Base Register 0
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| 406 | UINT32 MemoryLimit0; // Memory Limit Register 0
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| 407 | UINT32 MemoryBase1;
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| 408 | UINT32 MemoryLimit1;
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| 409 | UINT32 IoBase0;
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| 410 | UINT32 IoLimit0; // I/O Base Register 0
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| 411 | UINT32 IoBase1; // I/O Limit Register 0
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| 412 | UINT32 IoLimit1;
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| 413 |
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| 414 | UINT8 InterruptLine; // Interrupt Line
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| 415 | UINT8 InterruptPin; // Interrupt Pin
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| 416 | UINT16 BridgeControl; // Bridge Control
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| 417 | } PCI_CARDBUS_HEADER;
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| 418 |
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| 419 | //
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| 420 | // Data region after PCI configuration header(for cardbus bridge)
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| 421 | //
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| 422 | typedef struct {
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| 423 | UINT16 SubVendorId; // Subsystem Vendor ID
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| 424 | UINT16 SubSystemId; // Subsystem ID
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| 425 | UINT32 LegacyBase; // Optional 16-Bit PC Card Legacy
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| 426 | // Mode Base Address
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| 427 | //
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| 428 | UINT32 Data[46];
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| 429 | } PCI_CARDBUS_DATA;
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| 430 |
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| 431 | typedef union {
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| 432 | PCI_DEVICE_HEADER Device;
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| 433 | PCI_BRIDGE_HEADER Bridge;
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| 434 | PCI_CARDBUS_HEADER CardBus;
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| 435 | } NON_COMMON_UNION;
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| 436 |
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| 437 | typedef struct {
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| 438 | PCI_COMMON_HEADER Common;
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| 439 | NON_COMMON_UNION NonCommon;
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| 440 | UINT32 Data[48];
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| 441 | } PCI_CONFIG_SPACE;
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| 442 |
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| 443 | typedef struct {
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| 444 | UINT8 PcieCapId;
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| 445 | UINT8 NextCapPtr;
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| 446 | UINT16 PcieCapReg;
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| 447 | UINT32 PcieDeviceCap;
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| 448 | UINT16 DeviceControl;
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| 449 | UINT16 DeviceStatus;
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| 450 | UINT32 LinkCap;
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| 451 | UINT16 LinkControl;
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| 452 | UINT16 LinkStatus;
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| 453 | UINT32 SlotCap;
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| 454 | UINT16 SlotControl;
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| 455 | UINT16 SlotStatus;
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| 456 | UINT16 RootControl;
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| 457 | UINT16 RsvdP;
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| 458 | UINT32 RootStatus;
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| 459 | } PCIE_CAP_STRUCTURE;
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| 460 |
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| 461 | #pragma pack()
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| 462 |
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| 463 | #endif // _PCI_H_
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