| 1 | /** @file
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| 2 | C based implementation of IA32 interrupt handling only
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| 3 | requiring a minimal assembly interrupt entry point.
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| 4 |
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| 5 | Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 7 |
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| 8 | **/
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| 9 |
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| 10 | #ifndef _CPU_GDT_H_
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| 11 | #define _CPU_GDT_H_
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| 12 |
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| 13 | //
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| 14 | // Local structure definitions
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| 15 | //
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| 16 |
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| 17 | #pragma pack (1)
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| 18 |
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| 19 | //
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| 20 | // Global Descriptor Entry structures
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| 21 | //
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| 22 |
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| 23 | typedef struct _GDT_ENTRY {
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| 24 | UINT16 Limit15_0;
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| 25 | UINT16 Base15_0;
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| 26 | UINT8 Base23_16;
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| 27 | UINT8 Type;
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| 28 | UINT8 Limit19_16_and_flags;
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| 29 | UINT8 Base31_24;
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| 30 | } GDT_ENTRY;
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| 31 |
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| 32 | typedef
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| 33 | struct _GDT_ENTRIES {
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| 34 | GDT_ENTRY Null;
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| 35 | GDT_ENTRY Linear;
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| 36 | GDT_ENTRY LinearCode;
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| 37 | GDT_ENTRY SysData;
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| 38 | GDT_ENTRY SysCode;
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| 39 | GDT_ENTRY Spare4;
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| 40 | GDT_ENTRY LinearData64;
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| 41 | GDT_ENTRY LinearCode64;
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| 42 | GDT_ENTRY Spare5;
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| 43 | } GDT_ENTRIES;
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| 44 |
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| 45 | #pragma pack ()
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| 46 |
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| 47 | #define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
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| 48 | #define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
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| 49 | #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
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| 50 | #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
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| 51 | #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
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| 52 | #define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)
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| 53 | #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64)
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| 54 | #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
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| 55 | #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
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| 56 |
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| 57 | #if defined (MDE_CPU_IA32)
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| 58 | #define CPU_CODE_SEL LINEAR_CODE_SEL
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| 59 | #define CPU_DATA_SEL LINEAR_SEL
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| 60 | #elif defined (MDE_CPU_X64)
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| 61 | #define CPU_CODE_SEL LINEAR_CODE64_SEL
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| 62 | #define CPU_DATA_SEL LINEAR_DATA64_SEL
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| 63 | #else
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| 64 | #error CPU type not supported for CPU GDT initialization!
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| 65 | #endif
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| 66 |
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| 67 | #endif // _CPU_GDT_H_
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| 68 |
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