| 1 | /** @file
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| 2 | IA32 Local APIC Definitions.
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| 3 |
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| 4 | Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef __LOCAL_APIC_H__
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| 16 | #define __LOCAL_APIC_H__
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| 17 |
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| 18 | //
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| 19 | // Definitions for IA32 architectural MSRs
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| 20 | //
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| 21 | #define MSR_IA32_APIC_BASE_ADDRESS 0x1B
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| 22 |
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| 23 | //
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| 24 | // Definitions for CPUID instruction
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| 25 | //
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| 26 | #define CPUID_SIGNATURE 0x0
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| 27 | #define CPUID_VERSION_INFO 0x1
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| 28 | #define CPUID_EXTENDED_TOPOLOGY 0xB
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| 29 | #define CPUID_EXTENDED_FUNCTION 0x80000000
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| 30 | #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
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| 31 |
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| 32 | //
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| 33 | // Definition for Local APIC registers and related values
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| 34 | //
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| 35 | #define XAPIC_ID_OFFSET 0x20
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| 36 | #define XAPIC_VERSION_OFFSET 0x30
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| 37 | #define XAPIC_EOI_OFFSET 0x0b0
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| 38 | #define XAPIC_ICR_DFR_OFFSET 0x0e0
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| 39 | #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
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| 40 | #define XAPIC_ICR_LOW_OFFSET 0x300
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| 41 | #define XAPIC_ICR_HIGH_OFFSET 0x310
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| 42 | #define XAPIC_LVT_TIMER_OFFSET 0x320
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| 43 | #define XAPIC_LVT_LINT0_OFFSET 0x350
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| 44 | #define XAPIC_LVT_LINT1_OFFSET 0x360
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| 45 | #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
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| 46 | #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
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| 47 | #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
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| 48 |
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| 49 | #define X2APIC_MSR_BASE_ADDRESS 0x800
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| 50 | #define X2APIC_MSR_ICR_ADDRESS 0x830
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| 51 |
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| 52 | #define LOCAL_APIC_DELIVERY_MODE_FIXED 0
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| 53 | #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
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| 54 | #define LOCAL_APIC_DELIVERY_MODE_SMI 2
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| 55 | #define LOCAL_APIC_DELIVERY_MODE_NMI 4
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| 56 | #define LOCAL_APIC_DELIVERY_MODE_INIT 5
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| 57 | #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
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| 58 | #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
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| 59 |
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| 60 | #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
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| 61 | #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
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| 62 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
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| 63 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
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| 64 |
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| 65 | typedef union {
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| 66 | struct {
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| 67 | UINT32 Reserved0:8; ///< Reserved.
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| 68 | UINT32 Bsp:1; ///< Processor is BSP.
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| 69 | UINT32 Reserved1:1; ///< Reserved.
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| 70 | UINT32 Extd:1; ///< Enable x2APIC mode.
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| 71 | UINT32 En:1; ///< xAPIC global enable/disable.
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| 72 | UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
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| 73 | UINT32 ApicBaseHigh:32;
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| 74 | } Bits;
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| 75 | UINT64 Uint64;
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| 76 | } MSR_IA32_APIC_BASE;
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| 77 |
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| 78 | //
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| 79 | // Local APIC Version Register.
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| 80 | //
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| 81 | typedef union {
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| 82 | struct {
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| 83 | UINT32 Version:8; ///< The version numbers of the local APIC.
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| 84 | UINT32 Reserved0:8; ///< Reserved.
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| 85 | UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
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| 86 | UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
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| 87 | UINT32 Reserved1:7; ///< Reserved.
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| 88 | } Bits;
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| 89 | UINT32 Uint32;
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| 90 | } LOCAL_APIC_VERSION;
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| 91 |
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| 92 | //
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| 93 | // Low half of Interrupt Command Register (ICR).
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| 94 | //
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| 95 | typedef union {
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| 96 | struct {
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| 97 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.
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| 98 | UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
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| 99 | UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
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| 100 | UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
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| 101 | UINT32 Reserved0:1; ///< Reserved.
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| 102 | UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
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| 103 | UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
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| 104 | UINT32 Reserved1:2; ///< Reserved.
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| 105 | UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
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| 106 | UINT32 Reserved2:12; ///< Reserved.
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| 107 | } Bits;
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| 108 | UINT32 Uint32;
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| 109 | } LOCAL_APIC_ICR_LOW;
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| 110 |
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| 111 | //
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| 112 | // High half of Interrupt Command Register (ICR)
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| 113 | //
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| 114 | typedef union {
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| 115 | struct {
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| 116 | UINT32 Reserved0:24; ///< Reserved.
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| 117 | UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
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| 118 | } Bits;
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| 119 | UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
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| 120 | } LOCAL_APIC_ICR_HIGH;
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| 121 |
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| 122 | //
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| 123 | // Spurious-Interrupt Vector Register (SVR)
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| 124 | //
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| 125 | typedef union {
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| 126 | struct {
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| 127 | UINT32 SpuriousVector:8; ///< Spurious Vector.
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| 128 | UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
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| 129 | UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
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| 130 | UINT32 Reserved0:2; ///< Reserved.
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| 131 | UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
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| 132 | UINT32 Reserved1:19; ///< Reserved.
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| 133 | } Bits;
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| 134 | UINT32 Uint32;
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| 135 | } LOCAL_APIC_SVR;
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| 136 |
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| 137 | //
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| 138 | // Divide Configuration Register (DCR)
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| 139 | //
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| 140 | typedef union {
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| 141 | struct {
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| 142 | UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
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| 143 | UINT32 Reserved0:1; ///< Always 0.
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| 144 | UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
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| 145 | UINT32 Reserved1:28; ///< Reserved.
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| 146 | } Bits;
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| 147 | UINT32 Uint32;
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| 148 | } LOCAL_APIC_DCR;
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| 149 |
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| 150 | //
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| 151 | // LVT Timer Register
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| 152 | //
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| 153 | typedef union {
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| 154 | struct {
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| 155 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.
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| 156 | UINT32 Reserved0:4; ///< Reserved.
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| 157 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
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| 158 | UINT32 Reserved1:3; ///< Reserved.
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| 159 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
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| 160 | UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
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| 161 | UINT32 Reserved2:14; ///< Reserved.
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| 162 | } Bits;
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| 163 | UINT32 Uint32;
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| 164 | } LOCAL_APIC_LVT_TIMER;
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| 165 |
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| 166 | //
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| 167 | // LVT LINT0/LINT1 Register
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| 168 | //
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| 169 | typedef union {
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| 170 | struct {
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| 171 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.
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| 172 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
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| 173 | UINT32 Reserved0:1; ///< Reserved.
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| 174 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
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| 175 | UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
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| 176 | UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
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| 177 | UINT32 TriggerMode:1; ///< 0:edge, 1:level.
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| 178 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
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| 179 | UINT32 Reserved1:15; ///< Reserved.
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| 180 | } Bits;
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| 181 | UINT32 Uint32;
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| 182 | } LOCAL_APIC_LVT_LINT;
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| 183 |
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| 184 | //
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| 185 | // MSI Address Register
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| 186 | //
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| 187 | typedef union {
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| 188 | struct {
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| 189 | UINT32 Reserved0:2; ///< Reserved
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| 190 | UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
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| 191 | UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
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| 192 | UINT32 Reserved1:8; ///< Reserved.
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| 193 | UINT32 DestinationId:8; ///< Specifies the Destination ID.
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| 194 | UINT32 BaseAddress:12; ///< Must be 0FEEH
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| 195 | } Bits;
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| 196 | UINT32 Uint32;
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| 197 | } LOCAL_APIC_MSI_ADDRESS;
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| 198 |
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| 199 | //
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| 200 | // MSI Address Register
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| 201 | //
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| 202 | typedef union {
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| 203 | struct {
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| 204 | UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
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| 205 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
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| 206 | UINT32 Reserved0:3; ///< Reserved.
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| 207 | UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
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| 208 | UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
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| 209 | UINT32 Reserved1:16; ///< Reserved.
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| 210 | UINT32 Reserved2:32; ///< Reserved.
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| 211 | } Bits;
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| 212 | UINT64 Uint64;
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| 213 | } LOCAL_APIC_MSI_DATA;
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| 214 |
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| 215 | #endif
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| 216 |
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