| 1 | ;------------------------------------------------------------------------------ ;
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| 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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| 3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent
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| 4 | ;
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| 5 | ; Module Name:
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| 6 | ;
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| 7 | ; SmmInit.nasm
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| 8 | ;
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| 9 | ; Abstract:
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| 10 | ;
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| 11 | ; Functions for relocating SMBASE's for all processors
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| 12 | ;
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| 13 | ;-------------------------------------------------------------------------------
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| 14 |
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| 15 | %include "StuffRsbNasm.inc"
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| 16 |
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| 17 | extern ASM_PFX(SmmInitHandler)
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| 18 | extern ASM_PFX(mRebasedFlag)
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| 19 | extern ASM_PFX(mSmmRelocationOriginalAddress)
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| 20 |
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| 21 | global ASM_PFX(gPatchSmmCr3)
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| 22 | global ASM_PFX(gPatchSmmCr4)
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| 23 | global ASM_PFX(gPatchSmmCr0)
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| 24 | global ASM_PFX(gPatchSmmInitStack)
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| 25 | global ASM_PFX(gcSmiInitGdtr)
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| 26 | global ASM_PFX(gcSmmInitSize)
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| 27 | global ASM_PFX(gcSmmInitTemplate)
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| 28 | global ASM_PFX(gPatchRebasedFlagAddr32)
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| 29 | global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
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| 30 |
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| 31 | %define LONG_MODE_CS 0x38
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| 32 |
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| 33 | DEFAULT REL
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| 34 | SECTION .text
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| 35 |
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| 36 | ASM_PFX(gcSmiInitGdtr):
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| 37 | DW 0
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| 38 | DQ 0
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| 39 |
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| 40 | global ASM_PFX(SmmStartup)
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| 41 |
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| 42 | BITS 16
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| 43 | ASM_PFX(SmmStartup):
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| 44 | mov eax, 0x80000001 ; read capability
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| 45 | cpuid
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| 46 | mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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| 47 | mov eax, strict dword 0 ; source operand will be patched
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| 48 | ASM_PFX(gPatchSmmCr3):
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| 49 | mov cr3, eax
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| 50 | o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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| 51 | mov eax, strict dword 0 ; source operand will be patched
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| 52 | ASM_PFX(gPatchSmmCr4):
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| 53 | or ah, 2 ; enable XMM registers access
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| 54 | mov cr4, eax
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| 55 | mov ecx, 0xc0000080 ; IA32_EFER MSR
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| 56 | rdmsr
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| 57 | or ah, BIT0 ; set LME bit
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| 58 | test ebx, BIT20 ; check NXE capability
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| 59 | jz .1
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| 60 | or ah, BIT3 ; set NXE bit
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| 61 | .1:
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| 62 | wrmsr
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| 63 | mov eax, strict dword 0 ; source operand will be patched
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| 64 | ASM_PFX(gPatchSmmCr0):
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| 65 | mov cr0, eax ; enable protected mode & paging
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| 66 | jmp LONG_MODE_CS : dword 0 ; offset will be patched to @LongMode
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| 67 | @PatchLongModeOffset:
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| 68 |
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| 69 | BITS 64
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| 70 | @LongMode: ; long-mode starts here
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| 71 | mov rsp, strict qword 0 ; source operand will be patched
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| 72 | ASM_PFX(gPatchSmmInitStack):
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| 73 | and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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| 74 | ;
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| 75 | ; According to X64 calling convention, XMM0~5 are volatile, we need to save
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| 76 | ; them before calling C-function.
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| 77 | ;
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| 78 | sub rsp, 0x60
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| 79 | movdqa [rsp], xmm0
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| 80 | movdqa [rsp + 0x10], xmm1
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| 81 | movdqa [rsp + 0x20], xmm2
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| 82 | movdqa [rsp + 0x30], xmm3
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| 83 | movdqa [rsp + 0x40], xmm4
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| 84 | movdqa [rsp + 0x50], xmm5
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| 85 |
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| 86 | add rsp, -0x20
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| 87 | call ASM_PFX(SmmInitHandler)
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| 88 | add rsp, 0x20
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| 89 |
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| 90 | ;
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| 91 | ; Restore XMM0~5 after calling C-function.
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| 92 | ;
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| 93 | movdqa xmm0, [rsp]
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| 94 | movdqa xmm1, [rsp + 0x10]
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| 95 | movdqa xmm2, [rsp + 0x20]
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| 96 | movdqa xmm3, [rsp + 0x30]
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| 97 | movdqa xmm4, [rsp + 0x40]
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| 98 | movdqa xmm5, [rsp + 0x50]
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| 99 |
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| 100 | StuffRsb64
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| 101 | rsm
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| 102 |
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| 103 | BITS 16
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| 104 | ASM_PFX(gcSmmInitTemplate):
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| 105 | mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
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| 106 | sub ebp, 0x30000
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| 107 | jmp ebp
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| 108 | @L1:
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| 109 | DQ 0; ASM_PFX(SmmStartup)
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| 110 |
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| 111 | ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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| 112 |
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| 113 | BITS 64
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| 114 | global ASM_PFX(SmmRelocationSemaphoreComplete)
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| 115 | ASM_PFX(SmmRelocationSemaphoreComplete):
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| 116 | push rax
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| 117 | mov rax, [ASM_PFX(mRebasedFlag)]
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| 118 | mov byte [rax], 1
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| 119 | pop rax
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| 120 | jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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| 121 |
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| 122 | ;
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| 123 | ; Semaphore code running in 32-bit mode
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| 124 | ;
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| 125 | BITS 32
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| 126 | global ASM_PFX(SmmRelocationSemaphoreComplete32)
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| 127 | ASM_PFX(SmmRelocationSemaphoreComplete32):
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| 128 | push eax
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| 129 | mov eax, strict dword 0 ; source operand will be patched
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| 130 | ASM_PFX(gPatchRebasedFlagAddr32):
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| 131 | mov byte [eax], 1
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| 132 | pop eax
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| 133 | jmp dword [dword 0] ; destination will be patched
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| 134 | ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
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| 135 |
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| 136 | BITS 64
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| 137 | global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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| 138 | ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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| 139 | lea rax, [@LongMode]
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| 140 | lea rcx, [@PatchLongModeOffset - 6]
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| 141 | mov dword [rcx], eax
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| 142 |
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| 143 | lea rax, [ASM_PFX(SmmStartup)]
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| 144 | lea rcx, [@L1]
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| 145 | mov qword [rcx], rax
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| 146 | ret
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