| 1 | /** @file
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| 2 |
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| 3 | E1000 hardware interface definitions.
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| 4 |
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| 5 | Copyright (c) 2021-2024, Oracle and/or its affiliates.<BR>
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| 6 |
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| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 8 | **/
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| 9 |
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| 10 | #ifndef _E1K_NET_HW_H_
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| 11 | #define _E1K_NET_HW_H_
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| 12 |
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| 13 | #define INTEL_PCI_VENDOR_ID 0x8086
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| 14 | #define INTEL_82540EM_PCI_DEVICE_ID 0x100e
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| 15 | #define INTEL_82543GC_PCI_DEVICE_ID 0x1004
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| 16 | #define INTEL_82545EM_PCI_DEVICE_ID 0x100f
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| 17 |
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| 18 | //
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| 19 | // Receive descriptor.
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| 20 | //
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| 21 | typedef struct {
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| 22 | UINT32 AddrBufferLow;
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| 23 | UINT32 AddrBufferHigh;
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| 24 | UINT16 BufferLength;
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| 25 | UINT16 Checksum;
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| 26 | UINT8 Status;
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| 27 | UINT8 Errors;
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| 28 | UINT16 Special;
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| 29 | } E1K_RX_DESC;
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| 30 |
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| 31 | #define E1K_RX_STATUS_DONE BIT0
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| 32 | #define E1K_RX_STATUS_EOP BIT1
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| 33 |
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| 34 | #define E1K_RX_ERROR_CE BIT0
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| 35 | #define E1K_RX_ERROR_SEQ BIT2
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| 36 | #define E1K_RX_ERROR_CXE BIT4
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| 37 | #define E1K_RX_ERROR_RXE BIT7
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| 38 |
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| 39 | //
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| 40 | // Transmit descriptor.
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| 41 | //
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| 42 | typedef struct {
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| 43 | UINT32 AddrBufferLow;
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| 44 | UINT32 AddrBufferHigh;
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| 45 | UINT16 BufferLength;
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| 46 | UINT8 ChecksumOffset;
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| 47 | UINT8 Command;
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| 48 | UINT8 Status;
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| 49 | UINT8 ChecksumStart;
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| 50 | UINT16 Special;
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| 51 | } E1K_TX_DESC;
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| 52 |
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| 53 | #define E1K_TX_CMD_EOP BIT0
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| 54 | #define E1K_TX_CMD_FCS BIT1
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| 55 | #define E1K_TX_CMD_RS BIT3
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| 56 |
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| 57 | #define E1K_REG_CTRL 0x00000000
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| 58 | # define E1K_REG_CTRL_ASDE BIT5
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| 59 | # define E1K_REG_CTRL_SLU BIT6
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| 60 | # define E1K_REG_CTRL_RST BIT26
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| 61 | # define E1K_REG_CTRL_PHY_RST BIT31
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| 62 | #define E1K_REG_STATUS 0x00000008
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| 63 | # define E1K_REG_STATUS_LU BIT1
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| 64 | #define E1K_REG_EECD 0x00000010
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| 65 | #define E1K_REG_EERD 0x00000014
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| 66 | # define E1K_REG_EERD_START BIT0
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| 67 | # define E1K_REG_EERD_DONE BIT4
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| 68 | # define E1K_REG_EERD_DATA_GET(x) (((x) >> 16) & 0xffff)
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| 69 | #define E1K_REG_ICR 0x000000c0
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| 70 | #define E1K_REG_ITR 0x000000c4
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| 71 | #define E1K_REG_ICS 0x000000c8
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| 72 | #define E1K_REG_IMS 0x000000d0
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| 73 | #define E1K_REG_IMC 0x000000d8
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| 74 | #define E1K_REG_RCTL 0x00000100
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| 75 | # define E1K_REG_RCTL_EN BIT1
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| 76 | # define E1K_REG_RCTL_MPE BIT4
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| 77 | # define E1K_REG_RCTL_BSIZE_MASK 0x00030000
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| 78 | #define E1K_REG_RDBAL 0x00002800
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| 79 | #define E1K_REG_RDBAH 0x00002804
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| 80 | #define E1K_REG_RDLEN 0x00002808
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| 81 | #define E1K_REG_RDH 0x00002810
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| 82 | #define E1K_REG_RDT 0x00002818
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| 83 | #define E1K_REG_RDTR 0x00002820
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| 84 | #define E1K_REG_TCTL 0x00000400
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| 85 | # define E1K_REG_TCTL_EN BIT1
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| 86 | # define E1K_REG_TCTL_PSP BIT3
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| 87 | #define E1K_REG_TIPG 0x00000410
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| 88 | #define E1K_REG_TDBAL 0x00003800
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| 89 | #define E1K_REG_TDBAH 0x00003804
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| 90 | #define E1K_REG_TDLEN 0x00003808
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| 91 | #define E1K_REG_TDH 0x00003810
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| 92 | #define E1K_REG_TDT 0x00003818
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| 93 | #define E1K_REG_RAL 0x00005400
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| 94 | #define E1K_REG_RAH 0x00005404
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| 95 | # define E1K_REG_RAH_AV BIT31
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| 96 |
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| 97 | //
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| 98 | // MAC address.
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| 99 | //
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| 100 | typedef struct
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| 101 | {
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| 102 | UINT8 Mac[6];
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| 103 | } E1K_NET_MAC;
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| 104 |
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| 105 | #endif // _E1K_NET_HW_H_
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