ArmNameSpaceObjects.h@ 109193

Last change on this file since 109193 was 108794, checked in by vboxsync, 7 weeks ago
Devices/EFI/FirmwareNew: Merge edk2-stable202502 from the vendor branch and make it build for the important platforms, bugref:4643
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1	/** @file
2
3	Copyright (c) 2017 - 2024, Arm Limited. All rights reserved.<BR>
4
5	SPDX-License-Identifier: BSD-2-Clause-Patent
6
7	@par Glossary:
8	- Cm or CM - Configuration Manager
9	- Obj or OBJ - Object
10	- Std or STD - Standard
11	**/
12
13	#ifndef ARM_NAMESPACE_OBJECTS_H_
14	#define ARM_NAMESPACE_OBJECTS_H_
15
16	#include <AcpiObjects.h>
17	#include <StandardNameSpaceObjects.h>
18
19	#pragma pack(1)
20
21	/** The EARM_OBJECT_ID enum describes the Object IDs
22	in the ARM Namespace
23
24	Note: Whenever an entry in this enum is updated,
25	the following data structures must also be
26	updated:
27	- CM_OBJECT_TOKEN_FIXER TokenFixer[] in
28	Library\Common\DynamicPlatRepoLib\CmObjectTokenFixer.c
29	*/
30	typedef enum ArmObjectID {
31	EArmObjReserved, ///< 0 - Reserved
32	EArmObjBootArchInfo, ///< 1 - Boot Architecture Info
33	EArmObjGicCInfo, ///< 2 - GIC CPU Interface Info
34	EArmObjGicDInfo, ///< 3 - GIC Distributor Info
35	EArmObjGicMsiFrameInfo, ///< 4 - GIC MSI Frame Info
36	EArmObjGicRedistributorInfo, ///< 5 - GIC Redistributor Info
37	EArmObjGicItsInfo, ///< 6 - GIC ITS Info
38	EArmObjGenericTimerInfo, ///< 7 - Generic Timer Info
39	EArmObjPlatformGTBlockInfo, ///< 8 - Platform GT Block Info
40	EArmObjGTBlockTimerFrameInfo, ///< 9 - Generic Timer Block Frame Info
41	EArmObjPlatformGenericWatchdogInfo, ///< 10 - Platform Generic Watchdog
42	EArmObjItsGroup, ///< 11 - ITS Group
43	EArmObjNamedComponent, ///< 12 - Named Component
44	EArmObjRootComplex, ///< 13 - Root Complex
45	EArmObjSmmuV1SmmuV2, ///< 14 - SMMUv1 or SMMUv2
46	EArmObjSmmuV3, ///< 15 - SMMUv3
47	EArmObjPmcg, ///< 16 - PMCG
48	EArmObjGicItsIdentifierArray, ///< 17 - GIC ITS Identifier Array
49	EArmObjIdMappingArray, ///< 18 - ID Mapping Array
50	EArmObjSmmuInterruptArray, ///< 19 - SMMU Interrupt Array
51	EArmObjCmn600Info, ///< 20 - CMN-600 Info
52	EArmObjRmr, ///< 21 - Reserved Memory Range Node
53	EArmObjMemoryRangeDescriptor, ///< 22 - Memory Range Descriptor
54	EArmObjEtInfo, ///< 23 - Embedded Trace Extension/Module Info
55	EArmObjMax
56	} EARM_OBJECT_ID;
57
58	/** A structure that describes the
59	ARM Boot Architecture flags.
60
61	ID: EArmObjBootArchInfo
62	*/
63	typedef struct CmArmBootArchInfo {
64	/** This is the ARM_BOOT_ARCH flags field of the FADT Table
65	described in the ACPI Table Specification.
66	*/
67	UINT16 BootArchFlags;
68	} CM_ARM_BOOT_ARCH_INFO;
69
70	/** A structure that describes the
71	GIC CPU Interface for the Platform.
72
73	ID: EArmObjGicCInfo
74	*/
75	typedef struct CmArmGicCInfo {
76	/// The GIC CPU Interface number.
77	UINT32 CPUInterfaceNumber;
78
79	/** The ACPI Processor UID. This must match the
80	_UID of the CPU Device object information described
81	in the DSDT/SSDT for the CPU.
82	*/
83	UINT32 AcpiProcessorUid;
84
85	/** The flags field as described by the GICC structure
86	in the ACPI Specification.
87	*/
88	UINT32 Flags;
89
90	/** The parking protocol version field as described by
91	the GICC structure in the ACPI Specification.
92	*/
93	UINT32 ParkingProtocolVersion;
94
95	/** The Performance Interrupt field as described by
96	the GICC structure in the ACPI Specification.
97	*/
98	UINT32 PerformanceInterruptGsiv;
99
100	/** The CPU Parked address field as described by
101	the GICC structure in the ACPI Specification.
102	*/
103	UINT64 ParkedAddress;
104
105	/** The base address for the GIC CPU Interface
106	as described by the GICC structure in the
107	ACPI Specification.
108	*/
109	UINT64 PhysicalBaseAddress;
110
111	/** The base address for GICV interface
112	as described by the GICC structure in the
113	ACPI Specification.
114	*/
115	UINT64 GICV;
116
117	/** The base address for GICH interface
118	as described by the GICC structure in the
119	ACPI Specification.
120	*/
121	UINT64 GICH;
122
123	/** The GICV maintenance interrupt
124	as described by the GICC structure in the
125	ACPI Specification.
126	*/
127	UINT32 VGICMaintenanceInterrupt;
128
129	/** The base address for GICR interface
130	as described by the GICC structure in the
131	ACPI Specification.
132	*/
133	UINT64 GICRBaseAddress;
134
135	/** The MPIDR for the CPU
136	as described by the GICC structure in the
137	ACPI Specification.
138	*/
139	UINT64 MPIDR;
140
141	/** The Processor Power Efficiency class
142	as described by the GICC structure in the
143	ACPI Specification.
144	*/
145	UINT8 ProcessorPowerEfficiencyClass;
146
147	/** Statistical Profiling Extension buffer overflow GSIV. Zero if
148	unsupported by this processor. This field was introduced in
149	ACPI 6.3 (MADT revision 5) and is therefore ignored when
150	generating MADT revision 4 or lower.
151	*/
152	UINT16 SpeOverflowInterrupt;
153
154	/** The proximity domain to which the logical processor belongs.
155	This field is used to populate the GICC affinity structure
156	in the SRAT table.
157	*/
158	UINT32 ProximityDomain;
159
160	/** The clock domain to which the logical processor belongs.
161	This field is used to populate the GICC affinity structure
162	in the SRAT table.
163	*/
164	UINT32 ClockDomain;
165
166	/** The GICC Affinity flags field as described by the GICC Affinity structure
167	in the SRAT table.
168	*/
169	UINT32 AffinityFlags;
170
171	/** Optional field: Reference Token for the Cpc info of this processor.
172	i.e. a token referencing a CM_ARCH_COMMON_CPC_INFO object.
173	*/
174	CM_OBJECT_TOKEN CpcToken;
175
176	/** Trace Buffer Extension interrupt GSIV. Zero if
177	unsupported by this processor. This field was introduced in
178	ACPI 6.5 (MADT revision 6) and is therefore ignored when
179	generating MADT revision 5 or lower.
180	*/
181	UINT16 TrbeInterrupt;
182
183	/** Optional field: Reference Token for the Embedded Trace device info for
184	this processing element.
185	i.e. a token referencing a CM_ARM_ET_INFO object.
186	*/
187	CM_OBJECT_TOKEN EtToken;
188
189	/** Optional field: Reference Token for the Psd info of this processor.
190	i.e. a token referencing a CM_ARCH_COMMON_PSD_INFO object.
191	*/
192	CM_OBJECT_TOKEN PsdToken;
193	} CM_ARM_GICC_INFO;
194
195	/** A structure that describes the
196	GIC Distributor information for the Platform.
197
198	ID: EArmObjGicDInfo
199	*/
200	typedef struct CmArmGicDInfo {
201	/// The Physical Base address for the GIC Distributor.
202	UINT64 PhysicalBaseAddress;
203
204	/** The global system interrupt
205	number where this GIC Distributor's
206	interrupt inputs start.
207	*/
208	UINT32 SystemVectorBase;
209
210	/** The GIC version as described
211	by the GICD structure in the
212	ACPI Specification.
213	*/
214	UINT8 GicVersion;
215	} CM_ARM_GICD_INFO;
216
217	/** A structure that describes the
218	GIC MSI Frame information for the Platform.
219
220	ID: EArmObjGicMsiFrameInfo
221	*/
222	typedef struct CmArmGicMsiFrameInfo {
223	/// The GIC MSI Frame ID
224	UINT32 GicMsiFrameId;
225
226	/// The Physical base address for the MSI Frame
227	UINT64 PhysicalBaseAddress;
228
229	/** The GIC MSI Frame flags
230	as described by the GIC MSI frame
231	structure in the ACPI Specification.
232	*/
233	UINT32 Flags;
234
235	/// SPI Count used by this frame
236	UINT16 SPICount;
237
238	/// SPI Base used by this frame
239	UINT16 SPIBase;
240	} CM_ARM_GIC_MSI_FRAME_INFO;
241
242	/** A structure that describes the
243	GIC Redistributor information for the Platform.
244
245	ID: EArmObjGicRedistributorInfo
246	*/
247	typedef struct CmArmGicRedistInfo {
248	/** The physical address of a page range
249	containing all GIC Redistributors.
250	*/
251	UINT64 DiscoveryRangeBaseAddress;
252
253	/// Length of the GIC Redistributor Discovery page range
254	UINT32 DiscoveryRangeLength;
255	} CM_ARM_GIC_REDIST_INFO;
256
257	/** A structure that describes the
258	GIC Interrupt Translation Service information for the Platform.
259
260	ID: EArmObjGicItsInfo
261	*/
262	typedef struct CmArmGicItsInfo {
263	/// The GIC ITS ID
264	UINT32 GicItsId;
265
266	/// The physical address for the Interrupt Translation Service
267	UINT64 PhysicalBaseAddress;
268
269	/** The proximity domain to which the logical processor belongs.
270	This field is used to populate the GIC ITS affinity structure
271	in the SRAT table.
272	*/
273	UINT32 ProximityDomain;
274	} CM_ARM_GIC_ITS_INFO;
275
276	/** A structure that describes the
277	Generic Timer information for the Platform.
278
279	ID: EArmObjGenericTimerInfo
280	*/
281	typedef struct CmArmGenericTimerInfo {
282	/// The physical base address for the counter control frame
283	UINT64 CounterControlBaseAddress;
284
285	/// The physical base address for the counter read frame
286	UINT64 CounterReadBaseAddress;
287
288	/// The secure PL1 timer interrupt
289	UINT32 SecurePL1TimerGSIV;
290
291	/// The secure PL1 timer flags
292	UINT32 SecurePL1TimerFlags;
293
294	/// The non-secure PL1 timer interrupt
295	UINT32 NonSecurePL1TimerGSIV;
296
297	/// The non-secure PL1 timer flags
298	UINT32 NonSecurePL1TimerFlags;
299
300	/// The virtual timer interrupt
301	UINT32 VirtualTimerGSIV;
302
303	/// The virtual timer flags
304	UINT32 VirtualTimerFlags;
305
306	/// The non-secure PL2 timer interrupt
307	UINT32 NonSecurePL2TimerGSIV;
308
309	/// The non-secure PL2 timer flags
310	UINT32 NonSecurePL2TimerFlags;
311
312	/// GSIV for the virtual EL2 timer
313	UINT32 VirtualPL2TimerGSIV;
314
315	/// Flags for the virtual EL2 timer
316	UINT32 VirtualPL2TimerFlags;
317	} CM_ARM_GENERIC_TIMER_INFO;
318
319	/** A structure that describes the
320	Platform Generic Block Timer information for the Platform.
321
322	ID: EArmObjPlatformGTBlockInfo
323	*/
324	typedef struct CmArmGTBlockInfo {
325	/// The physical base address for the GT Block Timer structure
326	UINT64 GTBlockPhysicalAddress;
327
328	/// The number of timer frames implemented in the GT Block
329	UINT32 GTBlockTimerFrameCount;
330
331	/// Reference token for the GT Block timer frame list
332	CM_OBJECT_TOKEN GTBlockTimerFrameToken;
333	} CM_ARM_GTBLOCK_INFO;
334
335	/** A structure that describes the
336	Platform Generic Block Timer Frame information for the Platform.
337
338	ID: EArmObjGTBlockTimerFrameInfo
339	*/
340	typedef struct CmArmGTBlockTimerFrameInfo {
341	/// The Generic Timer frame number
342	UINT8 FrameNumber;
343
344	/// The physical base address for the CntBase block
345	UINT64 PhysicalAddressCntBase;
346
347	/// The physical base address for the CntEL0Base block
348	UINT64 PhysicalAddressCntEL0Base;
349
350	/// The physical timer interrupt
351	UINT32 PhysicalTimerGSIV;
352
353	/** The physical timer flags as described by the GT Block
354	Timer frame Structure in the ACPI Specification.
355	*/
356	UINT32 PhysicalTimerFlags;
357
358	/// The virtual timer interrupt
359	UINT32 VirtualTimerGSIV;
360
361	/** The virtual timer flags as described by the GT Block
362	Timer frame Structure in the ACPI Specification.
363	*/
364	UINT32 VirtualTimerFlags;
365
366	/** The common timer flags as described by the GT Block
367	Timer frame Structure in the ACPI Specification.
368	*/
369	UINT32 CommonFlags;
370	} CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
371
372	/** A structure that describes the
373	Arm Generic Watchdog information for the Platform.
374
375	ID: EArmObjPlatformGenericWatchdogInfo
376	*/
377	typedef struct CmArmGenericWatchdogInfo {
378	/// The physical base address of the Arm Watchdog control frame
379	UINT64 ControlFrameAddress;
380
381	/// The physical base address of the Arm Watchdog refresh frame
382	UINT64 RefreshFrameAddress;
383
384	/// The watchdog interrupt
385	UINT32 TimerGSIV;
386
387	/** The flags for the watchdog as described by the Arm watchdog
388	structure in the ACPI specification.
389	*/
390	UINT32 Flags;
391	} CM_ARM_GENERIC_WATCHDOG_INFO;
392
393	/** A structure that describes the
394	ITS Group node for the Platform.
395
396	ID: EArmObjItsGroup
397	*/
398	typedef struct CmArmItsGroupNode {
399	/// An unique token used to identify this object
400	CM_OBJECT_TOKEN Token;
401	/// The number of ITS identifiers in the ITS node
402	UINT32 ItsIdCount;
403	/// Reference token for the ITS identifier array
404	CM_OBJECT_TOKEN ItsIdToken;
405
406	/// Unique identifier for this node.
407	UINT32 Identifier;
408	} CM_ARM_ITS_GROUP_NODE;
409
410	/** A structure that describes the
411	Named component node for the Platform.
412
413	ID: EArmObjNamedComponent
414	*/
415	typedef struct CmArmNamedComponentNode {
416	/// An unique token used to identify this object
417	CM_OBJECT_TOKEN Token;
418	/// Number of ID mappings
419	UINT32 IdMappingCount;
420	/// Reference token for the ID mapping array
421	CM_OBJECT_TOKEN IdMappingToken;
422
423	/// Flags for the named component
424	UINT32 Flags;
425
426	/// Memory access properties : Cache coherent attributes
427	UINT32 CacheCoherent;
428	/// Memory access properties : Allocation hints
429	UINT8 AllocationHints;
430	/// Memory access properties : Memory access flags
431	UINT8 MemoryAccessFlags;
432
433	/// Memory access properties : Address size limit
434	UINT8 AddressSizeLimit;
435
436	/** ASCII Null terminated string with the full path to
437	the entry in the namespace for this object.
438	*/
439	CHAR8 *ObjectName;
440
441	/// Unique identifier for this node.
442	UINT32 Identifier;
443	} CM_ARM_NAMED_COMPONENT_NODE;
444
445	/** A structure that describes the
446	Root complex node for the Platform.
447
448	ID: EArmObjRootComplex
449	*/
450	typedef struct CmArmRootComplexNode {
451	/// An unique token used to identify this object
452	CM_OBJECT_TOKEN Token;
453	/// Number of ID mappings
454	UINT32 IdMappingCount;
455	/// Reference token for the ID mapping array
456	CM_OBJECT_TOKEN IdMappingToken;
457
458	/// Memory access properties : Cache coherent attributes
459	UINT32 CacheCoherent;
460	/// Memory access properties : Allocation hints
461	UINT8 AllocationHints;
462	/// Memory access properties : Memory access flags
463	UINT8 MemoryAccessFlags;
464
465	/// ATS attributes
466	UINT32 AtsAttribute;
467	/// PCI segment number
468	UINT32 PciSegmentNumber;
469	/// Memory address size limit
470	UINT8 MemoryAddressSize;
471	/// PASID capabilities
472	UINT16 PasidCapabilities;
473	/// Flags
474	UINT32 Flags;
475
476	/// Unique identifier for this node.
477	UINT32 Identifier;
478	} CM_ARM_ROOT_COMPLEX_NODE;
479
480	/** A structure that describes the
481	SMMUv1 or SMMUv2 node for the Platform.
482
483	ID: EArmObjSmmuV1SmmuV2
484	*/
485	typedef struct CmArmSmmuV1SmmuV2Node {
486	/// An unique token used to identify this object
487	CM_OBJECT_TOKEN Token;
488	/// Number of ID mappings
489	UINT32 IdMappingCount;
490	/// Reference token for the ID mapping array
491	CM_OBJECT_TOKEN IdMappingToken;
492
493	/// SMMU Base Address
494	UINT64 BaseAddress;
495	/// Length of the memory range covered by the SMMU
496	UINT64 Span;
497	/// SMMU Model
498	UINT32 Model;
499	/// SMMU flags
500	UINT32 Flags;
501
502	/// Number of context interrupts
503	UINT32 ContextInterruptCount;
504	/// Reference token for the context interrupt array
505	CM_OBJECT_TOKEN ContextInterruptToken;
506
507	/// Number of PMU interrupts
508	UINT32 PmuInterruptCount;
509	/// Reference token for the PMU interrupt array
510	CM_OBJECT_TOKEN PmuInterruptToken;
511
512	/// GSIV of the SMMU_NSgIrpt interrupt
513	UINT32 SMMU_NSgIrpt;
514	/// SMMU_NSgIrpt interrupt flags
515	UINT32 SMMU_NSgIrptFlags;
516	/// GSIV of the SMMU_NSgCfgIrpt interrupt
517	UINT32 SMMU_NSgCfgIrpt;
518	/// SMMU_NSgCfgIrpt interrupt flags
519	UINT32 SMMU_NSgCfgIrptFlags;
520
521	/// Unique identifier for this node.
522	UINT32 Identifier;
523	} CM_ARM_SMMUV1_SMMUV2_NODE;
524
525	/** A structure that describes the
526	SMMUv3 node for the Platform.
527
528	ID: EArmObjSmmuV3
529	*/
530	typedef struct CmArmSmmuV3Node {
531	/// An unique token used to identify this object
532	CM_OBJECT_TOKEN Token;
533	/// Number of ID mappings
534	UINT32 IdMappingCount;
535	/// Reference token for the ID mapping array
536	CM_OBJECT_TOKEN IdMappingToken;
537
538	/// SMMU Base Address
539	UINT64 BaseAddress;
540	/// SMMU flags
541	UINT32 Flags;
542	/// VATOS address
543	UINT64 VatosAddress;
544	/// Model
545	UINT32 Model;
546	/// GSIV of the Event interrupt if SPI based
547	UINT32 EventInterrupt;
548	/// PRI Interrupt if SPI based
549	UINT32 PriInterrupt;
550	/// GERR interrupt if GSIV based
551	UINT32 GerrInterrupt;
552	/// Sync interrupt if GSIV based
553	UINT32 SyncInterrupt;
554
555	/// Proximity domain flag
556	UINT32 ProximityDomain;
557	/// Index into the array of ID mapping
558	UINT32 DeviceIdMappingIndex;
559
560	/// Unique identifier for this node.
561	UINT32 Identifier;
562	} CM_ARM_SMMUV3_NODE;
563
564	/** A structure that describes the
565	PMCG node for the Platform.
566
567	ID: EArmObjPmcg
568	*/
569	typedef struct CmArmPmcgNode {
570	/// An unique token used to identify this object
571	CM_OBJECT_TOKEN Token;
572	/// Number of ID mappings
573	UINT32 IdMappingCount;
574	/// Reference token for the ID mapping array
575	CM_OBJECT_TOKEN IdMappingToken;
576
577	/// Base Address for performance monitor counter group
578	UINT64 BaseAddress;
579	/// GSIV for the Overflow interrupt
580	UINT32 OverflowInterrupt;
581	/// Page 1 Base address
582	UINT64 Page1BaseAddress;
583
584	/// Reference token for the IORT node associated with this node
585	CM_OBJECT_TOKEN ReferenceToken;
586
587	/// Unique identifier for this node.
588	UINT32 Identifier;
589	} CM_ARM_PMCG_NODE;
590
591	/** A structure that describes the
592	GIC ITS Identifiers for an ITS Group node.
593
594	ID: EArmObjGicItsIdentifierArray
595	*/
596	typedef struct CmArmGicItsIdentifier {
597	/// The ITS Identifier
598	UINT32 ItsId;
599	} CM_ARM_ITS_IDENTIFIER;
600
601	/** A structure that describes the
602	ID Mappings for the Platform.
603
604	ID: EArmObjIdMappingArray
605	*/
606	typedef struct CmArmIdMapping {
607	/// Input base
608	UINT32 InputBase;
609	/// Number of input IDs
610	UINT32 NumIds;
611	/// Output Base
612	UINT32 OutputBase;
613	/// Reference token for the output node
614	CM_OBJECT_TOKEN OutputReferenceToken;
615	/// Flags
616	UINT32 Flags;
617	} CM_ARM_ID_MAPPING;
618
619	/** A structure that describes the SMMU interrupts for the Platform.
620
621	Interrupt Interrupt number.
622	Flags Interrupt flags as defined for SMMU node.
623
624	ID: EArmObjSmmuInterruptArray
625	*/
626	typedef CM_ARCH_COMMON_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
627
628	/** A structure that describes the AML Extended Interrupts.
629
630	Interrupt Interrupt number.
631	Flags Interrupt flags as defined by the Interrupt
632	Vector Flags (Byte 3) of the Extended Interrupt
633	resource descriptor.
634	See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
635	*/
636	typedef CM_ARCH_COMMON_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
637
638	/** A structure that describes the CMN-600 hardware.
639
640	ID: EArmObjCmn600Info
641	*/
642	typedef struct CmArmCmn600Info {
643	/// The PERIPHBASE address.
644	/// Corresponds to the Configuration Node Region (CFGR) base address.
645	UINT64 PeriphBaseAddress;
646
647	/// The PERIPHBASE address length.
648	/// Corresponds to the CFGR base address length.
649	UINT64 PeriphBaseAddressLength;
650
651	/// The ROOTNODEBASE address.
652	/// Corresponds to the Root node (ROOT) base address.
653	UINT64 RootNodeBaseAddress;
654
655	/// The Debug and Trace Logic Controller (DTC) count.
656	/// CMN-600 can have maximum 4 DTCs.
657	UINT8 DtcCount;
658
659	/// DTC Interrupt list.
660	/// The first interrupt resource descriptor pertains to
661	/// DTC[0], the second to DTC[1] and so on.
662	/// DtcCount determines the number of DTC Interrupts that
663	/// are populated. If DTC count is 2 then DtcInterrupt[2]
664	/// and DtcInterrupt[3] are ignored.
665	/// Note: The size of CM_ARM_CMN_600_INFO structure remains
666	/// constant and does not vary with the DTC count.
667	CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
668	} CM_ARM_CMN_600_INFO;
669
670	/** A structure that describes the
671	RMR node for the Platform.
672
673	ID: EArmObjRmr
674	*/
675	typedef struct CmArmRmrNode {
676	/// An unique token used to identify this object
677	CM_OBJECT_TOKEN Token;
678	/// Number of ID mappings
679	UINT32 IdMappingCount;
680	/// Reference token for the ID mapping array
681	CM_OBJECT_TOKEN IdMappingToken;
682
683	/// Unique identifier for this node.
684	UINT32 Identifier;
685
686	/// Reserved Memory Range flags.
687	UINT32 Flags;
688
689	/// Memory range descriptor count.
690	UINT32 MemRangeDescCount;
691	/// Reference token for the Memory Range descriptor array
692	CM_OBJECT_TOKEN MemRangeDescToken;
693	} CM_ARM_RMR_NODE;
694
695	/** A structure that describes the
696	Memory Range descriptor.
697
698	ID: EArmObjMemoryRangeDescriptor
699	*/
700	typedef struct CmArmRmrDescriptor {
701	/// Base address of Reserved Memory Range,
702	/// aligned to a page size of 64K.
703	UINT64 BaseAddress;
704
705	/// Length of the Reserved Memory range.
706	/// Must be a multiple of the page size of 64K.
707	UINT64 Length;
708	} CM_ARM_MEMORY_RANGE_DESCRIPTOR;
709
710	/** An enum describing the Arm Embedded Trace device type.
711	*/
712	typedef enum ArmEtType {
713	ArmEtTypeEtm, ///< Embedded Trace module.
714	ArmEtTypeEte, ///< Embedded Trace Extension.
715	ArmEtTypeMax
716	} ARM_ET_TYPE;
717
718	/** A structure that describes the Embedded Trace Extension/Module.
719
720	ID: EArmObjEtInfo
721	*/
722	typedef struct CmArmEtInfo {
723	ARM_ET_TYPE EtType;
724	} CM_ARM_ET_INFO;
725
726	#pragma pack()
727
728	#endif // ARM_NAMESPACE_OBJECTS_H_

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