| 1 | /** @file
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| 2 | This driver installs Single Segment Pci Configuration 2 PPI
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| 3 | to provide read, write and modify access to Pci configuration space in PEI phase.
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| 4 | To follow PI specification, these services also support access to the unaligned Pci address.
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| 5 |
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| 6 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 8 |
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| 9 | **/
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| 10 |
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| 11 | #include <PiPei.h>
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| 12 | #include <Ppi/PciCfg2.h>
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| 13 | #include <Library/BaseLib.h>
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| 14 | #include <Library/DebugLib.h>
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| 15 | #include <Library/PciLib.h>
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| 16 | #include <Library/PeimEntryPoint.h>
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| 17 | #include <Library/PeiServicesLib.h>
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| 18 | #include <IndustryStandard/Pci.h>
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| 19 |
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| 20 | /**
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| 21 | Convert EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS to PCI_LIB_ADDRESS.
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| 22 |
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| 23 | @param Address PCI address with EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS format.
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| 24 |
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| 25 | @return PCI address with PCI_LIB_ADDRESS format.
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| 26 |
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| 27 | **/
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| 28 | UINTN
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| 29 | PciCfgAddressConvert (
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| 30 | EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *Address
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| 31 | )
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| 32 | {
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| 33 | if (Address->ExtendedRegister == 0) {
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| 34 | return PCI_LIB_ADDRESS (Address->Bus, Address->Device, Address->Function, Address->Register);
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| 35 | }
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| 36 |
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| 37 | return PCI_LIB_ADDRESS (Address->Bus, Address->Device, Address->Function, Address->ExtendedRegister);
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| 38 | }
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| 39 |
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| 40 | /**
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| 41 | Reads from a given location in the PCI configuration space.
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| 42 |
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| 43 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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| 44 | @param This Pointer to local data for the interface.
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| 45 | @param Width The width of the access. Enumerated in bytes.
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| 46 | See EFI_PEI_PCI_CFG_PPI_WIDTH above.
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| 47 | @param Address The physical address of the access. The format of
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| 48 | the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
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| 49 | @param Buffer A pointer to the buffer of data.
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| 50 |
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| 51 | @retval EFI_SUCCESS The function completed successfully.
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| 52 | @retval EFI_INVALID_PARAMETER The invalid access width.
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| 53 |
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| 54 | **/
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| 55 | EFI_STATUS
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| 56 | EFIAPI
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| 57 | PciCfg2Read (
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| 58 | IN CONST EFI_PEI_SERVICES **PeiServices,
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| 59 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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| 60 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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| 61 | IN UINT64 Address,
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| 62 | IN OUT VOID *Buffer
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| 63 | )
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| 64 | {
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| 65 | UINTN PciLibAddress;
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| 66 |
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| 67 | PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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| 68 |
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| 69 | if (Width == EfiPeiPciCfgWidthUint8) {
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| 70 | *((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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| 71 | } else if (Width == EfiPeiPciCfgWidthUint16) {
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| 72 | if ((PciLibAddress & 0x01) == 0) {
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| 73 | //
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| 74 | // Aligned Pci address access
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| 75 | //
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| 76 | WriteUnaligned16 (((UINT16 *) Buffer), PciRead16 (PciLibAddress));
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| 77 | } else {
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| 78 | //
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| 79 | // Unaligned Pci address access, break up the request into byte by byte.
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| 80 | //
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| 81 | *((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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| 82 | *((UINT8 *) Buffer + 1) = PciRead8 (PciLibAddress + 1);
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| 83 | }
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| 84 | } else if (Width == EfiPeiPciCfgWidthUint32) {
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| 85 | if ((PciLibAddress & 0x03) == 0) {
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| 86 | //
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| 87 | // Aligned Pci address access
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| 88 | //
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| 89 | WriteUnaligned32 (((UINT32 *) Buffer), PciRead32 (PciLibAddress));
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| 90 | } else if ((PciLibAddress & 0x01) == 0) {
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| 91 | //
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| 92 | // Unaligned Pci address access, break up the request into word by word.
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| 93 | //
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| 94 | WriteUnaligned16 (((UINT16 *) Buffer), PciRead16 (PciLibAddress));
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| 95 | WriteUnaligned16 (((UINT16 *) Buffer + 1), PciRead16 (PciLibAddress + 2));
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| 96 | } else {
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| 97 | //
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| 98 | // Unaligned Pci address access, break up the request into byte by byte.
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| 99 | //
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| 100 | *((UINT8 *) Buffer) = PciRead8 (PciLibAddress);
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| 101 | *((UINT8 *) Buffer + 1) = PciRead8 (PciLibAddress + 1);
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| 102 | *((UINT8 *) Buffer + 2) = PciRead8 (PciLibAddress + 2);
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| 103 | *((UINT8 *) Buffer + 3) = PciRead8 (PciLibAddress + 3);
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| 104 | }
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| 105 | } else {
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| 106 | return EFI_INVALID_PARAMETER;
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| 107 | }
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| 108 |
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| 109 | return EFI_SUCCESS;
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| 110 | }
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| 111 |
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| 112 | /**
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| 113 | Write to a given location in the PCI configuration space.
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| 114 |
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| 115 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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| 116 | @param This Pointer to local data for the interface.
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| 117 | @param Width The width of the access. Enumerated in bytes.
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| 118 | See EFI_PEI_PCI_CFG_PPI_WIDTH above.
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| 119 | @param Address The physical address of the access. The format of
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| 120 | the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
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| 121 | @param Buffer A pointer to the buffer of data.
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| 122 |
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| 123 | @retval EFI_SUCCESS The function completed successfully.
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| 124 | @retval EFI_INVALID_PARAMETER The invalid access width.
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| 125 |
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| 126 | **/
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| 127 | EFI_STATUS
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| 128 | EFIAPI
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| 129 | PciCfg2Write (
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| 130 | IN CONST EFI_PEI_SERVICES **PeiServices,
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| 131 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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| 132 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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| 133 | IN UINT64 Address,
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| 134 | IN OUT VOID *Buffer
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| 135 | )
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| 136 | {
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| 137 | UINTN PciLibAddress;
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| 138 |
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| 139 | PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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| 140 |
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| 141 | if (Width == EfiPeiPciCfgWidthUint8) {
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| 142 | PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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| 143 | } else if (Width == EfiPeiPciCfgWidthUint16) {
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| 144 | if ((PciLibAddress & 0x01) == 0) {
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| 145 | //
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| 146 | // Aligned Pci address access
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| 147 | //
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| 148 | PciWrite16 (PciLibAddress, ReadUnaligned16 ((UINT16 *) Buffer));
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| 149 | } else {
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| 150 | //
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| 151 | // Unaligned Pci address access, break up the request into byte by byte.
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| 152 | //
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| 153 | PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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| 154 | PciWrite8 (PciLibAddress + 1, *((UINT8 *) Buffer + 1));
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| 155 | }
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| 156 | } else if (Width == EfiPeiPciCfgWidthUint32) {
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| 157 | if ((PciLibAddress & 0x03) == 0) {
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| 158 | //
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| 159 | // Aligned Pci address access
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| 160 | //
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| 161 | PciWrite32 (PciLibAddress, ReadUnaligned32 ((UINT32 *) Buffer));
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| 162 | } else if ((PciLibAddress & 0x01) == 0) {
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| 163 | //
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| 164 | // Unaligned Pci address access, break up the request into word by word.
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| 165 | //
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| 166 | PciWrite16 (PciLibAddress, ReadUnaligned16 ((UINT16 *) Buffer));
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| 167 | PciWrite16 (PciLibAddress + 2, ReadUnaligned16 ((UINT16 *) Buffer + 1));
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| 168 | } else {
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| 169 | //
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| 170 | // Unaligned Pci address access, break up the request into byte by byte.
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| 171 | //
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| 172 | PciWrite8 (PciLibAddress, *((UINT8 *) Buffer));
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| 173 | PciWrite8 (PciLibAddress + 1, *((UINT8 *) Buffer + 1));
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| 174 | PciWrite8 (PciLibAddress + 2, *((UINT8 *) Buffer + 2));
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| 175 | PciWrite8 (PciLibAddress + 3, *((UINT8 *) Buffer + 3));
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| 176 | }
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| 177 | } else {
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| 178 | return EFI_INVALID_PARAMETER;
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| 179 | }
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| 180 |
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| 181 | return EFI_SUCCESS;
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| 182 | }
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| 183 |
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| 184 |
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| 185 | /**
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| 186 | This function performs a read-modify-write operation on the contents from a given
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| 187 | location in the PCI configuration space.
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| 188 |
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| 189 | @param PeiServices An indirect pointer to the PEI Services Table
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| 190 | published by the PEI Foundation.
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| 191 | @param This Pointer to local data for the interface.
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| 192 | @param Width The width of the access. Enumerated in bytes. Type
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| 193 | EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
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| 194 | @param Address The physical address of the access.
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| 195 | @param SetBits Points to value to bitwise-OR with the read configuration value.
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| 196 | The size of the value is determined by Width.
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| 197 | @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
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| 198 | The size of the value is determined by Width.
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| 199 |
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| 200 | @retval EFI_SUCCESS The function completed successfully.
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| 201 | @retval EFI_INVALID_PARAMETER The invalid access width.
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| 202 |
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| 203 | **/
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| 204 | EFI_STATUS
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| 205 | EFIAPI
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| 206 | PciCfg2Modify (
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| 207 | IN CONST EFI_PEI_SERVICES **PeiServices,
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| 208 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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| 209 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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| 210 | IN UINT64 Address,
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| 211 | IN VOID *SetBits,
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| 212 | IN VOID *ClearBits
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| 213 | )
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| 214 | {
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| 215 | UINTN PciLibAddress;
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| 216 | UINT16 ClearValue16;
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| 217 | UINT16 SetValue16;
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| 218 | UINT32 ClearValue32;
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| 219 | UINT32 SetValue32;
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| 220 |
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| 221 | PciLibAddress = PciCfgAddressConvert ((EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS *) &Address);
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| 222 |
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| 223 | if (Width == EfiPeiPciCfgWidthUint8) {
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| 224 | PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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| 225 | } else if (Width == EfiPeiPciCfgWidthUint16) {
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| 226 | if ((PciLibAddress & 0x01) == 0) {
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| 227 | //
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| 228 | // Aligned Pci address access
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| 229 | //
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| 230 | ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits));
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| 231 | SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits);
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| 232 | PciAndThenOr16 (PciLibAddress, ClearValue16, SetValue16);
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| 233 | } else {
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| 234 | //
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| 235 | // Unaligned Pci address access, break up the request into byte by byte.
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| 236 | //
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| 237 | PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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| 238 | PciAndThenOr8 (PciLibAddress + 1, (UINT8) (~(*((UINT8 *) ClearBits + 1))), *((UINT8 *) SetBits + 1));
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| 239 | }
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| 240 | } else if (Width == EfiPeiPciCfgWidthUint32) {
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| 241 | if ((PciLibAddress & 0x03) == 0) {
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| 242 | //
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| 243 | // Aligned Pci address access
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| 244 | //
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| 245 | ClearValue32 = (UINT32) (~ReadUnaligned32 ((UINT32 *) ClearBits));
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| 246 | SetValue32 = ReadUnaligned32 ((UINT32 *) SetBits);
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| 247 | PciAndThenOr32 (PciLibAddress, ClearValue32, SetValue32);
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| 248 | } else if ((PciLibAddress & 0x01) == 0) {
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| 249 | //
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| 250 | // Unaligned Pci address access, break up the request into word by word.
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| 251 | //
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| 252 | ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits));
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| 253 | SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits);
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| 254 | PciAndThenOr16 (PciLibAddress, ClearValue16, SetValue16);
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| 255 |
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| 256 | ClearValue16 = (UINT16) (~ReadUnaligned16 ((UINT16 *) ClearBits + 1));
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| 257 | SetValue16 = ReadUnaligned16 ((UINT16 *) SetBits + 1);
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| 258 | PciAndThenOr16 (PciLibAddress + 2, ClearValue16, SetValue16);
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| 259 | } else {
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| 260 | //
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| 261 | // Unaligned Pci address access, break up the request into byte by byte.
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| 262 | //
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| 263 | PciAndThenOr8 (PciLibAddress, (UINT8) (~(*(UINT8 *) ClearBits)), *((UINT8 *) SetBits));
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| 264 | PciAndThenOr8 (PciLibAddress + 1, (UINT8) (~(*((UINT8 *) ClearBits + 1))), *((UINT8 *) SetBits + 1));
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| 265 | PciAndThenOr8 (PciLibAddress + 2, (UINT8) (~(*((UINT8 *) ClearBits + 2))), *((UINT8 *) SetBits + 2));
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| 266 | PciAndThenOr8 (PciLibAddress + 3, (UINT8) (~(*((UINT8 *) ClearBits + 3))), *((UINT8 *) SetBits + 3));
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| 267 | }
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| 268 | } else {
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| 269 | return EFI_INVALID_PARAMETER;
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| 270 | }
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| 271 |
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| 272 | return EFI_SUCCESS;
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| 273 | }
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| 274 |
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| 275 | EFI_PEI_PCI_CFG2_PPI gPciCfg2Ppi = {
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| 276 | PciCfg2Read,
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| 277 | PciCfg2Write,
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| 278 | PciCfg2Modify,
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| 279 | 0
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| 280 | };
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| 281 |
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| 282 | EFI_PEI_PPI_DESCRIPTOR gPciCfg2PpiList = {
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| 283 | (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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| 284 | &gEfiPciCfg2PpiGuid,
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| 285 | &gPciCfg2Ppi
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| 286 | };
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| 287 |
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| 288 | /**
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| 289 | Module's entry function.
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| 290 | This routine will install EFI_PEI_PCI_CFG2_PPI.
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| 291 |
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| 292 | @param FileHandle Handle of the file being invoked.
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| 293 | @param PeiServices Describes the list of possible PEI Services.
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| 294 |
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| 295 | @return Whether success to install service.
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| 296 | **/
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| 297 | EFI_STATUS
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| 298 | EFIAPI
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| 299 | PeimInitializePciCfg (
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| 300 | IN EFI_PEI_FILE_HANDLE FileHandle,
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| 301 | IN CONST EFI_PEI_SERVICES **PeiServices
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| 302 | )
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| 303 | {
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| 304 | EFI_STATUS Status;
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| 305 |
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| 306 | (**(EFI_PEI_SERVICES **)PeiServices).PciCfg = &gPciCfg2Ppi;
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| 307 | Status = PeiServicesInstallPpi (&gPciCfg2PpiList);
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| 308 | ASSERT_EFI_ERROR (Status);
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| 309 |
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| 310 | return Status;
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| 311 | }
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