| 1 | /** @file
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| 2 | ACPI IO Remapping Table (IORT) definitions.
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| 3 |
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| 4 | Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
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| 5 | Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.<BR>
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| 6 |
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| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 8 |
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| 9 | @par Reference(s):
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| 10 | - IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022
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| 11 | (https://developer.arm.com/documentation/den0049/)
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| 12 | - IO Remapping Table, Platform Design Document, Revision E.e, Sept 2022
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| 13 | (https://developer.arm.com/documentation/den0049/)
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| 14 |
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| 15 | @par Glossary:
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| 16 | - Ref : Reference
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| 17 | - Mem : Memory
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| 18 | - Desc : Descriptor
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| 19 | **/
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| 20 |
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| 21 | #ifndef __IO_REMAPPING_TABLE_H__
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| 22 | #define __IO_REMAPPING_TABLE_H__
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| 23 |
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| 24 | #include <IndustryStandard/Acpi.h>
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| 25 |
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| 26 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 0x0
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| 27 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_04 0x4 // Deprecated
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| 28 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_05 0x5
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| 29 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_06 0x6
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| 30 |
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| 31 | #define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0
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| 32 | #define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1
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| 33 | #define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2
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| 34 | #define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3
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| 35 | #define EFI_ACPI_IORT_TYPE_SMMUv3 0x4
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| 36 | #define EFI_ACPI_IORT_TYPE_PMCG 0x5
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| 37 | #define EFI_ACPI_IORT_TYPE_RMR 0x6
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| 38 |
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| 39 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0
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| 40 |
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| 41 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0
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| 42 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1
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| 43 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
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| 44 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
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| 45 |
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| 46 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
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| 47 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
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| 48 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CANWBS BIT2
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| 49 |
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| 50 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
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| 51 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
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| 52 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2
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| 53 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3
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| 54 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4
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| 55 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5
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| 56 |
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| 57 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0
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| 58 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1
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| 59 |
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| 60 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0
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| 61 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
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| 62 |
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| 63 | #define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
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| 64 | #define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1 // HW update of Access Flag supported
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| 65 | #define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE_DS BIT2 // HW update of Access Flag + Dirty Flag supported
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| 66 | #define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
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| 67 | #define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4
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| 68 |
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| 69 | #define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0
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| 70 | #define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1
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| 71 | #define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2
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| 72 |
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| 73 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0
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| 74 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED BIT0
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| 75 |
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| 76 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_UNSUPPORTED 0x0
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| 77 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_SUPPORTED BIT1
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| 78 |
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| 79 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_UNSUPPORTED 0x0
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| 80 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_SUPPORTED BIT2
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| 81 |
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| 82 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_UNSUPPORTED 0x0
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| 83 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_SUPPORTED BIT1
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| 84 |
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| 85 | #define EFI_ACPI_IORT_RMR_REMAP_NOT_PERMITTED 0x0
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| 86 | #define EFI_ACPI_IORT_RMR_REMAP_PERMITTED BIT0
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| 87 |
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| 88 | #define EFI_ACPI_IORT_RMR_ACCESS_REQ_NOT_PRIVILEGED 0x0
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| 89 | #define EFI_ACPI_IORT_RMR_ACCESS_REQ_PRIVILEGED BIT1
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| 90 |
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| 91 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRNE 0x0
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| 92 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRE 0x1
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| 93 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGRE 0x2
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| 94 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_GRE 0x3
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| 95 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_NC_OUT_NC 0x4
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| 96 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_WB_OUT_WB_ISH 0x5
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| 97 |
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| 98 | #define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0
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| 99 |
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| 100 | #define EFI_ACPI_IORT_RMR_NODE_REVISION_02 0x2 // Deprecated
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| 101 |
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| 102 | #pragma pack(1)
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| 103 |
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| 104 | ///
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| 105 | /// Table header
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| 106 | ///
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| 107 | typedef struct {
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| 108 | EFI_ACPI_DESCRIPTION_HEADER Header;
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| 109 | UINT32 NumNodes;
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| 110 | UINT32 NodeOffset;
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| 111 | UINT32 Reserved;
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| 112 | } EFI_ACPI_6_0_IO_REMAPPING_TABLE;
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| 113 |
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| 114 | ///
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| 115 | /// Definition for ID mapping table shared by all node types
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| 116 | ///
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| 117 | typedef struct {
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| 118 | UINT32 InputBase;
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| 119 | UINT32 NumIds;
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| 120 | UINT32 OutputBase;
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| 121 | UINT32 OutputReference;
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| 122 | UINT32 Flags;
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| 123 | } EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
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| 124 |
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| 125 | ///
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| 126 | /// Node header definition shared by all node types
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| 127 | ///
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| 128 | typedef struct {
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| 129 | UINT8 Type;
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| 130 | UINT16 Length;
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| 131 | UINT8 Revision;
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| 132 | UINT32 Identifier;
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| 133 | UINT32 NumIdMappings;
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| 134 | UINT32 IdReference;
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| 135 | } EFI_ACPI_6_0_IO_REMAPPING_NODE;
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| 136 |
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| 137 | ///
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| 138 | /// Node type 0: ITS node
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| 139 | ///
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| 140 | typedef struct {
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| 141 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 142 |
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| 143 | UINT32 NumItsIdentifiers;
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| 144 | // UINT32 ItsIdentifiers[NumItsIdentifiers];
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| 145 | } EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
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| 146 |
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| 147 | ///
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| 148 | /// Node type 1: root complex node
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| 149 | ///
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| 150 | typedef struct {
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| 151 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 152 |
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| 153 | UINT32 CacheCoherent;
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| 154 | UINT8 AllocationHints;
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| 155 | UINT16 Reserved;
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| 156 | UINT8 MemoryAccessFlags;
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| 157 |
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| 158 | UINT32 AtsAttribute;
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| 159 | UINT32 PciSegmentNumber;
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| 160 | UINT8 MemoryAddressSize;
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| 161 | UINT16 PasidCapabilities;
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| 162 | UINT8 Reserved1[1];
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| 163 | UINT32 Flags;
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| 164 | } EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
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| 165 |
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| 166 | ///
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| 167 | /// Node type 2: named component node
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| 168 | ///
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| 169 | typedef struct {
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| 170 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 171 |
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| 172 | UINT32 Flags;
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| 173 | UINT32 CacheCoherent;
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| 174 | UINT8 AllocationHints;
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| 175 | UINT16 Reserved;
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| 176 | UINT8 MemoryAccessFlags;
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| 177 | UINT8 AddressSizeLimit;
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| 178 | // UINT8 ObjectName[];
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| 179 | } EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
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| 180 |
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| 181 | ///
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| 182 | /// Node type 3: SMMUv1 or SMMUv2 node
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| 183 | ///
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| 184 | typedef struct {
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| 185 | UINT32 Interrupt;
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| 186 | UINT32 InterruptFlags;
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| 187 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
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| 188 |
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| 189 | typedef struct {
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| 190 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 191 |
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| 192 | UINT64 Base;
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| 193 | UINT64 Span;
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| 194 | UINT32 Model;
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| 195 | UINT32 Flags;
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| 196 | UINT32 GlobalInterruptArrayRef;
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| 197 | UINT32 NumContextInterrupts;
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| 198 | UINT32 ContextInterruptArrayRef;
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| 199 | UINT32 NumPmuInterrupts;
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| 200 | UINT32 PmuInterruptArrayRef;
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| 201 |
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| 202 | UINT32 SMMU_NSgIrpt;
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| 203 | UINT32 SMMU_NSgIrptFlags;
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| 204 | UINT32 SMMU_NSgCfgIrpt;
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| 205 | UINT32 SMMU_NSgCfgIrptFlags;
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| 206 |
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| 207 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];
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| 208 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];
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| 209 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
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| 210 |
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| 211 | ///
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| 212 | /// Node type 4: SMMUv3 node
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| 213 | ///
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| 214 | typedef struct {
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| 215 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 216 |
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| 217 | UINT64 Base;
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| 218 | UINT32 Flags;
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| 219 | UINT32 Reserved;
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| 220 | UINT64 VatosAddress;
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| 221 | UINT32 Model;
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| 222 | UINT32 Event;
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| 223 | UINT32 Pri;
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| 224 | UINT32 Gerr;
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| 225 | UINT32 Sync;
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| 226 | UINT32 ProximityDomain;
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| 227 | UINT32 DeviceIdMappingIndex;
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| 228 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
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| 229 |
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| 230 | ///
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| 231 | /// Node type 5: PMCG node
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| 232 | ///
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| 233 | typedef struct {
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| 234 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 235 |
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| 236 | UINT64 Base;
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| 237 | UINT32 OverflowInterruptGsiv;
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| 238 | UINT32 NodeReference;
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| 239 | UINT64 Page1Base;
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| 240 | // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];
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| 241 | } EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
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| 242 |
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| 243 | ///
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| 244 | /// Memory Range Descriptor.
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| 245 | ///
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| 246 | typedef struct {
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| 247 | /// Base address of Reserved Memory Range,
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| 248 | /// aligned to a page size of 64K.
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| 249 | UINT64 Base;
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| 250 |
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| 251 | /// Length of the Reserved Memory range.
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| 252 | /// Must be a multiple of the page size of 64K.
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| 253 | UINT64 Length;
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| 254 |
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| 255 | /// Reserved, must be zero.
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| 256 | UINT32 Reserved;
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| 257 | } EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC;
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| 258 |
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| 259 | ///
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| 260 | /// Node type 6: Reserved Memory Range (RMR) node
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| 261 | ///
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| 262 | typedef struct {
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| 263 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
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| 264 |
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| 265 | /// RMR flags
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| 266 | UINT32 Flags;
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| 267 |
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| 268 | /// Memory range descriptor count.
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| 269 | UINT32 NumMemRangeDesc;
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| 270 |
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| 271 | /// Offset of the memory range descriptor array.
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| 272 | UINT32 MemRangeDescRef;
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| 273 | // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE IdMapping[1];
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| 274 | // EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC MemRangeDesc[1];
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| 275 | } EFI_ACPI_6_0_IO_REMAPPING_RMR_NODE;
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| 276 |
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| 277 | #pragma pack()
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| 278 |
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| 279 | #endif
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