| 1 | /** @file
|
|---|
| 2 | Support for the PCI Express 4.0 standard.
|
|---|
| 3 |
|
|---|
| 4 | This header file may not define all structures. Please extend as required.
|
|---|
| 5 |
|
|---|
| 6 | Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
|
|---|
| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent
|
|---|
| 8 |
|
|---|
| 9 | **/
|
|---|
| 10 |
|
|---|
| 11 | #ifndef _PCIEXPRESS40_H_
|
|---|
| 12 | #define _PCIEXPRESS40_H_
|
|---|
| 13 |
|
|---|
| 14 | #include <IndustryStandard/PciExpress31.h>
|
|---|
| 15 |
|
|---|
| 16 | #pragma pack(1)
|
|---|
| 17 |
|
|---|
| 18 | /// The Physical Layer PCI Express Extended Capability definitions.
|
|---|
| 19 | ///
|
|---|
| 20 | /// Based on section 7.7.5 of PCI Express Base Specification 4.0.
|
|---|
| 21 | ///@{
|
|---|
| 22 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026
|
|---|
| 23 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1
|
|---|
| 24 |
|
|---|
| 25 | // Register offsets from Physical Layer PCI-E Ext Cap Header
|
|---|
| 26 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
|
|---|
| 27 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
|
|---|
| 28 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
|
|---|
| 29 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
|
|---|
| 30 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
|
|---|
| 31 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
|
|---|
| 32 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
|
|---|
| 33 |
|
|---|
| 34 | typedef union {
|
|---|
| 35 | struct {
|
|---|
| 36 | UINT32 Reserved : 32; // Reserved bit 0:31
|
|---|
| 37 | } Bits;
|
|---|
| 38 | UINT32 Uint32;
|
|---|
| 39 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
|
|---|
| 40 |
|
|---|
| 41 | typedef union {
|
|---|
| 42 | struct {
|
|---|
| 43 | UINT32 Reserved : 32; // Reserved bit 0:31
|
|---|
| 44 | } Bits;
|
|---|
| 45 | UINT32 Uint32;
|
|---|
| 46 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
|
|---|
| 47 |
|
|---|
| 48 | typedef union {
|
|---|
| 49 | struct {
|
|---|
| 50 | UINT32 EqualizationComplete : 1; // bit 0
|
|---|
| 51 | UINT32 EqualizationPhase1Success : 1; // bit 1
|
|---|
| 52 | UINT32 EqualizationPhase2Success : 1; // bit 2
|
|---|
| 53 | UINT32 EqualizationPhase3Success : 1; // bit 3
|
|---|
| 54 | UINT32 LinkEqualizationRequest : 1; // bit 4
|
|---|
| 55 | UINT32 Reserved : 27; // Reserved bit 5:31
|
|---|
| 56 | } Bits;
|
|---|
| 57 | UINT32 Uint32;
|
|---|
| 58 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
|
|---|
| 59 |
|
|---|
| 60 | typedef union {
|
|---|
| 61 | struct {
|
|---|
| 62 | UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
|
|---|
| 63 | UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
|
|---|
| 64 | } Bits;
|
|---|
| 65 | UINT8 Uint8;
|
|---|
| 66 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
|
|---|
| 67 |
|
|---|
| 68 | typedef struct {
|
|---|
| 69 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
|---|
| 70 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
|
|---|
| 71 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
|
|---|
| 72 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
|
|---|
| 73 | UINT32 LocalDataParityMismatchStatus;
|
|---|
| 74 | UINT32 FirstRetimerDataParityMismatchStatus;
|
|---|
| 75 | UINT32 SecondRetimerDataParityMismatchStatus;
|
|---|
| 76 | UINT32 Reserved;
|
|---|
| 77 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
|
|---|
| 78 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
|
|---|
| 79 | ///@}
|
|---|
| 80 |
|
|---|
| 81 | #pragma pack()
|
|---|
| 82 |
|
|---|
| 83 | #endif
|
|---|
