| 1 | /** @file
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| 2 | Support for the PCI Express 6.0 standard.
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| 3 |
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| 4 | This header file may not define all structures. Please extend as required.
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| 5 |
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| 6 | Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
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| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 8 |
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| 9 | **/
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| 10 |
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| 11 | #ifndef PCIEXPRESS60_H_
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| 12 | #define PCIEXPRESS60_H_
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| 13 |
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| 14 | #include <IndustryStandard/PciExpress50.h>
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| 15 |
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| 16 | /// The Physical Layer PCI Express Extended Capability definitions.
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| 17 | ///
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| 18 | /// Based on section 7.7.7 of PCI Express Base Specification 6.0.
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| 19 | ///@{
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| 20 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
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| 21 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
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| 22 |
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| 23 | // Register offsets from Physical Layer PCI-E Ext Cap Header
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| 24 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
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| 25 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
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| 26 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
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| 27 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
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| 28 |
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| 29 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
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| 30 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
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| 31 |
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| 32 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
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| 33 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
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| 34 | #define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
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| 35 |
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| 36 | #pragma pack(1)
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| 37 |
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| 38 | typedef union {
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| 39 | struct {
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| 40 | UINT32 Reserved : 32; // Reserved bit 0:31
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| 41 | } Bits;
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| 42 | UINT32 Uint32;
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| 43 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
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| 44 |
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| 45 | typedef union {
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| 46 | struct {
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| 47 | UINT32 Reserved : 32; // Reserved bit 0:31
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| 48 | } Bits;
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| 49 | UINT32 Uint32;
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| 50 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
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| 51 |
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| 52 | typedef union {
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| 53 | struct {
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| 54 | UINT32 EqualizationComplete : 1; // bit 0
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| 55 | UINT32 EqualizationPhase1Success : 1; // bit 1
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| 56 | UINT32 EqualizationPhase2Success : 1; // bit 2
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| 57 | UINT32 EqualizationPhase3Success : 1; // bit 3
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| 58 | UINT32 LinkEqualizationRequest : 1; // bit 4
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| 59 | UINT32 TransmitterPrecodingOn : 1; // bit 5
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| 60 | UINT32 TransmitterPrecodeRequest : 1; // bit 6
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| 61 | UINT32 NoEqualizationNeededRcvd : 1; // bit 7
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| 62 | UINT32 Reserved : 24; // Reserved bit 8:31
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| 63 | } Bits;
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| 64 | UINT32 Uint32;
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| 65 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
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| 66 |
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| 67 | typedef union {
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| 68 | struct {
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| 69 | UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
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| 70 | UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
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| 71 | } Bits;
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| 72 | UINT8 Uint8;
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| 73 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
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| 74 |
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| 75 | typedef struct {
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| 76 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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| 77 | PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
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| 78 | PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
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| 79 | PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
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| 80 | PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
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| 81 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
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| 82 | ///@}
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| 83 |
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| 84 | typedef union {
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| 85 | struct {
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| 86 | UINT32 DmwrRequestRouting : 1; // bit 0
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| 87 | UINT32 FourteenBitTagCompleter : 1; // bit 1
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| 88 | UINT32 FourteenBitTagRequester : 1; // bit 2
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| 89 | UINT32 ReceiverL0p : 1; // bit 3
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| 90 | UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
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| 91 | UINT32 RetimerL0pExit : 3; // bit 7..9
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| 92 | UINT32 Reserved : 22; // bit 10..31
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| 93 | } Bits;
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| 94 | UINT32 Uint32;
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| 95 | } PCI_REG_PCIE_DEVICE_CAPABILITY3;
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| 96 |
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| 97 | typedef union {
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| 98 | struct {
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| 99 | UINT32 DmwrRequesterEnable : 1; // bit 0
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| 100 | UINT32 DmwrEgressBlocking : 1; // bit 1
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| 101 | UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
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| 102 | UINT32 L0pEnable : 1; // bit 3
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| 103 | UINT32 TargetLinkWidth : 3; // bit 4..6
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| 104 | UINT32 Reserved : 25; // bit 7..31
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| 105 | } Bits;
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| 106 | UINT32 Uint32;
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| 107 | } PCI_REG_PCIE_DEVICE_CONTROL3;
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| 108 |
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| 109 | typedef union {
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| 110 | struct {
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| 111 | UINT32 InitialLinkWidth : 3; // bit 0..2
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| 112 | UINT32 SegmentCaptured : 1; // bit 3
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| 113 | UINT32 RemoteL0pSupported : 1; // bit 4
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| 114 | UINT32 Reserved : 27; // bit 5..31
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| 115 | } Bits;
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| 116 | UINT32 Uint32;
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| 117 | } PCI_REG_PCIE_DEVICE_STATUS3;
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| 118 |
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| 119 | #pragma pack()
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| 120 |
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| 121 | #endif
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