PciCf8Lib.h@ 105668

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1	/** @file
2	Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
3
4	This library is identical to the PCI Library, except the access method for performing PCI
5	configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
6	access to PCI Segment #0.
7
8	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9	SPDX-License-Identifier: BSD-2-Clause-Patent
10
11	**/
12
13	#ifndef __PCI_CF8_LIB_H__
14	#define __PCI_CF8_LIB_H__
15
16	/**
17	Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
18	address that can be passed to the PCI Library functions.
19
20	Computes an address that is compatible with the PCI Library functions. The
21	unused upper bits of Bus, Device, Function and Register are stripped prior to
22	the generation of the address.
23
24	@param Bus PCI Bus number. Range 0..255.
25	@param Device PCI Device number. Range 0..31.
26	@param Function PCI Function number. Range 0..7.
27	@param Register PCI Register number. Range 0..255.
28
29	@return The encode PCI address.
30
31	**/
32	#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \
33	(((Offset) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))
34
35	/**
36	Registers a PCI device so PCI configuration registers may be accessed after
37	SetVirtualAddressMap().
38
39	Registers the PCI device specified by Address so all the PCI configuration registers
40	associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
41
42	If Address > 0x0FFFFFFF, then ASSERT().
43	If the register specified by Address >= 0x100, then ASSERT().
44
45	@param Address Address that encodes the PCI Bus, Device, Function and
46	Register.
47
48	@retval RETURN_SUCCESS The PCI device was registered for runtime access.
49	@retval RETURN_UNSUPPORTED An attempt was made to call this function
50	after ExitBootServices().
51	@retval RETURN_UNSUPPORTED The resources required to access the PCI device
52	at runtime could not be mapped.
53	@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
54	complete the registration.
55
56	**/
57	RETURN_STATUS
58	EFIAPI
59	PciCf8RegisterForRuntimeAccess (
60	IN UINTN Address
61	);
62
63	/**
64	Reads an 8-bit PCI configuration register.
65
66	Reads and returns the 8-bit PCI configuration register specified by Address.
67	This function must guarantee that all PCI read and write operations are
68	serialized.
69
70	If Address > 0x0FFFFFFF, then ASSERT().
71	If the register specified by Address >= 0x100, then ASSERT().
72
73	@param Address Address that encodes the PCI Bus, Device, Function and
74	Register.
75
76	@return The read value from the PCI configuration register.
77
78	**/
79	UINT8
80	EFIAPI
81	PciCf8Read8 (
82	IN UINTN Address
83	);
84
85	/**
86	Writes an 8-bit PCI configuration register.
87
88	Writes the 8-bit PCI configuration register specified by Address with the
89	value specified by Value. Value is returned. This function must guarantee
90	that all PCI read and write operations are serialized.
91
92	If Address > 0x0FFFFFFF, then ASSERT().
93	If the register specified by Address >= 0x100, then ASSERT().
94
95	@param Address Address that encodes the PCI Bus, Device, Function and
96	Register.
97	@param Value The value to write.
98
99	@return The value written to the PCI configuration register.
100
101	**/
102	UINT8
103	EFIAPI
104	PciCf8Write8 (
105	IN UINTN Address,
106	IN UINT8 Value
107	);
108
109	/**
110	Performs a bitwise OR of an 8-bit PCI configuration register with
111	an 8-bit value.
112
113	Reads the 8-bit PCI configuration register specified by Address, performs a
114	bitwise OR between the read result and the value specified by
115	OrData, and writes the result to the 8-bit PCI configuration register
116	specified by Address. The value written to the PCI configuration register is
117	returned. This function must guarantee that all PCI read and write operations
118	are serialized.
119
120	If Address > 0x0FFFFFFF, then ASSERT().
121	If the register specified by Address >= 0x100, then ASSERT().
122
123	@param Address Address that encodes the PCI Bus, Device, Function and
124	Register.
125	@param OrData The value to OR with the PCI configuration register.
126
127	@return The value written back to the PCI configuration register.
128
129	**/
130	UINT8
131	EFIAPI
132	PciCf8Or8 (
133	IN UINTN Address,
134	IN UINT8 OrData
135	);
136
137	/**
138	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139	value.
140
141	Reads the 8-bit PCI configuration register specified by Address, performs a
142	bitwise AND between the read result and the value specified by AndData, and
143	writes the result to the 8-bit PCI configuration register specified by
144	Address. The value written to the PCI configuration register is returned.
145	This function must guarantee that all PCI read and write operations are
146	serialized.
147
148	If Address > 0x0FFFFFFF, then ASSERT().
149	If the register specified by Address >= 0x100, then ASSERT().
150
151	@param Address Address that encodes the PCI Bus, Device, Function and
152	Register.
153	@param AndData The value to AND with the PCI configuration register.
154
155	@return The value written back to the PCI configuration register.
156
157	**/
158	UINT8
159	EFIAPI
160	PciCf8And8 (
161	IN UINTN Address,
162	IN UINT8 AndData
163	);
164
165	/**
166	Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
167	value, followed a bitwise OR with another 8-bit value.
168
169	Reads the 8-bit PCI configuration register specified by Address, performs a
170	bitwise AND between the read result and the value specified by AndData,
171	performs a bitwise OR between the result of the AND operation and
172	the value specified by OrData, and writes the result to the 8-bit PCI
173	configuration register specified by Address. The value written to the PCI
174	configuration register is returned. This function must guarantee that all PCI
175	read and write operations are serialized.
176
177	If Address > 0x0FFFFFFF, then ASSERT().
178	If the register specified by Address >= 0x100, then ASSERT().
179
180	@param Address Address that encodes the PCI Bus, Device, Function and
181	Register.
182	@param AndData The value to AND with the PCI configuration register.
183	@param OrData The value to OR with the result of the AND operation.
184
185	@return The value written back to the PCI configuration register.
186
187	**/
188	UINT8
189	EFIAPI
190	PciCf8AndThenOr8 (
191	IN UINTN Address,
192	IN UINT8 AndData,
193	IN UINT8 OrData
194	);
195
196	/**
197	Reads a bit field of a PCI configuration register.
198
199	Reads the bit field in an 8-bit PCI configuration register. The bit field is
200	specified by the StartBit and the EndBit. The value of the bit field is
201	returned.
202
203	If Address > 0x0FFFFFFF, then ASSERT().
204	If the register specified by Address >= 0x100, then ASSERT().
205	If StartBit is greater than 7, then ASSERT().
206	If EndBit is greater than 7, then ASSERT().
207	If EndBit is less than StartBit, then ASSERT().
208
209	@param Address PCI configuration register to read.
210	@param StartBit The ordinal of the least significant bit in the bit field.
211	Range 0..7.
212	@param EndBit The ordinal of the most significant bit in the bit field.
213	Range 0..7.
214
215	@return The value of the bit field read from the PCI configuration register.
216
217	**/
218	UINT8
219	EFIAPI
220	PciCf8BitFieldRead8 (
221	IN UINTN Address,
222	IN UINTN StartBit,
223	IN UINTN EndBit
224	);
225
226	/**
227	Writes a bit field to a PCI configuration register.
228
229	Writes Value to the bit field of the PCI configuration register. The bit
230	field is specified by the StartBit and the EndBit. All other bits in the
231	destination PCI configuration register are preserved. The new value of the
232	8-bit register is returned.
233
234	If Address > 0x0FFFFFFF, then ASSERT().
235	If the register specified by Address >= 0x100, then ASSERT().
236	If StartBit is greater than 7, then ASSERT().
237	If EndBit is greater than 7, then ASSERT().
238	If EndBit is less than StartBit, then ASSERT().
239	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
240
241	@param Address PCI configuration register to write.
242	@param StartBit The ordinal of the least significant bit in the bit field.
243	Range 0..7.
244	@param EndBit The ordinal of the most significant bit in the bit field.
245	Range 0..7.
246	@param Value New value of the bit field.
247
248	@return The value written back to the PCI configuration register.
249
250	**/
251	UINT8
252	EFIAPI
253	PciCf8BitFieldWrite8 (
254	IN UINTN Address,
255	IN UINTN StartBit,
256	IN UINTN EndBit,
257	IN UINT8 Value
258	);
259
260	/**
261	Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
262	writes the result back to the bit field in the 8-bit port.
263
264	Reads the 8-bit PCI configuration register specified by Address, performs a
265	bitwise OR between the read result and the value specified by
266	OrData, and writes the result to the 8-bit PCI configuration register
267	specified by Address. The value written to the PCI configuration register is
268	returned. This function must guarantee that all PCI read and write operations
269	are serialized. Extra left bits in OrData are stripped.
270
271	If Address > 0x0FFFFFFF, then ASSERT().
272	If the register specified by Address >= 0x100, then ASSERT().
273	If StartBit is greater than 7, then ASSERT().
274	If EndBit is greater than 7, then ASSERT().
275	If EndBit is less than StartBit, then ASSERT().
276	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
277
278	@param Address PCI configuration register to write.
279	@param StartBit The ordinal of the least significant bit in the bit field.
280	Range 0..7.
281	@param EndBit The ordinal of the most significant bit in the bit field.
282	Range 0..7.
283	@param OrData The value to OR with the PCI configuration register.
284
285	@return The value written back to the PCI configuration register.
286
287	**/
288	UINT8
289	EFIAPI
290	PciCf8BitFieldOr8 (
291	IN UINTN Address,
292	IN UINTN StartBit,
293	IN UINTN EndBit,
294	IN UINT8 OrData
295	);
296
297	/**
298	Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
299	AND, and writes the result back to the bit field in the 8-bit register.
300
301	Reads the 8-bit PCI configuration register specified by Address, performs a
302	bitwise AND between the read result and the value specified by AndData, and
303	writes the result to the 8-bit PCI configuration register specified by
304	Address. The value written to the PCI configuration register is returned.
305	This function must guarantee that all PCI read and write operations are
306	serialized. Extra left bits in AndData are stripped.
307
308	If Address > 0x0FFFFFFF, then ASSERT().
309	If the register specified by Address >= 0x100, then ASSERT().
310	If StartBit is greater than 7, then ASSERT().
311	If EndBit is greater than 7, then ASSERT().
312	If EndBit is less than StartBit, then ASSERT().
313	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
314
315	@param Address PCI configuration register to write.
316	@param StartBit The ordinal of the least significant bit in the bit field.
317	Range 0..7.
318	@param EndBit The ordinal of the most significant bit in the bit field.
319	Range 0..7.
320	@param AndData The value to AND with the PCI configuration register.
321
322	@return The value written back to the PCI configuration register.
323
324	**/
325	UINT8
326	EFIAPI
327	PciCf8BitFieldAnd8 (
328	IN UINTN Address,
329	IN UINTN StartBit,
330	IN UINTN EndBit,
331	IN UINT8 AndData
332	);
333
334	/**
335	Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
336	bitwise OR, and writes the result back to the bit field in the
337	8-bit port.
338
339	Reads the 8-bit PCI configuration register specified by Address, performs a
340	bitwise AND followed by a bitwise OR between the read result and
341	the value specified by AndData, and writes the result to the 8-bit PCI
342	configuration register specified by Address. The value written to the PCI
343	configuration register is returned. This function must guarantee that all PCI
344	read and write operations are serialized. Extra left bits in both AndData and
345	OrData are stripped.
346
347	If Address > 0x0FFFFFFF, then ASSERT().
348	If the register specified by Address >= 0x100, then ASSERT().
349	If StartBit is greater than 7, then ASSERT().
350	If EndBit is greater than 7, then ASSERT().
351	If EndBit is less than StartBit, then ASSERT().
352	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
353	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
354
355	@param Address PCI configuration register to write.
356	@param StartBit The ordinal of the least significant bit in the bit field.
357	Range 0..7.
358	@param EndBit The ordinal of the most significant bit in the bit field.
359	Range 0..7.
360	@param AndData The value to AND with the PCI configuration register.
361	@param OrData The value to OR with the result of the AND operation.
362
363	@return The value written back to the PCI configuration register.
364
365	**/
366	UINT8
367	EFIAPI
368	PciCf8BitFieldAndThenOr8 (
369	IN UINTN Address,
370	IN UINTN StartBit,
371	IN UINTN EndBit,
372	IN UINT8 AndData,
373	IN UINT8 OrData
374	);
375
376	/**
377	Reads a 16-bit PCI configuration register.
378
379	Reads and returns the 16-bit PCI configuration register specified by Address.
380	This function must guarantee that all PCI read and write operations are
381	serialized.
382
383	If Address > 0x0FFFFFFF, then ASSERT().
384	If Address is not aligned on a 16-bit boundary, then ASSERT().
385	If the register specified by Address >= 0x100, then ASSERT().
386
387	@param Address Address that encodes the PCI Bus, Device, Function and
388	Register.
389
390	@return The read value from the PCI configuration register.
391
392	**/
393	UINT16
394	EFIAPI
395	PciCf8Read16 (
396	IN UINTN Address
397	);
398
399	/**
400	Writes a 16-bit PCI configuration register.
401
402	Writes the 16-bit PCI configuration register specified by Address with the
403	value specified by Value. Value is returned. This function must guarantee
404	that all PCI read and write operations are serialized.
405
406	If Address > 0x0FFFFFFF, then ASSERT().
407	If Address is not aligned on a 16-bit boundary, then ASSERT().
408	If the register specified by Address >= 0x100, then ASSERT().
409
410	@param Address Address that encodes the PCI Bus, Device, Function and
411	Register.
412	@param Value The value to write.
413
414	@return The value written to the PCI configuration register.
415
416	**/
417	UINT16
418	EFIAPI
419	PciCf8Write16 (
420	IN UINTN Address,
421	IN UINT16 Value
422	);
423
424	/**
425	Performs a bitwise OR of a 16-bit PCI configuration register with
426	a 16-bit value.
427
428	Reads the 16-bit PCI configuration register specified by Address, performs a
429	bitwise OR between the read result and the value specified by
430	OrData, and writes the result to the 16-bit PCI configuration register
431	specified by Address. The value written to the PCI configuration register is
432	returned. This function must guarantee that all PCI read and write operations
433	are serialized.
434
435	If Address > 0x0FFFFFFF, then ASSERT().
436	If Address is not aligned on a 16-bit boundary, then ASSERT().
437	If the register specified by Address >= 0x100, then ASSERT().
438
439	@param Address Address that encodes the PCI Bus, Device, Function and
440	Register.
441	@param OrData The value to OR with the PCI configuration register.
442
443	@return The value written back to the PCI configuration register.
444
445	**/
446	UINT16
447	EFIAPI
448	PciCf8Or16 (
449	IN UINTN Address,
450	IN UINT16 OrData
451	);
452
453	/**
454	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
455	value.
456
457	Reads the 16-bit PCI configuration register specified by Address, performs a
458	bitwise AND between the read result and the value specified by AndData, and
459	writes the result to the 16-bit PCI configuration register specified by
460	Address. The value written to the PCI configuration register is returned.
461	This function must guarantee that all PCI read and write operations are
462	serialized.
463
464	If Address > 0x0FFFFFFF, then ASSERT().
465	If Address is not aligned on a 16-bit boundary, then ASSERT().
466	If the register specified by Address >= 0x100, then ASSERT().
467
468	@param Address Address that encodes the PCI Bus, Device, Function and
469	Register.
470	@param AndData The value to AND with the PCI configuration register.
471
472	@return The value written back to the PCI configuration register.
473
474	**/
475	UINT16
476	EFIAPI
477	PciCf8And16 (
478	IN UINTN Address,
479	IN UINT16 AndData
480	);
481
482	/**
483	Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
484	value, followed a bitwise OR with another 16-bit value.
485
486	Reads the 16-bit PCI configuration register specified by Address, performs a
487	bitwise AND between the read result and the value specified by AndData,
488	performs a bitwise OR between the result of the AND operation and
489	the value specified by OrData, and writes the result to the 16-bit PCI
490	configuration register specified by Address. The value written to the PCI
491	configuration register is returned. This function must guarantee that all PCI
492	read and write operations are serialized.
493
494	If Address > 0x0FFFFFFF, then ASSERT().
495	If Address is not aligned on a 16-bit boundary, then ASSERT().
496	If the register specified by Address >= 0x100, then ASSERT().
497
498	@param Address Address that encodes the PCI Bus, Device, Function and
499	Register.
500	@param AndData The value to AND with the PCI configuration register.
501	@param OrData The value to OR with the result of the AND operation.
502
503	@return The value written back to the PCI configuration register.
504
505	**/
506	UINT16
507	EFIAPI
508	PciCf8AndThenOr16 (
509	IN UINTN Address,
510	IN UINT16 AndData,
511	IN UINT16 OrData
512	);
513
514	/**
515	Reads a bit field of a PCI configuration register.
516
517	Reads the bit field in a 16-bit PCI configuration register. The bit field is
518	specified by the StartBit and the EndBit. The value of the bit field is
519	returned.
520
521	If Address > 0x0FFFFFFF, then ASSERT().
522	If Address is not aligned on a 16-bit boundary, then ASSERT().
523	If the register specified by Address >= 0x100, then ASSERT().
524	If StartBit is greater than 15, then ASSERT().
525	If EndBit is greater than 15, then ASSERT().
526	If EndBit is less than StartBit, then ASSERT().
527
528	@param Address PCI configuration register to read.
529	@param StartBit The ordinal of the least significant bit in the bit field.
530	Range 0..15.
531	@param EndBit The ordinal of the most significant bit in the bit field.
532	Range 0..15.
533
534	@return The value of the bit field read from the PCI configuration register.
535
536	**/
537	UINT16
538	EFIAPI
539	PciCf8BitFieldRead16 (
540	IN UINTN Address,
541	IN UINTN StartBit,
542	IN UINTN EndBit
543	);
544
545	/**
546	Writes a bit field to a PCI configuration register.
547
548	Writes Value to the bit field of the PCI configuration register. The bit
549	field is specified by the StartBit and the EndBit. All other bits in the
550	destination PCI configuration register are preserved. The new value of the
551	16-bit register is returned.
552
553	If Address > 0x0FFFFFFF, then ASSERT().
554	If Address is not aligned on a 16-bit boundary, then ASSERT().
555	If the register specified by Address >= 0x100, then ASSERT().
556	If StartBit is greater than 15, then ASSERT().
557	If EndBit is greater than 15, then ASSERT().
558	If EndBit is less than StartBit, then ASSERT().
559	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
560
561	@param Address PCI configuration register to write.
562	@param StartBit The ordinal of the least significant bit in the bit field.
563	Range 0..15.
564	@param EndBit The ordinal of the most significant bit in the bit field.
565	Range 0..15.
566	@param Value New value of the bit field.
567
568	@return The value written back to the PCI configuration register.
569
570	**/
571	UINT16
572	EFIAPI
573	PciCf8BitFieldWrite16 (
574	IN UINTN Address,
575	IN UINTN StartBit,
576	IN UINTN EndBit,
577	IN UINT16 Value
578	);
579
580	/**
581	Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
582	writes the result back to the bit field in the 16-bit port.
583
584	Reads the 16-bit PCI configuration register specified by Address, performs a
585	bitwise OR between the read result and the value specified by
586	OrData, and writes the result to the 16-bit PCI configuration register
587	specified by Address. The value written to the PCI configuration register is
588	returned. This function must guarantee that all PCI read and write operations
589	are serialized. Extra left bits in OrData are stripped.
590
591	If Address > 0x0FFFFFFF, then ASSERT().
592	If Address is not aligned on a 16-bit boundary, then ASSERT().
593	If the register specified by Address >= 0x100, then ASSERT().
594	If StartBit is greater than 15, then ASSERT().
595	If EndBit is greater than 15, then ASSERT().
596	If EndBit is less than StartBit, then ASSERT().
597	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
598
599	@param Address PCI configuration register to write.
600	@param StartBit The ordinal of the least significant bit in the bit field.
601	Range 0..15.
602	@param EndBit The ordinal of the most significant bit in the bit field.
603	Range 0..15.
604	@param OrData The value to OR with the PCI configuration register.
605
606	@return The value written back to the PCI configuration register.
607
608	**/
609	UINT16
610	EFIAPI
611	PciCf8BitFieldOr16 (
612	IN UINTN Address,
613	IN UINTN StartBit,
614	IN UINTN EndBit,
615	IN UINT16 OrData
616	);
617
618	/**
619	Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
620	AND, and writes the result back to the bit field in the 16-bit register.
621
622	Reads the 16-bit PCI configuration register specified by Address, performs a
623	bitwise AND between the read result and the value specified by AndData, and
624	writes the result to the 16-bit PCI configuration register specified by
625	Address. The value written to the PCI configuration register is returned.
626	This function must guarantee that all PCI read and write operations are
627	serialized. Extra left bits in AndData are stripped.
628
629	If Address > 0x0FFFFFFF, then ASSERT().
630	If Address is not aligned on a 16-bit boundary, then ASSERT().
631	If the register specified by Address >= 0x100, then ASSERT().
632	If StartBit is greater than 15, then ASSERT().
633	If EndBit is greater than 15, then ASSERT().
634	If EndBit is less than StartBit, then ASSERT().
635	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
636
637	@param Address PCI configuration register to write.
638	@param StartBit The ordinal of the least significant bit in the bit field.
639	Range 0..15.
640	@param EndBit The ordinal of the most significant bit in the bit field.
641	Range 0..15.
642	@param AndData The value to AND with the PCI configuration register.
643
644	@return The value written back to the PCI configuration register.
645
646	**/
647	UINT16
648	EFIAPI
649	PciCf8BitFieldAnd16 (
650	IN UINTN Address,
651	IN UINTN StartBit,
652	IN UINTN EndBit,
653	IN UINT16 AndData
654	);
655
656	/**
657	Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
658	bitwise OR, and writes the result back to the bit field in the
659	16-bit port.
660
661	Reads the 16-bit PCI configuration register specified by Address, performs a
662	bitwise AND followed by a bitwise OR between the read result and
663	the value specified by AndData, and writes the result to the 16-bit PCI
664	configuration register specified by Address. The value written to the PCI
665	configuration register is returned. This function must guarantee that all PCI
666	read and write operations are serialized. Extra left bits in both AndData and
667	OrData are stripped.
668
669	If Address > 0x0FFFFFFF, then ASSERT().
670	If Address is not aligned on a 16-bit boundary, then ASSERT().
671	If the register specified by Address >= 0x100, then ASSERT().
672	If StartBit is greater than 15, then ASSERT().
673	If EndBit is greater than 15, then ASSERT().
674	If EndBit is less than StartBit, then ASSERT().
675	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
676	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
677
678	@param Address PCI configuration register to write.
679	@param StartBit The ordinal of the least significant bit in the bit field.
680	Range 0..15.
681	@param EndBit The ordinal of the most significant bit in the bit field.
682	Range 0..15.
683	@param AndData The value to AND with the PCI configuration register.
684	@param OrData The value to OR with the result of the AND operation.
685
686	@return The value written back to the PCI configuration register.
687
688	**/
689	UINT16
690	EFIAPI
691	PciCf8BitFieldAndThenOr16 (
692	IN UINTN Address,
693	IN UINTN StartBit,
694	IN UINTN EndBit,
695	IN UINT16 AndData,
696	IN UINT16 OrData
697	);
698
699	/**
700	Reads a 32-bit PCI configuration register.
701
702	Reads and returns the 32-bit PCI configuration register specified by Address.
703	This function must guarantee that all PCI read and write operations are
704	serialized.
705
706	If Address > 0x0FFFFFFF, then ASSERT().
707	If Address is not aligned on a 32-bit boundary, then ASSERT().
708	If the register specified by Address >= 0x100, then ASSERT().
709
710	@param Address Address that encodes the PCI Bus, Device, Function and
711	Register.
712
713	@return The read value from the PCI configuration register.
714
715	**/
716	UINT32
717	EFIAPI
718	PciCf8Read32 (
719	IN UINTN Address
720	);
721
722	/**
723	Writes a 32-bit PCI configuration register.
724
725	Writes the 32-bit PCI configuration register specified by Address with the
726	value specified by Value. Value is returned. This function must guarantee
727	that all PCI read and write operations are serialized.
728
729	If Address > 0x0FFFFFFF, then ASSERT().
730	If Address is not aligned on a 32-bit boundary, then ASSERT().
731	If the register specified by Address >= 0x100, then ASSERT().
732
733	@param Address Address that encodes the PCI Bus, Device, Function and
734	Register.
735	@param Value The value to write.
736
737	@return The value written to the PCI configuration register.
738
739	**/
740	UINT32
741	EFIAPI
742	PciCf8Write32 (
743	IN UINTN Address,
744	IN UINT32 Value
745	);
746
747	/**
748	Performs a bitwise OR of a 32-bit PCI configuration register with
749	a 32-bit value.
750
751	Reads the 32-bit PCI configuration register specified by Address, performs a
752	bitwise OR between the read result and the value specified by
753	OrData, and writes the result to the 32-bit PCI configuration register
754	specified by Address. The value written to the PCI configuration register is
755	returned. This function must guarantee that all PCI read and write operations
756	are serialized.
757
758	If Address > 0x0FFFFFFF, then ASSERT().
759	If Address is not aligned on a 32-bit boundary, then ASSERT().
760	If the register specified by Address >= 0x100, then ASSERT().
761
762	@param Address Address that encodes the PCI Bus, Device, Function and
763	Register.
764	@param OrData The value to OR with the PCI configuration register.
765
766	@return The value written back to the PCI configuration register.
767
768	**/
769	UINT32
770	EFIAPI
771	PciCf8Or32 (
772	IN UINTN Address,
773	IN UINT32 OrData
774	);
775
776	/**
777	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
778	value.
779
780	Reads the 32-bit PCI configuration register specified by Address, performs a
781	bitwise AND between the read result and the value specified by AndData, and
782	writes the result to the 32-bit PCI configuration register specified by
783	Address. The value written to the PCI configuration register is returned.
784	This function must guarantee that all PCI read and write operations are
785	serialized.
786
787	If Address > 0x0FFFFFFF, then ASSERT().
788	If Address is not aligned on a 32-bit boundary, then ASSERT().
789	If the register specified by Address >= 0x100, then ASSERT().
790
791	@param Address Address that encodes the PCI Bus, Device, Function and
792	Register.
793	@param AndData The value to AND with the PCI configuration register.
794
795	@return The value written back to the PCI configuration register.
796
797	**/
798	UINT32
799	EFIAPI
800	PciCf8And32 (
801	IN UINTN Address,
802	IN UINT32 AndData
803	);
804
805	/**
806	Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
807	value, followed a bitwise OR with another 32-bit value.
808
809	Reads the 32-bit PCI configuration register specified by Address, performs a
810	bitwise AND between the read result and the value specified by AndData,
811	performs a bitwise OR between the result of the AND operation and
812	the value specified by OrData, and writes the result to the 32-bit PCI
813	configuration register specified by Address. The value written to the PCI
814	configuration register is returned. This function must guarantee that all PCI
815	read and write operations are serialized.
816
817	If Address > 0x0FFFFFFF, then ASSERT().
818	If Address is not aligned on a 32-bit boundary, then ASSERT().
819	If the register specified by Address >= 0x100, then ASSERT().
820
821	@param Address Address that encodes the PCI Bus, Device, Function and
822	Register.
823	@param AndData The value to AND with the PCI configuration register.
824	@param OrData The value to OR with the result of the AND operation.
825
826	@return The value written back to the PCI configuration register.
827
828	**/
829	UINT32
830	EFIAPI
831	PciCf8AndThenOr32 (
832	IN UINTN Address,
833	IN UINT32 AndData,
834	IN UINT32 OrData
835	);
836
837	/**
838	Reads a bit field of a PCI configuration register.
839
840	Reads the bit field in a 32-bit PCI configuration register. The bit field is
841	specified by the StartBit and the EndBit. The value of the bit field is
842	returned.
843
844	If Address > 0x0FFFFFFF, then ASSERT().
845	If Address is not aligned on a 32-bit boundary, then ASSERT().
846	If the register specified by Address >= 0x100, then ASSERT().
847	If StartBit is greater than 31, then ASSERT().
848	If EndBit is greater than 31, then ASSERT().
849	If EndBit is less than StartBit, then ASSERT().
850
851	@param Address PCI configuration register to read.
852	@param StartBit The ordinal of the least significant bit in the bit field.
853	Range 0..31.
854	@param EndBit The ordinal of the most significant bit in the bit field.
855	Range 0..31.
856
857	@return The value of the bit field read from the PCI configuration register.
858
859	**/
860	UINT32
861	EFIAPI
862	PciCf8BitFieldRead32 (
863	IN UINTN Address,
864	IN UINTN StartBit,
865	IN UINTN EndBit
866	);
867
868	/**
869	Writes a bit field to a PCI configuration register.
870
871	Writes Value to the bit field of the PCI configuration register. The bit
872	field is specified by the StartBit and the EndBit. All other bits in the
873	destination PCI configuration register are preserved. The new value of the
874	32-bit register is returned.
875
876	If Address > 0x0FFFFFFF, then ASSERT().
877	If Address is not aligned on a 32-bit boundary, then ASSERT().
878	If the register specified by Address >= 0x100, then ASSERT().
879	If StartBit is greater than 31, then ASSERT().
880	If EndBit is greater than 31, then ASSERT().
881	If EndBit is less than StartBit, then ASSERT().
882	If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
883
884	@param Address PCI configuration register to write.
885	@param StartBit The ordinal of the least significant bit in the bit field.
886	Range 0..31.
887	@param EndBit The ordinal of the most significant bit in the bit field.
888	Range 0..31.
889	@param Value New value of the bit field.
890
891	@return The value written back to the PCI configuration register.
892
893	**/
894	UINT32
895	EFIAPI
896	PciCf8BitFieldWrite32 (
897	IN UINTN Address,
898	IN UINTN StartBit,
899	IN UINTN EndBit,
900	IN UINT32 Value
901	);
902
903	/**
904	Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
905	writes the result back to the bit field in the 32-bit port.
906
907	Reads the 32-bit PCI configuration register specified by Address, performs a
908	bitwise OR between the read result and the value specified by
909	OrData, and writes the result to the 32-bit PCI configuration register
910	specified by Address. The value written to the PCI configuration register is
911	returned. This function must guarantee that all PCI read and write operations
912	are serialized. Extra left bits in OrData are stripped.
913
914	If Address > 0x0FFFFFFF, then ASSERT().
915	If Address is not aligned on a 32-bit boundary, then ASSERT().
916	If the register specified by Address >= 0x100, then ASSERT().
917	If StartBit is greater than 31, then ASSERT().
918	If EndBit is greater than 31, then ASSERT().
919	If EndBit is less than StartBit, then ASSERT().
920	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
921
922	@param Address PCI configuration register to write.
923	@param StartBit The ordinal of the least significant bit in the bit field.
924	Range 0..31.
925	@param EndBit The ordinal of the most significant bit in the bit field.
926	Range 0..31.
927	@param OrData The value to OR with the PCI configuration register.
928
929	@return The value written back to the PCI configuration register.
930
931	**/
932	UINT32
933	EFIAPI
934	PciCf8BitFieldOr32 (
935	IN UINTN Address,
936	IN UINTN StartBit,
937	IN UINTN EndBit,
938	IN UINT32 OrData
939	);
940
941	/**
942	Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
943	AND, and writes the result back to the bit field in the 32-bit register.
944
945	Reads the 32-bit PCI configuration register specified by Address, performs a
946	bitwise AND between the read result and the value specified by AndData, and
947	writes the result to the 32-bit PCI configuration register specified by
948	Address. The value written to the PCI configuration register is returned.
949	This function must guarantee that all PCI read and write operations are
950	serialized. Extra left bits in AndData are stripped.
951
952	If Address > 0x0FFFFFFF, then ASSERT().
953	If Address is not aligned on a 32-bit boundary, then ASSERT().
954	If the register specified by Address >= 0x100, then ASSERT().
955	If StartBit is greater than 31, then ASSERT().
956	If EndBit is greater than 31, then ASSERT().
957	If EndBit is less than StartBit, then ASSERT().
958	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
959
960	@param Address PCI configuration register to write.
961	@param StartBit The ordinal of the least significant bit in the bit field.
962	Range 0..31.
963	@param EndBit The ordinal of the most significant bit in the bit field.
964	Range 0..31.
965	@param AndData The value to AND with the PCI configuration register.
966
967	@return The value written back to the PCI configuration register.
968
969	**/
970	UINT32
971	EFIAPI
972	PciCf8BitFieldAnd32 (
973	IN UINTN Address,
974	IN UINTN StartBit,
975	IN UINTN EndBit,
976	IN UINT32 AndData
977	);
978
979	/**
980	Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
981	bitwise OR, and writes the result back to the bit field in the
982	32-bit port.
983
984	Reads the 32-bit PCI configuration register specified by Address, performs a
985	bitwise AND followed by a bitwise OR between the read result and
986	the value specified by AndData, and writes the result to the 32-bit PCI
987	configuration register specified by Address. The value written to the PCI
988	configuration register is returned. This function must guarantee that all PCI
989	read and write operations are serialized. Extra left bits in both AndData and
990	OrData are stripped.
991
992	If Address > 0x0FFFFFFF, then ASSERT().
993	If Address is not aligned on a 32-bit boundary, then ASSERT().
994	If the register specified by Address >= 0x100, then ASSERT().
995	If StartBit is greater than 31, then ASSERT().
996	If EndBit is greater than 31, then ASSERT().
997	If EndBit is less than StartBit, then ASSERT().
998	If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
999	If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1000
1001	@param Address PCI configuration register to write.
1002	@param StartBit The ordinal of the least significant bit in the bit field.
1003	Range 0..31.
1004	@param EndBit The ordinal of the most significant bit in the bit field.
1005	Range 0..31.
1006	@param AndData The value to AND with the PCI configuration register.
1007	@param OrData The value to OR with the result of the AND operation.
1008
1009	@return The value written back to the PCI configuration register.
1010
1011	**/
1012	UINT32
1013	EFIAPI
1014	PciCf8BitFieldAndThenOr32 (
1015	IN UINTN Address,
1016	IN UINTN StartBit,
1017	IN UINTN EndBit,
1018	IN UINT32 AndData,
1019	IN UINT32 OrData
1020	);
1021
1022	/**
1023	Reads a range of PCI configuration registers into a caller supplied buffer.
1024
1025	Reads the range of PCI configuration registers specified by StartAddress and
1026	Size into the buffer specified by Buffer. This function only allows the PCI
1027	configuration registers from a single PCI function to be read. Size is
1028	returned. When possible 32-bit PCI configuration read cycles are used to read
1029	from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
1030	and 16-bit PCI configuration read cycles may be used at the beginning and the
1031	end of the range.
1032
1033	If StartAddress > 0x0FFFFFFF, then ASSERT().
1034	If the register specified by StartAddress >= 0x100, then ASSERT().
1035	If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1036	If Size > 0 and Buffer is NULL, then ASSERT().
1037
1038	@param StartAddress Starting address that encodes the PCI Bus, Device,
1039	Function and Register.
1040	@param Size Size in bytes of the transfer.
1041	@param Buffer Pointer to a buffer receiving the data read.
1042
1043	@return Size read from StartAddress.
1044
1045	**/
1046	UINTN
1047	EFIAPI
1048	PciCf8ReadBuffer (
1049	IN UINTN StartAddress,
1050	IN UINTN Size,
1051	OUT VOID *Buffer
1052	);
1053
1054	/**
1055	Copies the data in a caller supplied buffer to a specified range of PCI
1056	configuration space.
1057
1058	Writes the range of PCI configuration registers specified by StartAddress and
1059	Size from the buffer specified by Buffer. This function only allows the PCI
1060	configuration registers from a single PCI function to be written. Size is
1061	returned. When possible 32-bit PCI configuration write cycles are used to
1062	write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1063	8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1064	and the end of the range.
1065
1066	If StartAddress > 0x0FFFFFFF, then ASSERT().
1067	If the register specified by StartAddress >= 0x100, then ASSERT().
1068	If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1069	If Size > 0 and Buffer is NULL, then ASSERT().
1070
1071	@param StartAddress Starting address that encodes the PCI Bus, Device,
1072	Function and Register.
1073	@param Size Size in bytes of the transfer.
1074	@param Buffer Pointer to a buffer containing the data to write.
1075
1076	@return Size written to StartAddress.
1077
1078	**/
1079	UINTN
1080	EFIAPI
1081	PciCf8WriteBuffer (
1082	IN UINTN StartAddress,
1083	IN UINTN Size,
1084	IN VOID *Buffer
1085	);
1086
1087	#endif

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source: vbox/trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Include/Library/PciCf8Lib.h@ 105668

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