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source: vbox/trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/ResetVector/ResetVector.nasmb

Last change on this file was 105670, checked in by vboxsync, 9 months ago

Devices/EFI/FirmwareNew: Merge edk2-stable-202405 and make it build on aarch64, bugref:4643

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1;------------------------------------------------------------------------------
2; @file
3; This file includes all other code files to assemble the reset vector code
4;
5; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
6; Copyright (c) 2020 - 2024, Advanced Micro Devices, Inc. All rights reserved.<BR>
7; SPDX-License-Identifier: BSD-2-Clause-Patent
8;
9;------------------------------------------------------------------------------
10
11;
12; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
13; Base.h to use the C pre-processor to determine the architecture.
14;
15%ifndef ARCH_IA32
16 %ifndef ARCH_X64
17 #include <Base.h>
18 #if defined (MDE_CPU_IA32)
19 %define ARCH_IA32
20 #elif defined (MDE_CPU_X64)
21 %define ARCH_X64
22 #endif
23 %endif
24%endif
25
26%ifdef ARCH_IA32
27 %ifdef ARCH_X64
28 %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
29 %endif
30%elifdef ARCH_X64
31%else
32 %error "Either ARCH_IA32 or ARCH_X64 must be defined."
33%endif
34
35%include "CommonMacros.inc"
36
37%include "PostCodes.inc"
38
39%ifdef DEBUG_PORT80
40 %include "Port80Debug.asm"
41%elifdef DEBUG_SERIAL
42 %include "SerialDebug.asm"
43%elif 0
44; Set ^ this to 1 to enable postcodes on the qemu debug console.
45; Disabled by default because it is incompatible with SEV-ES/SEV-SNP and TDX.
46 %include "QemuDebugCon.asm"
47%else
48 %include "DebugDisabled.asm"
49%endif
50
51%include "Ia32/SearchForBfvBase.asm"
52%include "Ia32/SearchForSecEntry.asm"
53
54%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))
55%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
56%define PG_5_LEVEL (FixedPcdGetBool (PcdUse5LevelPageTable))
57
58%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))
59%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))
60%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
61%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))
62%define SEV_ES_WORK_AREA_SIZE 25
63%define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase))
64%define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)
65%define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)
66%define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)
67%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
68%define SEV_SNP_SECRETS_BASE (FixedPcdGet32 (PcdOvmfSnpSecretsBase))
69%define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSize))
70%define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase))
71%define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize))
72%define SVSM_CAA_BASE (FixedPcdGet32 (PcdOvmfSecSvsmCaaBase))
73%define SVSM_CAA_SIZE (FixedPcdGet32 (PcdOvmfSecSvsmCaaSize))
74%if (FixedPcdGet32 (PcdSevLaunchSecretBase) > 0)
75 ; There's a reserved page for SEV secrets and hashes; the VMM will fill and
76 ; validate the page, or mark it as a zero page.
77 %define SEV_SNP_KERNEL_HASHES_BASE (FixedPcdGet32 (PcdSevLaunchSecretBase))
78 %define SEV_SNP_KERNEL_HASHES_SIZE (FixedPcdGet32 (PcdSevLaunchSecretSize) + FixedPcdGet32 (PcdQemuHashTableSize))
79%else
80 %define SEV_SNP_KERNEL_HASHES_BASE 0
81 %define SEV_SNP_KERNEL_HASHES_SIZE 0
82%endif
83%define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTablesBase))
84%define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SNP_SEC_MEM_BASE_DESC_1)
85;
86; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used
87; as GHCB shared page and second is used for bookkeeping to support the
88; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM
89; does not need to validate the shared page but it need to validate the
90; bookkeeping page.
91;
92%define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000)
93%define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE_DESC_2)
94%define SNP_SEC_MEM_BASE_DESC_3 (SVSM_CAA_BASE + SVSM_CAA_SIZE + SEV_SNP_KERNEL_HASHES_SIZE)
95%define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - SNP_SEC_MEM_BASE_DESC_3)
96
97%ifdef ARCH_X64
98 #include <AutoGen.h>
99
100 %if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
101 %error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
102 %endif
103
104 %if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) != 0x1000)
105 %error "This implementation inherently depends on PcdOvmfSecGhcbPageTableSize"
106 %endif
107
108 %if (FixedPcdGet32 (PcdOvmfSecGhcbSize) != 0x2000)
109 %error "This implementation inherently depends on PcdOvmfSecGhcbSize"
110 %endif
111
112 %if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) != \
113 ((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhcbSize) - 1) >> 21))
114 %error "This implementation inherently depends on PcdOvmfSecGhcbBase not straddling a 2MB boundary"
115 %endif
116
117 %define TDX_BFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdBfvRawDataOffset)
118 %define TDX_BFV_RAW_DATA_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
119 %define TDX_BFV_MEMORY_BASE FixedPcdGet32 (PcdBfvBase)
120 %define TDX_BFV_MEMORY_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
121
122 %define TDX_CFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdCfvRawDataOffset)
123 %define TDX_CFV_RAW_DATA_SIZE FixedPcdGet32 (PcdCfvRawDataSize)
124 %define TDX_CFV_MEMORY_BASE FixedPcdGet32 (PcdCfvBase),
125 %define TDX_CFV_MEMORY_SIZE FixedPcdGet32 (PcdCfvRawDataSize),
126
127 %define TDX_HEAP_STACK_BASE FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)
128 %define TDX_HEAP_STACK_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)
129
130 %define TDX_HOB_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBase)
131 %define TDX_HOB_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbSize)
132
133 %define TDX_INIT_MEMORY_BASE FixedPcdGet32 (PcdOvmfWorkAreaBase)
134 %define TDX_INIT_MEMORY_SIZE (FixedPcdGet32 (PcdOvmfWorkAreaSize) + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize))
135
136 %define OVMF_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecPageTablesBase)
137 %define OVMF_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecPageTablesSize)
138
139 %define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 4)
140 %define TDX_WORK_AREA_GPAW (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 8)
141
142 %include "X64/IntelTdxMetadata.asm"
143 %include "Ia32/Flat32ToFlat64.asm"
144 %include "Ia32/PageTables64.asm"
145 %include "Ia32/IntelTdx.asm"
146 %include "X64/OvmfSevMetadata.asm"
147%endif
148
149%include "Ia32/AmdSev.asm"
150
151%include "Ia16/Real16ToFlat32.asm"
152%include "Ia16/Init16.asm"
153
154%include "Main.asm"
155
156 %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase)
157 %define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase)
158 %define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize)
159 %define SEV_FW_HASH_BLOCK_BASE FixedPcdGet32 (PcdQemuHashTableBase)
160 %define SEV_FW_HASH_BLOCK_SIZE FixedPcdGet32 (PcdQemuHashTableSize)
161%include "Ia16/ResetVectorVtf0.asm"
162
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