1 | /** @file
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2 |
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3 | Functions and types shared by the SMM accessor PEI and DXE modules.
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4 |
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5 | Copyright (C) 2015, Red Hat, Inc.
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6 |
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7 | SPDX-License-Identifier: BSD-2-Clause-Patent
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8 |
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9 | **/
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10 |
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11 | #include <Guid/AcpiS3Context.h>
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12 | #include <IndustryStandard/Q35MchIch9.h>
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13 | #include <Library/DebugLib.h>
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14 | #include <Library/PcdLib.h>
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15 | #include <Library/PciLib.h>
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16 |
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17 | #include "SmramInternal.h"
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18 |
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19 | //
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20 | // The value of PcdQ35TsegMbytes is saved into this variable at module startup.
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21 | //
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22 | UINT16 mQ35TsegMbytes;
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23 |
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24 | //
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25 | // The value of PcdQ35SmramAtDefaultSmbase is saved into this variable at
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26 | // module startup.
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27 | //
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28 | STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
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29 |
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30 | /**
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31 | Save PcdQ35TsegMbytes into mQ35TsegMbytes.
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32 | **/
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33 | VOID
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34 | InitQ35TsegMbytes (
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35 | VOID
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36 | )
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37 | {
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38 | mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
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39 | }
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40 |
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41 | /**
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42 | Save PcdQ35SmramAtDefaultSmbase into mQ35SmramAtDefaultSmbase.
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43 | **/
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44 | VOID
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45 | InitQ35SmramAtDefaultSmbase (
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46 | VOID
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47 | )
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48 | {
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49 | mQ35SmramAtDefaultSmbase = PcdGetBool (PcdQ35SmramAtDefaultSmbase);
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50 | }
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51 |
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52 | /**
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53 | Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and
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54 | OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object,
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55 | from the D_LCK and T_EN bits.
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56 |
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57 | PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on
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58 | the LockState and OpenState fields being up-to-date on entry, and they need
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59 | to restore the same invariant on exit, if they touch the bits in question.
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60 |
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61 | @param[out] LockState Reflects the D_LCK bit on output; TRUE iff SMRAM is
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62 | locked.
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63 | @param[out] OpenState Reflects the inverse of the T_EN bit on output; TRUE
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64 | iff SMRAM is open.
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65 | **/
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66 | VOID
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67 | GetStates (
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68 | OUT BOOLEAN *LockState,
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69 | OUT BOOLEAN *OpenState
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70 | )
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71 | {
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72 | UINT8 SmramVal, EsmramcVal;
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73 |
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74 | SmramVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));
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75 | EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
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76 |
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77 | *LockState = !!(SmramVal & MCH_SMRAM_D_LCK);
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78 | *OpenState = !(EsmramcVal & MCH_ESMRAMC_T_EN);
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79 | }
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80 |
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81 | //
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82 | // The functions below follow the PEI_SMM_ACCESS_PPI and
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83 | // EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This
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84 | // pointers are removed (TSEG doesn't depend on them), and so is the
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85 | // DescriptorIndex parameter (TSEG doesn't support range-wise locking).
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86 | //
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87 | // The LockState and OpenState members that are common to both
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88 | // PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in
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89 | // isolation from the rest of the (non-shared) members.
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90 | //
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91 |
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92 | EFI_STATUS
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93 | SmramAccessOpen (
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94 | OUT BOOLEAN *LockState,
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95 | OUT BOOLEAN *OpenState
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96 | )
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97 | {
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98 | //
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99 | // Open TSEG by clearing T_EN.
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100 | //
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101 | PciAnd8 (
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102 | DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
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103 | (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff)
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104 | );
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105 |
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106 | GetStates (LockState, OpenState);
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107 | if (!*OpenState) {
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108 | return EFI_DEVICE_ERROR;
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109 | }
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110 |
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111 | return EFI_SUCCESS;
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112 | }
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113 |
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114 | EFI_STATUS
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115 | SmramAccessClose (
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116 | OUT BOOLEAN *LockState,
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117 | OUT BOOLEAN *OpenState
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118 | )
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119 | {
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120 | //
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121 | // Close TSEG by setting T_EN.
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122 | //
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123 | PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
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124 |
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125 | GetStates (LockState, OpenState);
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126 | if (*OpenState) {
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127 | return EFI_DEVICE_ERROR;
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128 | }
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129 |
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130 | return EFI_SUCCESS;
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131 | }
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132 |
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133 | EFI_STATUS
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134 | SmramAccessLock (
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135 | OUT BOOLEAN *LockState,
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136 | IN OUT BOOLEAN *OpenState
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137 | )
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138 | {
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139 | if (*OpenState) {
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140 | return EFI_DEVICE_ERROR;
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141 | }
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142 |
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143 | //
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144 | // Close & lock TSEG by setting T_EN and D_LCK.
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145 | //
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146 | PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
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147 | PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
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148 |
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149 | //
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150 | // Close & lock the SMRAM at the default SMBASE, if it exists.
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151 | //
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152 | if (mQ35SmramAtDefaultSmbase) {
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153 | PciWrite8 (
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154 | DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
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155 | MCH_DEFAULT_SMBASE_LCK
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156 | );
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157 | }
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158 |
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159 | GetStates (LockState, OpenState);
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160 | if (*OpenState || !*LockState) {
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161 | return EFI_DEVICE_ERROR;
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162 | }
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163 |
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164 | return EFI_SUCCESS;
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165 | }
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166 |
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167 | EFI_STATUS
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168 | SmramAccessGetCapabilities (
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169 | IN BOOLEAN LockState,
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170 | IN BOOLEAN OpenState,
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171 | IN OUT UINTN *SmramMapSize,
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172 | IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
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173 | )
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174 | {
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175 | UINTN OriginalSize;
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176 | UINT32 TsegMemoryBaseMb, TsegMemoryBase;
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177 | UINT64 CommonRegionState;
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178 | UINT8 TsegSizeBits;
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179 |
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180 | OriginalSize = *SmramMapSize;
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181 | *SmramMapSize = DescIdxCount * sizeof *SmramMap;
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182 | if (OriginalSize < *SmramMapSize) {
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183 | return EFI_BUFFER_TOO_SMALL;
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184 | }
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185 |
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186 | //
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187 | // Read the TSEG Memory Base register.
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188 | //
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189 | TsegMemoryBaseMb = PciRead32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB));
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190 | TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
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191 |
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192 | //
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193 | // Precompute the region state bits that will be set for all regions.
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194 | //
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195 | CommonRegionState = (OpenState ? EFI_SMRAM_OPEN : EFI_SMRAM_CLOSED) |
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196 | (LockState ? EFI_SMRAM_LOCKED : 0) |
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197 | EFI_CACHEABLE;
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198 |
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199 | //
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200 | // The first region hosts an SMM_S3_RESUME_STATE object. It is located at the
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201 | // start of TSEG. We round up the size to whole pages, and we report it as
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202 | // EFI_ALLOCATED, so that the SMM_CORE stays away from it.
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203 | //
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204 | SmramMap[DescIdxSmmS3ResumeState].PhysicalStart = TsegMemoryBase;
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205 | SmramMap[DescIdxSmmS3ResumeState].CpuStart = TsegMemoryBase;
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206 | SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =
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207 | EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
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208 | SmramMap[DescIdxSmmS3ResumeState].RegionState =
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209 | CommonRegionState | EFI_ALLOCATED;
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210 |
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211 | //
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212 | // Get the TSEG size bits from the ESMRAMC register.
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213 | //
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214 | TsegSizeBits = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)) &
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215 | MCH_ESMRAMC_TSEG_MASK;
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216 |
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217 | //
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218 | // The second region is the main one, following the first.
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219 | //
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220 | SmramMap[DescIdxMain].PhysicalStart =
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221 | SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
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222 | SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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223 | SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
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224 | SmramMap[DescIdxMain].PhysicalSize =
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225 | (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
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226 | TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
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227 | TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB :
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228 | mQ35TsegMbytes * SIZE_1MB) -
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229 | SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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230 | SmramMap[DescIdxMain].RegionState = CommonRegionState;
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231 |
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232 | return EFI_SUCCESS;
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233 | }
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