| 1 | /** @file
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| 2 | HPET register definitions from the IA-PC HPET (High Precision Event Timers)
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| 3 | Specification, Revision 1.0a, October 2004.
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| 4 |
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| 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
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| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 7 |
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| 8 | **/
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| 9 |
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| 10 | #ifndef __HPET_REGISTER_H__
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| 11 | #define __HPET_REGISTER_H__
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| 12 |
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| 13 | ///
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| 14 | /// HPET General Register Offsets
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| 15 | ///
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| 16 | #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
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| 17 | #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
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| 18 | #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
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| 19 |
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| 20 | ///
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| 21 | /// HPET Timer Register Offsets
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| 22 | ///
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| 23 | #define HPET_MAIN_COUNTER_OFFSET 0x0F0
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| 24 | #define HPET_TIMER_CONFIGURATION_OFFSET 0x100
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| 25 | #define HPET_TIMER_COMPARATOR_OFFSET 0x108
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| 26 | #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
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| 27 |
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| 28 | ///
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| 29 | /// Stride between sets of HPET Timer Registers
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| 30 | ///
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| 31 | #define HPET_TIMER_STRIDE 0x20
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| 32 |
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| 33 | #pragma pack(1)
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| 34 |
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| 35 | ///
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| 36 | /// HPET General Capabilities and ID Register
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| 37 | ///
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| 38 | typedef union {
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| 39 | struct {
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| 40 | UINT32 Revision:8;
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| 41 | UINT32 NumberOfTimers:5;
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| 42 | UINT32 CounterSize:1;
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| 43 | UINT32 Reserved0:1;
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| 44 | UINT32 LegacyRoute:1;
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| 45 | UINT32 VendorId:16;
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| 46 | UINT32 CounterClockPeriod:32;
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| 47 | } Bits;
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| 48 | UINT64 Uint64;
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| 49 | } HPET_GENERAL_CAPABILITIES_ID_REGISTER;
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| 50 |
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| 51 | ///
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| 52 | /// HPET General Configuration Register
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| 53 | ///
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| 54 | typedef union {
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| 55 | struct {
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| 56 | UINT32 MainCounterEnable:1;
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| 57 | UINT32 LegacyRouteEnable:1;
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| 58 | UINT32 Reserved0:30;
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| 59 | UINT32 Reserved1:32;
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| 60 | } Bits;
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| 61 | UINT64 Uint64;
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| 62 | } HPET_GENERAL_CONFIGURATION_REGISTER;
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| 63 |
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| 64 | ///
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| 65 | /// HPET Timer Configuration Register
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| 66 | ///
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| 67 | typedef union {
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| 68 | struct {
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| 69 | UINT32 Reserved0:1;
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| 70 | UINT32 LevelTriggeredInterrupt:1;
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| 71 | UINT32 InterruptEnable:1;
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| 72 | UINT32 PeriodicInterruptEnable:1;
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| 73 | UINT32 PeriodicInterruptCapablity:1;
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| 74 | UINT32 CounterSizeCapablity:1;
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| 75 | UINT32 ValueSetEnable:1;
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| 76 | UINT32 Reserved1:1;
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| 77 | UINT32 CounterSizeEnable:1;
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| 78 | UINT32 InterruptRoute:5;
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| 79 | UINT32 MsiInterruptEnable:1;
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| 80 | UINT32 MsiInterruptCapablity:1;
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| 81 | UINT32 Reserved2:16;
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| 82 | UINT32 InterruptRouteCapability;
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| 83 | } Bits;
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| 84 | UINT64 Uint64;
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| 85 | } HPET_TIMER_CONFIGURATION_REGISTER;
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| 86 |
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| 87 | ///
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| 88 | /// HPET Timer MSI Route Register
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| 89 | ///
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| 90 | typedef union {
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| 91 | struct {
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| 92 | UINT32 Value:32;
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| 93 | UINT32 Address:32;
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| 94 | } Bits;
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| 95 | UINT64 Uint64;
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| 96 | } HPET_TIMER_MSI_ROUTE_REGISTER;
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| 97 |
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| 98 | #pragma pack()
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| 99 |
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| 100 | #endif
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