1 | /** @file
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2 | C based implementation of IA32 interrupt handling only
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3 | requiring a minimal assembly interrupt entry point.
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4 |
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5 | Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
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6 | SPDX-License-Identifier: BSD-2-Clause-Patent
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7 |
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8 | **/
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9 |
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10 | #include "CpuDxe.h"
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11 | #include "CpuGdt.h"
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12 |
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13 | //
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14 | // Global descriptor table (GDT) Template
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15 | //
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16 | STATIC GDT_ENTRIES mGdtTemplate = {
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17 | //
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18 | // NULL_SEL
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19 | //
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20 | {
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21 | 0x0, // limit 15:0
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22 | 0x0, // base 15:0
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23 | 0x0, // base 23:16
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24 | 0x0, // type
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25 | 0x0, // limit 19:16, flags
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26 | 0x0, // base 31:24
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27 | },
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28 | //
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29 | // LINEAR_SEL
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30 | //
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31 | {
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32 | 0x0FFFF, // limit 15:0
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33 | 0x0, // base 15:0
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34 | 0x0, // base 23:16
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35 | 0x092, // present, ring 0, data, read/write
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36 | 0x0CF, // page-granular, 32-bit
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37 | 0x0,
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38 | },
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39 | //
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40 | // LINEAR_CODE_SEL
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41 | //
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42 | {
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43 | 0x0FFFF, // limit 15:0
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44 | 0x0, // base 15:0
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45 | 0x0, // base 23:16
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46 | 0x09F, // present, ring 0, code, execute/read, conforming, accessed
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47 | 0x0CF, // page-granular, 32-bit
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48 | 0x0,
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49 | },
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50 | //
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51 | // SYS_DATA_SEL
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52 | //
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53 | {
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54 | 0x0FFFF, // limit 15:0
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55 | 0x0, // base 15:0
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56 | 0x0, // base 23:16
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57 | 0x093, // present, ring 0, data, read/write, accessed
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58 | 0x0CF, // page-granular, 32-bit
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59 | 0x0,
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60 | },
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61 | //
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62 | // SYS_CODE_SEL
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63 | //
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64 | {
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65 | 0x0FFFF, // limit 15:0
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66 | 0x0, // base 15:0
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67 | 0x0, // base 23:16
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68 | 0x09A, // present, ring 0, code, execute/read
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69 | 0x0CF, // page-granular, 32-bit
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70 | 0x0,
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71 | },
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72 | //
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73 | // SYS_CODE16_SEL
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74 | //
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75 | {
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76 | 0x0FFFF, // limit 15:0
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77 | 0x0, // base 15:0
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78 | 0x0, // base 23:16
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79 | 0x09A, // present, ring 0, code, execute/read
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80 | 0x08F, // page-granular, 16-bit
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81 | 0x0, // base 31:24
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82 | },
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83 | //
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84 | // LINEAR_DATA64_SEL
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85 | //
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86 | {
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87 | 0x0FFFF, // limit 15:0
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88 | 0x0, // base 15:0
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89 | 0x0, // base 23:16
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90 | 0x092, // present, ring 0, data, read/write
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91 | 0x0CF, // page-granular, 32-bit
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92 | 0x0,
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93 | },
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94 | //
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95 | // LINEAR_CODE64_SEL
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96 | //
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97 | {
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98 | 0x0FFFF, // limit 15:0
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99 | 0x0, // base 15:0
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100 | 0x0, // base 23:16
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101 | 0x09A, // present, ring 0, code, execute/read
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102 | 0x0AF, // page-granular, 64-bit code
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103 | 0x0, // base (high)
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104 | },
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105 | //
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106 | // SPARE5_SEL
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107 | //
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108 | {
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109 | 0x0, // limit 15:0
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110 | 0x0, // base 15:0
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111 | 0x0, // base 23:16
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112 | 0x0, // type
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113 | 0x0, // limit 19:16, flags
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114 | 0x0, // base 31:24
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115 | },
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116 | };
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117 |
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118 | /**
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119 | Initialize Global Descriptor Table.
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120 |
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121 | **/
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122 | VOID
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123 | InitGlobalDescriptorTable (
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124 | VOID
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125 | )
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126 | {
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127 | #ifndef VBOX
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128 | EFI_STATUS Status;
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129 | #endif
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130 | GDT_ENTRIES *Gdt;
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131 | IA32_DESCRIPTOR Gdtr;
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132 | #ifndef VBOX
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133 | EFI_PHYSICAL_ADDRESS Memory;
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134 | #endif
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135 |
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136 | //
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137 | // Allocate Runtime Data below 4GB for the GDT
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138 | // AP uses the same GDT when it's waken up from real mode so
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139 | // the GDT needs to be below 4GB.
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140 | //
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141 | #ifndef VBOX
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142 | Memory = SIZE_4GB - 1;
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143 | Status = gBS->AllocatePages (
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144 | AllocateMaxAddress,
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145 | EfiRuntimeServicesData,
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146 | EFI_SIZE_TO_PAGES (sizeof (mGdtTemplate)),
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147 | &Memory
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148 | );
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149 | ASSERT_EFI_ERROR (Status);
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150 | ASSERT ((Memory != 0) && (Memory < SIZE_4GB));
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151 | Gdt = (GDT_ENTRIES *) (UINTN) Memory;
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152 | #else
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153 | /*
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154 | * Apples bootloader boot.efi for at least OS X Tiger, Leopard and Snow Leopard
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155 | * relocates runtime regions which doesn't make sense for the GDT as the GDTR is not
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156 | * updated and would point to invalid memory. Allocate the memory as reserved to hopefully
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157 | * keep the bootloaders hands off of it, see also OvmfPkg/PlatformPei/Platform.c
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158 | * (search for PeiServicesAllocatePages()) for a more detailed explanation of a
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159 | * related bug in Apples bootloader.
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160 | */
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161 | Gdt = AllocateReservedPool (sizeof (mGdtTemplate) + 8);
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162 | ASSERT (Gdt != NULL);
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163 | Gdt = ALIGN_POINTER (Gdt, 8);
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164 | #endif
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165 |
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166 | //
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167 | // Initialize all GDT entries
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168 | //
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169 | CopyMem (Gdt, &mGdtTemplate, sizeof (mGdtTemplate));
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170 |
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171 | //
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172 | // Write GDT register
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173 | //
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174 | Gdtr.Base = (UINT32) (UINTN) Gdt;
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175 | Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1);
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176 | AsmWriteGdtr (&Gdtr);
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177 |
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178 | //
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179 | // Update selector (segment) registers base on new GDT
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180 | //
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181 | SetCodeSelector ((UINT16)CPU_CODE_SEL);
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182 | SetDataSelectors ((UINT16)CPU_DATA_SEL);
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183 | }
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