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source: vbox/trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h@ 99404

Last change on this file since 99404 was 99404, checked in by vboxsync, 23 months ago

Devices/EFI/FirmwareNew: Update to edk2-stable202302 and make it build, bugref:4643
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1/** @file
2 Internal header for CpuPageTableLib.
3
4 Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7**/
8
9#ifndef CPU_PAGE_TABLE_H_
10#define CPU_PAGE_TABLE_H_
11
12#include <Base.h>
13#include <Library/BaseLib.h>
14#include <Library/BaseMemoryLib.h>
15#include <Library/DebugLib.h>
16#include <Library/CpuPageTableLib.h>
17
18#define IA32_PE_BASE_ADDRESS_MASK_40 0xFFFFFFFFFF000ull
19#define IA32_PE_BASE_ADDRESS_MASK_39 0xFFFFFFFFFE000ull
20
21#define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)
22
23typedef enum {
24 Pte = 1,
25 Pde = 2,
26 Pdpte = 3,
27 Pml4 = 4,
28 Pml5 = 5
29} IA32_PAGE_LEVEL;
30
31typedef struct {
32 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
33 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
34 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
35 UINT64 Reserved : 58;
36 UINT64 Nx : 1; // No Execute bit
37} IA32_PAGE_COMMON_ENTRY;
38
39///
40/// Format of a non-leaf entry that references a page table entry
41///
42typedef union {
43 struct {
44 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
45 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
46 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
47 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
48 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
49 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
50 UINT64 Available0 : 1; // Ignored
51 UINT64 MustBeZero : 1; // Must Be Zero
52
53 UINT64 Available2 : 4; // Ignored
54
55 UINT64 PageTableBaseAddress : 40; // Page Table Base Address
56 UINT64 Available3 : 11; // Ignored
57 UINT64 Nx : 1; // No Execute bit
58 } Bits;
59 UINT64 Uint64;
60} IA32_PAGE_NON_LEAF_ENTRY;
61
62#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
63
64///
65/// Format of a PML5 Entry (PML5E) that References a PML4 Table
66///
67typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML5E;
68
69///
70/// Format of a PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
71///
72typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML4E;
73
74///
75/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory
76///
77typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDPTE;
78
79///
80/// Format of a Page-Directory Entry that References a Page Table
81///
82typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
83
84///
85/// Format of a leaf entry that Maps a 1-Gbyte or 2-MByte Page
86///
87typedef union {
88 struct {
89 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
90 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
91 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
92 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
93 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
94 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
95 UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
96 UINT64 MustBeOne : 1; // Page Size. Must Be One
97
98 UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
99 UINT64 Available1 : 3; // Ignored
100 UINT64 Pat : 1; // PAT
101
102 UINT64 PageTableBaseAddress : 39; // Page Table Base Address
103 UINT64 Available3 : 7; // Ignored
104 UINT64 ProtectionKey : 4; // Protection key
105 UINT64 Nx : 1; // No Execute bit
106 } Bits;
107 UINT64 Uint64;
108} IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;
109#define IA32_PLEB_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_39)
110
111///
112/// Format of a Page-Directory Entry that Maps a 2-MByte Page
113///
114typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDE_2M;
115
116///
117/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
118///
119typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
120
121///
122/// Format of a Page-Table Entry that Maps a 4-KByte Page
123///
124typedef union {
125 struct {
126 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
127 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
128 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
129 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
130 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
131 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
132 UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
133 UINT64 Pat : 1; // PAT
134
135 UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
136 UINT64 Available1 : 3; // Ignored
137
138 UINT64 PageTableBaseAddress : 40; // Page Table Base Address
139 UINT64 Available3 : 7; // Ignored
140 UINT64 ProtectionKey : 4; // Protection key
141 UINT64 Nx : 1; // No Execute bit
142 } Bits;
143 UINT64 Uint64;
144} IA32_PTE_4K;
145#define IA32_PTE4K_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
146
147///
148/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory (32bit PAE specific)
149///
150typedef union {
151 struct {
152 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
153 UINT64 MustBeZero : 2; // Must Be Zero
154 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
155 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
156 UINT64 MustBeZero2 : 4; // Must Be Zero
157
158 UINT64 Available : 3; // Ignored
159
160 UINT64 PageTableBaseAddress : 40; // Page Table Base Address
161 UINT64 MustBeZero3 : 12; // Must Be Zero
162 } Bits;
163 UINT64 Uint64;
164} IA32_PDPTE_PAE;
165
166typedef union {
167 IA32_PAGE_NON_LEAF_ENTRY Pnle; // To access Pml5, Pml4, Pdpte and Pde.
168 IA32_PML5E Pml5;
169 IA32_PML4E Pml4;
170 IA32_PDPTE Pdpte;
171 IA32_PDE Pde;
172
173 IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE PleB; // to access Pdpte1G and Pde2M.
174 IA32_PDPTE_1G Pdpte1G;
175 IA32_PDE_2M Pde2M;
176
177 IA32_PTE_4K Pte4K;
178
179 IA32_PDPTE_PAE PdptePae;
180 IA32_PAGE_COMMON_ENTRY Pce; // To access all common bits in above entries.
181
182 UINT64 Uint64;
183 UINTN Uintn;
184} IA32_PAGING_ENTRY;
185
186/**
187 Return TRUE when the page table entry is a leaf entry that points to the physical address memory.
188 Return FALSE when the page table entry is a non-leaf entry that points to the page table entries.
189
190 @param[in] PagingEntry Pointer to the page table entry.
191 @param[in] Level Page level where the page table entry resides in.
192
193 @retval TRUE It's a leaf entry.
194 @retval FALSE It's a non-leaf entry.
195**/
196BOOLEAN
197IsPle (
198 IN IA32_PAGING_ENTRY *PagingEntry,
199 IN UINTN Level
200 );
201
202/**
203 Return the attribute of a 2M/1G page table entry.
204
205 @param[in] PleB Pointer to a 2M/1G page table entry.
206 @param[in] ParentMapAttribute Pointer to the parent attribute.
207
208 @return Attribute of the 2M/1G page table entry.
209**/
210UINT64
211PageTableLibGetPleBMapAttribute (
212 IN IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE *PleB,
213 IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
214 );
215
216/**
217 Return the attribute of a non-leaf page table entry.
218
219 @param[in] Pnle Pointer to a non-leaf page table entry.
220 @param[in] ParentMapAttribute Pointer to the parent attribute.
221
222 @return Attribute of the non-leaf page table entry.
223**/
224UINT64
225PageTableLibGetPnleMapAttribute (
226 IN IA32_PAGE_NON_LEAF_ENTRY *Pnle,
227 IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
228 );
229
230#endif
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