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source: vbox/trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c@ 108794

Last change on this file since 108794 was 108794, checked in by vboxsync, 2 weeks ago

Devices/EFI/FirmwareNew: Merge edk2-stable202502 from the vendor branch and make it build for the important platforms, bugref:4643
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1/** @file
2Provides services to access SMRAM Save State Map
3
4Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
5Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
6SPDX-License-Identifier: BSD-2-Clause-Patent
7
8**/
9
10#include "MmSaveState.h"
11#include <Register/Amd/SmramSaveStateMap.h>
12#include <Library/BaseLib.h>
13#include <Register/Amd/Msr.h>
14
15#define AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
16#define AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX 2
17
18// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
19#define MM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
20
21//
22// Lookup table used to retrieve the widths and offsets associated with each
23// supported EFI_MM_SAVE_STATE_REGISTER value
24//
25// Per AMD64 Architecture Programmer's Manual Volume 2: System
26// Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64
27// architecture does not use the legacy SMM state-save area format
28// (Table 10-2) for 32-bit SMRAM Save State Map.
29//
30CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] = {
31 { 0, 0, 0, 0, 0, FALSE }, // Reserved
32
33 //
34 // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
35 //
36 { 0, 4, 0, MM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
37
38 //
39 // CPU Save State registers defined in PI SMM CPU Protocol.
40 //
41 { 0, 8, 0, MM_CPU_OFFSET (x64._GDTRBaseLoDword), MM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4
42 { 0, 8, 0, MM_CPU_OFFSET (x64._IDTRBaseLoDword), MM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5
43 { 0, 8, 0, MM_CPU_OFFSET (x64._LDTRBaseLoDword), MM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6
44 { 0, 2, 0, MM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7
45 { 0, 2, 0, MM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8
46 { 0, 4, 0, MM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9
47 { 0, 0, 0, 0, 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10
48 { 0, 2, 0, MM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_ES = 20
49 { 0, 2, 0, MM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CS = 21
50 { 0, 2, 0, MM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_SS = 22
51 { 0, 2, 0, MM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DS = 23
52 { 0, 2, 0, MM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_FS = 24
53 { 0, 2, 0, MM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_GS = 25
54 { 0, 2, 0, MM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26
55 { 0, 2, 0, MM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27
56 { 0, 8, 0, MM_CPU_OFFSET (x64._DR7), MM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR7 = 28
57 { 0, 8, 0, MM_CPU_OFFSET (x64._DR6), MM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_DR6 = 29
58 { 0, 8, 0, MM_CPU_OFFSET (x64._R8), MM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R8 = 30
59 { 0, 8, 0, MM_CPU_OFFSET (x64._R9), MM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R9 = 31
60 { 0, 8, 0, MM_CPU_OFFSET (x64._R10), MM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R10 = 32
61 { 0, 8, 0, MM_CPU_OFFSET (x64._R11), MM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R11 = 33
62 { 0, 8, 0, MM_CPU_OFFSET (x64._R12), MM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R12 = 34
63 { 0, 8, 0, MM_CPU_OFFSET (x64._R13), MM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R13 = 35
64 { 0, 8, 0, MM_CPU_OFFSET (x64._R14), MM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R14 = 36
65 { 0, 8, 0, MM_CPU_OFFSET (x64._R15), MM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_R15 = 37
66 { 0, 8, 0, MM_CPU_OFFSET (x64._RAX), MM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RAX = 38
67 { 0, 8, 0, MM_CPU_OFFSET (x64._RBX), MM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39
68 { 0, 8, 0, MM_CPU_OFFSET (x64._RCX), MM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBX = 39
69 { 0, 8, 0, MM_CPU_OFFSET (x64._RDX), MM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDX = 41
70 { 0, 8, 0, MM_CPU_OFFSET (x64._RSP), MM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSP = 42
71 { 0, 8, 0, MM_CPU_OFFSET (x64._RBP), MM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RBP = 43
72 { 0, 8, 0, MM_CPU_OFFSET (x64._RSI), MM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RSI = 44
73 { 0, 8, 0, MM_CPU_OFFSET (x64._RDI), MM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RDI = 45
74 { 0, 8, 0, MM_CPU_OFFSET (x64._RIP), MM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RIP = 46
75
76 { 0, 8, 0, MM_CPU_OFFSET (x64._RFLAGS), MM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51
77 { 0, 8, 0, MM_CPU_OFFSET (x64._CR0), MM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR0 = 52
78 { 0, 8, 0, MM_CPU_OFFSET (x64._CR3), MM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR3 = 53
79 { 0, 8, 0, MM_CPU_OFFSET (x64._CR4), MM_CPU_OFFSET (x64._CR4) + 4, FALSE }, // EFI_MM_SAVE_STATE_REGISTER_CR4 = 54
80 { 0, 0, 0, 0, 0, FALSE }
81};
82
83/**
84 Read a save state register on the target processor. If this function
85 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
86 MM Save State register.
87
88 @param[in] CpuIndex The index of the CPU to read the Save State register.
89 The value must be between 0 and the NumberOfCpus field in
90 the System Management System Table (SMST).
91 @param[in] Register The MM Save State register to read.
92 @param[in] Width The number of bytes to read from the CPU save state.
93 @param[out] Buffer Upon return, this holds the CPU register value read
94 from the save state.
95
96 @retval EFI_SUCCESS The register was read from Save State.
97 @retval EFI_INVALID_PARAMTER Buffer is NULL.
98 @retval EFI_UNSUPPORTED This function does not support reading Register.
99 @retval EFI_NOT_FOUND If desired Register not found.
100**/
101EFI_STATUS
102EFIAPI
103MmSaveStateReadRegister (
104 IN UINTN CpuIndex,
105 IN EFI_MM_SAVE_STATE_REGISTER Register,
106 IN UINTN Width,
107 OUT VOID *Buffer
108 )
109{
110 UINT32 SmmRevId;
111 EFI_MM_SAVE_STATE_IO_INFO *IoInfo;
112 AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
113 UINT8 DataWidth;
114
115 // Read CPU State
116 CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)gMmst->CpuSaveState[CpuIndex];
117
118 // Check for special EFI_MM_SAVE_STATE_REGISTER_LMA
119 if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
120 // Only byte access is supported for this register
121 if (Width != 1) {
122 return EFI_INVALID_PARAMETER;
123 }
124
125 *(UINT8 *)Buffer = MmSaveStateGetRegisterLma ();
126
127 return EFI_SUCCESS;
128 }
129
130 // Check for special EFI_MM_SAVE_STATE_REGISTER_IO
131 if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
132 //
133 // Get SMM Revision ID
134 //
135 MmSaveStateReadRegisterByIndex (CpuIndex, AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
136
137 //
138 // See if the CPU supports the IOMisc register in the save state
139 //
140 if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) {
141 return EFI_NOT_FOUND;
142 }
143
144 // Check if IO Restart Dword [IO Trap] is valid or not using bit 1.
145 if (!(CpuSaveState->x64.IO_DWord & 0x02u)) {
146 return EFI_NOT_FOUND;
147 }
148
149 // Zero the IoInfo structure that will be returned in Buffer
150 IoInfo = (EFI_MM_SAVE_STATE_IO_INFO *)Buffer;
151 ZeroMem (IoInfo, sizeof (EFI_MM_SAVE_STATE_IO_INFO));
152
153 IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u);
154
155 if (CpuSaveState->x64.IO_DWord & 0x10u) {
156 IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT8;
157 DataWidth = 0x01u;
158 } else if (CpuSaveState->x64.IO_DWord & 0x20u) {
159 IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT16;
160 DataWidth = 0x02u;
161 } else {
162 IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT32;
163 DataWidth = 0x04u;
164 }
165
166 if (CpuSaveState->x64.IO_DWord & 0x01u) {
167 IoInfo->IoType = EFI_MM_SAVE_STATE_IO_TYPE_INPUT;
168 } else {
169 IoInfo->IoType = EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT;
170 }
171
172 if ((IoInfo->IoType == EFI_MM_SAVE_STATE_IO_TYPE_INPUT) || (IoInfo->IoType == EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT)) {
173 MmSaveStateReadRegister (CpuIndex, EFI_MM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData);
174 }
175
176 return EFI_SUCCESS;
177 }
178
179 // Convert Register to a register lookup table index
180 return MmSaveStateReadRegisterByIndex (CpuIndex, MmSaveStateGetRegisterIndex (Register, AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX), Width, Buffer);
181}
182
183/**
184 Writes a save state register on the target processor. If this function
185 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
186 MM save state register.
187
188 @param[in] CpuIndex The index of the CPU to write the MM Save State. The
189 value must be between 0 and the NumberOfCpus field in
190 the System Management System Table (SMST).
191 @param[in] Register The MM Save State register to write.
192 @param[in] Width The number of bytes to write to the CPU save state.
193 @param[in] Buffer Upon entry, this holds the new CPU register value.
194
195 @retval EFI_SUCCESS The register was written to Save State.
196 @retval EFI_INVALID_PARAMTER Buffer is NULL.
197 @retval EFI_UNSUPPORTED This function does not support writing Register.
198 @retval EFI_NOT_FOUND If desired Register not found.
199**/
200EFI_STATUS
201EFIAPI
202MmSaveStateWriteRegister (
203 IN UINTN CpuIndex,
204 IN EFI_MM_SAVE_STATE_REGISTER Register,
205 IN UINTN Width,
206 IN CONST VOID *Buffer
207 )
208{
209 UINTN RegisterIndex;
210 AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState;
211
212 //
213 // Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored
214 //
215 if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
216 return EFI_SUCCESS;
217 }
218
219 //
220 // Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported
221 //
222 if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
223 return EFI_NOT_FOUND;
224 }
225
226 //
227 // Convert Register to a register lookup table index
228 //
229 RegisterIndex = MmSaveStateGetRegisterIndex (Register, AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX);
230 if (RegisterIndex == 0) {
231 return EFI_NOT_FOUND;
232 }
233
234 CpuSaveState = gMmst->CpuSaveState[CpuIndex];
235
236 //
237 // Do not write non-writable SaveState, because it will cause exception.
238 //
239 if (!mCpuWidthOffset[RegisterIndex].Writeable) {
240 return EFI_UNSUPPORTED;
241 }
242
243 //
244 // If 64-bit mode width is zero, then the specified register can not be accessed
245 //
246 if (mCpuWidthOffset[RegisterIndex].Width64 == 0) {
247 return EFI_NOT_FOUND;
248 }
249
250 //
251 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
252 //
253 if (Width > mCpuWidthOffset[RegisterIndex].Width64) {
254 return EFI_INVALID_PARAMETER;
255 }
256
257 //
258 // Write lower 32-bits of SMM State register
259 //
260 CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
261 if (Width >= 4) {
262 //
263 // Write upper 32-bits of SMM State register
264 //
265 CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
266 }
267
268 return EFI_SUCCESS;
269}
270
271/**
272 Returns LMA value of the Processor.
273
274 @retval UINT8 returns LMA bit value.
275**/
276UINT8
277MmSaveStateGetRegisterLma (
278 VOID
279 )
280{
281 UINT32 LMAValue;
282
283 MSR_IA32_EFER_REGISTER Msr;
284
285 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
286 LMAValue = Msr.Bits.LMA;
287 if (LMAValue) {
288 return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
289 }
290
291 //
292 // AMD64 processors support EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT only
293 //
294 return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
295}
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