UefiCpuPkg.dec@ 109019

Last change on this file since 109019 was 108794, checked in by vboxsync, 4 weeks ago
Devices/EFI/FirmwareNew: Merge edk2-stable202502 from the vendor branch and make it build for the important platforms, bugref:4643
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1	## @file UefiCpuPkg.dec
2	# This Package provides UEFI compatible CPU modules and libraries.
3	#
4	# Copyright (c) 2007 - 2024, Intel Corporation. All rights reserved.<BR>
5	# Copyright (C) 2023 - 2024, Advanced Micro Devices, Inc. All rights reserved.<BR>
6	# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
7	#
8	# SPDX-License-Identifier: BSD-2-Clause-Patent
9	#
10	##
11
12	[Defines]
13	DEC_SPECIFICATION = 0x00010005
14	PACKAGE_NAME = UefiCpuPkg
15	PACKAGE_UNI_FILE = UefiCpuPkg.uni
16	PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
17	PACKAGE_VERSION = 0.90
18
19	[Includes]
20	Include
21
22	[LibraryClasses]
23	## @libraryclass Defines some routines that are used to register/manage/program
24	## CPU features.
25	##
26	RegisterCpuFeaturesLib\|Include/Library/RegisterCpuFeaturesLib.h
27
28	[LibraryClasses.IA32, LibraryClasses.X64]
29	## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
30	##
31	MtrrLib\|Include/Library/MtrrLib.h
32
33	## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
34	##
35	LocalApicLib\|Include/Library/LocalApicLib.h
36
37	## @libraryclass Provides platform specific initialization functions in the SEC phase.
38	##
39	PlatformSecLib\|Include/Library/PlatformSecLib.h
40
41	## @libraryclass Public include file for the SMM CPU Platform Hook Library.
42	##
43	SmmCpuPlatformHookLib\|Include/Library/SmmCpuPlatformHookLib.h
44
45	## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
46	##
47	SmmCpuFeaturesLib\|Include/Library/SmmCpuFeaturesLib.h
48
49	## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
50	##
51	MpInitLib\|Include/Library/MpInitLib.h
52
53	## @libraryclass Provides function to support CcExit processing.
54	CcExitLib\|Include/Library/CcExitLib.h
55
56	## @libraryclass Provides functions for Tdx Measurement processing
57	TdxMeasurementLib\|Include/Library/TdxMeasurementLib.h
58
59	## @libraryclass Provides function to support AmdSvsm processing.
60	AmdSvsmLib\|Include/Library/AmdSvsmLib.h
61
62	## @libraryclass Provides function to get CPU cache information.
63	CpuCacheInfoLib\|Include/Library/CpuCacheInfoLib.h
64
65	## @libraryclass Provides function for loading microcode.
66	MicrocodeLib\|Include/Library/MicrocodeLib.h
67
68	## @libraryclass Provides function for manipulating x86 paging structures.
69	CpuPageTableLib\|Include/Library/CpuPageTableLib.h
70
71	## @libraryclass Provides functions for manipulating smram savestate registers.
72	MmSaveStateLib\|Include/Library/MmSaveStateLib.h
73
74	## @libraryclass Provides functions for SMM CPU Sync Operation.
75	SmmCpuSyncLib\|Include/Library/SmmCpuSyncLib.h
76
77	## @libraryclass Provides functions for SMM Relocation Operation.
78	SmmRelocationLib\|Include/Library/SmmRelocationLib.h
79
80	[LibraryClasses.RISCV64]
81	## @libraryclass Provides function to initialize the FPU.
82	RiscVFpuLib\|Include/Library/BaseRiscVFpuLib.h
83	## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
84	##
85	RiscVMmuLib\|Include/Library/BaseRiscVMmuLib.h
86
87	[LibraryClasses.LoongArch64]
88	## @libraryclass Provides functions for the memory management unit.
89	CpuMmuLib\|Include/Library/CpuMmuLib.h
90
91	[Guids]
92	gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
93	gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
94
95	## Include/Guid/CpuFeaturesSetDone.h
96	gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
97
98	## Include/Guid/CpuFeaturesInitDone.h
99	gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
100
101	## Include/Guid/MicrocodePatchHob.h
102	gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
103
104	## Include/Guid/SmmBaseHob.h
105	gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
106
107	## Include/Guid/MpInformation2.h
108	gMpInformation2HobGuid = { 0x417a7f64, 0xf4e9, 0x4b32, {0x84, 0x6a, 0x5c, 0xc4, 0xd8, 0x62, 0x18, 0x79 }}
109
110	## Include/Guid/ProcessorResourceHob.h
111	gProcessorResourceHobGuid = { 0xb855c7fe, 0xa758, 0x701f, { 0xa7, 0x30, 0x87, 0xf3, 0x9c, 0x03, 0x46, 0x7e }}
112	#
113	## Include/Guid/GhcbApicIds.h
114	gGhcbApicIdsGuid = { 0xbc964338, 0xee39, 0x4fc8, { 0xa2, 0x24, 0x10, 0x10, 0x8b, 0x17, 0x80, 0x1b }}
115
116	## Include/Guid/MmUnblockRegion.h
117	gMmUnblockRegionHobGuid = { 0x7c316fb3, 0x849e, 0x4ee7, { 0x87, 0xfc, 0x16, 0x2d, 0x0b, 0x03, 0x42, 0xbf }}
118
119	## Include/Guid/MmProfileData.h
120	gMmProfileDataHobGuid = { 0x26ef081d, 0x19b0, 0x4c42, { 0xa2, 0x57, 0xa7, 0xf5, 0x9f, 0x8b, 0xd0, 0x38 }}
121
122	## Include/Guid/MmCpuSyncConfig.h
123	gMmCpuSyncConfigHobGuid = { 0x8b90bd26, 0xe4f9, 0x45c2, { 0x92, 0xa2, 0x9e, 0xac, 0xe6, 0x0e, 0x9d, 0xcc }}
124
125	# Include/Guid/MmAcpiS3Enable.h
126	gMmAcpiS3EnableHobGuid = { 0xe7402821, 0x2654, 0x4c1b, { 0x99, 0x0e, 0x04, 0x8f, 0x8d, 0x82, 0xcf, 0x67 }}
127
128	[Protocols]
129	## Include/Protocol/SmmCpuService.h
130	gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
131	gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
132
133	## Include/Protocol/SmMonitorInit.h
134	gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
135
136	[Protocols.RISCV64]
137	#
138	# Protocols defined for RISC-V systems
139	#
140	## Include/Protocol/RiscVBootProtocol.h
141	gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
142
143	#
144	# [Error.gUefiCpuPkgTokenSpaceGuid]
145	# 0x80000001 \| Invalid value provided.
146	#
147
148	[Ppis]
149	gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
150
151	## Include/Ppi/ShadowMicrocode.h
152	gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
153
154	## Include/Ppi/RepublishSecPpi.h
155	gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
156
157	[PcdsFeatureFlag]
158	## Indicates if SMM Profile will be enabled.
159	# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
160	# In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
161	# In IA32 build, the page table memory is not marked as read-only when it is enabled.
162	# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
163	# TRUE - SMM Profile will be enabled.<BR>
164	# FALSE - SMM Profile will be disabled.<BR>
165	# @Prompt Enable SMM Profile.
166	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable\|FALSE\|BOOLEAN\|0x32132109
167
168	## Indicates if the SMM profile log buffer is a ring buffer.
169	# If disabled, no additional log can be done when the buffer is full.<BR><BR>
170	# TRUE - the SMM profile log buffer is a ring buffer.<BR>
171	# FALSE - the SMM profile log buffer is a normal buffer.<BR>
172	# @Prompt The SMM profile log buffer is a ring buffer.
173	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer\|FALSE\|BOOLEAN\|0x3213210a
174
175	## Indicates if SMM Startup AP in a blocking fashion.
176	# TRUE - SMM Startup AP in a blocking fashion.<BR>
177	# FALSE - SMM Startup AP in a non-blocking fashion.<BR>
178	# @Prompt SMM Startup AP in a blocking fashion.
179	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp\|FALSE\|BOOLEAN\|0x32132108
180
181	## Indicates if SMM Stack Guard will be enabled.
182	# If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
183	# TRUE - SMM Stack Guard will be enabled.<BR>
184	# FALSE - SMM Stack Guard will be disabled.<BR>
185	# @Prompt Enable SMM Stack Guard.
186	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard\|TRUE\|BOOLEAN\|0x1000001C
187
188	## Indicates if BSP election in SMM will be enabled.
189	# If enabled, a BSP will be dynamically elected among all processors in each SMI.
190	# Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
191	# TRUE - BSP election in SMM will be enabled.<BR>
192	# FALSE - BSP election in SMM will be disabled.<BR>
193	# @Prompt Enable BSP election in SMM.
194	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection\|TRUE\|BOOLEAN\|0x32132106
195
196	## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
197	# TRUE - SMM CPU hot-plug will be enabled.<BR>
198	# FALSE - SMM CPU hot-plug will be disabled.<BR>
199	# @Prompt SMM CPU hot-plug.
200	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport\|FALSE\|BOOLEAN\|0x3213210C
201
202	## Indicates if SMM Debug will be enabled.
203	# If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
204	# TRUE - SMM Debug will be enabled.<BR>
205	# FALSE - SMM Debug will be disabled.<BR>
206	# @Prompt Enable SMM Debug.
207	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug\|FALSE\|BOOLEAN\|0x1000001B
208
209	## Indicates if lock SMM Feature Control MSR.<BR><BR>
210	# TRUE - SMM Feature Control MSR will be locked.<BR>
211	# FALSE - SMM Feature Control MSR will not be locked.<BR>
212	# @Prompt Lock SMM Feature Control MSR.
213	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock\|TRUE\|BOOLEAN\|0x3213210B
214
215	## Indicates if SMRR will be enabled.<BR><BR>
216	# TRUE - SMRR will be enabled.<BR>
217	# FALSE - SMRR will not be enabled.<BR>
218	# @Prompt Enable SMRR.
219	gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable\|TRUE\|BOOLEAN\|0x3213210D
220
221	## Indicates if SmmFeatureControl will be enabled.<BR><BR>
222	# TRUE - SmmFeatureControl will be enabled.<BR>
223	# FALSE - SmmFeatureControl will not be enabled.<BR>
224	# @Prompt Support SmmFeatureControl.
225	gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable\|TRUE\|BOOLEAN\|0x32132110
226
227	## Indicates if SMM perf logging in APs will be enabled.<BR><BR>
228	# TRUE - SMM perf logging in APs will be enabled.<BR>
229	# FALSE - SMM perf logging in APs will not be enabled.<BR>
230	# @Prompt Enable SMM perf logging in APs.
231	gUefiCpuPkgTokenSpaceGuid.PcdSmmApPerfLogEnable\|TRUE\|BOOLEAN\|0x32132114
232
233	[PcdsFixedAtBuild]
234	## List of exception vectors which need switching stack.
235	# This PCD will only take into effect if PcdCpuStackGuard is enabled.
236	# By default exception #DD(8), #PF(14) are supported.
237	# @Prompt Specify exception vectors which need switching stack.
238	gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList\|{0x08, 0x0E}\|VOID*\|0x30002000
239
240	## Size of good stack for an exception.
241	# This PCD will only take into effect if PcdCpuStackGuard is enabled.
242	# @Prompt Specify size of good stack of exception which need switching stack.
243	gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize\|2048\|UINT32\|0x30002001
244
245	## Count of pre allocated SMM MP tokens per chunk.
246	# @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
247	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk\|64\|UINT32\|0x30002002
248
249	## Area of memory where the SEV-ES work area block lives.
250	# @Prompt Configure the SEV-ES work area base
251	gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase\|0x0\|UINT32\|0x30002005
252
253	## Size of teh area of memory where the SEV-ES work area block lives.
254	# @Prompt Configure the SEV-ES work area base
255	gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize\|0x0\|UINT32\|0x30002006
256
257	## Determining APs' first-time wakeup by SIPI or INIT-SIPI-SIPI.
258	# Following a power-up or RESET of an MP system, The APs complete a
259	# minimal self-configuration, then wait for a startup signal (a SIPI
260	# message) from the BSP processor.
261	#
262	# TRUE - Broadcast SIPI.
263	# FALSE - Broadcast INIT-SIPI-SIPI.
264	#
265	# @Prompt BSP Broadcast Method for the first-time wakeup of APs
266	gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi\|TRUE\|BOOLEAN\|0x30002007
267
268	## The max mapping address in page table before Temp Ram Exit.
269	# After physical memory is initialized and before Temp Ram Exit, the physical memory is in UC state.
270	# The PCD controls the page table max mapping address in physical memory before Temp Ram Exit
271	# because creating a big page table in UC physical memory to cover the entire memory space
272	# is slow. The value of 0xFFFFFFFFFFFFFFFF, then firmware will map entire physical address space.
273	# @Prompt Configure max mapping address in page table before Temp Ram Exit.
274	gUefiCpuPkgTokenSpaceGuid.PcdMaxMappingAddressBeforeTempRamExit\|0xFFFFFFFFFFFFFFFF\|UINT64\|0x30002008
275
276	[PcdsFixedAtBuild, PcdsPatchableInModule]
277	## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
278	# @Prompt Configure base address of CPU Local APIC
279	# @Expression 0x80000001 \| (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
280	gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\|0xfee00000\|UINT32\|0x00000001
281
282	## Specifies delay value in microseconds after sending out an INIT IPI.
283	# @Prompt Configure delay value after send an INIT IPI
284	gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds\|10000\|UINT32\|0x30000002
285
286	## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
287	## aligns the address on a 4-KByte boundary.
288	# @Prompt Configure stack size for Application Processor (AP)
289	gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize\|0x8000\|UINT32\|0x00000003
290
291	## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
292	# @Prompt Stack size in the temporary RAM.
293	gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize\|0\|UINT32\|0x10001003
294
295	## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
296	# @Prompt SMM profile data buffer size.
297	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize\|0x600000\|UINT32\|0x32132107
298
299	## Specifies stack size in bytes for each processor in SMM.
300	# @Prompt Processor stack size in SMM.
301	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize\|0x2000\|UINT32\|0x32132105
302
303	## Specifies shadow stack size in bytes for each processor in SMM.
304	# @Prompt Processor shadow stack size in SMM.
305	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize\|0x2000\|UINT32\|0x3213210E
306
307	## Indicates if SMM Code Access Check is enabled.
308	# If enabled, the SMM handler cannot execute the code outside SMM regions.
309	# This PCD is suggested to TRUE in production image.<BR><BR>
310	# TRUE - SMM Code Access Check will be enabled.<BR>
311	# FALSE - SMM Code Access Check will be disabled.<BR>
312	# @Prompt SMM Code Access Check.
313	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable\|TRUE\|BOOLEAN\|0x60000013
314
315	## Specifies the number of variable MTRRs reserved for OS use. The default number of
316	# MTRRs reserved for OS use is 2.
317	# @Prompt Number of reserved variable MTRRs.
318	gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs\|0x2\|UINT32\|0x00000015
319
320	## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
321	# @Prompt STM exception stack size.
322	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize\|0x1000\|UINT32\|0x32132111
323
324	## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
325	# @Prompt MSEG size.
326	gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize\|0x200000\|UINT32\|0x32132112
327
328	## Specifies the supported CPU features bit in array.
329	# @Prompt Supported CPU features.
330	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport\|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}\|VOID*\|0x00000016
331
332	## Specifies if CPU features will be initialized after SMM relocation.
333	# @Prompt If CPU features will be initialized after SMM relocation.
334	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation\|FALSE\|BOOLEAN\|0x0000001C
335
336	## Specifies if CPU features will be initialized during S3 resume.
337	# @Prompt If CPU features will be initialized during S3 resume.
338	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume\|TRUE\|BOOLEAN\|0x0000001D
339
340	## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
341	# TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
342	# Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
343	# 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
344	# Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
345	# @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
346	gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency\|24000000\|UINT64\|0x32132113
347
348	## Specifies the periodic interval value in microseconds for the status check
349	# of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
350	# mode in DXE phase.
351	# @Prompt Periodic interval value in microseconds for AP status check in DXE.
352	gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds\|100000\|UINT32\|0x0000001E
353
354	[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
355	## Specifies max supported number of Logical Processors.
356	# @Prompt Configure max supported number of Logical Processors
357	gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber\|64\|UINT32\|0x00000002
358	## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
359	# @Prompt Timeout for the BSP to detect all APs for the first time.
360	gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds\|50000\|UINT32\|0x00000004
361	## Specifies the number of Logical Processors that are available in the
362	# preboot environment after platform reset, including BSP and APs. Possible
363	# values:<BR><BR>
364	# zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
365	# PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
366	# detection by the BSP.<BR>
367	# nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
368	# AP detection finishes only when the detected CPU count
369	# (BSP plus APs) reaches the value of
370	# PcdCpuBootLogicalProcessorNumber, regardless of how long
371	# that takes.<BR>
372	# @Prompt Number of Logical Processors available after platform reset.
373	gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber\|0\|UINT32\|0x00000008
374	## Specifies the base address of the first microcode Patch in the microcode Region.
375	# @Prompt Microcode Region base address.
376	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress\|0x0\|UINT64\|0x00000005
377	## Specifies the size of the microcode Region.
378	# @Prompt Microcode Region size.
379	gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\|0x0\|UINT64\|0x00000006
380	## Specifies the AP wait loop state during POST phase.
381	# The value is defined as below.<BR><BR>
382	# 1: Place AP in the Hlt-Loop state.<BR>
383	# 2: Place AP in the Mwait-Loop state.<BR>
384	# 3: Place AP in the Run-Loop state.<BR>
385	# @Prompt The AP wait loop state.
386	# @ValidRange 0x80000001 \| 1 - 3
387	gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode\|1\|UINT8\|0x60008006
388	## Specifies the AP target C-state for Mwait during POST phase.
389	# The default value 0 means C1 state.
390	# The value is defined as below.<BR><BR>
391	# @Prompt The specified AP target C-state for Mwait.
392	gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate\|0\|UINT8\|0x00000007
393
394	## Specifies the 1st timeout value in microseconds for the BSP/AP in SMM to wait for one another to enter SMM.
395	# @Prompt The 1st BSP/AP synchronization timeout value in SMM.
396	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout\|1000000\|UINT64\|0x32132104
397
398	## Specifies the 2nd timeout value in microseconds for the BSP/AP in SMM to wait for one another to enter SMM.
399	# @Prompt The 2nd BSP/AP synchronization timeout value in SMM.
400	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout2\|1000000\|UINT64\|0x32132115
401
402	## Indicates the CPU synchronization method used when processing an SMI.
403	# 0x00 - Traditional CPU synchronization method.<BR>
404	# 0x01 - Relaxed CPU synchronization method.<BR>
405	# @Prompt SMM CPU Synchronization Method.
406	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode\|0x00\|UINT8\|0x60000014
407
408	## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
409	# @Prompt The encoded values for target duty cycle modulation.
410	# @ValidRange 0x80000001 \| 0 - 15
411	gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle\|0x0\|UINT8\|0x0000001A
412
413	## Indicates if the current boot is a power-on reset.<BR><BR>
414	# TRUE - Current boot is a power-on reset.<BR>
415	# FALSE - Current boot is not a power-on reset.<BR>
416	# @Prompt Current boot is a power-on reset.
417	gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset\|FALSE\|BOOLEAN\|0x0000001B
418
419	## This PCD indicates whether CPU processor trace is enabled on BSP only when CPU processor trace is enabled.<BR><BR>
420	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
421	# TRUE - CPU processor trace is enabled on BSP only.<BR>
422	# FASLE - CPU processor trace is enabled on all CPU.<BR>
423	# @Prompt Enable CPU processor trace only on BSP.
424	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceBspOnly\|FALSE\|BOOLEAN\|0x60000019
425
426	## This PCD indicates if enable performance collecting when CPU processor trace is enabled.<BR><BR>
427	# CYC/TSC timing packets will be generated to collect performance data if this PCD is TRUE.
428	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
429	# TRUE - Performance collecting will be enabled in processor trace.<BR>
430	# FASLE - Performance collecting will be disabled in processor trace.<BR>
431	# @Prompt Enable performance collecting when processor trace is enabled.
432	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting\|FALSE\|BOOLEAN\|0x60000020
433
434	[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
435	## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
436	# MMIO access is always allowed regardless of the value of this PCD.
437	# Loose of such restriction is only required by RAS components in X64 platforms.
438	# The PCD value is considered as constantly TRUE in IA32 platforms.
439	# When the PCD value is TRUE, page table is initialized to cover all memory spaces
440	# and the memory occupied by page table is protected by page table itself as read-only.
441	# In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
442	# In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
443	# (PcdHeapGuardPropertyMask in MdeModulePkg).
444	# In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
445	# or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
446	# TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
447	# FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
448	# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
449	gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess\|TRUE\|BOOLEAN\|0x3213210F
450
451	[PcdsFixedAtBuild.RISCV64]
452	## Indicate the maximum SATP mode allowed.
453	# 0 - Bare mode.
454	# 8 - 39bit mode.
455	# 9 - 48bit mode.
456	# 10 - 57bit mode.
457	gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode\|10\|UINT32\|0x60000021
458
459	[PcdsFixedAtBuild.LOONGARCH64, PcdsPatchableInModule.LOONGARCH64, PcdsDynamic.LOONGARCH64, PcdsDynamicEx.LOONGARCH64]
460	## This PCD Contains the pointer to a CPU exception vector base address.
461	# @Prompt The pointer to a CPU exception vector base address.
462	gUefiCpuPkgTokenSpaceGuid.PcdLoongArchExceptionVectorBaseAddress\|0x0\|UINT64\|0x60000022
463
464	[PcdsDynamic, PcdsDynamicEx]
465	## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
466	# @Prompt The pointer to a CPU S3 data buffer.
467	# @ValidList 0x80000001 \| 0
468	gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress\|0x0\|UINT64\|0x60000010
469
470	## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
471	# @Prompt The pointer to CPU Hot Plug Data.
472	# @ValidList 0x80000001 \| 0
473	gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress\|0x0\|UINT64\|0x60000011
474
475	## Indicates processor feature capabilities, each bit corresponding to a specific feature.
476	# @Prompt Processor feature capabilities.
477	# @ValidList 0x80000001 \| 0
478	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000018
479
480	## As input, specifies user's desired settings for enabling/disabling processor features.
481	## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
482	# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
483	# @ValidList 0x80000001 \| 0
484	gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting\|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\|VOID*\|0x00000019
485
486	## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
487	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
488	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
489	# Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
490	# 0x0 - 4K.<BR>
491	# 0x1 - 8K.<BR>
492	# 0x2 - 16K.<BR>
493	# 0x3 - 32K.<BR>
494	# 0x4 - 64K.<BR>
495	# 0x5 - 128K.<BR>
496	# 0x6 - 256K.<BR>
497	# 0x7 - 512K.<BR>
498	# 0x8 - 1M.<BR>
499	# 0x9 - 2M.<BR>
500	# 0xA - 4M.<BR>
501	# 0xB - 8M.<BR>
502	# 0xC - 16M.<BR>
503	# 0xD - 32M.<BR>
504	# 0xE - 64M.<BR>
505	# 0xF - 128M.<BR>
506	# @Prompt The memory size used for processor trace if processor trace is enabled.
507	# @ValidRange 0x80000001 \| 0 - 0xF
508	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize\|0x0\|UINT32\|0x60000012
509
510	## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
511	# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
512	# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
513	# Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
514	# 0 - Single Range output scheme.<BR>
515	# 1 - ToPA(Table of physical address) scheme.<BR>
516	# @Prompt The processor trace output scheme used when processor trace is enabled.
517	# @ValidRange 0x80000001 \| 0 - 1
518	gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme\|0x0\|UINT8\|0x60000015
519
520	## This dynamic PCD indicates whether SEV-ES is enabled
521	# TRUE - SEV-ES is enabled
522	# FALSE - SEV-ES is not enabled
523	# @Prompt SEV-ES Status
524	gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled\|FALSE\|BOOLEAN\|0x60000016
525
526	## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
527	# features VMGEXIT defined in the version 2 of GHCB spec.
528	# @Prompt GHCB Hypervisor Features
529	gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures\|0x0\|UINT64\|0x60000018
530
531	[UserExtensions.TianoCore."ExtraFiles"]
532	UefiCpuPkgExtra.uni

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