| 1 | ## @file UefiCpuPkg.dec
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| 2 | # This Package provides UEFI compatible CPU modules and libraries.
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| 3 | #
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| 4 | # Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
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| 5 | #
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| 6 | # This program and the accompanying materials are licensed and made available under
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| 7 | # the terms and conditions of the BSD License which accompanies this distribution.
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| 8 | # The full text of the license may be found at
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| 9 | # http://opensource.org/licenses/bsd-license.php
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| 10 | #
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| 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 | #
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| 14 | ##
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| 15 |
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| 16 | [Defines]
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| 17 | DEC_SPECIFICATION = 0x00010005
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| 18 | PACKAGE_NAME = UefiCpuPkg
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| 19 | PACKAGE_UNI_FILE = UefiCpuPkg.uni
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| 20 | PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
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| 21 | PACKAGE_VERSION = 0.90
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| 22 |
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| 23 | [Includes]
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| 24 | Include
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| 25 |
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| 26 | [LibraryClasses]
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| 27 | ## @libraryclass Defines some routines that are generic for IA32 family CPU
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| 28 | ## to be UEFI specification compliant.
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| 29 | ##
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| 30 | UefiCpuLib|Include/Library/UefiCpuLib.h
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| 31 |
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| 32 | ## @libraryclass Defines some routines that are used to register/manage/program
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| 33 | ## CPU features.
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| 34 | ##
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| 35 | RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
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| 36 |
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| 37 | [LibraryClasses.IA32, LibraryClasses.X64]
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| 38 | ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
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| 39 | ##
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| 40 | MtrrLib|Include/Library/MtrrLib.h
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| 41 |
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| 42 | ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
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| 43 | ##
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| 44 | LocalApicLib|Include/Library/LocalApicLib.h
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| 45 |
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| 46 | ## @libraryclass Provides platform specific initialization functions in the SEC phase.
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| 47 | ##
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| 48 | PlatformSecLib|Include/Library/PlatformSecLib.h
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| 49 |
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| 50 | ## @libraryclass Public include file for the SMM CPU Platform Hook Library.
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| 51 | ##
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| 52 | SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
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| 53 |
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| 54 | ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
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| 55 | ##
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| 56 | SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
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| 57 |
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| 58 | ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
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| 59 | ##
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| 60 | MpInitLib|Include/Library/MpInitLib.h
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| 61 |
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| 62 | [Guids]
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| 63 | gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
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| 64 | gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
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| 65 |
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| 66 | ## Include/Guid/CpuFeaturesSetDone.h
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| 67 | gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
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| 68 |
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| 69 | ## Include/Guid/CpuFeaturesInitDone.h
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| 70 | gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
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| 71 |
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| 72 | [Protocols]
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| 73 | ## Include/Protocol/SmmCpuService.h
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| 74 | gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
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| 75 |
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| 76 | ## Include/Protocol/SmMonitorInit.h
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| 77 | gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
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| 78 |
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| 79 | #
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| 80 | # [Error.gUefiCpuPkgTokenSpaceGuid]
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| 81 | # 0x80000001 | Invalid value provided.
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| 82 | #
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| 83 |
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| 84 | [PcdsFeatureFlag]
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| 85 | ## Indicates if SMM Profile will be enabled.
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| 86 | # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
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| 87 | # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).
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| 88 | # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
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| 89 | # TRUE - SMM Profile will be enabled.<BR>
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| 90 | # FALSE - SMM Profile will be disabled.<BR>
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| 91 | # @Prompt Enable SMM Profile.
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| 92 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
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| 93 |
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| 94 | ## Indicates if the SMM profile log buffer is a ring buffer.
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| 95 | # If disabled, no additional log can be done when the buffer is full.<BR><BR>
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| 96 | # TRUE - the SMM profile log buffer is a ring buffer.<BR>
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| 97 | # FALSE - the SMM profile log buffer is a normal buffer.<BR>
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| 98 | # @Prompt The SMM profile log buffer is a ring buffer.
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| 99 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
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| 100 |
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| 101 | ## Indicates if SMM Startup AP in a blocking fashion.
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| 102 | # TRUE - SMM Startup AP in a blocking fashion.<BR>
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| 103 | # FALSE - SMM Startup AP in a non-blocking fashion.<BR>
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| 104 | # @Prompt SMM Startup AP in a blocking fashion.
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| 105 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
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| 106 |
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| 107 | ## Indicates if SMM Stack Guard will be enabled.
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| 108 | # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
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| 109 | # TRUE - SMM Stack Guard will be enabled.<BR>
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| 110 | # FALSE - SMM Stack Guard will be disabled.<BR>
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| 111 | # @Prompt Enable SMM Stack Guard.
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| 112 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
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| 113 |
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| 114 | ## Indicates if BSP election in SMM will be enabled.
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| 115 | # If enabled, a BSP will be dynamically elected among all processors in each SMI.
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| 116 | # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
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| 117 | # TRUE - BSP election in SMM will be enabled.<BR>
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| 118 | # FALSE - BSP election in SMM will be disabled.<BR>
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| 119 | # @Prompt Enable BSP election in SMM.
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| 120 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
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| 121 |
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| 122 | ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
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| 123 | # TRUE - SMM CPU hot-plug will be enabled.<BR>
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| 124 | # FALSE - SMM CPU hot-plug will be disabled.<BR>
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| 125 | # @Prompt SMM CPU hot-plug.
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| 126 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
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| 127 |
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| 128 | ## Indicates if SMM Debug will be enabled.
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| 129 | # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
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| 130 | # TRUE - SMM Debug will be enabled.<BR>
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| 131 | # FALSE - SMM Debug will be disabled.<BR>
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| 132 | # @Prompt Enable SMM Debug.
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| 133 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
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| 134 |
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| 135 | ## Indicates if lock SMM Feature Control MSR.<BR><BR>
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| 136 | # TRUE - SMM Feature Control MSR will be locked.<BR>
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| 137 | # FALSE - SMM Feature Control MSR will not be locked.<BR>
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| 138 | # @Prompt Lock SMM Feature Control MSR.
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| 139 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
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| 140 |
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| 141 | [PcdsFixedAtBuild]
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| 142 | ## List of exception vectors which need switching stack.
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| 143 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
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| 144 | # By default exception #DD(8), #PF(14) are supported.
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| 145 | # @Prompt Specify exception vectors which need switching stack.
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| 146 | gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
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| 147 |
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| 148 | ## Size of good stack for an exception.
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| 149 | # This PCD will only take into effect if PcdCpuStackGuard is enabled.
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| 150 | # @Prompt Specify size of good stack of exception which need switching stack.
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| 151 | gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
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| 152 |
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| 153 | [PcdsFixedAtBuild, PcdsPatchableInModule]
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| 154 | ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
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| 155 | # @Prompt Configure base address of CPU Local APIC
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| 156 | # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
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| 157 | gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
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| 158 |
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| 159 | ## Specifies delay value in microseconds after sending out an INIT IPI.
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| 160 | # @Prompt Configure delay value after send an INIT IPI
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| 161 | gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
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| 162 |
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| 163 | ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
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| 164 | ## aligns the address on a 4-KByte boundary.
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| 165 | # @Prompt Configure stack size for Application Processor (AP)
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| 166 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
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| 167 |
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| 168 | ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
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| 169 | # @Prompt Stack size in the temporary RAM.
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| 170 | gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
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| 171 |
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| 172 | ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
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| 173 | # @Prompt SMM profile data buffer size.
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| 174 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
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| 175 |
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| 176 | ## Specifies stack size in bytes for each processor in SMM.
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| 177 | # @Prompt Processor stack size in SMM.
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| 178 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
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| 179 |
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| 180 | ## Indicates if SMM Code Access Check is enabled.
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| 181 | # If enabled, the SMM handler cannot execute the code outside SMM regions.
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| 182 | # This PCD is suggested to TRUE in production image.<BR><BR>
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| 183 | # TRUE - SMM Code Access Check will be enabled.<BR>
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| 184 | # FALSE - SMM Code Access Check will be disabled.<BR>
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| 185 | # @Prompt SMM Code Access Check.
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| 186 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
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| 187 |
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| 188 | ## Specifies the number of variable MTRRs reserved for OS use. The default number of
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| 189 | # MTRRs reserved for OS use is 2.
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| 190 | # @Prompt Number of reserved variable MTRRs.
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| 191 | gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
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| 192 |
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| 193 | ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
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| 194 | # @Prompt STM exception stack size.
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| 195 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
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| 196 |
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| 197 | ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
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| 198 | # @Prompt MSEG size.
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| 199 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
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| 200 |
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| 201 | ## Specifies the supported CPU features bit in array.
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| 202 | # @Prompt Supported CPU features.
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| 203 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
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| 204 |
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| 205 | ## Specifies if CPU features will be initialized after SMM relocation.
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| 206 | # @Prompt If CPU features will be initialized after SMM relocation.
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| 207 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
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| 208 |
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| 209 | ## Specifies if CPU features will be initialized during S3 resume.
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| 210 | # @Prompt If CPU features will be initialized during S3 resume.
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| 211 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
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| 212 |
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| 213 | [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
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| 214 | ## Specifies max supported number of Logical Processors.
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| 215 | # @Prompt Configure max supported number of Logical Processors
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| 216 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
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| 217 | ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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| 218 | # @Prompt Timeout for the BSP to detect all APs for the first time.
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| 219 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
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| 220 | ## Specifies the base address of the first microcode Patch in the microcode Region.
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| 221 | # @Prompt Microcode Region base address.
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| 222 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
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| 223 | ## Specifies the size of the microcode Region.
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| 224 | # @Prompt Microcode Region size.
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| 225 | gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
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| 226 | ## Specifies the AP wait loop state during POST phase.
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| 227 | # The value is defined as below.<BR><BR>
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| 228 | # 1: Place AP in the Hlt-Loop state.<BR>
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| 229 | # 2: Place AP in the Mwait-Loop state.<BR>
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| 230 | # 3: Place AP in the Run-Loop state.<BR>
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| 231 | # @Prompt The AP wait loop state.
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| 232 | # @ValidRange 0x80000001 | 1 - 3
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| 233 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
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| 234 | ## Specifies the AP target C-state for Mwait during POST phase.
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| 235 | # The default value 0 means C1 state.
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| 236 | # The value is defined as below.<BR><BR>
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| 237 | # @Prompt The specified AP target C-state for Mwait.
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| 238 | gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
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| 239 |
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| 240 | ## Indicates if SMM uses static page table.
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| 241 | # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.
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| 242 | # This flag only impacts X64 build, because SMM always builds static page table for IA32.
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| 243 | # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
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| 244 | # It could not be enabled also at the same time with heap guard feature for SMM
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| 245 | # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>
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| 246 | # TRUE - SMM uses static page table for all memory.<BR>
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| 247 | # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>
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| 248 | # @Prompt Use static page table for all memory in SMM.
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| 249 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D
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| 250 |
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| 251 | ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
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| 252 | # @Prompt AP synchronization timeout value in SMM.
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| 253 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
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| 254 |
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| 255 | ## Indicates the CPU synchronization method used when processing an SMI.
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| 256 | # 0x00 - Traditional CPU synchronization method.<BR>
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| 257 | # 0x01 - Relaxed CPU synchronization method.<BR>
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| 258 | # @Prompt SMM CPU Synchronization Method.
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| 259 | gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
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| 260 |
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| 261 | ## Specifies user's desired settings for enabling/disabling processor features.
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| 262 | # @Prompt User settings for enabling/disabling processor features.
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| 263 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017
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| 264 |
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| 265 | ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
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| 266 | # @Prompt The encoded values for target duty cycle modulation.
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| 267 | # @ValidRange 0x80000001 | 0 - 15
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| 268 | gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
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| 269 |
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| 270 | ## Indicates if the current boot is a power-on reset.<BR><BR>
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| 271 | # TRUE - Current boot is a power-on reset.<BR>
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| 272 | # FALSE - Current boot is not a power-on reset.<BR>
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| 273 | # @Prompt Current boot is a power-on reset.
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| 274 | gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
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| 275 |
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| 276 | [PcdsDynamic, PcdsDynamicEx]
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| 277 | ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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| 278 | # @Prompt The pointer to a CPU S3 data buffer.
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| 279 | # @ValidList 0x80000001 | 0
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| 280 | gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
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| 281 |
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| 282 | ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
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| 283 | # @Prompt The pointer to CPU Hot Plug Data.
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| 284 | # @ValidList 0x80000001 | 0
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| 285 | gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
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| 286 |
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| 287 | ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
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| 288 | # @Prompt Processor feature capabilities.
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| 289 | # @ValidList 0x80000001 | 0
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| 290 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
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| 291 |
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| 292 | ## Specifies actual settings for processor features, each bit corresponding to a specific feature.
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| 293 | # @Prompt Actual processor feature settings.
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| 294 | # @ValidList 0x80000001 | 0
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| 295 | gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
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| 296 |
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| 297 | ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
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| 298 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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| 299 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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| 300 | # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
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| 301 | # 0x0 - 4K.<BR>
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| 302 | # 0x1 - 8K.<BR>
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| 303 | # 0x2 - 16K.<BR>
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| 304 | # 0x3 - 32K.<BR>
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| 305 | # 0x4 - 64K.<BR>
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| 306 | # 0x5 - 128K.<BR>
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| 307 | # 0x6 - 256K.<BR>
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| 308 | # 0x7 - 512K.<BR>
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| 309 | # 0x8 - 1M.<BR>
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| 310 | # 0x9 - 2M.<BR>
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| 311 | # 0xA - 4M.<BR>
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| 312 | # 0xB - 8M.<BR>
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| 313 | # 0xC - 16M.<BR>
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| 314 | # 0xD - 32M.<BR>
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| 315 | # 0xE - 64M.<BR>
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| 316 | # 0xF - 128M.<BR>
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| 317 | # @Prompt The memory size used for processor trace if processor trace is enabled.
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| 318 | # @ValidRange 0x80000001 | 0 - 0xF
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| 319 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
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| 320 |
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| 321 | ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
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| 322 | # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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| 323 | # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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| 324 | # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
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| 325 | # 0 - Single Range output scheme.<BR>
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| 326 | # 1 - ToPA(Table of physical address) scheme.<BR>
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| 327 | # @Prompt The processor trace output scheme used when processor trace is enabled.
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| 328 | # @ValidRange 0x80000001 | 0 - 1
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| 329 | gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
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| 330 |
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| 331 | [UserExtensions.TianoCore."ExtraFiles"]
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| 332 | UefiCpuPkgExtra.uni
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