| 1 | /** @file
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| 2 | Support for PCI 2.2 standard.
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| 3 |
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| 4 | Copyright (c) 2006 - 2008, Intel Corporation All rights reserved.
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| 5 |
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| 6 | This program and the accompanying materials are licensed and made available
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| 7 | under the terms and conditions of the BSD License which accompanies this
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| 8 | distribution. The full text of the license may be found at:
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| 9 | http://opensource.org/licenses/bsd-license.php
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| 10 |
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| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 |
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| 14 | File Name: pci22.h
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| 15 |
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| 16 | **/
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| 17 |
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| 18 | #ifndef _PCI22_H
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| 19 | #define _PCI22_H
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| 20 |
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| 21 | #define PCI_MAX_SEGMENT 0
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| 22 |
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| 23 | #define PCI_MAX_BUS 255
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| 24 |
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| 25 | #define PCI_MAX_DEVICE 31
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| 26 | #define PCI_MAX_FUNC 7
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| 27 |
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| 28 | //
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| 29 | // Command
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| 30 | //
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| 31 | #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
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| 32 |
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| 33 | #pragma pack(push, 1)
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| 34 | typedef struct {
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| 35 | UINT16 VendorId;
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| 36 | UINT16 DeviceId;
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| 37 | UINT16 Command;
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| 38 | UINT16 Status;
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| 39 | UINT8 RevisionID;
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| 40 | UINT8 ClassCode[3];
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| 41 | UINT8 CacheLineSize;
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| 42 | UINT8 LatencyTimer;
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| 43 | UINT8 HeaderType;
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| 44 | UINT8 BIST;
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| 45 | } PCI_DEVICE_INDEPENDENT_REGION;
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| 46 |
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| 47 | typedef struct {
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| 48 | UINT32 Bar[6];
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| 49 | UINT32 CISPtr;
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| 50 | UINT16 SubsystemVendorID;
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| 51 | UINT16 SubsystemID;
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| 52 | UINT32 ExpansionRomBar;
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| 53 | UINT8 CapabilityPtr;
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| 54 | UINT8 Reserved1[3];
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| 55 | UINT32 Reserved2;
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| 56 | UINT8 InterruptLine;
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| 57 | UINT8 InterruptPin;
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| 58 | UINT8 MinGnt;
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| 59 | UINT8 MaxLat;
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| 60 | } PCI_DEVICE_HEADER_TYPE_REGION;
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| 61 |
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| 62 | typedef struct {
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| 63 | PCI_DEVICE_INDEPENDENT_REGION Hdr;
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| 64 | PCI_DEVICE_HEADER_TYPE_REGION Device;
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| 65 | } PCI_TYPE00;
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| 66 |
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| 67 | typedef struct {
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| 68 | UINT32 Bar[2];
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| 69 | UINT8 PrimaryBus;
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| 70 | UINT8 SecondaryBus;
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| 71 | UINT8 SubordinateBus;
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| 72 | UINT8 SecondaryLatencyTimer;
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| 73 | UINT8 IoBase;
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| 74 | UINT8 IoLimit;
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| 75 | UINT16 SecondaryStatus;
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| 76 | UINT16 MemoryBase;
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| 77 | UINT16 MemoryLimit;
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| 78 | UINT16 PrefetchableMemoryBase;
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| 79 | UINT16 PrefetchableMemoryLimit;
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| 80 | UINT32 PrefetchableBaseUpper32;
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| 81 | UINT32 PrefetchableLimitUpper32;
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| 82 | UINT16 IoBaseUpper16;
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| 83 | UINT16 IoLimitUpper16;
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| 84 | UINT8 CapabilityPtr;
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| 85 | UINT8 Reserved[3];
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| 86 | UINT32 ExpansionRomBAR;
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| 87 | UINT8 InterruptLine;
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| 88 | UINT8 InterruptPin;
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| 89 | UINT16 BridgeControl;
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| 90 | } PCI_BRIDGE_CONTROL_REGISTER;
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| 91 |
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| 92 | typedef struct {
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| 93 | PCI_DEVICE_INDEPENDENT_REGION Hdr;
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| 94 | PCI_BRIDGE_CONTROL_REGISTER Bridge;
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| 95 | } PCI_TYPE01;
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| 96 |
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| 97 | typedef union {
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| 98 | PCI_TYPE00 Device;
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| 99 | PCI_TYPE01 Bridge;
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| 100 | } PCI_TYPE_GENERIC;
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| 101 |
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| 102 | typedef struct {
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| 103 | UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
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| 104 | // Address Register
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| 105 | //
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| 106 | UINT16 Reserved;
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| 107 | UINT16 SecondaryStatus; // Secondary Status
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| 108 | UINT8 PciBusNumber; // PCI Bus Number
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| 109 | UINT8 CardBusBusNumber; // CardBus Bus Number
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| 110 | UINT8 SubordinateBusNumber; // Subordinate Bus Number
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| 111 | UINT8 CardBusLatencyTimer; // CardBus Latency Timer
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| 112 | UINT32 MemoryBase0; // Memory Base Register 0
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| 113 | UINT32 MemoryLimit0; // Memory Limit Register 0
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| 114 | UINT32 MemoryBase1;
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| 115 | UINT32 MemoryLimit1;
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| 116 | UINT32 IoBase0;
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| 117 | UINT32 IoLimit0; // I/O Base Register 0
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| 118 | UINT32 IoBase1; // I/O Limit Register 0
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| 119 | UINT32 IoLimit1;
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| 120 | UINT8 InterruptLine; // Interrupt Line
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| 121 | UINT8 InterruptPin; // Interrupt Pin
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| 122 | UINT16 BridgeControl; // Bridge Control
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| 123 | } PCI_CARDBUS_CONTROL_REGISTER;
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| 124 |
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| 125 | //
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| 126 | // Definitions of PCI class bytes and manipulation macros.
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| 127 | //
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| 128 | #define PCI_CLASS_OLD 0x00
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| 129 | #define PCI_CLASS_OLD_OTHER 0x00
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| 130 | #define PCI_CLASS_OLD_VGA 0x01
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| 131 |
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| 132 | #define PCI_CLASS_MASS_STORAGE 0x01
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| 133 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
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| 134 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
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| 135 | #define PCI_CLASS_IDE 0x01
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| 136 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
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| 137 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03
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| 138 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04
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| 139 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
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| 140 |
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| 141 | #define PCI_CLASS_NETWORK 0x02
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| 142 | #define PCI_CLASS_NETWORK_ETHERNET 0x00
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| 143 | #define PCI_CLASS_ETHERNET 0x00 // obsolete
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| 144 | #define PCI_CLASS_NETWORK_TOKENRING 0x01
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| 145 | #define PCI_CLASS_NETWORK_FDDI 0x02
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| 146 | #define PCI_CLASS_NETWORK_ATM 0x03
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| 147 | #define PCI_CLASS_NETWORK_ISDN 0x04
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| 148 | #define PCI_CLASS_NETWORK_OTHER 0x80
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| 149 |
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| 150 | #define PCI_CLASS_DISPLAY 0x03
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| 151 | #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
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| 152 | #define PCI_CLASS_DISPLAY_VGA 0x00
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| 153 | #define PCI_CLASS_VGA 0x00 // obsolete
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| 154 | #define PCI_CLASS_DISPLAY_XGA 0x01
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| 155 | #define PCI_CLASS_DISPLAY_3D 0x02
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| 156 | #define PCI_CLASS_DISPLAY_OTHER 0x80
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| 157 | #define PCI_CLASS_DISPLAY_GFX 0x80
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| 158 | #define PCI_CLASS_GFX 0x80 // obsolete
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| 159 | #define PCI_CLASS_BRIDGE 0x06
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| 160 | #define PCI_CLASS_BRIDGE_HOST 0x00
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| 161 | #define PCI_CLASS_BRIDGE_ISA 0x01
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| 162 | #define PCI_CLASS_ISA 0x01 // obsolete
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| 163 | #define PCI_CLASS_BRIDGE_EISA 0x02
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| 164 | #define PCI_CLASS_BRIDGE_MCA 0x03
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| 165 | #define PCI_CLASS_BRIDGE_P2P 0x04
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| 166 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05
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| 167 | #define PCI_CLASS_BRIDGE_NUBUS 0x06
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| 168 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07
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| 169 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08
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| 170 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
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| 171 | #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
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| 172 |
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| 173 | #define PCI_CLASS_SCC 0x07 // Simple communications controllers
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| 174 | #define PCI_SUBCLASS_SERIAL 0x00
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| 175 | #define PCI_IF_GENERIC_XT 0x00
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| 176 | #define PCI_IF_16450 0x01
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| 177 | #define PCI_IF_16550 0x02
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| 178 | #define PCI_IF_16650 0x03
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| 179 | #define PCI_IF_16750 0x04
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| 180 | #define PCI_IF_16850 0x05
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| 181 | #define PCI_IF_16950 0x06
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| 182 | #define PCI_SUBCLASS_PARALLEL 0x01
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| 183 | #define PCI_IF_PARALLEL_PORT 0x00
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| 184 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
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| 185 | #define PCI_IF_ECP_PARALLEL_PORT 0x02
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| 186 | #define PCI_IF_1284_CONTROLLER 0x03
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| 187 | #define PCI_IF_1284_DEVICE 0xFE
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| 188 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
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| 189 | #define PCI_SUBCLASS_MODEM 0x03
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| 190 | #define PCI_IF_GENERIC_MODEM 0x00
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| 191 | #define PCI_IF_16450_MODEM 0x01
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| 192 | #define PCI_IF_16550_MODEM 0x02
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| 193 | #define PCI_IF_16650_MODEM 0x03
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| 194 | #define PCI_IF_16750_MODEM 0x04
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| 195 | #define PCI_SUBCLASS_OTHER 0x80
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| 196 |
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| 197 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
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| 198 | #define PCI_SUBCLASS_PIC 0x00
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| 199 | #define PCI_IF_8259_PIC 0x00
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| 200 | #define PCI_IF_ISA_PIC 0x01
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| 201 | #define PCI_IF_EISA_PIC 0x02
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| 202 | #define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
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| 203 | #define PCI_IF_APIC_CONTROLLER2 0x20
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| 204 | #define PCI_SUBCLASS_TIMER 0x02
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| 205 | #define PCI_IF_8254_TIMER 0x00
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| 206 | #define PCI_IF_ISA_TIMER 0x01
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| 207 | #define PCI_EISA_TIMER 0x02
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| 208 | #define PCI_SUBCLASS_RTC 0x03
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| 209 | #define PCI_IF_GENERIC_RTC 0x00
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| 210 | #define PCI_IF_ISA_RTC 0x00
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| 211 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
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| 212 |
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| 213 | #define PCI_CLASS_INPUT_DEVICE 0x09
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| 214 | #define PCI_SUBCLASS_KEYBOARD 0x00
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| 215 | #define PCI_SUBCLASS_PEN 0x01
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| 216 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
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| 217 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
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| 218 | #define PCI_SUBCLASS_GAMEPORT 0x04
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| 219 |
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| 220 | #define PCI_CLASS_DOCKING_STATION 0x0A
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| 221 |
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| 222 | #define PCI_CLASS_PROCESSOR 0x0B
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| 223 | #define PCI_SUBCLASS_PROC_386 0x00
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| 224 | #define PCI_SUBCLASS_PROC_486 0x01
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| 225 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02
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| 226 | #define PCI_SUBCLASS_PROC_ALPHA 0x10
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| 227 | #define PCI_SUBCLASS_PROC_POWERPC 0x20
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| 228 | #define PCI_SUBCLASS_PROC_MIPS 0x30
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| 229 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
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| 230 |
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| 231 | #define PCI_CLASS_SERIAL 0x0C
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| 232 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00
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| 233 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
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| 234 | #define PCI_CLASS_SERIAL_SSA 0x02
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| 235 | #define PCI_CLASS_SERIAL_USB 0x03
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| 236 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
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| 237 | #define PCI_CLASS_SERIAL_SMB 0x05
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| 238 |
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| 239 | #define PCI_CLASS_WIRELESS 0x0D
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| 240 | #define PCI_SUBCLASS_IRDA 0x00
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| 241 | #define PCI_SUBCLASS_IR 0x01
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| 242 | #define PCI_SUBCLASS_RF 0x02
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| 243 |
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| 244 | #define PCI_CLASS_INTELLIGENT_IO 0x0E
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| 245 |
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| 246 | #define PCI_CLASS_SATELLITE 0x0F
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| 247 | #define PCI_SUBCLASS_TV 0x01
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| 248 | #define PCI_SUBCLASS_AUDIO 0x02
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| 249 | #define PCI_SUBCLASS_VOICE 0x03
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| 250 | #define PCI_SUBCLASS_DATA 0x04
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| 251 |
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| 252 | #define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
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| 253 | #define PCI_SUBCLASS_NET_COMPUT 0x00
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| 254 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10
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| 255 |
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| 256 | #define PCI_CLASS_DPIO 0x11
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| 257 |
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| 258 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
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| 259 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
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| 260 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
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| 261 |
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| 262 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
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| 263 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
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| 264 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
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| 265 | #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
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| 266 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
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| 267 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
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| 268 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
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| 269 | #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
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| 270 | #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
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| 271 | #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
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| 272 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
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| 273 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
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| 274 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
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| 275 |
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| 276 | #define HEADER_TYPE_DEVICE 0x00
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| 277 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
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| 278 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
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| 279 |
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| 280 | #define HEADER_TYPE_MULTI_FUNCTION 0x80
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| 281 | #define HEADER_LAYOUT_CODE 0x7f
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| 282 |
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| 283 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
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| 284 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
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| 285 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
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| 286 |
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| 287 | #define PCI_DEVICE_ROMBAR 0x30
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| 288 | #define PCI_BRIDGE_ROMBAR 0x38
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| 289 |
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| 290 | #define PCI_MAX_BAR 0x0006
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| 291 | #define PCI_MAX_CONFIG_OFFSET 0x0100
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| 292 |
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| 293 | #define PCI_VENDOR_ID_OFFSET 0x00
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| 294 | #define PCI_DEVICE_ID_OFFSET 0x02
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| 295 | #define PCI_COMMAND_OFFSET 0x04
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| 296 | #define PCI_PRIMARY_STATUS_OFFSET 0x06
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| 297 | #define PCI_REVISION_ID_OFFSET 0x08
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| 298 | #define PCI_CLASSCODE_OFFSET 0x09
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| 299 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C
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| 300 | #define PCI_LATENCY_TIMER_OFFSET 0x0D
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| 301 | #define PCI_HEADER_TYPE_OFFSET 0x0E
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| 302 | #define PCI_BIST_OFFSET 0x0F
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| 303 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10
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| 304 | #define PCI_CARDBUS_CIS_OFFSET 0x28
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| 305 | #define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
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| 306 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
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| 307 | #define PCI_SID_OFFSET 0x2E // SubSystem ID
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| 308 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
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| 309 | #define PCI_EXPANSION_ROM_BASE 0x30
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| 310 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34
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| 311 | #define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
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| 312 | #define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
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| 313 | #define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
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| 314 | #define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
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| 315 |
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| 316 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
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| 317 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
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| 318 |
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| 319 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
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| 320 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
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| 321 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
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| 322 |
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| 323 | typedef union {
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| 324 | struct {
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| 325 | UINT32 Reg : 8;
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| 326 | UINT32 Func : 3;
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| 327 | UINT32 Dev : 5;
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| 328 | UINT32 Bus : 8;
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| 329 | UINT32 Reserved : 7;
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| 330 | UINT32 Enable : 1;
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| 331 | } Bits;
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| 332 | UINT32 Uint32;
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| 333 | } PCI_CONFIG_ACCESS_CF8;
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| 334 |
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| 335 | #pragma pack()
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| 336 |
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| 337 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
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| 338 | #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
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| 339 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
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| 340 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03
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| 341 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
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| 342 |
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| 343 | #define EFI_PCI_COMMAND_IO_SPACE 0x0001
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| 344 | #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
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| 345 | #define EFI_PCI_COMMAND_BUS_MASTER 0x0004
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| 346 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
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| 347 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
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| 348 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
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| 349 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
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| 350 | #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
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| 351 | #define EFI_PCI_COMMAND_SERR 0x0100
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| 352 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
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| 353 |
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| 354 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
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| 355 | #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
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| 356 | #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
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| 357 | #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
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| 358 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
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| 359 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
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| 360 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
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| 361 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
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| 362 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
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| 363 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
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| 364 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
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| 365 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
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| 366 |
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| 367 | //
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| 368 | // Following are the PCI-CARDBUS bridge control bit
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| 369 | //
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| 370 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
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| 371 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
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| 372 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
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| 373 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
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| 374 |
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| 375 | //
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| 376 | // Following are the PCI status control bit
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| 377 | //
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| 378 | #define EFI_PCI_STATUS_CAPABILITY 0x0010
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| 379 | #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
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| 380 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
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| 381 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
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| 382 |
|
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| 383 | #define EFI_PCI_CAPABILITY_PTR 0x34
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| 384 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
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| 385 |
|
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| 386 | #pragma pack(1)
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| 387 | typedef struct {
|
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| 388 | UINT16 Signature; // 0xaa55
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| 389 | UINT8 Reserved[0x16];
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| 390 | UINT16 PcirOffset;
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| 391 | } PCI_EXPANSION_ROM_HEADER;
|
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| 392 |
|
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| 393 | typedef struct {
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| 394 | UINT16 Signature; // 0xaa55
|
|---|
| 395 | UINT8 Size512;
|
|---|
| 396 | UINT8 InitEntryPoint[3];
|
|---|
| 397 | UINT8 Reserved[0x12];
|
|---|
| 398 | UINT16 PcirOffset;
|
|---|
| 399 | } EFI_LEGACY_EXPANSION_ROM_HEADER;
|
|---|
| 400 |
|
|---|
| 401 | typedef struct {
|
|---|
| 402 | UINT32 Signature; // "PCIR"
|
|---|
| 403 | UINT16 VendorId;
|
|---|
| 404 | UINT16 DeviceId;
|
|---|
| 405 | UINT16 Reserved0;
|
|---|
| 406 | UINT16 Length;
|
|---|
| 407 | UINT8 Revision;
|
|---|
| 408 | UINT8 ClassCode[3];
|
|---|
| 409 | UINT16 ImageLength;
|
|---|
| 410 | UINT16 CodeRevision;
|
|---|
| 411 | UINT8 CodeType;
|
|---|
| 412 | UINT8 Indicator;
|
|---|
| 413 | UINT16 Reserved1;
|
|---|
| 414 | } PCI_DATA_STRUCTURE;
|
|---|
| 415 |
|
|---|
| 416 | //
|
|---|
| 417 | // PCI Capability List IDs and records
|
|---|
| 418 | //
|
|---|
| 419 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01
|
|---|
| 420 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02
|
|---|
| 421 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03
|
|---|
| 422 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
|
|---|
| 423 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05
|
|---|
| 424 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
|
|---|
| 425 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
|
|---|
| 426 |
|
|---|
| 427 | typedef struct {
|
|---|
| 428 | UINT8 CapabilityID;
|
|---|
| 429 | UINT8 NextItemPtr;
|
|---|
| 430 | } EFI_PCI_CAPABILITY_HDR;
|
|---|
| 431 |
|
|---|
| 432 | //
|
|---|
| 433 | // Capability EFI_PCI_CAPABILITY_ID_PMI
|
|---|
| 434 | //
|
|---|
| 435 | typedef struct {
|
|---|
| 436 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 437 | UINT16 PMC;
|
|---|
| 438 | UINT16 PMCSR;
|
|---|
| 439 | UINT8 BridgeExtention;
|
|---|
| 440 | UINT8 Data;
|
|---|
| 441 | } EFI_PCI_CAPABILITY_PMI;
|
|---|
| 442 |
|
|---|
| 443 | //
|
|---|
| 444 | // Capability EFI_PCI_CAPABILITY_ID_AGP
|
|---|
| 445 | //
|
|---|
| 446 | typedef struct {
|
|---|
| 447 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 448 | UINT8 Rev;
|
|---|
| 449 | UINT8 Reserved;
|
|---|
| 450 | UINT32 Status;
|
|---|
| 451 | UINT32 Command;
|
|---|
| 452 | } EFI_PCI_CAPABILITY_AGP;
|
|---|
| 453 |
|
|---|
| 454 | //
|
|---|
| 455 | // Capability EFI_PCI_CAPABILITY_ID_VPD
|
|---|
| 456 | //
|
|---|
| 457 | typedef struct {
|
|---|
| 458 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 459 | UINT16 AddrReg;
|
|---|
| 460 | UINT32 DataReg;
|
|---|
| 461 | } EFI_PCI_CAPABILITY_VPD;
|
|---|
| 462 |
|
|---|
| 463 | //
|
|---|
| 464 | // Capability EFI_PCI_CAPABILITY_ID_SLOTID
|
|---|
| 465 | //
|
|---|
| 466 | typedef struct {
|
|---|
| 467 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 468 | UINT8 ExpnsSlotReg;
|
|---|
| 469 | UINT8 ChassisNo;
|
|---|
| 470 | } EFI_PCI_CAPABILITY_SLOTID;
|
|---|
| 471 |
|
|---|
| 472 | //
|
|---|
| 473 | // Capability EFI_PCI_CAPABILITY_ID_MSI
|
|---|
| 474 | //
|
|---|
| 475 | typedef struct {
|
|---|
| 476 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 477 | UINT16 MsgCtrlReg;
|
|---|
| 478 | UINT32 MsgAddrReg;
|
|---|
| 479 | UINT16 MsgDataReg;
|
|---|
| 480 | } EFI_PCI_CAPABILITY_MSI32;
|
|---|
| 481 |
|
|---|
| 482 | typedef struct {
|
|---|
| 483 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 484 | UINT16 MsgCtrlReg;
|
|---|
| 485 | UINT32 MsgAddrRegLsdw;
|
|---|
| 486 | UINT32 MsgAddrRegMsdw;
|
|---|
| 487 | UINT16 MsgDataReg;
|
|---|
| 488 | } EFI_PCI_CAPABILITY_MSI64;
|
|---|
| 489 |
|
|---|
| 490 | //
|
|---|
| 491 | // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
|
|---|
| 492 | //
|
|---|
| 493 | typedef struct {
|
|---|
| 494 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 495 | //
|
|---|
| 496 | // not finished - fields need to go here
|
|---|
| 497 | //
|
|---|
| 498 | } EFI_PCI_CAPABILITY_HOTPLUG;
|
|---|
| 499 |
|
|---|
| 500 | //
|
|---|
| 501 | // Capability EFI_PCI_CAPABILITY_ID_PCIX
|
|---|
| 502 | //
|
|---|
| 503 | typedef struct {
|
|---|
| 504 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 505 | UINT16 CommandReg;
|
|---|
| 506 | UINT32 StatusReg;
|
|---|
| 507 | } EFI_PCI_CAPABILITY_PCIX;
|
|---|
| 508 |
|
|---|
| 509 | typedef struct {
|
|---|
| 510 | EFI_PCI_CAPABILITY_HDR Hdr;
|
|---|
| 511 | UINT16 SecStatusReg;
|
|---|
| 512 | UINT32 StatusReg;
|
|---|
| 513 | UINT32 SplitTransCtrlRegUp;
|
|---|
| 514 | UINT32 SplitTransCtrlRegDn;
|
|---|
| 515 | } EFI_PCI_CAPABILITY_PCIX_BRDG;
|
|---|
| 516 |
|
|---|
| 517 | #define DEVICE_ID_NOCARE 0xFFFF
|
|---|
| 518 |
|
|---|
| 519 | #define PCI_ACPI_UNUSED 0
|
|---|
| 520 | #define PCI_BAR_NOCHANGE 0
|
|---|
| 521 | #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
|
|---|
| 522 | #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
|
|---|
| 523 | #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
|
|---|
| 524 | #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
|
|---|
| 525 |
|
|---|
| 526 | #define PCI_BAR_IDX0 0x00
|
|---|
| 527 | #define PCI_BAR_IDX1 0x01
|
|---|
| 528 | #define PCI_BAR_IDX2 0x02
|
|---|
| 529 | #define PCI_BAR_IDX3 0x03
|
|---|
| 530 | #define PCI_BAR_IDX4 0x04
|
|---|
| 531 | #define PCI_BAR_IDX5 0x05
|
|---|
| 532 | #define PCI_BAR_ALL 0xFF
|
|---|
| 533 |
|
|---|
| 534 | #pragma pack(pop)
|
|---|
| 535 |
|
|---|
| 536 | //
|
|---|
| 537 | // NOTE: The following header files are included here for
|
|---|
| 538 | // compatibility consideration.
|
|---|
| 539 | //
|
|---|
| 540 | #include "pci23.h"
|
|---|
| 541 | #include "pci30.h"
|
|---|
| 542 | #include "EfiPci.h"
|
|---|
| 543 |
|
|---|
| 544 | #endif
|
|---|
