VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 100942

Last change on this file since 100942 was 100712, checked in by vboxsync, 19 months ago

Devices/Graphics: pre-initialize screen ids. bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 274.1 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 100712 2023-07-26 22:38:25Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef IN_RING3
29# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
30#endif
31
32
33#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
34#include <iprt/mem.h>
35#include <VBox/AssertGuest.h>
36#include <VBox/log.h>
37#include <VBox/vmm/pdmdev.h>
38#include <VBoxVideo.h>
39
40/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
41#include "DevVGA.h"
42
43/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
44#ifdef VBOX_WITH_VMSVGA3D
45# include "DevVGA-SVGA3d.h"
46#endif
47#include "DevVGA-SVGA-internal.h"
48
49#include <iprt/formats/bmp.h>
50#include <stdio.h>
51
52#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
53# define SVGA_CASE_ID2STR(idx) case idx: return #idx
54
55static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
56{
57 switch (enmCmdId)
58 {
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION); /* SVGA_3D_CMD_DEAD1 */
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
292 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
293 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
294 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
295 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
296 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
297 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
298 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
299 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
300 }
301 return "UNKNOWN_3D";
302}
303
304/**
305 * FIFO command name lookup
306 *
307 * @returns FIFO command string or "UNKNOWN"
308 * @param u32Cmd FIFO command
309 */
310const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
311{
312 switch (u32Cmd)
313 {
314 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
316 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
318 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
320 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
321 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
322 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
323 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
324 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
326 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
328 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
330 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
331 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
332 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
333 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
334 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
335 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
336 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
337 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
338 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
339 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
340 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
341 default:
342 if ( u32Cmd >= SVGA_3D_CMD_BASE
343 && u32Cmd < SVGA_3D_CMD_MAX)
344 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
345 }
346 return "UNKNOWN";
347}
348# undef SVGA_CASE_ID2STR
349#endif /* LOG_ENABLED || VBOX_STRICT */
350
351
352/*
353 *
354 * Guest-Backed Objects (GBO).
355 *
356 */
357
358#ifdef VBOX_WITH_VMSVGA3D
359
360static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, PVMSVGAGBO pGbo)
361{
362 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
363
364 /*
365 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
366 * Content of the root page depends on the ptDepth value:
367 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
368 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
369 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
370 * The code below extracts the page addresses of the GBO.
371 */
372
373 /* Verify and normalize the ptDepth value. */
374 bool fGCPhys64; /* Whether the page table contains 64 bit page numbers. */
375 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
376 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
377 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
378 fGCPhys64 = true;
379 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
380 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
381 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
382 {
383 fGCPhys64 = false;
384 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
385 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
386 }
387 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
388 fGCPhys64 = false; /* Does not matter, there is no page table. */
389 else
390 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
391
392 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
393
394 pGbo->cbTotal = sizeInBytes;
395 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
396
397 /* Allocate the maximum amount possible (everything non-continuous) */
398 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
399 AssertReturn(paDescriptors, VERR_NO_MEMORY);
400
401 int rc = VINF_SUCCESS;
402 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
403 {
404 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
405 RTMemFree(paDescriptors),
406 VERR_INVALID_PARAMETER);
407
408 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
409 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
410 paDescriptors[0].GCPhys = GCPhys;
411 paDescriptors[0].cPages = 1;
412 }
413 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
414 {
415 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
416 RTMemFree(paDescriptors),
417 VERR_INVALID_PARAMETER);
418
419 /* Read the root page. */
420 uint8_t au8RootPage[X86_PAGE_SIZE];
421 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
422 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
423 if (RT_SUCCESS(rc))
424 {
425 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
426 PPN *paPPN32 = (PPN *)&au8RootPage[0];
427 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
428 {
429 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
430 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
431 paDescriptors[iPPN].GCPhys = GCPhys;
432 paDescriptors[iPPN].cPages = 1;
433 }
434 }
435 }
436 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
437 {
438 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
439 RTMemFree(paDescriptors),
440 VERR_INVALID_PARAMETER);
441
442 /* Read the Level2 root page. */
443 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
444 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
445 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
446 if (RT_SUCCESS(rc))
447 {
448 uint32_t cPagesLeft = pGbo->cTotalPages;
449
450 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
451 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
452
453 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
454 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
455 {
456 /* Read the Level1 root page. */
457 uint8_t au8RootPage[X86_PAGE_SIZE];
458 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
459 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
460 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
461 if (RT_SUCCESS(rc))
462 {
463 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
464 PPN *paPPN32 = (PPN *)&au8RootPage[0];
465
466 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
467 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
468 {
469 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
472 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
473 }
474 cPagesLeft -= cPPNs;
475 }
476 }
477 }
478 }
479 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
480 {
481 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
482 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
483 paDescriptors[0].GCPhys = GCPhys;
484 paDescriptors[0].cPages = pGbo->cTotalPages;
485 }
486 else
487 {
488 AssertFailed();
489 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
490 }
491
492 /* Compress the descriptors. */
493 if (ptDepth != SVGA3D_MOBFMT_RANGE)
494 {
495 uint32_t iDescriptor = 0;
496 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
497 {
498 /* Continuous physical memory? */
499 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
500 {
501 Assert(paDescriptors[iDescriptor].cPages);
502 paDescriptors[iDescriptor].cPages++;
503 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
504 }
505 else
506 {
507 iDescriptor++;
508 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
509 paDescriptors[iDescriptor].cPages = 1;
510 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
511 }
512 }
513
514 pGbo->cDescriptors = iDescriptor + 1;
515 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
516 }
517 else
518 pGbo->cDescriptors = 1;
519
520 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
521 {
522 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
523 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
524 }
525 else
526 pGbo->paDescriptors = paDescriptors;
527
528 pGbo->fGboFlags = 0;
529 pGbo->pvHost = NULL;
530
531 return VINF_SUCCESS;
532}
533
534
535static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
536{
537 RT_NOREF(pSvgaR3State);
538
539 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
540 {
541 RTMemFree(pGbo->pvHost);
542 RTMemFree(pGbo->paDescriptors);
543 RT_ZERO(*pGbo);
544 }
545}
546
547/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
548
549typedef enum VMSVGAGboTransferDirection
550{
551 VMSVGAGboTransferDirection_Read,
552 VMSVGAGboTransferDirection_Write,
553} VMSVGAGboTransferDirection;
554
555static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
556 uint32_t off, void *pvData, uint32_t cbData,
557 VMSVGAGboTransferDirection enmDirection)
558{
559 //DEBUG_BREAKPOINT_TEST();
560 int rc = VINF_SUCCESS;
561 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
562
563 /* Find the right descriptor */
564 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
565 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
566 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
567 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
568 {
569 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
570 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
571 ++iDescriptor;
572 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
573 }
574
575 while (cbData)
576 {
577 uint32_t cbToCopy;
578 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
579 cbToCopy = cbData;
580 else
581 {
582 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
583 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
584 }
585
586 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
587 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
588
589 /*
590 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
591 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
592 * see @bugref{9654#c75}.
593 */
594 if (enmDirection == VMSVGAGboTransferDirection_Read)
595 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
596 else
597 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
598 AssertRCBreak(rc);
599
600 cbData -= cbToCopy;
601 off += cbToCopy;
602 pu8CurrentHost += cbToCopy;
603
604 /* Go to the next descriptor if there's anything left. */
605 if (cbData)
606 {
607 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
608 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
609 ++iDescriptor;
610 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
611 }
612 }
613 return rc;
614}
615
616
617static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
618 uint32_t off, void const *pvData, uint32_t cbData)
619{
620 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
621 off, (void *)pvData, cbData,
622 VMSVGAGboTransferDirection_Write);
623}
624
625
626static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
627 uint32_t off, void *pvData, uint32_t cbData)
628{
629 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
630 off, pvData, cbData,
631 VMSVGAGboTransferDirection_Read);
632}
633
634
635static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
636{
637 int rc;
638
639 /* Just reread the data if pvHost has been allocated already. */
640 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
641 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
642
643 if (pGbo->pvHost)
644 {
645 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
646 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
647 }
648 else
649 rc = VERR_NO_MEMORY;
650
651 if (RT_SUCCESS(rc))
652 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
653 else
654 {
655 RTMemFree(pGbo->pvHost);
656 pGbo->pvHost = NULL;
657 }
658 return rc;
659}
660
661
662static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
663{
664 RT_NOREF(pSvgaR3State);
665 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
666 RTMemFree(pGbo->pvHost);
667 pGbo->pvHost = NULL;
668 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
669}
670
671
672static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
673{
674 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
675 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
676}
677
678
679static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
680{
681 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
682 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
683}
684
685static int vmsvgaR3GboCopy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboDst, uint32_t offDst,
686 PVMSVGAGBO pGboSrc, uint32_t offSrc, uint32_t cbCopy)
687{
688 uint32_t const cbTmpBuf = GUEST_PAGE_SIZE;
689 void *pvTmpBuf = RTMemTmpAlloc(cbTmpBuf);
690 AssertPtrReturn(pvTmpBuf, VERR_NO_MEMORY);
691
692 int rc = VINF_SUCCESS;
693 while (cbCopy > 0)
694 {
695 uint32_t const cbToCopy = RT_MIN(cbTmpBuf, cbCopy);
696
697 rc = vmsvgaR3GboRead(pSvgaR3State, pGboSrc, offSrc, pvTmpBuf, cbToCopy);
698 AssertRCBreak(rc);
699
700 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboDst, offDst, pvTmpBuf, cbToCopy);
701 AssertRCBreak(rc);
702
703 offSrc += cbToCopy;
704 offDst += cbToCopy;
705 cbCopy -= cbToCopy;
706 }
707
708 RTMemTmpFree(pvTmpBuf);
709 return rc;
710}
711
712
713/*
714 *
715 * Object Tables.
716 *
717 */
718
719static int vmsvgaR3OTableSetOrGrow(PVMSVGAR3STATE pSvgaR3State, SVGAOTableType type, PPN64 baseAddress,
720 uint32_t sizeInBytes, uint32 validSizeInBytes, SVGAMobFormat ptDepth, bool fGrow)
721{
722 ASSERT_GUEST_RETURN(type < RT_ELEMENTS(pSvgaR3State->aGboOTables), VERR_INVALID_PARAMETER);
723 ASSERT_GUEST_RETURN(sizeInBytes >= validSizeInBytes, VERR_INVALID_PARAMETER);
724 RT_UNTRUSTED_VALIDATED_FENCE();
725
726 ASSERT_GUEST_RETURN(pSvgaR3State->aGboOTables[type].cbTotal >= validSizeInBytes, VERR_INVALID_PARAMETER);
727
728 if (sizeInBytes > 0)
729 {
730 /* Create a new guest backed object for the object table. */
731 VMSVGAGBO gbo;
732 int rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &gbo);
733 AssertRCReturn(rc, rc);
734
735 /* If the guest sets a new OTable (fGrow == false), then it has already copied the valid data to the new GBO. */
736 if (fGrow && validSizeInBytes)
737 {
738 /* Copy data from old gbo to the new one. */
739 rc = vmsvgaR3GboCopy(pSvgaR3State, &gbo, 0, &pSvgaR3State->aGboOTables[type], 0, validSizeInBytes);
740 AssertRCReturnStmt(rc, vmsvgaR3GboDestroy(pSvgaR3State, &gbo), rc);
741 }
742
743 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
744 pSvgaR3State->aGboOTables[type] = gbo;
745
746 }
747 else
748 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
749
750 return VINF_SUCCESS;
751}
752
753
754static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
755 uint32_t idx, uint32_t cbEntry)
756{
757 RT_NOREF(pSvgaR3State);
758
759 /* The table must exist and the index must be within the table. */
760 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
761 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
762 RT_UNTRUSTED_VALIDATED_FENCE();
763 return VINF_SUCCESS;
764}
765
766
767static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
768 uint32_t idx, uint32_t cbEntry,
769 void *pvData, uint32_t cbData)
770{
771 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
772
773 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
774 if (RT_SUCCESS(rc))
775 {
776 uint32_t const off = idx * cbEntry;
777 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
778 }
779 return rc;
780}
781
782static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
783 uint32_t idx, uint32_t cbEntry,
784 void const *pvData, uint32_t cbData)
785{
786 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
787
788 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
789 if (RT_SUCCESS(rc))
790 {
791 uint32_t const off = idx * cbEntry;
792 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
793 }
794 return rc;
795}
796
797
798int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
799{
800 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
801 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
802}
803
804
805/*
806 *
807 * The guest's Memory OBjects (MOB).
808 *
809 */
810
811static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
812 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
813 PVMSVGAMOB pMob)
814{
815 RT_ZERO(*pMob);
816
817 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
818 SVGAOTableMobEntry entry;
819 entry.ptDepth = ptDepth;
820 entry.sizeInBytes = sizeInBytes;
821 entry.base = baseAddress;
822 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
823 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
824 if (RT_SUCCESS(rc))
825 {
826 /* Create the corresponding GBO. */
827 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &pMob->Gbo);
828 if (RT_SUCCESS(rc))
829 {
830 /* If a mob with this id already exists, then delete it. */
831 PVMSVGAMOB pOldMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
832 if (pOldMob)
833 {
834 /* This should not happen. */
835 ASSERT_GUEST_FAILED();
836 RTListNodeRemove(&pOldMob->nodeLRU);
837 vmsvgaR3GboDestroy(pSvgaR3State, &pOldMob->Gbo);
838 RTMemFree(pOldMob);
839 }
840
841 /* Add to the tree of known MOBs and the LRU list. */
842 pMob->Core.Key = mobid;
843 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
844 {
845 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
846 return VINF_SUCCESS;
847 }
848
849 AssertFailedStmt(rc = VERR_INVALID_STATE);
850 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
851 }
852 }
853
854 return rc;
855}
856
857
858static void vmsvgaR3MobFree(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
859{
860 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
861 RTMemFree(pMob);
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3MobFree(pSvgaR3State, pMob);
878 return VINF_SUCCESS;
879 }
880
881 return VERR_INVALID_PARAMETER;
882}
883
884
885PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
886{
887 if (mobid == SVGA_ID_INVALID)
888 return NULL;
889
890 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
891 if (pMob)
892 {
893 /* Move to the head of the LRU list. */
894 RTListNodeRemove(&pMob->nodeLRU);
895 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
896 }
897 else
898 ASSERT_GUEST_FAILED();
899
900 return pMob;
901}
902
903
904int vmsvgaR3MobWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
905 uint32_t off, void const *pvData, uint32_t cbData)
906{
907 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
908}
909
910
911int vmsvgaR3MobRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
912 uint32_t off, void *pvData, uint32_t cbData)
913{
914 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
915}
916
917
918/** Create a host ring-3 pointer to the MOB data.
919 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
920 * @param pSvgaR3State R3 device state.
921 * @param pMob The MOB.
922 * @param cbValid How many bytes of the guest backing memory contain valid data.
923 * @return VBox status.
924 */
925/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
926int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
927{
928 AssertReturn(pMob, VERR_INVALID_PARAMETER);
929 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
930}
931
932
933void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
934{
935 if (pMob)
936 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
937}
938
939
940int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
941{
942 if (pMob)
943 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
944 return VERR_INVALID_PARAMETER;
945}
946
947
948int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
949{
950 if (pMob)
951 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
952 return VERR_INVALID_PARAMETER;
953}
954
955
956void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
957{
958 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
959 {
960 if (off <= pMob->Gbo.cbTotal)
961 return (uint8_t *)pMob->Gbo.pvHost + off;
962 }
963 return NULL;
964}
965
966
967static DECLCALLBACK(int) vmsvgaR3MobFreeCb(PAVLU32NODECORE pNode, void *pvUser)
968{
969 PVMSVGAMOB pMob = (PVMSVGAMOB)pNode;
970 PVMSVGAR3STATE pSvgaR3State = (PVMSVGAR3STATE)pvUser;
971 vmsvgaR3MobFree(pSvgaR3State, pMob);
972 return 0;
973}
974
975
976#endif /* VBOX_WITH_VMSVGA3D */
977
978
979
980void vmsvgaR3ResetSvgaState(PVGASTATE pThis, PVGASTATECC pThisCC)
981{
982#ifdef VBOX_WITH_VMSVGA3D
983 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
984 RT_NOREF(pThis);
985
986 RTAvlU32Destroy(&pSvgaR3State->MOBTree, vmsvgaR3MobFreeCb, pSvgaR3State);
987 RTListInit(&pSvgaR3State->MOBLRUList);
988
989 for (unsigned i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables); ++i)
990 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[i]);
991#else
992 RT_NOREF(pThis, pThisCC);
993#endif
994}
995
996
997void vmsvgaR3TerminateSvgaState(PVGASTATE pThis, PVGASTATECC pThisCC)
998{
999 vmsvgaR3ResetSvgaState(pThis, pThisCC);
1000}
1001
1002
1003/*
1004 * Screen objects.
1005 */
1006VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1007{
1008 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1009 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1010 && pSVGAState
1011 && pSVGAState->aScreens[idScreen].fDefined)
1012 {
1013 Assert(pSVGAState->aScreens[idScreen].idScreen == idScreen);
1014 return &pSVGAState->aScreens[idScreen];
1015 }
1016 return NULL;
1017}
1018
1019
1020int vmsvgaR3DestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
1021{
1022 pScreen->fModified = true;
1023 pScreen->fDefined = false;
1024
1025 /* Notify frontend that the screen is about to be deleted. */
1026 vmsvgaR3ChangeMode(pThis, pThisCC);
1027
1028#ifdef VBOX_WITH_VMSVGA3D
1029 if (RT_LIKELY(pThis->svga.f3DEnabled))
1030 vmsvga3dDestroyScreen(pThisCC, pScreen);
1031#endif
1032
1033 RTMemFree(pScreen->pvScreenBitmap);
1034 pScreen->pvScreenBitmap = NULL;
1035
1036 return VINF_SUCCESS;
1037}
1038
1039
1040void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1041{
1042 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1043 {
1044 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1045 if (pScreen)
1046 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
1047 }
1048}
1049
1050
1051/**
1052 * Copy a rectangle of pixels within guest VRAM.
1053 */
1054static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1055 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1056{
1057 if (!width || !height)
1058 return; /* Nothing to do, don't even bother. */
1059
1060 /*
1061 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1062 * corresponding to the current display mode.
1063 */
1064 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1065 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1066 uint8_t const *pSrc;
1067 uint8_t *pDst;
1068 unsigned const cbRectWidth = width * cbPixel;
1069 unsigned uMaxOffset;
1070
1071 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1072 if (uMaxOffset >= cbFrameBuffer)
1073 {
1074 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1075 return; /* Just don't listen to a bad guest. */
1076 }
1077
1078 pSrc = pDst = pThisCC->pbVRam;
1079 pSrc += srcY * cbScanline + srcX * cbPixel;
1080 pDst += dstY * cbScanline + dstX * cbPixel;
1081
1082 if (srcY >= dstY)
1083 {
1084 /* Source below destination, copy top to bottom. */
1085 for (; height > 0; height--)
1086 {
1087 memmove(pDst, pSrc, cbRectWidth);
1088 pSrc += cbScanline;
1089 pDst += cbScanline;
1090 }
1091 }
1092 else
1093 {
1094 /* Source above destination, copy bottom to top. */
1095 pSrc += cbScanline * (height - 1);
1096 pDst += cbScanline * (height - 1);
1097 for (; height > 0; height--)
1098 {
1099 memmove(pDst, pSrc, cbRectWidth);
1100 pSrc -= cbScanline;
1101 pDst -= cbScanline;
1102 }
1103 }
1104}
1105
1106
1107/**
1108 * Common worker for changing the pointer shape.
1109 *
1110 * @param pThisCC The VGA/VMSVGA state for ring-3.
1111 * @param pSVGAState The VMSVGA ring-3 instance data.
1112 * @param fAlpha Whether there is alpha or not.
1113 * @param xHot Hotspot x coordinate.
1114 * @param yHot Hotspot y coordinate.
1115 * @param cx Width.
1116 * @param cy Height.
1117 * @param pbData Heap copy of the cursor data. Consumed.
1118 * @param cbData The size of the data.
1119 */
1120static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1121 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1122{
1123 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1124#ifdef LOG_ENABLED
1125 if (LogIs2Enabled())
1126 {
1127 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1128 if (!fAlpha)
1129 {
1130 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1131 for (uint32_t y = 0; y < cy; y++)
1132 {
1133 Log2(("%3u:", y));
1134 uint8_t const *pbLine = &pbData[y * cbAndLine];
1135 for (uint32_t x = 0; x < cx; x += 8)
1136 {
1137 uint8_t b = pbLine[x / 8];
1138 char szByte[12];
1139 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1140 szByte[1] = b & 0x40 ? '*' : ' ';
1141 szByte[2] = b & 0x20 ? '*' : ' ';
1142 szByte[3] = b & 0x10 ? '*' : ' ';
1143 szByte[4] = b & 0x08 ? '*' : ' ';
1144 szByte[5] = b & 0x04 ? '*' : ' ';
1145 szByte[6] = b & 0x02 ? '*' : ' ';
1146 szByte[7] = b & 0x01 ? '*' : ' ';
1147 szByte[8] = '\0';
1148 Log2(("%s", szByte));
1149 }
1150 Log2(("\n"));
1151 }
1152 }
1153
1154 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1155 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1156 for (uint32_t y = 0; y < cy; y++)
1157 {
1158 Log2(("%3u:", y));
1159 uint32_t const *pu32Line = &pu32Xor[y * cx];
1160 for (uint32_t x = 0; x < cx; x++)
1161 Log2((" %08x", pu32Line[x]));
1162 Log2(("\n"));
1163 }
1164 }
1165#endif
1166
1167 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1168 AssertRC(rc);
1169
1170 if (pSVGAState->Cursor.fActive)
1171 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1172
1173 pSVGAState->Cursor.fActive = true;
1174 pSVGAState->Cursor.xHotspot = xHot;
1175 pSVGAState->Cursor.yHotspot = yHot;
1176 pSVGAState->Cursor.width = cx;
1177 pSVGAState->Cursor.height = cy;
1178 pSVGAState->Cursor.cbData = cbData;
1179 pSVGAState->Cursor.pData = pbData;
1180}
1181
1182
1183#ifdef VBOX_WITH_VMSVGA3D
1184
1185/*
1186 * SVGA_3D_CMD_* handlers.
1187 */
1188
1189
1190/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1191 *
1192 * @param pThisCC The VGA/VMSVGA state for the current context.
1193 * @param pCmd The VMSVGA command.
1194 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1195 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1196 */
1197static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1198 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1199{
1200 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1201 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1202 RT_UNTRUSTED_VALIDATED_FENCE();
1203
1204 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1205 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1206 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1207 */
1208 uint32_t cRemainingMipLevels = cMipLevelSizes;
1209 uint32_t cFaces = 0;
1210 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1211 {
1212 if (pCmd->face[i].numMipLevels == 0)
1213 break;
1214
1215 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1216 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1217
1218 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1219 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1220 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1221
1222 ++cFaces;
1223 }
1224 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1225 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1226
1227 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1228 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1229
1230 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1231 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1232 RT_UNTRUSTED_VALIDATED_FENCE();
1233
1234 /* Verify paMipLevelSizes */
1235 uint32_t cWidth = paMipLevelSizes[0].width;
1236 uint32_t cHeight = paMipLevelSizes[0].height;
1237 uint32_t cDepth = paMipLevelSizes[0].depth;
1238 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1239 {
1240 cWidth >>= 1;
1241 if (cWidth == 0) cWidth = 1;
1242 cHeight >>= 1;
1243 if (cHeight == 0) cHeight = 1;
1244 cDepth >>= 1;
1245 if (cDepth == 0) cDepth = 1;
1246 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1247 {
1248 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1249 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1250 && cHeight == paMipLevelSizes[iMipLevelSize].height
1251 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1252 }
1253 }
1254 RT_UNTRUSTED_VALIDATED_FENCE();
1255
1256 /* Create the surface. */
1257 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1258 pCmd->multisampleCount, pCmd->autogenFilter,
1259 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* fAllocMipLevels = */ true);
1260}
1261
1262
1263/* SVGA_3D_CMD_SET_OTABLE_BASE 1091 */
1264static void vmsvga3dCmdSetOTableBase(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase const *pCmd)
1265{
1266 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1267 vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1268 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ false);
1269}
1270
1271
1272/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1273static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1274{
1275 DEBUG_BREAKPOINT_TEST();
1276 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1277
1278 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1279
1280 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1281 /* Allocate a structure for the MOB. */
1282 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1283 AssertPtrReturnVoid(pMob);
1284
1285 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
1286 if (RT_SUCCESS(rc))
1287 {
1288 return;
1289 }
1290
1291 AssertFailed();
1292
1293 RTMemFree(pMob);
1294}
1295
1296
1297/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1298static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1299{
1300 //DEBUG_BREAKPOINT_TEST();
1301 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1302
1303 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1304
1305 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1306 if (RT_SUCCESS(rc))
1307 {
1308 return;
1309 }
1310
1311 AssertFailed();
1312}
1313
1314
1315/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1316static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1317{
1318 //DEBUG_BREAKPOINT_TEST();
1319 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1320
1321 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1322 SVGAOTableSurfaceEntry entry;
1323 RT_ZERO(entry);
1324 entry.format = pCmd->format;
1325 entry.surface1Flags = pCmd->surfaceFlags;
1326 entry.numMipLevels = pCmd->numMipLevels;
1327 entry.multisampleCount = pCmd->multisampleCount;
1328 entry.autogenFilter = pCmd->autogenFilter;
1329 entry.size = pCmd->size;
1330 entry.mobid = SVGA_ID_INVALID;
1331 // entry.arraySize = 0;
1332 // entry.mobPitch = 0;
1333 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1334 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1335 if (RT_SUCCESS(rc))
1336 {
1337 /* Create the host surface. */
1338 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1339 pCmd->multisampleCount, pCmd->autogenFilter,
1340 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* fAllocMipLevels = */ false);
1341 }
1342}
1343
1344
1345/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1346static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1347{
1348 //DEBUG_BREAKPOINT_TEST();
1349 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1350
1351 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1352 SVGAOTableSurfaceEntry entry;
1353 RT_ZERO(entry);
1354 entry.mobid = SVGA_ID_INVALID;
1355 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1356 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1357
1358 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1359}
1360
1361
1362/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1363static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1364{
1365 //DEBUG_BREAKPOINT_TEST();
1366 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1367
1368 /* Assign the mobid to the surface. */
1369 int rc = VINF_SUCCESS;
1370 if (pCmd->mobid != SVGA_ID_INVALID)
1371 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1372 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1373 if (RT_SUCCESS(rc))
1374 {
1375 SVGAOTableSurfaceEntry entry;
1376 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1377 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1378 if (RT_SUCCESS(rc))
1379 {
1380 entry.mobid = pCmd->mobid;
1381 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1382 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1383 if (RT_SUCCESS(rc))
1384 {
1385 /* */
1386 }
1387 }
1388 }
1389}
1390
1391
1392typedef union
1393{
1394 float f;
1395 uint32_t u;
1396} Unsigned2Float;
1397
1398float float16ToFloat(uint16_t f16)
1399{
1400 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1401 uint16_t const f = f16 & 0x3FF;
1402 uint16_t const e = (f16 >> 10) & 0x1F;
1403 uint16_t const s = (f16 >> 15) & 0x1;
1404 Unsigned2Float u2f;
1405
1406 if (e == 0)
1407 {
1408 if (f == 0)
1409 {
1410 /* zero, -0 */
1411 u2f.u = (s << 31) | (0 << 23) | 0;
1412 return u2f.f;
1413 }
1414
1415 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1416 float const k = 1.0f / 16384.0f; /* 2^-14 */
1417 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1418 }
1419
1420 if (e == 31)
1421 {
1422 if (f == 0)
1423 {
1424 /* +-infinity */
1425 u2f.u = (s << 31) | (0xFF << 23) | 0;
1426 return u2f.f;
1427 }
1428
1429 /* NaN */
1430 u2f.u = (s << 31) | (0xFF << 23) | 1;
1431 return u2f.f;
1432 }
1433
1434 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1435 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1436 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1437 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1438 return u2f.f;
1439}
1440
1441
1442static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1443{
1444 if ( pMap->cbBlock != 4 && pMap->cbBlock != 1
1445 && pMap->format != SVGA3D_R16G16B16A16_FLOAT
1446 && pMap->format != SVGA3D_R32G32B32A32_FLOAT)
1447 return VERR_NOT_SUPPORTED;
1448
1449 int const w = pMap->cbRow / pMap->cbBlock;
1450 int const h = pMap->cRows;
1451
1452 const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1453
1454 FILE *f = fopen(pszFilename, "wb");
1455 if (!f)
1456 return VERR_FILE_NOT_FOUND;
1457
1458#ifdef RT_OS_WINDOWS
1459 if (pMap->cbBlock == 4)
1460 {
1461 BMPFILEHDR fileHdr;
1462 RT_ZERO(fileHdr);
1463 fileHdr.uType = BMP_HDR_MAGIC;
1464 fileHdr.cbFileSize = sizeof(fileHdr) + sizeof(BITMAPV4HEADER) + cbBitmap;
1465 fileHdr.offBits = sizeof(fileHdr) + sizeof(BITMAPV4HEADER);
1466
1467 BITMAPV4HEADER hdrV4;
1468 RT_ZERO(hdrV4);
1469 hdrV4.bV4Size = sizeof(hdrV4);
1470 hdrV4.bV4Width = w;
1471 hdrV4.bV4Height = -h;
1472 hdrV4.bV4Planes = 1;
1473 hdrV4.bV4BitCount = 32;
1474 hdrV4.bV4V4Compression = BI_BITFIELDS;
1475 hdrV4.bV4SizeImage = cbBitmap;
1476 hdrV4.bV4XPelsPerMeter = 2835;
1477 hdrV4.bV4YPelsPerMeter = 2835;
1478 // hdrV4.bV4ClrUsed = 0;
1479 // hdrV4.bV4ClrImportant = 0;
1480 hdrV4.bV4RedMask = 0x00ff0000;
1481 hdrV4.bV4GreenMask = 0x0000ff00;
1482 hdrV4.bV4BlueMask = 0x000000ff;
1483 hdrV4.bV4AlphaMask = 0xff000000;
1484 hdrV4.bV4CSType = LCS_WINDOWS_COLOR_SPACE;
1485 // hdrV4.bV4Endpoints = {0};
1486 // hdrV4.bV4GammaRed = 0;
1487 // hdrV4.bV4GammaGreen = 0;
1488 // hdrV4.bV4GammaBlue = 0;
1489
1490 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1491 fwrite(&hdrV4, 1, sizeof(hdrV4), f);
1492 }
1493 else
1494#endif
1495 {
1496 BMPFILEHDR fileHdr;
1497 RT_ZERO(fileHdr);
1498 fileHdr.uType = BMP_HDR_MAGIC;
1499 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1500 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1501
1502 BMPWIN3XINFOHDR coreHdr;
1503 RT_ZERO(coreHdr);
1504 coreHdr.cbSize = sizeof(coreHdr);
1505 coreHdr.uWidth = w;
1506 coreHdr.uHeight = -h;
1507 coreHdr.cPlanes = 1;
1508 coreHdr.cBits = 32;
1509 coreHdr.cbSizeImage = cbBitmap;
1510
1511 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1512 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1513 }
1514
1515 if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1516 {
1517 const uint8_t *s = (uint8_t *)pMap->pvData;
1518 for (int32_t y = 0; y < h; ++y)
1519 {
1520 for (int32_t x = 0; x < w; ++x)
1521 {
1522 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1523 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1524 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1525 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1526 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1527 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1528 fwrite(&u32Pixel, 1, 4, f);
1529 }
1530
1531 s += pMap->cbRowPitch;
1532 }
1533 }
1534 else if (pMap->format == SVGA3D_R32G32B32A32_FLOAT)
1535 {
1536 const uint8_t *s = (uint8_t *)pMap->pvData;
1537 for (int32_t y = 0; y < h; ++y)
1538 {
1539 for (int32_t x = 0; x < w; ++x)
1540 {
1541 float const *pPixel = (float *)(s + x * 8);
1542 uint8_t r = (uint8_t)(255.0 * pPixel[0]);
1543 uint8_t g = (uint8_t)(255.0 * pPixel[1]);
1544 uint8_t b = (uint8_t)(255.0 * pPixel[2]);
1545 uint8_t a = (uint8_t)(255.0 * pPixel[3]);
1546 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1547 fwrite(&u32Pixel, 1, 4, f);
1548 }
1549
1550 s += pMap->cbRowPitch;
1551 }
1552 }
1553 else if (pMap->cbBlock == 4)
1554 {
1555 const uint8_t *s = (uint8_t *)pMap->pvData;
1556 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1557 {
1558 fwrite(s, 1, pMap->cbRow, f);
1559
1560 s += pMap->cbRowPitch;
1561 }
1562 }
1563 else if (pMap->cbBlock == 1)
1564 {
1565 const uint8_t *s = (uint8_t *)pMap->pvData;
1566 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1567 {
1568 for (int32_t x = 0; x < w; ++x)
1569 {
1570 uint32_t u32Pixel = s[x];
1571 fwrite(&u32Pixel, 1, 4, f);
1572 }
1573
1574 s += pMap->cbRowPitch;
1575 }
1576 }
1577
1578 fclose(f);
1579
1580 return VINF_SUCCESS;
1581}
1582
1583
1584void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1585{
1586 static int idxBitmap = 0;
1587 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1588 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1589 Log(("WriteBmpFile %s format %d %Rrc\n", pszFilename, pMap->format, rc)); RT_NOREF(rc);
1590 RTStrFree(pszFilename);
1591}
1592
1593
1594static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1595 PVMSVGAMOB pMob,
1596 SVGA3dSurfaceImageId const *pImage,
1597 SVGA3dBox const *pBox,
1598 SVGA3dTransferType enmTransfer)
1599{
1600 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1601
1602 VMSVGA3D_SURFACE_MAP enmMapType;
1603 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1604 enmMapType = pBox
1605 ? VMSVGA3D_SURFACE_MAP_WRITE
1606 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1607 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1608 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1609 else
1610 AssertFailedReturn(VERR_INVALID_PARAMETER);
1611
1612 VMSVGA3D_MAPPED_SURFACE map;
1613 int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1614 if (RT_SUCCESS(rc))
1615 {
1616 /* Copy mapped surface <-> MOB. */
1617 VMSGA3D_BOX_DIMENSIONS dims;
1618 rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1619 if (RT_SUCCESS(rc))
1620 {
1621 for (uint32_t z = 0; z < map.box.d; ++z)
1622 {
1623 uint8_t *pu8Map = (uint8_t *)map.pvData + z * map.cbDepthPitch;
1624 uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1625
1626 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1627 {
1628 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1629 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1630 else
1631 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1632 AssertRCBreak(rc);
1633
1634 pu8Map += map.cbRowPitch;
1635 offMob += dims.cbPitch;
1636 }
1637 }
1638 }
1639
1640 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1641
1642 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1643 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1644 }
1645
1646 return rc;
1647}
1648
1649
1650/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1651static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1652{
1653 //DEBUG_BREAKPOINT_TEST();
1654 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1655
1656 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1657 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1658
1659/*
1660 SVGA3dSurfaceFormat format;
1661 SVGA3dSurface1Flags surface1Flags;
1662 uint32 numMipLevels;
1663 uint32 multisampleCount;
1664 SVGA3dTextureFilter autogenFilter;
1665 SVGA3dSize size;
1666 SVGAMobId mobid;
1667 uint32 arraySize;
1668 uint32 mobPitch;
1669 SVGA3dSurface2Flags surface2Flags;
1670 uint8 multisamplePattern;
1671 uint8 qualityLevel;
1672 uint16 bufferByteStride;
1673 float minLOD;
1674*/
1675
1676 /* "update a surface from its backing MOB." */
1677 SVGAOTableSurfaceEntry entrySurface;
1678 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1679 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1680 if (RT_SUCCESS(rc))
1681 {
1682 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1683 if (pMob)
1684 {
1685 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1686 AssertRC(rc);
1687 }
1688 }
1689}
1690
1691
1692/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1693static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1694{
1695 //DEBUG_BREAKPOINT_TEST();
1696 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1697
1698 LogFlowFunc(("sid=%u\n",
1699 pCmd->sid));
1700
1701 /* "update a surface from its backing MOB." */
1702 SVGAOTableSurfaceEntry entrySurface;
1703 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1704 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1705 if (RT_SUCCESS(rc))
1706 {
1707 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1708 if (pMob)
1709 {
1710 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1711 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1712 {
1713 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1714 {
1715 SVGA3dSurfaceImageId image;
1716 image.sid = pCmd->sid;
1717 image.face = iArray;
1718 image.mipmap = iMipmap;
1719
1720 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1721 AssertRCBreak(rc);
1722 }
1723 }
1724 }
1725 }
1726}
1727
1728
1729/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1730static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1731{
1732 //DEBUG_BREAKPOINT_TEST();
1733 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1734
1735 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1736 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1737
1738 /* Read a surface to its backing MOB. */
1739 SVGAOTableSurfaceEntry entrySurface;
1740 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1741 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1742 if (RT_SUCCESS(rc))
1743 {
1744 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1745 if (pMob)
1746 {
1747 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1748 AssertRC(rc);
1749 }
1750 }
1751}
1752
1753
1754/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1755static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1756{
1757 //DEBUG_BREAKPOINT_TEST();
1758 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1759
1760 LogFlowFunc(("sid=%u\n",
1761 pCmd->sid));
1762
1763 /* Read a surface to its backing MOB. */
1764 SVGAOTableSurfaceEntry entrySurface;
1765 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1766 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1767 if (RT_SUCCESS(rc))
1768 {
1769 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1770 if (pMob)
1771 {
1772 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1773 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1774 {
1775 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1776 {
1777 SVGA3dSurfaceImageId image;
1778 image.sid = pCmd->sid;
1779 image.face = iArray;
1780 image.mipmap = iMipmap;
1781
1782 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1783 AssertRCBreak(rc);
1784 }
1785 }
1786 }
1787 }
1788}
1789
1790
1791/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1792static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1793{
1794 //DEBUG_BREAKPOINT_TEST();
1795 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1796}
1797
1798
1799/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1800static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1801{
1802 //DEBUG_BREAKPOINT_TEST();
1803 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1804}
1805
1806
1807/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1808static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1809{
1810 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1811 vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1812 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ false);
1813}
1814
1815
1816/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1817static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1818{
1819 //DEBUG_BREAKPOINT_TEST();
1820 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1821
1822 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1823 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1824 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1825 RT_UNTRUSTED_VALIDATED_FENCE();
1826
1827 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1828 SVGAOTableScreenTargetEntry entry;
1829 RT_ZERO(entry);
1830 entry.image.sid = SVGA_ID_INVALID;
1831 // entry.image.face = 0;
1832 // entry.image.mipmap = 0;
1833 entry.width = pCmd->width;
1834 entry.height = pCmd->height;
1835 entry.xRoot = pCmd->xRoot;
1836 entry.yRoot = pCmd->yRoot;
1837 entry.flags = pCmd->flags;
1838 entry.dpi = pCmd->dpi;
1839
1840 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1841 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1842 if (RT_SUCCESS(rc))
1843 {
1844 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1845 /** @todo Generic screen object/target interface. */
1846 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1847 Assert(pScreen->idScreen == pCmd->stid);
1848 pScreen->fDefined = true;
1849 pScreen->fModified = true;
1850 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1851 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1852
1853 pScreen->xOrigin = pCmd->xRoot;
1854 pScreen->yOrigin = pCmd->yRoot;
1855 pScreen->cWidth = pCmd->width;
1856 pScreen->cHeight = pCmd->height;
1857 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1858 pScreen->cbPitch = pCmd->width * 4;
1859 pScreen->cBpp = 32;
1860
1861 if (RT_LIKELY(pThis->svga.f3DEnabled))
1862 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1863
1864 if (!pScreen->pHwScreen)
1865 {
1866 /* System memory buffer. */
1867 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1868 }
1869
1870 pThis->svga.fGFBRegisters = false;
1871 vmsvgaR3ChangeMode(pThis, pThisCC);
1872 }
1873}
1874
1875
1876/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1877static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1878{
1879 //DEBUG_BREAKPOINT_TEST();
1880 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1881
1882 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1883 RT_UNTRUSTED_VALIDATED_FENCE();
1884
1885 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1886 SVGAOTableScreenTargetEntry entry;
1887 RT_ZERO(entry);
1888 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1889 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1890 if (RT_SUCCESS(rc))
1891 {
1892 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1893 /** @todo Generic screen object/target interface. */
1894 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1895 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
1896 }
1897}
1898
1899
1900/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1901static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1902{
1903 //DEBUG_BREAKPOINT_TEST();
1904 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1905
1906 /* "Binding a surface to a Screen Target the same as flipping" */
1907
1908 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1909 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1910 RT_UNTRUSTED_VALIDATED_FENCE();
1911
1912 /* Assign the surface to the screen target. */
1913 int rc = VINF_SUCCESS;
1914 if (pCmd->image.sid != SVGA_ID_INVALID)
1915 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1916 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1917 if (RT_SUCCESS(rc))
1918 {
1919 SVGAOTableScreenTargetEntry entry;
1920 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1921 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1922 if (RT_SUCCESS(rc))
1923 {
1924 entry.image = pCmd->image;
1925 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1926 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1927 if (RT_SUCCESS(rc))
1928 {
1929 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1930 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1931 AssertRC(rc);
1932 }
1933 }
1934 }
1935}
1936
1937
1938/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1939static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1940{
1941 //DEBUG_BREAKPOINT_TEST();
1942 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1943
1944 /* Update the screen target from its backing surface. */
1945 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1946 RT_UNTRUSTED_VALIDATED_FENCE();
1947
1948 /* Get the screen target info. */
1949 SVGAOTableScreenTargetEntry entryScreenTarget;
1950 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1951 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1952 if (RT_SUCCESS(rc))
1953 {
1954 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1955 RT_UNTRUSTED_VALIDATED_FENCE();
1956
1957 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1958 {
1959 SVGAOTableSurfaceEntry entrySurface;
1960 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1961 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1962 if (RT_SUCCESS(rc))
1963 {
1964 /* Copy entrySurface.mobid content to the screen target. */
1965 if (entrySurface.mobid != SVGA_ID_INVALID)
1966 {
1967 RT_UNTRUSTED_VALIDATED_FENCE();
1968 SVGA3dRect targetRect = pCmd->rect;
1969
1970 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1971 if (pScreen->pHwScreen)
1972 {
1973 /* Copy the screen target surface to the backend's screen. */
1974 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1975 }
1976 else
1977 {
1978 SVGASignedRect r;
1979 r.left = pCmd->rect.x;
1980 r.top = pCmd->rect.y;
1981 r.right = pCmd->rect.x + pCmd->rect.w;
1982 r.bottom = pCmd->rect.y + pCmd->rect.h;
1983 vmsvga3dScreenUpdate(pThisCC, pCmd->stid, r, entryScreenTarget.image, r, 0, NULL);
1984 }
1985 }
1986 }
1987 }
1988 }
1989}
1990
1991
1992/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1993static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1994{
1995 //DEBUG_BREAKPOINT_TEST();
1996 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1997
1998 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1999 SVGAOTableSurfaceEntry entry;
2000 RT_ZERO(entry);
2001 entry.format = pCmd->format;
2002 entry.surface1Flags = pCmd->surfaceFlags;
2003 entry.numMipLevels = pCmd->numMipLevels;
2004 entry.multisampleCount = pCmd->multisampleCount;
2005 entry.autogenFilter = pCmd->autogenFilter;
2006 entry.size = pCmd->size;
2007 entry.mobid = SVGA_ID_INVALID;
2008 entry.arraySize = pCmd->arraySize;
2009 // entry.mobPitch = 0;
2010 // entry.mobPitch = 0;
2011 // entry.surface2Flags = 0;
2012 // entry.multisamplePattern = 0;
2013 // entry.qualityLevel = 0;
2014 // entry.bufferByteStride = 0;
2015 // entry.minLOD = 0;
2016
2017 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2018 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
2019 if (RT_SUCCESS(rc))
2020 {
2021 /* Create the host surface. */
2022 /** @todo SVGAOTableSurfaceEntry as input parameter? */
2023 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
2024 pCmd->multisampleCount, pCmd->autogenFilter,
2025 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
2026 }
2027}
2028
2029
2030/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
2031static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
2032{
2033 //DEBUG_BREAKPOINT_TEST();
2034 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2035
2036 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
2037
2038 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
2039 /* Allocate a structure for the MOB. */
2040 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
2041 AssertPtrReturnVoid(pMob);
2042
2043 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
2044 if (RT_SUCCESS(rc))
2045 {
2046 return;
2047 }
2048
2049 RTMemFree(pMob);
2050}
2051
2052
2053/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
2054static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
2055{
2056#ifdef VMSVGA3D_DX
2057 //DEBUG_BREAKPOINT_TEST();
2058 RT_NOREF(cbCmd);
2059
2060 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2061
2062 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2063 SVGAOTableDXContextEntry entry;
2064 RT_ZERO(entry);
2065 entry.cid = pCmd->cid;
2066 entry.mobid = SVGA_ID_INVALID;
2067 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2068 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2069 if (RT_SUCCESS(rc))
2070 {
2071 /* Create the host context. */
2072 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2073 }
2074
2075 return rc;
2076#else
2077 RT_NOREF(pThisCC, pCmd, cbCmd);
2078 return VERR_NOT_SUPPORTED;
2079#endif
2080}
2081
2082
2083/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2084static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2085{
2086#ifdef VMSVGA3D_DX
2087 //DEBUG_BREAKPOINT_TEST();
2088 RT_NOREF(cbCmd);
2089
2090 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2091
2092 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2093 SVGAOTableDXContextEntry entry;
2094 RT_ZERO(entry);
2095 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2096 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2097
2098 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2099#else
2100 RT_NOREF(pThisCC, pCmd, cbCmd);
2101 return VERR_NOT_SUPPORTED;
2102#endif
2103}
2104
2105
2106/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2107static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2108{
2109#ifdef VMSVGA3D_DX
2110 //DEBUG_BREAKPOINT_TEST();
2111 RT_NOREF(cbCmd);
2112
2113 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2114
2115 /* Assign a mobid to a cid. */
2116 int rc = VINF_SUCCESS;
2117 if (pCmd->mobid != SVGA_ID_INVALID)
2118 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2119 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2120 if (RT_SUCCESS(rc))
2121 {
2122 SVGAOTableDXContextEntry entry;
2123 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2124 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2125 if (RT_SUCCESS(rc))
2126 {
2127 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2128 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2129 {
2130 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2131 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2132 if (pSvgaDXContext)
2133 {
2134 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2135 if (RT_SUCCESS(rc))
2136 {
2137 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2138 if (pMob)
2139 {
2140 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2141 }
2142 }
2143
2144 RTMemFree(pSvgaDXContext);
2145 pSvgaDXContext = NULL;
2146 }
2147 }
2148
2149 if (pCmd->mobid != SVGA_ID_INVALID)
2150 {
2151 /* Bind a new context. Copy existing data from the guest backing memory. */
2152 if (pCmd->validContents)
2153 {
2154 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2155 if (pMob)
2156 {
2157 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2158 if (pSvgaDXContext)
2159 {
2160 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2161 if (RT_FAILURE(rc))
2162 {
2163 RTMemFree(pSvgaDXContext);
2164 pSvgaDXContext = NULL;
2165 }
2166 }
2167 }
2168 }
2169
2170 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2171
2172 RTMemFree(pSvgaDXContext);
2173 }
2174
2175 /* Update the object table. */
2176 entry.mobid = pCmd->mobid;
2177 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2178 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2179 }
2180 }
2181
2182 return rc;
2183#else
2184 RT_NOREF(pThisCC, pCmd, cbCmd);
2185 return VERR_NOT_SUPPORTED;
2186#endif
2187}
2188
2189
2190/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2191static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2192{
2193#ifdef VMSVGA3D_DX
2194 //DEBUG_BREAKPOINT_TEST();
2195 RT_NOREF(cbCmd);
2196
2197 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2198
2199 /* "Request that the device flush the contents back into guest memory." */
2200 SVGAOTableDXContextEntry entry;
2201 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2202 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2203 if (RT_SUCCESS(rc))
2204 {
2205 if (entry.mobid != SVGA_ID_INVALID)
2206 {
2207 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2208 if (pMob)
2209 {
2210 /* Get the content. */
2211 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2212 if (pSvgaDXContext)
2213 {
2214 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2215 if (RT_SUCCESS(rc))
2216 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2217
2218 RTMemFree(pSvgaDXContext);
2219 }
2220 else
2221 rc = VERR_NO_MEMORY;
2222 }
2223 }
2224 }
2225
2226 return rc;
2227#else
2228 RT_NOREF(pThisCC, pCmd, cbCmd);
2229 return VERR_NOT_SUPPORTED;
2230#endif
2231}
2232
2233
2234/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2235static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2236{
2237#ifdef VMSVGA3D_DX
2238 DEBUG_BREAKPOINT_TEST();
2239 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2240 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2241 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2242#else
2243 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2244 return VERR_NOT_SUPPORTED;
2245#endif
2246}
2247
2248
2249/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2250static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2251{
2252#ifdef VMSVGA3D_DX
2253 //DEBUG_BREAKPOINT_TEST();
2254 RT_NOREF(cbCmd);
2255 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2256#else
2257 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2258 return VERR_NOT_SUPPORTED;
2259#endif
2260}
2261
2262
2263/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2264static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2265{
2266#ifdef VMSVGA3D_DX
2267 //DEBUG_BREAKPOINT_TEST();
2268 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2269 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2270 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2271#else
2272 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2273 return VERR_NOT_SUPPORTED;
2274#endif
2275}
2276
2277
2278/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2279static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2280{
2281#ifdef VMSVGA3D_DX
2282 //DEBUG_BREAKPOINT_TEST();
2283 RT_NOREF(cbCmd);
2284 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2285#else
2286 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2287 return VERR_NOT_SUPPORTED;
2288#endif
2289}
2290
2291
2292/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2293static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2294{
2295#ifdef VMSVGA3D_DX
2296 //DEBUG_BREAKPOINT_TEST();
2297 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2298 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2299 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2300#else
2301 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2302 return VERR_NOT_SUPPORTED;
2303#endif
2304}
2305
2306
2307/* SVGA_3D_CMD_DX_DRAW 1152 */
2308static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2309{
2310#ifdef VMSVGA3D_DX
2311 //DEBUG_BREAKPOINT_TEST();
2312 RT_NOREF(cbCmd);
2313 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2314#else
2315 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2316 return VERR_NOT_SUPPORTED;
2317#endif
2318}
2319
2320
2321/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2322static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2323{
2324#ifdef VMSVGA3D_DX
2325 //DEBUG_BREAKPOINT_TEST();
2326 RT_NOREF(cbCmd);
2327 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2328#else
2329 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2330 return VERR_NOT_SUPPORTED;
2331#endif
2332}
2333
2334
2335/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2336static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2337{
2338#ifdef VMSVGA3D_DX
2339 //DEBUG_BREAKPOINT_TEST();
2340 RT_NOREF(cbCmd);
2341 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2342#else
2343 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2344 return VERR_NOT_SUPPORTED;
2345#endif
2346}
2347
2348
2349/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2350static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2351{
2352#ifdef VMSVGA3D_DX
2353 //DEBUG_BREAKPOINT_TEST();
2354 RT_NOREF(cbCmd);
2355 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2356#else
2357 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2358 return VERR_NOT_SUPPORTED;
2359#endif
2360}
2361
2362
2363/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2364static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2365{
2366#ifdef VMSVGA3D_DX
2367 //DEBUG_BREAKPOINT_TEST();
2368 RT_NOREF(pCmd, cbCmd);
2369 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2370#else
2371 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2372 return VERR_NOT_SUPPORTED;
2373#endif
2374}
2375
2376
2377/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2378static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2379{
2380#ifdef VMSVGA3D_DX
2381 //DEBUG_BREAKPOINT_TEST();
2382 RT_NOREF(cbCmd);
2383 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2384#else
2385 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2386 return VERR_NOT_SUPPORTED;
2387#endif
2388}
2389
2390
2391/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2392static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2393{
2394#ifdef VMSVGA3D_DX
2395 //DEBUG_BREAKPOINT_TEST();
2396 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2397 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2398 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2399#else
2400 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2401 return VERR_NOT_SUPPORTED;
2402#endif
2403}
2404
2405
2406/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2407static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2408{
2409#ifdef VMSVGA3D_DX
2410 //DEBUG_BREAKPOINT_TEST();
2411 RT_NOREF(cbCmd);
2412 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2413#else
2414 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2415 return VERR_NOT_SUPPORTED;
2416#endif
2417}
2418
2419
2420/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2421static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2422{
2423#ifdef VMSVGA3D_DX
2424 //DEBUG_BREAKPOINT_TEST();
2425 RT_NOREF(cbCmd);
2426 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2427#else
2428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2429 return VERR_NOT_SUPPORTED;
2430#endif
2431}
2432
2433
2434/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2435static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2436{
2437#ifdef VMSVGA3D_DX
2438 //DEBUG_BREAKPOINT_TEST();
2439 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2440 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2441 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2442#else
2443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2444 return VERR_NOT_SUPPORTED;
2445#endif
2446}
2447
2448
2449/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2450static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2451{
2452#ifdef VMSVGA3D_DX
2453 //DEBUG_BREAKPOINT_TEST();
2454 RT_NOREF(cbCmd);
2455 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2456#else
2457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2458 return VERR_NOT_SUPPORTED;
2459#endif
2460}
2461
2462
2463/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2464static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2465{
2466#ifdef VMSVGA3D_DX
2467 //DEBUG_BREAKPOINT_TEST();
2468 RT_NOREF(cbCmd);
2469 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2470#else
2471 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2472 return VERR_NOT_SUPPORTED;
2473#endif
2474}
2475
2476
2477/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2478static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2479{
2480#ifdef VMSVGA3D_DX
2481 //DEBUG_BREAKPOINT_TEST();
2482 RT_NOREF(cbCmd);
2483 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2484#else
2485 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2486 return VERR_NOT_SUPPORTED;
2487#endif
2488}
2489
2490
2491/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2492static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2493{
2494#ifdef VMSVGA3D_DX
2495 //DEBUG_BREAKPOINT_TEST();
2496 RT_NOREF(cbCmd);
2497 return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2498#else
2499 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2500 return VERR_NOT_SUPPORTED;
2501#endif
2502}
2503
2504
2505/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2506static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2507{
2508#ifdef VMSVGA3D_DX
2509 //DEBUG_BREAKPOINT_TEST();
2510 RT_NOREF(cbCmd);
2511 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2512#else
2513 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2514 return VERR_NOT_SUPPORTED;
2515#endif
2516}
2517
2518
2519/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2520static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2521{
2522#ifdef VMSVGA3D_DX
2523 //DEBUG_BREAKPOINT_TEST();
2524 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2525 RT_NOREF(cbCmd);
2526 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2527 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2528 return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2529#else
2530 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2531 return VERR_NOT_SUPPORTED;
2532#endif
2533}
2534
2535
2536/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2537static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2538{
2539#ifdef VMSVGA3D_DX
2540 //DEBUG_BREAKPOINT_TEST();
2541 RT_NOREF(cbCmd);
2542 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2543#else
2544 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2545 return VERR_NOT_SUPPORTED;
2546#endif
2547}
2548
2549
2550/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2551static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2552{
2553#ifdef VMSVGA3D_DX
2554 //DEBUG_BREAKPOINT_TEST();
2555 RT_NOREF(cbCmd);
2556 return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2557#else
2558 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2559 return VERR_NOT_SUPPORTED;
2560#endif
2561}
2562
2563
2564/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2565static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2566{
2567#ifdef VMSVGA3D_DX
2568 //DEBUG_BREAKPOINT_TEST();
2569 RT_NOREF(cbCmd);
2570 return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2571#else
2572 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2573 return VERR_NOT_SUPPORTED;
2574#endif
2575}
2576
2577
2578/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2579static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2580{
2581#ifdef VMSVGA3D_DX
2582 //DEBUG_BREAKPOINT_TEST();
2583 RT_NOREF(cbCmd);
2584 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2585#else
2586 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2587 return VERR_NOT_SUPPORTED;
2588#endif
2589}
2590
2591
2592/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2593static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2594{
2595#ifdef VMSVGA3D_DX
2596 //DEBUG_BREAKPOINT_TEST();
2597 RT_NOREF(cbCmd);
2598 return vmsvga3dDXSetPredication(pThisCC, idDXContext, pCmd);
2599#else
2600 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2601 return VERR_NOT_SUPPORTED;
2602#endif
2603}
2604
2605
2606/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2607static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2608{
2609#ifdef VMSVGA3D_DX
2610 //DEBUG_BREAKPOINT_TEST();
2611 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2612 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2613 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2614#else
2615 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2616 return VERR_NOT_SUPPORTED;
2617#endif
2618}
2619
2620
2621/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2622static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2623{
2624#ifdef VMSVGA3D_DX
2625 //DEBUG_BREAKPOINT_TEST();
2626 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2627 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2628 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2629#else
2630 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2631 return VERR_NOT_SUPPORTED;
2632#endif
2633}
2634
2635
2636/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2637static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2638{
2639#ifdef VMSVGA3D_DX
2640 //DEBUG_BREAKPOINT_TEST();
2641 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2642 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2643 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2644#else
2645 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2646 return VERR_NOT_SUPPORTED;
2647#endif
2648}
2649
2650
2651/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2652static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2653{
2654#ifdef VMSVGA3D_DX
2655 //DEBUG_BREAKPOINT_TEST();
2656 RT_NOREF(cbCmd);
2657 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2658#else
2659 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2660 return VERR_NOT_SUPPORTED;
2661#endif
2662}
2663
2664
2665/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2666static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2667{
2668#ifdef VMSVGA3D_DX
2669 //DEBUG_BREAKPOINT_TEST();
2670 RT_NOREF(cbCmd);
2671 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2672#else
2673 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2674 return VERR_NOT_SUPPORTED;
2675#endif
2676}
2677
2678
2679/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2680static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2681{
2682#ifdef VMSVGA3D_DX
2683 //DEBUG_BREAKPOINT_TEST();
2684 RT_NOREF(cbCmd);
2685 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2686#else
2687 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2688 return VERR_NOT_SUPPORTED;
2689#endif
2690}
2691
2692
2693/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2694static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2695{
2696#ifdef VMSVGA3D_DX
2697 //DEBUG_BREAKPOINT_TEST();
2698 RT_NOREF(cbCmd);
2699 return vmsvga3dDXPredCopy(pThisCC, idDXContext, pCmd);
2700#else
2701 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2702 return VERR_NOT_SUPPORTED;
2703#endif
2704}
2705
2706
2707/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2708static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2709{
2710#ifdef VMSVGA3D_DX
2711 //DEBUG_BREAKPOINT_TEST();
2712 RT_NOREF(cbCmd);
2713 return vmsvga3dDXPresentBlt(pThisCC, idDXContext, pCmd);
2714#else
2715 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2716 return VERR_NOT_SUPPORTED;
2717#endif
2718}
2719
2720
2721/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2722static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2723{
2724#ifdef VMSVGA3D_DX
2725 //DEBUG_BREAKPOINT_TEST();
2726 RT_NOREF(cbCmd);
2727 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2728#else
2729 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2730 return VERR_NOT_SUPPORTED;
2731#endif
2732}
2733
2734
2735/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2736static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2737{
2738#ifdef VMSVGA3D_DX
2739 //DEBUG_BREAKPOINT_TEST();
2740 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2741 RT_NOREF(cbCmd);
2742
2743 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2744 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
2745
2746 /* "Inform the device that the guest-contents have been updated." */
2747 SVGAOTableSurfaceEntry entrySurface;
2748 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2749 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2750 if (RT_SUCCESS(rc))
2751 {
2752 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2753 if (pMob)
2754 {
2755 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2756 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2757 /* pCmd->box will be verified by the mapping function. */
2758 RT_UNTRUSTED_VALIDATED_FENCE();
2759
2760 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2761 SVGA3dSurfaceImageId image;
2762 image.sid = pCmd->sid;
2763 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2764
2765 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2766 AssertRC(rc);
2767 }
2768 }
2769
2770 return rc;
2771#else
2772 RT_NOREF(pThisCC, pCmd, cbCmd);
2773 return VERR_NOT_SUPPORTED;
2774#endif
2775}
2776
2777
2778/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2779static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2780{
2781#ifdef VMSVGA3D_DX
2782 //DEBUG_BREAKPOINT_TEST();
2783 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2784 RT_NOREF(cbCmd);
2785
2786 LogFlowFunc(("sid=%u, subResource=%u\n",
2787 pCmd->sid, pCmd->subResource));
2788
2789 /* "Request the device to flush the dirty contents into the guest." */
2790 SVGAOTableSurfaceEntry entrySurface;
2791 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2792 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2793 if (RT_SUCCESS(rc))
2794 {
2795 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2796 if (pMob)
2797 {
2798 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2799 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2800 RT_UNTRUSTED_VALIDATED_FENCE();
2801
2802 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2803 SVGA3dSurfaceImageId image;
2804 image.sid = pCmd->sid;
2805 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2806
2807 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2808 AssertRC(rc);
2809 }
2810 }
2811
2812 return rc;
2813#else
2814 RT_NOREF(pThisCC, pCmd, cbCmd);
2815 return VERR_NOT_SUPPORTED;
2816#endif
2817}
2818
2819
2820/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2821static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2822{
2823#ifdef VMSVGA3D_DX
2824 DEBUG_BREAKPOINT_TEST();
2825 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2826 RT_NOREF(cbCmd);
2827
2828 LogFlowFunc(("sid=%u, subResource=%u\n",
2829 pCmd->sid, pCmd->subResource));
2830
2831 /* "Notify the device that the contents can be lost." */
2832 SVGAOTableSurfaceEntry entrySurface;
2833 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2834 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2835 if (RT_SUCCESS(rc))
2836 {
2837 uint32_t iFace;
2838 uint32_t iMipmap;
2839 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2840 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2841 }
2842
2843 return rc;
2844#else
2845 RT_NOREF(pThisCC, pCmd, cbCmd);
2846 return VERR_NOT_SUPPORTED;
2847#endif
2848}
2849
2850
2851/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2852static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2853{
2854#ifdef VMSVGA3D_DX
2855 //DEBUG_BREAKPOINT_TEST();
2856 RT_NOREF(cbCmd);
2857 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2858#else
2859 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2860 return VERR_NOT_SUPPORTED;
2861#endif
2862}
2863
2864
2865/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2866static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2867{
2868#ifdef VMSVGA3D_DX
2869 //DEBUG_BREAKPOINT_TEST();
2870 RT_NOREF(cbCmd);
2871 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2872#else
2873 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2874 return VERR_NOT_SUPPORTED;
2875#endif
2876}
2877
2878
2879/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2880static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2881{
2882#ifdef VMSVGA3D_DX
2883 //DEBUG_BREAKPOINT_TEST();
2884 RT_NOREF(cbCmd);
2885 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2886#else
2887 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2888 return VERR_NOT_SUPPORTED;
2889#endif
2890}
2891
2892
2893/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2894static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2895{
2896#ifdef VMSVGA3D_DX
2897 //DEBUG_BREAKPOINT_TEST();
2898 RT_NOREF(cbCmd);
2899 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2900#else
2901 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2902 return VERR_NOT_SUPPORTED;
2903#endif
2904}
2905
2906
2907/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2908static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2909{
2910#ifdef VMSVGA3D_DX
2911 //DEBUG_BREAKPOINT_TEST();
2912 RT_NOREF(cbCmd);
2913 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2914 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2915 cmd.sid = pCmd->sid;
2916 cmd.format = pCmd->format;
2917 cmd.resourceDimension = pCmd->resourceDimension;
2918 cmd.mipSlice = pCmd->mipSlice;
2919 cmd.firstArraySlice = pCmd->firstArraySlice;
2920 cmd.arraySize = pCmd->arraySize;
2921 cmd.flags = 0;
2922 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2923#else
2924 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2925 return VERR_NOT_SUPPORTED;
2926#endif
2927}
2928
2929
2930/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2931static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2932{
2933#ifdef VMSVGA3D_DX
2934 //DEBUG_BREAKPOINT_TEST();
2935 RT_NOREF(cbCmd);
2936 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2937#else
2938 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2939 return VERR_NOT_SUPPORTED;
2940#endif
2941}
2942
2943
2944/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2945static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2946{
2947#ifdef VMSVGA3D_DX
2948 //DEBUG_BREAKPOINT_TEST();
2949 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2950 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2951 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2952#else
2953 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2954 return VERR_NOT_SUPPORTED;
2955#endif
2956}
2957
2958
2959/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2960static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2961{
2962#ifdef VMSVGA3D_DX
2963 //DEBUG_BREAKPOINT_TEST();
2964 RT_NOREF(cbCmd);
2965 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
2966#else
2967 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2968 return VERR_NOT_SUPPORTED;
2969#endif
2970}
2971
2972
2973/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2974static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2975{
2976#ifdef VMSVGA3D_DX
2977 //DEBUG_BREAKPOINT_TEST();
2978 RT_NOREF(cbCmd);
2979 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2980#else
2981 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2982 return VERR_NOT_SUPPORTED;
2983#endif
2984}
2985
2986
2987/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2988static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2989{
2990#ifdef VMSVGA3D_DX
2991 //DEBUG_BREAKPOINT_TEST();
2992 RT_NOREF(cbCmd);
2993 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
2994#else
2995 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2996 return VERR_NOT_SUPPORTED;
2997#endif
2998}
2999
3000
3001/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
3002static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
3003{
3004#ifdef VMSVGA3D_DX
3005 //DEBUG_BREAKPOINT_TEST();
3006 RT_NOREF(cbCmd);
3007 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
3008#else
3009 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3010 return VERR_NOT_SUPPORTED;
3011#endif
3012}
3013
3014
3015/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
3016static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
3017{
3018#ifdef VMSVGA3D_DX
3019 //DEBUG_BREAKPOINT_TEST();
3020 RT_NOREF(cbCmd);
3021 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
3022#else
3023 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3024 return VERR_NOT_SUPPORTED;
3025#endif
3026}
3027
3028
3029/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
3030static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
3031{
3032#ifdef VMSVGA3D_DX
3033 //DEBUG_BREAKPOINT_TEST();
3034 RT_NOREF(cbCmd);
3035 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
3036#else
3037 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3038 return VERR_NOT_SUPPORTED;
3039#endif
3040}
3041
3042
3043/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
3044static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
3045{
3046#ifdef VMSVGA3D_DX
3047 //DEBUG_BREAKPOINT_TEST();
3048 RT_NOREF(cbCmd);
3049 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
3050#else
3051 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3052 return VERR_NOT_SUPPORTED;
3053#endif
3054}
3055
3056
3057/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3058static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3059{
3060#ifdef VMSVGA3D_DX
3061 //DEBUG_BREAKPOINT_TEST();
3062 RT_NOREF(cbCmd);
3063 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3064#else
3065 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3066 return VERR_NOT_SUPPORTED;
3067#endif
3068}
3069
3070
3071/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3072static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3073{
3074#ifdef VMSVGA3D_DX
3075 //DEBUG_BREAKPOINT_TEST();
3076 RT_NOREF(cbCmd);
3077 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
3078#else
3079 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3080 return VERR_NOT_SUPPORTED;
3081#endif
3082}
3083
3084
3085/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3086static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3087{
3088#ifdef VMSVGA3D_DX
3089 //DEBUG_BREAKPOINT_TEST();
3090 RT_NOREF(cbCmd);
3091 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3092#else
3093 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3094 return VERR_NOT_SUPPORTED;
3095#endif
3096}
3097
3098
3099/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3100static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3101{
3102#ifdef VMSVGA3D_DX
3103 //DEBUG_BREAKPOINT_TEST();
3104 RT_NOREF(cbCmd);
3105 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3106#else
3107 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3108 return VERR_NOT_SUPPORTED;
3109#endif
3110}
3111
3112
3113/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3114static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3115{
3116#ifdef VMSVGA3D_DX
3117 //DEBUG_BREAKPOINT_TEST();
3118 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3119 RT_NOREF(idDXContext, cbCmd);
3120 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3121 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3122 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3123#else
3124 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3125 return VERR_NOT_SUPPORTED;
3126#endif
3127}
3128
3129
3130/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3131static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3132{
3133#ifdef VMSVGA3D_DX
3134 //DEBUG_BREAKPOINT_TEST();
3135 RT_NOREF(cbCmd);
3136 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3137#else
3138 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3139 return VERR_NOT_SUPPORTED;
3140#endif
3141}
3142
3143
3144/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3145static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3146{
3147#ifdef VMSVGA3D_DX
3148 //DEBUG_BREAKPOINT_TEST();
3149 RT_NOREF(cbCmd);
3150 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3151#else
3152 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3153 return VERR_NOT_SUPPORTED;
3154#endif
3155}
3156
3157
3158/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3159static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3160{
3161#ifdef VMSVGA3D_DX
3162 //DEBUG_BREAKPOINT_TEST();
3163 RT_NOREF(cbCmd);
3164 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3165#else
3166 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3167 return VERR_NOT_SUPPORTED;
3168#endif
3169}
3170
3171
3172/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3173static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3174{
3175#ifdef VMSVGA3D_DX
3176 //DEBUG_BREAKPOINT_TEST();
3177 RT_NOREF(cbCmd);
3178 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3179 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3180 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3181 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3182#else
3183 RT_NOREF(pThisCC, pCmd, cbCmd);
3184 return VERR_NOT_SUPPORTED;
3185#endif
3186}
3187
3188
3189/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3190static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3191{
3192#ifdef VMSVGA3D_DX
3193 //DEBUG_BREAKPOINT_TEST();
3194 RT_NOREF(idDXContext, cbCmd);
3195 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3196#else
3197 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3198 return VERR_NOT_SUPPORTED;
3199#endif
3200}
3201
3202
3203/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3204static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3205{
3206#ifdef VMSVGA3D_DX
3207 //DEBUG_BREAKPOINT_TEST();
3208 RT_NOREF(idDXContext, cbCmd);
3209
3210 int rc;
3211
3212 /** @todo Backend should o the copy is both buffers have a hardware resource. */
3213 SVGA3dSurfaceImageId imageBufferSrc;
3214 imageBufferSrc.sid = pCmd->src;
3215 imageBufferSrc.face = 0;
3216 imageBufferSrc.mipmap = 0;
3217
3218 SVGA3dSurfaceImageId imageBufferDest;
3219 imageBufferDest.sid = pCmd->dest;
3220 imageBufferDest.face = 0;
3221 imageBufferDest.mipmap = 0;
3222
3223 /*
3224 * Map the source buffer.
3225 */
3226 VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3227 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3228 if (RT_SUCCESS(rc))
3229 {
3230 /*
3231 * Map the destination buffer.
3232 */
3233 VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3234 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3235 if (RT_SUCCESS(rc))
3236 {
3237 /*
3238 * Copy the source buffer to the destination.
3239 */
3240 uint8_t const *pu8BufferSrc = (uint8_t *)mapBufferSrc.pvData;
3241 uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3242
3243 uint8_t *pu8BufferDest = (uint8_t *)mapBufferDest.pvData;
3244 uint32_t const cbBufferDest = mapBufferDest.cbRow;
3245
3246 if ( pCmd->srcX < cbBufferSrc
3247 && pCmd->width <= cbBufferSrc- pCmd->srcX
3248 && pCmd->destX < cbBufferDest
3249 && pCmd->width <= cbBufferDest - pCmd->destX)
3250 {
3251 RT_UNTRUSTED_VALIDATED_FENCE();
3252
3253 memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3254 }
3255 else
3256 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3257
3258 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3259 }
3260
3261 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3262 }
3263
3264 return rc;
3265#else
3266 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3267 return VERR_NOT_SUPPORTED;
3268#endif
3269}
3270
3271
3272/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3273static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3274{
3275#ifdef VMSVGA3D_DX
3276 //DEBUG_BREAKPOINT_TEST();
3277 RT_NOREF(cbCmd);
3278
3279 /* Plan:
3280 * - map the buffer;
3281 * - map the surface;
3282 * - copy from buffer map to the surface map.
3283 */
3284
3285 int rc;
3286
3287 SVGA3dSurfaceImageId imageBuffer;
3288 imageBuffer.sid = pCmd->srcSid;
3289 imageBuffer.face = 0;
3290 imageBuffer.mipmap = 0;
3291
3292 SVGA3dSurfaceImageId imageSurface;
3293 imageSurface.sid = pCmd->destSid;
3294 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3295 AssertRCReturn(rc, rc);
3296
3297 /*
3298 * Map the buffer.
3299 */
3300 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3301 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3302 if (RT_SUCCESS(rc))
3303 {
3304 /*
3305 * Map the surface.
3306 */
3307 VMSVGA3D_MAPPED_SURFACE mapSurface;
3308 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3309 if (RT_SUCCESS(rc))
3310 {
3311 /*
3312 * Copy the mapped buffer to the surface. "Raw byte wise transfer"
3313 */
3314 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3315 uint32_t const cbBuffer = mapBuffer.cbRow;
3316
3317 if (pCmd->srcOffset <= cbBuffer)
3318 {
3319 RT_UNTRUSTED_VALIDATED_FENCE();
3320 uint8_t const *pu8BufferBegin = pu8Buffer;
3321 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3322
3323 pu8Buffer += pCmd->srcOffset;
3324
3325 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3326
3327 uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3328 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3329 {
3330 uint8_t const *pu8BufferRow = pu8Buffer;
3331 uint8_t *pu8SurfaceRow = pu8Surface;
3332 for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3333 {
3334 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3335 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3336 && (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3337 && (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3338 && (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3339 rc = VERR_INVALID_PARAMETER);
3340
3341 memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3342
3343 pu8SurfaceRow += mapSurface.cbRowPitch;
3344 pu8BufferRow += pCmd->srcPitch;
3345 }
3346
3347 pu8Buffer += pCmd->srcSlicePitch;
3348 pu8Surface += mapSurface.cbDepthPitch;
3349 }
3350 }
3351 else
3352 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3353
3354 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3355 }
3356
3357 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3358 }
3359
3360 return rc;
3361#else
3362 RT_NOREF(pThisCC, pCmd, cbCmd);
3363 return VERR_NOT_SUPPORTED;
3364#endif
3365}
3366
3367
3368/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3369static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3370{
3371#ifdef VMSVGA3D_DX
3372 DEBUG_BREAKPOINT_TEST();
3373 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3374 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3375 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3376#else
3377 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3378 return VERR_NOT_SUPPORTED;
3379#endif
3380}
3381
3382
3383/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3384static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3385{
3386#ifdef VMSVGA3D_DX
3387 DEBUG_BREAKPOINT_TEST();
3388 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3389 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3390 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3391#else
3392 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3393 return VERR_NOT_SUPPORTED;
3394#endif
3395}
3396
3397
3398/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3399static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3400{
3401#ifdef VMSVGA3D_DX
3402 //DEBUG_BREAKPOINT_TEST();
3403 RT_NOREF(cbCmd);
3404 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3405#else
3406 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3407 return VERR_NOT_SUPPORTED;
3408#endif
3409}
3410
3411
3412/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3413static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3414{
3415#ifdef VMSVGA3D_DX
3416 //DEBUG_BREAKPOINT_TEST();
3417 RT_NOREF(cbCmd);
3418 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3419#else
3420 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3421 return VERR_NOT_SUPPORTED;
3422#endif
3423}
3424
3425
3426/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3427static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3428{
3429#ifdef VMSVGA3D_DX
3430 //DEBUG_BREAKPOINT_TEST();
3431 RT_NOREF(idDXContext, cbCmd);
3432
3433 /* This command is executed in a context: "The context is implied from the command buffer header."
3434 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3435 */
3436 SVGA3dCmdDXTransferFromBuffer cmd;
3437 cmd.srcSid = pCmd->srcSid;
3438 cmd.srcOffset = pCmd->srcOffset;
3439 cmd.srcPitch = pCmd->srcPitch;
3440 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3441 cmd.destSid = pCmd->destSid;
3442 cmd.destSubResource = pCmd->destSubResource;
3443 cmd.destBox = pCmd->destBox;
3444 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3445#else
3446 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3447 return VERR_NOT_SUPPORTED;
3448#endif
3449}
3450
3451
3452/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3453static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3454{
3455#ifdef VMSVGA3D_DX
3456 //DEBUG_BREAKPOINT_TEST();
3457 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3458 RT_NOREF(cbCmd);
3459
3460 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobId);
3461 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
3462
3463 int rc = vmsvgaR3MobWrite(pSvgaR3State, pMob, pCmd->mobOffset, &pCmd->value, sizeof(pCmd->value));
3464 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), rc);
3465
3466 return VINF_SUCCESS;
3467#else
3468 RT_NOREF(pThisCC, pCmd, cbCmd);
3469 return VERR_NOT_SUPPORTED;
3470#endif
3471}
3472
3473
3474/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3475static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3476{
3477#ifdef VMSVGA3D_DX
3478 DEBUG_BREAKPOINT_TEST();
3479 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3480 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3481 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3482#else
3483 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3484 return VERR_NOT_SUPPORTED;
3485#endif
3486}
3487
3488
3489/* SVGA_3D_CMD_DX_HINT 1218 */
3490static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3491{
3492#ifdef VMSVGA3D_DX
3493 DEBUG_BREAKPOINT_TEST();
3494 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3495 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3496 return vmsvga3dDXHint(pThisCC, idDXContext);
3497#else
3498 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3499 return VERR_NOT_SUPPORTED;
3500#endif
3501}
3502
3503
3504/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3505static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3506{
3507#ifdef VMSVGA3D_DX
3508 DEBUG_BREAKPOINT_TEST();
3509 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3510 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3511 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3512#else
3513 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3514 return VERR_NOT_SUPPORTED;
3515#endif
3516}
3517
3518
3519/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3520static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3521{
3522#ifdef VMSVGA3D_DX
3523 //DEBUG_BREAKPOINT_TEST();
3524 RT_NOREF(cbCmd);
3525 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_VS);
3526#else
3527 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3528 return VERR_NOT_SUPPORTED;
3529#endif
3530}
3531
3532
3533/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3534static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3535{
3536#ifdef VMSVGA3D_DX
3537 //DEBUG_BREAKPOINT_TEST();
3538 RT_NOREF(cbCmd);
3539 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_PS);
3540#else
3541 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3542 return VERR_NOT_SUPPORTED;
3543#endif
3544}
3545
3546
3547/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3548static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3549{
3550#ifdef VMSVGA3D_DX
3551 //DEBUG_BREAKPOINT_TEST();
3552 RT_NOREF(cbCmd);
3553 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_GS);
3554#else
3555 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3556 return VERR_NOT_SUPPORTED;
3557#endif
3558}
3559
3560
3561/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3562static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3563{
3564#ifdef VMSVGA3D_DX
3565 //DEBUG_BREAKPOINT_TEST();
3566 RT_NOREF(cbCmd);
3567 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_HS);
3568#else
3569 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3570 return VERR_NOT_SUPPORTED;
3571#endif
3572}
3573
3574
3575/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3576static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3577{
3578#ifdef VMSVGA3D_DX
3579 //DEBUG_BREAKPOINT_TEST();
3580 RT_NOREF(cbCmd);
3581 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_DS);
3582#else
3583 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3584 return VERR_NOT_SUPPORTED;
3585#endif
3586}
3587
3588
3589/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3590static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3591{
3592#ifdef VMSVGA3D_DX
3593 //DEBUG_BREAKPOINT_TEST();
3594 RT_NOREF(cbCmd);
3595 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_CS);
3596#else
3597 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3598 return VERR_NOT_SUPPORTED;
3599#endif
3600}
3601
3602
3603/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3604static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3605{
3606#ifdef VMSVGA3D_DX
3607 DEBUG_BREAKPOINT_TEST();
3608 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3609 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3610 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3611#else
3612 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3613 return VERR_NOT_SUPPORTED;
3614#endif
3615}
3616
3617
3618/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3619static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3620{
3621#ifdef VMSVGA3D_DX
3622 DEBUG_BREAKPOINT_TEST();
3623 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3624 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3625 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3626#else
3627 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3628 return VERR_NOT_SUPPORTED;
3629#endif
3630}
3631
3632
3633/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3634static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3635{
3636#ifdef VMSVGA3D_DX
3637 //DEBUG_BREAKPOINT_TEST();
3638 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3639 RT_NOREF(cbCmd);
3640 return vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
3641 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ true);
3642#else
3643 RT_NOREF(pThisCC, pCmd, cbCmd);
3644 return VERR_NOT_SUPPORTED;
3645#endif
3646}
3647
3648
3649/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3650static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3651{
3652#ifdef VMSVGA3D_DX
3653 //DEBUG_BREAKPOINT_TEST();
3654 RT_NOREF(cbCmd);
3655 return vmsvga3dDXGrowCOTable(pThisCC, pCmd);
3656#else
3657 RT_NOREF(pThisCC, pCmd, cbCmd);
3658 return VERR_NOT_SUPPORTED;
3659#endif
3660}
3661
3662
3663/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3664static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3665{
3666#ifdef VMSVGA3D_DX
3667 //DEBUG_BREAKPOINT_TEST();
3668 RT_NOREF(cbCmd);
3669 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext, pCmd);
3670#else
3671 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3672 return VERR_NOT_SUPPORTED;
3673#endif
3674}
3675
3676
3677/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3678static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
3679{
3680#ifdef VMSVGA3D_DX
3681 //DEBUG_BREAKPOINT_TEST();
3682 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3683
3684 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
3685 SVGAOTableSurfaceEntry entry;
3686 RT_ZERO(entry);
3687 entry.format = pCmd->format;
3688 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
3689 entry.numMipLevels = pCmd->numMipLevels;
3690 entry.multisampleCount = pCmd->multisampleCount;
3691 entry.autogenFilter = pCmd->autogenFilter;
3692 entry.size = pCmd->size;
3693 entry.mobid = SVGA_ID_INVALID;
3694 entry.arraySize = pCmd->arraySize;
3695 // entry.mobPitch = 0;
3696 // entry.mobPitch = 0;
3697 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
3698 // entry.multisamplePattern = 0;
3699 // entry.qualityLevel = 0;
3700 // entry.bufferByteStride = 0;
3701 // entry.minLOD = 0;
3702
3703 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
3704 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
3705 if (RT_SUCCESS(rc))
3706 {
3707 /* Create the host surface. */
3708 /** @todo SVGAOTableSurfaceEntry as input parameter? */
3709 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
3710 pCmd->multisampleCount, pCmd->autogenFilter,
3711 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
3712 }
3713 return rc;
3714#else
3715 RT_NOREF(pThisCC, pCmd);
3716 return VERR_NOT_SUPPORTED;
3717#endif
3718}
3719
3720
3721/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3722static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3723{
3724#ifdef VMSVGA3D_DX
3725 DEBUG_BREAKPOINT_TEST();
3726 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3727 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3728 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3729#else
3730 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3731 return VERR_NOT_SUPPORTED;
3732#endif
3733}
3734
3735
3736/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3737static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3738{
3739#ifdef VMSVGA3D_DX
3740 DEBUG_BREAKPOINT_TEST();
3741 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3742 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3743 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3744#else
3745 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3746 return VERR_NOT_SUPPORTED;
3747#endif
3748}
3749
3750
3751/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3752static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3753{
3754#ifdef VMSVGA3D_DX
3755 DEBUG_BREAKPOINT_TEST();
3756 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3757 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3758 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3759#else
3760 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3761 return VERR_NOT_SUPPORTED;
3762#endif
3763}
3764
3765
3766/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3767static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3768{
3769#ifdef VMSVGA3D_DX
3770 DEBUG_BREAKPOINT_TEST();
3771 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3772 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3773 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3774#else
3775 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3776 return VERR_NOT_SUPPORTED;
3777#endif
3778}
3779
3780
3781/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3782static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3783{
3784#ifdef VMSVGA3D_DX
3785 DEBUG_BREAKPOINT_TEST();
3786 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3787 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3788 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3789#else
3790 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3791 return VERR_NOT_SUPPORTED;
3792#endif
3793}
3794
3795
3796/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3797static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3798{
3799#ifdef VMSVGA3D_DX
3800 //DEBUG_BREAKPOINT_TEST();
3801 RT_NOREF(cbCmd);
3802 return vmsvga3dDXDefineUAView(pThisCC, idDXContext, pCmd);
3803#else
3804 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3805 return VERR_NOT_SUPPORTED;
3806#endif
3807}
3808
3809
3810/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3811static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3812{
3813#ifdef VMSVGA3D_DX
3814 //DEBUG_BREAKPOINT_TEST();
3815 RT_NOREF(cbCmd);
3816 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext, pCmd);
3817#else
3818 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3819 return VERR_NOT_SUPPORTED;
3820#endif
3821}
3822
3823
3824/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3825static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3826{
3827#ifdef VMSVGA3D_DX
3828 DEBUG_BREAKPOINT_TEST();
3829 RT_NOREF(cbCmd);
3830 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext, pCmd);
3831#else
3832 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3833 return VERR_NOT_SUPPORTED;
3834#endif
3835}
3836
3837
3838/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3839static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3840{
3841#ifdef VMSVGA3D_DX
3842 DEBUG_BREAKPOINT_TEST();
3843 RT_NOREF(cbCmd);
3844 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext, pCmd);
3845#else
3846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3847 return VERR_NOT_SUPPORTED;
3848#endif
3849}
3850
3851
3852/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3853static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3854{
3855#ifdef VMSVGA3D_DX
3856 //DEBUG_BREAKPOINT_TEST();
3857 RT_NOREF(cbCmd);
3858 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext, pCmd);
3859#else
3860 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3861 return VERR_NOT_SUPPORTED;
3862#endif
3863}
3864
3865
3866/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3867static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3868{
3869#ifdef VMSVGA3D_DX
3870 //DEBUG_BREAKPOINT_TEST();
3871 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
3872 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
3873 return vmsvga3dDXSetUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
3874#else
3875 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3876 return VERR_NOT_SUPPORTED;
3877#endif
3878}
3879
3880
3881/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3882static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3883{
3884#ifdef VMSVGA3D_DX
3885 //DEBUG_BREAKPOINT_TEST();
3886 RT_NOREF(cbCmd);
3887 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd);
3888#else
3889 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3890 return VERR_NOT_SUPPORTED;
3891#endif
3892}
3893
3894
3895/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3896static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3897{
3898#ifdef VMSVGA3D_DX
3899 //DEBUG_BREAKPOINT_TEST();
3900 RT_NOREF(cbCmd);
3901 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd);
3902#else
3903 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3904 return VERR_NOT_SUPPORTED;
3905#endif
3906}
3907
3908
3909/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3910static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3911{
3912#ifdef VMSVGA3D_DX
3913 //DEBUG_BREAKPOINT_TEST();
3914 RT_NOREF(cbCmd);
3915 return vmsvga3dDXDispatch(pThisCC, idDXContext, pCmd);
3916#else
3917 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3918 return VERR_NOT_SUPPORTED;
3919#endif
3920}
3921
3922
3923/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3924static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3925{
3926#ifdef VMSVGA3D_DX
3927 DEBUG_BREAKPOINT_TEST();
3928 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3929 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3930 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3931#else
3932 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3933 return VERR_NOT_SUPPORTED;
3934#endif
3935}
3936
3937
3938/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3939static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3940{
3941#ifdef VMSVGA3D_DX
3942 DEBUG_BREAKPOINT_TEST();
3943 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3944 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3945 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3946#else
3947 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3948 return VERR_NOT_SUPPORTED;
3949#endif
3950}
3951
3952
3953/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3954static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3955{
3956#ifdef VMSVGA3D_DX
3957 DEBUG_BREAKPOINT_TEST();
3958 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3959 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3960 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3961#else
3962 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3963 return VERR_NOT_SUPPORTED;
3964#endif
3965}
3966
3967
3968/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3969static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3970{
3971#ifdef VMSVGA3D_DX
3972 DEBUG_BREAKPOINT_TEST();
3973 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3974 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3975 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3976#else
3977 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3978 return VERR_NOT_SUPPORTED;
3979#endif
3980}
3981
3982
3983/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3984static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3985{
3986#ifdef VMSVGA3D_DX
3987 //DEBUG_BREAKPOINT_TEST();
3988 RT_NOREF(cbCmd);
3989 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext, pCmd);
3990#else
3991 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3992 return VERR_NOT_SUPPORTED;
3993#endif
3994}
3995
3996
3997/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3998static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3999{
4000#ifdef VMSVGA3D_DX
4001 DEBUG_BREAKPOINT_TEST();
4002 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4003 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4004 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
4005#else
4006 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4007 return VERR_NOT_SUPPORTED;
4008#endif
4009}
4010
4011
4012/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
4013static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
4014{
4015#ifdef VMSVGA3D_DX
4016 DEBUG_BREAKPOINT_TEST();
4017 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4018 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4019 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
4020#else
4021 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4022 return VERR_NOT_SUPPORTED;
4023#endif
4024}
4025
4026
4027/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
4028static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
4029{
4030#ifdef VMSVGA3D_DX
4031 DEBUG_BREAKPOINT_TEST();
4032 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4033 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4034 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
4035#else
4036 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4037 return VERR_NOT_SUPPORTED;
4038#endif
4039}
4040
4041
4042/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
4043static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
4044{
4045#ifdef VMSVGA3D_DX
4046 DEBUG_BREAKPOINT_TEST();
4047 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4048 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4049 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
4050#else
4051 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4052 return VERR_NOT_SUPPORTED;
4053#endif
4054}
4055
4056
4057/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
4058static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
4059{
4060#ifdef VMSVGA3D_DX
4061 DEBUG_BREAKPOINT_TEST();
4062 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4063 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4064 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
4065#else
4066 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4067 return VERR_NOT_SUPPORTED;
4068#endif
4069}
4070
4071
4072/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
4073static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
4074{
4075#ifdef VMSVGA3D_DX
4076 DEBUG_BREAKPOINT_TEST();
4077 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4078 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4079 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4080#else
4081 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4082 return VERR_NOT_SUPPORTED;
4083#endif
4084}
4085
4086
4087/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4088static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
4089{
4090#ifdef VMSVGA3D_DX
4091 //DEBUG_BREAKPOINT_TEST();
4092 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4093
4094 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
4095 SVGAOTableSurfaceEntry entry;
4096 RT_ZERO(entry);
4097 entry.format = pCmd->format;
4098 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
4099 entry.numMipLevels = pCmd->numMipLevels;
4100 entry.multisampleCount = pCmd->multisampleCount;
4101 entry.autogenFilter = pCmd->autogenFilter;
4102 entry.size = pCmd->size;
4103 entry.mobid = SVGA_ID_INVALID;
4104 entry.arraySize = pCmd->arraySize;
4105 // entry.mobPitch = 0;
4106 // entry.mobPitch = 0;
4107 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
4108 // entry.multisamplePattern = 0;
4109 // entry.qualityLevel = 0;
4110 entry.bufferByteStride = pCmd->bufferByteStride;
4111 // entry.minLOD = 0;
4112
4113 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
4114 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
4115 if (RT_SUCCESS(rc))
4116 {
4117 /* Create the host surface. */
4118 /** @todo SVGAOTableSurfaceEntry as input parameter? */
4119 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
4120 pCmd->multisampleCount, pCmd->autogenFilter,
4121 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
4122 }
4123 return rc;
4124#else
4125 RT_NOREF(pThisCC, pCmd);
4126 return VERR_NOT_SUPPORTED;
4127#endif
4128}
4129
4130
4131/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4132static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4133{
4134#ifdef VMSVGA3D_DX
4135 //DEBUG_BREAKPOINT_TEST();
4136 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
4137 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
4138 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
4139#else
4140 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4141 return VERR_NOT_SUPPORTED;
4142#endif
4143}
4144
4145
4146/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4147static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4148{
4149#ifdef VMSVGA3D_DX
4150 DEBUG_BREAKPOINT_TEST();
4151 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4152 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4153 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4154#else
4155 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4156 return VERR_NOT_SUPPORTED;
4157#endif
4158}
4159
4160
4161/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4162static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4163{
4164#ifdef VMSVGA3D_DX
4165 //DEBUG_BREAKPOINT_TEST();
4166 RT_NOREF(cbCmd);
4167 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4168#else
4169 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4170 return VERR_NOT_SUPPORTED;
4171#endif
4172}
4173
4174
4175/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4176static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4177{
4178#ifdef VMSVGA3D_DX
4179 //DEBUG_BREAKPOINT_TEST();
4180 RT_NOREF(cbCmd);
4181 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd);
4182#else
4183 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4184 return VERR_NOT_SUPPORTED;
4185#endif
4186}
4187
4188
4189/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4190static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4191{
4192#ifdef VMSVGA3D_DX
4193 DEBUG_BREAKPOINT_TEST();
4194 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4195 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4196 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4197#else
4198 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4199 return VERR_NOT_SUPPORTED;
4200#endif
4201}
4202
4203
4204/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4205static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4206{
4207#ifdef VMSVGA3D_DX
4208 //DEBUG_BREAKPOINT_TEST();
4209 RT_NOREF(cbCmd);
4210 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext, pCmd);
4211#else
4212 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4213 return VERR_NOT_SUPPORTED;
4214#endif
4215}
4216
4217
4218/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4219static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4220{
4221#ifdef VMSVGA3D_DX
4222 DEBUG_BREAKPOINT_TEST();
4223 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4224 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4225 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4226#else
4227 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4228 return VERR_NOT_SUPPORTED;
4229#endif
4230}
4231
4232
4233/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4234static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4235{
4236#ifdef VMSVGA3D_DX
4237 DEBUG_BREAKPOINT_TEST();
4238 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4239 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4240 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4241#else
4242 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4243 return VERR_NOT_SUPPORTED;
4244#endif
4245}
4246
4247
4248/* SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION 1083 */
4249static int vmsvga3dCmdVBDXClearRenderTargetViewRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd, uint32_t cbCmd)
4250{
4251#ifdef VMSVGA3D_DX
4252 //DEBUG_BREAKPOINT_TEST();
4253 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4254 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4255 return vmsvga3dVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cRect, paRect);
4256#else
4257 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4258 return VERR_NOT_SUPPORTED;
4259#endif
4260}
4261
4262
4263/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4264 * Check that the 3D command has at least a_cbMin of payload bytes after the
4265 * header. Will break out of the switch if it doesn't.
4266 */
4267# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4268 if (1) { \
4269 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4270 RT_UNTRUSTED_VALIDATED_FENCE(); \
4271 } else do {} while (0)
4272
4273# define VMSVGA_3D_CMD_NOTIMPL() \
4274 if (1) { \
4275 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4276 } else do {} while (0)
4277
4278/** SVGA_3D_CMD_* handler.
4279 * This function parses the command and calls the corresponding command handler.
4280 *
4281 * @param pThis The shared VGA/VMSVGA state.
4282 * @param pThisCC The VGA/VMSVGA state for the current context.
4283 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4284 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4285 * @param cbCmd Size of the command in bytes.
4286 * @param pvCmd Pointer to the command.
4287 * @returns VBox status code if an error was detected parsing a command.
4288 */
4289int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4290{
4291 if (enmCmdId > SVGA_3D_CMD_MAX)
4292 {
4293 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4294 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4295 }
4296
4297 int rcParse = VINF_SUCCESS;
4298 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4299
4300 switch (enmCmdId)
4301 {
4302 case SVGA_3D_CMD_SURFACE_DEFINE:
4303 {
4304 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4305 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4306 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4307
4308 SVGA3dCmdDefineSurface_v2 cmd;
4309 cmd.sid = pCmd->sid;
4310 cmd.surfaceFlags = pCmd->surfaceFlags;
4311 cmd.format = pCmd->format;
4312 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4313 cmd.multisampleCount = 0;
4314 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4315
4316 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4317 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4318# ifdef DEBUG_GMR_ACCESS
4319 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4320# endif
4321 break;
4322 }
4323
4324 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4325 {
4326 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4327 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4328 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4329
4330 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4331 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4332# ifdef DEBUG_GMR_ACCESS
4333 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4334# endif
4335 break;
4336 }
4337
4338 case SVGA_3D_CMD_SURFACE_DESTROY:
4339 {
4340 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4341 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4342 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4343
4344 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4345 break;
4346 }
4347
4348 case SVGA_3D_CMD_SURFACE_COPY:
4349 {
4350 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4351 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4352 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4353
4354 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4355 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4356 break;
4357 }
4358
4359 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4360 {
4361 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4363 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4364
4365 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4366 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4367 break;
4368 }
4369
4370 case SVGA_3D_CMD_SURFACE_DMA:
4371 {
4372 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4373 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4374 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4375
4376 uint64_t u64NanoTS = 0;
4377 if (LogRelIs3Enabled())
4378 u64NanoTS = RTTimeNanoTS();
4379 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4380 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4381 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4382 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4383 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4384 if (LogRelIs3Enabled())
4385 {
4386 if (cCopyBoxes)
4387 {
4388 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4389 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4390 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4391 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4392 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4393 }
4394 }
4395 break;
4396 }
4397
4398 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4399 {
4400 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4403
4404 static uint64_t u64FrameStartNanoTS = 0;
4405 static uint64_t u64ElapsedPerSecNano = 0;
4406 static int cFrames = 0;
4407 uint64_t u64NanoTS = 0;
4408 if (LogRelIs3Enabled())
4409 u64NanoTS = RTTimeNanoTS();
4410 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4411 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4412 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4413 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4414 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4415 if (LogRelIs3Enabled())
4416 {
4417 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4418 u64ElapsedPerSecNano += u64ElapsedNano;
4419
4420 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4421 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4422 (u64ElapsedNano) / 1000ULL, cRects,
4423 pFirstRect->left, pFirstRect->top,
4424 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4425
4426 ++cFrames;
4427 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4428 {
4429 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4430 cFrames, u64ElapsedPerSecNano / 1000ULL));
4431 u64FrameStartNanoTS = u64NanoTS;
4432 cFrames = 0;
4433 u64ElapsedPerSecNano = 0;
4434 }
4435 }
4436 break;
4437 }
4438
4439 case SVGA_3D_CMD_CONTEXT_DEFINE:
4440 {
4441 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4443 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4444
4445 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4446 break;
4447 }
4448
4449 case SVGA_3D_CMD_CONTEXT_DESTROY:
4450 {
4451 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4452 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4453 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4454
4455 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4456 break;
4457 }
4458
4459 case SVGA_3D_CMD_SETTRANSFORM:
4460 {
4461 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4463 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4464
4465 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4466 break;
4467 }
4468
4469 case SVGA_3D_CMD_SETZRANGE:
4470 {
4471 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4472 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4473 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4474
4475 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4476 break;
4477 }
4478
4479 case SVGA_3D_CMD_SETRENDERSTATE:
4480 {
4481 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4482 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4483 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4484
4485 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4486 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4487 break;
4488 }
4489
4490 case SVGA_3D_CMD_SETRENDERTARGET:
4491 {
4492 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4493 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4494 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4495
4496 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4497 break;
4498 }
4499
4500 case SVGA_3D_CMD_SETTEXTURESTATE:
4501 {
4502 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4505
4506 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4507 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4508 break;
4509 }
4510
4511 case SVGA_3D_CMD_SETMATERIAL:
4512 {
4513 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4514 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4515 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4516
4517 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4518 break;
4519 }
4520
4521 case SVGA_3D_CMD_SETLIGHTDATA:
4522 {
4523 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4524 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4525 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4526
4527 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4528 break;
4529 }
4530
4531 case SVGA_3D_CMD_SETLIGHTENABLED:
4532 {
4533 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4535 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4536
4537 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4538 break;
4539 }
4540
4541 case SVGA_3D_CMD_SETVIEWPORT:
4542 {
4543 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4544 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4545 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4546
4547 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4548 break;
4549 }
4550
4551 case SVGA_3D_CMD_SETCLIPPLANE:
4552 {
4553 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4555 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4556
4557 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4558 break;
4559 }
4560
4561 case SVGA_3D_CMD_CLEAR:
4562 {
4563 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4564 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4565 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4566
4567 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4568 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4569 break;
4570 }
4571
4572 case SVGA_3D_CMD_PRESENT:
4573 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4574 {
4575 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4576 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4578 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4579 else
4580 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4581
4582 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4583 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4584 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4585 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4586 break;
4587 }
4588
4589 case SVGA_3D_CMD_SHADER_DEFINE:
4590 {
4591 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4592 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4593 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4594
4595 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4596 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4597 break;
4598 }
4599
4600 case SVGA_3D_CMD_SHADER_DESTROY:
4601 {
4602 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4603 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4604 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4605
4606 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4607 break;
4608 }
4609
4610 case SVGA_3D_CMD_SET_SHADER:
4611 {
4612 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4615
4616 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4617 break;
4618 }
4619
4620 case SVGA_3D_CMD_SET_SHADER_CONST:
4621 {
4622 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4625
4626 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4627 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4628 break;
4629 }
4630
4631 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4632 {
4633 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4634 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4635 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4636
4637 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4638 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4639 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4640 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4641 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4642
4643 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4644 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4645 RT_UNTRUSTED_VALIDATED_FENCE();
4646
4647 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4648 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4649 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4650
4651 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4652 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4653 pNumRange, cVertexDivisor, pVertexDivisor);
4654 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4655 break;
4656 }
4657
4658 case SVGA_3D_CMD_SETSCISSORRECT:
4659 {
4660 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4662 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4663
4664 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4665 break;
4666 }
4667
4668 case SVGA_3D_CMD_BEGIN_QUERY:
4669 {
4670 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4671 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4672 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4673
4674 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4675 break;
4676 }
4677
4678 case SVGA_3D_CMD_END_QUERY:
4679 {
4680 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4681 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4682 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4683
4684 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4685 break;
4686 }
4687
4688 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4689 {
4690 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4691 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4692 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4693
4694 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4695 break;
4696 }
4697
4698 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4699 {
4700 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4702 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4703
4704 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4705 break;
4706 }
4707
4708 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4709 /* context id + surface id? */
4710 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4711 break;
4712
4713 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4714 /* context id + surface id? */
4715 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4716 break;
4717
4718 /*
4719 *
4720 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4721 *
4722 */
4723 case SVGA_3D_CMD_SCREEN_DMA:
4724 {
4725 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4726 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4727 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4728 break;
4729 }
4730
4731 /* case SVGA_3D_CMD_DEAD1: New SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION */
4732 case SVGA_3D_CMD_DEAD2:
4733 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4734 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4735 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4736 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4737 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4738 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4739 {
4740 VMSVGA_3D_CMD_NOTIMPL();
4741 break;
4742 }
4743
4744 case SVGA_3D_CMD_SET_OTABLE_BASE:
4745 {
4746 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4747 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4748 vmsvga3dCmdSetOTableBase(pThisCC, pCmd);
4749 break;
4750 }
4751
4752 case SVGA_3D_CMD_READBACK_OTABLE:
4753 {
4754 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4755 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4756 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4757 break;
4758 }
4759
4760 case SVGA_3D_CMD_DEFINE_GB_MOB:
4761 {
4762 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4763 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4764 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4765 break;
4766 }
4767
4768 case SVGA_3D_CMD_DESTROY_GB_MOB:
4769 {
4770 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4771 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4772 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4773 break;
4774 }
4775
4776 case SVGA_3D_CMD_DEAD3:
4777 {
4778 VMSVGA_3D_CMD_NOTIMPL();
4779 break;
4780 }
4781
4782 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4783 {
4784 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4785 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4786 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4787 break;
4788 }
4789
4790 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4791 {
4792 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4793 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4794 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4795 break;
4796 }
4797
4798 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4799 {
4800 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4802 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4803 break;
4804 }
4805
4806 case SVGA_3D_CMD_BIND_GB_SURFACE:
4807 {
4808 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4809 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4810 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4811 break;
4812 }
4813
4814 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4815 {
4816 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4817 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4818 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4819 break;
4820 }
4821
4822 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4823 {
4824 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4825 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4826 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4827 break;
4828 }
4829
4830 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4831 {
4832 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4834 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4835 break;
4836 }
4837
4838 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4839 {
4840 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4841 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4842 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4843 break;
4844 }
4845
4846 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4847 {
4848 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4850 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4851 break;
4852 }
4853
4854 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4855 {
4856 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4858 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4859 break;
4860 }
4861
4862 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4863 {
4864 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4865 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4866 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4867 break;
4868 }
4869
4870 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4871 {
4872 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4873 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4874 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4875 break;
4876 }
4877
4878 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4879 {
4880 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4881 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4882 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4883 break;
4884 }
4885
4886 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4887 {
4888 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4889 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4890 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4891 break;
4892 }
4893
4894 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4895 {
4896 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4897 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4898 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4899 break;
4900 }
4901
4902 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4903 {
4904 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4905 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4906 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4907 break;
4908 }
4909
4910 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4911 {
4912 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4914 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4915 break;
4916 }
4917
4918 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4919 {
4920 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4921 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4922 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4923 break;
4924 }
4925
4926 case SVGA_3D_CMD_BIND_GB_SHADER:
4927 {
4928 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4930 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4931 break;
4932 }
4933
4934 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4935 {
4936 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4937 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4938 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4939 break;
4940 }
4941
4942 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4943 {
4944 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4946 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4947 break;
4948 }
4949
4950 case SVGA_3D_CMD_END_GB_QUERY:
4951 {
4952 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4954 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4955 break;
4956 }
4957
4958 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4959 {
4960 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4962 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4963 break;
4964 }
4965
4966 case SVGA_3D_CMD_NOP:
4967 {
4968 /* Apparently there is nothing to do. */
4969 break;
4970 }
4971
4972 case SVGA_3D_CMD_ENABLE_GART:
4973 {
4974 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4975 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4976 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4977 break;
4978 }
4979
4980 case SVGA_3D_CMD_DISABLE_GART:
4981 {
4982 /* No corresponding SVGA3dCmd structure. */
4983 VMSVGA_3D_CMD_NOTIMPL();
4984 break;
4985 }
4986
4987 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4988 {
4989 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4991 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4992 break;
4993 }
4994
4995 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4996 {
4997 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4999 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
5004 {
5005 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
5012 {
5013 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
5020 {
5021 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
5028 {
5029 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
5036 {
5037 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
5044 {
5045 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
5052 {
5053 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_GB_SCREEN_DMA:
5060 {
5061 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5064 break;
5065 }
5066
5067 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
5068 {
5069 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
5070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5071 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5072 break;
5073 }
5074
5075 case SVGA_3D_CMD_GB_MOB_FENCE:
5076 {
5077 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
5078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
5084 {
5085 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
5086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5087 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
5088 break;
5089 }
5090
5091 case SVGA_3D_CMD_DEFINE_GB_MOB64:
5092 {
5093 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
5094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5095 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
5096 break;
5097 }
5098
5099 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
5100 {
5101 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5104 break;
5105 }
5106
5107 case SVGA_3D_CMD_NOP_ERROR:
5108 {
5109 /* Apparently there is nothing to do. */
5110 break;
5111 }
5112
5113 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5114 {
5115 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
5116 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5117 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5118 break;
5119 }
5120
5121 case SVGA_3D_CMD_SET_VERTEX_DECLS:
5122 {
5123 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
5124 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5125 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5126 break;
5127 }
5128
5129 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5130 {
5131 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
5132 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5133 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5134 break;
5135 }
5136
5137 case SVGA_3D_CMD_DRAW:
5138 {
5139 /* No corresponding SVGA3dCmd structure. */
5140 VMSVGA_3D_CMD_NOTIMPL();
5141 break;
5142 }
5143
5144 case SVGA_3D_CMD_DRAW_INDEXED:
5145 {
5146 /* No corresponding SVGA3dCmd structure. */
5147 VMSVGA_3D_CMD_NOTIMPL();
5148 break;
5149 }
5150
5151 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5152 {
5153 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5154 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5155 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5156 break;
5157 }
5158
5159 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5160 {
5161 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5163 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5164 break;
5165 }
5166
5167 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5168 {
5169 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5171 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5172 break;
5173 }
5174
5175 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5176 {
5177 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5178 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5179 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5180 break;
5181 }
5182
5183 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5184 {
5185 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5186 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5187 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5188 break;
5189 }
5190
5191 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5192 {
5193 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5195 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5196 break;
5197 }
5198
5199 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5200 {
5201 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5203 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5204 break;
5205 }
5206
5207 case SVGA_3D_CMD_DX_SET_SHADER:
5208 {
5209 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5210 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5211 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5212 break;
5213 }
5214
5215 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5216 {
5217 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5219 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5220 break;
5221 }
5222
5223 case SVGA_3D_CMD_DX_DRAW:
5224 {
5225 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5226 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5227 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5228 break;
5229 }
5230
5231 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5232 {
5233 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5234 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5235 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5236 break;
5237 }
5238
5239 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5240 {
5241 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5242 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5243 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5244 break;
5245 }
5246
5247 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5248 {
5249 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5250 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5251 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5252 break;
5253 }
5254
5255 case SVGA_3D_CMD_DX_DRAW_AUTO:
5256 {
5257 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5258 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5259 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5260 break;
5261 }
5262
5263 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5264 {
5265 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5267 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5268 break;
5269 }
5270
5271 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5272 {
5273 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5275 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5276 break;
5277 }
5278
5279 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5280 {
5281 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5282 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5283 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5284 break;
5285 }
5286
5287 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5288 {
5289 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5291 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5292 break;
5293 }
5294
5295 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5296 {
5297 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5299 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5300 break;
5301 }
5302
5303 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5304 {
5305 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5306 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5307 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5308 break;
5309 }
5310
5311 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5312 {
5313 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5315 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5316 break;
5317 }
5318
5319 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5320 {
5321 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5323 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5324 break;
5325 }
5326
5327 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5328 {
5329 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5331 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5332 break;
5333 }
5334
5335 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5336 {
5337 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5339 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5340 break;
5341 }
5342
5343 case SVGA_3D_CMD_DX_BIND_QUERY:
5344 {
5345 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5346 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5347 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5348 break;
5349 }
5350
5351 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5352 {
5353 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5355 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5356 break;
5357 }
5358
5359 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5360 {
5361 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5363 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5364 break;
5365 }
5366
5367 case SVGA_3D_CMD_DX_END_QUERY:
5368 {
5369 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5371 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5372 break;
5373 }
5374
5375 case SVGA_3D_CMD_DX_READBACK_QUERY:
5376 {
5377 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5379 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5380 break;
5381 }
5382
5383 case SVGA_3D_CMD_DX_SET_PREDICATION:
5384 {
5385 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5387 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5388 break;
5389 }
5390
5391 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5392 {
5393 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5395 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5396 break;
5397 }
5398
5399 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5400 {
5401 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5403 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5404 break;
5405 }
5406
5407 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5408 {
5409 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5410 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5411 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5412 break;
5413 }
5414
5415 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5416 {
5417 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5419 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5420 break;
5421 }
5422
5423 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5424 {
5425 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5426 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5427 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5428 break;
5429 }
5430
5431 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5432 {
5433 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5435 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5436 break;
5437 }
5438
5439 case SVGA_3D_CMD_DX_PRED_COPY:
5440 {
5441 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5443 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5444 break;
5445 }
5446
5447 case SVGA_3D_CMD_DX_PRESENTBLT:
5448 {
5449 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5450 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5451 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5452 break;
5453 }
5454
5455 case SVGA_3D_CMD_DX_GENMIPS:
5456 {
5457 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5459 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5460 break;
5461 }
5462
5463 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5464 {
5465 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5466 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5467 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5468 break;
5469 }
5470
5471 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5472 {
5473 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5474 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5475 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5476 break;
5477 }
5478
5479 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5480 {
5481 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5482 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5483 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5484 break;
5485 }
5486
5487 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5488 {
5489 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5490 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5491 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5492 break;
5493 }
5494
5495 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5496 {
5497 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5499 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5500 break;
5501 }
5502
5503 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5504 {
5505 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5506 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5507 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5508 break;
5509 }
5510
5511 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5512 {
5513 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5514 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5515 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5516 break;
5517 }
5518
5519 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5520 {
5521 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5522 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5523 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5524 break;
5525 }
5526
5527 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5528 {
5529 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5530 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5531 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5532 break;
5533 }
5534
5535 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5536 {
5537 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5538 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5539 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5540 break;
5541 }
5542
5543 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5544 {
5545 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5546 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5547 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5548 break;
5549 }
5550
5551 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5552 {
5553 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5555 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5556 break;
5557 }
5558
5559 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5560 {
5561 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5563 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5564 break;
5565 }
5566
5567 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5568 {
5569 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5570 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5571 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5572 break;
5573 }
5574
5575 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5576 {
5577 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5578 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5579 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5580 break;
5581 }
5582
5583 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5584 {
5585 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5586 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5587 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5588 break;
5589 }
5590
5591 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5592 {
5593 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5594 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5595 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5596 break;
5597 }
5598
5599 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5600 {
5601 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5602 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5603 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5604 break;
5605 }
5606
5607 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5608 {
5609 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5610 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5611 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5612 break;
5613 }
5614
5615 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5616 {
5617 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5618 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5619 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5620 break;
5621 }
5622
5623 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5624 {
5625 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5626 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5627 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5628 break;
5629 }
5630
5631 case SVGA_3D_CMD_DX_BIND_SHADER:
5632 {
5633 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5634 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5635 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5636 break;
5637 }
5638
5639 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5640 {
5641 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5642 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5643 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5644 break;
5645 }
5646
5647 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5648 {
5649 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5651 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5652 break;
5653 }
5654
5655 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5656 {
5657 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5658 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5659 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5660 break;
5661 }
5662
5663 case SVGA_3D_CMD_DX_SET_COTABLE:
5664 {
5665 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5666 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5667 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5668 break;
5669 }
5670
5671 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5672 {
5673 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5674 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5675 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5676 break;
5677 }
5678
5679 case SVGA_3D_CMD_DX_BUFFER_COPY:
5680 {
5681 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5682 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5683 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5684 break;
5685 }
5686
5687 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5688 {
5689 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5690 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5691 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5692 break;
5693 }
5694
5695 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5696 {
5697 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5698 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5699 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5700 break;
5701 }
5702
5703 case SVGA_3D_CMD_DX_MOVE_QUERY:
5704 {
5705 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5706 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5707 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5708 break;
5709 }
5710
5711 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5712 {
5713 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5714 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5715 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5716 break;
5717 }
5718
5719 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5720 {
5721 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5722 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5723 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5724 break;
5725 }
5726
5727 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5728 {
5729 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5730 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5731 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5732 break;
5733 }
5734
5735 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5736 {
5737 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5738 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5739 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, pCmd, cbCmd);
5740 break;
5741 }
5742
5743 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5744 {
5745 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5747 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5748 break;
5749 }
5750
5751 case SVGA_3D_CMD_DX_HINT:
5752 {
5753 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5754 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5755 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5756 break;
5757 }
5758
5759 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5760 {
5761 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5763 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5764 break;
5765 }
5766
5767 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5768 {
5769 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5770 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5771 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5772 break;
5773 }
5774
5775 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5776 {
5777 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5778 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5779 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5780 break;
5781 }
5782
5783 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5784 {
5785 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5786 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5787 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5788 break;
5789 }
5790
5791 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5792 {
5793 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5794 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5795 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5796 break;
5797 }
5798
5799 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5800 {
5801 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5802 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5803 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5804 break;
5805 }
5806
5807 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5808 {
5809 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5810 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5811 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5812 break;
5813 }
5814
5815 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5816 {
5817 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5819 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5820 break;
5821 }
5822
5823 case SVGA_3D_CMD_SCREEN_COPY:
5824 {
5825 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5827 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5828 break;
5829 }
5830
5831 case SVGA_3D_CMD_RESERVED1:
5832 {
5833 VMSVGA_3D_CMD_NOTIMPL();
5834 break;
5835 }
5836
5837 case SVGA_3D_CMD_RESERVED2:
5838 {
5839 VMSVGA_3D_CMD_NOTIMPL();
5840 break;
5841 }
5842
5843 case SVGA_3D_CMD_RESERVED3:
5844 {
5845 VMSVGA_3D_CMD_NOTIMPL();
5846 break;
5847 }
5848
5849 case SVGA_3D_CMD_RESERVED4:
5850 {
5851 VMSVGA_3D_CMD_NOTIMPL();
5852 break;
5853 }
5854
5855 case SVGA_3D_CMD_RESERVED5:
5856 {
5857 VMSVGA_3D_CMD_NOTIMPL();
5858 break;
5859 }
5860
5861 case SVGA_3D_CMD_RESERVED6:
5862 {
5863 VMSVGA_3D_CMD_NOTIMPL();
5864 break;
5865 }
5866
5867 case SVGA_3D_CMD_RESERVED7:
5868 {
5869 VMSVGA_3D_CMD_NOTIMPL();
5870 break;
5871 }
5872
5873 case SVGA_3D_CMD_RESERVED8:
5874 {
5875 VMSVGA_3D_CMD_NOTIMPL();
5876 break;
5877 }
5878
5879 case SVGA_3D_CMD_GROW_OTABLE:
5880 {
5881 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5883 rcParse = vmsvga3dCmdGrowOTable(pThisCC, pCmd, cbCmd);
5884 break;
5885 }
5886
5887 case SVGA_3D_CMD_DX_GROW_COTABLE:
5888 {
5889 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5891 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd, cbCmd);
5892 break;
5893 }
5894
5895 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5896 {
5897 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5899 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5900 break;
5901 }
5902
5903 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5904 {
5905 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5907 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
5908 break;
5909 }
5910
5911 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5912 {
5913 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5915 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5916 break;
5917 }
5918
5919 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5920 {
5921 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5923 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5924 break;
5925 }
5926
5927 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5928 {
5929 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5931 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5932 break;
5933 }
5934
5935 case SVGA_3D_CMD_DX_PRED_CONVERT:
5936 {
5937 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5939 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5940 break;
5941 }
5942
5943 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5944 {
5945 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5946 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5947 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5948 break;
5949 }
5950
5951 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5952 {
5953 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5955 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5956 break;
5957 }
5958
5959 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5960 {
5961 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5963 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5964 break;
5965 }
5966
5967 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5968 {
5969 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5971 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5972 break;
5973 }
5974
5975 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5976 {
5977 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5979 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5980 break;
5981 }
5982
5983 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5984 {
5985 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5987 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5988 break;
5989 }
5990
5991 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5992 {
5993 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5995 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5996 break;
5997 }
5998
5999 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
6000 {
6001 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
6002 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6003 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6004 break;
6005 }
6006
6007 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
6008 {
6009 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
6010 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6011 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6012 break;
6013 }
6014
6015 case SVGA_3D_CMD_DX_DISPATCH:
6016 {
6017 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
6018 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6019 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
6020 break;
6021 }
6022
6023 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
6024 {
6025 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
6026 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6027 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6028 break;
6029 }
6030
6031 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
6032 {
6033 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
6034 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6035 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
6036 break;
6037 }
6038
6039 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
6040 {
6041 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
6042 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6043 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
6044 break;
6045 }
6046
6047 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
6048 {
6049 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
6050 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6051 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
6052 break;
6053 }
6054
6055 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
6056 {
6057 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
6058 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6059 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
6060 break;
6061 }
6062
6063 case SVGA_3D_CMD_LOGICOPS_BITBLT:
6064 {
6065 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
6066 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6067 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
6068 break;
6069 }
6070
6071 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
6072 {
6073 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
6074 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6075 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
6076 break;
6077 }
6078
6079 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
6080 {
6081 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
6082 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6083 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
6084 break;
6085 }
6086
6087 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
6088 {
6089 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
6090 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6091 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
6092 break;
6093 }
6094
6095 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
6096 {
6097 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
6098 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6099 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
6100 break;
6101 }
6102
6103 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
6104 {
6105 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
6106 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6107 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6108 break;
6109 }
6110
6111 case SVGA_3D_CMD_RESERVED2_1:
6112 {
6113 VMSVGA_3D_CMD_NOTIMPL();
6114 break;
6115 }
6116
6117 case SVGA_3D_CMD_RESERVED2_2:
6118 {
6119 VMSVGA_3D_CMD_NOTIMPL();
6120 break;
6121 }
6122
6123 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6124 {
6125 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
6126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6127 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
6128 break;
6129 }
6130
6131 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6132 {
6133 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
6134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6135 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6136 break;
6137 }
6138
6139 case SVGA_3D_CMD_DX_SET_MIN_LOD:
6140 {
6141 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
6142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6143 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6144 break;
6145 }
6146
6147 case SVGA_3D_CMD_RESERVED2_3:
6148 {
6149 VMSVGA_3D_CMD_NOTIMPL();
6150 break;
6151 }
6152
6153 case SVGA_3D_CMD_RESERVED2_4:
6154 {
6155 VMSVGA_3D_CMD_NOTIMPL();
6156 break;
6157 }
6158
6159 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6160 {
6161 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6163 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6164 break;
6165 }
6166
6167 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6168 {
6169 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6171 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6172 break;
6173 }
6174
6175 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6176 {
6177 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6178 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6179 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6180 break;
6181 }
6182
6183 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6184 {
6185 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6186 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6187 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6188 break;
6189 }
6190
6191 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6192 {
6193 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6195 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6196 break;
6197 }
6198
6199 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6200 {
6201 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6203 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6204 break;
6205 }
6206
6207 case SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION:
6208 {
6209 SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd = (SVGA3dCmdVBDXClearRenderTargetViewRegion *)pvCmd;
6210 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6211 rcParse = vmsvga3dCmdVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cbCmd);
6212 break;
6213 }
6214
6215 /* Unsupported commands. */
6216 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6217 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6218 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6219 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6220 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6221 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6222 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6223 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6224 /* Prevent the compiler warning. */
6225 case SVGA_3D_CMD_LEGACY_BASE:
6226 case SVGA_3D_CMD_MAX:
6227 case SVGA_3D_CMD_FUTURE_MAX:
6228 /* No 'default' case */
6229 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6230 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6231 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6232 rcParse = VERR_NOT_IMPLEMENTED;
6233 break;
6234 }
6235
6236 return VINF_SUCCESS;
6237// return rcParse;
6238}
6239# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6240#endif /* VBOX_WITH_VMSVGA3D */
6241
6242
6243/*
6244 *
6245 * Handlers for FIFO commands.
6246 *
6247 * Every handler takes the following parameters:
6248 *
6249 * pThis The shared VGA/VMSVGA state.
6250 * pThisCC The VGA/VMSVGA state for ring-3.
6251 * pCmd The command data.
6252 */
6253
6254
6255/* SVGA_CMD_UPDATE */
6256void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6257{
6258 RT_NOREF(pThis);
6259 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6260
6261 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6262 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6263
6264 /** @todo Multiple screens? */
6265 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6266 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6267 return;
6268
6269 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6270}
6271
6272
6273/* SVGA_CMD_UPDATE_VERBOSE */
6274void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6275{
6276 RT_NOREF(pThis);
6277 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6278
6279 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6280 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6281
6282 /** @todo Multiple screens? */
6283 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6284 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6285 return;
6286
6287 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6288}
6289
6290
6291/* SVGA_CMD_RECT_FILL */
6292void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6293{
6294 RT_NOREF(pThis, pCmd);
6295 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6296
6297 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6298 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6299 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6300}
6301
6302
6303/* SVGA_CMD_RECT_COPY */
6304void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6305{
6306 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6307
6308 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6309 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6310
6311 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6312 AssertPtrReturnVoid(pScreen);
6313
6314 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6315 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6316 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6317 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6318 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6319 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6320 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6321
6322 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6323 pCmd->width, pCmd->height, pThis->vram_size);
6324 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6325}
6326
6327
6328/* SVGA_CMD_RECT_ROP_COPY */
6329void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6330{
6331 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6332
6333 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6334 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6335
6336 if (pCmd->rop != SVGA_ROP_COPY)
6337 {
6338 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6339 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6340 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6341 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6342 */
6343 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6344 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6345 return;
6346 }
6347
6348 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6349 AssertPtrReturnVoid(pScreen);
6350
6351 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6352 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6353 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6354 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6355 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6356 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6357 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6358
6359 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6360 pCmd->width, pCmd->height, pThis->vram_size);
6361 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6362}
6363
6364
6365/* SVGA_CMD_DISPLAY_CURSOR */
6366void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6367{
6368 RT_NOREF(pThis, pCmd);
6369 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6370
6371 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6372 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6373 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6374}
6375
6376
6377/* SVGA_CMD_MOVE_CURSOR */
6378void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6379{
6380 RT_NOREF(pThis, pCmd);
6381 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6382
6383 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6384 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6385 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6386}
6387
6388
6389/* SVGA_CMD_DEFINE_CURSOR */
6390void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6391{
6392 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6393
6394 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6395 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6396 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6397
6398 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6399 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6400 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6401 RT_UNTRUSTED_VALIDATED_FENCE();
6402
6403 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6404 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6405 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6406
6407 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6408 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6409
6410 uint32_t const cx = pCmd->width;
6411 uint32_t const cy = pCmd->height;
6412
6413 /*
6414 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6415 * The AND data uses 8-bit aligned scanlines.
6416 * The XOR data must be starting on a 32-bit boundrary.
6417 */
6418 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6419 uint32_t cbDstAndMask = cbDstAndLine * cy;
6420 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6421 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6422
6423 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6424 AssertReturnVoid(pbCopy);
6425
6426 /* Convert the AND mask. */
6427 uint8_t *pbDst = pbCopy;
6428 uint8_t const *pbSrc = pbSrcAndMask;
6429 switch (pCmd->andMaskDepth)
6430 {
6431 case 1:
6432 if (cbSrcAndLine == cbDstAndLine)
6433 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6434 else
6435 {
6436 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6437 for (uint32_t y = 0; y < cy; y++)
6438 {
6439 memcpy(pbDst, pbSrc, cbDstAndLine);
6440 pbDst += cbDstAndLine;
6441 pbSrc += cbSrcAndLine;
6442 }
6443 }
6444 break;
6445 /* Should take the XOR mask into account for the multi-bit AND mask. */
6446 case 8:
6447 for (uint32_t y = 0; y < cy; y++)
6448 {
6449 for (uint32_t x = 0; x < cx; )
6450 {
6451 uint8_t bDst = 0;
6452 uint8_t fBit = 0x80;
6453 do
6454 {
6455 uintptr_t const idxPal = pbSrc[x] * 3;
6456 if ((( pThis->last_palette[idxPal]
6457 | (pThis->last_palette[idxPal] >> 8)
6458 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6459 bDst |= fBit;
6460 fBit >>= 1;
6461 x++;
6462 } while (x < cx && (x & 7));
6463 pbDst[(x - 1) / 8] = bDst;
6464 }
6465 pbDst += cbDstAndLine;
6466 pbSrc += cbSrcAndLine;
6467 }
6468 break;
6469 case 15:
6470 for (uint32_t y = 0; y < cy; y++)
6471 {
6472 for (uint32_t x = 0; x < cx; )
6473 {
6474 uint8_t bDst = 0;
6475 uint8_t fBit = 0x80;
6476 do
6477 {
6478 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6479 bDst |= fBit;
6480 fBit >>= 1;
6481 x++;
6482 } while (x < cx && (x & 7));
6483 pbDst[(x - 1) / 8] = bDst;
6484 }
6485 pbDst += cbDstAndLine;
6486 pbSrc += cbSrcAndLine;
6487 }
6488 break;
6489 case 16:
6490 for (uint32_t y = 0; y < cy; y++)
6491 {
6492 for (uint32_t x = 0; x < cx; )
6493 {
6494 uint8_t bDst = 0;
6495 uint8_t fBit = 0x80;
6496 do
6497 {
6498 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6499 bDst |= fBit;
6500 fBit >>= 1;
6501 x++;
6502 } while (x < cx && (x & 7));
6503 pbDst[(x - 1) / 8] = bDst;
6504 }
6505 pbDst += cbDstAndLine;
6506 pbSrc += cbSrcAndLine;
6507 }
6508 break;
6509 case 24:
6510 for (uint32_t y = 0; y < cy; y++)
6511 {
6512 for (uint32_t x = 0; x < cx; )
6513 {
6514 uint8_t bDst = 0;
6515 uint8_t fBit = 0x80;
6516 do
6517 {
6518 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6519 bDst |= fBit;
6520 fBit >>= 1;
6521 x++;
6522 } while (x < cx && (x & 7));
6523 pbDst[(x - 1) / 8] = bDst;
6524 }
6525 pbDst += cbDstAndLine;
6526 pbSrc += cbSrcAndLine;
6527 }
6528 break;
6529 case 32:
6530 for (uint32_t y = 0; y < cy; y++)
6531 {
6532 for (uint32_t x = 0; x < cx; )
6533 {
6534 uint8_t bDst = 0;
6535 uint8_t fBit = 0x80;
6536 do
6537 {
6538 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6539 bDst |= fBit;
6540 fBit >>= 1;
6541 x++;
6542 } while (x < cx && (x & 7));
6543 pbDst[(x - 1) / 8] = bDst;
6544 }
6545 pbDst += cbDstAndLine;
6546 pbSrc += cbSrcAndLine;
6547 }
6548 break;
6549 default:
6550 RTMemFreeZ(pbCopy, cbCopy);
6551 AssertFailedReturnVoid();
6552 }
6553
6554 /* Convert the XOR mask. */
6555 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6556 pbSrc = pbSrcXorMask;
6557 switch (pCmd->xorMaskDepth)
6558 {
6559 case 1:
6560 for (uint32_t y = 0; y < cy; y++)
6561 {
6562 for (uint32_t x = 0; x < cx; )
6563 {
6564 /* most significant bit is the left most one. */
6565 uint8_t bSrc = pbSrc[x / 8];
6566 do
6567 {
6568 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6569 bSrc <<= 1;
6570 x++;
6571 } while ((x & 7) && x < cx);
6572 }
6573 pbSrc += cbSrcXorLine;
6574 }
6575 break;
6576 case 8:
6577 for (uint32_t y = 0; y < cy; y++)
6578 {
6579 for (uint32_t x = 0; x < cx; x++)
6580 {
6581 uint32_t u = pThis->last_palette[pbSrc[x]];
6582 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6583 }
6584 pbSrc += cbSrcXorLine;
6585 }
6586 break;
6587 case 15: /* Src: RGB-5-5-5 */
6588 for (uint32_t y = 0; y < cy; y++)
6589 {
6590 for (uint32_t x = 0; x < cx; x++)
6591 {
6592 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6593 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6594 ((uValue >> 5) & 0x1f) << 3,
6595 ((uValue >> 10) & 0x1f) << 3, 0);
6596 }
6597 pbSrc += cbSrcXorLine;
6598 }
6599 break;
6600 case 16: /* Src: RGB-5-6-5 */
6601 for (uint32_t y = 0; y < cy; y++)
6602 {
6603 for (uint32_t x = 0; x < cx; x++)
6604 {
6605 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6606 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6607 ((uValue >> 5) & 0x3f) << 2,
6608 ((uValue >> 11) & 0x1f) << 3, 0);
6609 }
6610 pbSrc += cbSrcXorLine;
6611 }
6612 break;
6613 case 24:
6614 for (uint32_t y = 0; y < cy; y++)
6615 {
6616 for (uint32_t x = 0; x < cx; x++)
6617 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6618 pbSrc += cbSrcXorLine;
6619 }
6620 break;
6621 case 32:
6622 for (uint32_t y = 0; y < cy; y++)
6623 {
6624 for (uint32_t x = 0; x < cx; x++)
6625 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6626 pbSrc += cbSrcXorLine;
6627 }
6628 break;
6629 default:
6630 RTMemFreeZ(pbCopy, cbCopy);
6631 AssertFailedReturnVoid();
6632 }
6633
6634 /*
6635 * Pass it to the frontend/whatever.
6636 */
6637 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6638 cx, cy, pbCopy, cbCopy);
6639}
6640
6641
6642/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6643void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6644{
6645 RT_NOREF(pThis);
6646 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6647
6648 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6649 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6650
6651 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6652 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6653 RT_UNTRUSTED_VALIDATED_FENCE();
6654
6655 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6656 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6657 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6658 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6659 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6660
6661 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6662 AssertPtrReturnVoid(pCursorCopy);
6663
6664 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6665 memset(pCursorCopy, 0xff, cbAndMask);
6666 /* Colour data */
6667 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6668
6669 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6670 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6671}
6672
6673
6674/* SVGA_CMD_ESCAPE */
6675void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6676{
6677 RT_NOREF(pThis);
6678 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6679
6680 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6681
6682 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6683 {
6684 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6685 RT_UNTRUSTED_VALIDATED_FENCE();
6686
6687 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6688 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6689
6690 switch (cmd)
6691 {
6692 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6693 {
6694 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6695 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6696 RT_UNTRUSTED_VALIDATED_FENCE();
6697
6698 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6699
6700 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6701 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6702 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6703 RT_NOREF_PV(pVideoCmd);
6704 break;
6705 }
6706
6707 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6708 {
6709 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6710 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6711 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6712 RT_NOREF_PV(pVideoCmd);
6713 break;
6714 }
6715
6716 default:
6717 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6718 break;
6719 }
6720 }
6721 else
6722 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6723}
6724
6725
6726/* SVGA_CMD_DEFINE_SCREEN */
6727void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6728{
6729 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6730
6731 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6732 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6733 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6734 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6735
6736 uint32_t const idScreen = pCmd->screen.id;
6737 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6738
6739 uint32_t const uWidth = pCmd->screen.size.width;
6740 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6741
6742 uint32_t const uHeight = pCmd->screen.size.height;
6743 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6744
6745 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6746 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6747 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6748
6749 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6750 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6751
6752 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6753 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6754 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6755 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6756 RT_UNTRUSTED_VALIDATED_FENCE();
6757
6758 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6759 Assert(pScreen->idScreen == idScreen);
6760 pScreen->fDefined = true;
6761 pScreen->fModified = true;
6762 pScreen->fuScreen = pCmd->screen.flags;
6763 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6764 {
6765 /* Not blanked. */
6766 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6767 RT_UNTRUSTED_VALIDATED_FENCE();
6768
6769 pScreen->xOrigin = pCmd->screen.root.x;
6770 pScreen->yOrigin = pCmd->screen.root.y;
6771 pScreen->cWidth = uWidth;
6772 pScreen->cHeight = uHeight;
6773 pScreen->offVRAM = uScreenOffset;
6774 pScreen->cbPitch = cbPitch;
6775 pScreen->cBpp = 32;
6776 }
6777 else
6778 {
6779 /* Screen blanked. Keep old values. */
6780 }
6781
6782 pThis->svga.fGFBRegisters = false;
6783 vmsvgaR3ChangeMode(pThis, pThisCC);
6784
6785#ifdef VBOX_WITH_VMSVGA3D
6786 if (RT_LIKELY(pThis->svga.f3DEnabled))
6787 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6788#endif
6789}
6790
6791
6792/* SVGA_CMD_DESTROY_SCREEN */
6793void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6794{
6795 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6796
6797 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6798 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6799
6800 uint32_t const idScreen = pCmd->screenId;
6801 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6802 RT_UNTRUSTED_VALIDATED_FENCE();
6803
6804 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6805 Assert(pScreen->idScreen == idScreen);
6806 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
6807}
6808
6809
6810/* SVGA_CMD_DEFINE_GMRFB */
6811void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6812{
6813 RT_NOREF(pThis);
6814 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6815
6816 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6817 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6818 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6819
6820 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6821 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6822 pSvgaR3State->GMRFB.format = pCmd->format;
6823}
6824
6825
6826/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6827void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6828{
6829 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6830
6831 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6832 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6833 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6834
6835 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6836 RT_UNTRUSTED_VALIDATED_FENCE();
6837
6838 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6839 AssertPtrReturnVoid(pScreen);
6840
6841 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6842 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6843
6844 /* Clip destRect to the screen dimensions. */
6845 SVGASignedRect screenRect;
6846 screenRect.left = 0;
6847 screenRect.top = 0;
6848 screenRect.right = pScreen->cWidth;
6849 screenRect.bottom = pScreen->cHeight;
6850 SVGASignedRect clipRect = pCmd->destRect;
6851 vmsvgaR3ClipRect(&screenRect, &clipRect);
6852 RT_UNTRUSTED_VALIDATED_FENCE();
6853
6854 uint32_t const width = clipRect.right - clipRect.left;
6855 uint32_t const height = clipRect.bottom - clipRect.top;
6856
6857 if ( width == 0
6858 || height == 0)
6859 return; /* Nothing to do. */
6860
6861 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6862 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6863
6864 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6865 * Prepare parameters for vmsvgaR3GmrTransfer.
6866 */
6867 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6868
6869 /* Destination: host buffer which describes the screen 0 VRAM.
6870 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6871 */
6872 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6873 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6874 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6875 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6876 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6877 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6878 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6879 + cbScanline * clipRect.top;
6880 int32_t const cbHstPitch = cbScanline;
6881
6882 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6883 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6884 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6885 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6886 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6887
6888 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6889 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6890 gstPtr, offGst, cbGstPitch,
6891 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6892 AssertRC(rc);
6893 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6894}
6895
6896
6897/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6898void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6899{
6900 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6901
6902 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6903 /* Note! This can fetch 3d render results as well!! */
6904 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6905 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6906
6907 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6908 RT_UNTRUSTED_VALIDATED_FENCE();
6909
6910 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6911 AssertPtrReturnVoid(pScreen);
6912
6913 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6914 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6915
6916 /* Clip destRect to the screen dimensions. */
6917 SVGASignedRect screenRect;
6918 screenRect.left = 0;
6919 screenRect.top = 0;
6920 screenRect.right = pScreen->cWidth;
6921 screenRect.bottom = pScreen->cHeight;
6922 SVGASignedRect clipRect = pCmd->srcRect;
6923 vmsvgaR3ClipRect(&screenRect, &clipRect);
6924 RT_UNTRUSTED_VALIDATED_FENCE();
6925
6926 uint32_t const width = clipRect.right - clipRect.left;
6927 uint32_t const height = clipRect.bottom - clipRect.top;
6928
6929 if ( width == 0
6930 || height == 0)
6931 return; /* Nothing to do. */
6932
6933 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6934 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6935
6936 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6937 * Prepare parameters for vmsvgaR3GmrTransfer.
6938 */
6939 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6940
6941 /* Source: host buffer which describes the screen 0 VRAM.
6942 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6943 */
6944 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6945 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6946 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6947 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6948 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6949 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6950 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6951 + cbScanline * clipRect.top;
6952 int32_t const cbHstPitch = cbScanline;
6953
6954 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6955 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6956 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6957 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6958 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6959
6960 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6961 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6962 gstPtr, offGst, cbGstPitch,
6963 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6964 AssertRC(rc);
6965}
6966
6967
6968/* SVGA_CMD_ANNOTATION_FILL */
6969void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6970{
6971 RT_NOREF(pThis);
6972 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6973
6974 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6975 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6976
6977 pSvgaR3State->colorAnnotation = pCmd->color;
6978}
6979
6980
6981/* SVGA_CMD_ANNOTATION_COPY */
6982void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6983{
6984 RT_NOREF(pThis, pCmd);
6985 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6986
6987 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6988 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6989
6990 AssertFailed();
6991}
6992
6993
6994#ifdef VBOX_WITH_VMSVGA3D
6995/* SVGA_CMD_DEFINE_GMR2 */
6996void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6997{
6998 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6999
7000 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
7001 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
7002
7003 /* Validate current GMR id. */
7004 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
7005 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
7006 RT_UNTRUSTED_VALIDATED_FENCE();
7007
7008 if (!pCmd->numPages)
7009 {
7010 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
7011 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
7012 }
7013 else
7014 {
7015 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
7016 if (pGMR->cMaxPages)
7017 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
7018
7019 /* Not sure if we should always free the descriptor, but for simplicity
7020 we do so if the new size is smaller than the current. */
7021 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
7022 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
7023 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
7024
7025 pGMR->cMaxPages = pCmd->numPages;
7026 /* The rest is done by the REMAP_GMR2 command. */
7027 }
7028}
7029
7030
7031/* SVGA_CMD_REMAP_GMR2 */
7032void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
7033{
7034 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7035
7036 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
7037 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
7038
7039 /* Validate current GMR id and size. */
7040 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
7041 RT_UNTRUSTED_VALIDATED_FENCE();
7042 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
7043 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
7044 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
7045 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
7046
7047 if (pCmd->numPages == 0)
7048 return;
7049 RT_UNTRUSTED_VALIDATED_FENCE();
7050
7051 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
7052 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
7053
7054 /*
7055 * We flatten the existing descriptors into a page array, overwrite the
7056 * pages specified in this command and then recompress the descriptor.
7057 */
7058 /** @todo Optimize the GMR remap algorithm! */
7059
7060 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
7061 uint64_t *paNewPage64 = NULL;
7062 if (pGMR->paDesc)
7063 {
7064 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
7065
7066 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
7067 AssertPtrReturnVoid(paNewPage64);
7068
7069 uint32_t idxPage = 0;
7070 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
7071 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
7072 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
7073 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
7074 RT_UNTRUSTED_VALIDATED_FENCE();
7075 }
7076
7077 /* Free the old GMR if present. */
7078 if (pGMR->paDesc)
7079 RTMemFree(pGMR->paDesc);
7080
7081 /* Allocate the maximum amount possible (everything non-continuous) */
7082 PVMSVGAGMRDESCRIPTOR paDescs;
7083 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
7084 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
7085
7086 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
7087 {
7088 /** @todo */
7089 AssertFailed();
7090 pGMR->numDescriptors = 0;
7091 }
7092 else
7093 {
7094 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
7095 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
7096 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
7097
7098 uint32_t cPages;
7099 if (paNewPage64)
7100 {
7101 /* Overwrite the old page array with the new page values. */
7102 if (fGCPhys64)
7103 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7104 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
7105 else
7106 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7107 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
7108
7109 /* Use the updated page array instead of the command data. */
7110 fGCPhys64 = true;
7111 paPages64 = paNewPage64;
7112 cPages = cNewTotalPages;
7113 }
7114 else
7115 cPages = pCmd->numPages;
7116
7117 /* The first page. */
7118 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
7119 * applied to paNewPage64. */
7120 RTGCPHYS GCPhys;
7121 if (fGCPhys64)
7122 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7123 else
7124 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
7125 paDescs[0].GCPhys = GCPhys;
7126 paDescs[0].numPages = 1;
7127
7128 /* Subsequent pages. */
7129 uint32_t iDescriptor = 0;
7130 for (uint32_t i = 1; i < cPages; i++)
7131 {
7132 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
7133 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7134 else
7135 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
7136
7137 /* Continuous physical memory? */
7138 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
7139 {
7140 Assert(paDescs[iDescriptor].numPages);
7141 paDescs[iDescriptor].numPages++;
7142 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
7143 }
7144 else
7145 {
7146 iDescriptor++;
7147 paDescs[iDescriptor].GCPhys = GCPhys;
7148 paDescs[iDescriptor].numPages = 1;
7149 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7150 }
7151 }
7152
7153 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7154 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7155 pGMR->numDescriptors = iDescriptor + 1;
7156 }
7157
7158 if (paNewPage64)
7159 RTMemFree(paNewPage64);
7160}
7161
7162
7163/**
7164 * Free the specified GMR
7165 *
7166 * @param pThisCC The VGA/VMSVGA state for ring-3.
7167 * @param idGMR GMR id
7168 */
7169void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7170{
7171 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7172
7173 /* Free the old descriptor if present. */
7174 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7175 if ( pGMR->numDescriptors
7176 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7177 {
7178# ifdef DEBUG_GMR_ACCESS
7179 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7180# endif
7181
7182 Assert(pGMR->paDesc);
7183 RTMemFree(pGMR->paDesc);
7184 pGMR->paDesc = NULL;
7185 pGMR->numDescriptors = 0;
7186 pGMR->cbTotal = 0;
7187 pGMR->cMaxPages = 0;
7188 }
7189 Assert(!pGMR->cMaxPages);
7190 Assert(!pGMR->cbTotal);
7191}
7192#endif /* VBOX_WITH_VMSVGA3D */
7193
7194
7195/**
7196 * Copy between a GMR and a host memory buffer.
7197 *
7198 * @returns VBox status code.
7199 * @param pThis The shared VGA/VMSVGA instance data.
7200 * @param pThisCC The VGA/VMSVGA state for ring-3.
7201 * @param enmTransferType Transfer type (read/write)
7202 * @param pbHstBuf Host buffer pointer (valid)
7203 * @param cbHstBuf Size of host buffer (valid)
7204 * @param offHst Host buffer offset of the first scanline
7205 * @param cbHstPitch Destination buffer pitch
7206 * @param gstPtr GMR description
7207 * @param offGst Guest buffer offset of the first scanline
7208 * @param cbGstPitch Guest buffer pitch
7209 * @param cbWidth Width in bytes to copy
7210 * @param cHeight Number of scanllines to copy
7211 */
7212int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7213 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7214 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7215 uint32_t cbWidth, uint32_t cHeight)
7216{
7217 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7218 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7219 int rc;
7220
7221 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7222 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7223 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7224 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7225 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7226
7227 PGMR pGMR;
7228 uint32_t cbGmr; /* The GMR size in bytes. */
7229 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7230 {
7231 pGMR = NULL;
7232 cbGmr = pThis->vram_size;
7233 }
7234 else
7235 {
7236 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7237 RT_UNTRUSTED_VALIDATED_FENCE();
7238 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7239 cbGmr = pGMR->cbTotal;
7240 }
7241
7242 /*
7243 * GMR
7244 */
7245 /* Calculate GMR offset of the data to be copied. */
7246 AssertMsgReturn(gstPtr.offset < cbGmr,
7247 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7248 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7249 VERR_INVALID_PARAMETER);
7250 RT_UNTRUSTED_VALIDATED_FENCE();
7251 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7252 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7253 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7254 VERR_INVALID_PARAMETER);
7255 RT_UNTRUSTED_VALIDATED_FENCE();
7256 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7257
7258 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7259 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7260 AssertMsgReturn(cbGmrScanline != 0,
7261 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7262 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7263 VERR_INVALID_PARAMETER);
7264 RT_UNTRUSTED_VALIDATED_FENCE();
7265 AssertMsgReturn(cbWidth <= cbGmrScanline,
7266 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7267 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7268 VERR_INVALID_PARAMETER);
7269 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7270 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7271 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7272 VERR_INVALID_PARAMETER);
7273 RT_UNTRUSTED_VALIDATED_FENCE();
7274
7275 /* How many bytes are available for the data in the GMR. */
7276 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7277
7278 /* How many scanlines would fit into the available data. */
7279 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7280 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7281 if (cbWidth <= cbGmrLastScanline)
7282 ++cGmrScanlines;
7283
7284 if (cHeight > cGmrScanlines)
7285 cHeight = cGmrScanlines;
7286
7287 AssertMsgReturn(cHeight > 0,
7288 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7289 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7290 VERR_INVALID_PARAMETER);
7291 RT_UNTRUSTED_VALIDATED_FENCE();
7292
7293 /*
7294 * Host buffer.
7295 */
7296 AssertMsgReturn(offHst < cbHstBuf,
7297 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7298 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7299 VERR_INVALID_PARAMETER);
7300
7301 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7302 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7303 AssertMsgReturn(cbHstScanline != 0,
7304 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7305 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7306 VERR_INVALID_PARAMETER);
7307 AssertMsgReturn(cbWidth <= cbHstScanline,
7308 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7309 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7310 VERR_INVALID_PARAMETER);
7311 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7312 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7313 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7314 VERR_INVALID_PARAMETER);
7315
7316 /* How many bytes are available for the data in the buffer. */
7317 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7318
7319 /* How many scanlines would fit into the available data. */
7320 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7321 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7322 if (cbWidth <= cbHstLastScanline)
7323 ++cHstScanlines;
7324
7325 if (cHeight > cHstScanlines)
7326 cHeight = cHstScanlines;
7327
7328 AssertMsgReturn(cHeight > 0,
7329 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7330 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7331 VERR_INVALID_PARAMETER);
7332
7333 uint8_t *pbHst = pbHstBuf + offHst;
7334
7335 /* Shortcut for the framebuffer. */
7336 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7337 {
7338 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7339
7340 uint8_t const *pbSrc;
7341 int32_t cbSrcPitch;
7342 uint8_t *pbDst;
7343 int32_t cbDstPitch;
7344
7345 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7346 {
7347 pbSrc = pbHst;
7348 cbSrcPitch = cbHstPitch;
7349 pbDst = pbGst;
7350 cbDstPitch = cbGstPitch;
7351 }
7352 else
7353 {
7354 pbSrc = pbGst;
7355 cbSrcPitch = cbGstPitch;
7356 pbDst = pbHst;
7357 cbDstPitch = cbHstPitch;
7358 }
7359
7360 if ( cbWidth == (uint32_t)cbGstPitch
7361 && cbGstPitch == cbHstPitch)
7362 {
7363 /* Entire scanlines, positive pitch. */
7364 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7365 }
7366 else
7367 {
7368 for (uint32_t i = 0; i < cHeight; ++i)
7369 {
7370 memcpy(pbDst, pbSrc, cbWidth);
7371
7372 pbDst += cbDstPitch;
7373 pbSrc += cbSrcPitch;
7374 }
7375 }
7376 return VINF_SUCCESS;
7377 }
7378
7379 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7380 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7381
7382 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7383 uint32_t iDesc = 0; /* Index in the descriptor array. */
7384 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7385 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7386 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7387 for (uint32_t i = 0; i < cHeight; ++i)
7388 {
7389 uint32_t cbCurrentWidth = cbWidth;
7390 uint32_t offGmrCurrent = offGmrScanline;
7391 uint8_t *pbCurrentHost = pbHstScanline;
7392
7393 /* Find the right descriptor */
7394 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7395 {
7396 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7397 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7398 ++iDesc;
7399 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7400 }
7401
7402 while (cbCurrentWidth)
7403 {
7404 uint32_t cbToCopy;
7405
7406 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7407 cbToCopy = cbCurrentWidth;
7408 else
7409 {
7410 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7411 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7412 }
7413
7414 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7415
7416 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7417
7418 /*
7419 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7420 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7421 * see @bugref{9654#c75}.
7422 */
7423 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7424 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7425 else
7426 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7427 AssertRCBreak(rc);
7428
7429 cbCurrentWidth -= cbToCopy;
7430 offGmrCurrent += cbToCopy;
7431 pbCurrentHost += cbToCopy;
7432
7433 /* Go to the next descriptor if there's anything left. */
7434 if (cbCurrentWidth)
7435 {
7436 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7437 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7438 ++iDesc;
7439 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7440 }
7441 }
7442
7443 offGmrScanline += cbGstPitch;
7444 pbHstScanline += cbHstPitch;
7445 }
7446
7447 return VINF_SUCCESS;
7448}
7449
7450
7451/**
7452 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7453 *
7454 * @param pSizeSrc Source surface dimensions.
7455 * @param pSizeDest Destination surface dimensions.
7456 * @param pBox Coordinates to be clipped.
7457 */
7458void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7459{
7460 /* Src x, w */
7461 if (pBox->srcx > pSizeSrc->width)
7462 pBox->srcx = pSizeSrc->width;
7463 if (pBox->w > pSizeSrc->width - pBox->srcx)
7464 pBox->w = pSizeSrc->width - pBox->srcx;
7465
7466 /* Src y, h */
7467 if (pBox->srcy > pSizeSrc->height)
7468 pBox->srcy = pSizeSrc->height;
7469 if (pBox->h > pSizeSrc->height - pBox->srcy)
7470 pBox->h = pSizeSrc->height - pBox->srcy;
7471
7472 /* Src z, d */
7473 if (pBox->srcz > pSizeSrc->depth)
7474 pBox->srcz = pSizeSrc->depth;
7475 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7476 pBox->d = pSizeSrc->depth - pBox->srcz;
7477
7478 /* Dest x, w */
7479 if (pBox->x > pSizeDest->width)
7480 pBox->x = pSizeDest->width;
7481 if (pBox->w > pSizeDest->width - pBox->x)
7482 pBox->w = pSizeDest->width - pBox->x;
7483
7484 /* Dest y, h */
7485 if (pBox->y > pSizeDest->height)
7486 pBox->y = pSizeDest->height;
7487 if (pBox->h > pSizeDest->height - pBox->y)
7488 pBox->h = pSizeDest->height - pBox->y;
7489
7490 /* Dest z, d */
7491 if (pBox->z > pSizeDest->depth)
7492 pBox->z = pSizeDest->depth;
7493 if (pBox->d > pSizeDest->depth - pBox->z)
7494 pBox->d = pSizeDest->depth - pBox->z;
7495}
7496
7497
7498/**
7499 * Unsigned coordinates in pBox. Clip to [0; pSize).
7500 *
7501 * @param pSize Source surface dimensions.
7502 * @param pBox Coordinates to be clipped.
7503 */
7504void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7505{
7506 /* x, w */
7507 if (pBox->x > pSize->width)
7508 pBox->x = pSize->width;
7509 if (pBox->w > pSize->width - pBox->x)
7510 pBox->w = pSize->width - pBox->x;
7511
7512 /* y, h */
7513 if (pBox->y > pSize->height)
7514 pBox->y = pSize->height;
7515 if (pBox->h > pSize->height - pBox->y)
7516 pBox->h = pSize->height - pBox->y;
7517
7518 /* z, d */
7519 if (pBox->z > pSize->depth)
7520 pBox->z = pSize->depth;
7521 if (pBox->d > pSize->depth - pBox->z)
7522 pBox->d = pSize->depth - pBox->z;
7523}
7524
7525
7526/**
7527 * Clip.
7528 *
7529 * @param pBound Bounding rectangle.
7530 * @param pRect Rectangle to be clipped.
7531 */
7532void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7533{
7534 int32_t left;
7535 int32_t top;
7536 int32_t right;
7537 int32_t bottom;
7538
7539 /* Right order. */
7540 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7541 if (pRect->left < pRect->right)
7542 {
7543 left = pRect->left;
7544 right = pRect->right;
7545 }
7546 else
7547 {
7548 left = pRect->right;
7549 right = pRect->left;
7550 }
7551 if (pRect->top < pRect->bottom)
7552 {
7553 top = pRect->top;
7554 bottom = pRect->bottom;
7555 }
7556 else
7557 {
7558 top = pRect->bottom;
7559 bottom = pRect->top;
7560 }
7561
7562 if (left < pBound->left)
7563 left = pBound->left;
7564 if (right < pBound->left)
7565 right = pBound->left;
7566
7567 if (left > pBound->right)
7568 left = pBound->right;
7569 if (right > pBound->right)
7570 right = pBound->right;
7571
7572 if (top < pBound->top)
7573 top = pBound->top;
7574 if (bottom < pBound->top)
7575 bottom = pBound->top;
7576
7577 if (top > pBound->bottom)
7578 top = pBound->bottom;
7579 if (bottom > pBound->bottom)
7580 bottom = pBound->bottom;
7581
7582 pRect->left = left;
7583 pRect->right = right;
7584 pRect->top = top;
7585 pRect->bottom = bottom;
7586}
7587
7588
7589/**
7590 * Clip.
7591 *
7592 * @param pBound Bounding rectangle.
7593 * @param pRect Rectangle to be clipped.
7594 */
7595void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7596{
7597 uint32_t const leftBound = pBound->x;
7598 uint32_t const rightBound = pBound->x + pBound->w;
7599 uint32_t const topBound = pBound->y;
7600 uint32_t const bottomBound = pBound->y + pBound->h;
7601
7602 uint32_t x = pRect->x;
7603 uint32_t y = pRect->y;
7604 uint32_t w = pRect->w;
7605 uint32_t h = pRect->h;
7606
7607 /* Make sure that right and bottom coordinates can be safely computed. */
7608 if (x > rightBound)
7609 x = rightBound;
7610 if (w > rightBound - x)
7611 w = rightBound - x;
7612 if (y > bottomBound)
7613 y = bottomBound;
7614 if (h > bottomBound - y)
7615 h = bottomBound - y;
7616
7617 /* Switch from x, y, w, h to left, top, right, bottom. */
7618 uint32_t left = x;
7619 uint32_t right = x + w;
7620 uint32_t top = y;
7621 uint32_t bottom = y + h;
7622
7623 /* A standard left, right, bottom, top clipping. */
7624 if (left < leftBound)
7625 left = leftBound;
7626 if (right < leftBound)
7627 right = leftBound;
7628
7629 if (left > rightBound)
7630 left = rightBound;
7631 if (right > rightBound)
7632 right = rightBound;
7633
7634 if (top < topBound)
7635 top = topBound;
7636 if (bottom < topBound)
7637 bottom = topBound;
7638
7639 if (top > bottomBound)
7640 top = bottomBound;
7641 if (bottom > bottomBound)
7642 bottom = bottomBound;
7643
7644 /* Back to x, y, w, h representation. */
7645 pRect->x = left;
7646 pRect->y = top;
7647 pRect->w = right - left;
7648 pRect->h = bottom - top;
7649}
7650
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