VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 87812

Last change on this file since 87812 was 87028, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Devices/Graphics/DevVGA-SVGA: Use non-PCI guest memory read/write for bypassing the IOMMU for certain reads and writes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 230.3 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 87028 2020-12-02 05:09:19Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344#if !defined(VMSVGA3D_DX)
345# ifdef VBOX_WITH_VMSVGA3D
346/*
347 * Stub for old backends.
348 */
349int vmsvga3dQueryInterface(PVGASTATECC pThisCC, char const *pszInterfaceName, void *pvInterfaceFuncs, size_t cbInterfaceFuncs)
350{
351 RT_NOREF(pThisCC, pszInterfaceName, pvInterfaceFuncs, cbInterfaceFuncs);
352 return VERR_NOT_IMPLEMENTED;
353}
354# endif
355#endif
356
357
358/*
359 *
360 * Guest-Backed Objects (GBO).
361 *
362 */
363
364/**
365 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
366 *
367 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
368 * @param pVM VM Handle.
369 * @param pVCpu The cross context CPU structure for the calling EMT.
370 * @param GCPhys The physical address the guest is writing to.
371 * @param pvPhys The HC mapping of that address.
372 * @param pvBuf What the guest is reading/writing.
373 * @param cbBuf How much it's reading/writing.
374 * @param enmAccessType The access type.
375 * @param enmOrigin Who is making the access.
376 * @param pvUser User argument.
377 */
378DECLCALLBACK(VBOXSTRICTRC)
379vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
380 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
381{
382 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
383
384 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
385 return VINF_PGM_HANDLER_DO_DEFAULT;
386
387 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
388 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
389 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
390 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
391
392 /*
393 * The guest is not allowed to access the memory.
394 * Set the error condition.
395 */
396 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
397
398 /* Try to find the GBO which the guest is accessing. */
399 char const *pszTarget = NULL;
400 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
401 {
402 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
403 if (pGbo->cDescriptors)
404 {
405 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
406 {
407 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
408 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
409 {
410 switch (i)
411 {
412 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
413 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
414 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
415 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
416 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
417 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
418 default: pszTarget = "Unknown OTABLE"; break;
419 }
420 break;
421 }
422 }
423 }
424 }
425
426 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
427 "%.*Rhxd\n",
428 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
429
430 return VINF_PGM_HANDLER_DO_DEFAULT;
431}
432
433
434static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
435{
436 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
437
438 /*
439 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
440 * Content of the root page depends on the ptDepth value:
441 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
442 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
443 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
444 * The code below extracts the page addresses of the GBO.
445 */
446
447 /* Verify and normalize the ptDepth value. */
448 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
449 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
450 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
451 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
452 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
453 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
454 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
455 {
456 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
457 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
458 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
459 }
460 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
461 { }
462 else
463 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
464
465 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
466
467 pGbo->cbTotal = sizeInBytes;
468 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
469
470 /* Allocate the maximum amount possible (everything non-continuous) */
471 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
472 AssertReturn(paDescriptors, VERR_NO_MEMORY);
473
474 int rc = VINF_SUCCESS;
475 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
476 {
477 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
478 RTMemFree(paDescriptors),
479 VERR_INVALID_PARAMETER);
480
481 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
482 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
483 paDescriptors[0].GCPhys = GCPhys;
484 paDescriptors[0].cPages = 1;
485 }
486 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
487 {
488 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
489 RTMemFree(paDescriptors),
490 VERR_INVALID_PARAMETER);
491
492 /* Read the root page. */
493 uint8_t au8RootPage[X86_PAGE_SIZE];
494 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
495 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
496 if (RT_SUCCESS(rc))
497 {
498 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
499 PPN *paPPN32 = (PPN *)&au8RootPage[0];
500 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
501 {
502 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
503 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
504 paDescriptors[iPPN].GCPhys = GCPhys;
505 paDescriptors[iPPN].cPages = 1;
506 }
507 }
508 }
509 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
510 {
511 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
512 RTMemFree(paDescriptors),
513 VERR_INVALID_PARAMETER);
514
515 /* Read the Level2 root page. */
516 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
517 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
518 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
519 if (RT_SUCCESS(rc))
520 {
521 uint32_t cPagesLeft = pGbo->cTotalPages;
522
523 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
524 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
525
526 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
527 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
528 {
529 /* Read the Level1 root page. */
530 uint8_t au8RootPage[X86_PAGE_SIZE];
531 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
532 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
533 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
534 if (RT_SUCCESS(rc))
535 {
536 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
537 PPN *paPPN32 = (PPN *)&au8RootPage[0];
538
539 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
540 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
541 {
542 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
545 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
546 }
547 cPagesLeft -= cPPNs;
548 }
549 }
550 }
551 }
552 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
553 {
554 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
555 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
556 paDescriptors[0].GCPhys = GCPhys;
557 paDescriptors[0].cPages = pGbo->cTotalPages;
558 }
559 else
560 {
561 AssertFailed();
562 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
563 }
564
565 /* Compress the descriptors. */
566 if (ptDepth != SVGA3D_MOBFMT_RANGE)
567 {
568 uint32_t iDescriptor = 0;
569 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
570 {
571 /* Continuous physical memory? */
572 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
573 {
574 Assert(paDescriptors[iDescriptor].cPages);
575 paDescriptors[iDescriptor].cPages++;
576 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
577 }
578 else
579 {
580 iDescriptor++;
581 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
582 paDescriptors[iDescriptor].cPages = 1;
583 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
584 }
585 }
586
587 pGbo->cDescriptors = iDescriptor + 1;
588 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
589 }
590 else
591 pGbo->cDescriptors = 1;
592
593 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
594 {
595 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
596 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
597 }
598 else
599 pGbo->paDescriptors = paDescriptors;
600
601 if (fWriteProtected)
602 {
603 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
604 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
605 {
606 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
607 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
608 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
609 AssertRC(rc);
610 }
611 }
612
613 return VINF_SUCCESS;
614}
615
616
617static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
618{
619 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
620 {
621 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
622 {
623 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
624 {
625 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
626 AssertRC(rc);
627 }
628 }
629 RTMemFree(pGbo->paDescriptors);
630 RT_ZERO(pGbo);
631 }
632}
633
634
635typedef enum VMSVGAGboTransferDirection
636{
637 VMSVGAGboTransferDirection_Read,
638 VMSVGAGboTransferDirection_Write,
639} VMSVGAGboTransferDirection;
640
641static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
642 uint32_t off, void *pvData, uint32_t cbData,
643 VMSVGAGboTransferDirection enmDirection)
644{
645// ASMBreakpoint();
646 int rc = VINF_SUCCESS;
647 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
648
649 /* Find the right descriptor */
650 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
651 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
652 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
653 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
654 {
655 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
656 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
657 ++iDescriptor;
658 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
659 }
660
661 while (cbData)
662 {
663 uint32_t cbToCopy;
664 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
665 cbToCopy = cbData;
666 else
667 {
668 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
669 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
670 }
671
672 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
673 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
674
675 /*
676 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
677 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
678 * see @bugref{9654#c75}.
679 */
680 if (enmDirection == VMSVGAGboTransferDirection_Read)
681 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
682 else
683 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
684 AssertRCBreak(rc);
685
686 cbData -= cbToCopy;
687 off += cbToCopy;
688 pu8CurrentHost += cbToCopy;
689
690 /* Go to the next descriptor if there's anything left. */
691 if (cbData)
692 {
693 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
694 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
695 ++iDescriptor;
696 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
697 }
698 }
699 return rc;
700}
701
702
703static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
704 uint32_t off, void const *pvData, uint32_t cbData)
705{
706 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
707 off, (void *)pvData, cbData,
708 VMSVGAGboTransferDirection_Write);
709}
710
711
712static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
713 uint32_t off, void *pvData, uint32_t cbData)
714{
715 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
716 off, pvData, cbData,
717 VMSVGAGboTransferDirection_Read);
718}
719
720
721/*
722 *
723 * Object Tables.
724 *
725 */
726
727static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
728 uint32_t idx, uint32_t cbEntry)
729{
730 RT_NOREF(pSvgaR3State);
731
732 /* The table must exist and the index must be within the table. */
733 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
734 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
735 RT_UNTRUSTED_VALIDATED_FENCE();
736 return VINF_SUCCESS;
737}
738
739
740static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
741 uint32_t idx, uint32_t cbEntry,
742 void *pvData, uint32_t cbData)
743{
744 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
745
746 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
747 if (RT_SUCCESS(rc))
748 {
749 uint32_t const off = idx * cbEntry;
750 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
751 }
752 return rc;
753}
754
755static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
756 uint32_t idx, uint32_t cbEntry,
757 void const *pvData, uint32_t cbData)
758{
759 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
760
761 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
762 if (RT_SUCCESS(rc))
763 {
764 uint32_t const off = idx * cbEntry;
765 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
766 }
767 return rc;
768}
769
770
771/*
772 *
773 * The guest's Memory OBjects (MOB).
774 *
775 */
776
777static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
778 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
779 bool fGCPhys64, PVMSVGAMOB pMob)
780{
781 RT_ZERO(*pMob);
782
783 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
784 SVGAOTableMobEntry entry;
785 entry.ptDepth = ptDepth;
786 entry.sizeInBytes = sizeInBytes;
787 entry.base = baseAddress;
788 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
789 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
790 if (RT_SUCCESS(rc))
791 {
792 /* Create the corresponding GBO. */
793 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
794 if (RT_SUCCESS(rc))
795 {
796 /* Add to the tree of known GBOs and the LRU list. */
797 pMob->Core.Key = mobid;
798 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
799 {
800 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
801 return VINF_SUCCESS;
802 }
803
804 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
805 }
806 }
807
808 return rc;
809}
810
811
812static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
813{
814 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
815 SVGAOTableMobEntry entry;
816 RT_ZERO(entry);
817 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
818 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
819
820 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
821 if (pMob)
822 {
823 RTListNodeRemove(&pMob->nodeLRU);
824 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
825 RTMemFree(pMob);
826 return VINF_SUCCESS;
827 }
828
829 return VERR_INVALID_PARAMETER;
830}
831
832
833static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
834{
835 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
836 if (pMob)
837 {
838 /* Move to the head of the LRU list. */
839 RTListNodeRemove(&pMob->nodeLRU);
840 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
841 }
842
843 return pMob;
844}
845
846/*
847 * Screen objects.
848 */
849VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
850{
851 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
852 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
853 && pSVGAState
854 && pSVGAState->aScreens[idScreen].fDefined)
855 {
856 return &pSVGAState->aScreens[idScreen];
857 }
858 return NULL;
859}
860
861void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
862{
863#ifdef VBOX_WITH_VMSVGA3D
864 if (pThis->svga.f3DEnabled)
865 {
866 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
867 {
868 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
869 if (pScreen)
870 vmsvga3dDestroyScreen(pThisCC, pScreen);
871 }
872 }
873#else
874 RT_NOREF(pThis, pThisCC);
875#endif
876}
877
878
879/**
880 * Copy a rectangle of pixels within guest VRAM.
881 */
882static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
883 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
884{
885 if (!width || !height)
886 return; /* Nothing to do, don't even bother. */
887
888 /*
889 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
890 * corresponding to the current display mode.
891 */
892 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
893 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
894 uint8_t const *pSrc;
895 uint8_t *pDst;
896 unsigned const cbRectWidth = width * cbPixel;
897 unsigned uMaxOffset;
898
899 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
900 if (uMaxOffset >= cbFrameBuffer)
901 {
902 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
903 return; /* Just don't listen to a bad guest. */
904 }
905
906 pSrc = pDst = pThisCC->pbVRam;
907 pSrc += srcY * cbScanline + srcX * cbPixel;
908 pDst += dstY * cbScanline + dstX * cbPixel;
909
910 if (srcY >= dstY)
911 {
912 /* Source below destination, copy top to bottom. */
913 for (; height > 0; height--)
914 {
915 memmove(pDst, pSrc, cbRectWidth);
916 pSrc += cbScanline;
917 pDst += cbScanline;
918 }
919 }
920 else
921 {
922 /* Source above destination, copy bottom to top. */
923 pSrc += cbScanline * (height - 1);
924 pDst += cbScanline * (height - 1);
925 for (; height > 0; height--)
926 {
927 memmove(pDst, pSrc, cbRectWidth);
928 pSrc -= cbScanline;
929 pDst -= cbScanline;
930 }
931 }
932}
933
934
935/**
936 * Common worker for changing the pointer shape.
937 *
938 * @param pThisCC The VGA/VMSVGA state for ring-3.
939 * @param pSVGAState The VMSVGA ring-3 instance data.
940 * @param fAlpha Whether there is alpha or not.
941 * @param xHot Hotspot x coordinate.
942 * @param yHot Hotspot y coordinate.
943 * @param cx Width.
944 * @param cy Height.
945 * @param pbData Heap copy of the cursor data. Consumed.
946 * @param cbData The size of the data.
947 */
948static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
949 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
950{
951 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
952#ifdef LOG_ENABLED
953 if (LogIs2Enabled())
954 {
955 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
956 if (!fAlpha)
957 {
958 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
959 for (uint32_t y = 0; y < cy; y++)
960 {
961 Log2(("%3u:", y));
962 uint8_t const *pbLine = &pbData[y * cbAndLine];
963 for (uint32_t x = 0; x < cx; x += 8)
964 {
965 uint8_t b = pbLine[x / 8];
966 char szByte[12];
967 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
968 szByte[1] = b & 0x40 ? '*' : ' ';
969 szByte[2] = b & 0x20 ? '*' : ' ';
970 szByte[3] = b & 0x10 ? '*' : ' ';
971 szByte[4] = b & 0x08 ? '*' : ' ';
972 szByte[5] = b & 0x04 ? '*' : ' ';
973 szByte[6] = b & 0x02 ? '*' : ' ';
974 szByte[7] = b & 0x01 ? '*' : ' ';
975 szByte[8] = '\0';
976 Log2(("%s", szByte));
977 }
978 Log2(("\n"));
979 }
980 }
981
982 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
983 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
984 for (uint32_t y = 0; y < cy; y++)
985 {
986 Log2(("%3u:", y));
987 uint32_t const *pu32Line = &pu32Xor[y * cx];
988 for (uint32_t x = 0; x < cx; x++)
989 Log2((" %08x", pu32Line[x]));
990 Log2(("\n"));
991 }
992 }
993#endif
994
995 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
996 AssertRC(rc);
997
998 if (pSVGAState->Cursor.fActive)
999 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1000
1001 pSVGAState->Cursor.fActive = true;
1002 pSVGAState->Cursor.xHotspot = xHot;
1003 pSVGAState->Cursor.yHotspot = yHot;
1004 pSVGAState->Cursor.width = cx;
1005 pSVGAState->Cursor.height = cy;
1006 pSVGAState->Cursor.cbData = cbData;
1007 pSVGAState->Cursor.pData = pbData;
1008}
1009
1010
1011#ifdef VBOX_WITH_VMSVGA3D
1012
1013/*
1014 * SVGA_3D_CMD_* handlers.
1015 */
1016
1017
1018/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1019 *
1020 * @param pThisCC The VGA/VMSVGA state for the current context.
1021 * @param pCmd The VMSVGA command.
1022 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1023 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1024 */
1025static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1026 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1027{
1028 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1029 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1030 RT_UNTRUSTED_VALIDATED_FENCE();
1031
1032 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1033 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1034 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1035 */
1036 uint32_t cRemainingMipLevels = cMipLevelSizes;
1037 uint32_t cFaces = 0;
1038 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1039 {
1040 if (pCmd->face[i].numMipLevels == 0)
1041 break;
1042
1043 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1044 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1045
1046 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1047 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1048 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1049
1050 ++cFaces;
1051 }
1052 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1053 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1054
1055 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1056 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1057
1058 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1059 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1060 RT_UNTRUSTED_VALIDATED_FENCE();
1061
1062 /* Verify paMipLevelSizes */
1063 uint32_t cWidth = paMipLevelSizes[0].width;
1064 uint32_t cHeight = paMipLevelSizes[0].height;
1065 uint32_t cDepth = paMipLevelSizes[0].depth;
1066 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1067 {
1068 cWidth >>= 1;
1069 if (cWidth == 0) cWidth = 1;
1070 cHeight >>= 1;
1071 if (cHeight == 0) cHeight = 1;
1072 cDepth >>= 1;
1073 if (cDepth == 0) cDepth = 1;
1074 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1075 {
1076 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1077 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1078 && cHeight == paMipLevelSizes[iMipLevelSize].height
1079 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1080 }
1081 }
1082 RT_UNTRUSTED_VALIDATED_FENCE();
1083
1084 /* Create the surface. */
1085 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1086 pCmd->multisampleCount, pCmd->autogenFilter,
1087 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1088}
1089
1090
1091/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1092static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1093{
1094 ASMBreakpoint();
1095 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1096
1097 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1098
1099 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1100 /* Allocate a structure for the MOB. */
1101 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1102 AssertPtrReturnVoid(pMob);
1103
1104 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1105 if (RT_SUCCESS(rc))
1106 {
1107 return;
1108 }
1109
1110 AssertFailed();
1111
1112 RTMemFree(pMob);
1113}
1114
1115
1116/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1117static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1118{
1119// ASMBreakpoint();
1120 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1121
1122 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1123
1124 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1125 if (RT_SUCCESS(rc))
1126 {
1127 return;
1128 }
1129
1130 AssertFailed();
1131}
1132
1133
1134/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1135static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1136{
1137// ASMBreakpoint();
1138 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1139
1140 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1141 SVGAOTableSurfaceEntry entry;
1142 RT_ZERO(entry);
1143 entry.format = pCmd->format;
1144 entry.surface1Flags = pCmd->surfaceFlags;
1145 entry.numMipLevels = pCmd->numMipLevels;
1146 entry.multisampleCount = pCmd->multisampleCount;
1147 entry.autogenFilter = pCmd->autogenFilter;
1148 entry.size = pCmd->size;
1149 entry.mobid = SVGA_ID_INVALID;
1150 // entry.arraySize = 0;
1151 // entry.mobPitch = 0;
1152 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1153 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1154 if (RT_SUCCESS(rc))
1155 {
1156 /* Create the host surface. */
1157 /** @todo fGBO = true flag. */
1158 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1159 pCmd->multisampleCount, pCmd->autogenFilter,
1160 pCmd->numMipLevels, &pCmd->size);
1161 }
1162}
1163
1164
1165/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1166static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1167{
1168// ASMBreakpoint();
1169 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1170
1171 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1172 SVGAOTableSurfaceEntry entry;
1173 RT_ZERO(entry);
1174 entry.mobid = SVGA_ID_INVALID;
1175 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1176 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1177
1178 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1179}
1180
1181
1182/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1183static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1184{
1185// ASMBreakpoint();
1186 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1187 RT_NOREF(pCmd, pSvgaR3State);
1188
1189 /* Assign the mobid to the surface. */
1190 int rc = VINF_SUCCESS;
1191 if (pCmd->mobid != SVGA_ID_INVALID)
1192 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1193 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1194 if (RT_SUCCESS(rc))
1195 {
1196 SVGAOTableSurfaceEntry entry;
1197 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1198 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1199 if (RT_SUCCESS(rc))
1200 {
1201 entry.mobid = pCmd->mobid;
1202 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1203 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1204 if (RT_SUCCESS(rc))
1205 {
1206 /* */
1207 }
1208 }
1209 }
1210}
1211
1212
1213#ifdef DUMP_BITMAPS
1214static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1215{
1216 if (pMap->cbPixel != 4)
1217 return VERR_NOT_SUPPORTED;
1218
1219 int const w = pMap->box.w;
1220 int const h = pMap->box.h;
1221
1222 const int cbBitmap = w * h * 4;
1223
1224 FILE *f = fopen(pszFilename, "wb");
1225 if (!f)
1226 return VERR_FILE_NOT_FOUND;
1227
1228 {
1229 BMPFILEHDR fileHdr;
1230 RT_ZERO(fileHdr);
1231 fileHdr.uType = BMP_HDR_MAGIC;
1232 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1233 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1234
1235 BMPWIN3XINFOHDR coreHdr;
1236 RT_ZERO(coreHdr);
1237 coreHdr.cbSize = sizeof(coreHdr);
1238 coreHdr.uWidth = w;
1239 coreHdr.uHeight = -h;
1240 coreHdr.cPlanes = 1;
1241 coreHdr.cBits = 32;
1242 coreHdr.cbSizeImage = cbBitmap;
1243
1244 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1245 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1246 }
1247
1248 if (pMap->cbPixel == 4)
1249 {
1250 const uint8_t *s = (uint8_t *)pMap->pvData;
1251 for (int32_t y = 0; y < h; ++y)
1252 {
1253 fwrite(s, 1, w * pMap->cbPixel, f);
1254
1255 s += pMap->cbRowPitch;
1256 }
1257 }
1258
1259 fclose(f);
1260
1261 return VINF_SUCCESS;
1262}
1263
1264
1265void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1266{
1267 static int idxBitmap = 0;
1268 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1269 vmsvga3dBmpWrite(pszFilename, pMap);
1270 RTStrFree(pszFilename);
1271}
1272#endif /* DUMP_BITMAPS */
1273
1274
1275/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1276static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1277{
1278// ASMBreakpoint();
1279 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1280
1281 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1282 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1283
1284 /* "update a surface from its backing MOB." */
1285 SVGAOTableSurfaceEntry entrySurface;
1286 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1287 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1288 if (RT_SUCCESS(rc))
1289 {
1290 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1291 if (pMob)
1292 {
1293 VMSVGA3D_MAPPED_SURFACE map;
1294 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1295 if (RT_SUCCESS(rc))
1296 {
1297 /* Copy MOB -> mapped surface. */
1298 uint32_t offSrc = pCmd->box.x * map.cbPixel
1299 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1300 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1301 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1302 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1303 {
1304 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1305 {
1306 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1307 if (RT_FAILURE(rc))
1308 break;
1309
1310 pu8Dst += map.cbRowPitch;
1311 offSrc += entrySurface.size.width * map.cbPixel;
1312 }
1313
1314 pu8Dst += map.cbDepthPitch;
1315 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1316 }
1317
1318 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1319
1320 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1321 }
1322 }
1323 }
1324}
1325
1326
1327/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1328static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1329{
1330// ASMBreakpoint();
1331 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1332 RT_NOREF(pSvgaR3State, pCmd);
1333 /** @todo Implement. */
1334}
1335
1336
1337/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1338static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1339{
1340 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1341
1342 /*
1343 * Create a GBO for the table.
1344 */
1345 PVMSVGAGBO pGbo;
1346 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1347 {
1348 RT_UNTRUSTED_VALIDATED_FENCE();
1349 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1350 }
1351 else
1352 {
1353 ASSERT_GUEST_FAILED();
1354 pGbo = NULL;
1355 }
1356
1357 if (pGbo)
1358 {
1359 /* Recreate. */
1360 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1361 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1362 AssertRC(rc);
1363 }
1364}
1365
1366
1367/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1368static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1369{
1370// ASMBreakpoint();
1371 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1372
1373 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1374 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1375 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1376 RT_UNTRUSTED_VALIDATED_FENCE();
1377
1378 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1379 SVGAOTableScreenTargetEntry entry;
1380 RT_ZERO(entry);
1381 entry.image.sid = SVGA_ID_INVALID;
1382 // entry.image.face = 0;
1383 // entry.image.mipmap = 0;
1384 entry.width = pCmd->width;
1385 entry.height = pCmd->height;
1386 entry.xRoot = pCmd->xRoot;
1387 entry.yRoot = pCmd->yRoot;
1388 entry.flags = pCmd->flags;
1389 entry.dpi = pCmd->dpi;
1390 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1391 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1392 if (RT_SUCCESS(rc))
1393 {
1394 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1395 /** @todo Generic screen object/target interface. */
1396 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1397 pScreen->fDefined = true;
1398 pScreen->fModified = true;
1399 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1400 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1401 pScreen->idScreen = pCmd->stid;
1402
1403 pScreen->xOrigin = pCmd->xRoot;
1404 pScreen->yOrigin = pCmd->yRoot;
1405 pScreen->cWidth = pCmd->width;
1406 pScreen->cHeight = pCmd->height;
1407 pScreen->offVRAM = 0; /* Always for screen targets, they use either a separate memory buffer or a host window. */
1408 pScreen->cbPitch = pCmd->width * 4;
1409 pScreen->cBpp = 32;
1410
1411 if (RT_LIKELY(pThis->svga.f3DEnabled))
1412 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1413
1414 if (!pScreen->pHwScreen)
1415 {
1416 /* System memory buffer. */
1417 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1418 }
1419
1420 pThis->svga.fGFBRegisters = false;
1421 vmsvgaR3ChangeMode(pThis, pThisCC);
1422 }
1423}
1424
1425
1426/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1427static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1428{
1429// ASMBreakpoint();
1430 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1431
1432 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1433 RT_UNTRUSTED_VALIDATED_FENCE();
1434
1435 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1436 SVGAOTableScreenTargetEntry entry;
1437 RT_ZERO(entry);
1438 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1439 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1440 if (RT_SUCCESS(rc))
1441 {
1442 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1443 /** @todo Generic screen object/target interface. */
1444 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1445 pScreen->fModified = true;
1446 pScreen->fDefined = false;
1447 pScreen->idScreen = pCmd->stid;
1448
1449 if (RT_LIKELY(pThis->svga.f3DEnabled))
1450 vmsvga3dDestroyScreen(pThisCC, pScreen);
1451
1452 vmsvgaR3ChangeMode(pThis, pThisCC);
1453
1454 RTMemFree(pScreen->pvScreenBitmap);
1455 pScreen->pvScreenBitmap = NULL;
1456 }
1457}
1458
1459
1460/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1461static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1462{
1463// ASMBreakpoint();
1464 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1465
1466 /* "Binding a surface to a Screen Target the same as flipping" */
1467
1468 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1469 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1470 RT_UNTRUSTED_VALIDATED_FENCE();
1471
1472 /* Assign the surface to the screen target. */
1473 int rc = VINF_SUCCESS;
1474 if (pCmd->image.sid != SVGA_ID_INVALID)
1475 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1476 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1477 if (RT_SUCCESS(rc))
1478 {
1479 SVGAOTableScreenTargetEntry entry;
1480 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1481 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1482 if (RT_SUCCESS(rc))
1483 {
1484 entry.image = pCmd->image;
1485 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1486 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1487 if (RT_SUCCESS(rc))
1488 {
1489 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1490 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1491 AssertRC(rc);
1492 }
1493 }
1494 }
1495}
1496
1497
1498/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1499static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1500{
1501// ASMBreakpoint();
1502 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1503
1504 /* Update the screen target from its backing surface. */
1505 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1506 RT_UNTRUSTED_VALIDATED_FENCE();
1507
1508 /* Get the screen target info. */
1509 SVGAOTableScreenTargetEntry entryScreenTarget;
1510 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1511 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1512 if (RT_SUCCESS(rc))
1513 {
1514 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1515 RT_UNTRUSTED_VALIDATED_FENCE();
1516
1517 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1518 {
1519 SVGAOTableSurfaceEntry entrySurface;
1520 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1521 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1522 if (RT_SUCCESS(rc))
1523 {
1524 /* Copy entrySurface.mobid content to the screen target. */
1525 if (entrySurface.mobid != SVGA_ID_INVALID)
1526 {
1527 RT_UNTRUSTED_VALIDATED_FENCE();
1528 SVGA3dRect targetRect = pCmd->rect;
1529
1530 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1531 if (pScreen->pHwScreen)
1532 {
1533 /* Copy the screen target surface to the backend's screen. */
1534 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1535 }
1536 else if (pScreen->pvScreenBitmap)
1537 {
1538 /* Copy the screen target surface to the memory buffer. */
1539 VMSVGA3D_MAPPED_SURFACE map;
1540 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1541 if (RT_SUCCESS(rc))
1542 {
1543 uint8_t const *pu8Src = (uint8_t *)map.pvData
1544 + targetRect.x * map.cbPixel
1545 + targetRect.y * map.cbRowPitch;
1546 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1547 + targetRect.x * map.cbPixel
1548 + targetRect.y * map.box.w * map.cbPixel;
1549 for (uint32_t y = 0; y < targetRect.h; ++y)
1550 {
1551 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1552
1553 pu8Src += map.cbRowPitch;
1554 pu8Dst += map.box.w * map.cbPixel;
1555 }
1556
1557 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1558
1559 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1560 }
1561 else
1562 AssertFailed();
1563 }
1564 }
1565 }
1566 }
1567 }
1568}
1569
1570
1571/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1572static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1573{
1574// ASMBreakpoint();
1575 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1576
1577 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1578
1579 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1580 /* Allocate a structure for the MOB. */
1581 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1582 AssertPtrReturnVoid(pMob);
1583
1584 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1585 if (RT_SUCCESS(rc))
1586 {
1587 return;
1588 }
1589
1590 RTMemFree(pMob);
1591}
1592
1593
1594/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1595static void vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd)
1596{
1597ASMBreakpoint();
1598 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1599 if (pSvgaR3State->pFuncsDX)
1600 {
1601 RT_NOREF(pCmd);
1602 pSvgaR3State->pFuncsDX->pfnDXDefineContext(pThisCC->svga.p3dState);
1603 }
1604}
1605
1606
1607/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1608static void vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd)
1609{
1610ASMBreakpoint();
1611 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1612 if (pSvgaR3State->pFuncsDX)
1613 {
1614 RT_NOREF(pCmd);
1615 pSvgaR3State->pFuncsDX->pfnDXDestroyContext(pThisCC->svga.p3dState);
1616 }
1617}
1618
1619
1620/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1621static void vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd)
1622{
1623ASMBreakpoint();
1624 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1625 if (pSvgaR3State->pFuncsDX)
1626 {
1627 RT_NOREF(pCmd);
1628 pSvgaR3State->pFuncsDX->pfnDXBindContext(pThisCC->svga.p3dState);
1629 }
1630}
1631
1632
1633/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1634static void vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd)
1635{
1636ASMBreakpoint();
1637 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1638 if (pSvgaR3State->pFuncsDX)
1639 {
1640 RT_NOREF(pCmd);
1641 pSvgaR3State->pFuncsDX->pfnDXReadbackContext(pThisCC->svga.p3dState);
1642 }
1643}
1644
1645
1646/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1647static void vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateContext const *pCmd)
1648{
1649ASMBreakpoint();
1650 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1651 if (pSvgaR3State->pFuncsDX)
1652 {
1653 RT_NOREF(pCmd);
1654 pSvgaR3State->pFuncsDX->pfnDXInvalidateContext(pThisCC->svga.p3dState);
1655 }
1656}
1657
1658
1659/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1660static void vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd)
1661{
1662ASMBreakpoint();
1663 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1664 if (pSvgaR3State->pFuncsDX)
1665 {
1666 RT_NOREF(pCmd);
1667 pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer(pThisCC->svga.p3dState);
1668 }
1669}
1670
1671
1672/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
1673static void vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, SVGA3dCmdDXSetShaderResources const *pCmd)
1674{
1675ASMBreakpoint();
1676 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1677 if (pSvgaR3State->pFuncsDX)
1678 {
1679 RT_NOREF(pCmd);
1680 pSvgaR3State->pFuncsDX->pfnDXSetShaderResources(pThisCC->svga.p3dState);
1681 }
1682}
1683
1684
1685/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
1686static void vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, SVGA3dCmdDXSetShader const *pCmd)
1687{
1688ASMBreakpoint();
1689 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1690 if (pSvgaR3State->pFuncsDX)
1691 {
1692 RT_NOREF(pCmd);
1693 pSvgaR3State->pFuncsDX->pfnDXSetShader(pThisCC->svga.p3dState);
1694 }
1695}
1696
1697
1698/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
1699static void vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, SVGA3dCmdDXSetSamplers const *pCmd)
1700{
1701ASMBreakpoint();
1702 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1703 if (pSvgaR3State->pFuncsDX)
1704 {
1705 RT_NOREF(pCmd);
1706 pSvgaR3State->pFuncsDX->pfnDXSetSamplers(pThisCC->svga.p3dState);
1707 }
1708}
1709
1710
1711/* SVGA_3D_CMD_DX_DRAW 1152 */
1712static void vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, SVGA3dCmdDXDraw const *pCmd)
1713{
1714ASMBreakpoint();
1715 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1716 if (pSvgaR3State->pFuncsDX)
1717 {
1718 RT_NOREF(pCmd);
1719 pSvgaR3State->pFuncsDX->pfnDXDraw(pThisCC->svga.p3dState);
1720 }
1721}
1722
1723
1724/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
1725static void vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexed const *pCmd)
1726{
1727ASMBreakpoint();
1728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1729 if (pSvgaR3State->pFuncsDX)
1730 {
1731 RT_NOREF(pCmd);
1732 pSvgaR3State->pFuncsDX->pfnDXDrawIndexed(pThisCC->svga.p3dState);
1733 }
1734}
1735
1736
1737/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
1738static void vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, SVGA3dCmdDXDrawInstanced const *pCmd)
1739{
1740ASMBreakpoint();
1741 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1742 if (pSvgaR3State->pFuncsDX)
1743 {
1744 RT_NOREF(pCmd);
1745 pSvgaR3State->pFuncsDX->pfnDXDrawInstanced(pThisCC->svga.p3dState);
1746 }
1747}
1748
1749
1750/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
1751static void vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexedInstanced const *pCmd)
1752{
1753ASMBreakpoint();
1754 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1755 if (pSvgaR3State->pFuncsDX)
1756 {
1757 RT_NOREF(pCmd);
1758 pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstanced(pThisCC->svga.p3dState);
1759 }
1760}
1761
1762
1763/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
1764static void vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, SVGA3dCmdDXDrawAuto const *pCmd)
1765{
1766ASMBreakpoint();
1767 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1768 if (pSvgaR3State->pFuncsDX)
1769 {
1770 RT_NOREF(pCmd);
1771 pSvgaR3State->pFuncsDX->pfnDXDrawAuto(pThisCC->svga.p3dState);
1772 }
1773}
1774
1775
1776/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
1777static void vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, SVGA3dCmdDXSetInputLayout const *pCmd)
1778{
1779ASMBreakpoint();
1780 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1781 if (pSvgaR3State->pFuncsDX)
1782 {
1783 RT_NOREF(pCmd);
1784 pSvgaR3State->pFuncsDX->pfnDXSetInputLayout(pThisCC->svga.p3dState);
1785 }
1786}
1787
1788
1789/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
1790static void vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, SVGA3dCmdDXSetVertexBuffers const *pCmd)
1791{
1792ASMBreakpoint();
1793 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1794 if (pSvgaR3State->pFuncsDX)
1795 {
1796 RT_NOREF(pCmd);
1797 pSvgaR3State->pFuncsDX->pfnDXSetVertexBuffers(pThisCC->svga.p3dState);
1798 }
1799}
1800
1801
1802/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
1803static void vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXSetIndexBuffer const *pCmd)
1804{
1805ASMBreakpoint();
1806 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1807 if (pSvgaR3State->pFuncsDX)
1808 {
1809 RT_NOREF(pCmd);
1810 pSvgaR3State->pFuncsDX->pfnDXSetIndexBuffer(pThisCC->svga.p3dState);
1811 }
1812}
1813
1814
1815/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
1816static void vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, SVGA3dCmdDXSetTopology const *pCmd)
1817{
1818ASMBreakpoint();
1819 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1820 if (pSvgaR3State->pFuncsDX)
1821 {
1822 RT_NOREF(pCmd);
1823 pSvgaR3State->pFuncsDX->pfnDXSetTopology(pThisCC->svga.p3dState);
1824 }
1825}
1826
1827
1828/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
1829static void vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, SVGA3dCmdDXSetRenderTargets const *pCmd)
1830{
1831ASMBreakpoint();
1832 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1833 if (pSvgaR3State->pFuncsDX)
1834 {
1835 RT_NOREF(pCmd);
1836 pSvgaR3State->pFuncsDX->pfnDXSetRenderTargets(pThisCC->svga.p3dState);
1837 }
1838}
1839
1840
1841/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
1842static void vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXSetBlendState const *pCmd)
1843{
1844ASMBreakpoint();
1845 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1846 if (pSvgaR3State->pFuncsDX)
1847 {
1848 RT_NOREF(pCmd);
1849 pSvgaR3State->pFuncsDX->pfnDXSetBlendState(pThisCC->svga.p3dState);
1850 }
1851}
1852
1853
1854/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
1855static void vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXSetDepthStencilState const *pCmd)
1856{
1857ASMBreakpoint();
1858 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1859 if (pSvgaR3State->pFuncsDX)
1860 {
1861 RT_NOREF(pCmd);
1862 pSvgaR3State->pFuncsDX->pfnDXSetDepthStencilState(pThisCC->svga.p3dState);
1863 }
1864}
1865
1866
1867/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
1868static void vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXSetRasterizerState const *pCmd)
1869{
1870ASMBreakpoint();
1871 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1872 if (pSvgaR3State->pFuncsDX)
1873 {
1874 RT_NOREF(pCmd);
1875 pSvgaR3State->pFuncsDX->pfnDXSetRasterizerState(pThisCC->svga.p3dState);
1876 }
1877}
1878
1879
1880/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
1881static void vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, SVGA3dCmdDXDefineQuery const *pCmd)
1882{
1883ASMBreakpoint();
1884 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1885 if (pSvgaR3State->pFuncsDX)
1886 {
1887 RT_NOREF(pCmd);
1888 pSvgaR3State->pFuncsDX->pfnDXDefineQuery(pThisCC->svga.p3dState);
1889 }
1890}
1891
1892
1893/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
1894static void vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyQuery const *pCmd)
1895{
1896ASMBreakpoint();
1897 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1898 if (pSvgaR3State->pFuncsDX)
1899 {
1900 RT_NOREF(pCmd);
1901 pSvgaR3State->pFuncsDX->pfnDXDestroyQuery(pThisCC->svga.p3dState);
1902 }
1903}
1904
1905
1906/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
1907static void vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBindQuery const *pCmd)
1908{
1909ASMBreakpoint();
1910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1911 if (pSvgaR3State->pFuncsDX)
1912 {
1913 RT_NOREF(pCmd);
1914 pSvgaR3State->pFuncsDX->pfnDXBindQuery(pThisCC->svga.p3dState);
1915 }
1916}
1917
1918
1919/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
1920static void vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetQueryOffset const *pCmd)
1921{
1922ASMBreakpoint();
1923 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1924 if (pSvgaR3State->pFuncsDX)
1925 {
1926 RT_NOREF(pCmd);
1927 pSvgaR3State->pFuncsDX->pfnDXSetQueryOffset(pThisCC->svga.p3dState);
1928 }
1929}
1930
1931
1932/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
1933static void vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBeginQuery const *pCmd)
1934{
1935ASMBreakpoint();
1936 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1937 if (pSvgaR3State->pFuncsDX)
1938 {
1939 RT_NOREF(pCmd);
1940 pSvgaR3State->pFuncsDX->pfnDXBeginQuery(pThisCC->svga.p3dState);
1941 }
1942}
1943
1944
1945/* SVGA_3D_CMD_DX_END_QUERY 1170 */
1946static void vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, SVGA3dCmdDXEndQuery const *pCmd)
1947{
1948ASMBreakpoint();
1949 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1950 if (pSvgaR3State->pFuncsDX)
1951 {
1952 RT_NOREF(pCmd);
1953 pSvgaR3State->pFuncsDX->pfnDXEndQuery(pThisCC->svga.p3dState);
1954 }
1955}
1956
1957
1958/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
1959static void vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackQuery const *pCmd)
1960{
1961ASMBreakpoint();
1962 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1963 if (pSvgaR3State->pFuncsDX)
1964 {
1965 RT_NOREF(pCmd);
1966 pSvgaR3State->pFuncsDX->pfnDXReadbackQuery(pThisCC->svga.p3dState);
1967 }
1968}
1969
1970
1971/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
1972static void vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, SVGA3dCmdDXSetPredication const *pCmd)
1973{
1974ASMBreakpoint();
1975 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1976 if (pSvgaR3State->pFuncsDX)
1977 {
1978 RT_NOREF(pCmd);
1979 pSvgaR3State->pFuncsDX->pfnDXSetPredication(pThisCC->svga.p3dState);
1980 }
1981}
1982
1983
1984/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
1985static void vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, SVGA3dCmdDXSetSOTargets const *pCmd)
1986{
1987ASMBreakpoint();
1988 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1989 if (pSvgaR3State->pFuncsDX)
1990 {
1991 RT_NOREF(pCmd);
1992 pSvgaR3State->pFuncsDX->pfnDXSetSOTargets(pThisCC->svga.p3dState);
1993 }
1994}
1995
1996
1997/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
1998static void vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, SVGA3dCmdDXSetViewports const *pCmd)
1999{
2000ASMBreakpoint();
2001 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2002 if (pSvgaR3State->pFuncsDX)
2003 {
2004 RT_NOREF(pCmd);
2005 pSvgaR3State->pFuncsDX->pfnDXSetViewports(pThisCC->svga.p3dState);
2006 }
2007}
2008
2009
2010/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2011static void vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, SVGA3dCmdDXSetScissorRects const *pCmd)
2012{
2013ASMBreakpoint();
2014 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2015 if (pSvgaR3State->pFuncsDX)
2016 {
2017 RT_NOREF(pCmd);
2018 pSvgaR3State->pFuncsDX->pfnDXSetScissorRects(pThisCC->svga.p3dState);
2019 }
2020}
2021
2022
2023/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2024static void vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXClearRenderTargetView const *pCmd)
2025{
2026ASMBreakpoint();
2027 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2028 if (pSvgaR3State->pFuncsDX)
2029 {
2030 RT_NOREF(pCmd);
2031 pSvgaR3State->pFuncsDX->pfnDXClearRenderTargetView(pThisCC->svga.p3dState);
2032 }
2033}
2034
2035
2036/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2037static void vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXClearDepthStencilView const *pCmd)
2038{
2039ASMBreakpoint();
2040 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2041 if (pSvgaR3State->pFuncsDX)
2042 {
2043 RT_NOREF(pCmd);
2044 pSvgaR3State->pFuncsDX->pfnDXClearDepthStencilView(pThisCC->svga.p3dState);
2045 }
2046}
2047
2048
2049/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2050static void vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, SVGA3dCmdDXPredCopyRegion const *pCmd)
2051{
2052ASMBreakpoint();
2053 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2054 if (pSvgaR3State->pFuncsDX)
2055 {
2056 RT_NOREF(pCmd);
2057 pSvgaR3State->pFuncsDX->pfnDXPredCopyRegion(pThisCC->svga.p3dState);
2058 }
2059}
2060
2061
2062/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2063static void vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, SVGA3dCmdDXPredCopy const *pCmd)
2064{
2065ASMBreakpoint();
2066 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2067 if (pSvgaR3State->pFuncsDX)
2068 {
2069 RT_NOREF(pCmd);
2070 pSvgaR3State->pFuncsDX->pfnDXPredCopy(pThisCC->svga.p3dState);
2071 }
2072}
2073
2074
2075/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2076static void vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, SVGA3dCmdDXPresentBlt const *pCmd)
2077{
2078ASMBreakpoint();
2079 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2080 if (pSvgaR3State->pFuncsDX)
2081 {
2082 RT_NOREF(pCmd);
2083 pSvgaR3State->pFuncsDX->pfnDXPresentBlt(pThisCC->svga.p3dState);
2084 }
2085}
2086
2087
2088/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2089static void vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, SVGA3dCmdDXGenMips const *pCmd)
2090{
2091ASMBreakpoint();
2092 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2093 if (pSvgaR3State->pFuncsDX)
2094 {
2095 RT_NOREF(pCmd);
2096 pSvgaR3State->pFuncsDX->pfnDXGenMips(pThisCC->svga.p3dState);
2097 }
2098}
2099
2100
2101/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2102static void vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd)
2103{
2104ASMBreakpoint();
2105 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2106 if (pSvgaR3State->pFuncsDX)
2107 {
2108 RT_NOREF(pCmd);
2109 pSvgaR3State->pFuncsDX->pfnDXUpdateSubResource(pThisCC->svga.p3dState);
2110 }
2111}
2112
2113
2114/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2115static void vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd)
2116{
2117ASMBreakpoint();
2118 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2119 if (pSvgaR3State->pFuncsDX)
2120 {
2121 RT_NOREF(pCmd);
2122 pSvgaR3State->pFuncsDX->pfnDXReadbackSubResource(pThisCC->svga.p3dState);
2123 }
2124}
2125
2126
2127/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2128static void vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd)
2129{
2130ASMBreakpoint();
2131 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2132 if (pSvgaR3State->pFuncsDX)
2133 {
2134 RT_NOREF(pCmd);
2135 pSvgaR3State->pFuncsDX->pfnDXInvalidateSubResource(pThisCC->svga.p3dState);
2136 }
2137}
2138
2139
2140/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2141static void vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineShaderResourceView const *pCmd)
2142{
2143ASMBreakpoint();
2144 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2145 if (pSvgaR3State->pFuncsDX)
2146 {
2147 RT_NOREF(pCmd);
2148 pSvgaR3State->pFuncsDX->pfnDXDefineShaderResourceView(pThisCC->svga.p3dState);
2149 }
2150}
2151
2152
2153/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2154static void vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyShaderResourceView const *pCmd)
2155{
2156ASMBreakpoint();
2157 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2158 if (pSvgaR3State->pFuncsDX)
2159 {
2160 RT_NOREF(pCmd);
2161 pSvgaR3State->pFuncsDX->pfnDXDestroyShaderResourceView(pThisCC->svga.p3dState);
2162 }
2163}
2164
2165
2166/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2167static void vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineRenderTargetView const *pCmd)
2168{
2169ASMBreakpoint();
2170 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2171 if (pSvgaR3State->pFuncsDX)
2172 {
2173 RT_NOREF(pCmd);
2174 pSvgaR3State->pFuncsDX->pfnDXDefineRenderTargetView(pThisCC->svga.p3dState);
2175 }
2176}
2177
2178
2179/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2180static void vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyRenderTargetView const *pCmd)
2181{
2182ASMBreakpoint();
2183 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2184 if (pSvgaR3State->pFuncsDX)
2185 {
2186 RT_NOREF(pCmd);
2187 pSvgaR3State->pFuncsDX->pfnDXDestroyRenderTargetView(pThisCC->svga.p3dState);
2188 }
2189}
2190
2191
2192/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2193static void vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilView const *pCmd)
2194{
2195ASMBreakpoint();
2196 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2197 if (pSvgaR3State->pFuncsDX)
2198 {
2199 RT_NOREF(pCmd);
2200 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView(pThisCC->svga.p3dState);
2201 }
2202}
2203
2204
2205/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2206static void vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyDepthStencilView const *pCmd)
2207{
2208ASMBreakpoint();
2209 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2210 if (pSvgaR3State->pFuncsDX)
2211 {
2212 RT_NOREF(pCmd);
2213 pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilView(pThisCC->svga.p3dState);
2214 }
2215}
2216
2217
2218/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2219static void vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, SVGA3dCmdDXDefineElementLayout const *pCmd)
2220{
2221ASMBreakpoint();
2222 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2223 if (pSvgaR3State->pFuncsDX)
2224 {
2225 RT_NOREF(pCmd);
2226 pSvgaR3State->pFuncsDX->pfnDXDefineElementLayout(pThisCC->svga.p3dState);
2227 }
2228}
2229
2230
2231/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2232static void vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyElementLayout const *pCmd)
2233{
2234ASMBreakpoint();
2235 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2236 if (pSvgaR3State->pFuncsDX)
2237 {
2238 RT_NOREF(pCmd);
2239 pSvgaR3State->pFuncsDX->pfnDXDestroyElementLayout(pThisCC->svga.p3dState);
2240 }
2241}
2242
2243
2244/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2245static void vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineBlendState const *pCmd)
2246{
2247ASMBreakpoint();
2248 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2249 if (pSvgaR3State->pFuncsDX)
2250 {
2251 RT_NOREF(pCmd);
2252 pSvgaR3State->pFuncsDX->pfnDXDefineBlendState(pThisCC->svga.p3dState);
2253 }
2254}
2255
2256
2257/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2258static void vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyBlendState const *pCmd)
2259{
2260ASMBreakpoint();
2261 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2262 if (pSvgaR3State->pFuncsDX)
2263 {
2264 RT_NOREF(pCmd);
2265 pSvgaR3State->pFuncsDX->pfnDXDestroyBlendState(pThisCC->svga.p3dState);
2266 }
2267}
2268
2269
2270/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2271static void vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilState const *pCmd)
2272{
2273ASMBreakpoint();
2274 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2275 if (pSvgaR3State->pFuncsDX)
2276 {
2277 RT_NOREF(pCmd);
2278 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilState(pThisCC->svga.p3dState);
2279 }
2280}
2281
2282
2283/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2284static void vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyDepthStencilState const *pCmd)
2285{
2286ASMBreakpoint();
2287 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2288 if (pSvgaR3State->pFuncsDX)
2289 {
2290 RT_NOREF(pCmd);
2291 pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilState(pThisCC->svga.p3dState);
2292 }
2293}
2294
2295
2296/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2297static void vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineRasterizerState const *pCmd)
2298{
2299ASMBreakpoint();
2300 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2301 if (pSvgaR3State->pFuncsDX)
2302 {
2303 RT_NOREF(pCmd);
2304 pSvgaR3State->pFuncsDX->pfnDXDefineRasterizerState(pThisCC->svga.p3dState);
2305 }
2306}
2307
2308
2309/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2310static void vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyRasterizerState const *pCmd)
2311{
2312ASMBreakpoint();
2313 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2314 if (pSvgaR3State->pFuncsDX)
2315 {
2316 RT_NOREF(pCmd);
2317 pSvgaR3State->pFuncsDX->pfnDXDestroyRasterizerState(pThisCC->svga.p3dState);
2318 }
2319}
2320
2321
2322/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2323static void vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineSamplerState const *pCmd)
2324{
2325ASMBreakpoint();
2326 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2327 if (pSvgaR3State->pFuncsDX)
2328 {
2329 RT_NOREF(pCmd);
2330 pSvgaR3State->pFuncsDX->pfnDXDefineSamplerState(pThisCC->svga.p3dState);
2331 }
2332}
2333
2334
2335/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2336static void vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroySamplerState const *pCmd)
2337{
2338ASMBreakpoint();
2339 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2340 if (pSvgaR3State->pFuncsDX)
2341 {
2342 RT_NOREF(pCmd);
2343 pSvgaR3State->pFuncsDX->pfnDXDestroySamplerState(pThisCC->svga.p3dState);
2344 }
2345}
2346
2347
2348/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2349static void vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, SVGA3dCmdDXDefineShader const *pCmd)
2350{
2351ASMBreakpoint();
2352 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2353 if (pSvgaR3State->pFuncsDX)
2354 {
2355 RT_NOREF(pCmd);
2356 pSvgaR3State->pFuncsDX->pfnDXDefineShader(pThisCC->svga.p3dState);
2357 }
2358}
2359
2360
2361/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2362static void vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyShader const *pCmd)
2363{
2364ASMBreakpoint();
2365 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2366 if (pSvgaR3State->pFuncsDX)
2367 {
2368 RT_NOREF(pCmd);
2369 pSvgaR3State->pFuncsDX->pfnDXDestroyShader(pThisCC->svga.p3dState);
2370 }
2371}
2372
2373
2374/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2375static void vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, SVGA3dCmdDXBindShader const *pCmd)
2376{
2377ASMBreakpoint();
2378 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2379 if (pSvgaR3State->pFuncsDX)
2380 {
2381 RT_NOREF(pCmd);
2382 pSvgaR3State->pFuncsDX->pfnDXBindShader(pThisCC->svga.p3dState);
2383 }
2384}
2385
2386
2387/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2388static void vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXDefineStreamOutput const *pCmd)
2389{
2390ASMBreakpoint();
2391 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2392 if (pSvgaR3State->pFuncsDX)
2393 {
2394 RT_NOREF(pCmd);
2395 pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutput(pThisCC->svga.p3dState);
2396 }
2397}
2398
2399
2400/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2401static void vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyStreamOutput const *pCmd)
2402{
2403ASMBreakpoint();
2404 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2405 if (pSvgaR3State->pFuncsDX)
2406 {
2407 RT_NOREF(pCmd);
2408 pSvgaR3State->pFuncsDX->pfnDXDestroyStreamOutput(pThisCC->svga.p3dState);
2409 }
2410}
2411
2412
2413/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2414static void vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXSetStreamOutput const *pCmd)
2415{
2416ASMBreakpoint();
2417 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2418 if (pSvgaR3State->pFuncsDX)
2419 {
2420 RT_NOREF(pCmd);
2421 pSvgaR3State->pFuncsDX->pfnDXSetStreamOutput(pThisCC->svga.p3dState);
2422 }
2423}
2424
2425
2426/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2427static void vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd)
2428{
2429ASMBreakpoint();
2430 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2431 if (pSvgaR3State->pFuncsDX)
2432 {
2433 RT_NOREF(pCmd);
2434 pSvgaR3State->pFuncsDX->pfnDXSetCOTable(pThisCC->svga.p3dState);
2435 }
2436}
2437
2438
2439/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2440static void vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackCOTable const *pCmd)
2441{
2442ASMBreakpoint();
2443 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2444 if (pSvgaR3State->pFuncsDX)
2445 {
2446 RT_NOREF(pCmd);
2447 pSvgaR3State->pFuncsDX->pfnDXReadbackCOTable(pThisCC->svga.p3dState);
2448 }
2449}
2450
2451
2452/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2453static void vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, SVGA3dCmdDXBufferCopy const *pCmd)
2454{
2455ASMBreakpoint();
2456 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2457 if (pSvgaR3State->pFuncsDX)
2458 {
2459 RT_NOREF(pCmd);
2460 pSvgaR3State->pFuncsDX->pfnDXBufferCopy(pThisCC->svga.p3dState);
2461 }
2462}
2463
2464
2465/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2466static void vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd)
2467{
2468ASMBreakpoint();
2469 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2470 if (pSvgaR3State->pFuncsDX)
2471 {
2472 RT_NOREF(pCmd);
2473 pSvgaR3State->pFuncsDX->pfnDXTransferFromBuffer(pThisCC->svga.p3dState);
2474 }
2475}
2476
2477
2478/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2479static void vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd)
2480{
2481ASMBreakpoint();
2482 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2483 if (pSvgaR3State->pFuncsDX)
2484 {
2485 RT_NOREF(pCmd);
2486 pSvgaR3State->pFuncsDX->pfnDXSurfaceCopyAndReadback(pThisCC->svga.p3dState);
2487 }
2488}
2489
2490
2491/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2492static void vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, SVGA3dCmdDXMoveQuery const *pCmd)
2493{
2494ASMBreakpoint();
2495 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2496 if (pSvgaR3State->pFuncsDX)
2497 {
2498 RT_NOREF(pCmd);
2499 pSvgaR3State->pFuncsDX->pfnDXMoveQuery(pThisCC->svga.p3dState);
2500 }
2501}
2502
2503
2504/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2505static void vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBindAllQuery const *pCmd)
2506{
2507ASMBreakpoint();
2508 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2509 if (pSvgaR3State->pFuncsDX)
2510 {
2511 RT_NOREF(pCmd);
2512 pSvgaR3State->pFuncsDX->pfnDXBindAllQuery(pThisCC->svga.p3dState);
2513 }
2514}
2515
2516
2517/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2518static void vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackAllQuery const *pCmd)
2519{
2520ASMBreakpoint();
2521 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2522 if (pSvgaR3State->pFuncsDX)
2523 {
2524 RT_NOREF(pCmd);
2525 pSvgaR3State->pFuncsDX->pfnDXReadbackAllQuery(pThisCC->svga.p3dState);
2526 }
2527}
2528
2529
2530/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2531static void vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXPredTransferFromBuffer const *pCmd)
2532{
2533ASMBreakpoint();
2534 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2535 if (pSvgaR3State->pFuncsDX)
2536 {
2537 RT_NOREF(pCmd);
2538 pSvgaR3State->pFuncsDX->pfnDXPredTransferFromBuffer(pThisCC->svga.p3dState);
2539 }
2540}
2541
2542
2543/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
2544static void vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd)
2545{
2546ASMBreakpoint();
2547 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2548 if (pSvgaR3State->pFuncsDX)
2549 {
2550 RT_NOREF(pCmd);
2551 pSvgaR3State->pFuncsDX->pfnDXMobFence64(pThisCC->svga.p3dState);
2552 }
2553}
2554
2555
2556/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
2557static void vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, SVGA3dCmdDXBindAllShader const *pCmd)
2558{
2559ASMBreakpoint();
2560 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2561 if (pSvgaR3State->pFuncsDX)
2562 {
2563 RT_NOREF(pCmd);
2564 pSvgaR3State->pFuncsDX->pfnDXBindAllShader(pThisCC->svga.p3dState);
2565 }
2566}
2567
2568
2569/* SVGA_3D_CMD_DX_HINT 1218 */
2570static void vmsvga3dCmdDXHint(PVGASTATECC pThisCC, SVGA3dCmdDXHint const *pCmd)
2571{
2572ASMBreakpoint();
2573 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2574 if (pSvgaR3State->pFuncsDX)
2575 {
2576 RT_NOREF(pCmd);
2577 pSvgaR3State->pFuncsDX->pfnDXHint(pThisCC->svga.p3dState);
2578 }
2579}
2580
2581
2582/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
2583static void vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, SVGA3dCmdDXBufferUpdate const *pCmd)
2584{
2585ASMBreakpoint();
2586 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2587 if (pSvgaR3State->pFuncsDX)
2588 {
2589 RT_NOREF(pCmd);
2590 pSvgaR3State->pFuncsDX->pfnDXBufferUpdate(pThisCC->svga.p3dState);
2591 }
2592}
2593
2594
2595/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
2596static void vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd)
2597{
2598ASMBreakpoint();
2599 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2600 if (pSvgaR3State->pFuncsDX)
2601 {
2602 RT_NOREF(pCmd);
2603 pSvgaR3State->pFuncsDX->pfnDXSetVSConstantBufferOffset(pThisCC->svga.p3dState);
2604 }
2605}
2606
2607
2608/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
2609static void vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd)
2610{
2611ASMBreakpoint();
2612 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2613 if (pSvgaR3State->pFuncsDX)
2614 {
2615 RT_NOREF(pCmd);
2616 pSvgaR3State->pFuncsDX->pfnDXSetPSConstantBufferOffset(pThisCC->svga.p3dState);
2617 }
2618}
2619
2620
2621/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
2622static void vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd)
2623{
2624ASMBreakpoint();
2625 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2626 if (pSvgaR3State->pFuncsDX)
2627 {
2628 RT_NOREF(pCmd);
2629 pSvgaR3State->pFuncsDX->pfnDXSetGSConstantBufferOffset(pThisCC->svga.p3dState);
2630 }
2631}
2632
2633
2634/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
2635static void vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd)
2636{
2637ASMBreakpoint();
2638 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2639 if (pSvgaR3State->pFuncsDX)
2640 {
2641 RT_NOREF(pCmd);
2642 pSvgaR3State->pFuncsDX->pfnDXSetHSConstantBufferOffset(pThisCC->svga.p3dState);
2643 }
2644}
2645
2646
2647/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
2648static void vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd)
2649{
2650ASMBreakpoint();
2651 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2652 if (pSvgaR3State->pFuncsDX)
2653 {
2654 RT_NOREF(pCmd);
2655 pSvgaR3State->pFuncsDX->pfnDXSetDSConstantBufferOffset(pThisCC->svga.p3dState);
2656 }
2657}
2658
2659
2660/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
2661static void vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd)
2662{
2663ASMBreakpoint();
2664 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2665 if (pSvgaR3State->pFuncsDX)
2666 {
2667 RT_NOREF(pCmd);
2668 pSvgaR3State->pFuncsDX->pfnDXSetCSConstantBufferOffset(pThisCC->svga.p3dState);
2669 }
2670}
2671
2672
2673/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
2674static void vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, SVGA3dCmdDXCondBindAllShader const *pCmd)
2675{
2676ASMBreakpoint();
2677 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2678 if (pSvgaR3State->pFuncsDX)
2679 {
2680 RT_NOREF(pCmd);
2681 pSvgaR3State->pFuncsDX->pfnDXCondBindAllShader(pThisCC->svga.p3dState);
2682 }
2683}
2684
2685
2686/* SVGA_3D_CMD_SCREEN_COPY 1227 */
2687static void vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, SVGA3dCmdScreenCopy const *pCmd)
2688{
2689ASMBreakpoint();
2690 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2691 if (pSvgaR3State->pFuncsDX)
2692 {
2693 RT_NOREF(pCmd);
2694 pSvgaR3State->pFuncsDX->pfnScreenCopy(pThisCC->svga.p3dState);
2695 }
2696}
2697
2698
2699/* SVGA_3D_CMD_GROW_OTABLE 1236 */
2700static void vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd)
2701{
2702ASMBreakpoint();
2703 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2704 if (pSvgaR3State->pFuncsDX)
2705 {
2706 RT_NOREF(pCmd);
2707 pSvgaR3State->pFuncsDX->pfnGrowOTable(pThisCC->svga.p3dState);
2708 }
2709}
2710
2711
2712/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
2713static void vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd)
2714{
2715ASMBreakpoint();
2716 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2717 if (pSvgaR3State->pFuncsDX)
2718 {
2719 RT_NOREF(pCmd);
2720 pSvgaR3State->pFuncsDX->pfnDXGrowCOTable(pThisCC->svga.p3dState);
2721 }
2722}
2723
2724
2725/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
2726static void vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdIntraSurfaceCopy const *pCmd)
2727{
2728ASMBreakpoint();
2729 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2730 if (pSvgaR3State->pFuncsDX)
2731 {
2732 RT_NOREF(pCmd);
2733 pSvgaR3State->pFuncsDX->pfnIntraSurfaceCopy(pThisCC->svga.p3dState);
2734 }
2735}
2736
2737
2738/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
2739static void vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
2740{
2741ASMBreakpoint();
2742 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2743 if (pSvgaR3State->pFuncsDX)
2744 {
2745 RT_NOREF(pCmd);
2746 pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v3(pThisCC->svga.p3dState);
2747 }
2748}
2749
2750
2751/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
2752static void vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXResolveCopy const *pCmd)
2753{
2754ASMBreakpoint();
2755 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2756 if (pSvgaR3State->pFuncsDX)
2757 {
2758 RT_NOREF(pCmd);
2759 pSvgaR3State->pFuncsDX->pfnDXResolveCopy(pThisCC->svga.p3dState);
2760 }
2761}
2762
2763
2764/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
2765static void vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXPredResolveCopy const *pCmd)
2766{
2767ASMBreakpoint();
2768 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2769 if (pSvgaR3State->pFuncsDX)
2770 {
2771 RT_NOREF(pCmd);
2772 pSvgaR3State->pFuncsDX->pfnDXPredResolveCopy(pThisCC->svga.p3dState);
2773 }
2774}
2775
2776
2777/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
2778static void vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvertRegion const *pCmd)
2779{
2780ASMBreakpoint();
2781 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2782 if (pSvgaR3State->pFuncsDX)
2783 {
2784 RT_NOREF(pCmd);
2785 pSvgaR3State->pFuncsDX->pfnDXPredConvertRegion(pThisCC->svga.p3dState);
2786 }
2787}
2788
2789
2790/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
2791static void vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvert const *pCmd)
2792{
2793ASMBreakpoint();
2794 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2795 if (pSvgaR3State->pFuncsDX)
2796 {
2797 RT_NOREF(pCmd);
2798 pSvgaR3State->pFuncsDX->pfnDXPredConvert(pThisCC->svga.p3dState);
2799 }
2800}
2801
2802
2803/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
2804static void vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdWholeSurfaceCopy const *pCmd)
2805{
2806ASMBreakpoint();
2807 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2808 if (pSvgaR3State->pFuncsDX)
2809 {
2810 RT_NOREF(pCmd);
2811 pSvgaR3State->pFuncsDX->pfnWholeSurfaceCopy(pThisCC->svga.p3dState);
2812 }
2813}
2814
2815
2816/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
2817static void vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineUAView const *pCmd)
2818{
2819ASMBreakpoint();
2820 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2821 if (pSvgaR3State->pFuncsDX)
2822 {
2823 RT_NOREF(pCmd);
2824 pSvgaR3State->pFuncsDX->pfnDXDefineUAView(pThisCC->svga.p3dState);
2825 }
2826}
2827
2828
2829/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
2830static void vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyUAView const *pCmd)
2831{
2832ASMBreakpoint();
2833 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2834 if (pSvgaR3State->pFuncsDX)
2835 {
2836 RT_NOREF(pCmd);
2837 pSvgaR3State->pFuncsDX->pfnDXDestroyUAView(pThisCC->svga.p3dState);
2838 }
2839}
2840
2841
2842/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
2843static void vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewUint const *pCmd)
2844{
2845ASMBreakpoint();
2846 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2847 if (pSvgaR3State->pFuncsDX)
2848 {
2849 RT_NOREF(pCmd);
2850 pSvgaR3State->pFuncsDX->pfnDXClearUAViewUint(pThisCC->svga.p3dState);
2851 }
2852}
2853
2854
2855/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
2856static void vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewFloat const *pCmd)
2857{
2858ASMBreakpoint();
2859 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2860 if (pSvgaR3State->pFuncsDX)
2861 {
2862 RT_NOREF(pCmd);
2863 pSvgaR3State->pFuncsDX->pfnDXClearUAViewFloat(pThisCC->svga.p3dState);
2864 }
2865}
2866
2867
2868/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
2869static void vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXCopyStructureCount const *pCmd)
2870{
2871ASMBreakpoint();
2872 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2873 if (pSvgaR3State->pFuncsDX)
2874 {
2875 RT_NOREF(pCmd);
2876 pSvgaR3State->pFuncsDX->pfnDXCopyStructureCount(pThisCC->svga.p3dState);
2877 }
2878}
2879
2880
2881/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
2882static void vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetUAViews const *pCmd)
2883{
2884ASMBreakpoint();
2885 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2886 if (pSvgaR3State->pFuncsDX)
2887 {
2888 RT_NOREF(pCmd);
2889 pSvgaR3State->pFuncsDX->pfnDXSetUAViews(pThisCC->svga.p3dState);
2890 }
2891}
2892
2893
2894/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
2895static void vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd)
2896{
2897ASMBreakpoint();
2898 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2899 if (pSvgaR3State->pFuncsDX)
2900 {
2901 RT_NOREF(pCmd);
2902 pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstancedIndirect(pThisCC->svga.p3dState);
2903 }
2904}
2905
2906
2907/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
2908static void vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawInstancedIndirect const *pCmd)
2909{
2910ASMBreakpoint();
2911 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2912 if (pSvgaR3State->pFuncsDX)
2913 {
2914 RT_NOREF(pCmd);
2915 pSvgaR3State->pFuncsDX->pfnDXDrawInstancedIndirect(pThisCC->svga.p3dState);
2916 }
2917}
2918
2919
2920/* SVGA_3D_CMD_DX_DISPATCH 1253 */
2921static void vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, SVGA3dCmdDXDispatch const *pCmd)
2922{
2923ASMBreakpoint();
2924 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2925 if (pSvgaR3State->pFuncsDX)
2926 {
2927 RT_NOREF(pCmd);
2928 pSvgaR3State->pFuncsDX->pfnDXDispatch(pThisCC->svga.p3dState);
2929 }
2930}
2931
2932
2933/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
2934static void vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDispatchIndirect const *pCmd)
2935{
2936ASMBreakpoint();
2937 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2938 if (pSvgaR3State->pFuncsDX)
2939 {
2940 RT_NOREF(pCmd);
2941 pSvgaR3State->pFuncsDX->pfnDXDispatchIndirect(pThisCC->svga.p3dState);
2942 }
2943}
2944
2945
2946/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
2947static void vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdWriteZeroSurface const *pCmd)
2948{
2949ASMBreakpoint();
2950 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2951 if (pSvgaR3State->pFuncsDX)
2952 {
2953 RT_NOREF(pCmd);
2954 pSvgaR3State->pFuncsDX->pfnWriteZeroSurface(pThisCC->svga.p3dState);
2955 }
2956}
2957
2958
2959/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
2960static void vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdHintZeroSurface const *pCmd)
2961{
2962ASMBreakpoint();
2963 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2964 if (pSvgaR3State->pFuncsDX)
2965 {
2966 RT_NOREF(pCmd);
2967 pSvgaR3State->pFuncsDX->pfnHintZeroSurface(pThisCC->svga.p3dState);
2968 }
2969}
2970
2971
2972/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
2973static void vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferToBuffer const *pCmd)
2974{
2975ASMBreakpoint();
2976 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2977 if (pSvgaR3State->pFuncsDX)
2978 {
2979 RT_NOREF(pCmd);
2980 pSvgaR3State->pFuncsDX->pfnDXTransferToBuffer(pThisCC->svga.p3dState);
2981 }
2982}
2983
2984
2985/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
2986static void vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXSetStructureCount const *pCmd)
2987{
2988ASMBreakpoint();
2989 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2990 if (pSvgaR3State->pFuncsDX)
2991 {
2992 RT_NOREF(pCmd);
2993 pSvgaR3State->pFuncsDX->pfnDXSetStructureCount(pThisCC->svga.p3dState);
2994 }
2995}
2996
2997
2998/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
2999static void vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsBitBlt const *pCmd)
3000{
3001ASMBreakpoint();
3002 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3003 if (pSvgaR3State->pFuncsDX)
3004 {
3005 RT_NOREF(pCmd);
3006 pSvgaR3State->pFuncsDX->pfnLogicOpsBitBlt(pThisCC->svga.p3dState);
3007 }
3008}
3009
3010
3011/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3012static void vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsTransBlt const *pCmd)
3013{
3014ASMBreakpoint();
3015 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3016 if (pSvgaR3State->pFuncsDX)
3017 {
3018 RT_NOREF(pCmd);
3019 pSvgaR3State->pFuncsDX->pfnLogicOpsTransBlt(pThisCC->svga.p3dState);
3020 }
3021}
3022
3023
3024/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3025static void vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsStretchBlt const *pCmd)
3026{
3027ASMBreakpoint();
3028 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3029 if (pSvgaR3State->pFuncsDX)
3030 {
3031 RT_NOREF(pCmd);
3032 pSvgaR3State->pFuncsDX->pfnLogicOpsStretchBlt(pThisCC->svga.p3dState);
3033 }
3034}
3035
3036
3037/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3038static void vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsColorFill const *pCmd)
3039{
3040ASMBreakpoint();
3041 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3042 if (pSvgaR3State->pFuncsDX)
3043 {
3044 RT_NOREF(pCmd);
3045 pSvgaR3State->pFuncsDX->pfnLogicOpsColorFill(pThisCC->svga.p3dState);
3046 }
3047}
3048
3049
3050/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3051static void vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsAlphaBlend const *pCmd)
3052{
3053ASMBreakpoint();
3054 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3055 if (pSvgaR3State->pFuncsDX)
3056 {
3057 RT_NOREF(pCmd);
3058 pSvgaR3State->pFuncsDX->pfnLogicOpsAlphaBlend(pThisCC->svga.p3dState);
3059 }
3060}
3061
3062
3063/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3064static void vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd)
3065{
3066ASMBreakpoint();
3067 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3068 if (pSvgaR3State->pFuncsDX)
3069 {
3070 RT_NOREF(pCmd);
3071 pSvgaR3State->pFuncsDX->pfnLogicOpsClearTypeBlend(pThisCC->svga.p3dState);
3072 }
3073}
3074
3075
3076/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3077static void vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
3078{
3079ASMBreakpoint();
3080 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3081 if (pSvgaR3State->pFuncsDX)
3082 {
3083 RT_NOREF(pCmd);
3084 pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v4(pThisCC->svga.p3dState);
3085 }
3086}
3087
3088
3089/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3090static void vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSUAViews const *pCmd)
3091{
3092ASMBreakpoint();
3093 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3094 if (pSvgaR3State->pFuncsDX)
3095 {
3096 RT_NOREF(pCmd);
3097 pSvgaR3State->pFuncsDX->pfnDXSetCSUAViews(pThisCC->svga.p3dState);
3098 }
3099}
3100
3101
3102/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3103static void vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, SVGA3dCmdDXSetMinLOD const *pCmd)
3104{
3105ASMBreakpoint();
3106 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3107 if (pSvgaR3State->pFuncsDX)
3108 {
3109 RT_NOREF(pCmd);
3110 pSvgaR3State->pFuncsDX->pfnDXSetMinLOD(pThisCC->svga.p3dState);
3111 }
3112}
3113
3114
3115/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3116static void vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd)
3117{
3118ASMBreakpoint();
3119 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3120 if (pSvgaR3State->pFuncsDX)
3121 {
3122 RT_NOREF(pCmd);
3123 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView_v2(pThisCC->svga.p3dState);
3124 }
3125}
3126
3127
3128/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3129static void vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd)
3130{
3131ASMBreakpoint();
3132 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3133 if (pSvgaR3State->pFuncsDX)
3134 {
3135 RT_NOREF(pCmd);
3136 pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutputWithMob(pThisCC->svga.p3dState);
3137 }
3138}
3139
3140
3141/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3142static void vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXSetShaderIface const *pCmd)
3143{
3144ASMBreakpoint();
3145 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3146 if (pSvgaR3State->pFuncsDX)
3147 {
3148 RT_NOREF(pCmd);
3149 pSvgaR3State->pFuncsDX->pfnDXSetShaderIface(pThisCC->svga.p3dState);
3150 }
3151}
3152
3153
3154/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3155static void vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXBindStreamOutput const *pCmd)
3156{
3157ASMBreakpoint();
3158 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3159 if (pSvgaR3State->pFuncsDX)
3160 {
3161 RT_NOREF(pCmd);
3162 pSvgaR3State->pFuncsDX->pfnDXBindStreamOutput(pThisCC->svga.p3dState);
3163 }
3164}
3165
3166
3167/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3168static void vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd)
3169{
3170ASMBreakpoint();
3171 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3172 if (pSvgaR3State->pFuncsDX)
3173 {
3174 RT_NOREF(pCmd);
3175 pSvgaR3State->pFuncsDX->pfnSurfaceStretchBltNonMSToMS(pThisCC->svga.p3dState);
3176 }
3177}
3178
3179
3180/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3181static void vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXBindShaderIface const *pCmd)
3182{
3183ASMBreakpoint();
3184 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3185 if (pSvgaR3State->pFuncsDX)
3186 {
3187 RT_NOREF(pCmd);
3188 pSvgaR3State->pFuncsDX->pfnDXBindShaderIface(pThisCC->svga.p3dState);
3189 }
3190}
3191
3192
3193/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3194 * Check that the 3D command has at least a_cbMin of payload bytes after the
3195 * header. Will break out of the switch if it doesn't.
3196 */
3197# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3198 if (1) { \
3199 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3200 RT_UNTRUSTED_VALIDATED_FENCE(); \
3201 } else do {} while (0)
3202
3203# define VMSVGA_3D_CMD_NOTIMPL() \
3204 if (1) { \
3205 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3206 } else do {} while (0)
3207
3208/** SVGA_3D_CMD_* handler.
3209 * This function parses the command and calls the corresponding command handler.
3210 *
3211 * @param pThis The shared VGA/VMSVGA state.
3212 * @param pThisCC The VGA/VMSVGA state for the current context.
3213 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3214 * @param cbCmd Size of the command in bytes.
3215 * @param pvCmd Pointer to the command.
3216 * @returns VBox status code if an error was detected parsing a command.
3217 */
3218int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3219{
3220 if (enmCmdId > SVGA_3D_CMD_MAX)
3221 {
3222 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3223 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3224 }
3225
3226 int rcParse = VINF_SUCCESS;
3227 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3228
3229 switch (enmCmdId)
3230 {
3231 case SVGA_3D_CMD_SURFACE_DEFINE:
3232 {
3233 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3234 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3235 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3236
3237 SVGA3dCmdDefineSurface_v2 cmd;
3238 cmd.sid = pCmd->sid;
3239 cmd.surfaceFlags = pCmd->surfaceFlags;
3240 cmd.format = pCmd->format;
3241 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3242 cmd.multisampleCount = 0;
3243 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3244
3245 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3246 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3247# ifdef DEBUG_GMR_ACCESS
3248 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3249# endif
3250 break;
3251 }
3252
3253 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3254 {
3255 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3256 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3257 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3258
3259 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3260 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3261# ifdef DEBUG_GMR_ACCESS
3262 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3263# endif
3264 break;
3265 }
3266
3267 case SVGA_3D_CMD_SURFACE_DESTROY:
3268 {
3269 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3271 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3272
3273 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3274 break;
3275 }
3276
3277 case SVGA_3D_CMD_SURFACE_COPY:
3278 {
3279 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3280 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3281 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3282
3283 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3284 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3285 break;
3286 }
3287
3288 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3289 {
3290 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3291 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3292 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3293
3294 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3295 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3296 break;
3297 }
3298
3299 case SVGA_3D_CMD_SURFACE_DMA:
3300 {
3301 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3302 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3303 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3304
3305 uint64_t u64NanoTS = 0;
3306 if (LogRelIs3Enabled())
3307 u64NanoTS = RTTimeNanoTS();
3308 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3309 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3310 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3311 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3312 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3313 if (LogRelIs3Enabled())
3314 {
3315 if (cCopyBoxes)
3316 {
3317 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3318 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3319 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3320 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3321 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3322 }
3323 }
3324 break;
3325 }
3326
3327 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3328 {
3329 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3331 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3332
3333 static uint64_t u64FrameStartNanoTS = 0;
3334 static uint64_t u64ElapsedPerSecNano = 0;
3335 static int cFrames = 0;
3336 uint64_t u64NanoTS = 0;
3337 if (LogRelIs3Enabled())
3338 u64NanoTS = RTTimeNanoTS();
3339 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3340 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3341 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3342 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3343 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3344 if (LogRelIs3Enabled())
3345 {
3346 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3347 u64ElapsedPerSecNano += u64ElapsedNano;
3348
3349 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3350 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3351 (u64ElapsedNano) / 1000ULL, cRects,
3352 pFirstRect->left, pFirstRect->top,
3353 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3354
3355 ++cFrames;
3356 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3357 {
3358 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3359 cFrames, u64ElapsedPerSecNano / 1000ULL));
3360 u64FrameStartNanoTS = u64NanoTS;
3361 cFrames = 0;
3362 u64ElapsedPerSecNano = 0;
3363 }
3364 }
3365 break;
3366 }
3367
3368 case SVGA_3D_CMD_CONTEXT_DEFINE:
3369 {
3370 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3371 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3372 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3373
3374 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3375 break;
3376 }
3377
3378 case SVGA_3D_CMD_CONTEXT_DESTROY:
3379 {
3380 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3382 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3383
3384 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3385 break;
3386 }
3387
3388 case SVGA_3D_CMD_SETTRANSFORM:
3389 {
3390 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3391 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3392 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3393
3394 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3395 break;
3396 }
3397
3398 case SVGA_3D_CMD_SETZRANGE:
3399 {
3400 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3402 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3403
3404 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3405 break;
3406 }
3407
3408 case SVGA_3D_CMD_SETRENDERSTATE:
3409 {
3410 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3411 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3412 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3413
3414 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3415 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3416 break;
3417 }
3418
3419 case SVGA_3D_CMD_SETRENDERTARGET:
3420 {
3421 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3422 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3423 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3424
3425 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3426 break;
3427 }
3428
3429 case SVGA_3D_CMD_SETTEXTURESTATE:
3430 {
3431 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3433 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3434
3435 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3436 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3437 break;
3438 }
3439
3440 case SVGA_3D_CMD_SETMATERIAL:
3441 {
3442 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3443 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3444 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3445
3446 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3447 break;
3448 }
3449
3450 case SVGA_3D_CMD_SETLIGHTDATA:
3451 {
3452 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3453 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3454 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3455
3456 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3457 break;
3458 }
3459
3460 case SVGA_3D_CMD_SETLIGHTENABLED:
3461 {
3462 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3464 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3465
3466 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3467 break;
3468 }
3469
3470 case SVGA_3D_CMD_SETVIEWPORT:
3471 {
3472 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
3473 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3474 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
3475
3476 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
3477 break;
3478 }
3479
3480 case SVGA_3D_CMD_SETCLIPPLANE:
3481 {
3482 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
3483 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3484 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
3485
3486 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
3487 break;
3488 }
3489
3490 case SVGA_3D_CMD_CLEAR:
3491 {
3492 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
3493 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3494 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
3495
3496 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3497 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3498 break;
3499 }
3500
3501 case SVGA_3D_CMD_PRESENT:
3502 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3503 {
3504 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
3505 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3506 if (enmCmdId == SVGA_3D_CMD_PRESENT)
3507 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
3508 else
3509 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
3510
3511 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3512 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3513 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3514 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3515 break;
3516 }
3517
3518 case SVGA_3D_CMD_SHADER_DEFINE:
3519 {
3520 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
3521 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3522 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
3523
3524 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
3525 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3526 break;
3527 }
3528
3529 case SVGA_3D_CMD_SHADER_DESTROY:
3530 {
3531 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
3532 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3533 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
3534
3535 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
3536 break;
3537 }
3538
3539 case SVGA_3D_CMD_SET_SHADER:
3540 {
3541 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
3542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3543 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
3544
3545 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3546 break;
3547 }
3548
3549 case SVGA_3D_CMD_SET_SHADER_CONST:
3550 {
3551 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
3552 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3553 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
3554
3555 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3556 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3557 break;
3558 }
3559
3560 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3561 {
3562 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
3563 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3564 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
3565
3566 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
3567 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
3568 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
3569 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
3570 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
3571
3572 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
3573 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
3574 RT_UNTRUSTED_VALIDATED_FENCE();
3575
3576 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3577 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
3578 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
3579
3580 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3581 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
3582 pNumRange, cVertexDivisor, pVertexDivisor);
3583 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3584 break;
3585 }
3586
3587 case SVGA_3D_CMD_SETSCISSORRECT:
3588 {
3589 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
3590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3591 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
3592
3593 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
3594 break;
3595 }
3596
3597 case SVGA_3D_CMD_BEGIN_QUERY:
3598 {
3599 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
3600 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3601 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
3602
3603 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
3604 break;
3605 }
3606
3607 case SVGA_3D_CMD_END_QUERY:
3608 {
3609 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
3610 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3611 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
3612
3613 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3614 break;
3615 }
3616
3617 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3618 {
3619 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
3620 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3621 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
3622
3623 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3624 break;
3625 }
3626
3627 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3628 {
3629 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
3630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3631 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
3632
3633 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
3634 break;
3635 }
3636
3637 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3638 /* context id + surface id? */
3639 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
3640 break;
3641
3642 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3643 /* context id + surface id? */
3644 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
3645 break;
3646
3647 /*
3648 *
3649 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
3650 *
3651 */
3652 case SVGA_3D_CMD_SCREEN_DMA:
3653 {
3654 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
3655 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3656 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3657 break;
3658 }
3659
3660 case SVGA_3D_CMD_DEAD1:
3661 case SVGA_3D_CMD_DEAD2:
3662 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
3663 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
3664 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
3665 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
3666 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
3667 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
3668 {
3669 VMSVGA_3D_CMD_NOTIMPL();
3670 break;
3671 }
3672
3673 case SVGA_3D_CMD_SET_OTABLE_BASE:
3674 {
3675 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
3676 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3677 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3678 break;
3679 }
3680
3681 case SVGA_3D_CMD_READBACK_OTABLE:
3682 {
3683 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
3684 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3685 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3686 break;
3687 }
3688
3689 case SVGA_3D_CMD_DEFINE_GB_MOB:
3690 {
3691 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
3692 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3693 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
3694 break;
3695 }
3696
3697 case SVGA_3D_CMD_DESTROY_GB_MOB:
3698 {
3699 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
3700 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3701 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
3702 break;
3703 }
3704
3705 case SVGA_3D_CMD_DEAD3:
3706 {
3707 VMSVGA_3D_CMD_NOTIMPL();
3708 break;
3709 }
3710
3711 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
3712 {
3713 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
3714 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3715 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3716 break;
3717 }
3718
3719 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
3720 {
3721 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
3722 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3723 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
3724 break;
3725 }
3726
3727 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
3728 {
3729 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
3730 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3731 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
3732 break;
3733 }
3734
3735 case SVGA_3D_CMD_BIND_GB_SURFACE:
3736 {
3737 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
3738 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3739 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
3740 break;
3741 }
3742
3743 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
3744 {
3745 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
3746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3747 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3748 break;
3749 }
3750
3751 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
3752 {
3753 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
3754 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3755 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
3756 break;
3757 }
3758
3759 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
3760 {
3761 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
3762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3763 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3764 break;
3765 }
3766
3767 case SVGA_3D_CMD_READBACK_GB_IMAGE:
3768 {
3769 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
3770 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3771 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3772 break;
3773 }
3774
3775 case SVGA_3D_CMD_READBACK_GB_SURFACE:
3776 {
3777 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
3778 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3779 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3780 break;
3781 }
3782
3783 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
3784 {
3785 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
3786 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3787 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3788 break;
3789 }
3790
3791 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
3792 {
3793 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
3794 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3795 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
3796 break;
3797 }
3798
3799 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
3800 {
3801 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
3802 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3803 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3804 break;
3805 }
3806
3807 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
3808 {
3809 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
3810 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3811 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3812 break;
3813 }
3814
3815 case SVGA_3D_CMD_BIND_GB_CONTEXT:
3816 {
3817 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
3818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3819 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3820 break;
3821 }
3822
3823 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
3824 {
3825 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
3826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3827 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3828 break;
3829 }
3830
3831 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
3832 {
3833 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
3834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3835 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3836 break;
3837 }
3838
3839 case SVGA_3D_CMD_DEFINE_GB_SHADER:
3840 {
3841 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
3842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3843 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3844 break;
3845 }
3846
3847 case SVGA_3D_CMD_DESTROY_GB_SHADER:
3848 {
3849 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
3850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3851 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3852 break;
3853 }
3854
3855 case SVGA_3D_CMD_BIND_GB_SHADER:
3856 {
3857 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
3858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3859 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3860 break;
3861 }
3862
3863 case SVGA_3D_CMD_SET_OTABLE_BASE64:
3864 {
3865 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
3866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3867 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
3868 break;
3869 }
3870
3871 case SVGA_3D_CMD_BEGIN_GB_QUERY:
3872 {
3873 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
3874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3875 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3876 break;
3877 }
3878
3879 case SVGA_3D_CMD_END_GB_QUERY:
3880 {
3881 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
3882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3883 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3884 break;
3885 }
3886
3887 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
3888 {
3889 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
3890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3891 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3892 break;
3893 }
3894
3895 case SVGA_3D_CMD_NOP:
3896 {
3897 /* Apparently there is nothing to do. */
3898 break;
3899 }
3900
3901 case SVGA_3D_CMD_ENABLE_GART:
3902 {
3903 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
3904 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3905 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3906 break;
3907 }
3908
3909 case SVGA_3D_CMD_DISABLE_GART:
3910 {
3911 /* No corresponding SVGA3dCmd structure. */
3912 VMSVGA_3D_CMD_NOTIMPL();
3913 break;
3914 }
3915
3916 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
3917 {
3918 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
3919 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3920 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3921 break;
3922 }
3923
3924 case SVGA_3D_CMD_UNMAP_GART_RANGE:
3925 {
3926 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
3927 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3928 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3929 break;
3930 }
3931
3932 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
3933 {
3934 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
3935 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3936 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
3937 break;
3938 }
3939
3940 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
3941 {
3942 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
3943 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3944 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
3945 break;
3946 }
3947
3948 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
3949 {
3950 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
3951 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3952 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
3953 break;
3954 }
3955
3956 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
3957 {
3958 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
3959 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3960 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
3961 break;
3962 }
3963
3964 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
3965 {
3966 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
3967 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3968 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3969 break;
3970 }
3971
3972 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
3973 {
3974 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
3975 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3976 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3977 break;
3978 }
3979
3980 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
3981 {
3982 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
3983 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3984 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3985 break;
3986 }
3987
3988 case SVGA_3D_CMD_GB_SCREEN_DMA:
3989 {
3990 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
3991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3992 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3993 break;
3994 }
3995
3996 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
3997 {
3998 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
3999 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4000 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4001 break;
4002 }
4003
4004 case SVGA_3D_CMD_GB_MOB_FENCE:
4005 {
4006 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4007 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4008 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4009 break;
4010 }
4011
4012 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4013 {
4014 /// @todo SVGA3dCmdDefineGBSurface_v2 is not defined in Mesa 17 header. Mesa 20 has it.
4015 //SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4016 //VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4017 VMSVGA_3D_CMD_NOTIMPL();
4018 break;
4019 }
4020
4021 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4022 {
4023 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4024 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4025 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4026 break;
4027 }
4028
4029 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4030 {
4031 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4032 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4033 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4034 break;
4035 }
4036
4037 case SVGA_3D_CMD_NOP_ERROR:
4038 {
4039 /* Apparently there is nothing to do. */
4040 break;
4041 }
4042
4043 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4044 {
4045 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4047 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4048 break;
4049 }
4050
4051 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4052 {
4053 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4055 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4056 break;
4057 }
4058
4059 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4060 {
4061 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4063 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4064 break;
4065 }
4066
4067 case SVGA_3D_CMD_DRAW:
4068 {
4069 /* No corresponding SVGA3dCmd structure. */
4070 VMSVGA_3D_CMD_NOTIMPL();
4071 break;
4072 }
4073
4074 case SVGA_3D_CMD_DRAW_INDEXED:
4075 {
4076 /* No corresponding SVGA3dCmd structure. */
4077 VMSVGA_3D_CMD_NOTIMPL();
4078 break;
4079 }
4080
4081 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4082 {
4083 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4084 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4085 vmsvga3dCmdDXDefineContext(pThisCC, pCmd);
4086 break;
4087 }
4088
4089 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4090 {
4091 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4092 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4093 vmsvga3dCmdDXDestroyContext(pThisCC, pCmd);
4094 break;
4095 }
4096
4097 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4098 {
4099 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4100 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4101 vmsvga3dCmdDXBindContext(pThisCC, pCmd);
4102 break;
4103 }
4104
4105 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4106 {
4107 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4108 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4109 vmsvga3dCmdDXReadbackContext(pThisCC, pCmd);
4110 break;
4111 }
4112
4113 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4114 {
4115 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4116 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4117 vmsvga3dCmdDXInvalidateContext(pThisCC, pCmd);
4118 break;
4119 }
4120
4121 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4122 {
4123 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4124 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4125 vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, pCmd);
4126 break;
4127 }
4128
4129 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4130 {
4131 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4132 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4133 vmsvga3dCmdDXSetShaderResources(pThisCC, pCmd);
4134 break;
4135 }
4136
4137 case SVGA_3D_CMD_DX_SET_SHADER:
4138 {
4139 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4140 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4141 vmsvga3dCmdDXSetShader(pThisCC, pCmd);
4142 break;
4143 }
4144
4145 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4146 {
4147 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4148 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4149 vmsvga3dCmdDXSetSamplers(pThisCC, pCmd);
4150 break;
4151 }
4152
4153 case SVGA_3D_CMD_DX_DRAW:
4154 {
4155 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4156 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4157 vmsvga3dCmdDXDraw(pThisCC, pCmd);
4158 break;
4159 }
4160
4161 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4162 {
4163 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4164 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4165 vmsvga3dCmdDXDrawIndexed(pThisCC, pCmd);
4166 break;
4167 }
4168
4169 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4170 {
4171 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4172 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4173 vmsvga3dCmdDXDrawInstanced(pThisCC, pCmd);
4174 break;
4175 }
4176
4177 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4178 {
4179 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4180 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4181 vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, pCmd);
4182 break;
4183 }
4184
4185 case SVGA_3D_CMD_DX_DRAW_AUTO:
4186 {
4187 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4188 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4189 vmsvga3dCmdDXDrawAuto(pThisCC, pCmd);
4190 break;
4191 }
4192
4193 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4194 {
4195 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4196 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4197 vmsvga3dCmdDXSetInputLayout(pThisCC, pCmd);
4198 break;
4199 }
4200
4201 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4202 {
4203 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4204 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4205 vmsvga3dCmdDXSetVertexBuffers(pThisCC, pCmd);
4206 break;
4207 }
4208
4209 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4210 {
4211 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4212 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4213 vmsvga3dCmdDXSetIndexBuffer(pThisCC, pCmd);
4214 break;
4215 }
4216
4217 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4218 {
4219 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4220 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4221 vmsvga3dCmdDXSetTopology(pThisCC, pCmd);
4222 break;
4223 }
4224
4225 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4226 {
4227 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4228 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4229 vmsvga3dCmdDXSetRenderTargets(pThisCC, pCmd);
4230 break;
4231 }
4232
4233 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4234 {
4235 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4236 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4237 vmsvga3dCmdDXSetBlendState(pThisCC, pCmd);
4238 break;
4239 }
4240
4241 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4242 {
4243 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4244 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4245 vmsvga3dCmdDXSetDepthStencilState(pThisCC, pCmd);
4246 break;
4247 }
4248
4249 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4250 {
4251 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4252 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4253 vmsvga3dCmdDXSetRasterizerState(pThisCC, pCmd);
4254 break;
4255 }
4256
4257 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4258 {
4259 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4260 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4261 vmsvga3dCmdDXDefineQuery(pThisCC, pCmd);
4262 break;
4263 }
4264
4265 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4266 {
4267 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4268 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4269 vmsvga3dCmdDXDestroyQuery(pThisCC, pCmd);
4270 break;
4271 }
4272
4273 case SVGA_3D_CMD_DX_BIND_QUERY:
4274 {
4275 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4276 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4277 vmsvga3dCmdDXBindQuery(pThisCC, pCmd);
4278 break;
4279 }
4280
4281 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4282 {
4283 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4284 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4285 vmsvga3dCmdDXSetQueryOffset(pThisCC, pCmd);
4286 break;
4287 }
4288
4289 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4290 {
4291 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4292 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4293 vmsvga3dCmdDXBeginQuery(pThisCC, pCmd);
4294 break;
4295 }
4296
4297 case SVGA_3D_CMD_DX_END_QUERY:
4298 {
4299 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4300 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4301 vmsvga3dCmdDXEndQuery(pThisCC, pCmd);
4302 break;
4303 }
4304
4305 case SVGA_3D_CMD_DX_READBACK_QUERY:
4306 {
4307 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4308 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4309 vmsvga3dCmdDXReadbackQuery(pThisCC, pCmd);
4310 break;
4311 }
4312
4313 case SVGA_3D_CMD_DX_SET_PREDICATION:
4314 {
4315 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4316 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4317 vmsvga3dCmdDXSetPredication(pThisCC, pCmd);
4318 break;
4319 }
4320
4321 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4322 {
4323 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4324 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325 vmsvga3dCmdDXSetSOTargets(pThisCC, pCmd);
4326 break;
4327 }
4328
4329 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4330 {
4331 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4332 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4333 vmsvga3dCmdDXSetViewports(pThisCC, pCmd);
4334 break;
4335 }
4336
4337 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4338 {
4339 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4340 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4341 vmsvga3dCmdDXSetScissorRects(pThisCC, pCmd);
4342 break;
4343 }
4344
4345 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4346 {
4347 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4348 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4349 vmsvga3dCmdDXClearRenderTargetView(pThisCC, pCmd);
4350 break;
4351 }
4352
4353 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4354 {
4355 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4356 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4357 vmsvga3dCmdDXClearDepthStencilView(pThisCC, pCmd);
4358 break;
4359 }
4360
4361 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4362 {
4363 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4364 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4365 vmsvga3dCmdDXPredCopyRegion(pThisCC, pCmd);
4366 break;
4367 }
4368
4369 case SVGA_3D_CMD_DX_PRED_COPY:
4370 {
4371 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4372 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4373 vmsvga3dCmdDXPredCopy(pThisCC, pCmd);
4374 break;
4375 }
4376
4377 case SVGA_3D_CMD_DX_PRESENTBLT:
4378 {
4379 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4380 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381 vmsvga3dCmdDXPresentBlt(pThisCC, pCmd);
4382 break;
4383 }
4384
4385 case SVGA_3D_CMD_DX_GENMIPS:
4386 {
4387 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4388 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4389 vmsvga3dCmdDXGenMips(pThisCC, pCmd);
4390 break;
4391 }
4392
4393 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4394 {
4395 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4396 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4397 vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd);
4398 break;
4399 }
4400
4401 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4402 {
4403 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4404 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4405 vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd);
4406 break;
4407 }
4408
4409 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4410 {
4411 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4412 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4413 vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd);
4414 break;
4415 }
4416
4417 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4418 {
4419 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4420 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4421 vmsvga3dCmdDXDefineShaderResourceView(pThisCC, pCmd);
4422 break;
4423 }
4424
4425 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4426 {
4427 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4428 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4429 vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, pCmd);
4430 break;
4431 }
4432
4433 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4434 {
4435 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4436 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4437 vmsvga3dCmdDXDefineRenderTargetView(pThisCC, pCmd);
4438 break;
4439 }
4440
4441 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
4442 {
4443 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
4444 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445 vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, pCmd);
4446 break;
4447 }
4448
4449 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
4450 {
4451 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
4452 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4453 vmsvga3dCmdDXDefineDepthStencilView(pThisCC, pCmd);
4454 break;
4455 }
4456
4457 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
4458 {
4459 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
4460 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4461 vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, pCmd);
4462 break;
4463 }
4464
4465 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
4466 {
4467 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
4468 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4469 vmsvga3dCmdDXDefineElementLayout(pThisCC, pCmd);
4470 break;
4471 }
4472
4473 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
4474 {
4475 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
4476 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4477 vmsvga3dCmdDXDestroyElementLayout(pThisCC, pCmd);
4478 break;
4479 }
4480
4481 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
4482 {
4483 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
4484 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4485 vmsvga3dCmdDXDefineBlendState(pThisCC, pCmd);
4486 break;
4487 }
4488
4489 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
4490 {
4491 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
4492 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4493 vmsvga3dCmdDXDestroyBlendState(pThisCC, pCmd);
4494 break;
4495 }
4496
4497 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
4498 {
4499 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
4500 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4501 vmsvga3dCmdDXDefineDepthStencilState(pThisCC, pCmd);
4502 break;
4503 }
4504
4505 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
4506 {
4507 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
4508 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4509 vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, pCmd);
4510 break;
4511 }
4512
4513 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
4514 {
4515 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
4516 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4517 vmsvga3dCmdDXDefineRasterizerState(pThisCC, pCmd);
4518 break;
4519 }
4520
4521 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
4522 {
4523 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
4524 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4525 vmsvga3dCmdDXDestroyRasterizerState(pThisCC, pCmd);
4526 break;
4527 }
4528
4529 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
4530 {
4531 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
4532 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4533 vmsvga3dCmdDXDefineSamplerState(pThisCC, pCmd);
4534 break;
4535 }
4536
4537 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
4538 {
4539 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
4540 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4541 vmsvga3dCmdDXDestroySamplerState(pThisCC, pCmd);
4542 break;
4543 }
4544
4545 case SVGA_3D_CMD_DX_DEFINE_SHADER:
4546 {
4547 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
4548 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4549 vmsvga3dCmdDXDefineShader(pThisCC, pCmd);
4550 break;
4551 }
4552
4553 case SVGA_3D_CMD_DX_DESTROY_SHADER:
4554 {
4555 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
4556 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4557 vmsvga3dCmdDXDestroyShader(pThisCC, pCmd);
4558 break;
4559 }
4560
4561 case SVGA_3D_CMD_DX_BIND_SHADER:
4562 {
4563 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
4564 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4565 vmsvga3dCmdDXBindShader(pThisCC, pCmd);
4566 break;
4567 }
4568
4569 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
4570 {
4571 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
4572 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4573 vmsvga3dCmdDXDefineStreamOutput(pThisCC, pCmd);
4574 break;
4575 }
4576
4577 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
4578 {
4579 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
4580 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581 vmsvga3dCmdDXDestroyStreamOutput(pThisCC, pCmd);
4582 break;
4583 }
4584
4585 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
4586 {
4587 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
4588 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4589 vmsvga3dCmdDXSetStreamOutput(pThisCC, pCmd);
4590 break;
4591 }
4592
4593 case SVGA_3D_CMD_DX_SET_COTABLE:
4594 {
4595 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
4596 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4597 vmsvga3dCmdDXSetCOTable(pThisCC, pCmd);
4598 break;
4599 }
4600
4601 case SVGA_3D_CMD_DX_READBACK_COTABLE:
4602 {
4603 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
4604 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4605 vmsvga3dCmdDXReadbackCOTable(pThisCC, pCmd);
4606 break;
4607 }
4608
4609 case SVGA_3D_CMD_DX_BUFFER_COPY:
4610 {
4611 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
4612 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4613 vmsvga3dCmdDXBufferCopy(pThisCC, pCmd);
4614 break;
4615 }
4616
4617 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
4618 {
4619 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
4620 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4621 vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd);
4622 break;
4623 }
4624
4625 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
4626 {
4627 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
4628 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4629 vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, pCmd);
4630 break;
4631 }
4632
4633 case SVGA_3D_CMD_DX_MOVE_QUERY:
4634 {
4635 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
4636 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4637 vmsvga3dCmdDXMoveQuery(pThisCC, pCmd);
4638 break;
4639 }
4640
4641 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
4642 {
4643 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
4644 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4645 vmsvga3dCmdDXBindAllQuery(pThisCC, pCmd);
4646 break;
4647 }
4648
4649 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
4650 {
4651 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
4652 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4653 vmsvga3dCmdDXReadbackAllQuery(pThisCC, pCmd);
4654 break;
4655 }
4656
4657 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
4658 {
4659 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
4660 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4661 vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, pCmd);
4662 break;
4663 }
4664
4665 case SVGA_3D_CMD_DX_MOB_FENCE_64:
4666 {
4667 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
4668 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4669 vmsvga3dCmdDXMobFence64(pThisCC, pCmd);
4670 break;
4671 }
4672
4673 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
4674 {
4675 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
4676 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4677 vmsvga3dCmdDXBindAllShader(pThisCC, pCmd);
4678 break;
4679 }
4680
4681 case SVGA_3D_CMD_DX_HINT:
4682 {
4683 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
4684 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4685 vmsvga3dCmdDXHint(pThisCC, pCmd);
4686 break;
4687 }
4688
4689 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
4690 {
4691 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
4692 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4693 vmsvga3dCmdDXBufferUpdate(pThisCC, pCmd);
4694 break;
4695 }
4696
4697 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
4698 {
4699 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
4700 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4701 vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, pCmd);
4702 break;
4703 }
4704
4705 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
4706 {
4707 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
4708 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4709 vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, pCmd);
4710 break;
4711 }
4712
4713 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
4714 {
4715 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
4716 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4717 vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, pCmd);
4718 break;
4719 }
4720
4721 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
4722 {
4723 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
4724 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4725 vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, pCmd);
4726 break;
4727 }
4728
4729 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
4730 {
4731 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
4732 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4733 vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, pCmd);
4734 break;
4735 }
4736
4737 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
4738 {
4739 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
4740 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4741 vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, pCmd);
4742 break;
4743 }
4744
4745 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
4746 {
4747 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
4748 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4749 vmsvga3dCmdDXCondBindAllShader(pThisCC, pCmd);
4750 break;
4751 }
4752
4753 case SVGA_3D_CMD_SCREEN_COPY:
4754 {
4755 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
4756 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4757 vmsvga3dCmdScreenCopy(pThisCC, pCmd);
4758 break;
4759 }
4760
4761 case SVGA_3D_CMD_RESERVED1:
4762 {
4763 VMSVGA_3D_CMD_NOTIMPL();
4764 break;
4765 }
4766
4767 case SVGA_3D_CMD_RESERVED2:
4768 {
4769 VMSVGA_3D_CMD_NOTIMPL();
4770 break;
4771 }
4772
4773 case SVGA_3D_CMD_RESERVED3:
4774 {
4775 VMSVGA_3D_CMD_NOTIMPL();
4776 break;
4777 }
4778
4779 case SVGA_3D_CMD_RESERVED4:
4780 {
4781 VMSVGA_3D_CMD_NOTIMPL();
4782 break;
4783 }
4784
4785 case SVGA_3D_CMD_RESERVED5:
4786 {
4787 VMSVGA_3D_CMD_NOTIMPL();
4788 break;
4789 }
4790
4791 case SVGA_3D_CMD_RESERVED6:
4792 {
4793 VMSVGA_3D_CMD_NOTIMPL();
4794 break;
4795 }
4796
4797 case SVGA_3D_CMD_RESERVED7:
4798 {
4799 VMSVGA_3D_CMD_NOTIMPL();
4800 break;
4801 }
4802
4803 case SVGA_3D_CMD_RESERVED8:
4804 {
4805 VMSVGA_3D_CMD_NOTIMPL();
4806 break;
4807 }
4808
4809 case SVGA_3D_CMD_GROW_OTABLE:
4810 {
4811 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
4812 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4813 vmsvga3dCmdGrowOTable(pThisCC, pCmd);
4814 break;
4815 }
4816
4817 case SVGA_3D_CMD_DX_GROW_COTABLE:
4818 {
4819 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
4820 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4821 vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd);
4822 break;
4823 }
4824
4825 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
4826 {
4827 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
4828 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4829 vmsvga3dCmdIntraSurfaceCopy(pThisCC, pCmd);
4830 break;
4831 }
4832
4833 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
4834 {
4835 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
4836 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4837 vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
4838 break;
4839 }
4840
4841 case SVGA_3D_CMD_DX_RESOLVE_COPY:
4842 {
4843 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
4844 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4845 vmsvga3dCmdDXResolveCopy(pThisCC, pCmd);
4846 break;
4847 }
4848
4849 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
4850 {
4851 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
4852 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4853 vmsvga3dCmdDXPredResolveCopy(pThisCC, pCmd);
4854 break;
4855 }
4856
4857 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
4858 {
4859 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
4860 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4861 vmsvga3dCmdDXPredConvertRegion(pThisCC, pCmd);
4862 break;
4863 }
4864
4865 case SVGA_3D_CMD_DX_PRED_CONVERT:
4866 {
4867 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
4868 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4869 vmsvga3dCmdDXPredConvert(pThisCC, pCmd);
4870 break;
4871 }
4872
4873 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
4874 {
4875 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
4876 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4877 vmsvga3dCmdWholeSurfaceCopy(pThisCC, pCmd);
4878 break;
4879 }
4880
4881 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
4882 {
4883 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
4884 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4885 vmsvga3dCmdDXDefineUAView(pThisCC, pCmd);
4886 break;
4887 }
4888
4889 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
4890 {
4891 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
4892 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4893 vmsvga3dCmdDXDestroyUAView(pThisCC, pCmd);
4894 break;
4895 }
4896
4897 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
4898 {
4899 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
4900 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4901 vmsvga3dCmdDXClearUAViewUint(pThisCC, pCmd);
4902 break;
4903 }
4904
4905 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
4906 {
4907 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
4908 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4909 vmsvga3dCmdDXClearUAViewFloat(pThisCC, pCmd);
4910 break;
4911 }
4912
4913 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
4914 {
4915 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
4916 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4917 vmsvga3dCmdDXCopyStructureCount(pThisCC, pCmd);
4918 break;
4919 }
4920
4921 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
4922 {
4923 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
4924 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4925 vmsvga3dCmdDXSetUAViews(pThisCC, pCmd);
4926 break;
4927 }
4928
4929 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
4930 {
4931 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
4932 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4933 vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, pCmd);
4934 break;
4935 }
4936
4937 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
4938 {
4939 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
4940 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4941 vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, pCmd);
4942 break;
4943 }
4944
4945 case SVGA_3D_CMD_DX_DISPATCH:
4946 {
4947 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
4948 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4949 vmsvga3dCmdDXDispatch(pThisCC, pCmd);
4950 break;
4951 }
4952
4953 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
4954 {
4955 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
4956 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4957 vmsvga3dCmdDXDispatchIndirect(pThisCC, pCmd);
4958 break;
4959 }
4960
4961 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
4962 {
4963 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
4964 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4965 vmsvga3dCmdWriteZeroSurface(pThisCC, pCmd);
4966 break;
4967 }
4968
4969 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
4970 {
4971 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
4972 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4973 vmsvga3dCmdHintZeroSurface(pThisCC, pCmd);
4974 break;
4975 }
4976
4977 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
4978 {
4979 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
4980 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4981 vmsvga3dCmdDXTransferToBuffer(pThisCC, pCmd);
4982 break;
4983 }
4984
4985 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
4986 {
4987 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
4988 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4989 vmsvga3dCmdDXSetStructureCount(pThisCC, pCmd);
4990 break;
4991 }
4992
4993 case SVGA_3D_CMD_LOGICOPS_BITBLT:
4994 {
4995 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
4996 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4997 vmsvga3dCmdLogicOpsBitBlt(pThisCC, pCmd);
4998 break;
4999 }
5000
5001 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5002 {
5003 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5004 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5005 vmsvga3dCmdLogicOpsTransBlt(pThisCC, pCmd);
5006 break;
5007 }
5008
5009 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5010 {
5011 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5012 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5013 vmsvga3dCmdLogicOpsStretchBlt(pThisCC, pCmd);
5014 break;
5015 }
5016
5017 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5018 {
5019 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5020 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5021 vmsvga3dCmdLogicOpsColorFill(pThisCC, pCmd);
5022 break;
5023 }
5024
5025 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5026 {
5027 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5028 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5029 vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, pCmd);
5030 break;
5031 }
5032
5033 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5034 {
5035 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5036 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5037 vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, pCmd);
5038 break;
5039 }
5040
5041 case SVGA_3D_CMD_RESERVED2_1:
5042 {
5043 VMSVGA_3D_CMD_NOTIMPL();
5044 break;
5045 }
5046
5047 case SVGA_3D_CMD_RESERVED2_2:
5048 {
5049 VMSVGA_3D_CMD_NOTIMPL();
5050 break;
5051 }
5052
5053 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5054 {
5055 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5056 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5057 vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
5058 break;
5059 }
5060
5061 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5062 {
5063 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5064 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5065 vmsvga3dCmdDXSetCSUAViews(pThisCC, pCmd);
5066 break;
5067 }
5068
5069 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5070 {
5071 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5072 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5073 vmsvga3dCmdDXSetMinLOD(pThisCC, pCmd);
5074 break;
5075 }
5076
5077 case SVGA_3D_CMD_RESERVED2_3:
5078 {
5079 VMSVGA_3D_CMD_NOTIMPL();
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_RESERVED2_4:
5084 {
5085 VMSVGA_3D_CMD_NOTIMPL();
5086 break;
5087 }
5088
5089 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5090 {
5091 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5092 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5093 vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, pCmd);
5094 break;
5095 }
5096
5097 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5098 {
5099 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5100 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5101 vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, pCmd);
5102 break;
5103 }
5104
5105 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5106 {
5107 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5108 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5109 vmsvga3dCmdDXSetShaderIface(pThisCC, pCmd);
5110 break;
5111 }
5112
5113 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5114 {
5115 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5116 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5117 vmsvga3dCmdDXBindStreamOutput(pThisCC, pCmd);
5118 break;
5119 }
5120
5121 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5122 {
5123 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5124 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5125 vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, pCmd);
5126 break;
5127 }
5128
5129 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5130 {
5131 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5132 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5133 vmsvga3dCmdDXBindShaderIface(pThisCC, pCmd);
5134 break;
5135 }
5136
5137 /* Unsupported commands. */
5138 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5139 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5140 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5141 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5142 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5143 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5144 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5145 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5146 /* Prevent the compiler warning. */
5147 case SVGA_3D_CMD_LEGACY_BASE:
5148 case SVGA_3D_CMD_MAX:
5149 case SVGA_3D_CMD_FUTURE_MAX:
5150 /* No 'default' case */
5151 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5152 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5153 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5154 rcParse = VERR_NOT_IMPLEMENTED;
5155 break;
5156 }
5157
5158 return rcParse;
5159}
5160# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5161#endif /* VBOX_WITH_VMSVGA3D */
5162
5163
5164/*
5165 *
5166 * Handlers for FIFO commands.
5167 *
5168 * Every handler takes the following parameters:
5169 *
5170 * pThis The shared VGA/VMSVGA state.
5171 * pThisCC The VGA/VMSVGA state for ring-3.
5172 * pCmd The command data.
5173 */
5174
5175
5176/* SVGA_CMD_UPDATE */
5177void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5178{
5179 RT_NOREF(pThis);
5180 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5181
5182 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5183 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5184
5185 /** @todo Multiple screens? */
5186 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5187 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5188 return;
5189
5190 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5191}
5192
5193
5194/* SVGA_CMD_UPDATE_VERBOSE */
5195void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5196{
5197 RT_NOREF(pThis);
5198 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5199
5200 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5201 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5202
5203 /** @todo Multiple screens? */
5204 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5205 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5206 return;
5207
5208 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5209}
5210
5211
5212/* SVGA_CMD_RECT_FILL */
5213void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5214{
5215 RT_NOREF(pThis, pCmd);
5216 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5217
5218 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5219 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5220 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5221}
5222
5223
5224/* SVGA_CMD_RECT_COPY */
5225void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5226{
5227 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5228
5229 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5230 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5231
5232 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5233 AssertPtrReturnVoid(pScreen);
5234
5235 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5236 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5237 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5238 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5239 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5240 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5241 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5242
5243 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5244 pCmd->width, pCmd->height, pThis->vram_size);
5245 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5246}
5247
5248
5249/* SVGA_CMD_RECT_ROP_COPY */
5250void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5251{
5252 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5253
5254 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5255 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5256
5257 if (pCmd->rop != SVGA_ROP_COPY)
5258 {
5259 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5260 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5261 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5262 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5263 */
5264 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5265 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5266 return;
5267 }
5268
5269 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5270 AssertPtrReturnVoid(pScreen);
5271
5272 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5273 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5274 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5275 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5276 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5277 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5278 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5279
5280 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5281 pCmd->width, pCmd->height, pThis->vram_size);
5282 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5283}
5284
5285
5286/* SVGA_CMD_DISPLAY_CURSOR */
5287void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5288{
5289 RT_NOREF(pThis, pCmd);
5290 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5291
5292 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5293 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5294 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5295}
5296
5297
5298/* SVGA_CMD_MOVE_CURSOR */
5299void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5300{
5301 RT_NOREF(pThis, pCmd);
5302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5303
5304 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5305 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5306 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5307}
5308
5309
5310/* SVGA_CMD_DEFINE_CURSOR */
5311void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5312{
5313 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5314
5315 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5316 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5317 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5318
5319 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5320 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5321 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5322 RT_UNTRUSTED_VALIDATED_FENCE();
5323
5324 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5325 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5326 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5327
5328 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5329 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5330
5331 uint32_t const cx = pCmd->width;
5332 uint32_t const cy = pCmd->height;
5333
5334 /*
5335 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5336 * The AND data uses 8-bit aligned scanlines.
5337 * The XOR data must be starting on a 32-bit boundrary.
5338 */
5339 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5340 uint32_t cbDstAndMask = cbDstAndLine * cy;
5341 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5342 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5343
5344 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5345 AssertReturnVoid(pbCopy);
5346
5347 /* Convert the AND mask. */
5348 uint8_t *pbDst = pbCopy;
5349 uint8_t const *pbSrc = pbSrcAndMask;
5350 switch (pCmd->andMaskDepth)
5351 {
5352 case 1:
5353 if (cbSrcAndLine == cbDstAndLine)
5354 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5355 else
5356 {
5357 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5358 for (uint32_t y = 0; y < cy; y++)
5359 {
5360 memcpy(pbDst, pbSrc, cbDstAndLine);
5361 pbDst += cbDstAndLine;
5362 pbSrc += cbSrcAndLine;
5363 }
5364 }
5365 break;
5366 /* Should take the XOR mask into account for the multi-bit AND mask. */
5367 case 8:
5368 for (uint32_t y = 0; y < cy; y++)
5369 {
5370 for (uint32_t x = 0; x < cx; )
5371 {
5372 uint8_t bDst = 0;
5373 uint8_t fBit = 0x80;
5374 do
5375 {
5376 uintptr_t const idxPal = pbSrc[x] * 3;
5377 if ((( pThis->last_palette[idxPal]
5378 | (pThis->last_palette[idxPal] >> 8)
5379 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5380 bDst |= fBit;
5381 fBit >>= 1;
5382 x++;
5383 } while (x < cx && (x & 7));
5384 pbDst[(x - 1) / 8] = bDst;
5385 }
5386 pbDst += cbDstAndLine;
5387 pbSrc += cbSrcAndLine;
5388 }
5389 break;
5390 case 15:
5391 for (uint32_t y = 0; y < cy; y++)
5392 {
5393 for (uint32_t x = 0; x < cx; )
5394 {
5395 uint8_t bDst = 0;
5396 uint8_t fBit = 0x80;
5397 do
5398 {
5399 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5400 bDst |= fBit;
5401 fBit >>= 1;
5402 x++;
5403 } while (x < cx && (x & 7));
5404 pbDst[(x - 1) / 8] = bDst;
5405 }
5406 pbDst += cbDstAndLine;
5407 pbSrc += cbSrcAndLine;
5408 }
5409 break;
5410 case 16:
5411 for (uint32_t y = 0; y < cy; y++)
5412 {
5413 for (uint32_t x = 0; x < cx; )
5414 {
5415 uint8_t bDst = 0;
5416 uint8_t fBit = 0x80;
5417 do
5418 {
5419 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5420 bDst |= fBit;
5421 fBit >>= 1;
5422 x++;
5423 } while (x < cx && (x & 7));
5424 pbDst[(x - 1) / 8] = bDst;
5425 }
5426 pbDst += cbDstAndLine;
5427 pbSrc += cbSrcAndLine;
5428 }
5429 break;
5430 case 24:
5431 for (uint32_t y = 0; y < cy; y++)
5432 {
5433 for (uint32_t x = 0; x < cx; )
5434 {
5435 uint8_t bDst = 0;
5436 uint8_t fBit = 0x80;
5437 do
5438 {
5439 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
5440 bDst |= fBit;
5441 fBit >>= 1;
5442 x++;
5443 } while (x < cx && (x & 7));
5444 pbDst[(x - 1) / 8] = bDst;
5445 }
5446 pbDst += cbDstAndLine;
5447 pbSrc += cbSrcAndLine;
5448 }
5449 break;
5450 case 32:
5451 for (uint32_t y = 0; y < cy; y++)
5452 {
5453 for (uint32_t x = 0; x < cx; )
5454 {
5455 uint8_t bDst = 0;
5456 uint8_t fBit = 0x80;
5457 do
5458 {
5459 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
5460 bDst |= fBit;
5461 fBit >>= 1;
5462 x++;
5463 } while (x < cx && (x & 7));
5464 pbDst[(x - 1) / 8] = bDst;
5465 }
5466 pbDst += cbDstAndLine;
5467 pbSrc += cbSrcAndLine;
5468 }
5469 break;
5470 default:
5471 RTMemFreeZ(pbCopy, cbCopy);
5472 AssertFailedReturnVoid();
5473 }
5474
5475 /* Convert the XOR mask. */
5476 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
5477 pbSrc = pbSrcXorMask;
5478 switch (pCmd->xorMaskDepth)
5479 {
5480 case 1:
5481 for (uint32_t y = 0; y < cy; y++)
5482 {
5483 for (uint32_t x = 0; x < cx; )
5484 {
5485 /* most significant bit is the left most one. */
5486 uint8_t bSrc = pbSrc[x / 8];
5487 do
5488 {
5489 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
5490 bSrc <<= 1;
5491 x++;
5492 } while ((x & 7) && x < cx);
5493 }
5494 pbSrc += cbSrcXorLine;
5495 }
5496 break;
5497 case 8:
5498 for (uint32_t y = 0; y < cy; y++)
5499 {
5500 for (uint32_t x = 0; x < cx; x++)
5501 {
5502 uint32_t u = pThis->last_palette[pbSrc[x]];
5503 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
5504 }
5505 pbSrc += cbSrcXorLine;
5506 }
5507 break;
5508 case 15: /* Src: RGB-5-5-5 */
5509 for (uint32_t y = 0; y < cy; y++)
5510 {
5511 for (uint32_t x = 0; x < cx; x++)
5512 {
5513 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
5514 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
5515 ((uValue >> 5) & 0x1f) << 3,
5516 ((uValue >> 10) & 0x1f) << 3, 0);
5517 }
5518 pbSrc += cbSrcXorLine;
5519 }
5520 break;
5521 case 16: /* Src: RGB-5-6-5 */
5522 for (uint32_t y = 0; y < cy; y++)
5523 {
5524 for (uint32_t x = 0; x < cx; x++)
5525 {
5526 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
5527 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
5528 ((uValue >> 5) & 0x3f) << 2,
5529 ((uValue >> 11) & 0x1f) << 3, 0);
5530 }
5531 pbSrc += cbSrcXorLine;
5532 }
5533 break;
5534 case 24:
5535 for (uint32_t y = 0; y < cy; y++)
5536 {
5537 for (uint32_t x = 0; x < cx; x++)
5538 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
5539 pbSrc += cbSrcXorLine;
5540 }
5541 break;
5542 case 32:
5543 for (uint32_t y = 0; y < cy; y++)
5544 {
5545 for (uint32_t x = 0; x < cx; x++)
5546 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
5547 pbSrc += cbSrcXorLine;
5548 }
5549 break;
5550 default:
5551 RTMemFreeZ(pbCopy, cbCopy);
5552 AssertFailedReturnVoid();
5553 }
5554
5555 /*
5556 * Pass it to the frontend/whatever.
5557 */
5558 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
5559 cx, cy, pbCopy, cbCopy);
5560}
5561
5562
5563/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
5564void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
5565{
5566 RT_NOREF(pThis);
5567 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5568
5569 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
5570 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
5571
5572 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
5573 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5574 RT_UNTRUSTED_VALIDATED_FENCE();
5575
5576 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
5577 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
5578 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
5579 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
5580 uint32_t cbCursorShape = cbAndMask + cbXorMask;
5581
5582 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
5583 AssertPtrReturnVoid(pCursorCopy);
5584
5585 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
5586 memset(pCursorCopy, 0xff, cbAndMask);
5587 /* Colour data */
5588 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
5589
5590 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
5591 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
5592}
5593
5594
5595/* SVGA_CMD_ESCAPE */
5596void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
5597{
5598 RT_NOREF(pThis);
5599 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5600
5601 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
5602
5603 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
5604 {
5605 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
5606 RT_UNTRUSTED_VALIDATED_FENCE();
5607
5608 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
5609 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
5610
5611 switch (cmd)
5612 {
5613 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
5614 {
5615 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
5616 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
5617 RT_UNTRUSTED_VALIDATED_FENCE();
5618
5619 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
5620
5621 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
5622 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
5623 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
5624 RT_NOREF_PV(pVideoCmd);
5625 break;
5626 }
5627
5628 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
5629 {
5630 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
5631 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
5632 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
5633 RT_NOREF_PV(pVideoCmd);
5634 break;
5635 }
5636
5637 default:
5638 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
5639 break;
5640 }
5641 }
5642 else
5643 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
5644}
5645
5646
5647/* SVGA_CMD_DEFINE_SCREEN */
5648void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
5649{
5650 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5651
5652 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
5653 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
5654 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
5655 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
5656
5657 uint32_t const idScreen = pCmd->screen.id;
5658 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
5659
5660 uint32_t const uWidth = pCmd->screen.size.width;
5661 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
5662
5663 uint32_t const uHeight = pCmd->screen.size.height;
5664 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
5665
5666 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
5667 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
5668 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
5669
5670 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
5671 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
5672
5673 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
5674 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
5675 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
5676 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
5677 RT_UNTRUSTED_VALIDATED_FENCE();
5678
5679 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
5680 pScreen->fDefined = true;
5681 pScreen->fModified = true;
5682 pScreen->fuScreen = pCmd->screen.flags;
5683 pScreen->idScreen = idScreen;
5684 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
5685 {
5686 /* Not blanked. */
5687 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
5688 RT_UNTRUSTED_VALIDATED_FENCE();
5689
5690 pScreen->xOrigin = pCmd->screen.root.x;
5691 pScreen->yOrigin = pCmd->screen.root.y;
5692 pScreen->cWidth = uWidth;
5693 pScreen->cHeight = uHeight;
5694 pScreen->offVRAM = uScreenOffset;
5695 pScreen->cbPitch = cbPitch;
5696 pScreen->cBpp = 32;
5697 }
5698 else
5699 {
5700 /* Screen blanked. Keep old values. */
5701 }
5702
5703 pThis->svga.fGFBRegisters = false;
5704 vmsvgaR3ChangeMode(pThis, pThisCC);
5705
5706#ifdef VBOX_WITH_VMSVGA3D
5707 if (RT_LIKELY(pThis->svga.f3DEnabled))
5708 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
5709#endif
5710}
5711
5712
5713/* SVGA_CMD_DESTROY_SCREEN */
5714void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
5715{
5716 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5717
5718 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
5719 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
5720
5721 uint32_t const idScreen = pCmd->screenId;
5722 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
5723 RT_UNTRUSTED_VALIDATED_FENCE();
5724
5725 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
5726 pScreen->fModified = true;
5727 pScreen->fDefined = false;
5728 pScreen->idScreen = idScreen;
5729
5730#ifdef VBOX_WITH_VMSVGA3D
5731 if (RT_LIKELY(pThis->svga.f3DEnabled))
5732 vmsvga3dDestroyScreen(pThisCC, pScreen);
5733#endif
5734 vmsvgaR3ChangeMode(pThis, pThisCC);
5735}
5736
5737
5738/* SVGA_CMD_DEFINE_GMRFB */
5739void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
5740{
5741 RT_NOREF(pThis);
5742 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5743
5744 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
5745 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
5746 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
5747
5748 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
5749 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
5750 pSvgaR3State->GMRFB.format = pCmd->format;
5751}
5752
5753
5754/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
5755void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
5756{
5757 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5758
5759 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
5760 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
5761 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
5762
5763 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
5764 RT_UNTRUSTED_VALIDATED_FENCE();
5765
5766 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
5767 AssertPtrReturnVoid(pScreen);
5768
5769 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
5770 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
5771
5772 /* Clip destRect to the screen dimensions. */
5773 SVGASignedRect screenRect;
5774 screenRect.left = 0;
5775 screenRect.top = 0;
5776 screenRect.right = pScreen->cWidth;
5777 screenRect.bottom = pScreen->cHeight;
5778 SVGASignedRect clipRect = pCmd->destRect;
5779 vmsvgaR3ClipRect(&screenRect, &clipRect);
5780 RT_UNTRUSTED_VALIDATED_FENCE();
5781
5782 uint32_t const width = clipRect.right - clipRect.left;
5783 uint32_t const height = clipRect.bottom - clipRect.top;
5784
5785 if ( width == 0
5786 || height == 0)
5787 return; /* Nothing to do. */
5788
5789 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
5790 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
5791
5792 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
5793 * Prepare parameters for vmsvgaR3GmrTransfer.
5794 */
5795 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
5796
5797 /* Destination: host buffer which describes the screen 0 VRAM.
5798 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
5799 */
5800 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
5801 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
5802 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
5803 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
5804 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
5805 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
5806 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
5807 + cbScanline * clipRect.top;
5808 int32_t const cbHstPitch = cbScanline;
5809
5810 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
5811 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
5812 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
5813 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
5814 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
5815
5816 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
5817 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5818 gstPtr, offGst, cbGstPitch,
5819 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
5820 AssertRC(rc);
5821 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
5822}
5823
5824
5825/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
5826void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
5827{
5828 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5829
5830 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
5831 /* Note! This can fetch 3d render results as well!! */
5832 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
5833 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
5834
5835 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
5836 RT_UNTRUSTED_VALIDATED_FENCE();
5837
5838 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
5839 AssertPtrReturnVoid(pScreen);
5840
5841 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
5842 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
5843
5844 /* Clip destRect to the screen dimensions. */
5845 SVGASignedRect screenRect;
5846 screenRect.left = 0;
5847 screenRect.top = 0;
5848 screenRect.right = pScreen->cWidth;
5849 screenRect.bottom = pScreen->cHeight;
5850 SVGASignedRect clipRect = pCmd->srcRect;
5851 vmsvgaR3ClipRect(&screenRect, &clipRect);
5852 RT_UNTRUSTED_VALIDATED_FENCE();
5853
5854 uint32_t const width = clipRect.right - clipRect.left;
5855 uint32_t const height = clipRect.bottom - clipRect.top;
5856
5857 if ( width == 0
5858 || height == 0)
5859 return; /* Nothing to do. */
5860
5861 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
5862 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
5863
5864 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
5865 * Prepare parameters for vmsvgaR3GmrTransfer.
5866 */
5867 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
5868
5869 /* Source: host buffer which describes the screen 0 VRAM.
5870 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
5871 */
5872 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
5873 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
5874 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
5875 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
5876 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
5877 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
5878 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
5879 + cbScanline * clipRect.top;
5880 int32_t const cbHstPitch = cbScanline;
5881
5882 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
5883 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
5884 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
5885 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
5886 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
5887
5888 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
5889 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5890 gstPtr, offGst, cbGstPitch,
5891 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
5892 AssertRC(rc);
5893}
5894
5895
5896/* SVGA_CMD_ANNOTATION_FILL */
5897void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
5898{
5899 RT_NOREF(pThis);
5900 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5901
5902 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
5903 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
5904
5905 pSvgaR3State->colorAnnotation = pCmd->color;
5906}
5907
5908
5909/* SVGA_CMD_ANNOTATION_COPY */
5910void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
5911{
5912 RT_NOREF(pThis, pCmd);
5913 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5914
5915 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
5916 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
5917
5918 AssertFailed();
5919}
5920
5921
5922#ifdef VBOX_WITH_VMSVGA3D
5923/* SVGA_CMD_DEFINE_GMR2 */
5924void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
5925{
5926 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5927
5928 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
5929 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
5930
5931 /* Validate current GMR id. */
5932 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
5933 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
5934 RT_UNTRUSTED_VALIDATED_FENCE();
5935
5936 if (!pCmd->numPages)
5937 {
5938 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
5939 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
5940 }
5941 else
5942 {
5943 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
5944 if (pGMR->cMaxPages)
5945 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
5946
5947 /* Not sure if we should always free the descriptor, but for simplicity
5948 we do so if the new size is smaller than the current. */
5949 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
5950 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
5951 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
5952
5953 pGMR->cMaxPages = pCmd->numPages;
5954 /* The rest is done by the REMAP_GMR2 command. */
5955 }
5956}
5957
5958
5959/* SVGA_CMD_REMAP_GMR2 */
5960void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
5961{
5962 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5963
5964 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
5965 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
5966
5967 /* Validate current GMR id and size. */
5968 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
5969 RT_UNTRUSTED_VALIDATED_FENCE();
5970 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
5971 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
5972 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
5973 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
5974
5975 if (pCmd->numPages == 0)
5976 return;
5977 RT_UNTRUSTED_VALIDATED_FENCE();
5978
5979 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
5980 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
5981
5982 /*
5983 * We flatten the existing descriptors into a page array, overwrite the
5984 * pages specified in this command and then recompress the descriptor.
5985 */
5986 /** @todo Optimize the GMR remap algorithm! */
5987
5988 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
5989 uint64_t *paNewPage64 = NULL;
5990 if (pGMR->paDesc)
5991 {
5992 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
5993
5994 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
5995 AssertPtrReturnVoid(paNewPage64);
5996
5997 uint32_t idxPage = 0;
5998 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
5999 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6000 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6001 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6002 RT_UNTRUSTED_VALIDATED_FENCE();
6003 }
6004
6005 /* Free the old GMR if present. */
6006 if (pGMR->paDesc)
6007 RTMemFree(pGMR->paDesc);
6008
6009 /* Allocate the maximum amount possible (everything non-continuous) */
6010 PVMSVGAGMRDESCRIPTOR paDescs;
6011 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6012 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6013
6014 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6015 {
6016 /** @todo */
6017 AssertFailed();
6018 pGMR->numDescriptors = 0;
6019 }
6020 else
6021 {
6022 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6023 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6024 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6025
6026 uint32_t cPages;
6027 if (paNewPage64)
6028 {
6029 /* Overwrite the old page array with the new page values. */
6030 if (fGCPhys64)
6031 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6032 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6033 else
6034 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6035 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6036
6037 /* Use the updated page array instead of the command data. */
6038 fGCPhys64 = true;
6039 paPages64 = paNewPage64;
6040 cPages = cNewTotalPages;
6041 }
6042 else
6043 cPages = pCmd->numPages;
6044
6045 /* The first page. */
6046 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6047 * applied to paNewPage64. */
6048 RTGCPHYS GCPhys;
6049 if (fGCPhys64)
6050 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6051 else
6052 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6053 paDescs[0].GCPhys = GCPhys;
6054 paDescs[0].numPages = 1;
6055
6056 /* Subsequent pages. */
6057 uint32_t iDescriptor = 0;
6058 for (uint32_t i = 1; i < cPages; i++)
6059 {
6060 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6061 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6062 else
6063 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6064
6065 /* Continuous physical memory? */
6066 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6067 {
6068 Assert(paDescs[iDescriptor].numPages);
6069 paDescs[iDescriptor].numPages++;
6070 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6071 }
6072 else
6073 {
6074 iDescriptor++;
6075 paDescs[iDescriptor].GCPhys = GCPhys;
6076 paDescs[iDescriptor].numPages = 1;
6077 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6078 }
6079 }
6080
6081 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6082 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6083 pGMR->numDescriptors = iDescriptor + 1;
6084 }
6085
6086 if (paNewPage64)
6087 RTMemFree(paNewPage64);
6088}
6089
6090
6091/**
6092 * Free the specified GMR
6093 *
6094 * @param pThisCC The VGA/VMSVGA state for ring-3.
6095 * @param idGMR GMR id
6096 */
6097void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6098{
6099 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6100
6101 /* Free the old descriptor if present. */
6102 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6103 if ( pGMR->numDescriptors
6104 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6105 {
6106# ifdef DEBUG_GMR_ACCESS
6107 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6108# endif
6109
6110 Assert(pGMR->paDesc);
6111 RTMemFree(pGMR->paDesc);
6112 pGMR->paDesc = NULL;
6113 pGMR->numDescriptors = 0;
6114 pGMR->cbTotal = 0;
6115 pGMR->cMaxPages = 0;
6116 }
6117 Assert(!pGMR->cMaxPages);
6118 Assert(!pGMR->cbTotal);
6119}
6120#endif /* VBOX_WITH_VMSVGA3D */
6121
6122
6123/**
6124 * Copy between a GMR and a host memory buffer.
6125 *
6126 * @returns VBox status code.
6127 * @param pThis The shared VGA/VMSVGA instance data.
6128 * @param pThisCC The VGA/VMSVGA state for ring-3.
6129 * @param enmTransferType Transfer type (read/write)
6130 * @param pbHstBuf Host buffer pointer (valid)
6131 * @param cbHstBuf Size of host buffer (valid)
6132 * @param offHst Host buffer offset of the first scanline
6133 * @param cbHstPitch Destination buffer pitch
6134 * @param gstPtr GMR description
6135 * @param offGst Guest buffer offset of the first scanline
6136 * @param cbGstPitch Guest buffer pitch
6137 * @param cbWidth Width in bytes to copy
6138 * @param cHeight Number of scanllines to copy
6139 */
6140int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6141 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6142 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6143 uint32_t cbWidth, uint32_t cHeight)
6144{
6145 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6146 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6147 int rc;
6148
6149 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6150 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6151 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6152 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6153 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6154
6155 PGMR pGMR;
6156 uint32_t cbGmr; /* The GMR size in bytes. */
6157 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6158 {
6159 pGMR = NULL;
6160 cbGmr = pThis->vram_size;
6161 }
6162 else
6163 {
6164 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6165 RT_UNTRUSTED_VALIDATED_FENCE();
6166 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6167 cbGmr = pGMR->cbTotal;
6168 }
6169
6170 /*
6171 * GMR
6172 */
6173 /* Calculate GMR offset of the data to be copied. */
6174 AssertMsgReturn(gstPtr.offset < cbGmr,
6175 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6176 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6177 VERR_INVALID_PARAMETER);
6178 RT_UNTRUSTED_VALIDATED_FENCE();
6179 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6180 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6181 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6182 VERR_INVALID_PARAMETER);
6183 RT_UNTRUSTED_VALIDATED_FENCE();
6184 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6185
6186 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6187 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6188 AssertMsgReturn(cbGmrScanline != 0,
6189 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6190 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6191 VERR_INVALID_PARAMETER);
6192 RT_UNTRUSTED_VALIDATED_FENCE();
6193 AssertMsgReturn(cbWidth <= cbGmrScanline,
6194 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6195 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6196 VERR_INVALID_PARAMETER);
6197 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6198 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6199 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6200 VERR_INVALID_PARAMETER);
6201 RT_UNTRUSTED_VALIDATED_FENCE();
6202
6203 /* How many bytes are available for the data in the GMR. */
6204 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6205
6206 /* How many scanlines would fit into the available data. */
6207 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6208 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6209 if (cbWidth <= cbGmrLastScanline)
6210 ++cGmrScanlines;
6211
6212 if (cHeight > cGmrScanlines)
6213 cHeight = cGmrScanlines;
6214
6215 AssertMsgReturn(cHeight > 0,
6216 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6217 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6218 VERR_INVALID_PARAMETER);
6219 RT_UNTRUSTED_VALIDATED_FENCE();
6220
6221 /*
6222 * Host buffer.
6223 */
6224 AssertMsgReturn(offHst < cbHstBuf,
6225 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6226 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6227 VERR_INVALID_PARAMETER);
6228
6229 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6230 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6231 AssertMsgReturn(cbHstScanline != 0,
6232 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6233 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6234 VERR_INVALID_PARAMETER);
6235 AssertMsgReturn(cbWidth <= cbHstScanline,
6236 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6237 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6238 VERR_INVALID_PARAMETER);
6239 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6240 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6241 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6242 VERR_INVALID_PARAMETER);
6243
6244 /* How many bytes are available for the data in the buffer. */
6245 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6246
6247 /* How many scanlines would fit into the available data. */
6248 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6249 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6250 if (cbWidth <= cbHstLastScanline)
6251 ++cHstScanlines;
6252
6253 if (cHeight > cHstScanlines)
6254 cHeight = cHstScanlines;
6255
6256 AssertMsgReturn(cHeight > 0,
6257 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6258 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6259 VERR_INVALID_PARAMETER);
6260
6261 uint8_t *pbHst = pbHstBuf + offHst;
6262
6263 /* Shortcut for the framebuffer. */
6264 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6265 {
6266 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6267
6268 uint8_t const *pbSrc;
6269 int32_t cbSrcPitch;
6270 uint8_t *pbDst;
6271 int32_t cbDstPitch;
6272
6273 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6274 {
6275 pbSrc = pbHst;
6276 cbSrcPitch = cbHstPitch;
6277 pbDst = pbGst;
6278 cbDstPitch = cbGstPitch;
6279 }
6280 else
6281 {
6282 pbSrc = pbGst;
6283 cbSrcPitch = cbGstPitch;
6284 pbDst = pbHst;
6285 cbDstPitch = cbHstPitch;
6286 }
6287
6288 if ( cbWidth == (uint32_t)cbGstPitch
6289 && cbGstPitch == cbHstPitch)
6290 {
6291 /* Entire scanlines, positive pitch. */
6292 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6293 }
6294 else
6295 {
6296 for (uint32_t i = 0; i < cHeight; ++i)
6297 {
6298 memcpy(pbDst, pbSrc, cbWidth);
6299
6300 pbDst += cbDstPitch;
6301 pbSrc += cbSrcPitch;
6302 }
6303 }
6304 return VINF_SUCCESS;
6305 }
6306
6307 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6308 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6309
6310 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6311 uint32_t iDesc = 0; /* Index in the descriptor array. */
6312 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6313 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6314 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6315 for (uint32_t i = 0; i < cHeight; ++i)
6316 {
6317 uint32_t cbCurrentWidth = cbWidth;
6318 uint32_t offGmrCurrent = offGmrScanline;
6319 uint8_t *pbCurrentHost = pbHstScanline;
6320
6321 /* Find the right descriptor */
6322 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6323 {
6324 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6325 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6326 ++iDesc;
6327 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6328 }
6329
6330 while (cbCurrentWidth)
6331 {
6332 uint32_t cbToCopy;
6333
6334 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6335 {
6336 cbToCopy = cbCurrentWidth;
6337 }
6338 else
6339 {
6340 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6341 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6342 }
6343
6344 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6345
6346 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6347
6348 /*
6349 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
6350 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
6351 * see @bugref{9654#c75}.
6352 */
6353 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6354 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6355 else
6356 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6357 AssertRCBreak(rc);
6358
6359 cbCurrentWidth -= cbToCopy;
6360 offGmrCurrent += cbToCopy;
6361 pbCurrentHost += cbToCopy;
6362
6363 /* Go to the next descriptor if there's anything left. */
6364 if (cbCurrentWidth)
6365 {
6366 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6367 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6368 ++iDesc;
6369 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6370 }
6371 }
6372
6373 offGmrScanline += cbGstPitch;
6374 pbHstScanline += cbHstPitch;
6375 }
6376
6377 return VINF_SUCCESS;
6378}
6379
6380
6381/**
6382 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6383 *
6384 * @param pSizeSrc Source surface dimensions.
6385 * @param pSizeDest Destination surface dimensions.
6386 * @param pBox Coordinates to be clipped.
6387 */
6388void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6389{
6390 /* Src x, w */
6391 if (pBox->srcx > pSizeSrc->width)
6392 pBox->srcx = pSizeSrc->width;
6393 if (pBox->w > pSizeSrc->width - pBox->srcx)
6394 pBox->w = pSizeSrc->width - pBox->srcx;
6395
6396 /* Src y, h */
6397 if (pBox->srcy > pSizeSrc->height)
6398 pBox->srcy = pSizeSrc->height;
6399 if (pBox->h > pSizeSrc->height - pBox->srcy)
6400 pBox->h = pSizeSrc->height - pBox->srcy;
6401
6402 /* Src z, d */
6403 if (pBox->srcz > pSizeSrc->depth)
6404 pBox->srcz = pSizeSrc->depth;
6405 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6406 pBox->d = pSizeSrc->depth - pBox->srcz;
6407
6408 /* Dest x, w */
6409 if (pBox->x > pSizeDest->width)
6410 pBox->x = pSizeDest->width;
6411 if (pBox->w > pSizeDest->width - pBox->x)
6412 pBox->w = pSizeDest->width - pBox->x;
6413
6414 /* Dest y, h */
6415 if (pBox->y > pSizeDest->height)
6416 pBox->y = pSizeDest->height;
6417 if (pBox->h > pSizeDest->height - pBox->y)
6418 pBox->h = pSizeDest->height - pBox->y;
6419
6420 /* Dest z, d */
6421 if (pBox->z > pSizeDest->depth)
6422 pBox->z = pSizeDest->depth;
6423 if (pBox->d > pSizeDest->depth - pBox->z)
6424 pBox->d = pSizeDest->depth - pBox->z;
6425}
6426
6427
6428/**
6429 * Unsigned coordinates in pBox. Clip to [0; pSize).
6430 *
6431 * @param pSize Source surface dimensions.
6432 * @param pBox Coordinates to be clipped.
6433 */
6434void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6435{
6436 /* x, w */
6437 if (pBox->x > pSize->width)
6438 pBox->x = pSize->width;
6439 if (pBox->w > pSize->width - pBox->x)
6440 pBox->w = pSize->width - pBox->x;
6441
6442 /* y, h */
6443 if (pBox->y > pSize->height)
6444 pBox->y = pSize->height;
6445 if (pBox->h > pSize->height - pBox->y)
6446 pBox->h = pSize->height - pBox->y;
6447
6448 /* z, d */
6449 if (pBox->z > pSize->depth)
6450 pBox->z = pSize->depth;
6451 if (pBox->d > pSize->depth - pBox->z)
6452 pBox->d = pSize->depth - pBox->z;
6453}
6454
6455
6456/**
6457 * Clip.
6458 *
6459 * @param pBound Bounding rectangle.
6460 * @param pRect Rectangle to be clipped.
6461 */
6462void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
6463{
6464 int32_t left;
6465 int32_t top;
6466 int32_t right;
6467 int32_t bottom;
6468
6469 /* Right order. */
6470 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
6471 if (pRect->left < pRect->right)
6472 {
6473 left = pRect->left;
6474 right = pRect->right;
6475 }
6476 else
6477 {
6478 left = pRect->right;
6479 right = pRect->left;
6480 }
6481 if (pRect->top < pRect->bottom)
6482 {
6483 top = pRect->top;
6484 bottom = pRect->bottom;
6485 }
6486 else
6487 {
6488 top = pRect->bottom;
6489 bottom = pRect->top;
6490 }
6491
6492 if (left < pBound->left)
6493 left = pBound->left;
6494 if (right < pBound->left)
6495 right = pBound->left;
6496
6497 if (left > pBound->right)
6498 left = pBound->right;
6499 if (right > pBound->right)
6500 right = pBound->right;
6501
6502 if (top < pBound->top)
6503 top = pBound->top;
6504 if (bottom < pBound->top)
6505 bottom = pBound->top;
6506
6507 if (top > pBound->bottom)
6508 top = pBound->bottom;
6509 if (bottom > pBound->bottom)
6510 bottom = pBound->bottom;
6511
6512 pRect->left = left;
6513 pRect->right = right;
6514 pRect->top = top;
6515 pRect->bottom = bottom;
6516}
6517
6518
6519/**
6520 * Clip.
6521 *
6522 * @param pBound Bounding rectangle.
6523 * @param pRect Rectangle to be clipped.
6524 */
6525void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
6526{
6527 uint32_t const leftBound = pBound->x;
6528 uint32_t const rightBound = pBound->x + pBound->w;
6529 uint32_t const topBound = pBound->y;
6530 uint32_t const bottomBound = pBound->y + pBound->h;
6531
6532 uint32_t x = pRect->x;
6533 uint32_t y = pRect->y;
6534 uint32_t w = pRect->w;
6535 uint32_t h = pRect->h;
6536
6537 /* Make sure that right and bottom coordinates can be safely computed. */
6538 if (x > rightBound)
6539 x = rightBound;
6540 if (w > rightBound - x)
6541 w = rightBound - x;
6542 if (y > bottomBound)
6543 y = bottomBound;
6544 if (h > bottomBound - y)
6545 h = bottomBound - y;
6546
6547 /* Switch from x, y, w, h to left, top, right, bottom. */
6548 uint32_t left = x;
6549 uint32_t right = x + w;
6550 uint32_t top = y;
6551 uint32_t bottom = y + h;
6552
6553 /* A standard left, right, bottom, top clipping. */
6554 if (left < leftBound)
6555 left = leftBound;
6556 if (right < leftBound)
6557 right = leftBound;
6558
6559 if (left > rightBound)
6560 left = rightBound;
6561 if (right > rightBound)
6562 right = rightBound;
6563
6564 if (top < topBound)
6565 top = topBound;
6566 if (bottom < topBound)
6567 bottom = topBound;
6568
6569 if (top > bottomBound)
6570 top = bottomBound;
6571 if (bottom > bottomBound)
6572 bottom = bottomBound;
6573
6574 /* Back to x, y, w, h representation. */
6575 pRect->x = left;
6576 pRect->y = top;
6577 pRect->w = right - left;
6578 pRect->h = bottom - top;
6579}
6580
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