VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 88798

Last change on this file since 88798 was 88788, checked in by vboxsync, 4 years ago

Devices/Graphics: a few DX commands (doxygen fix). bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 257.2 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 88788 2021-04-29 15:59:09Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344/*
345 *
346 * Guest-Backed Objects (GBO).
347 *
348 */
349
350/**
351 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
352 *
353 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
354 * @param pVM VM Handle.
355 * @param pVCpu The cross context CPU structure for the calling EMT.
356 * @param GCPhys The physical address the guest is writing to.
357 * @param pvPhys The HC mapping of that address.
358 * @param pvBuf What the guest is reading/writing.
359 * @param cbBuf How much it's reading/writing.
360 * @param enmAccessType The access type.
361 * @param enmOrigin Who is making the access.
362 * @param pvUser User argument.
363 */
364DECLCALLBACK(VBOXSTRICTRC)
365vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
366 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
367{
368 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
369
370 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
371 return VINF_PGM_HANDLER_DO_DEFAULT;
372
373 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
374 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
375 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
376 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
377
378 /*
379 * The guest is not allowed to access the memory.
380 * Set the error condition.
381 */
382 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
383
384 /* Try to find the GBO which the guest is accessing. */
385 char const *pszTarget = NULL;
386 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
387 {
388 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
389 if (pGbo->cDescriptors)
390 {
391 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
392 {
393 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
394 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
395 {
396 switch (i)
397 {
398 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
399 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
400 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
401 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
402 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
403 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
404 default: pszTarget = "Unknown OTABLE"; break;
405 }
406 break;
407 }
408 }
409 }
410 }
411
412 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
413 "%.*Rhxd\n",
414 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
415
416 return VINF_PGM_HANDLER_DO_DEFAULT;
417}
418
419
420static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
421{
422 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
423
424 /*
425 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
426 * Content of the root page depends on the ptDepth value:
427 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
428 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
429 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
430 * The code below extracts the page addresses of the GBO.
431 */
432
433 /* Verify and normalize the ptDepth value. */
434 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
435 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
436 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
437 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
438 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
439 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
440 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
441 {
442 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
443 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
444 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
445 }
446 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
447 { }
448 else
449 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
450
451 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
452
453 pGbo->cbTotal = sizeInBytes;
454 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
455
456 /* Allocate the maximum amount possible (everything non-continuous) */
457 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
458 AssertReturn(paDescriptors, VERR_NO_MEMORY);
459
460 int rc = VINF_SUCCESS;
461 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
462 {
463 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
464 RTMemFree(paDescriptors),
465 VERR_INVALID_PARAMETER);
466
467 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
468 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
469 paDescriptors[0].GCPhys = GCPhys;
470 paDescriptors[0].cPages = 1;
471 }
472 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
473 {
474 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
475 RTMemFree(paDescriptors),
476 VERR_INVALID_PARAMETER);
477
478 /* Read the root page. */
479 uint8_t au8RootPage[X86_PAGE_SIZE];
480 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
481 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
482 if (RT_SUCCESS(rc))
483 {
484 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
485 PPN *paPPN32 = (PPN *)&au8RootPage[0];
486 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
487 {
488 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
489 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
490 paDescriptors[iPPN].GCPhys = GCPhys;
491 paDescriptors[iPPN].cPages = 1;
492 }
493 }
494 }
495 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
496 {
497 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
498 RTMemFree(paDescriptors),
499 VERR_INVALID_PARAMETER);
500
501 /* Read the Level2 root page. */
502 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
503 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
504 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
505 if (RT_SUCCESS(rc))
506 {
507 uint32_t cPagesLeft = pGbo->cTotalPages;
508
509 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
510 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
511
512 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
513 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
514 {
515 /* Read the Level1 root page. */
516 uint8_t au8RootPage[X86_PAGE_SIZE];
517 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
518 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
519 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
520 if (RT_SUCCESS(rc))
521 {
522 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
523 PPN *paPPN32 = (PPN *)&au8RootPage[0];
524
525 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
526 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
527 {
528 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
529 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
530 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
531 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
532 }
533 cPagesLeft -= cPPNs;
534 }
535 }
536 }
537 }
538 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
539 {
540 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
541 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
542 paDescriptors[0].GCPhys = GCPhys;
543 paDescriptors[0].cPages = pGbo->cTotalPages;
544 }
545 else
546 {
547 AssertFailed();
548 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
549 }
550
551 /* Compress the descriptors. */
552 if (ptDepth != SVGA3D_MOBFMT_RANGE)
553 {
554 uint32_t iDescriptor = 0;
555 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
556 {
557 /* Continuous physical memory? */
558 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
559 {
560 Assert(paDescriptors[iDescriptor].cPages);
561 paDescriptors[iDescriptor].cPages++;
562 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
563 }
564 else
565 {
566 iDescriptor++;
567 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
568 paDescriptors[iDescriptor].cPages = 1;
569 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
570 }
571 }
572
573 pGbo->cDescriptors = iDescriptor + 1;
574 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
575 }
576 else
577 pGbo->cDescriptors = 1;
578
579 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
580 {
581 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
582 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
583 }
584 else
585 pGbo->paDescriptors = paDescriptors;
586
587#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
588fWriteProtected = false;
589#endif
590 if (fWriteProtected)
591 {
592 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
593 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
594 {
595 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
596 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
597 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
598 AssertRC(rc);
599 }
600 }
601
602 return VINF_SUCCESS;
603}
604
605
606static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
607{
608 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
609 {
610 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
611 {
612 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
613 {
614 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
615 AssertRC(rc);
616 }
617 }
618 RTMemFree(pGbo->paDescriptors);
619 RT_ZERO(pGbo);
620 }
621}
622
623/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
624
625typedef enum VMSVGAGboTransferDirection
626{
627 VMSVGAGboTransferDirection_Read,
628 VMSVGAGboTransferDirection_Write,
629} VMSVGAGboTransferDirection;
630
631static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
632 uint32_t off, void *pvData, uint32_t cbData,
633 VMSVGAGboTransferDirection enmDirection)
634{
635// ASMBreakpoint();
636 int rc = VINF_SUCCESS;
637 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
638
639 /* Find the right descriptor */
640 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
641 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
642 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
643 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
644 {
645 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
646 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
647 ++iDescriptor;
648 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
649 }
650
651 while (cbData)
652 {
653 uint32_t cbToCopy;
654 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
655 cbToCopy = cbData;
656 else
657 {
658 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
659 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
660 }
661
662 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
663 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
664
665 /*
666 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
667 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
668 * see @bugref{9654#c75}.
669 */
670 if (enmDirection == VMSVGAGboTransferDirection_Read)
671 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
672 else
673 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
674 AssertRCBreak(rc);
675
676 cbData -= cbToCopy;
677 off += cbToCopy;
678 pu8CurrentHost += cbToCopy;
679
680 /* Go to the next descriptor if there's anything left. */
681 if (cbData)
682 {
683 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
684 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
685 ++iDescriptor;
686 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
687 }
688 }
689 return rc;
690}
691
692
693static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
694 uint32_t off, void const *pvData, uint32_t cbData)
695{
696 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
697 off, (void *)pvData, cbData,
698 VMSVGAGboTransferDirection_Write);
699}
700
701
702static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
703 uint32_t off, void *pvData, uint32_t cbData)
704{
705 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
706 off, pvData, cbData,
707 VMSVGAGboTransferDirection_Read);
708}
709
710
711static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
712{
713 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
714 vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
715 RTMemFree(pGbo->pvHost);
716 pGbo->pvHost = NULL;
717 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
718}
719
720
721static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
722{
723 int rc;
724
725 /* Just reread the data if pvHost has been allocated already. */
726 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
727 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
728
729 if (pGbo->pvHost)
730 {
731 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
732 }
733 else
734 rc = VERR_NO_MEMORY;
735
736 if (RT_SUCCESS(rc))
737 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
738 else
739 {
740 RTMemFree(pGbo->pvHost);
741 pGbo->pvHost = NULL;
742 }
743 return rc;
744}
745
746
747
748/*
749 *
750 * Object Tables.
751 *
752 */
753
754static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
755 uint32_t idx, uint32_t cbEntry)
756{
757 RT_NOREF(pSvgaR3State);
758
759 /* The table must exist and the index must be within the table. */
760 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
761 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
762 RT_UNTRUSTED_VALIDATED_FENCE();
763 return VINF_SUCCESS;
764}
765
766
767static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
768 uint32_t idx, uint32_t cbEntry,
769 void *pvData, uint32_t cbData)
770{
771 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
772
773 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
774 if (RT_SUCCESS(rc))
775 {
776 uint32_t const off = idx * cbEntry;
777 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
778 }
779 return rc;
780}
781
782static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
783 uint32_t idx, uint32_t cbEntry,
784 void const *pvData, uint32_t cbData)
785{
786 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
787
788 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
789 if (RT_SUCCESS(rc))
790 {
791 uint32_t const off = idx * cbEntry;
792 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
793 }
794 return rc;
795}
796
797
798/*
799 *
800 * The guest's Memory OBjects (MOB).
801 *
802 */
803
804static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
805 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
806 bool fGCPhys64, PVMSVGAMOB pMob)
807{
808 RT_ZERO(*pMob);
809
810 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
811 SVGAOTableMobEntry entry;
812 entry.ptDepth = ptDepth;
813 entry.sizeInBytes = sizeInBytes;
814 entry.base = baseAddress;
815 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
816 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
817 if (RT_SUCCESS(rc))
818 {
819 /* Create the corresponding GBO. */
820 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
821 if (RT_SUCCESS(rc))
822 {
823 /* Add to the tree of known GBOs and the LRU list. */
824 pMob->Core.Key = mobid;
825 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
826 {
827 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
828 return VINF_SUCCESS;
829 }
830
831 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
832 }
833 }
834
835 return rc;
836}
837
838
839static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
840{
841 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
842 SVGAOTableMobEntry entry;
843 RT_ZERO(entry);
844 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
845 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
846
847 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
848 if (pMob)
849 {
850 RTListNodeRemove(&pMob->nodeLRU);
851 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
852 RTMemFree(pMob);
853 return VINF_SUCCESS;
854 }
855
856 return VERR_INVALID_PARAMETER;
857}
858
859
860static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
861{
862 if (mobid == SVGA_ID_INVALID)
863 return NULL;
864
865 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
866 if (pMob)
867 {
868 /* Move to the head of the LRU list. */
869 RTListNodeRemove(&pMob->nodeLRU);
870 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
871 }
872 else
873 ASSERT_GUEST_FAILED();
874
875 return pMob;
876}
877
878
879/** Create a host ring-3 pointer to the MOB data.
880 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
881 * @param pSvgaR3State R3 device state.
882 * @param pMob The MOB.
883 * @param cbValid How many bytes of the guest backing memory contain valid data.
884 * @return VBox status.
885 */
886/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
887int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
888{
889 AssertReturn(pMob, VERR_INVALID_PARAMETER);
890 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
891}
892
893
894void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
895{
896 if (pMob)
897 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
898}
899
900
901void *vmsvgaR3MobBackingStoreGet(PVMSVGAMOB pMob, uint32_t off)
902{
903 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
904 {
905 if (off <= pMob->Gbo.cbTotal)
906 return (uint8_t *)pMob->Gbo.pvHost + off;
907 }
908 return NULL;
909}
910
911
912#ifdef VBOX_WITH_VMSVGA3D
913int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
914{
915 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
916
917 SVGAOTableSurfaceEntry entrySurface;
918 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
919 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
920 if (RT_SUCCESS(rc))
921 {
922 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
923 if (pMob)
924 {
925 VMSVGA3D_MAPPED_SURFACE map;
926 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
927 if (RT_SUCCESS(rc))
928 {
929 /* Copy MOB -> mapped surface. */
930 uint32_t offSrc = pBox->x * map.cbPixel
931 + pBox->y * entrySurface.size.width * map.cbPixel
932 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
933 uint8_t *pu8Dst = (uint8_t *)map.pvData;
934 for (uint32_t z = 0; z < pBox->d; ++z)
935 {
936 for (uint32_t y = 0; y < pBox->h; ++y)
937 {
938 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
939 if (RT_FAILURE(rc))
940 break;
941
942 pu8Dst += map.cbRowPitch;
943 offSrc += entrySurface.size.width * map.cbPixel;
944 }
945
946 pu8Dst += map.cbDepthPitch;
947 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
948 }
949
950 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
951 }
952 }
953 else
954 rc = VERR_INVALID_STATE;
955 }
956
957 return rc;
958}
959
960
961int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
962{
963 /* pPtSrc must be verified by the caller. */
964 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
965
966 SVGAOTableSurfaceEntry entrySurface;
967 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
968 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
969 if (RT_SUCCESS(rc))
970 {
971 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
972 if (pMob)
973 {
974 VMSVGA3D_MAPPED_SURFACE map;
975 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
976 if (RT_SUCCESS(rc))
977 {
978 /* Copy MOB -> mapped surface. */
979 uint32_t offSrc = pPtSrc->x * map.cbPixel
980 + pPtSrc->y * entrySurface.size.width * map.cbPixel
981 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
982 uint8_t *pu8Dst = (uint8_t *)map.pvData;
983 for (uint32_t z = 0; z < pBoxDst->d; ++z)
984 {
985 for (uint32_t y = 0; y < pBoxDst->h; ++y)
986 {
987 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
988 if (RT_FAILURE(rc))
989 break;
990
991 pu8Dst += map.cbRowPitch;
992 offSrc += entrySurface.size.width * map.cbPixel;
993 }
994
995 pu8Dst += map.cbDepthPitch;
996 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
997 }
998
999 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1000 }
1001 }
1002 else
1003 rc = VERR_INVALID_STATE;
1004 }
1005
1006 return rc;
1007}
1008#endif /* VBOX_WITH_VMSVGA3D */
1009
1010
1011/*
1012 * Screen objects.
1013 */
1014VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1015{
1016 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1017 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1018 && pSVGAState
1019 && pSVGAState->aScreens[idScreen].fDefined)
1020 {
1021 return &pSVGAState->aScreens[idScreen];
1022 }
1023 return NULL;
1024}
1025
1026void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1027{
1028#ifdef VBOX_WITH_VMSVGA3D
1029 if (pThis->svga.f3DEnabled)
1030 {
1031 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1032 {
1033 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1034 if (pScreen)
1035 vmsvga3dDestroyScreen(pThisCC, pScreen);
1036 }
1037 }
1038#else
1039 RT_NOREF(pThis, pThisCC);
1040#endif
1041}
1042
1043
1044/**
1045 * Copy a rectangle of pixels within guest VRAM.
1046 */
1047static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1048 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1049{
1050 if (!width || !height)
1051 return; /* Nothing to do, don't even bother. */
1052
1053 /*
1054 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1055 * corresponding to the current display mode.
1056 */
1057 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1058 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1059 uint8_t const *pSrc;
1060 uint8_t *pDst;
1061 unsigned const cbRectWidth = width * cbPixel;
1062 unsigned uMaxOffset;
1063
1064 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1065 if (uMaxOffset >= cbFrameBuffer)
1066 {
1067 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1068 return; /* Just don't listen to a bad guest. */
1069 }
1070
1071 pSrc = pDst = pThisCC->pbVRam;
1072 pSrc += srcY * cbScanline + srcX * cbPixel;
1073 pDst += dstY * cbScanline + dstX * cbPixel;
1074
1075 if (srcY >= dstY)
1076 {
1077 /* Source below destination, copy top to bottom. */
1078 for (; height > 0; height--)
1079 {
1080 memmove(pDst, pSrc, cbRectWidth);
1081 pSrc += cbScanline;
1082 pDst += cbScanline;
1083 }
1084 }
1085 else
1086 {
1087 /* Source above destination, copy bottom to top. */
1088 pSrc += cbScanline * (height - 1);
1089 pDst += cbScanline * (height - 1);
1090 for (; height > 0; height--)
1091 {
1092 memmove(pDst, pSrc, cbRectWidth);
1093 pSrc -= cbScanline;
1094 pDst -= cbScanline;
1095 }
1096 }
1097}
1098
1099
1100/**
1101 * Common worker for changing the pointer shape.
1102 *
1103 * @param pThisCC The VGA/VMSVGA state for ring-3.
1104 * @param pSVGAState The VMSVGA ring-3 instance data.
1105 * @param fAlpha Whether there is alpha or not.
1106 * @param xHot Hotspot x coordinate.
1107 * @param yHot Hotspot y coordinate.
1108 * @param cx Width.
1109 * @param cy Height.
1110 * @param pbData Heap copy of the cursor data. Consumed.
1111 * @param cbData The size of the data.
1112 */
1113static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1114 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1115{
1116 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1117#ifdef LOG_ENABLED
1118 if (LogIs2Enabled())
1119 {
1120 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1121 if (!fAlpha)
1122 {
1123 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1124 for (uint32_t y = 0; y < cy; y++)
1125 {
1126 Log2(("%3u:", y));
1127 uint8_t const *pbLine = &pbData[y * cbAndLine];
1128 for (uint32_t x = 0; x < cx; x += 8)
1129 {
1130 uint8_t b = pbLine[x / 8];
1131 char szByte[12];
1132 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1133 szByte[1] = b & 0x40 ? '*' : ' ';
1134 szByte[2] = b & 0x20 ? '*' : ' ';
1135 szByte[3] = b & 0x10 ? '*' : ' ';
1136 szByte[4] = b & 0x08 ? '*' : ' ';
1137 szByte[5] = b & 0x04 ? '*' : ' ';
1138 szByte[6] = b & 0x02 ? '*' : ' ';
1139 szByte[7] = b & 0x01 ? '*' : ' ';
1140 szByte[8] = '\0';
1141 Log2(("%s", szByte));
1142 }
1143 Log2(("\n"));
1144 }
1145 }
1146
1147 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1148 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1149 for (uint32_t y = 0; y < cy; y++)
1150 {
1151 Log2(("%3u:", y));
1152 uint32_t const *pu32Line = &pu32Xor[y * cx];
1153 for (uint32_t x = 0; x < cx; x++)
1154 Log2((" %08x", pu32Line[x]));
1155 Log2(("\n"));
1156 }
1157 }
1158#endif
1159
1160 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1161 AssertRC(rc);
1162
1163 if (pSVGAState->Cursor.fActive)
1164 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1165
1166 pSVGAState->Cursor.fActive = true;
1167 pSVGAState->Cursor.xHotspot = xHot;
1168 pSVGAState->Cursor.yHotspot = yHot;
1169 pSVGAState->Cursor.width = cx;
1170 pSVGAState->Cursor.height = cy;
1171 pSVGAState->Cursor.cbData = cbData;
1172 pSVGAState->Cursor.pData = pbData;
1173}
1174
1175
1176#ifdef VBOX_WITH_VMSVGA3D
1177
1178/*
1179 * SVGA_3D_CMD_* handlers.
1180 */
1181
1182
1183/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1184 *
1185 * @param pThisCC The VGA/VMSVGA state for the current context.
1186 * @param pCmd The VMSVGA command.
1187 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1188 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1189 */
1190static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1191 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1192{
1193 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1194 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1195 RT_UNTRUSTED_VALIDATED_FENCE();
1196
1197 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1198 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1199 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1200 */
1201 uint32_t cRemainingMipLevels = cMipLevelSizes;
1202 uint32_t cFaces = 0;
1203 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1204 {
1205 if (pCmd->face[i].numMipLevels == 0)
1206 break;
1207
1208 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1209 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1210
1211 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1212 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1213 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1214
1215 ++cFaces;
1216 }
1217 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1218 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1219
1220 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1221 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1222
1223 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1224 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1225 RT_UNTRUSTED_VALIDATED_FENCE();
1226
1227 /* Verify paMipLevelSizes */
1228 uint32_t cWidth = paMipLevelSizes[0].width;
1229 uint32_t cHeight = paMipLevelSizes[0].height;
1230 uint32_t cDepth = paMipLevelSizes[0].depth;
1231 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1232 {
1233 cWidth >>= 1;
1234 if (cWidth == 0) cWidth = 1;
1235 cHeight >>= 1;
1236 if (cHeight == 0) cHeight = 1;
1237 cDepth >>= 1;
1238 if (cDepth == 0) cDepth = 1;
1239 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1240 {
1241 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1242 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1243 && cHeight == paMipLevelSizes[iMipLevelSize].height
1244 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1245 }
1246 }
1247 RT_UNTRUSTED_VALIDATED_FENCE();
1248
1249 /* Create the surface. */
1250 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1251 pCmd->multisampleCount, pCmd->autogenFilter,
1252 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1253}
1254
1255
1256/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1257static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1258{
1259 ASMBreakpoint();
1260 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1261
1262 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1263
1264 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1265 /* Allocate a structure for the MOB. */
1266 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1267 AssertPtrReturnVoid(pMob);
1268
1269 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1270 if (RT_SUCCESS(rc))
1271 {
1272 return;
1273 }
1274
1275 AssertFailed();
1276
1277 RTMemFree(pMob);
1278}
1279
1280
1281/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1282static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1283{
1284// ASMBreakpoint();
1285 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1286
1287 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1288
1289 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1290 if (RT_SUCCESS(rc))
1291 {
1292 return;
1293 }
1294
1295 AssertFailed();
1296}
1297
1298
1299/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1300static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1301{
1302// ASMBreakpoint();
1303 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1304
1305 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1306 SVGAOTableSurfaceEntry entry;
1307 RT_ZERO(entry);
1308 entry.format = pCmd->format;
1309 entry.surface1Flags = pCmd->surfaceFlags;
1310 entry.numMipLevels = pCmd->numMipLevels;
1311 entry.multisampleCount = pCmd->multisampleCount;
1312 entry.autogenFilter = pCmd->autogenFilter;
1313 entry.size = pCmd->size;
1314 entry.mobid = SVGA_ID_INVALID;
1315 // entry.arraySize = 0;
1316 // entry.mobPitch = 0;
1317 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1318 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1319 if (RT_SUCCESS(rc))
1320 {
1321 /* Create the host surface. */
1322 /** @todo fGBO = true flag. */
1323 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1324 pCmd->multisampleCount, pCmd->autogenFilter,
1325 pCmd->numMipLevels, &pCmd->size);
1326 }
1327}
1328
1329
1330/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1331static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1332{
1333// ASMBreakpoint();
1334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1335
1336 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1337 SVGAOTableSurfaceEntry entry;
1338 RT_ZERO(entry);
1339 entry.mobid = SVGA_ID_INVALID;
1340 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1341 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1342
1343 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1344}
1345
1346
1347/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1348static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1349{
1350// ASMBreakpoint();
1351 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1352
1353 /* Assign the mobid to the surface. */
1354 int rc = VINF_SUCCESS;
1355 if (pCmd->mobid != SVGA_ID_INVALID)
1356 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1357 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1358 if (RT_SUCCESS(rc))
1359 {
1360 SVGAOTableSurfaceEntry entry;
1361 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1362 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1363 if (RT_SUCCESS(rc))
1364 {
1365 entry.mobid = pCmd->mobid;
1366 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1367 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1368 if (RT_SUCCESS(rc))
1369 {
1370 /* */
1371 }
1372 }
1373 }
1374}
1375
1376
1377#ifdef DUMP_BITMAPS
1378static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1379{
1380 if (pMap->cbPixel != 4)
1381 return VERR_NOT_SUPPORTED;
1382
1383 int const w = pMap->box.w;
1384 int const h = pMap->box.h;
1385
1386 const int cbBitmap = w * h * 4;
1387
1388 FILE *f = fopen(pszFilename, "wb");
1389 if (!f)
1390 return VERR_FILE_NOT_FOUND;
1391
1392 {
1393 BMPFILEHDR fileHdr;
1394 RT_ZERO(fileHdr);
1395 fileHdr.uType = BMP_HDR_MAGIC;
1396 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1397 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1398
1399 BMPWIN3XINFOHDR coreHdr;
1400 RT_ZERO(coreHdr);
1401 coreHdr.cbSize = sizeof(coreHdr);
1402 coreHdr.uWidth = w;
1403 coreHdr.uHeight = -h;
1404 coreHdr.cPlanes = 1;
1405 coreHdr.cBits = 32;
1406 coreHdr.cbSizeImage = cbBitmap;
1407
1408 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1409 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1410 }
1411
1412 if (pMap->cbPixel == 4)
1413 {
1414 const uint8_t *s = (uint8_t *)pMap->pvData;
1415 for (int32_t y = 0; y < h; ++y)
1416 {
1417 fwrite(s, 1, w * pMap->cbPixel, f);
1418
1419 s += pMap->cbRowPitch;
1420 }
1421 }
1422
1423 fclose(f);
1424
1425 return VINF_SUCCESS;
1426}
1427
1428
1429void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1430{
1431 static int idxBitmap = 0;
1432 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1433 vmsvga3dBmpWrite(pszFilename, pMap);
1434 RTStrFree(pszFilename);
1435}
1436#endif /* DUMP_BITMAPS */
1437
1438
1439/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1440static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1441{
1442// ASMBreakpoint();
1443 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1444
1445 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1446 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1447
1448 /* "update a surface from its backing MOB." */
1449 SVGAOTableSurfaceEntry entrySurface;
1450 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1451 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1452 if (RT_SUCCESS(rc))
1453 {
1454 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1455 if (pMob)
1456 {
1457 VMSVGA3D_MAPPED_SURFACE map;
1458 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1459 if (RT_SUCCESS(rc))
1460 {
1461 /* Copy MOB -> mapped surface. */
1462 uint32_t offSrc = pCmd->box.x * map.cbPixel
1463 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1464 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1465 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1466 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1467 {
1468 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1469 {
1470 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1471 if (RT_FAILURE(rc))
1472 break;
1473
1474 pu8Dst += map.cbRowPitch;
1475 offSrc += entrySurface.size.width * map.cbPixel;
1476 }
1477
1478 pu8Dst += map.cbDepthPitch;
1479 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1480 }
1481
1482 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1483
1484 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1485 }
1486 }
1487 }
1488}
1489
1490
1491/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1492static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1493{
1494// ASMBreakpoint();
1495 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1496}
1497
1498
1499/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1500static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1501{
1502// ASMBreakpoint();
1503 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1504}
1505
1506
1507/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1508static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1509{
1510 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1511
1512 /*
1513 * Create a GBO for the table.
1514 */
1515 PVMSVGAGBO pGbo;
1516 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1517 {
1518 RT_UNTRUSTED_VALIDATED_FENCE();
1519 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1520 }
1521 else
1522 {
1523 ASSERT_GUEST_FAILED();
1524 pGbo = NULL;
1525 }
1526
1527 if (pGbo)
1528 {
1529 /* Recreate. */
1530 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1531 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1532 AssertRC(rc);
1533 }
1534}
1535
1536
1537/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1538static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1539{
1540// ASMBreakpoint();
1541 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1542
1543 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1544 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1545 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1546 RT_UNTRUSTED_VALIDATED_FENCE();
1547
1548 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1549 SVGAOTableScreenTargetEntry entry;
1550 RT_ZERO(entry);
1551 entry.image.sid = SVGA_ID_INVALID;
1552 // entry.image.face = 0;
1553 // entry.image.mipmap = 0;
1554 entry.width = pCmd->width;
1555 entry.height = pCmd->height;
1556 entry.xRoot = pCmd->xRoot;
1557 entry.yRoot = pCmd->yRoot;
1558 entry.flags = pCmd->flags;
1559 entry.dpi = pCmd->dpi;
1560
1561 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1562 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1563 if (RT_SUCCESS(rc))
1564 {
1565 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1566 /** @todo Generic screen object/target interface. */
1567 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1568 pScreen->fDefined = true;
1569 pScreen->fModified = true;
1570 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1571 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1572 pScreen->idScreen = pCmd->stid;
1573
1574 pScreen->xOrigin = pCmd->xRoot;
1575 pScreen->yOrigin = pCmd->yRoot;
1576 pScreen->cWidth = pCmd->width;
1577 pScreen->cHeight = pCmd->height;
1578 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1579 pScreen->cbPitch = pCmd->width * 4;
1580 pScreen->cBpp = 32;
1581
1582 if (RT_LIKELY(pThis->svga.f3DEnabled))
1583 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1584
1585 if (!pScreen->pHwScreen)
1586 {
1587 /* System memory buffer. */
1588 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1589 }
1590
1591 pThis->svga.fGFBRegisters = false;
1592 vmsvgaR3ChangeMode(pThis, pThisCC);
1593 }
1594}
1595
1596
1597/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1598static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1599{
1600// ASMBreakpoint();
1601 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1602
1603 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1604 RT_UNTRUSTED_VALIDATED_FENCE();
1605
1606 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1607 SVGAOTableScreenTargetEntry entry;
1608 RT_ZERO(entry);
1609 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1610 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1611 if (RT_SUCCESS(rc))
1612 {
1613 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1614 /** @todo Generic screen object/target interface. */
1615 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1616 pScreen->fModified = true;
1617 pScreen->fDefined = false;
1618 pScreen->idScreen = pCmd->stid;
1619
1620 if (RT_LIKELY(pThis->svga.f3DEnabled))
1621 vmsvga3dDestroyScreen(pThisCC, pScreen);
1622
1623 vmsvgaR3ChangeMode(pThis, pThisCC);
1624
1625 RTMemFree(pScreen->pvScreenBitmap);
1626 pScreen->pvScreenBitmap = NULL;
1627 }
1628}
1629
1630
1631/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1632static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1633{
1634// ASMBreakpoint();
1635 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1636
1637 /* "Binding a surface to a Screen Target the same as flipping" */
1638
1639 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1640 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1641 RT_UNTRUSTED_VALIDATED_FENCE();
1642
1643 /* Assign the surface to the screen target. */
1644 int rc = VINF_SUCCESS;
1645 if (pCmd->image.sid != SVGA_ID_INVALID)
1646 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1647 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1648 if (RT_SUCCESS(rc))
1649 {
1650 SVGAOTableScreenTargetEntry entry;
1651 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1652 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1653 if (RT_SUCCESS(rc))
1654 {
1655 entry.image = pCmd->image;
1656 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1657 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1658 if (RT_SUCCESS(rc))
1659 {
1660 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1661 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1662 AssertRC(rc);
1663 }
1664 }
1665 }
1666}
1667
1668
1669/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1670static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1671{
1672// ASMBreakpoint();
1673 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1674
1675 /* Update the screen target from its backing surface. */
1676 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1677 RT_UNTRUSTED_VALIDATED_FENCE();
1678
1679 /* Get the screen target info. */
1680 SVGAOTableScreenTargetEntry entryScreenTarget;
1681 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1682 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1683 if (RT_SUCCESS(rc))
1684 {
1685 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1686 RT_UNTRUSTED_VALIDATED_FENCE();
1687
1688 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1689 {
1690 SVGAOTableSurfaceEntry entrySurface;
1691 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1692 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1693 if (RT_SUCCESS(rc))
1694 {
1695 /* Copy entrySurface.mobid content to the screen target. */
1696 if (entrySurface.mobid != SVGA_ID_INVALID)
1697 {
1698 RT_UNTRUSTED_VALIDATED_FENCE();
1699 SVGA3dRect targetRect = pCmd->rect;
1700
1701 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1702 if (pScreen->pHwScreen)
1703 {
1704 /* Copy the screen target surface to the backend's screen. */
1705 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1706 }
1707 else if (pScreen->pvScreenBitmap)
1708 {
1709 /* Copy the screen target surface to the memory buffer. */
1710 VMSVGA3D_MAPPED_SURFACE map;
1711 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1712 if (RT_SUCCESS(rc))
1713 {
1714 uint8_t const *pu8Src = (uint8_t *)map.pvData
1715 + targetRect.x * map.cbPixel
1716 + targetRect.y * map.cbRowPitch;
1717 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1718 + targetRect.x * map.cbPixel
1719 + targetRect.y * map.box.w * map.cbPixel;
1720 for (uint32_t y = 0; y < targetRect.h; ++y)
1721 {
1722 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1723
1724 pu8Src += map.cbRowPitch;
1725 pu8Dst += map.box.w * map.cbPixel;
1726 }
1727
1728 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1729
1730 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1731 }
1732 else
1733 AssertFailed();
1734 }
1735 }
1736 }
1737 }
1738 }
1739}
1740
1741
1742/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1743static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1744{
1745 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1746
1747 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1748 SVGAOTableSurfaceEntry entry;
1749 RT_ZERO(entry);
1750 entry.format = pCmd->format;
1751 entry.surface1Flags = pCmd->surfaceFlags;
1752 entry.numMipLevels = pCmd->numMipLevels;
1753 entry.multisampleCount = pCmd->multisampleCount;
1754 entry.autogenFilter = pCmd->autogenFilter;
1755 entry.size = pCmd->size;
1756 entry.mobid = SVGA_ID_INVALID;
1757 entry.arraySize = pCmd->arraySize;
1758 // entry.mobPitch = 0;
1759 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1760 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1761 if (RT_SUCCESS(rc))
1762 {
1763 /* Create the host surface. */
1764 /** @todo fGBO = true flag. */
1765 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1766 pCmd->multisampleCount, pCmd->autogenFilter,
1767 pCmd->numMipLevels, &pCmd->size);
1768 }
1769}
1770
1771
1772/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1773static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1774{
1775// ASMBreakpoint();
1776 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1777
1778 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1779
1780 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1781 /* Allocate a structure for the MOB. */
1782 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1783 AssertPtrReturnVoid(pMob);
1784
1785 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1786 if (RT_SUCCESS(rc))
1787 {
1788 return;
1789 }
1790
1791 RTMemFree(pMob);
1792}
1793
1794
1795/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1796static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1797{
1798#ifdef VMSVGA3D_DX
1799//ASMBreakpoint();
1800 RT_NOREF(cbCmd);
1801
1802 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1803
1804 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1805 SVGAOTableDXContextEntry entry;
1806 RT_ZERO(entry);
1807 entry.cid = pCmd->cid;
1808 entry.mobid = SVGA_ID_INVALID;
1809 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1810 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1811 if (RT_SUCCESS(rc))
1812 {
1813 /* Create the host context. */
1814 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1815 }
1816
1817 return rc;
1818#else
1819 RT_NOREF(pThisCC, pCmd, cbCmd);
1820 return VERR_NOT_SUPPORTED;
1821#endif
1822}
1823
1824
1825/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1826static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
1827{
1828#ifdef VMSVGA3D_DX
1829//ASMBreakpoint();
1830 RT_NOREF(cbCmd);
1831
1832 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1833
1834 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1835 SVGAOTableDXContextEntry entry;
1836 RT_ZERO(entry);
1837 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1838 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1839
1840 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
1841#else
1842 RT_NOREF(pThisCC, pCmd, cbCmd);
1843 return VERR_NOT_SUPPORTED;
1844#endif
1845}
1846
1847
1848/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1849static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
1850{
1851#ifdef VMSVGA3D_DX
1852//ASMBreakpoint();
1853 RT_NOREF(cbCmd);
1854
1855 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1856
1857 /* Assign a mobid to a cid. */
1858 int rc = VINF_SUCCESS;
1859 if (pCmd->mobid != SVGA_ID_INVALID)
1860 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1861 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1862 if (RT_SUCCESS(rc))
1863 {
1864 SVGAOTableDXContextEntry entry;
1865 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1866 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1867 if (RT_SUCCESS(rc))
1868 {
1869 SVGADXContextMobFormat *pSvgaDXContext = NULL;
1870 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
1871 {
1872 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
1873 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1874 if (pSvgaDXContext)
1875 {
1876 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1877 if (RT_SUCCESS(rc))
1878 {
1879 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
1880 if (pMob)
1881 {
1882 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1883 }
1884 }
1885
1886 RTMemFree(pSvgaDXContext);
1887 pSvgaDXContext = NULL;
1888 }
1889 }
1890
1891 if (pCmd->mobid != SVGA_ID_INVALID)
1892 {
1893 /* Bind a new context. Copy existing data from the guyest backing memory. */
1894 if (pCmd->validContents)
1895 {
1896 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
1897 if (pMob)
1898 {
1899 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1900 if (pSvgaDXContext)
1901 {
1902 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1903 if (RT_FAILURE(rc))
1904 {
1905 RTMemFree(pSvgaDXContext);
1906 pSvgaDXContext = NULL;
1907 }
1908 }
1909 }
1910 }
1911
1912 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1913
1914 RTMemFree(pSvgaDXContext);
1915 }
1916
1917 /* Update the object table. */
1918 entry.mobid = pCmd->mobid;
1919 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1920 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1921 }
1922 }
1923
1924 return rc;
1925#else
1926 RT_NOREF(pThisCC, pCmd, cbCmd);
1927 return VERR_NOT_SUPPORTED;
1928#endif
1929}
1930
1931
1932/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1933static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
1934{
1935#ifdef VMSVGA3D_DX
1936ASMBreakpoint();
1937 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1938 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1939 return vmsvga3dDXReadbackContext(pThisCC, idDXContext);
1940#else
1941 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1942 return VERR_NOT_SUPPORTED;
1943#endif
1944}
1945
1946
1947/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1948static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
1949{
1950#ifdef VMSVGA3D_DX
1951ASMBreakpoint();
1952 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1953 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1954 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
1955#else
1956 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1957 return VERR_NOT_SUPPORTED;
1958#endif
1959}
1960
1961
1962/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1963static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
1964{
1965#ifdef VMSVGA3D_DX
1966//ASMBreakpoint();
1967 RT_NOREF(cbCmd);
1968 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
1969#else
1970 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1971 return VERR_NOT_SUPPORTED;
1972#endif
1973}
1974
1975
1976/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
1977static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
1978{
1979#ifdef VMSVGA3D_DX
1980ASMBreakpoint();
1981 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1982 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1983 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext);
1984#else
1985 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1986 return VERR_NOT_SUPPORTED;
1987#endif
1988}
1989
1990
1991/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
1992static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
1993{
1994#ifdef VMSVGA3D_DX
1995//ASMBreakpoint();
1996 RT_NOREF(cbCmd);
1997 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
1998#else
1999 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2000 return VERR_NOT_SUPPORTED;
2001#endif
2002}
2003
2004
2005/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2006static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2007{
2008#ifdef VMSVGA3D_DX
2009//ASMBreakpoint();
2010 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2011 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2012 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd->startSampler, pCmd->type, cSamplerId, paSamplerId);
2013#else
2014 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2015 return VERR_NOT_SUPPORTED;
2016#endif
2017}
2018
2019
2020/* SVGA_3D_CMD_DX_DRAW 1152 */
2021static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2022{
2023#ifdef VMSVGA3D_DX
2024//ASMBreakpoint();
2025 RT_NOREF(cbCmd);
2026 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2027#else
2028 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2029 return VERR_NOT_SUPPORTED;
2030#endif
2031}
2032
2033
2034/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2035static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2036{
2037#ifdef VMSVGA3D_DX
2038ASMBreakpoint();
2039 RT_NOREF(cbCmd);
2040 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2041#else
2042 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2043 return VERR_NOT_SUPPORTED;
2044#endif
2045}
2046
2047
2048/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2049static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2050{
2051#ifdef VMSVGA3D_DX
2052ASMBreakpoint();
2053 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2054 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2055 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext);
2056#else
2057 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2058 return VERR_NOT_SUPPORTED;
2059#endif
2060}
2061
2062
2063/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2064static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2065{
2066#ifdef VMSVGA3D_DX
2067ASMBreakpoint();
2068 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2069 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2070 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext);
2071#else
2072 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2073 return VERR_NOT_SUPPORTED;
2074#endif
2075}
2076
2077
2078/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2079static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2080{
2081#ifdef VMSVGA3D_DX
2082ASMBreakpoint();
2083 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2084 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2085 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2086#else
2087 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2088 return VERR_NOT_SUPPORTED;
2089#endif
2090}
2091
2092
2093/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2094static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2095{
2096#ifdef VMSVGA3D_DX
2097//ASMBreakpoint();
2098 RT_NOREF(cbCmd);
2099 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2100#else
2101 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2102 return VERR_NOT_SUPPORTED;
2103#endif
2104}
2105
2106
2107/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2108static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2109{
2110#ifdef VMSVGA3D_DX
2111//ASMBreakpoint();
2112 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2113 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2114 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2115#else
2116 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2117 return VERR_NOT_SUPPORTED;
2118#endif
2119}
2120
2121
2122/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2123static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2124{
2125#ifdef VMSVGA3D_DX
2126//ASMBreakpoint();
2127 RT_NOREF(cbCmd);
2128 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2129#else
2130 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2131 return VERR_NOT_SUPPORTED;
2132#endif
2133}
2134
2135
2136/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2137static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2138{
2139#ifdef VMSVGA3D_DX
2140//ASMBreakpoint();
2141 RT_NOREF(cbCmd);
2142 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2143#else
2144 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2145 return VERR_NOT_SUPPORTED;
2146#endif
2147}
2148
2149
2150/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2151static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2152{
2153#ifdef VMSVGA3D_DX
2154//ASMBreakpoint();
2155 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2156 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2157 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2158#else
2159 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2160 return VERR_NOT_SUPPORTED;
2161#endif
2162}
2163
2164
2165/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2166static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2167{
2168#ifdef VMSVGA3D_DX
2169//ASMBreakpoint();
2170 RT_NOREF(cbCmd);
2171 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2172#else
2173 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2174 return VERR_NOT_SUPPORTED;
2175#endif
2176}
2177
2178
2179/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2180static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2181{
2182#ifdef VMSVGA3D_DX
2183//ASMBreakpoint();
2184 RT_NOREF(cbCmd);
2185 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2186#else
2187 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2188 return VERR_NOT_SUPPORTED;
2189#endif
2190}
2191
2192
2193/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2194static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2195{
2196#ifdef VMSVGA3D_DX
2197//ASMBreakpoint();
2198 RT_NOREF(cbCmd);
2199 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2200#else
2201 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2202 return VERR_NOT_SUPPORTED;
2203#endif
2204}
2205
2206
2207/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2208static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2209{
2210#ifdef VMSVGA3D_DX
2211ASMBreakpoint();
2212 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2213 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2214 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2215#else
2216 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2217 return VERR_NOT_SUPPORTED;
2218#endif
2219}
2220
2221
2222/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2223static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2224{
2225#ifdef VMSVGA3D_DX
2226ASMBreakpoint();
2227 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2228 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2229 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2230#else
2231 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2232 return VERR_NOT_SUPPORTED;
2233#endif
2234}
2235
2236
2237/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2238static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2239{
2240#ifdef VMSVGA3D_DX
2241ASMBreakpoint();
2242 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2243 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2244 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2245#else
2246 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2247 return VERR_NOT_SUPPORTED;
2248#endif
2249}
2250
2251
2252/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2253static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2254{
2255#ifdef VMSVGA3D_DX
2256ASMBreakpoint();
2257 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2258 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2259 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2260#else
2261 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2262 return VERR_NOT_SUPPORTED;
2263#endif
2264}
2265
2266
2267/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2268static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2269{
2270#ifdef VMSVGA3D_DX
2271ASMBreakpoint();
2272 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2273 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2274 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2275#else
2276 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2277 return VERR_NOT_SUPPORTED;
2278#endif
2279}
2280
2281
2282/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2283static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2284{
2285#ifdef VMSVGA3D_DX
2286ASMBreakpoint();
2287 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2288 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2289 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2290#else
2291 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2292 return VERR_NOT_SUPPORTED;
2293#endif
2294}
2295
2296
2297/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2298static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2299{
2300#ifdef VMSVGA3D_DX
2301ASMBreakpoint();
2302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2303 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2304 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2305#else
2306 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2307 return VERR_NOT_SUPPORTED;
2308#endif
2309}
2310
2311
2312/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2313static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2314{
2315#ifdef VMSVGA3D_DX
2316ASMBreakpoint();
2317 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2318 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2319 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2320#else
2321 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2322 return VERR_NOT_SUPPORTED;
2323#endif
2324}
2325
2326
2327/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2328static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2329{
2330#ifdef VMSVGA3D_DX
2331ASMBreakpoint();
2332 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2333 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2334 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext);
2335#else
2336 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2337 return VERR_NOT_SUPPORTED;
2338#endif
2339}
2340
2341
2342/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2343static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2344{
2345#ifdef VMSVGA3D_DX
2346//ASMBreakpoint();
2347 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2348 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2349 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2350#else
2351 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2352 return VERR_NOT_SUPPORTED;
2353#endif
2354}
2355
2356
2357/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2358static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2359{
2360#ifdef VMSVGA3D_DX
2361//ASMBreakpoint();
2362 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2363 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2364 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2365#else
2366 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2367 return VERR_NOT_SUPPORTED;
2368#endif
2369}
2370
2371
2372/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2373static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2374{
2375#ifdef VMSVGA3D_DX
2376ASMBreakpoint();
2377 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2378 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2379 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext);
2380#else
2381 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2382 return VERR_NOT_SUPPORTED;
2383#endif
2384}
2385
2386
2387/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2388static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2389{
2390#ifdef VMSVGA3D_DX
2391ASMBreakpoint();
2392 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2393 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2394 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext);
2395#else
2396 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2397 return VERR_NOT_SUPPORTED;
2398#endif
2399}
2400
2401
2402/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2403static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2404{
2405#ifdef VMSVGA3D_DX
2406ASMBreakpoint();
2407 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2408 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2409 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext);
2410#else
2411 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2412 return VERR_NOT_SUPPORTED;
2413#endif
2414}
2415
2416
2417/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2418static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2419{
2420#ifdef VMSVGA3D_DX
2421ASMBreakpoint();
2422 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2423 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2424 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2425#else
2426 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2427 return VERR_NOT_SUPPORTED;
2428#endif
2429}
2430
2431
2432/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2433static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2434{
2435#ifdef VMSVGA3D_DX
2436ASMBreakpoint();
2437 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2438 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2439 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2440#else
2441 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2442 return VERR_NOT_SUPPORTED;
2443#endif
2444}
2445
2446
2447/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2448static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2449{
2450#ifdef VMSVGA3D_DX
2451ASMBreakpoint();
2452 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2453 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2454 return vmsvga3dDXGenMips(pThisCC, idDXContext);
2455#else
2456 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2457 return VERR_NOT_SUPPORTED;
2458#endif
2459}
2460
2461
2462/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2463static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2464{
2465#ifdef VMSVGA3D_DX
2466ASMBreakpoint();
2467 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2468 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2469 return vmsvga3dDXUpdateSubResource(pThisCC, idDXContext);
2470#else
2471 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2472 return VERR_NOT_SUPPORTED;
2473#endif
2474}
2475
2476
2477/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2478static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2479{
2480#ifdef VMSVGA3D_DX
2481ASMBreakpoint();
2482 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2483 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2484 return vmsvga3dDXReadbackSubResource(pThisCC, idDXContext);
2485#else
2486 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2487 return VERR_NOT_SUPPORTED;
2488#endif
2489}
2490
2491
2492/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2493static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2494{
2495#ifdef VMSVGA3D_DX
2496ASMBreakpoint();
2497 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2498 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2499 return vmsvga3dDXInvalidateSubResource(pThisCC, idDXContext);
2500#else
2501 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2502 return VERR_NOT_SUPPORTED;
2503#endif
2504}
2505
2506
2507/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2508static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2509{
2510#ifdef VMSVGA3D_DX
2511ASMBreakpoint();
2512 RT_NOREF(cbCmd);
2513 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2514#else
2515 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2516 return VERR_NOT_SUPPORTED;
2517#endif
2518}
2519
2520
2521/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2522static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2523{
2524#ifdef VMSVGA3D_DX
2525ASMBreakpoint();
2526 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2527 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2528 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext);
2529#else
2530 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2531 return VERR_NOT_SUPPORTED;
2532#endif
2533}
2534
2535
2536/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2537static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2538{
2539#ifdef VMSVGA3D_DX
2540//ASMBreakpoint();
2541 RT_NOREF(cbCmd);
2542 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2543#else
2544 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2545 return VERR_NOT_SUPPORTED;
2546#endif
2547}
2548
2549
2550/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2551static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2552{
2553#ifdef VMSVGA3D_DX
2554ASMBreakpoint();
2555 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2556 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2557 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext);
2558#else
2559 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2560 return VERR_NOT_SUPPORTED;
2561#endif
2562}
2563
2564
2565/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2566static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2567{
2568#ifdef VMSVGA3D_DX
2569ASMBreakpoint();
2570 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2571 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2572 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext);
2573#else
2574 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2575 return VERR_NOT_SUPPORTED;
2576#endif
2577}
2578
2579
2580/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2581static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2582{
2583#ifdef VMSVGA3D_DX
2584ASMBreakpoint();
2585 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2586 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2587 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext);
2588#else
2589 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2590 return VERR_NOT_SUPPORTED;
2591#endif
2592}
2593
2594
2595/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2596static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2597{
2598#ifdef VMSVGA3D_DX
2599//ASMBreakpoint();
2600 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2601 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2602 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2603#else
2604 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2605 return VERR_NOT_SUPPORTED;
2606#endif
2607}
2608
2609
2610/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2611static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2612{
2613#ifdef VMSVGA3D_DX
2614ASMBreakpoint();
2615 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2616 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2617 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2618#else
2619 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2620 return VERR_NOT_SUPPORTED;
2621#endif
2622}
2623
2624
2625/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2626static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2627{
2628#ifdef VMSVGA3D_DX
2629//ASMBreakpoint();
2630 RT_NOREF(cbCmd);
2631 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2632#else
2633 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2634 return VERR_NOT_SUPPORTED;
2635#endif
2636}
2637
2638
2639/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2640static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2641{
2642#ifdef VMSVGA3D_DX
2643ASMBreakpoint();
2644 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2645 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2646 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2647#else
2648 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2649 return VERR_NOT_SUPPORTED;
2650#endif
2651}
2652
2653
2654/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2655static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2656{
2657#ifdef VMSVGA3D_DX
2658//ASMBreakpoint();
2659 RT_NOREF(cbCmd);
2660 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2661#else
2662 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2663 return VERR_NOT_SUPPORTED;
2664#endif
2665}
2666
2667
2668/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2669static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2670{
2671#ifdef VMSVGA3D_DX
2672ASMBreakpoint();
2673 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2674 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2675 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2676#else
2677 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2678 return VERR_NOT_SUPPORTED;
2679#endif
2680}
2681
2682
2683/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2684static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2685{
2686#ifdef VMSVGA3D_DX
2687//ASMBreakpoint();
2688 RT_NOREF(cbCmd);
2689 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2690#else
2691 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2692 return VERR_NOT_SUPPORTED;
2693#endif
2694}
2695
2696
2697/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2698static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2699{
2700#ifdef VMSVGA3D_DX
2701ASMBreakpoint();
2702 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2703 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2704 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2705#else
2706 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2707 return VERR_NOT_SUPPORTED;
2708#endif
2709}
2710
2711
2712/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2713static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2714{
2715#ifdef VMSVGA3D_DX
2716//ASMBreakpoint();
2717 RT_NOREF(cbCmd);
2718 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2719#else
2720 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2721 return VERR_NOT_SUPPORTED;
2722#endif
2723}
2724
2725
2726/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2727static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2728{
2729#ifdef VMSVGA3D_DX
2730ASMBreakpoint();
2731 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2732 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2733 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
2734#else
2735 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2736 return VERR_NOT_SUPPORTED;
2737#endif
2738}
2739
2740
2741/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2742static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
2743{
2744#ifdef VMSVGA3D_DX
2745//ASMBreakpoint();
2746 RT_NOREF(cbCmd);
2747 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
2748#else
2749 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2750 return VERR_NOT_SUPPORTED;
2751#endif
2752}
2753
2754
2755/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2756static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
2757{
2758#ifdef VMSVGA3D_DX
2759ASMBreakpoint();
2760 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2761 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2762 return vmsvga3dDXDestroyShader(pThisCC, idDXContext);
2763#else
2764 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2765 return VERR_NOT_SUPPORTED;
2766#endif
2767}
2768
2769
2770/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2771static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
2772{
2773#ifdef VMSVGA3D_DX
2774//ASMBreakpoint();
2775 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2776 RT_NOREF(cbCmd);
2777 ASSERT_GUEST_LOGREL_MSG(idDXContext == pCmd->cid, ("idDXContext = %u, pCmd->cid = %u\n", idDXContext, pCmd->cid));
2778 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2779 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2780 return vmsvga3dDXBindShader(pThisCC, pCmd->cid, pMob, pCmd->shid, pCmd->offsetInBytes);
2781#else
2782 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2783 return VERR_NOT_SUPPORTED;
2784#endif
2785}
2786
2787
2788/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2789static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
2790{
2791#ifdef VMSVGA3D_DX
2792ASMBreakpoint();
2793 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2794 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2795 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext);
2796#else
2797 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2798 return VERR_NOT_SUPPORTED;
2799#endif
2800}
2801
2802
2803/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2804static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
2805{
2806#ifdef VMSVGA3D_DX
2807ASMBreakpoint();
2808 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2809 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2810 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext);
2811#else
2812 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2813 return VERR_NOT_SUPPORTED;
2814#endif
2815}
2816
2817
2818/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2819static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
2820{
2821#ifdef VMSVGA3D_DX
2822ASMBreakpoint();
2823 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2824 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2825 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext);
2826#else
2827 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2828 return VERR_NOT_SUPPORTED;
2829#endif
2830}
2831
2832
2833/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2834static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
2835{
2836#ifdef VMSVGA3D_DX
2837//ASMBreakpoint();
2838 RT_NOREF(cbCmd);
2839 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2840 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2841 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2842 return vmsvga3dDXSetCOTable(pThisCC, pCmd->cid, pMob, pCmd->type, pCmd->validSizeInBytes);
2843#else
2844 RT_NOREF(pThisCC, pCmd, cbCmd);
2845 return VERR_NOT_SUPPORTED;
2846#endif
2847}
2848
2849
2850/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2851static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
2852{
2853#ifdef VMSVGA3D_DX
2854ASMBreakpoint();
2855 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2856 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2857 return vmsvga3dDXReadbackCOTable(pThisCC, idDXContext);
2858#else
2859 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2860 return VERR_NOT_SUPPORTED;
2861#endif
2862}
2863
2864
2865/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2866static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
2867{
2868#ifdef VMSVGA3D_DX
2869ASMBreakpoint();
2870 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2871 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2872 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
2873#else
2874 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2875 return VERR_NOT_SUPPORTED;
2876#endif
2877}
2878
2879
2880/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2881static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
2882{
2883#ifdef VMSVGA3D_DX
2884ASMBreakpoint();
2885 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2886 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2887 return vmsvga3dDXTransferFromBuffer(pThisCC, idDXContext);
2888#else
2889 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2890 return VERR_NOT_SUPPORTED;
2891#endif
2892}
2893
2894
2895/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2896static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
2897{
2898#ifdef VMSVGA3D_DX
2899ASMBreakpoint();
2900 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2901 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2902 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
2903#else
2904 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2905 return VERR_NOT_SUPPORTED;
2906#endif
2907}
2908
2909
2910/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2911static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
2912{
2913#ifdef VMSVGA3D_DX
2914ASMBreakpoint();
2915 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2916 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2917 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
2918#else
2919 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2920 return VERR_NOT_SUPPORTED;
2921#endif
2922}
2923
2924
2925/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2926static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
2927{
2928#ifdef VMSVGA3D_DX
2929ASMBreakpoint();
2930 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2931 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2932 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
2933#else
2934 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2935 return VERR_NOT_SUPPORTED;
2936#endif
2937}
2938
2939
2940/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2941static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
2942{
2943#ifdef VMSVGA3D_DX
2944ASMBreakpoint();
2945 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2946 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2947 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
2948#else
2949 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2950 return VERR_NOT_SUPPORTED;
2951#endif
2952}
2953
2954
2955/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2956static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
2957{
2958#ifdef VMSVGA3D_DX
2959ASMBreakpoint();
2960 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2961 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2962 return vmsvga3dDXPredTransferFromBuffer(pThisCC, idDXContext);
2963#else
2964 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2965 return VERR_NOT_SUPPORTED;
2966#endif
2967}
2968
2969
2970/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
2971static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
2972{
2973#ifdef VMSVGA3D_DX
2974ASMBreakpoint();
2975 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2976 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2977 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
2978#else
2979 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2980 return VERR_NOT_SUPPORTED;
2981#endif
2982}
2983
2984
2985/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
2986static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
2987{
2988#ifdef VMSVGA3D_DX
2989ASMBreakpoint();
2990 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2991 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2992 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
2993#else
2994 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2995 return VERR_NOT_SUPPORTED;
2996#endif
2997}
2998
2999
3000/* SVGA_3D_CMD_DX_HINT 1218 */
3001static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3002{
3003#ifdef VMSVGA3D_DX
3004ASMBreakpoint();
3005 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3006 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3007 return vmsvga3dDXHint(pThisCC, idDXContext);
3008#else
3009 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3010 return VERR_NOT_SUPPORTED;
3011#endif
3012}
3013
3014
3015/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3016static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3017{
3018#ifdef VMSVGA3D_DX
3019ASMBreakpoint();
3020 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3021 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3022 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3023#else
3024 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3025 return VERR_NOT_SUPPORTED;
3026#endif
3027}
3028
3029
3030/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3031static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3032{
3033#ifdef VMSVGA3D_DX
3034ASMBreakpoint();
3035 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3036 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3037 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3038#else
3039 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3040 return VERR_NOT_SUPPORTED;
3041#endif
3042}
3043
3044
3045/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3046static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3047{
3048#ifdef VMSVGA3D_DX
3049ASMBreakpoint();
3050 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3051 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3052 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3053#else
3054 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3055 return VERR_NOT_SUPPORTED;
3056#endif
3057}
3058
3059
3060/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3061static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3062{
3063#ifdef VMSVGA3D_DX
3064ASMBreakpoint();
3065 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3066 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3067 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3068#else
3069 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3070 return VERR_NOT_SUPPORTED;
3071#endif
3072}
3073
3074
3075/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3076static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3077{
3078#ifdef VMSVGA3D_DX
3079ASMBreakpoint();
3080 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3081 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3082 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3083#else
3084 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3085 return VERR_NOT_SUPPORTED;
3086#endif
3087}
3088
3089
3090/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3091static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3092{
3093#ifdef VMSVGA3D_DX
3094ASMBreakpoint();
3095 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3096 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3097 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3098#else
3099 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3100 return VERR_NOT_SUPPORTED;
3101#endif
3102}
3103
3104
3105/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3106static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3107{
3108#ifdef VMSVGA3D_DX
3109ASMBreakpoint();
3110 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3111 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3112 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3113#else
3114 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3115 return VERR_NOT_SUPPORTED;
3116#endif
3117}
3118
3119
3120/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3121static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3122{
3123#ifdef VMSVGA3D_DX
3124ASMBreakpoint();
3125 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3126 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3127 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3128#else
3129 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3130 return VERR_NOT_SUPPORTED;
3131#endif
3132}
3133
3134
3135/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3136static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3137{
3138#ifdef VMSVGA3D_DX
3139ASMBreakpoint();
3140 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3141 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3142 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3143#else
3144 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3145 return VERR_NOT_SUPPORTED;
3146#endif
3147}
3148
3149
3150/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3151static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3152{
3153#ifdef VMSVGA3D_DX
3154ASMBreakpoint();
3155 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3156 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3157 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3158#else
3159 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3160 return VERR_NOT_SUPPORTED;
3161#endif
3162}
3163
3164
3165/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3166static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3167{
3168#ifdef VMSVGA3D_DX
3169ASMBreakpoint();
3170 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3171 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3172 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3173#else
3174 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3175 return VERR_NOT_SUPPORTED;
3176#endif
3177}
3178
3179
3180/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3181static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3182{
3183#ifdef VMSVGA3D_DX
3184ASMBreakpoint();
3185 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3186 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3187 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3188#else
3189 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3190 return VERR_NOT_SUPPORTED;
3191#endif
3192}
3193
3194
3195/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3196static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3197{
3198#ifdef VMSVGA3D_DX
3199ASMBreakpoint();
3200 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3201 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3202 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3203#else
3204 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3205 return VERR_NOT_SUPPORTED;
3206#endif
3207}
3208
3209
3210/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3211static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3212{
3213#ifdef VMSVGA3D_DX
3214ASMBreakpoint();
3215 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3216 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3217 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3218#else
3219 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3220 return VERR_NOT_SUPPORTED;
3221#endif
3222}
3223
3224
3225/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3226static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3227{
3228#ifdef VMSVGA3D_DX
3229ASMBreakpoint();
3230 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3231 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3232 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3233#else
3234 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3235 return VERR_NOT_SUPPORTED;
3236#endif
3237}
3238
3239
3240/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3241static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3242{
3243#ifdef VMSVGA3D_DX
3244ASMBreakpoint();
3245 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3246 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3247 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3248#else
3249 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3250 return VERR_NOT_SUPPORTED;
3251#endif
3252}
3253
3254
3255/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3256static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3257{
3258#ifdef VMSVGA3D_DX
3259ASMBreakpoint();
3260 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3261 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3262 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3263#else
3264 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3265 return VERR_NOT_SUPPORTED;
3266#endif
3267}
3268
3269
3270/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3271static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3272{
3273#ifdef VMSVGA3D_DX
3274ASMBreakpoint();
3275 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3276 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3277 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3278#else
3279 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3280 return VERR_NOT_SUPPORTED;
3281#endif
3282}
3283
3284
3285/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3286static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3287{
3288#ifdef VMSVGA3D_DX
3289ASMBreakpoint();
3290 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3291 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3292 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3293#else
3294 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3295 return VERR_NOT_SUPPORTED;
3296#endif
3297}
3298
3299
3300/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3301static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3302{
3303#ifdef VMSVGA3D_DX
3304ASMBreakpoint();
3305 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3306 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3307 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3308#else
3309 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3310 return VERR_NOT_SUPPORTED;
3311#endif
3312}
3313
3314
3315/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3316static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3317{
3318#ifdef VMSVGA3D_DX
3319ASMBreakpoint();
3320 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3321 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3322 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3323#else
3324 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3325 return VERR_NOT_SUPPORTED;
3326#endif
3327}
3328
3329
3330/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3331static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3332{
3333#ifdef VMSVGA3D_DX
3334ASMBreakpoint();
3335 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3336 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3337 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3338#else
3339 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3340 return VERR_NOT_SUPPORTED;
3341#endif
3342}
3343
3344
3345/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3346static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3347{
3348#ifdef VMSVGA3D_DX
3349ASMBreakpoint();
3350 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3351 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3352 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3353#else
3354 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3355 return VERR_NOT_SUPPORTED;
3356#endif
3357}
3358
3359
3360/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3361static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3362{
3363#ifdef VMSVGA3D_DX
3364ASMBreakpoint();
3365 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3366 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3367 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3368#else
3369 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3370 return VERR_NOT_SUPPORTED;
3371#endif
3372}
3373
3374
3375/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3376static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3377{
3378#ifdef VMSVGA3D_DX
3379ASMBreakpoint();
3380 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3381 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3382 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3383#else
3384 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3385 return VERR_NOT_SUPPORTED;
3386#endif
3387}
3388
3389
3390/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3391static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3392{
3393#ifdef VMSVGA3D_DX
3394ASMBreakpoint();
3395 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3396 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3397 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3398#else
3399 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3400 return VERR_NOT_SUPPORTED;
3401#endif
3402}
3403
3404
3405/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3406static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3407{
3408#ifdef VMSVGA3D_DX
3409ASMBreakpoint();
3410 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3411 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3412 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3413#else
3414 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3415 return VERR_NOT_SUPPORTED;
3416#endif
3417}
3418
3419
3420/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3421static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3422{
3423#ifdef VMSVGA3D_DX
3424ASMBreakpoint();
3425 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3426 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3427 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3428#else
3429 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3430 return VERR_NOT_SUPPORTED;
3431#endif
3432}
3433
3434
3435/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3436static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3437{
3438#ifdef VMSVGA3D_DX
3439ASMBreakpoint();
3440 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3441 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3442 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3443#else
3444 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3445 return VERR_NOT_SUPPORTED;
3446#endif
3447}
3448
3449
3450/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3451static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3452{
3453#ifdef VMSVGA3D_DX
3454ASMBreakpoint();
3455 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3456 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3457 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3458#else
3459 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3460 return VERR_NOT_SUPPORTED;
3461#endif
3462}
3463
3464
3465/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3466static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3467{
3468#ifdef VMSVGA3D_DX
3469ASMBreakpoint();
3470 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3471 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3472 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3473#else
3474 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3475 return VERR_NOT_SUPPORTED;
3476#endif
3477}
3478
3479
3480/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3481static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3482{
3483#ifdef VMSVGA3D_DX
3484ASMBreakpoint();
3485 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3486 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3487 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3488#else
3489 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3490 return VERR_NOT_SUPPORTED;
3491#endif
3492}
3493
3494
3495/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3496static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3497{
3498#ifdef VMSVGA3D_DX
3499ASMBreakpoint();
3500 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3501 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3502 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3503#else
3504 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3505 return VERR_NOT_SUPPORTED;
3506#endif
3507}
3508
3509
3510/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3511static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3512{
3513#ifdef VMSVGA3D_DX
3514ASMBreakpoint();
3515 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3516 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3517 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3518#else
3519 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3520 return VERR_NOT_SUPPORTED;
3521#endif
3522}
3523
3524
3525/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3526static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3527{
3528#ifdef VMSVGA3D_DX
3529ASMBreakpoint();
3530 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3531 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3532 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3533#else
3534 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3535 return VERR_NOT_SUPPORTED;
3536#endif
3537}
3538
3539
3540/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3541static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3542{
3543#ifdef VMSVGA3D_DX
3544ASMBreakpoint();
3545 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3546 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3547 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3548#else
3549 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3550 return VERR_NOT_SUPPORTED;
3551#endif
3552}
3553
3554
3555/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3556static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3557{
3558#ifdef VMSVGA3D_DX
3559ASMBreakpoint();
3560 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3561 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3562 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3563#else
3564 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3565 return VERR_NOT_SUPPORTED;
3566#endif
3567}
3568
3569
3570/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3571static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3572{
3573#ifdef VMSVGA3D_DX
3574ASMBreakpoint();
3575 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3576 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3577 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3578#else
3579 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3580 return VERR_NOT_SUPPORTED;
3581#endif
3582}
3583
3584
3585/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3586static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3587{
3588#ifdef VMSVGA3D_DX
3589ASMBreakpoint();
3590 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3591 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3592 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3593#else
3594 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3595 return VERR_NOT_SUPPORTED;
3596#endif
3597}
3598
3599
3600/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3601static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3602{
3603#ifdef VMSVGA3D_DX
3604ASMBreakpoint();
3605 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3606 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3607 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3608#else
3609 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3610 return VERR_NOT_SUPPORTED;
3611#endif
3612}
3613
3614
3615/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3616static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3617{
3618#ifdef VMSVGA3D_DX
3619ASMBreakpoint();
3620 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3621 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3622 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3623#else
3624 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3625 return VERR_NOT_SUPPORTED;
3626#endif
3627}
3628
3629
3630/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3631static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
3632{
3633#ifdef VMSVGA3D_DX
3634ASMBreakpoint();
3635 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3636 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3637 return vmsvga3dDXDefineDepthStencilView_v2(pThisCC, idDXContext);
3638#else
3639 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3640 return VERR_NOT_SUPPORTED;
3641#endif
3642}
3643
3644
3645/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3646static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
3647{
3648#ifdef VMSVGA3D_DX
3649ASMBreakpoint();
3650 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3651 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3652 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
3653#else
3654 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3655 return VERR_NOT_SUPPORTED;
3656#endif
3657}
3658
3659
3660/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3661static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
3662{
3663#ifdef VMSVGA3D_DX
3664ASMBreakpoint();
3665 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3666 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3667 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
3668#else
3669 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3670 return VERR_NOT_SUPPORTED;
3671#endif
3672}
3673
3674
3675/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3676static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
3677{
3678#ifdef VMSVGA3D_DX
3679ASMBreakpoint();
3680 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3681 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3682 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
3683#else
3684 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3685 return VERR_NOT_SUPPORTED;
3686#endif
3687}
3688
3689
3690/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3691static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
3692{
3693#ifdef VMSVGA3D_DX
3694ASMBreakpoint();
3695 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3696 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3697 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
3698#else
3699 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3700 return VERR_NOT_SUPPORTED;
3701#endif
3702}
3703
3704
3705/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3706static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
3707{
3708#ifdef VMSVGA3D_DX
3709ASMBreakpoint();
3710 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3711 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3712 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
3713#else
3714 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3715 return VERR_NOT_SUPPORTED;
3716#endif
3717}
3718
3719
3720/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3721 * Check that the 3D command has at least a_cbMin of payload bytes after the
3722 * header. Will break out of the switch if it doesn't.
3723 */
3724# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3725 if (1) { \
3726 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3727 RT_UNTRUSTED_VALIDATED_FENCE(); \
3728 } else do {} while (0)
3729
3730# define VMSVGA_3D_CMD_NOTIMPL() \
3731 if (1) { \
3732 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3733 } else do {} while (0)
3734
3735/** SVGA_3D_CMD_* handler.
3736 * This function parses the command and calls the corresponding command handler.
3737 *
3738 * @param pThis The shared VGA/VMSVGA state.
3739 * @param pThisCC The VGA/VMSVGA state for the current context.
3740 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3741 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3742 * @param cbCmd Size of the command in bytes.
3743 * @param pvCmd Pointer to the command.
3744 * @returns VBox status code if an error was detected parsing a command.
3745 */
3746int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3747{
3748 if (enmCmdId > SVGA_3D_CMD_MAX)
3749 {
3750 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3751 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3752 }
3753
3754 int rcParse = VINF_SUCCESS;
3755 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3756
3757 switch (enmCmdId)
3758 {
3759 case SVGA_3D_CMD_SURFACE_DEFINE:
3760 {
3761 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3763 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3764
3765 SVGA3dCmdDefineSurface_v2 cmd;
3766 cmd.sid = pCmd->sid;
3767 cmd.surfaceFlags = pCmd->surfaceFlags;
3768 cmd.format = pCmd->format;
3769 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3770 cmd.multisampleCount = 0;
3771 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3772
3773 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3774 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3775# ifdef DEBUG_GMR_ACCESS
3776 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3777# endif
3778 break;
3779 }
3780
3781 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3782 {
3783 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3784 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3785 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3786
3787 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3788 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3789# ifdef DEBUG_GMR_ACCESS
3790 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3791# endif
3792 break;
3793 }
3794
3795 case SVGA_3D_CMD_SURFACE_DESTROY:
3796 {
3797 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3799 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3800
3801 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3802 break;
3803 }
3804
3805 case SVGA_3D_CMD_SURFACE_COPY:
3806 {
3807 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3808 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3809 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3810
3811 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3812 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3813 break;
3814 }
3815
3816 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3817 {
3818 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3819 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3820 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3821
3822 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3823 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3824 break;
3825 }
3826
3827 case SVGA_3D_CMD_SURFACE_DMA:
3828 {
3829 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3831 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3832
3833 uint64_t u64NanoTS = 0;
3834 if (LogRelIs3Enabled())
3835 u64NanoTS = RTTimeNanoTS();
3836 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3837 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3838 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3839 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3840 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3841 if (LogRelIs3Enabled())
3842 {
3843 if (cCopyBoxes)
3844 {
3845 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3846 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3847 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3848 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3849 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3850 }
3851 }
3852 break;
3853 }
3854
3855 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3856 {
3857 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3859 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3860
3861 static uint64_t u64FrameStartNanoTS = 0;
3862 static uint64_t u64ElapsedPerSecNano = 0;
3863 static int cFrames = 0;
3864 uint64_t u64NanoTS = 0;
3865 if (LogRelIs3Enabled())
3866 u64NanoTS = RTTimeNanoTS();
3867 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3868 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3869 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3870 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3871 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3872 if (LogRelIs3Enabled())
3873 {
3874 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3875 u64ElapsedPerSecNano += u64ElapsedNano;
3876
3877 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3878 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3879 (u64ElapsedNano) / 1000ULL, cRects,
3880 pFirstRect->left, pFirstRect->top,
3881 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3882
3883 ++cFrames;
3884 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3885 {
3886 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3887 cFrames, u64ElapsedPerSecNano / 1000ULL));
3888 u64FrameStartNanoTS = u64NanoTS;
3889 cFrames = 0;
3890 u64ElapsedPerSecNano = 0;
3891 }
3892 }
3893 break;
3894 }
3895
3896 case SVGA_3D_CMD_CONTEXT_DEFINE:
3897 {
3898 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3899 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3900 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3901
3902 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3903 break;
3904 }
3905
3906 case SVGA_3D_CMD_CONTEXT_DESTROY:
3907 {
3908 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3909 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3910 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3911
3912 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3913 break;
3914 }
3915
3916 case SVGA_3D_CMD_SETTRANSFORM:
3917 {
3918 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3919 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3920 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3921
3922 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3923 break;
3924 }
3925
3926 case SVGA_3D_CMD_SETZRANGE:
3927 {
3928 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3930 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3931
3932 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3933 break;
3934 }
3935
3936 case SVGA_3D_CMD_SETRENDERSTATE:
3937 {
3938 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3939 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3940 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3941
3942 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3943 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3944 break;
3945 }
3946
3947 case SVGA_3D_CMD_SETRENDERTARGET:
3948 {
3949 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3950 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3951 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3952
3953 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3954 break;
3955 }
3956
3957 case SVGA_3D_CMD_SETTEXTURESTATE:
3958 {
3959 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3960 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3961 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3962
3963 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3964 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3965 break;
3966 }
3967
3968 case SVGA_3D_CMD_SETMATERIAL:
3969 {
3970 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3971 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3972 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3973
3974 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3975 break;
3976 }
3977
3978 case SVGA_3D_CMD_SETLIGHTDATA:
3979 {
3980 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3981 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3982 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3983
3984 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3985 break;
3986 }
3987
3988 case SVGA_3D_CMD_SETLIGHTENABLED:
3989 {
3990 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3992 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3993
3994 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3995 break;
3996 }
3997
3998 case SVGA_3D_CMD_SETVIEWPORT:
3999 {
4000 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4001 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4002 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4003
4004 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4005 break;
4006 }
4007
4008 case SVGA_3D_CMD_SETCLIPPLANE:
4009 {
4010 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4011 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4012 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4013
4014 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4015 break;
4016 }
4017
4018 case SVGA_3D_CMD_CLEAR:
4019 {
4020 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4021 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4022 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4023
4024 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4025 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4026 break;
4027 }
4028
4029 case SVGA_3D_CMD_PRESENT:
4030 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4031 {
4032 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4033 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4034 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4035 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4036 else
4037 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4038
4039 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4040 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4041 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4042 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4043 break;
4044 }
4045
4046 case SVGA_3D_CMD_SHADER_DEFINE:
4047 {
4048 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4049 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4050 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4051
4052 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4053 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4054 break;
4055 }
4056
4057 case SVGA_3D_CMD_SHADER_DESTROY:
4058 {
4059 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4060 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4061 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4062
4063 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4064 break;
4065 }
4066
4067 case SVGA_3D_CMD_SET_SHADER:
4068 {
4069 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4071 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4072
4073 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4074 break;
4075 }
4076
4077 case SVGA_3D_CMD_SET_SHADER_CONST:
4078 {
4079 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4080 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4081 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4082
4083 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4084 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4085 break;
4086 }
4087
4088 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4089 {
4090 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4091 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4092 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4093
4094 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4095 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4096 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4097 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4098 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4099
4100 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4101 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4102 RT_UNTRUSTED_VALIDATED_FENCE();
4103
4104 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4105 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4106 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4107
4108 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4109 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4110 pNumRange, cVertexDivisor, pVertexDivisor);
4111 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4112 break;
4113 }
4114
4115 case SVGA_3D_CMD_SETSCISSORRECT:
4116 {
4117 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4119 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4120
4121 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4122 break;
4123 }
4124
4125 case SVGA_3D_CMD_BEGIN_QUERY:
4126 {
4127 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4128 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4129 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4130
4131 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4132 break;
4133 }
4134
4135 case SVGA_3D_CMD_END_QUERY:
4136 {
4137 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4138 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4139 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4140
4141 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4142 break;
4143 }
4144
4145 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4146 {
4147 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4148 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4149 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4150
4151 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4152 break;
4153 }
4154
4155 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4156 {
4157 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4158 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4159 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4160
4161 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4162 break;
4163 }
4164
4165 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4166 /* context id + surface id? */
4167 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4168 break;
4169
4170 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4171 /* context id + surface id? */
4172 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4173 break;
4174
4175 /*
4176 *
4177 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4178 *
4179 */
4180 case SVGA_3D_CMD_SCREEN_DMA:
4181 {
4182 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4183 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4184 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4185 break;
4186 }
4187
4188 case SVGA_3D_CMD_DEAD1:
4189 case SVGA_3D_CMD_DEAD2:
4190 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4191 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4192 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4193 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4194 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4195 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4196 {
4197 VMSVGA_3D_CMD_NOTIMPL();
4198 break;
4199 }
4200
4201 case SVGA_3D_CMD_SET_OTABLE_BASE:
4202 {
4203 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4204 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4205 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4206 break;
4207 }
4208
4209 case SVGA_3D_CMD_READBACK_OTABLE:
4210 {
4211 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4212 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4213 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4214 break;
4215 }
4216
4217 case SVGA_3D_CMD_DEFINE_GB_MOB:
4218 {
4219 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4220 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4221 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4222 break;
4223 }
4224
4225 case SVGA_3D_CMD_DESTROY_GB_MOB:
4226 {
4227 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4228 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4229 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4230 break;
4231 }
4232
4233 case SVGA_3D_CMD_DEAD3:
4234 {
4235 VMSVGA_3D_CMD_NOTIMPL();
4236 break;
4237 }
4238
4239 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4240 {
4241 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4242 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4243 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4244 break;
4245 }
4246
4247 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4248 {
4249 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4250 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4251 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4252 break;
4253 }
4254
4255 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4256 {
4257 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4258 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4259 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4260 break;
4261 }
4262
4263 case SVGA_3D_CMD_BIND_GB_SURFACE:
4264 {
4265 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4267 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4268 break;
4269 }
4270
4271 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4272 {
4273 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4275 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4276 break;
4277 }
4278
4279 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4280 {
4281 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4282 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4283 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4284 break;
4285 }
4286
4287 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4288 {
4289 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4291 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4292 break;
4293 }
4294
4295 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4296 {
4297 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4299 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4300 break;
4301 }
4302
4303 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4304 {
4305 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4306 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4307 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4308 break;
4309 }
4310
4311 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4312 {
4313 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4315 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4316 break;
4317 }
4318
4319 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4320 {
4321 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4323 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4324 break;
4325 }
4326
4327 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4328 {
4329 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4330 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4331 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4332 break;
4333 }
4334
4335 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4336 {
4337 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4339 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4340 break;
4341 }
4342
4343 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4344 {
4345 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4346 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4347 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4348 break;
4349 }
4350
4351 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4352 {
4353 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4355 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4356 break;
4357 }
4358
4359 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4360 {
4361 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4363 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4364 break;
4365 }
4366
4367 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4368 {
4369 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4372 break;
4373 }
4374
4375 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4376 {
4377 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4379 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4380 break;
4381 }
4382
4383 case SVGA_3D_CMD_BIND_GB_SHADER:
4384 {
4385 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4387 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4388 break;
4389 }
4390
4391 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4392 {
4393 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4396 break;
4397 }
4398
4399 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4400 {
4401 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4403 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4404 break;
4405 }
4406
4407 case SVGA_3D_CMD_END_GB_QUERY:
4408 {
4409 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4410 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4411 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4412 break;
4413 }
4414
4415 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4416 {
4417 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4419 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4420 break;
4421 }
4422
4423 case SVGA_3D_CMD_NOP:
4424 {
4425 /* Apparently there is nothing to do. */
4426 break;
4427 }
4428
4429 case SVGA_3D_CMD_ENABLE_GART:
4430 {
4431 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4433 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4434 break;
4435 }
4436
4437 case SVGA_3D_CMD_DISABLE_GART:
4438 {
4439 /* No corresponding SVGA3dCmd structure. */
4440 VMSVGA_3D_CMD_NOTIMPL();
4441 break;
4442 }
4443
4444 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4445 {
4446 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4447 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4449 break;
4450 }
4451
4452 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4453 {
4454 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4455 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4457 break;
4458 }
4459
4460 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4461 {
4462 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4464 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4465 break;
4466 }
4467
4468 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4469 {
4470 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4471 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4472 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4473 break;
4474 }
4475
4476 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4477 {
4478 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4479 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4480 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4481 break;
4482 }
4483
4484 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4485 {
4486 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4489 break;
4490 }
4491
4492 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4493 {
4494 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4495 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4496 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4497 break;
4498 }
4499
4500 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4501 {
4502 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4505 break;
4506 }
4507
4508 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4509 {
4510 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4511 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4512 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4513 break;
4514 }
4515
4516 case SVGA_3D_CMD_GB_SCREEN_DMA:
4517 {
4518 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4519 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4520 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4521 break;
4522 }
4523
4524 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4525 {
4526 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4528 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4529 break;
4530 }
4531
4532 case SVGA_3D_CMD_GB_MOB_FENCE:
4533 {
4534 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4535 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4536 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4537 break;
4538 }
4539
4540 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4541 {
4542 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4543 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4545 break;
4546 }
4547
4548 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4549 {
4550 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4551 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4552 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4553 break;
4554 }
4555
4556 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4557 {
4558 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4559 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4560 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4561 break;
4562 }
4563
4564 case SVGA_3D_CMD_NOP_ERROR:
4565 {
4566 /* Apparently there is nothing to do. */
4567 break;
4568 }
4569
4570 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4571 {
4572 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4573 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4574 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4575 break;
4576 }
4577
4578 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4579 {
4580 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4581 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4582 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4583 break;
4584 }
4585
4586 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4587 {
4588 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4589 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4590 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4591 break;
4592 }
4593
4594 case SVGA_3D_CMD_DRAW:
4595 {
4596 /* No corresponding SVGA3dCmd structure. */
4597 VMSVGA_3D_CMD_NOTIMPL();
4598 break;
4599 }
4600
4601 case SVGA_3D_CMD_DRAW_INDEXED:
4602 {
4603 /* No corresponding SVGA3dCmd structure. */
4604 VMSVGA_3D_CMD_NOTIMPL();
4605 break;
4606 }
4607
4608 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4609 {
4610 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4611 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4612 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4613 break;
4614 }
4615
4616 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4617 {
4618 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4619 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4620 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4621 break;
4622 }
4623
4624 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4625 {
4626 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4627 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4628 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
4629 break;
4630 }
4631
4632 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4633 {
4634 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4635 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4636 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, idDXContext, pCmd, cbCmd);
4637 break;
4638 }
4639
4640 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4641 {
4642 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4643 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4644 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
4645 break;
4646 }
4647
4648 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4649 {
4650 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4651 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4652 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4653 break;
4654 }
4655
4656 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4657 {
4658 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4659 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
4661 break;
4662 }
4663
4664 case SVGA_3D_CMD_DX_SET_SHADER:
4665 {
4666 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4667 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
4669 break;
4670 }
4671
4672 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4673 {
4674 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4675 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4676 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
4677 break;
4678 }
4679
4680 case SVGA_3D_CMD_DX_DRAW:
4681 {
4682 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4683 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4684 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
4685 break;
4686 }
4687
4688 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4689 {
4690 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4691 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4692 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
4693 break;
4694 }
4695
4696 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4697 {
4698 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4699 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4700 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4701 break;
4702 }
4703
4704 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4705 {
4706 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4707 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4709 break;
4710 }
4711
4712 case SVGA_3D_CMD_DX_DRAW_AUTO:
4713 {
4714 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4715 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4716 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
4717 break;
4718 }
4719
4720 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4721 {
4722 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4723 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4724 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
4725 break;
4726 }
4727
4728 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4729 {
4730 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4731 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4732 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
4733 break;
4734 }
4735
4736 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4737 {
4738 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4739 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4740 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4741 break;
4742 }
4743
4744 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4745 {
4746 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4747 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4748 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
4749 break;
4750 }
4751
4752 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4753 {
4754 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4755 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4756 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
4757 break;
4758 }
4759
4760 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4761 {
4762 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4763 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4764 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
4765 break;
4766 }
4767
4768 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4769 {
4770 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4771 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4772 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
4773 break;
4774 }
4775
4776 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4777 {
4778 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4779 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4780 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
4781 break;
4782 }
4783
4784 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4785 {
4786 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4787 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4788 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
4789 break;
4790 }
4791
4792 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4793 {
4794 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4795 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4796 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
4797 break;
4798 }
4799
4800 case SVGA_3D_CMD_DX_BIND_QUERY:
4801 {
4802 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4803 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
4805 break;
4806 }
4807
4808 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4809 {
4810 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4811 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4812 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
4813 break;
4814 }
4815
4816 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4817 {
4818 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4819 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4820 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
4821 break;
4822 }
4823
4824 case SVGA_3D_CMD_DX_END_QUERY:
4825 {
4826 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4827 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4828 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
4829 break;
4830 }
4831
4832 case SVGA_3D_CMD_DX_READBACK_QUERY:
4833 {
4834 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4835 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4836 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
4837 break;
4838 }
4839
4840 case SVGA_3D_CMD_DX_SET_PREDICATION:
4841 {
4842 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4843 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4844 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
4845 break;
4846 }
4847
4848 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4849 {
4850 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4851 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4852 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
4853 break;
4854 }
4855
4856 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4857 {
4858 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4859 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4860 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
4861 break;
4862 }
4863
4864 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4865 {
4866 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4867 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4868 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
4869 break;
4870 }
4871
4872 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4873 {
4874 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4875 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4876 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4877 break;
4878 }
4879
4880 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4881 {
4882 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4883 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4884 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4885 break;
4886 }
4887
4888 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4889 {
4890 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4891 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4892 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
4893 break;
4894 }
4895
4896 case SVGA_3D_CMD_DX_PRED_COPY:
4897 {
4898 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4899 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4900 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
4901 break;
4902 }
4903
4904 case SVGA_3D_CMD_DX_PRESENTBLT:
4905 {
4906 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4907 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4908 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
4909 break;
4910 }
4911
4912 case SVGA_3D_CMD_DX_GENMIPS:
4913 {
4914 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4915 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4916 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
4917 break;
4918 }
4919
4920 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4921 {
4922 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4923 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4924 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4925 break;
4926 }
4927
4928 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4929 {
4930 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4931 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4932 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4933 break;
4934 }
4935
4936 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4937 {
4938 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4939 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4940 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4941 break;
4942 }
4943
4944 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4945 {
4946 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4947 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4948 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4949 break;
4950 }
4951
4952 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4953 {
4954 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4955 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4956 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4957 break;
4958 }
4959
4960 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4961 {
4962 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4964 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4965 break;
4966 }
4967
4968 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
4969 {
4970 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
4971 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4972 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4973 break;
4974 }
4975
4976 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
4977 {
4978 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
4979 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4980 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4981 break;
4982 }
4983
4984 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
4985 {
4986 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
4987 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4988 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4989 break;
4990 }
4991
4992 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
4993 {
4994 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
4995 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4996 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
4997 break;
4998 }
4999
5000 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5001 {
5002 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5003 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5004 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5005 break;
5006 }
5007
5008 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5009 {
5010 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5011 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5012 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5013 break;
5014 }
5015
5016 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5017 {
5018 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5019 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5020 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5021 break;
5022 }
5023
5024 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5025 {
5026 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5027 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5028 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5029 break;
5030 }
5031
5032 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5033 {
5034 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5035 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5036 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5037 break;
5038 }
5039
5040 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5041 {
5042 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5043 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5044 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5045 break;
5046 }
5047
5048 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5049 {
5050 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5051 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5052 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5053 break;
5054 }
5055
5056 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5057 {
5058 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5059 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5060 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5061 break;
5062 }
5063
5064 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5065 {
5066 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5067 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5068 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5069 break;
5070 }
5071
5072 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5073 {
5074 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5075 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5076 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5077 break;
5078 }
5079
5080 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5081 {
5082 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5083 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5084 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5085 break;
5086 }
5087
5088 case SVGA_3D_CMD_DX_BIND_SHADER:
5089 {
5090 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5091 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5092 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5093 break;
5094 }
5095
5096 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5097 {
5098 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5099 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5100 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5101 break;
5102 }
5103
5104 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5105 {
5106 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5107 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5108 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5109 break;
5110 }
5111
5112 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5113 {
5114 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5115 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5116 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5117 break;
5118 }
5119
5120 case SVGA_3D_CMD_DX_SET_COTABLE:
5121 {
5122 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5123 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5124 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5125 break;
5126 }
5127
5128 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5129 {
5130 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5131 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5132 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5133 break;
5134 }
5135
5136 case SVGA_3D_CMD_DX_BUFFER_COPY:
5137 {
5138 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5139 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5140 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5141 break;
5142 }
5143
5144 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5145 {
5146 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5147 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5148 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5149 break;
5150 }
5151
5152 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5153 {
5154 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5155 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5156 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5157 break;
5158 }
5159
5160 case SVGA_3D_CMD_DX_MOVE_QUERY:
5161 {
5162 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5163 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5164 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5165 break;
5166 }
5167
5168 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5169 {
5170 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5171 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5172 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5173 break;
5174 }
5175
5176 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5177 {
5178 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5180 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5181 break;
5182 }
5183
5184 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5185 {
5186 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5187 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5188 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5189 break;
5190 }
5191
5192 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5193 {
5194 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5195 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5196 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5197 break;
5198 }
5199
5200 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5201 {
5202 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5203 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5204 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5205 break;
5206 }
5207
5208 case SVGA_3D_CMD_DX_HINT:
5209 {
5210 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5211 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5212 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5213 break;
5214 }
5215
5216 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5217 {
5218 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5219 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5220 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5221 break;
5222 }
5223
5224 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5225 {
5226 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5227 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5228 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5229 break;
5230 }
5231
5232 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5233 {
5234 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5235 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5236 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5237 break;
5238 }
5239
5240 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5241 {
5242 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5243 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5244 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5245 break;
5246 }
5247
5248 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5249 {
5250 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5251 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5252 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5253 break;
5254 }
5255
5256 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5257 {
5258 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5259 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5260 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5261 break;
5262 }
5263
5264 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5265 {
5266 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5267 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5268 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5269 break;
5270 }
5271
5272 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5273 {
5274 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5275 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5276 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5277 break;
5278 }
5279
5280 case SVGA_3D_CMD_SCREEN_COPY:
5281 {
5282 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5283 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5284 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5285 break;
5286 }
5287
5288 case SVGA_3D_CMD_RESERVED1:
5289 {
5290 VMSVGA_3D_CMD_NOTIMPL();
5291 break;
5292 }
5293
5294 case SVGA_3D_CMD_RESERVED2:
5295 {
5296 VMSVGA_3D_CMD_NOTIMPL();
5297 break;
5298 }
5299
5300 case SVGA_3D_CMD_RESERVED3:
5301 {
5302 VMSVGA_3D_CMD_NOTIMPL();
5303 break;
5304 }
5305
5306 case SVGA_3D_CMD_RESERVED4:
5307 {
5308 VMSVGA_3D_CMD_NOTIMPL();
5309 break;
5310 }
5311
5312 case SVGA_3D_CMD_RESERVED5:
5313 {
5314 VMSVGA_3D_CMD_NOTIMPL();
5315 break;
5316 }
5317
5318 case SVGA_3D_CMD_RESERVED6:
5319 {
5320 VMSVGA_3D_CMD_NOTIMPL();
5321 break;
5322 }
5323
5324 case SVGA_3D_CMD_RESERVED7:
5325 {
5326 VMSVGA_3D_CMD_NOTIMPL();
5327 break;
5328 }
5329
5330 case SVGA_3D_CMD_RESERVED8:
5331 {
5332 VMSVGA_3D_CMD_NOTIMPL();
5333 break;
5334 }
5335
5336 case SVGA_3D_CMD_GROW_OTABLE:
5337 {
5338 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5339 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5340 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5341 break;
5342 }
5343
5344 case SVGA_3D_CMD_DX_GROW_COTABLE:
5345 {
5346 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5347 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5348 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5349 break;
5350 }
5351
5352 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5353 {
5354 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5355 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5356 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5357 break;
5358 }
5359
5360 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5361 {
5362 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5363 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5364 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5365 break;
5366 }
5367
5368 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5369 {
5370 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5371 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5372 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5373 break;
5374 }
5375
5376 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5377 {
5378 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5379 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5380 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5381 break;
5382 }
5383
5384 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5385 {
5386 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5387 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5388 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5389 break;
5390 }
5391
5392 case SVGA_3D_CMD_DX_PRED_CONVERT:
5393 {
5394 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5395 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5396 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5397 break;
5398 }
5399
5400 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5401 {
5402 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5403 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5404 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5405 break;
5406 }
5407
5408 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5409 {
5410 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5411 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5412 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5413 break;
5414 }
5415
5416 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5417 {
5418 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5419 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5420 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5421 break;
5422 }
5423
5424 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5425 {
5426 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5427 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5428 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5429 break;
5430 }
5431
5432 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5433 {
5434 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5435 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5436 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5437 break;
5438 }
5439
5440 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5441 {
5442 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5443 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5444 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5445 break;
5446 }
5447
5448 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5449 {
5450 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5451 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5452 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5453 break;
5454 }
5455
5456 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5457 {
5458 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5459 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5460 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5461 break;
5462 }
5463
5464 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5465 {
5466 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5467 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5468 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5469 break;
5470 }
5471
5472 case SVGA_3D_CMD_DX_DISPATCH:
5473 {
5474 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5475 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5476 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5477 break;
5478 }
5479
5480 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5481 {
5482 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5483 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5484 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5485 break;
5486 }
5487
5488 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5489 {
5490 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5491 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5492 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5493 break;
5494 }
5495
5496 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5497 {
5498 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5499 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5500 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5501 break;
5502 }
5503
5504 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5505 {
5506 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5507 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5508 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5509 break;
5510 }
5511
5512 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5513 {
5514 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5515 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5516 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5517 break;
5518 }
5519
5520 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5521 {
5522 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5523 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5524 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5525 break;
5526 }
5527
5528 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5529 {
5530 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5531 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5532 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5533 break;
5534 }
5535
5536 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5537 {
5538 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5539 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5540 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5541 break;
5542 }
5543
5544 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5545 {
5546 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5547 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5548 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5549 break;
5550 }
5551
5552 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5553 {
5554 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5555 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5556 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5557 break;
5558 }
5559
5560 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5561 {
5562 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5563 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5564 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5565 break;
5566 }
5567
5568 case SVGA_3D_CMD_RESERVED2_1:
5569 {
5570 VMSVGA_3D_CMD_NOTIMPL();
5571 break;
5572 }
5573
5574 case SVGA_3D_CMD_RESERVED2_2:
5575 {
5576 VMSVGA_3D_CMD_NOTIMPL();
5577 break;
5578 }
5579
5580 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5581 {
5582 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5584 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5585 break;
5586 }
5587
5588 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5589 {
5590 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5592 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5593 break;
5594 }
5595
5596 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5597 {
5598 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5600 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5601 break;
5602 }
5603
5604 case SVGA_3D_CMD_RESERVED2_3:
5605 {
5606 VMSVGA_3D_CMD_NOTIMPL();
5607 break;
5608 }
5609
5610 case SVGA_3D_CMD_RESERVED2_4:
5611 {
5612 VMSVGA_3D_CMD_NOTIMPL();
5613 break;
5614 }
5615
5616 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5617 {
5618 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5619 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5620 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5621 break;
5622 }
5623
5624 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5625 {
5626 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5627 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5628 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
5629 break;
5630 }
5631
5632 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5633 {
5634 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5635 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5636 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5637 break;
5638 }
5639
5640 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5641 {
5642 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5643 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5644 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5645 break;
5646 }
5647
5648 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5649 {
5650 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5651 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5652 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
5653 break;
5654 }
5655
5656 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5657 {
5658 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5659 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5660 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5661 break;
5662 }
5663
5664 /* Unsupported commands. */
5665 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5666 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5667 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5668 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5669 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5670 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5671 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5672 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5673 /* Prevent the compiler warning. */
5674 case SVGA_3D_CMD_LEGACY_BASE:
5675 case SVGA_3D_CMD_MAX:
5676 case SVGA_3D_CMD_FUTURE_MAX:
5677 /* No 'default' case */
5678 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5679 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5680 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5681 rcParse = VERR_NOT_IMPLEMENTED;
5682 break;
5683 }
5684
5685 return VINF_SUCCESS;
5686// return rcParse;
5687}
5688# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5689#endif /* VBOX_WITH_VMSVGA3D */
5690
5691
5692/*
5693 *
5694 * Handlers for FIFO commands.
5695 *
5696 * Every handler takes the following parameters:
5697 *
5698 * pThis The shared VGA/VMSVGA state.
5699 * pThisCC The VGA/VMSVGA state for ring-3.
5700 * pCmd The command data.
5701 */
5702
5703
5704/* SVGA_CMD_UPDATE */
5705void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5706{
5707 RT_NOREF(pThis);
5708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5709
5710 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5711 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5712
5713 /** @todo Multiple screens? */
5714 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5715 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5716 return;
5717
5718 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5719}
5720
5721
5722/* SVGA_CMD_UPDATE_VERBOSE */
5723void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5724{
5725 RT_NOREF(pThis);
5726 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5727
5728 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5729 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5730
5731 /** @todo Multiple screens? */
5732 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5733 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5734 return;
5735
5736 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5737}
5738
5739
5740/* SVGA_CMD_RECT_FILL */
5741void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5742{
5743 RT_NOREF(pThis, pCmd);
5744 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5745
5746 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5747 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5748 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5749}
5750
5751
5752/* SVGA_CMD_RECT_COPY */
5753void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5754{
5755 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5756
5757 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5758 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5759
5760 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5761 AssertPtrReturnVoid(pScreen);
5762
5763 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5764 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5765 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5766 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5767 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5768 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5769 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5770
5771 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5772 pCmd->width, pCmd->height, pThis->vram_size);
5773 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5774}
5775
5776
5777/* SVGA_CMD_RECT_ROP_COPY */
5778void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5779{
5780 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5781
5782 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5783 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5784
5785 if (pCmd->rop != SVGA_ROP_COPY)
5786 {
5787 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5788 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5789 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5790 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5791 */
5792 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5793 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5794 return;
5795 }
5796
5797 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5798 AssertPtrReturnVoid(pScreen);
5799
5800 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5801 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5802 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5803 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5804 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5805 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5806 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5807
5808 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5809 pCmd->width, pCmd->height, pThis->vram_size);
5810 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5811}
5812
5813
5814/* SVGA_CMD_DISPLAY_CURSOR */
5815void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5816{
5817 RT_NOREF(pThis, pCmd);
5818 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5819
5820 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5821 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5822 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5823}
5824
5825
5826/* SVGA_CMD_MOVE_CURSOR */
5827void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5828{
5829 RT_NOREF(pThis, pCmd);
5830 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5831
5832 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5833 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5834 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5835}
5836
5837
5838/* SVGA_CMD_DEFINE_CURSOR */
5839void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5840{
5841 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5842
5843 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5844 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5845 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5846
5847 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5848 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5849 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5850 RT_UNTRUSTED_VALIDATED_FENCE();
5851
5852 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5853 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5854 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5855
5856 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5857 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5858
5859 uint32_t const cx = pCmd->width;
5860 uint32_t const cy = pCmd->height;
5861
5862 /*
5863 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5864 * The AND data uses 8-bit aligned scanlines.
5865 * The XOR data must be starting on a 32-bit boundrary.
5866 */
5867 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5868 uint32_t cbDstAndMask = cbDstAndLine * cy;
5869 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5870 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5871
5872 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5873 AssertReturnVoid(pbCopy);
5874
5875 /* Convert the AND mask. */
5876 uint8_t *pbDst = pbCopy;
5877 uint8_t const *pbSrc = pbSrcAndMask;
5878 switch (pCmd->andMaskDepth)
5879 {
5880 case 1:
5881 if (cbSrcAndLine == cbDstAndLine)
5882 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5883 else
5884 {
5885 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5886 for (uint32_t y = 0; y < cy; y++)
5887 {
5888 memcpy(pbDst, pbSrc, cbDstAndLine);
5889 pbDst += cbDstAndLine;
5890 pbSrc += cbSrcAndLine;
5891 }
5892 }
5893 break;
5894 /* Should take the XOR mask into account for the multi-bit AND mask. */
5895 case 8:
5896 for (uint32_t y = 0; y < cy; y++)
5897 {
5898 for (uint32_t x = 0; x < cx; )
5899 {
5900 uint8_t bDst = 0;
5901 uint8_t fBit = 0x80;
5902 do
5903 {
5904 uintptr_t const idxPal = pbSrc[x] * 3;
5905 if ((( pThis->last_palette[idxPal]
5906 | (pThis->last_palette[idxPal] >> 8)
5907 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5908 bDst |= fBit;
5909 fBit >>= 1;
5910 x++;
5911 } while (x < cx && (x & 7));
5912 pbDst[(x - 1) / 8] = bDst;
5913 }
5914 pbDst += cbDstAndLine;
5915 pbSrc += cbSrcAndLine;
5916 }
5917 break;
5918 case 15:
5919 for (uint32_t y = 0; y < cy; y++)
5920 {
5921 for (uint32_t x = 0; x < cx; )
5922 {
5923 uint8_t bDst = 0;
5924 uint8_t fBit = 0x80;
5925 do
5926 {
5927 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5928 bDst |= fBit;
5929 fBit >>= 1;
5930 x++;
5931 } while (x < cx && (x & 7));
5932 pbDst[(x - 1) / 8] = bDst;
5933 }
5934 pbDst += cbDstAndLine;
5935 pbSrc += cbSrcAndLine;
5936 }
5937 break;
5938 case 16:
5939 for (uint32_t y = 0; y < cy; y++)
5940 {
5941 for (uint32_t x = 0; x < cx; )
5942 {
5943 uint8_t bDst = 0;
5944 uint8_t fBit = 0x80;
5945 do
5946 {
5947 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5948 bDst |= fBit;
5949 fBit >>= 1;
5950 x++;
5951 } while (x < cx && (x & 7));
5952 pbDst[(x - 1) / 8] = bDst;
5953 }
5954 pbDst += cbDstAndLine;
5955 pbSrc += cbSrcAndLine;
5956 }
5957 break;
5958 case 24:
5959 for (uint32_t y = 0; y < cy; y++)
5960 {
5961 for (uint32_t x = 0; x < cx; )
5962 {
5963 uint8_t bDst = 0;
5964 uint8_t fBit = 0x80;
5965 do
5966 {
5967 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
5968 bDst |= fBit;
5969 fBit >>= 1;
5970 x++;
5971 } while (x < cx && (x & 7));
5972 pbDst[(x - 1) / 8] = bDst;
5973 }
5974 pbDst += cbDstAndLine;
5975 pbSrc += cbSrcAndLine;
5976 }
5977 break;
5978 case 32:
5979 for (uint32_t y = 0; y < cy; y++)
5980 {
5981 for (uint32_t x = 0; x < cx; )
5982 {
5983 uint8_t bDst = 0;
5984 uint8_t fBit = 0x80;
5985 do
5986 {
5987 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
5988 bDst |= fBit;
5989 fBit >>= 1;
5990 x++;
5991 } while (x < cx && (x & 7));
5992 pbDst[(x - 1) / 8] = bDst;
5993 }
5994 pbDst += cbDstAndLine;
5995 pbSrc += cbSrcAndLine;
5996 }
5997 break;
5998 default:
5999 RTMemFreeZ(pbCopy, cbCopy);
6000 AssertFailedReturnVoid();
6001 }
6002
6003 /* Convert the XOR mask. */
6004 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6005 pbSrc = pbSrcXorMask;
6006 switch (pCmd->xorMaskDepth)
6007 {
6008 case 1:
6009 for (uint32_t y = 0; y < cy; y++)
6010 {
6011 for (uint32_t x = 0; x < cx; )
6012 {
6013 /* most significant bit is the left most one. */
6014 uint8_t bSrc = pbSrc[x / 8];
6015 do
6016 {
6017 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6018 bSrc <<= 1;
6019 x++;
6020 } while ((x & 7) && x < cx);
6021 }
6022 pbSrc += cbSrcXorLine;
6023 }
6024 break;
6025 case 8:
6026 for (uint32_t y = 0; y < cy; y++)
6027 {
6028 for (uint32_t x = 0; x < cx; x++)
6029 {
6030 uint32_t u = pThis->last_palette[pbSrc[x]];
6031 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6032 }
6033 pbSrc += cbSrcXorLine;
6034 }
6035 break;
6036 case 15: /* Src: RGB-5-5-5 */
6037 for (uint32_t y = 0; y < cy; y++)
6038 {
6039 for (uint32_t x = 0; x < cx; x++)
6040 {
6041 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6042 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6043 ((uValue >> 5) & 0x1f) << 3,
6044 ((uValue >> 10) & 0x1f) << 3, 0);
6045 }
6046 pbSrc += cbSrcXorLine;
6047 }
6048 break;
6049 case 16: /* Src: RGB-5-6-5 */
6050 for (uint32_t y = 0; y < cy; y++)
6051 {
6052 for (uint32_t x = 0; x < cx; x++)
6053 {
6054 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6055 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6056 ((uValue >> 5) & 0x3f) << 2,
6057 ((uValue >> 11) & 0x1f) << 3, 0);
6058 }
6059 pbSrc += cbSrcXorLine;
6060 }
6061 break;
6062 case 24:
6063 for (uint32_t y = 0; y < cy; y++)
6064 {
6065 for (uint32_t x = 0; x < cx; x++)
6066 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6067 pbSrc += cbSrcXorLine;
6068 }
6069 break;
6070 case 32:
6071 for (uint32_t y = 0; y < cy; y++)
6072 {
6073 for (uint32_t x = 0; x < cx; x++)
6074 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6075 pbSrc += cbSrcXorLine;
6076 }
6077 break;
6078 default:
6079 RTMemFreeZ(pbCopy, cbCopy);
6080 AssertFailedReturnVoid();
6081 }
6082
6083 /*
6084 * Pass it to the frontend/whatever.
6085 */
6086 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6087 cx, cy, pbCopy, cbCopy);
6088}
6089
6090
6091/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6092void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6093{
6094 RT_NOREF(pThis);
6095 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6096
6097 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6098 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6099
6100 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6101 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6102 RT_UNTRUSTED_VALIDATED_FENCE();
6103
6104 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6105 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6106 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6107 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6108 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6109
6110 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6111 AssertPtrReturnVoid(pCursorCopy);
6112
6113 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6114 memset(pCursorCopy, 0xff, cbAndMask);
6115 /* Colour data */
6116 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6117
6118 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6119 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6120}
6121
6122
6123/* SVGA_CMD_ESCAPE */
6124void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6125{
6126 RT_NOREF(pThis);
6127 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6128
6129 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6130
6131 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6132 {
6133 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6134 RT_UNTRUSTED_VALIDATED_FENCE();
6135
6136 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6137 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6138
6139 switch (cmd)
6140 {
6141 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6142 {
6143 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6144 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6145 RT_UNTRUSTED_VALIDATED_FENCE();
6146
6147 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6148
6149 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6150 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6151 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6152 RT_NOREF_PV(pVideoCmd);
6153 break;
6154 }
6155
6156 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6157 {
6158 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6159 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6160 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6161 RT_NOREF_PV(pVideoCmd);
6162 break;
6163 }
6164
6165 default:
6166 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6167 break;
6168 }
6169 }
6170 else
6171 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6172}
6173
6174
6175/* SVGA_CMD_DEFINE_SCREEN */
6176void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6177{
6178 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6179
6180 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6181 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6182 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6183 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6184
6185 uint32_t const idScreen = pCmd->screen.id;
6186 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6187
6188 uint32_t const uWidth = pCmd->screen.size.width;
6189 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6190
6191 uint32_t const uHeight = pCmd->screen.size.height;
6192 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6193
6194 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6195 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6196 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6197
6198 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6199 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6200
6201 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6202 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6203 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6204 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6205 RT_UNTRUSTED_VALIDATED_FENCE();
6206
6207 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6208 pScreen->fDefined = true;
6209 pScreen->fModified = true;
6210 pScreen->fuScreen = pCmd->screen.flags;
6211 pScreen->idScreen = idScreen;
6212 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6213 {
6214 /* Not blanked. */
6215 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6216 RT_UNTRUSTED_VALIDATED_FENCE();
6217
6218 pScreen->xOrigin = pCmd->screen.root.x;
6219 pScreen->yOrigin = pCmd->screen.root.y;
6220 pScreen->cWidth = uWidth;
6221 pScreen->cHeight = uHeight;
6222 pScreen->offVRAM = uScreenOffset;
6223 pScreen->cbPitch = cbPitch;
6224 pScreen->cBpp = 32;
6225 }
6226 else
6227 {
6228 /* Screen blanked. Keep old values. */
6229 }
6230
6231 pThis->svga.fGFBRegisters = false;
6232 vmsvgaR3ChangeMode(pThis, pThisCC);
6233
6234#ifdef VBOX_WITH_VMSVGA3D
6235 if (RT_LIKELY(pThis->svga.f3DEnabled))
6236 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6237#endif
6238}
6239
6240
6241/* SVGA_CMD_DESTROY_SCREEN */
6242void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6243{
6244 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6245
6246 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6247 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6248
6249 uint32_t const idScreen = pCmd->screenId;
6250 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6251 RT_UNTRUSTED_VALIDATED_FENCE();
6252
6253 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6254 pScreen->fModified = true;
6255 pScreen->fDefined = false;
6256 pScreen->idScreen = idScreen;
6257
6258#ifdef VBOX_WITH_VMSVGA3D
6259 if (RT_LIKELY(pThis->svga.f3DEnabled))
6260 vmsvga3dDestroyScreen(pThisCC, pScreen);
6261#endif
6262 vmsvgaR3ChangeMode(pThis, pThisCC);
6263}
6264
6265
6266/* SVGA_CMD_DEFINE_GMRFB */
6267void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6268{
6269 RT_NOREF(pThis);
6270 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6271
6272 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6273 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6274 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6275
6276 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6277 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6278 pSvgaR3State->GMRFB.format = pCmd->format;
6279}
6280
6281
6282/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6283void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6284{
6285 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6286
6287 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6288 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6289 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6290
6291 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6292 RT_UNTRUSTED_VALIDATED_FENCE();
6293
6294 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6295 AssertPtrReturnVoid(pScreen);
6296
6297 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6298 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6299
6300 /* Clip destRect to the screen dimensions. */
6301 SVGASignedRect screenRect;
6302 screenRect.left = 0;
6303 screenRect.top = 0;
6304 screenRect.right = pScreen->cWidth;
6305 screenRect.bottom = pScreen->cHeight;
6306 SVGASignedRect clipRect = pCmd->destRect;
6307 vmsvgaR3ClipRect(&screenRect, &clipRect);
6308 RT_UNTRUSTED_VALIDATED_FENCE();
6309
6310 uint32_t const width = clipRect.right - clipRect.left;
6311 uint32_t const height = clipRect.bottom - clipRect.top;
6312
6313 if ( width == 0
6314 || height == 0)
6315 return; /* Nothing to do. */
6316
6317 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6318 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6319
6320 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6321 * Prepare parameters for vmsvgaR3GmrTransfer.
6322 */
6323 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6324
6325 /* Destination: host buffer which describes the screen 0 VRAM.
6326 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6327 */
6328 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6329 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6330 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6331 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6332 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6333 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6334 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6335 + cbScanline * clipRect.top;
6336 int32_t const cbHstPitch = cbScanline;
6337
6338 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6339 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6340 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6341 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6342 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6343
6344 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6345 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6346 gstPtr, offGst, cbGstPitch,
6347 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6348 AssertRC(rc);
6349 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6350}
6351
6352
6353/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6354void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6355{
6356 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6357
6358 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6359 /* Note! This can fetch 3d render results as well!! */
6360 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6361 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6362
6363 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6364 RT_UNTRUSTED_VALIDATED_FENCE();
6365
6366 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6367 AssertPtrReturnVoid(pScreen);
6368
6369 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6370 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6371
6372 /* Clip destRect to the screen dimensions. */
6373 SVGASignedRect screenRect;
6374 screenRect.left = 0;
6375 screenRect.top = 0;
6376 screenRect.right = pScreen->cWidth;
6377 screenRect.bottom = pScreen->cHeight;
6378 SVGASignedRect clipRect = pCmd->srcRect;
6379 vmsvgaR3ClipRect(&screenRect, &clipRect);
6380 RT_UNTRUSTED_VALIDATED_FENCE();
6381
6382 uint32_t const width = clipRect.right - clipRect.left;
6383 uint32_t const height = clipRect.bottom - clipRect.top;
6384
6385 if ( width == 0
6386 || height == 0)
6387 return; /* Nothing to do. */
6388
6389 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6390 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6391
6392 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6393 * Prepare parameters for vmsvgaR3GmrTransfer.
6394 */
6395 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6396
6397 /* Source: host buffer which describes the screen 0 VRAM.
6398 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6399 */
6400 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6401 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6402 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6403 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6404 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6405 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6406 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6407 + cbScanline * clipRect.top;
6408 int32_t const cbHstPitch = cbScanline;
6409
6410 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6411 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6412 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6413 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6414 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6415
6416 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6417 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6418 gstPtr, offGst, cbGstPitch,
6419 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6420 AssertRC(rc);
6421}
6422
6423
6424/* SVGA_CMD_ANNOTATION_FILL */
6425void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6426{
6427 RT_NOREF(pThis);
6428 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6429
6430 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6431 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6432
6433 pSvgaR3State->colorAnnotation = pCmd->color;
6434}
6435
6436
6437/* SVGA_CMD_ANNOTATION_COPY */
6438void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6439{
6440 RT_NOREF(pThis, pCmd);
6441 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6442
6443 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6444 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6445
6446 AssertFailed();
6447}
6448
6449
6450#ifdef VBOX_WITH_VMSVGA3D
6451/* SVGA_CMD_DEFINE_GMR2 */
6452void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6453{
6454 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6455
6456 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6457 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6458
6459 /* Validate current GMR id. */
6460 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6461 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6462 RT_UNTRUSTED_VALIDATED_FENCE();
6463
6464 if (!pCmd->numPages)
6465 {
6466 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6467 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6468 }
6469 else
6470 {
6471 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6472 if (pGMR->cMaxPages)
6473 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6474
6475 /* Not sure if we should always free the descriptor, but for simplicity
6476 we do so if the new size is smaller than the current. */
6477 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6478 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
6479 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6480
6481 pGMR->cMaxPages = pCmd->numPages;
6482 /* The rest is done by the REMAP_GMR2 command. */
6483 }
6484}
6485
6486
6487/* SVGA_CMD_REMAP_GMR2 */
6488void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6489{
6490 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6491
6492 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6493 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6494
6495 /* Validate current GMR id and size. */
6496 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6497 RT_UNTRUSTED_VALIDATED_FENCE();
6498 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6499 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6500 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6501 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6502
6503 if (pCmd->numPages == 0)
6504 return;
6505 RT_UNTRUSTED_VALIDATED_FENCE();
6506
6507 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6508 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6509
6510 /*
6511 * We flatten the existing descriptors into a page array, overwrite the
6512 * pages specified in this command and then recompress the descriptor.
6513 */
6514 /** @todo Optimize the GMR remap algorithm! */
6515
6516 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6517 uint64_t *paNewPage64 = NULL;
6518 if (pGMR->paDesc)
6519 {
6520 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6521
6522 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6523 AssertPtrReturnVoid(paNewPage64);
6524
6525 uint32_t idxPage = 0;
6526 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6527 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6528 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6529 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6530 RT_UNTRUSTED_VALIDATED_FENCE();
6531 }
6532
6533 /* Free the old GMR if present. */
6534 if (pGMR->paDesc)
6535 RTMemFree(pGMR->paDesc);
6536
6537 /* Allocate the maximum amount possible (everything non-continuous) */
6538 PVMSVGAGMRDESCRIPTOR paDescs;
6539 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6540 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6541
6542 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6543 {
6544 /** @todo */
6545 AssertFailed();
6546 pGMR->numDescriptors = 0;
6547 }
6548 else
6549 {
6550 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6551 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6552 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6553
6554 uint32_t cPages;
6555 if (paNewPage64)
6556 {
6557 /* Overwrite the old page array with the new page values. */
6558 if (fGCPhys64)
6559 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6560 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6561 else
6562 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6563 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6564
6565 /* Use the updated page array instead of the command data. */
6566 fGCPhys64 = true;
6567 paPages64 = paNewPage64;
6568 cPages = cNewTotalPages;
6569 }
6570 else
6571 cPages = pCmd->numPages;
6572
6573 /* The first page. */
6574 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6575 * applied to paNewPage64. */
6576 RTGCPHYS GCPhys;
6577 if (fGCPhys64)
6578 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6579 else
6580 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6581 paDescs[0].GCPhys = GCPhys;
6582 paDescs[0].numPages = 1;
6583
6584 /* Subsequent pages. */
6585 uint32_t iDescriptor = 0;
6586 for (uint32_t i = 1; i < cPages; i++)
6587 {
6588 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6589 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6590 else
6591 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6592
6593 /* Continuous physical memory? */
6594 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6595 {
6596 Assert(paDescs[iDescriptor].numPages);
6597 paDescs[iDescriptor].numPages++;
6598 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6599 }
6600 else
6601 {
6602 iDescriptor++;
6603 paDescs[iDescriptor].GCPhys = GCPhys;
6604 paDescs[iDescriptor].numPages = 1;
6605 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6606 }
6607 }
6608
6609 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6610 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6611 pGMR->numDescriptors = iDescriptor + 1;
6612 }
6613
6614 if (paNewPage64)
6615 RTMemFree(paNewPage64);
6616}
6617
6618
6619/**
6620 * Free the specified GMR
6621 *
6622 * @param pThisCC The VGA/VMSVGA state for ring-3.
6623 * @param idGMR GMR id
6624 */
6625void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6626{
6627 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6628
6629 /* Free the old descriptor if present. */
6630 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6631 if ( pGMR->numDescriptors
6632 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6633 {
6634# ifdef DEBUG_GMR_ACCESS
6635 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6636# endif
6637
6638 Assert(pGMR->paDesc);
6639 RTMemFree(pGMR->paDesc);
6640 pGMR->paDesc = NULL;
6641 pGMR->numDescriptors = 0;
6642 pGMR->cbTotal = 0;
6643 pGMR->cMaxPages = 0;
6644 }
6645 Assert(!pGMR->cMaxPages);
6646 Assert(!pGMR->cbTotal);
6647}
6648#endif /* VBOX_WITH_VMSVGA3D */
6649
6650
6651/**
6652 * Copy between a GMR and a host memory buffer.
6653 *
6654 * @returns VBox status code.
6655 * @param pThis The shared VGA/VMSVGA instance data.
6656 * @param pThisCC The VGA/VMSVGA state for ring-3.
6657 * @param enmTransferType Transfer type (read/write)
6658 * @param pbHstBuf Host buffer pointer (valid)
6659 * @param cbHstBuf Size of host buffer (valid)
6660 * @param offHst Host buffer offset of the first scanline
6661 * @param cbHstPitch Destination buffer pitch
6662 * @param gstPtr GMR description
6663 * @param offGst Guest buffer offset of the first scanline
6664 * @param cbGstPitch Guest buffer pitch
6665 * @param cbWidth Width in bytes to copy
6666 * @param cHeight Number of scanllines to copy
6667 */
6668int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6669 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6670 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6671 uint32_t cbWidth, uint32_t cHeight)
6672{
6673 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6674 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6675 int rc;
6676
6677 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6678 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6679 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6680 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6681 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6682
6683 PGMR pGMR;
6684 uint32_t cbGmr; /* The GMR size in bytes. */
6685 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6686 {
6687 pGMR = NULL;
6688 cbGmr = pThis->vram_size;
6689 }
6690 else
6691 {
6692 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6693 RT_UNTRUSTED_VALIDATED_FENCE();
6694 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6695 cbGmr = pGMR->cbTotal;
6696 }
6697
6698 /*
6699 * GMR
6700 */
6701 /* Calculate GMR offset of the data to be copied. */
6702 AssertMsgReturn(gstPtr.offset < cbGmr,
6703 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6704 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6705 VERR_INVALID_PARAMETER);
6706 RT_UNTRUSTED_VALIDATED_FENCE();
6707 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6708 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6709 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6710 VERR_INVALID_PARAMETER);
6711 RT_UNTRUSTED_VALIDATED_FENCE();
6712 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6713
6714 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6715 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6716 AssertMsgReturn(cbGmrScanline != 0,
6717 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6718 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6719 VERR_INVALID_PARAMETER);
6720 RT_UNTRUSTED_VALIDATED_FENCE();
6721 AssertMsgReturn(cbWidth <= cbGmrScanline,
6722 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6723 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6724 VERR_INVALID_PARAMETER);
6725 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6726 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6727 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6728 VERR_INVALID_PARAMETER);
6729 RT_UNTRUSTED_VALIDATED_FENCE();
6730
6731 /* How many bytes are available for the data in the GMR. */
6732 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6733
6734 /* How many scanlines would fit into the available data. */
6735 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6736 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6737 if (cbWidth <= cbGmrLastScanline)
6738 ++cGmrScanlines;
6739
6740 if (cHeight > cGmrScanlines)
6741 cHeight = cGmrScanlines;
6742
6743 AssertMsgReturn(cHeight > 0,
6744 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6745 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6746 VERR_INVALID_PARAMETER);
6747 RT_UNTRUSTED_VALIDATED_FENCE();
6748
6749 /*
6750 * Host buffer.
6751 */
6752 AssertMsgReturn(offHst < cbHstBuf,
6753 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6754 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6755 VERR_INVALID_PARAMETER);
6756
6757 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6758 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6759 AssertMsgReturn(cbHstScanline != 0,
6760 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6761 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6762 VERR_INVALID_PARAMETER);
6763 AssertMsgReturn(cbWidth <= cbHstScanline,
6764 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6765 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6766 VERR_INVALID_PARAMETER);
6767 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6768 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6769 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6770 VERR_INVALID_PARAMETER);
6771
6772 /* How many bytes are available for the data in the buffer. */
6773 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6774
6775 /* How many scanlines would fit into the available data. */
6776 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6777 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6778 if (cbWidth <= cbHstLastScanline)
6779 ++cHstScanlines;
6780
6781 if (cHeight > cHstScanlines)
6782 cHeight = cHstScanlines;
6783
6784 AssertMsgReturn(cHeight > 0,
6785 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6786 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6787 VERR_INVALID_PARAMETER);
6788
6789 uint8_t *pbHst = pbHstBuf + offHst;
6790
6791 /* Shortcut for the framebuffer. */
6792 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6793 {
6794 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6795
6796 uint8_t const *pbSrc;
6797 int32_t cbSrcPitch;
6798 uint8_t *pbDst;
6799 int32_t cbDstPitch;
6800
6801 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6802 {
6803 pbSrc = pbHst;
6804 cbSrcPitch = cbHstPitch;
6805 pbDst = pbGst;
6806 cbDstPitch = cbGstPitch;
6807 }
6808 else
6809 {
6810 pbSrc = pbGst;
6811 cbSrcPitch = cbGstPitch;
6812 pbDst = pbHst;
6813 cbDstPitch = cbHstPitch;
6814 }
6815
6816 if ( cbWidth == (uint32_t)cbGstPitch
6817 && cbGstPitch == cbHstPitch)
6818 {
6819 /* Entire scanlines, positive pitch. */
6820 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6821 }
6822 else
6823 {
6824 for (uint32_t i = 0; i < cHeight; ++i)
6825 {
6826 memcpy(pbDst, pbSrc, cbWidth);
6827
6828 pbDst += cbDstPitch;
6829 pbSrc += cbSrcPitch;
6830 }
6831 }
6832 return VINF_SUCCESS;
6833 }
6834
6835 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6836 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6837
6838 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6839 uint32_t iDesc = 0; /* Index in the descriptor array. */
6840 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6841 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6842 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6843 for (uint32_t i = 0; i < cHeight; ++i)
6844 {
6845 uint32_t cbCurrentWidth = cbWidth;
6846 uint32_t offGmrCurrent = offGmrScanline;
6847 uint8_t *pbCurrentHost = pbHstScanline;
6848
6849 /* Find the right descriptor */
6850 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6851 {
6852 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6853 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6854 ++iDesc;
6855 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6856 }
6857
6858 while (cbCurrentWidth)
6859 {
6860 uint32_t cbToCopy;
6861
6862 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6863 {
6864 cbToCopy = cbCurrentWidth;
6865 }
6866 else
6867 {
6868 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6869 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6870 }
6871
6872 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6873
6874 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6875
6876 /*
6877 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
6878 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
6879 * see @bugref{9654#c75}.
6880 */
6881 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6882 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6883 else
6884 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6885 AssertRCBreak(rc);
6886
6887 cbCurrentWidth -= cbToCopy;
6888 offGmrCurrent += cbToCopy;
6889 pbCurrentHost += cbToCopy;
6890
6891 /* Go to the next descriptor if there's anything left. */
6892 if (cbCurrentWidth)
6893 {
6894 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6895 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6896 ++iDesc;
6897 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6898 }
6899 }
6900
6901 offGmrScanline += cbGstPitch;
6902 pbHstScanline += cbHstPitch;
6903 }
6904
6905 return VINF_SUCCESS;
6906}
6907
6908
6909/**
6910 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6911 *
6912 * @param pSizeSrc Source surface dimensions.
6913 * @param pSizeDest Destination surface dimensions.
6914 * @param pBox Coordinates to be clipped.
6915 */
6916void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6917{
6918 /* Src x, w */
6919 if (pBox->srcx > pSizeSrc->width)
6920 pBox->srcx = pSizeSrc->width;
6921 if (pBox->w > pSizeSrc->width - pBox->srcx)
6922 pBox->w = pSizeSrc->width - pBox->srcx;
6923
6924 /* Src y, h */
6925 if (pBox->srcy > pSizeSrc->height)
6926 pBox->srcy = pSizeSrc->height;
6927 if (pBox->h > pSizeSrc->height - pBox->srcy)
6928 pBox->h = pSizeSrc->height - pBox->srcy;
6929
6930 /* Src z, d */
6931 if (pBox->srcz > pSizeSrc->depth)
6932 pBox->srcz = pSizeSrc->depth;
6933 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6934 pBox->d = pSizeSrc->depth - pBox->srcz;
6935
6936 /* Dest x, w */
6937 if (pBox->x > pSizeDest->width)
6938 pBox->x = pSizeDest->width;
6939 if (pBox->w > pSizeDest->width - pBox->x)
6940 pBox->w = pSizeDest->width - pBox->x;
6941
6942 /* Dest y, h */
6943 if (pBox->y > pSizeDest->height)
6944 pBox->y = pSizeDest->height;
6945 if (pBox->h > pSizeDest->height - pBox->y)
6946 pBox->h = pSizeDest->height - pBox->y;
6947
6948 /* Dest z, d */
6949 if (pBox->z > pSizeDest->depth)
6950 pBox->z = pSizeDest->depth;
6951 if (pBox->d > pSizeDest->depth - pBox->z)
6952 pBox->d = pSizeDest->depth - pBox->z;
6953}
6954
6955
6956/**
6957 * Unsigned coordinates in pBox. Clip to [0; pSize).
6958 *
6959 * @param pSize Source surface dimensions.
6960 * @param pBox Coordinates to be clipped.
6961 */
6962void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6963{
6964 /* x, w */
6965 if (pBox->x > pSize->width)
6966 pBox->x = pSize->width;
6967 if (pBox->w > pSize->width - pBox->x)
6968 pBox->w = pSize->width - pBox->x;
6969
6970 /* y, h */
6971 if (pBox->y > pSize->height)
6972 pBox->y = pSize->height;
6973 if (pBox->h > pSize->height - pBox->y)
6974 pBox->h = pSize->height - pBox->y;
6975
6976 /* z, d */
6977 if (pBox->z > pSize->depth)
6978 pBox->z = pSize->depth;
6979 if (pBox->d > pSize->depth - pBox->z)
6980 pBox->d = pSize->depth - pBox->z;
6981}
6982
6983
6984/**
6985 * Clip.
6986 *
6987 * @param pBound Bounding rectangle.
6988 * @param pRect Rectangle to be clipped.
6989 */
6990void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
6991{
6992 int32_t left;
6993 int32_t top;
6994 int32_t right;
6995 int32_t bottom;
6996
6997 /* Right order. */
6998 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
6999 if (pRect->left < pRect->right)
7000 {
7001 left = pRect->left;
7002 right = pRect->right;
7003 }
7004 else
7005 {
7006 left = pRect->right;
7007 right = pRect->left;
7008 }
7009 if (pRect->top < pRect->bottom)
7010 {
7011 top = pRect->top;
7012 bottom = pRect->bottom;
7013 }
7014 else
7015 {
7016 top = pRect->bottom;
7017 bottom = pRect->top;
7018 }
7019
7020 if (left < pBound->left)
7021 left = pBound->left;
7022 if (right < pBound->left)
7023 right = pBound->left;
7024
7025 if (left > pBound->right)
7026 left = pBound->right;
7027 if (right > pBound->right)
7028 right = pBound->right;
7029
7030 if (top < pBound->top)
7031 top = pBound->top;
7032 if (bottom < pBound->top)
7033 bottom = pBound->top;
7034
7035 if (top > pBound->bottom)
7036 top = pBound->bottom;
7037 if (bottom > pBound->bottom)
7038 bottom = pBound->bottom;
7039
7040 pRect->left = left;
7041 pRect->right = right;
7042 pRect->top = top;
7043 pRect->bottom = bottom;
7044}
7045
7046
7047/**
7048 * Clip.
7049 *
7050 * @param pBound Bounding rectangle.
7051 * @param pRect Rectangle to be clipped.
7052 */
7053void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7054{
7055 uint32_t const leftBound = pBound->x;
7056 uint32_t const rightBound = pBound->x + pBound->w;
7057 uint32_t const topBound = pBound->y;
7058 uint32_t const bottomBound = pBound->y + pBound->h;
7059
7060 uint32_t x = pRect->x;
7061 uint32_t y = pRect->y;
7062 uint32_t w = pRect->w;
7063 uint32_t h = pRect->h;
7064
7065 /* Make sure that right and bottom coordinates can be safely computed. */
7066 if (x > rightBound)
7067 x = rightBound;
7068 if (w > rightBound - x)
7069 w = rightBound - x;
7070 if (y > bottomBound)
7071 y = bottomBound;
7072 if (h > bottomBound - y)
7073 h = bottomBound - y;
7074
7075 /* Switch from x, y, w, h to left, top, right, bottom. */
7076 uint32_t left = x;
7077 uint32_t right = x + w;
7078 uint32_t top = y;
7079 uint32_t bottom = y + h;
7080
7081 /* A standard left, right, bottom, top clipping. */
7082 if (left < leftBound)
7083 left = leftBound;
7084 if (right < leftBound)
7085 right = leftBound;
7086
7087 if (left > rightBound)
7088 left = rightBound;
7089 if (right > rightBound)
7090 right = rightBound;
7091
7092 if (top < topBound)
7093 top = topBound;
7094 if (bottom < topBound)
7095 bottom = topBound;
7096
7097 if (top > bottomBound)
7098 top = bottomBound;
7099 if (bottom > bottomBound)
7100 bottom = bottomBound;
7101
7102 /* Back to x, y, w, h representation. */
7103 pRect->x = left;
7104 pRect->y = top;
7105 pRect->w = right - left;
7106 pRect->h = bottom - top;
7107}
7108
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