VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 93956

Last change on this file since 93956 was 93944, checked in by vboxsync, 3 years ago

Devices: Must not use PAGE_SIZE, PAGE_SHIFT, PAGE_OFFSET_MASK, PAGE_ADDRESS or PHYS_PAGE_ADDRESS here either. bugref:9898
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 271.7 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 93944 2022-02-24 21:15:14Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817/*
818 *
819 * The guest's Memory OBjects (MOB).
820 *
821 */
822
823static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
824 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
825 bool fGCPhys64, PVMSVGAMOB pMob)
826{
827 RT_ZERO(*pMob);
828
829 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
830 SVGAOTableMobEntry entry;
831 entry.ptDepth = ptDepth;
832 entry.sizeInBytes = sizeInBytes;
833 entry.base = baseAddress;
834 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
835 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
836 if (RT_SUCCESS(rc))
837 {
838 /* Create the corresponding GBO. */
839 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
840 if (RT_SUCCESS(rc))
841 {
842 /* Add to the tree of known GBOs and the LRU list. */
843 pMob->Core.Key = mobid;
844 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
845 {
846 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
847 return VINF_SUCCESS;
848 }
849
850 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
851 }
852 }
853
854 return rc;
855}
856
857
858static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
859{
860 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
861 SVGAOTableMobEntry entry;
862 RT_ZERO(entry);
863 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
864 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
865
866 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
867 if (pMob)
868 {
869 RTListNodeRemove(&pMob->nodeLRU);
870 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
871 RTMemFree(pMob);
872 return VINF_SUCCESS;
873 }
874
875 return VERR_INVALID_PARAMETER;
876}
877
878
879static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
880{
881 if (mobid == SVGA_ID_INVALID)
882 return NULL;
883
884 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
885 if (pMob)
886 {
887 /* Move to the head of the LRU list. */
888 RTListNodeRemove(&pMob->nodeLRU);
889 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
890 }
891 else
892 ASSERT_GUEST_FAILED();
893
894 return pMob;
895}
896
897
898/** Create a host ring-3 pointer to the MOB data.
899 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
900 * @param pSvgaR3State R3 device state.
901 * @param pMob The MOB.
902 * @param cbValid How many bytes of the guest backing memory contain valid data.
903 * @return VBox status.
904 */
905/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
906int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
907{
908 AssertReturn(pMob, VERR_INVALID_PARAMETER);
909 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
910}
911
912
913void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
914{
915 if (pMob)
916 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
917}
918
919
920int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
921{
922 if (pMob)
923 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
924 return VERR_INVALID_PARAMETER;
925}
926
927
928int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
929{
930 if (pMob)
931 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
932 return VERR_INVALID_PARAMETER;
933}
934
935
936void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
937{
938 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
939 {
940 if (off <= pMob->Gbo.cbTotal)
941 return (uint8_t *)pMob->Gbo.pvHost + off;
942 }
943 return NULL;
944}
945
946
947int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
948{
949 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
950
951 SVGAOTableSurfaceEntry entrySurface;
952 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
953 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
954 if (RT_SUCCESS(rc))
955 {
956 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
957 if (pMob)
958 {
959 VMSVGA3D_MAPPED_SURFACE map;
960 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE, &map);
961 if (RT_SUCCESS(rc))
962 {
963 /* Copy MOB -> mapped surface. */
964 uint32_t offSrc = pBox->x * map.cbPixel
965 + pBox->y * entrySurface.size.width * map.cbPixel
966 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
967 uint8_t *pu8Dst = (uint8_t *)map.pvData;
968 for (uint32_t z = 0; z < pBox->d; ++z)
969 {
970 for (uint32_t y = 0; y < pBox->h; ++y)
971 {
972 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
973 if (RT_FAILURE(rc))
974 break;
975
976 pu8Dst += map.cbRowPitch;
977 offSrc += entrySurface.size.width * map.cbPixel;
978 }
979
980 pu8Dst += map.cbDepthPitch;
981 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
982 }
983
984 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
985 }
986 }
987 else
988 rc = VERR_INVALID_STATE;
989 }
990
991 return rc;
992}
993
994
995int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
996{
997 /* pPtSrc must be verified by the caller. */
998 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
999
1000 SVGAOTableSurfaceEntry entrySurface;
1001 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1002 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1003 if (RT_SUCCESS(rc))
1004 {
1005 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1006 if (pMob)
1007 {
1008 VMSVGA3D_MAPPED_SURFACE map;
1009 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE, &map);
1010 if (RT_SUCCESS(rc))
1011 {
1012 /* Copy MOB -> mapped surface. */
1013 uint32_t offSrc = pPtSrc->x * map.cbPixel
1014 + pPtSrc->y * entrySurface.size.width * map.cbPixel
1015 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1016 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1017 for (uint32_t z = 0; z < pBoxDst->d; ++z)
1018 {
1019 for (uint32_t y = 0; y < pBoxDst->h; ++y)
1020 {
1021 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1022 if (RT_FAILURE(rc))
1023 break;
1024
1025 pu8Dst += map.cbRowPitch;
1026 offSrc += entrySurface.size.width * map.cbPixel;
1027 }
1028
1029 pu8Dst += map.cbDepthPitch;
1030 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1031 }
1032
1033 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1034 }
1035 }
1036 else
1037 rc = VERR_INVALID_STATE;
1038 }
1039
1040 return rc;
1041}
1042
1043#endif /* VBOX_WITH_VMSVGA3D */
1044
1045/*
1046 * Screen objects.
1047 */
1048VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1049{
1050 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1051 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1052 && pSVGAState
1053 && pSVGAState->aScreens[idScreen].fDefined)
1054 {
1055 return &pSVGAState->aScreens[idScreen];
1056 }
1057 return NULL;
1058}
1059
1060void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1061{
1062#ifdef VBOX_WITH_VMSVGA3D
1063 if (pThis->svga.f3DEnabled)
1064 {
1065 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1066 {
1067 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1068 if (pScreen)
1069 vmsvga3dDestroyScreen(pThisCC, pScreen);
1070 }
1071 }
1072#else
1073 RT_NOREF(pThis, pThisCC);
1074#endif
1075}
1076
1077
1078/**
1079 * Copy a rectangle of pixels within guest VRAM.
1080 */
1081static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1082 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1083{
1084 if (!width || !height)
1085 return; /* Nothing to do, don't even bother. */
1086
1087 /*
1088 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1089 * corresponding to the current display mode.
1090 */
1091 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1092 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1093 uint8_t const *pSrc;
1094 uint8_t *pDst;
1095 unsigned const cbRectWidth = width * cbPixel;
1096 unsigned uMaxOffset;
1097
1098 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1099 if (uMaxOffset >= cbFrameBuffer)
1100 {
1101 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1102 return; /* Just don't listen to a bad guest. */
1103 }
1104
1105 pSrc = pDst = pThisCC->pbVRam;
1106 pSrc += srcY * cbScanline + srcX * cbPixel;
1107 pDst += dstY * cbScanline + dstX * cbPixel;
1108
1109 if (srcY >= dstY)
1110 {
1111 /* Source below destination, copy top to bottom. */
1112 for (; height > 0; height--)
1113 {
1114 memmove(pDst, pSrc, cbRectWidth);
1115 pSrc += cbScanline;
1116 pDst += cbScanline;
1117 }
1118 }
1119 else
1120 {
1121 /* Source above destination, copy bottom to top. */
1122 pSrc += cbScanline * (height - 1);
1123 pDst += cbScanline * (height - 1);
1124 for (; height > 0; height--)
1125 {
1126 memmove(pDst, pSrc, cbRectWidth);
1127 pSrc -= cbScanline;
1128 pDst -= cbScanline;
1129 }
1130 }
1131}
1132
1133
1134/**
1135 * Common worker for changing the pointer shape.
1136 *
1137 * @param pThisCC The VGA/VMSVGA state for ring-3.
1138 * @param pSVGAState The VMSVGA ring-3 instance data.
1139 * @param fAlpha Whether there is alpha or not.
1140 * @param xHot Hotspot x coordinate.
1141 * @param yHot Hotspot y coordinate.
1142 * @param cx Width.
1143 * @param cy Height.
1144 * @param pbData Heap copy of the cursor data. Consumed.
1145 * @param cbData The size of the data.
1146 */
1147static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1148 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1149{
1150 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1151#ifdef LOG_ENABLED
1152 if (LogIs2Enabled())
1153 {
1154 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1155 if (!fAlpha)
1156 {
1157 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1158 for (uint32_t y = 0; y < cy; y++)
1159 {
1160 Log2(("%3u:", y));
1161 uint8_t const *pbLine = &pbData[y * cbAndLine];
1162 for (uint32_t x = 0; x < cx; x += 8)
1163 {
1164 uint8_t b = pbLine[x / 8];
1165 char szByte[12];
1166 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1167 szByte[1] = b & 0x40 ? '*' : ' ';
1168 szByte[2] = b & 0x20 ? '*' : ' ';
1169 szByte[3] = b & 0x10 ? '*' : ' ';
1170 szByte[4] = b & 0x08 ? '*' : ' ';
1171 szByte[5] = b & 0x04 ? '*' : ' ';
1172 szByte[6] = b & 0x02 ? '*' : ' ';
1173 szByte[7] = b & 0x01 ? '*' : ' ';
1174 szByte[8] = '\0';
1175 Log2(("%s", szByte));
1176 }
1177 Log2(("\n"));
1178 }
1179 }
1180
1181 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1182 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1183 for (uint32_t y = 0; y < cy; y++)
1184 {
1185 Log2(("%3u:", y));
1186 uint32_t const *pu32Line = &pu32Xor[y * cx];
1187 for (uint32_t x = 0; x < cx; x++)
1188 Log2((" %08x", pu32Line[x]));
1189 Log2(("\n"));
1190 }
1191 }
1192#endif
1193
1194 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1195 AssertRC(rc);
1196
1197 if (pSVGAState->Cursor.fActive)
1198 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1199
1200 pSVGAState->Cursor.fActive = true;
1201 pSVGAState->Cursor.xHotspot = xHot;
1202 pSVGAState->Cursor.yHotspot = yHot;
1203 pSVGAState->Cursor.width = cx;
1204 pSVGAState->Cursor.height = cy;
1205 pSVGAState->Cursor.cbData = cbData;
1206 pSVGAState->Cursor.pData = pbData;
1207}
1208
1209
1210#ifdef VBOX_WITH_VMSVGA3D
1211
1212/*
1213 * SVGA_3D_CMD_* handlers.
1214 */
1215
1216
1217/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1218 *
1219 * @param pThisCC The VGA/VMSVGA state for the current context.
1220 * @param pCmd The VMSVGA command.
1221 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1222 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1223 */
1224static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1225 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1226{
1227 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1228 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1229 RT_UNTRUSTED_VALIDATED_FENCE();
1230
1231 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1232 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1233 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1234 */
1235 uint32_t cRemainingMipLevels = cMipLevelSizes;
1236 uint32_t cFaces = 0;
1237 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1238 {
1239 if (pCmd->face[i].numMipLevels == 0)
1240 break;
1241
1242 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1243 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1244
1245 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1246 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1247 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1248
1249 ++cFaces;
1250 }
1251 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1252 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1253
1254 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1255 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1256
1257 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1258 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1259 RT_UNTRUSTED_VALIDATED_FENCE();
1260
1261 /* Verify paMipLevelSizes */
1262 uint32_t cWidth = paMipLevelSizes[0].width;
1263 uint32_t cHeight = paMipLevelSizes[0].height;
1264 uint32_t cDepth = paMipLevelSizes[0].depth;
1265 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1266 {
1267 cWidth >>= 1;
1268 if (cWidth == 0) cWidth = 1;
1269 cHeight >>= 1;
1270 if (cHeight == 0) cHeight = 1;
1271 cDepth >>= 1;
1272 if (cDepth == 0) cDepth = 1;
1273 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1274 {
1275 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1276 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1277 && cHeight == paMipLevelSizes[iMipLevelSize].height
1278 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1279 }
1280 }
1281 RT_UNTRUSTED_VALIDATED_FENCE();
1282
1283 /* Create the surface. */
1284 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1285 pCmd->multisampleCount, pCmd->autogenFilter,
1286 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* fAllocMipLevels = */ true);
1287}
1288
1289
1290/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1291static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1292{
1293 DEBUG_BREAKPOINT_TEST();
1294 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1295
1296 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1297
1298 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1299 /* Allocate a structure for the MOB. */
1300 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1301 AssertPtrReturnVoid(pMob);
1302
1303 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1304 if (RT_SUCCESS(rc))
1305 {
1306 return;
1307 }
1308
1309 AssertFailed();
1310
1311 RTMemFree(pMob);
1312}
1313
1314
1315/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1316static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1317{
1318 //DEBUG_BREAKPOINT_TEST();
1319 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1320
1321 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1322
1323 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1324 if (RT_SUCCESS(rc))
1325 {
1326 return;
1327 }
1328
1329 AssertFailed();
1330}
1331
1332
1333/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1334static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1335{
1336 //DEBUG_BREAKPOINT_TEST();
1337 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1338
1339 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1340 SVGAOTableSurfaceEntry entry;
1341 RT_ZERO(entry);
1342 entry.format = pCmd->format;
1343 entry.surface1Flags = pCmd->surfaceFlags;
1344 entry.numMipLevels = pCmd->numMipLevels;
1345 entry.multisampleCount = pCmd->multisampleCount;
1346 entry.autogenFilter = pCmd->autogenFilter;
1347 entry.size = pCmd->size;
1348 entry.mobid = SVGA_ID_INVALID;
1349 // entry.arraySize = 0;
1350 // entry.mobPitch = 0;
1351 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1352 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1353 if (RT_SUCCESS(rc))
1354 {
1355 /* Create the host surface. */
1356 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1357 pCmd->multisampleCount, pCmd->autogenFilter,
1358 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1359 }
1360}
1361
1362
1363/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1364static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1365{
1366 //DEBUG_BREAKPOINT_TEST();
1367 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1368
1369 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1370 SVGAOTableSurfaceEntry entry;
1371 RT_ZERO(entry);
1372 entry.mobid = SVGA_ID_INVALID;
1373 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1374 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1375
1376 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1377}
1378
1379
1380/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1381static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1382{
1383 //DEBUG_BREAKPOINT_TEST();
1384 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1385
1386 /* Assign the mobid to the surface. */
1387 int rc = VINF_SUCCESS;
1388 if (pCmd->mobid != SVGA_ID_INVALID)
1389 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1390 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1391 if (RT_SUCCESS(rc))
1392 {
1393 SVGAOTableSurfaceEntry entry;
1394 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1395 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1396 if (RT_SUCCESS(rc))
1397 {
1398 entry.mobid = pCmd->mobid;
1399 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1400 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1401 if (RT_SUCCESS(rc))
1402 {
1403 /* */
1404 }
1405 }
1406 }
1407}
1408
1409
1410static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1411{
1412 if (pMap->cbPixel != 4)
1413 return VERR_NOT_SUPPORTED;
1414
1415 int const w = pMap->box.w;
1416 int const h = pMap->box.h;
1417
1418 const int cbBitmap = w * h * 4;
1419
1420 FILE *f = fopen(pszFilename, "wb");
1421 if (!f)
1422 return VERR_FILE_NOT_FOUND;
1423
1424 {
1425 BMPFILEHDR fileHdr;
1426 RT_ZERO(fileHdr);
1427 fileHdr.uType = BMP_HDR_MAGIC;
1428 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1429 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1430
1431 BMPWIN3XINFOHDR coreHdr;
1432 RT_ZERO(coreHdr);
1433 coreHdr.cbSize = sizeof(coreHdr);
1434 coreHdr.uWidth = w;
1435 coreHdr.uHeight = -h;
1436 coreHdr.cPlanes = 1;
1437 coreHdr.cBits = 32;
1438 coreHdr.cbSizeImage = cbBitmap;
1439
1440 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1441 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1442 }
1443
1444 if (pMap->cbPixel == 4)
1445 {
1446 const uint8_t *s = (uint8_t *)pMap->pvData;
1447 for (int32_t y = 0; y < h; ++y)
1448 {
1449 fwrite(s, 1, w * pMap->cbPixel, f);
1450
1451 s += pMap->cbRowPitch;
1452 }
1453 }
1454
1455 fclose(f);
1456
1457 return VINF_SUCCESS;
1458}
1459
1460
1461void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1462{
1463 static int idxBitmap = 0;
1464 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1465 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1466 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1467 RTStrFree(pszFilename);
1468}
1469
1470
1471static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1472 PVMSVGAMOB pMob,
1473 SVGA3dSurfaceImageId const *pImage,
1474 SVGA3dBox const *pBox,
1475 SVGA3dTransferType enmTransfer)
1476{
1477 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1478
1479 VMSVGA3D_SURFACE_MAP enmMapType;
1480 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1481 enmMapType = pBox
1482 ? VMSVGA3D_SURFACE_MAP_WRITE
1483 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1484 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1485 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1486 else
1487 AssertFailedReturn(VERR_INVALID_PARAMETER);
1488
1489 VMSGA3D_BOX_DIMENSIONS dims;
1490 int rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1491 AssertRCReturn(rc, rc);
1492
1493 VMSVGA3D_MAPPED_SURFACE map;
1494 rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1495 if (RT_SUCCESS(rc))
1496 {
1497 /* Copy mapped surface <-> MOB. */
1498 uint8_t *pu8Map = (uint8_t *)map.pvData;
1499 uint32_t offMob = dims.offSubresource + dims.offBox;
1500 for (uint32_t z = 0; z < dims.cDepth; ++z)
1501 {
1502 for (uint32_t y = 0; y < dims.cyBlocks; ++y)
1503 {
1504 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1505 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1506 else
1507 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1508 if (RT_FAILURE(rc))
1509 break;
1510
1511 pu8Map += map.cbRowPitch;
1512 offMob += dims.cbPitch;
1513 }
1514 }
1515
1516 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1517
1518 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1519 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1520 }
1521
1522 return rc;
1523}
1524
1525
1526/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1527static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1528{
1529 //DEBUG_BREAKPOINT_TEST();
1530 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1531
1532 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1533 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1534
1535/*
1536 SVGA3dSurfaceFormat format;
1537 SVGA3dSurface1Flags surface1Flags;
1538 uint32 numMipLevels;
1539 uint32 multisampleCount;
1540 SVGA3dTextureFilter autogenFilter;
1541 SVGA3dSize size;
1542 SVGAMobId mobid;
1543 uint32 arraySize;
1544 uint32 mobPitch;
1545 SVGA3dSurface2Flags surface2Flags;
1546 uint8 multisamplePattern;
1547 uint8 qualityLevel;
1548 uint16 bufferByteStride;
1549 float minLOD;
1550*/
1551
1552 /* "update a surface from its backing MOB." */
1553 SVGAOTableSurfaceEntry entrySurface;
1554 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1555 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1556 if (RT_SUCCESS(rc))
1557 {
1558 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1559 if (pMob)
1560 {
1561 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1562 AssertRC(rc);
1563 }
1564 }
1565}
1566
1567
1568/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1569static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1570{
1571 //DEBUG_BREAKPOINT_TEST();
1572 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1573
1574 LogFlowFunc(("sid=%u\n",
1575 pCmd->sid));
1576
1577 /* "update a surface from its backing MOB." */
1578 SVGAOTableSurfaceEntry entrySurface;
1579 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1580 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1581 if (RT_SUCCESS(rc))
1582 {
1583 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1584 if (pMob)
1585 {
1586 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1587 ? SVGA3D_MAX_SURFACE_FACES
1588 : RT_MAX(entrySurface.arraySize, 1);
1589 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1590 {
1591 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1592 {
1593 SVGA3dSurfaceImageId image;
1594 image.sid = pCmd->sid;
1595 image.face = iArray;
1596 image.mipmap = iMipmap;
1597
1598 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1599 AssertRCBreak(rc);
1600 }
1601 }
1602 }
1603 }
1604}
1605
1606
1607/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1608static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1609{
1610 //DEBUG_BREAKPOINT_TEST();
1611 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1612
1613 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1614 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1615
1616 /* Read a surface to its backing MOB. */
1617 SVGAOTableSurfaceEntry entrySurface;
1618 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1619 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1620 if (RT_SUCCESS(rc))
1621 {
1622 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1623 if (pMob)
1624 {
1625 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1626 AssertRC(rc);
1627 }
1628 }
1629}
1630
1631
1632/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1633static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1634{
1635 //DEBUG_BREAKPOINT_TEST();
1636 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1637
1638 LogFlowFunc(("sid=%u\n",
1639 pCmd->sid));
1640
1641 /* Read a surface to its backing MOB. */
1642 SVGAOTableSurfaceEntry entrySurface;
1643 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1644 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1645 if (RT_SUCCESS(rc))
1646 {
1647 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1648 if (pMob)
1649 {
1650 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1651 ? SVGA3D_MAX_SURFACE_FACES
1652 : RT_MAX(entrySurface.arraySize, 1);
1653 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1654 {
1655 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1656 {
1657 SVGA3dSurfaceImageId image;
1658 image.sid = pCmd->sid;
1659 image.face = iArray;
1660 image.mipmap = iMipmap;
1661
1662 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1663 AssertRCBreak(rc);
1664 }
1665 }
1666 }
1667 }
1668}
1669
1670
1671/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1672static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1673{
1674 //DEBUG_BREAKPOINT_TEST();
1675 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1676}
1677
1678
1679/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1680static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1681{
1682 //DEBUG_BREAKPOINT_TEST();
1683 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1684}
1685
1686
1687/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1688static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1689{
1690 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1691
1692 /*
1693 * Create a GBO for the table.
1694 */
1695 PVMSVGAGBO pGbo;
1696 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1697 {
1698 RT_UNTRUSTED_VALIDATED_FENCE();
1699 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1700 }
1701 else
1702 {
1703 ASSERT_GUEST_FAILED();
1704 pGbo = NULL;
1705 }
1706
1707 if (pGbo)
1708 {
1709 /* Recreate. */
1710 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1711 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1712 AssertRC(rc);
1713 }
1714}
1715
1716
1717/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1718static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1719{
1720 //DEBUG_BREAKPOINT_TEST();
1721 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1722
1723 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1724 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1725 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1726 RT_UNTRUSTED_VALIDATED_FENCE();
1727
1728 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1729 SVGAOTableScreenTargetEntry entry;
1730 RT_ZERO(entry);
1731 entry.image.sid = SVGA_ID_INVALID;
1732 // entry.image.face = 0;
1733 // entry.image.mipmap = 0;
1734 entry.width = pCmd->width;
1735 entry.height = pCmd->height;
1736 entry.xRoot = pCmd->xRoot;
1737 entry.yRoot = pCmd->yRoot;
1738 entry.flags = pCmd->flags;
1739 entry.dpi = pCmd->dpi;
1740
1741 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1742 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1743 if (RT_SUCCESS(rc))
1744 {
1745 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1746 /** @todo Generic screen object/target interface. */
1747 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1748 pScreen->fDefined = true;
1749 pScreen->fModified = true;
1750 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1751 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1752 pScreen->idScreen = pCmd->stid;
1753
1754 pScreen->xOrigin = pCmd->xRoot;
1755 pScreen->yOrigin = pCmd->yRoot;
1756 pScreen->cWidth = pCmd->width;
1757 pScreen->cHeight = pCmd->height;
1758 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1759 pScreen->cbPitch = pCmd->width * 4;
1760 pScreen->cBpp = 32;
1761
1762 if (RT_LIKELY(pThis->svga.f3DEnabled))
1763 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1764
1765 if (!pScreen->pHwScreen)
1766 {
1767 /* System memory buffer. */
1768 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1769 }
1770
1771 pThis->svga.fGFBRegisters = false;
1772 vmsvgaR3ChangeMode(pThis, pThisCC);
1773 }
1774}
1775
1776
1777/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1778static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1779{
1780 //DEBUG_BREAKPOINT_TEST();
1781 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1782
1783 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1784 RT_UNTRUSTED_VALIDATED_FENCE();
1785
1786 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1787 SVGAOTableScreenTargetEntry entry;
1788 RT_ZERO(entry);
1789 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1790 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1791 if (RT_SUCCESS(rc))
1792 {
1793 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1794 /** @todo Generic screen object/target interface. */
1795 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1796 pScreen->fModified = true;
1797 pScreen->fDefined = false;
1798 pScreen->idScreen = pCmd->stid;
1799
1800 if (RT_LIKELY(pThis->svga.f3DEnabled))
1801 vmsvga3dDestroyScreen(pThisCC, pScreen);
1802
1803 vmsvgaR3ChangeMode(pThis, pThisCC);
1804
1805 RTMemFree(pScreen->pvScreenBitmap);
1806 pScreen->pvScreenBitmap = NULL;
1807 }
1808}
1809
1810
1811/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1812static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1813{
1814 //DEBUG_BREAKPOINT_TEST();
1815 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1816
1817 /* "Binding a surface to a Screen Target the same as flipping" */
1818
1819 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1820 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1821 RT_UNTRUSTED_VALIDATED_FENCE();
1822
1823 /* Assign the surface to the screen target. */
1824 int rc = VINF_SUCCESS;
1825 if (pCmd->image.sid != SVGA_ID_INVALID)
1826 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1827 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1828 if (RT_SUCCESS(rc))
1829 {
1830 SVGAOTableScreenTargetEntry entry;
1831 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1832 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1833 if (RT_SUCCESS(rc))
1834 {
1835 entry.image = pCmd->image;
1836 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1837 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1838 if (RT_SUCCESS(rc))
1839 {
1840 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1841 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1842 AssertRC(rc);
1843 }
1844 }
1845 }
1846}
1847
1848
1849/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1850static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1851{
1852 //DEBUG_BREAKPOINT_TEST();
1853 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1854
1855 /* Update the screen target from its backing surface. */
1856 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1857 RT_UNTRUSTED_VALIDATED_FENCE();
1858
1859 /* Get the screen target info. */
1860 SVGAOTableScreenTargetEntry entryScreenTarget;
1861 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1862 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1863 if (RT_SUCCESS(rc))
1864 {
1865 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1866 RT_UNTRUSTED_VALIDATED_FENCE();
1867
1868 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1869 {
1870 SVGAOTableSurfaceEntry entrySurface;
1871 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1872 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1873 if (RT_SUCCESS(rc))
1874 {
1875 /* Copy entrySurface.mobid content to the screen target. */
1876 if (entrySurface.mobid != SVGA_ID_INVALID)
1877 {
1878 RT_UNTRUSTED_VALIDATED_FENCE();
1879 SVGA3dRect targetRect = pCmd->rect;
1880
1881 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1882 if (pScreen->pHwScreen)
1883 {
1884 /* Copy the screen target surface to the backend's screen. */
1885 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1886 }
1887 else if (pScreen->pvScreenBitmap)
1888 {
1889 /* Copy the screen target surface to the memory buffer. */
1890 VMSVGA3D_MAPPED_SURFACE map;
1891 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1892 if (RT_SUCCESS(rc))
1893 {
1894 uint8_t const *pu8Src = (uint8_t *)map.pvData
1895 + targetRect.x * map.cbPixel
1896 + targetRect.y * map.cbRowPitch;
1897 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1898 + targetRect.x * map.cbPixel
1899 + targetRect.y * map.box.w * map.cbPixel;
1900 for (uint32_t y = 0; y < targetRect.h; ++y)
1901 {
1902 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1903
1904 pu8Src += map.cbRowPitch;
1905 pu8Dst += map.box.w * map.cbPixel;
1906 }
1907
1908 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1909
1910 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1911 }
1912 else
1913 AssertFailed();
1914 }
1915 }
1916 }
1917 }
1918 }
1919}
1920
1921
1922/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1923static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1924{
1925 //DEBUG_BREAKPOINT_TEST();
1926 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1927
1928 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1929 SVGAOTableSurfaceEntry entry;
1930 RT_ZERO(entry);
1931 entry.format = pCmd->format;
1932 entry.surface1Flags = pCmd->surfaceFlags;
1933 entry.numMipLevels = pCmd->numMipLevels;
1934 entry.multisampleCount = pCmd->multisampleCount;
1935 entry.autogenFilter = pCmd->autogenFilter;
1936 entry.size = pCmd->size;
1937 entry.mobid = SVGA_ID_INVALID;
1938 entry.arraySize = pCmd->arraySize;
1939 // entry.mobPitch = 0;
1940 // ...
1941Assert( pCmd->arraySize == 0
1942 || pCmd->arraySize == 1
1943 || (pCmd->arraySize == 6 && (pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP)));
1944 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1945 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1946 if (RT_SUCCESS(rc))
1947 {
1948 /* Create the host surface. */
1949 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1950 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1951 pCmd->multisampleCount, pCmd->autogenFilter,
1952 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1953 }
1954}
1955
1956
1957/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1958static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1959{
1960 //DEBUG_BREAKPOINT_TEST();
1961 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1962
1963 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1964
1965 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1966 /* Allocate a structure for the MOB. */
1967 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1968 AssertPtrReturnVoid(pMob);
1969
1970 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1971 if (RT_SUCCESS(rc))
1972 {
1973 return;
1974 }
1975
1976 RTMemFree(pMob);
1977}
1978
1979
1980/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1981static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1982{
1983#ifdef VMSVGA3D_DX
1984 //DEBUG_BREAKPOINT_TEST();
1985 RT_NOREF(cbCmd);
1986
1987 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1988
1989 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1990 SVGAOTableDXContextEntry entry;
1991 RT_ZERO(entry);
1992 entry.cid = pCmd->cid;
1993 entry.mobid = SVGA_ID_INVALID;
1994 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1995 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1996 if (RT_SUCCESS(rc))
1997 {
1998 /* Create the host context. */
1999 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2000 }
2001
2002 return rc;
2003#else
2004 RT_NOREF(pThisCC, pCmd, cbCmd);
2005 return VERR_NOT_SUPPORTED;
2006#endif
2007}
2008
2009
2010/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2011static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2012{
2013#ifdef VMSVGA3D_DX
2014 //DEBUG_BREAKPOINT_TEST();
2015 RT_NOREF(cbCmd);
2016
2017 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2018
2019 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2020 SVGAOTableDXContextEntry entry;
2021 RT_ZERO(entry);
2022 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2023 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2024
2025 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2026#else
2027 RT_NOREF(pThisCC, pCmd, cbCmd);
2028 return VERR_NOT_SUPPORTED;
2029#endif
2030}
2031
2032
2033/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2034static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2035{
2036#ifdef VMSVGA3D_DX
2037 //DEBUG_BREAKPOINT_TEST();
2038 RT_NOREF(cbCmd);
2039
2040 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2041
2042 /* Assign a mobid to a cid. */
2043 int rc = VINF_SUCCESS;
2044 if (pCmd->mobid != SVGA_ID_INVALID)
2045 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2046 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2047 if (RT_SUCCESS(rc))
2048 {
2049 SVGAOTableDXContextEntry entry;
2050 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2051 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2052 if (RT_SUCCESS(rc))
2053 {
2054 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2055 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2056 {
2057 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2058 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2059 if (pSvgaDXContext)
2060 {
2061 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2062 if (RT_SUCCESS(rc))
2063 {
2064 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2065 if (pMob)
2066 {
2067 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2068 }
2069 }
2070
2071 RTMemFree(pSvgaDXContext);
2072 pSvgaDXContext = NULL;
2073 }
2074 }
2075
2076 if (pCmd->mobid != SVGA_ID_INVALID)
2077 {
2078 /* Bind a new context. Copy existing data from the guest backing memory. */
2079 if (pCmd->validContents)
2080 {
2081 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2082 if (pMob)
2083 {
2084 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2085 if (pSvgaDXContext)
2086 {
2087 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2088 if (RT_FAILURE(rc))
2089 {
2090 RTMemFree(pSvgaDXContext);
2091 pSvgaDXContext = NULL;
2092 }
2093 }
2094 }
2095 }
2096
2097 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2098
2099 RTMemFree(pSvgaDXContext);
2100 }
2101
2102 /* Update the object table. */
2103 entry.mobid = pCmd->mobid;
2104 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2105 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2106 }
2107 }
2108
2109 return rc;
2110#else
2111 RT_NOREF(pThisCC, pCmd, cbCmd);
2112 return VERR_NOT_SUPPORTED;
2113#endif
2114}
2115
2116
2117/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2118static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2119{
2120#ifdef VMSVGA3D_DX
2121 //DEBUG_BREAKPOINT_TEST();
2122 RT_NOREF(cbCmd);
2123
2124 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2125
2126 /* "Request that the device flush the contents back into guest memory." */
2127 SVGAOTableDXContextEntry entry;
2128 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2129 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2130 if (RT_SUCCESS(rc))
2131 {
2132 if (entry.mobid != SVGA_ID_INVALID)
2133 {
2134 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2135 if (pMob)
2136 {
2137 /* Get the content. */
2138 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2139 if (pSvgaDXContext)
2140 {
2141 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2142 if (RT_SUCCESS(rc))
2143 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2144
2145 RTMemFree(pSvgaDXContext);
2146 }
2147 else
2148 rc = VERR_NO_MEMORY;
2149 }
2150 }
2151 }
2152
2153 return rc;
2154#else
2155 RT_NOREF(pThisCC, pCmd, cbCmd);
2156 return VERR_NOT_SUPPORTED;
2157#endif
2158}
2159
2160
2161/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2162static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2163{
2164#ifdef VMSVGA3D_DX
2165 DEBUG_BREAKPOINT_TEST();
2166 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2167 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2168 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2169#else
2170 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2171 return VERR_NOT_SUPPORTED;
2172#endif
2173}
2174
2175
2176/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2177static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2178{
2179#ifdef VMSVGA3D_DX
2180 //DEBUG_BREAKPOINT_TEST();
2181 RT_NOREF(cbCmd);
2182 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2183#else
2184 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2185 return VERR_NOT_SUPPORTED;
2186#endif
2187}
2188
2189
2190/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2191static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2192{
2193#ifdef VMSVGA3D_DX
2194 //DEBUG_BREAKPOINT_TEST();
2195 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2196 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2197 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2198#else
2199 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2200 return VERR_NOT_SUPPORTED;
2201#endif
2202}
2203
2204
2205/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2206static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2207{
2208#ifdef VMSVGA3D_DX
2209 //DEBUG_BREAKPOINT_TEST();
2210 RT_NOREF(cbCmd);
2211 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2212#else
2213 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2214 return VERR_NOT_SUPPORTED;
2215#endif
2216}
2217
2218
2219/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2220static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2221{
2222#ifdef VMSVGA3D_DX
2223 //DEBUG_BREAKPOINT_TEST();
2224 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2225 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2226 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2227#else
2228 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2229 return VERR_NOT_SUPPORTED;
2230#endif
2231}
2232
2233
2234/* SVGA_3D_CMD_DX_DRAW 1152 */
2235static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2236{
2237#ifdef VMSVGA3D_DX
2238 //DEBUG_BREAKPOINT_TEST();
2239 RT_NOREF(cbCmd);
2240 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2241#else
2242 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2243 return VERR_NOT_SUPPORTED;
2244#endif
2245}
2246
2247
2248/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2249static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2250{
2251#ifdef VMSVGA3D_DX
2252 //DEBUG_BREAKPOINT_TEST();
2253 RT_NOREF(cbCmd);
2254 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2255#else
2256 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2257 return VERR_NOT_SUPPORTED;
2258#endif
2259}
2260
2261
2262/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2263static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2264{
2265#ifdef VMSVGA3D_DX
2266 //DEBUG_BREAKPOINT_TEST();
2267 RT_NOREF(cbCmd);
2268 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2269#else
2270 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2271 return VERR_NOT_SUPPORTED;
2272#endif
2273}
2274
2275
2276/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2277static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2278{
2279#ifdef VMSVGA3D_DX
2280 //DEBUG_BREAKPOINT_TEST();
2281 RT_NOREF(cbCmd);
2282 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2283#else
2284 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2285 return VERR_NOT_SUPPORTED;
2286#endif
2287}
2288
2289
2290/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2291static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2292{
2293#ifdef VMSVGA3D_DX
2294 DEBUG_BREAKPOINT_TEST();
2295 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2296 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2297 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2298#else
2299 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2300 return VERR_NOT_SUPPORTED;
2301#endif
2302}
2303
2304
2305/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2306static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2307{
2308#ifdef VMSVGA3D_DX
2309 //DEBUG_BREAKPOINT_TEST();
2310 RT_NOREF(cbCmd);
2311 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2312#else
2313 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2314 return VERR_NOT_SUPPORTED;
2315#endif
2316}
2317
2318
2319/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2320static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2321{
2322#ifdef VMSVGA3D_DX
2323 //DEBUG_BREAKPOINT_TEST();
2324 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2325 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2326 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2327#else
2328 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2329 return VERR_NOT_SUPPORTED;
2330#endif
2331}
2332
2333
2334/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2335static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2336{
2337#ifdef VMSVGA3D_DX
2338 //DEBUG_BREAKPOINT_TEST();
2339 RT_NOREF(cbCmd);
2340 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2341#else
2342 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2343 return VERR_NOT_SUPPORTED;
2344#endif
2345}
2346
2347
2348/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2349static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2350{
2351#ifdef VMSVGA3D_DX
2352 //DEBUG_BREAKPOINT_TEST();
2353 RT_NOREF(cbCmd);
2354 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2355#else
2356 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2357 return VERR_NOT_SUPPORTED;
2358#endif
2359}
2360
2361
2362/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2363static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2364{
2365#ifdef VMSVGA3D_DX
2366 //DEBUG_BREAKPOINT_TEST();
2367 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2368 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2369 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2370#else
2371 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2372 return VERR_NOT_SUPPORTED;
2373#endif
2374}
2375
2376
2377/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2378static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2379{
2380#ifdef VMSVGA3D_DX
2381 //DEBUG_BREAKPOINT_TEST();
2382 RT_NOREF(cbCmd);
2383 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2384#else
2385 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2386 return VERR_NOT_SUPPORTED;
2387#endif
2388}
2389
2390
2391/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2392static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2393{
2394#ifdef VMSVGA3D_DX
2395 //DEBUG_BREAKPOINT_TEST();
2396 RT_NOREF(cbCmd);
2397 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2398#else
2399 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2400 return VERR_NOT_SUPPORTED;
2401#endif
2402}
2403
2404
2405/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2406static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2407{
2408#ifdef VMSVGA3D_DX
2409 //DEBUG_BREAKPOINT_TEST();
2410 RT_NOREF(cbCmd);
2411 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2412#else
2413 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2414 return VERR_NOT_SUPPORTED;
2415#endif
2416}
2417
2418
2419/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2420static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2421{
2422#ifdef VMSVGA3D_DX
2423 DEBUG_BREAKPOINT_TEST();
2424 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2425 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2426 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2427#else
2428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2429 return VERR_NOT_SUPPORTED;
2430#endif
2431}
2432
2433
2434/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2435static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2436{
2437#ifdef VMSVGA3D_DX
2438 DEBUG_BREAKPOINT_TEST();
2439 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2440 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2441 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2442#else
2443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2444 return VERR_NOT_SUPPORTED;
2445#endif
2446}
2447
2448
2449/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2450static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2451{
2452#ifdef VMSVGA3D_DX
2453 DEBUG_BREAKPOINT_TEST();
2454 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2455 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2456 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2457#else
2458 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2459 return VERR_NOT_SUPPORTED;
2460#endif
2461}
2462
2463
2464/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2465static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2466{
2467#ifdef VMSVGA3D_DX
2468 DEBUG_BREAKPOINT_TEST();
2469 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2470 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2471 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2472#else
2473 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2474 return VERR_NOT_SUPPORTED;
2475#endif
2476}
2477
2478
2479/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2480static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2481{
2482#ifdef VMSVGA3D_DX
2483 DEBUG_BREAKPOINT_TEST();
2484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2485 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2486 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2487#else
2488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2489 return VERR_NOT_SUPPORTED;
2490#endif
2491}
2492
2493
2494/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2495static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2496{
2497#ifdef VMSVGA3D_DX
2498 DEBUG_BREAKPOINT_TEST();
2499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2500 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2501 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2502#else
2503 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2504 return VERR_NOT_SUPPORTED;
2505#endif
2506}
2507
2508
2509/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2510static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2511{
2512#ifdef VMSVGA3D_DX
2513 DEBUG_BREAKPOINT_TEST();
2514 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2515 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2516 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2517#else
2518 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2519 return VERR_NOT_SUPPORTED;
2520#endif
2521}
2522
2523
2524/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2525static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2526{
2527#ifdef VMSVGA3D_DX
2528 DEBUG_BREAKPOINT_TEST();
2529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2530 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2531 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2532#else
2533 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2534 return VERR_NOT_SUPPORTED;
2535#endif
2536}
2537
2538
2539/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2540static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2541{
2542#ifdef VMSVGA3D_DX
2543 //DEBUG_BREAKPOINT_TEST();
2544 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2545 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2546 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2547#else
2548 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2549 return VERR_NOT_SUPPORTED;
2550#endif
2551}
2552
2553
2554/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2555static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2556{
2557#ifdef VMSVGA3D_DX
2558 //DEBUG_BREAKPOINT_TEST();
2559 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2560 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2561 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2562#else
2563 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2564 return VERR_NOT_SUPPORTED;
2565#endif
2566}
2567
2568
2569/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2570static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2571{
2572#ifdef VMSVGA3D_DX
2573 //DEBUG_BREAKPOINT_TEST();
2574 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2575 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2576 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2577#else
2578 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2579 return VERR_NOT_SUPPORTED;
2580#endif
2581}
2582
2583
2584/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2585static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2586{
2587#ifdef VMSVGA3D_DX
2588 //DEBUG_BREAKPOINT_TEST();
2589 RT_NOREF(cbCmd);
2590 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2591#else
2592 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2593 return VERR_NOT_SUPPORTED;
2594#endif
2595}
2596
2597
2598/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2599static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2600{
2601#ifdef VMSVGA3D_DX
2602 //DEBUG_BREAKPOINT_TEST();
2603 RT_NOREF(cbCmd);
2604 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2605#else
2606 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2607 return VERR_NOT_SUPPORTED;
2608#endif
2609}
2610
2611
2612/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2613static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2614{
2615#ifdef VMSVGA3D_DX
2616 //DEBUG_BREAKPOINT_TEST();
2617 RT_NOREF(cbCmd);
2618 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2619#else
2620 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2621 return VERR_NOT_SUPPORTED;
2622#endif
2623}
2624
2625
2626/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2627static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2628{
2629#ifdef VMSVGA3D_DX
2630 DEBUG_BREAKPOINT_TEST();
2631 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2632 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2633 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2634#else
2635 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2636 return VERR_NOT_SUPPORTED;
2637#endif
2638}
2639
2640
2641/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2642static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2643{
2644#ifdef VMSVGA3D_DX
2645 DEBUG_BREAKPOINT_TEST();
2646 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2647 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2648 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2649#else
2650 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2651 return VERR_NOT_SUPPORTED;
2652#endif
2653}
2654
2655
2656/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2657static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2658{
2659#ifdef VMSVGA3D_DX
2660 //DEBUG_BREAKPOINT_TEST();
2661 RT_NOREF(cbCmd);
2662 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2663#else
2664 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2665 return VERR_NOT_SUPPORTED;
2666#endif
2667}
2668
2669
2670/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2671static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2672{
2673#ifdef VMSVGA3D_DX
2674 //DEBUG_BREAKPOINT_TEST();
2675 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2676 RT_NOREF(cbCmd);
2677
2678 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2679 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2680
2681 /* "Inform the device that the guest-contents have been updated." */
2682 SVGAOTableSurfaceEntry entrySurface;
2683 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2684 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2685 if (RT_SUCCESS(rc))
2686 {
2687 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2688 if (pMob)
2689 {
2690 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2691 ? SVGA3D_MAX_SURFACE_FACES
2692 : RT_MAX(entrySurface.arraySize, 1);
2693 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2694 /* pCmd->box will be verified by the mapping function. */
2695 RT_UNTRUSTED_VALIDATED_FENCE();
2696
2697 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2698 SVGA3dSurfaceImageId image;
2699 image.sid = pCmd->sid;
2700 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2701
2702 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2703 AssertRC(rc);
2704 }
2705 }
2706
2707 return rc;
2708#else
2709 RT_NOREF(pThisCC, pCmd, cbCmd);
2710 return VERR_NOT_SUPPORTED;
2711#endif
2712}
2713
2714
2715/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2716static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2717{
2718#ifdef VMSVGA3D_DX
2719 //DEBUG_BREAKPOINT_TEST();
2720 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2721 RT_NOREF(cbCmd);
2722
2723 LogFlowFunc(("sid=%u, subResource=%u\n",
2724 pCmd->sid, pCmd->subResource));
2725
2726 /* "Request the device to flush the dirty contents into the guest." */
2727 SVGAOTableSurfaceEntry entrySurface;
2728 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2729 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2730 if (RT_SUCCESS(rc))
2731 {
2732 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2733 if (pMob)
2734 {
2735 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2736 ? SVGA3D_MAX_SURFACE_FACES
2737 : RT_MAX(entrySurface.arraySize, 1);
2738 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2739 RT_UNTRUSTED_VALIDATED_FENCE();
2740
2741 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2742 SVGA3dSurfaceImageId image;
2743 image.sid = pCmd->sid;
2744 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2745
2746 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2747 AssertRC(rc);
2748 }
2749 }
2750
2751 return rc;
2752#else
2753 RT_NOREF(pThisCC, pCmd, cbCmd);
2754 return VERR_NOT_SUPPORTED;
2755#endif
2756}
2757
2758
2759/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2760static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2761{
2762#ifdef VMSVGA3D_DX
2763 DEBUG_BREAKPOINT_TEST();
2764 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2765 RT_NOREF(cbCmd);
2766
2767 LogFlowFunc(("sid=%u, subResource=%u\n",
2768 pCmd->sid, pCmd->subResource));
2769
2770 /* "Notify the device that the contents can be lost." */
2771 SVGAOTableSurfaceEntry entrySurface;
2772 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2773 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2774 if (RT_SUCCESS(rc))
2775 {
2776 uint32_t iFace;
2777 uint32_t iMipmap;
2778 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2779 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2780 }
2781
2782 return rc;
2783#else
2784 RT_NOREF(pThisCC, pCmd, cbCmd);
2785 return VERR_NOT_SUPPORTED;
2786#endif
2787}
2788
2789
2790/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2791static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2792{
2793#ifdef VMSVGA3D_DX
2794 //DEBUG_BREAKPOINT_TEST();
2795 RT_NOREF(cbCmd);
2796 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2797#else
2798 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2799 return VERR_NOT_SUPPORTED;
2800#endif
2801}
2802
2803
2804/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2805static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2806{
2807#ifdef VMSVGA3D_DX
2808 //DEBUG_BREAKPOINT_TEST();
2809 RT_NOREF(cbCmd);
2810 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2811#else
2812 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2813 return VERR_NOT_SUPPORTED;
2814#endif
2815}
2816
2817
2818/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2819static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2820{
2821#ifdef VMSVGA3D_DX
2822 //DEBUG_BREAKPOINT_TEST();
2823 RT_NOREF(cbCmd);
2824 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2825#else
2826 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2827 return VERR_NOT_SUPPORTED;
2828#endif
2829}
2830
2831
2832/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2833static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2834{
2835#ifdef VMSVGA3D_DX
2836 //DEBUG_BREAKPOINT_TEST();
2837 RT_NOREF(cbCmd);
2838 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2839#else
2840 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2841 return VERR_NOT_SUPPORTED;
2842#endif
2843}
2844
2845
2846/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2847static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2848{
2849#ifdef VMSVGA3D_DX
2850 //DEBUG_BREAKPOINT_TEST();
2851 RT_NOREF(cbCmd);
2852 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2853 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2854 cmd.sid = pCmd->sid;
2855 cmd.format = pCmd->format;
2856 cmd.resourceDimension = pCmd->resourceDimension;
2857 cmd.mipSlice = pCmd->mipSlice;
2858 cmd.firstArraySlice = pCmd->firstArraySlice;
2859 cmd.arraySize = pCmd->arraySize;
2860 cmd.flags = 0;
2861 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2862#else
2863 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2864 return VERR_NOT_SUPPORTED;
2865#endif
2866}
2867
2868
2869/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2870static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2871{
2872#ifdef VMSVGA3D_DX
2873 //DEBUG_BREAKPOINT_TEST();
2874 RT_NOREF(cbCmd);
2875 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2876#else
2877 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2878 return VERR_NOT_SUPPORTED;
2879#endif
2880}
2881
2882
2883/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2884static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2885{
2886#ifdef VMSVGA3D_DX
2887 //DEBUG_BREAKPOINT_TEST();
2888 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2889 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2890 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2891#else
2892 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2893 return VERR_NOT_SUPPORTED;
2894#endif
2895}
2896
2897
2898/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2899static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2900{
2901#ifdef VMSVGA3D_DX
2902 DEBUG_BREAKPOINT_TEST();
2903 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2904 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2905 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2906#else
2907 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2908 return VERR_NOT_SUPPORTED;
2909#endif
2910}
2911
2912
2913/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2914static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2915{
2916#ifdef VMSVGA3D_DX
2917 //DEBUG_BREAKPOINT_TEST();
2918 RT_NOREF(cbCmd);
2919 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2920#else
2921 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2922 return VERR_NOT_SUPPORTED;
2923#endif
2924}
2925
2926
2927/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2928static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2929{
2930#ifdef VMSVGA3D_DX
2931 DEBUG_BREAKPOINT_TEST();
2932 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2933 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2934 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2935#else
2936 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2937 return VERR_NOT_SUPPORTED;
2938#endif
2939}
2940
2941
2942/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2943static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2944{
2945#ifdef VMSVGA3D_DX
2946 //DEBUG_BREAKPOINT_TEST();
2947 RT_NOREF(cbCmd);
2948 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2949#else
2950 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2951 return VERR_NOT_SUPPORTED;
2952#endif
2953}
2954
2955
2956/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2957static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2958{
2959#ifdef VMSVGA3D_DX
2960 DEBUG_BREAKPOINT_TEST();
2961 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2962 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2963 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2964#else
2965 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2966 return VERR_NOT_SUPPORTED;
2967#endif
2968}
2969
2970
2971/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2972static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2973{
2974#ifdef VMSVGA3D_DX
2975 //DEBUG_BREAKPOINT_TEST();
2976 RT_NOREF(cbCmd);
2977 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2978#else
2979 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2980 return VERR_NOT_SUPPORTED;
2981#endif
2982}
2983
2984
2985/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2986static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2987{
2988#ifdef VMSVGA3D_DX
2989 DEBUG_BREAKPOINT_TEST();
2990 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2991 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2992 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2993#else
2994 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2995 return VERR_NOT_SUPPORTED;
2996#endif
2997}
2998
2999
3000/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3001static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3002{
3003#ifdef VMSVGA3D_DX
3004 //DEBUG_BREAKPOINT_TEST();
3005 RT_NOREF(cbCmd);
3006 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3007#else
3008 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3009 return VERR_NOT_SUPPORTED;
3010#endif
3011}
3012
3013
3014/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3015static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3016{
3017#ifdef VMSVGA3D_DX
3018 DEBUG_BREAKPOINT_TEST();
3019 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3020 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3021 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
3022#else
3023 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3024 return VERR_NOT_SUPPORTED;
3025#endif
3026}
3027
3028
3029/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3030static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3031{
3032#ifdef VMSVGA3D_DX
3033 //DEBUG_BREAKPOINT_TEST();
3034 RT_NOREF(cbCmd);
3035 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3036#else
3037 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3038 return VERR_NOT_SUPPORTED;
3039#endif
3040}
3041
3042
3043/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3044static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3045{
3046#ifdef VMSVGA3D_DX
3047 //DEBUG_BREAKPOINT_TEST();
3048 RT_NOREF(cbCmd);
3049 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3050#else
3051 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3052 return VERR_NOT_SUPPORTED;
3053#endif
3054}
3055
3056
3057/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3058static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3059{
3060#ifdef VMSVGA3D_DX
3061 //DEBUG_BREAKPOINT_TEST();
3062 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3063 RT_NOREF(idDXContext, cbCmd);
3064 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3065 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3066 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3067#else
3068 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3069 return VERR_NOT_SUPPORTED;
3070#endif
3071}
3072
3073
3074/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3075static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3076{
3077#ifdef VMSVGA3D_DX
3078 //DEBUG_BREAKPOINT_TEST();
3079 RT_NOREF(cbCmd);
3080 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3081#else
3082 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3083 return VERR_NOT_SUPPORTED;
3084#endif
3085}
3086
3087
3088/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3089static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3090{
3091#ifdef VMSVGA3D_DX
3092 DEBUG_BREAKPOINT_TEST();
3093 RT_NOREF(cbCmd);
3094 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3095#else
3096 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3097 return VERR_NOT_SUPPORTED;
3098#endif
3099}
3100
3101
3102/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3103static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3104{
3105#ifdef VMSVGA3D_DX
3106 //DEBUG_BREAKPOINT_TEST();
3107 RT_NOREF(cbCmd);
3108 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3109#else
3110 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3111 return VERR_NOT_SUPPORTED;
3112#endif
3113}
3114
3115
3116/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3117static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3118{
3119#ifdef VMSVGA3D_DX
3120 //DEBUG_BREAKPOINT_TEST();
3121 RT_NOREF(cbCmd);
3122 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3123 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3124 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3125 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3126#else
3127 RT_NOREF(pThisCC, pCmd, cbCmd);
3128 return VERR_NOT_SUPPORTED;
3129#endif
3130}
3131
3132
3133/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3134static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3135{
3136#ifdef VMSVGA3D_DX
3137 //DEBUG_BREAKPOINT_TEST();
3138 RT_NOREF(idDXContext, cbCmd);
3139 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3140#else
3141 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3142 return VERR_NOT_SUPPORTED;
3143#endif
3144}
3145
3146
3147/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3148static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3149{
3150#ifdef VMSVGA3D_DX
3151 DEBUG_BREAKPOINT_TEST();
3152 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3153 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3154 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
3155#else
3156 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3157 return VERR_NOT_SUPPORTED;
3158#endif
3159}
3160
3161
3162/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3163static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3164{
3165#ifdef VMSVGA3D_DX
3166 //DEBUG_BREAKPOINT_TEST();
3167 RT_NOREF(cbCmd);
3168
3169 /* Plan:
3170 * - map the buffer;
3171 * - map the surface;
3172 * - copy from buffer map to the surface map.
3173 */
3174
3175 int rc;
3176
3177 SVGA3dSurfaceImageId imageBuffer;
3178 imageBuffer.sid = pCmd->srcSid;
3179 imageBuffer.face = 0;
3180 imageBuffer.mipmap = 0;
3181
3182 SVGA3dSurfaceImageId imageSurface;
3183 imageSurface.sid = pCmd->destSid;
3184 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3185 AssertRCReturn(rc, rc);
3186
3187 /*
3188 * Map the buffer.
3189 */
3190 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3191 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3192 if (RT_SUCCESS(rc))
3193 {
3194 /*
3195 * Map the surface.
3196 */
3197 VMSVGA3D_MAPPED_SURFACE mapSurface;
3198 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3199 if (RT_SUCCESS(rc))
3200 {
3201 /*
3202 * Copy the mapped buffer to the surface.
3203 */
3204 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3205 uint32_t const cbBuffer = mapBuffer.box.w * mapBuffer.cbPixel;
3206
3207 if (pCmd->srcOffset <= cbBuffer)
3208 {
3209 RT_UNTRUSTED_VALIDATED_FENCE();
3210 uint8_t const *pu8BufferBegin = pu8Buffer;
3211 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3212
3213 pu8Buffer += pCmd->srcOffset;
3214
3215 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3216
3217 uint32_t const cbWidth = mapSurface.box.w * mapSurface.cbPixel;
3218 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3219 {
3220 uint8_t const *pu8BufferRow = pu8Buffer;
3221 uint8_t *pu8SurfaceRow = pu8Surface;
3222 for (uint32_t y = 0; y < mapSurface.box.h; ++y)
3223 {
3224 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3225 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3226 && (uintptr_t)(pu8BufferRow + cbWidth) > (uintptr_t)pu8BufferBegin
3227 && (uintptr_t)(pu8BufferRow + cbWidth) <= (uintptr_t)pu8BufferEnd,
3228 rc = VERR_INVALID_PARAMETER);
3229
3230 memcpy(pu8SurfaceRow, pu8BufferRow, cbWidth);
3231
3232 pu8SurfaceRow += mapSurface.cbRowPitch;
3233 pu8BufferRow += pCmd->srcPitch;
3234 }
3235
3236 pu8Buffer += pCmd->srcSlicePitch;
3237 pu8Surface += mapSurface.cbDepthPitch;
3238 }
3239 }
3240 else
3241 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3242
3243 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3244 }
3245
3246 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3247 }
3248
3249 return rc;
3250#else
3251 RT_NOREF(pThisCC, pCmd, cbCmd);
3252 return VERR_NOT_SUPPORTED;
3253#endif
3254}
3255
3256
3257/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3258static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3259{
3260#ifdef VMSVGA3D_DX
3261 DEBUG_BREAKPOINT_TEST();
3262 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3263 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3264 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3265#else
3266 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3267 return VERR_NOT_SUPPORTED;
3268#endif
3269}
3270
3271
3272/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3273static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3274{
3275#ifdef VMSVGA3D_DX
3276 DEBUG_BREAKPOINT_TEST();
3277 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3278 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3279 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3280#else
3281 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3282 return VERR_NOT_SUPPORTED;
3283#endif
3284}
3285
3286
3287/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3288static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3289{
3290#ifdef VMSVGA3D_DX
3291 DEBUG_BREAKPOINT_TEST();
3292 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3293 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3294 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
3295#else
3296 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3297 return VERR_NOT_SUPPORTED;
3298#endif
3299}
3300
3301
3302/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3303static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3304{
3305#ifdef VMSVGA3D_DX
3306 DEBUG_BREAKPOINT_TEST();
3307 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3308 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3309 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
3310#else
3311 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3312 return VERR_NOT_SUPPORTED;
3313#endif
3314}
3315
3316
3317/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3318static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3319{
3320#ifdef VMSVGA3D_DX
3321 //DEBUG_BREAKPOINT_TEST();
3322 RT_NOREF(idDXContext, cbCmd);
3323
3324 /* This command is executed in a context: "The context is implied from the command buffer header."
3325 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3326 */
3327 SVGA3dCmdDXTransferFromBuffer cmd;
3328 cmd.srcSid = pCmd->srcSid;
3329 cmd.srcOffset = pCmd->srcOffset;
3330 cmd.srcPitch = pCmd->srcPitch;
3331 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3332 cmd.destSid = pCmd->destSid;
3333 cmd.destSubResource = pCmd->destSubResource;
3334 cmd.destBox = pCmd->destBox;
3335 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3336#else
3337 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3338 return VERR_NOT_SUPPORTED;
3339#endif
3340}
3341
3342
3343/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3344static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3345{
3346#ifdef VMSVGA3D_DX
3347 DEBUG_BREAKPOINT_TEST();
3348 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3349 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3350 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3351#else
3352 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3353 return VERR_NOT_SUPPORTED;
3354#endif
3355}
3356
3357
3358/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3359static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3360{
3361#ifdef VMSVGA3D_DX
3362 DEBUG_BREAKPOINT_TEST();
3363 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3364 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3365 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3366#else
3367 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3368 return VERR_NOT_SUPPORTED;
3369#endif
3370}
3371
3372
3373/* SVGA_3D_CMD_DX_HINT 1218 */
3374static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3375{
3376#ifdef VMSVGA3D_DX
3377 DEBUG_BREAKPOINT_TEST();
3378 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3379 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3380 return vmsvga3dDXHint(pThisCC, idDXContext);
3381#else
3382 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3383 return VERR_NOT_SUPPORTED;
3384#endif
3385}
3386
3387
3388/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3389static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3390{
3391#ifdef VMSVGA3D_DX
3392 DEBUG_BREAKPOINT_TEST();
3393 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3394 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3395 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3396#else
3397 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3398 return VERR_NOT_SUPPORTED;
3399#endif
3400}
3401
3402
3403/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3404static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3405{
3406#ifdef VMSVGA3D_DX
3407 DEBUG_BREAKPOINT_TEST();
3408 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3409 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3410 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3411#else
3412 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3413 return VERR_NOT_SUPPORTED;
3414#endif
3415}
3416
3417
3418/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3419static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3420{
3421#ifdef VMSVGA3D_DX
3422 DEBUG_BREAKPOINT_TEST();
3423 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3424 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3425 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3426#else
3427 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3428 return VERR_NOT_SUPPORTED;
3429#endif
3430}
3431
3432
3433/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3434static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3435{
3436#ifdef VMSVGA3D_DX
3437 DEBUG_BREAKPOINT_TEST();
3438 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3439 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3440 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3441#else
3442 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3443 return VERR_NOT_SUPPORTED;
3444#endif
3445}
3446
3447
3448/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3449static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3450{
3451#ifdef VMSVGA3D_DX
3452 DEBUG_BREAKPOINT_TEST();
3453 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3454 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3455 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3456#else
3457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3458 return VERR_NOT_SUPPORTED;
3459#endif
3460}
3461
3462
3463/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3464static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3465{
3466#ifdef VMSVGA3D_DX
3467 DEBUG_BREAKPOINT_TEST();
3468 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3469 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3470 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3471#else
3472 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3473 return VERR_NOT_SUPPORTED;
3474#endif
3475}
3476
3477
3478/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3479static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3480{
3481#ifdef VMSVGA3D_DX
3482 DEBUG_BREAKPOINT_TEST();
3483 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3484 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3485 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3486#else
3487 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3488 return VERR_NOT_SUPPORTED;
3489#endif
3490}
3491
3492
3493/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3494static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3495{
3496#ifdef VMSVGA3D_DX
3497 DEBUG_BREAKPOINT_TEST();
3498 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3499 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3500 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3501#else
3502 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3503 return VERR_NOT_SUPPORTED;
3504#endif
3505}
3506
3507
3508/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3509static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3510{
3511#ifdef VMSVGA3D_DX
3512 DEBUG_BREAKPOINT_TEST();
3513 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3514 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3515 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3516#else
3517 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3518 return VERR_NOT_SUPPORTED;
3519#endif
3520}
3521
3522
3523/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3524static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3525{
3526#ifdef VMSVGA3D_DX
3527 DEBUG_BREAKPOINT_TEST();
3528 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3529 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3530 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3531#else
3532 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3533 return VERR_NOT_SUPPORTED;
3534#endif
3535}
3536
3537
3538/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3539static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3540{
3541#ifdef VMSVGA3D_DX
3542 DEBUG_BREAKPOINT_TEST();
3543 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3544 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3545 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3546#else
3547 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3548 return VERR_NOT_SUPPORTED;
3549#endif
3550}
3551
3552
3553/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3554static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3555{
3556#ifdef VMSVGA3D_DX
3557 DEBUG_BREAKPOINT_TEST();
3558 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3559 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3560 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3561#else
3562 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3563 return VERR_NOT_SUPPORTED;
3564#endif
3565}
3566
3567
3568/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3569static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3570{
3571#ifdef VMSVGA3D_DX
3572 DEBUG_BREAKPOINT_TEST();
3573 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3574 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3575 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3576#else
3577 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3578 return VERR_NOT_SUPPORTED;
3579#endif
3580}
3581
3582
3583/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3584static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3585{
3586#ifdef VMSVGA3D_DX
3587 DEBUG_BREAKPOINT_TEST();
3588 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3589 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3590 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3591#else
3592 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3593 return VERR_NOT_SUPPORTED;
3594#endif
3595}
3596
3597
3598/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3599static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3600{
3601#ifdef VMSVGA3D_DX
3602 DEBUG_BREAKPOINT_TEST();
3603 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3604 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3605 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3606#else
3607 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3608 return VERR_NOT_SUPPORTED;
3609#endif
3610}
3611
3612
3613/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3614static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3615{
3616#ifdef VMSVGA3D_DX
3617 DEBUG_BREAKPOINT_TEST();
3618 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3619 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3620 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3621#else
3622 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3623 return VERR_NOT_SUPPORTED;
3624#endif
3625}
3626
3627
3628/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3629static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3630{
3631#ifdef VMSVGA3D_DX
3632 DEBUG_BREAKPOINT_TEST();
3633 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3634 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3635 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3636#else
3637 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3638 return VERR_NOT_SUPPORTED;
3639#endif
3640}
3641
3642
3643/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3644static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3645{
3646#ifdef VMSVGA3D_DX
3647 DEBUG_BREAKPOINT_TEST();
3648 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3649 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3650 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3651#else
3652 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3653 return VERR_NOT_SUPPORTED;
3654#endif
3655}
3656
3657
3658/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3659static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3660{
3661#ifdef VMSVGA3D_DX
3662 DEBUG_BREAKPOINT_TEST();
3663 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3664 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3665 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3666#else
3667 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3668 return VERR_NOT_SUPPORTED;
3669#endif
3670}
3671
3672
3673/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3674static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3675{
3676#ifdef VMSVGA3D_DX
3677 DEBUG_BREAKPOINT_TEST();
3678 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3679 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3680 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3681#else
3682 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3683 return VERR_NOT_SUPPORTED;
3684#endif
3685}
3686
3687
3688/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3689static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3690{
3691#ifdef VMSVGA3D_DX
3692 DEBUG_BREAKPOINT_TEST();
3693 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3694 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3695 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3696#else
3697 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3698 return VERR_NOT_SUPPORTED;
3699#endif
3700}
3701
3702
3703/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3704static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3705{
3706#ifdef VMSVGA3D_DX
3707 DEBUG_BREAKPOINT_TEST();
3708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3709 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3710 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3711#else
3712 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3713 return VERR_NOT_SUPPORTED;
3714#endif
3715}
3716
3717
3718/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3719static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3720{
3721#ifdef VMSVGA3D_DX
3722 DEBUG_BREAKPOINT_TEST();
3723 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3724 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3725 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3726#else
3727 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3728 return VERR_NOT_SUPPORTED;
3729#endif
3730}
3731
3732
3733/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3734static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3735{
3736#ifdef VMSVGA3D_DX
3737 DEBUG_BREAKPOINT_TEST();
3738 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3739 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3740 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3741#else
3742 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3743 return VERR_NOT_SUPPORTED;
3744#endif
3745}
3746
3747
3748/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3749static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3750{
3751#ifdef VMSVGA3D_DX
3752 DEBUG_BREAKPOINT_TEST();
3753 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3754 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3755 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3756#else
3757 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3758 return VERR_NOT_SUPPORTED;
3759#endif
3760}
3761
3762
3763/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3764static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3765{
3766#ifdef VMSVGA3D_DX
3767 DEBUG_BREAKPOINT_TEST();
3768 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3769 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3770 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3771#else
3772 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3773 return VERR_NOT_SUPPORTED;
3774#endif
3775}
3776
3777
3778/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3779static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3780{
3781#ifdef VMSVGA3D_DX
3782 DEBUG_BREAKPOINT_TEST();
3783 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3784 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3785 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3786#else
3787 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3788 return VERR_NOT_SUPPORTED;
3789#endif
3790}
3791
3792
3793/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3794static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3795{
3796#ifdef VMSVGA3D_DX
3797 DEBUG_BREAKPOINT_TEST();
3798 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3799 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3800 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3801#else
3802 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3803 return VERR_NOT_SUPPORTED;
3804#endif
3805}
3806
3807
3808/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3809static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3810{
3811#ifdef VMSVGA3D_DX
3812 DEBUG_BREAKPOINT_TEST();
3813 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3814 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3815 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3816#else
3817 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3818 return VERR_NOT_SUPPORTED;
3819#endif
3820}
3821
3822
3823/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3824static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3825{
3826#ifdef VMSVGA3D_DX
3827 DEBUG_BREAKPOINT_TEST();
3828 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3829 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3830 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3831#else
3832 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3833 return VERR_NOT_SUPPORTED;
3834#endif
3835}
3836
3837
3838/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3839static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3840{
3841#ifdef VMSVGA3D_DX
3842 DEBUG_BREAKPOINT_TEST();
3843 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3844 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3845 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3846#else
3847 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3848 return VERR_NOT_SUPPORTED;
3849#endif
3850}
3851
3852
3853/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3854static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3855{
3856#ifdef VMSVGA3D_DX
3857 DEBUG_BREAKPOINT_TEST();
3858 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3859 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3860 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3861#else
3862 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3863 return VERR_NOT_SUPPORTED;
3864#endif
3865}
3866
3867
3868/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3869static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3870{
3871#ifdef VMSVGA3D_DX
3872 DEBUG_BREAKPOINT_TEST();
3873 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3874 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3875 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3876#else
3877 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3878 return VERR_NOT_SUPPORTED;
3879#endif
3880}
3881
3882
3883/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3884static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3885{
3886#ifdef VMSVGA3D_DX
3887 DEBUG_BREAKPOINT_TEST();
3888 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3889 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3890 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3891#else
3892 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3893 return VERR_NOT_SUPPORTED;
3894#endif
3895}
3896
3897
3898/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3899static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3900{
3901#ifdef VMSVGA3D_DX
3902 DEBUG_BREAKPOINT_TEST();
3903 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3904 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3905 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3906#else
3907 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3908 return VERR_NOT_SUPPORTED;
3909#endif
3910}
3911
3912
3913/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3914static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3915{
3916#ifdef VMSVGA3D_DX
3917 DEBUG_BREAKPOINT_TEST();
3918 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3919 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3920 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3921#else
3922 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3923 return VERR_NOT_SUPPORTED;
3924#endif
3925}
3926
3927
3928/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3929static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3930{
3931#ifdef VMSVGA3D_DX
3932 DEBUG_BREAKPOINT_TEST();
3933 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3934 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3935 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3936#else
3937 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3938 return VERR_NOT_SUPPORTED;
3939#endif
3940}
3941
3942
3943/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3944static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3945{
3946#ifdef VMSVGA3D_DX
3947 DEBUG_BREAKPOINT_TEST();
3948 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3949 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3950 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3951#else
3952 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3953 return VERR_NOT_SUPPORTED;
3954#endif
3955}
3956
3957
3958/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3959static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3960{
3961#ifdef VMSVGA3D_DX
3962 DEBUG_BREAKPOINT_TEST();
3963 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3964 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3965 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3966#else
3967 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3968 return VERR_NOT_SUPPORTED;
3969#endif
3970}
3971
3972
3973/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3974static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3975{
3976#ifdef VMSVGA3D_DX
3977 DEBUG_BREAKPOINT_TEST();
3978 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3979 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3980 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3981#else
3982 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3983 return VERR_NOT_SUPPORTED;
3984#endif
3985}
3986
3987
3988/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3989static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3990{
3991#ifdef VMSVGA3D_DX
3992 DEBUG_BREAKPOINT_TEST();
3993 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3994 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3995 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3996#else
3997 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3998 return VERR_NOT_SUPPORTED;
3999#endif
4000}
4001
4002
4003/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4004static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4005{
4006#ifdef VMSVGA3D_DX
4007 //DEBUG_BREAKPOINT_TEST();
4008 RT_NOREF(cbCmd);
4009 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4010#else
4011 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4012 return VERR_NOT_SUPPORTED;
4013#endif
4014}
4015
4016
4017/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4018static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4019{
4020#ifdef VMSVGA3D_DX
4021 DEBUG_BREAKPOINT_TEST();
4022 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4023 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4024 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4025#else
4026 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4027 return VERR_NOT_SUPPORTED;
4028#endif
4029}
4030
4031
4032/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4033static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4034{
4035#ifdef VMSVGA3D_DX
4036 DEBUG_BREAKPOINT_TEST();
4037 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4038 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4039 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4040#else
4041 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4042 return VERR_NOT_SUPPORTED;
4043#endif
4044}
4045
4046
4047/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4048static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4049{
4050#ifdef VMSVGA3D_DX
4051 DEBUG_BREAKPOINT_TEST();
4052 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4053 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4054 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4055#else
4056 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4057 return VERR_NOT_SUPPORTED;
4058#endif
4059}
4060
4061
4062/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4063static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4064{
4065#ifdef VMSVGA3D_DX
4066 DEBUG_BREAKPOINT_TEST();
4067 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4068 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4069 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4070#else
4071 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4072 return VERR_NOT_SUPPORTED;
4073#endif
4074}
4075
4076
4077/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4078static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4079{
4080#ifdef VMSVGA3D_DX
4081 DEBUG_BREAKPOINT_TEST();
4082 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4083 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4084 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4085#else
4086 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4087 return VERR_NOT_SUPPORTED;
4088#endif
4089}
4090
4091
4092/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4093 * Check that the 3D command has at least a_cbMin of payload bytes after the
4094 * header. Will break out of the switch if it doesn't.
4095 */
4096# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4097 if (1) { \
4098 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4099 RT_UNTRUSTED_VALIDATED_FENCE(); \
4100 } else do {} while (0)
4101
4102# define VMSVGA_3D_CMD_NOTIMPL() \
4103 if (1) { \
4104 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4105 } else do {} while (0)
4106
4107/** SVGA_3D_CMD_* handler.
4108 * This function parses the command and calls the corresponding command handler.
4109 *
4110 * @param pThis The shared VGA/VMSVGA state.
4111 * @param pThisCC The VGA/VMSVGA state for the current context.
4112 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4113 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4114 * @param cbCmd Size of the command in bytes.
4115 * @param pvCmd Pointer to the command.
4116 * @returns VBox status code if an error was detected parsing a command.
4117 */
4118int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4119{
4120 if (enmCmdId > SVGA_3D_CMD_MAX)
4121 {
4122 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4123 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4124 }
4125
4126 int rcParse = VINF_SUCCESS;
4127 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4128
4129 switch (enmCmdId)
4130 {
4131 case SVGA_3D_CMD_SURFACE_DEFINE:
4132 {
4133 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4135 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4136
4137 SVGA3dCmdDefineSurface_v2 cmd;
4138 cmd.sid = pCmd->sid;
4139 cmd.surfaceFlags = pCmd->surfaceFlags;
4140 cmd.format = pCmd->format;
4141 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4142 cmd.multisampleCount = 0;
4143 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4144
4145 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4146 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4147# ifdef DEBUG_GMR_ACCESS
4148 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4149# endif
4150 break;
4151 }
4152
4153 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4154 {
4155 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4156 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4157 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4158
4159 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4160 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4161# ifdef DEBUG_GMR_ACCESS
4162 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4163# endif
4164 break;
4165 }
4166
4167 case SVGA_3D_CMD_SURFACE_DESTROY:
4168 {
4169 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4171 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4172
4173 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4174 break;
4175 }
4176
4177 case SVGA_3D_CMD_SURFACE_COPY:
4178 {
4179 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4180 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4181 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4182
4183 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4184 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4185 break;
4186 }
4187
4188 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4189 {
4190 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4191 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4192 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4193
4194 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4195 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4196 break;
4197 }
4198
4199 case SVGA_3D_CMD_SURFACE_DMA:
4200 {
4201 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4203 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4204
4205 uint64_t u64NanoTS = 0;
4206 if (LogRelIs3Enabled())
4207 u64NanoTS = RTTimeNanoTS();
4208 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4209 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4210 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4211 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4212 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4213 if (LogRelIs3Enabled())
4214 {
4215 if (cCopyBoxes)
4216 {
4217 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4218 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4219 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4220 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4221 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4222 }
4223 }
4224 break;
4225 }
4226
4227 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4228 {
4229 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4230 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4231 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4232
4233 static uint64_t u64FrameStartNanoTS = 0;
4234 static uint64_t u64ElapsedPerSecNano = 0;
4235 static int cFrames = 0;
4236 uint64_t u64NanoTS = 0;
4237 if (LogRelIs3Enabled())
4238 u64NanoTS = RTTimeNanoTS();
4239 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4240 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4241 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4242 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4243 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4244 if (LogRelIs3Enabled())
4245 {
4246 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4247 u64ElapsedPerSecNano += u64ElapsedNano;
4248
4249 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4250 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4251 (u64ElapsedNano) / 1000ULL, cRects,
4252 pFirstRect->left, pFirstRect->top,
4253 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4254
4255 ++cFrames;
4256 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4257 {
4258 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4259 cFrames, u64ElapsedPerSecNano / 1000ULL));
4260 u64FrameStartNanoTS = u64NanoTS;
4261 cFrames = 0;
4262 u64ElapsedPerSecNano = 0;
4263 }
4264 }
4265 break;
4266 }
4267
4268 case SVGA_3D_CMD_CONTEXT_DEFINE:
4269 {
4270 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4271 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4272 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4273
4274 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4275 break;
4276 }
4277
4278 case SVGA_3D_CMD_CONTEXT_DESTROY:
4279 {
4280 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4281 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4282 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4283
4284 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4285 break;
4286 }
4287
4288 case SVGA_3D_CMD_SETTRANSFORM:
4289 {
4290 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4291 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4292 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4293
4294 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4295 break;
4296 }
4297
4298 case SVGA_3D_CMD_SETZRANGE:
4299 {
4300 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4301 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4302 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4303
4304 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4305 break;
4306 }
4307
4308 case SVGA_3D_CMD_SETRENDERSTATE:
4309 {
4310 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4311 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4312 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4313
4314 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4315 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4316 break;
4317 }
4318
4319 case SVGA_3D_CMD_SETRENDERTARGET:
4320 {
4321 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4323 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4324
4325 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4326 break;
4327 }
4328
4329 case SVGA_3D_CMD_SETTEXTURESTATE:
4330 {
4331 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4332 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4333 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4334
4335 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4336 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4337 break;
4338 }
4339
4340 case SVGA_3D_CMD_SETMATERIAL:
4341 {
4342 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4343 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4344 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4345
4346 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4347 break;
4348 }
4349
4350 case SVGA_3D_CMD_SETLIGHTDATA:
4351 {
4352 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4354 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4355
4356 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4357 break;
4358 }
4359
4360 case SVGA_3D_CMD_SETLIGHTENABLED:
4361 {
4362 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4363 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4364 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4365
4366 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4367 break;
4368 }
4369
4370 case SVGA_3D_CMD_SETVIEWPORT:
4371 {
4372 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4373 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4374 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4375
4376 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4377 break;
4378 }
4379
4380 case SVGA_3D_CMD_SETCLIPPLANE:
4381 {
4382 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4383 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4384 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4385
4386 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4387 break;
4388 }
4389
4390 case SVGA_3D_CMD_CLEAR:
4391 {
4392 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4393 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4394 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4395
4396 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4397 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4398 break;
4399 }
4400
4401 case SVGA_3D_CMD_PRESENT:
4402 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4403 {
4404 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4405 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4406 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4407 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4408 else
4409 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4410
4411 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4412 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4413 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4414 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4415 break;
4416 }
4417
4418 case SVGA_3D_CMD_SHADER_DEFINE:
4419 {
4420 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4421 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4423
4424 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4425 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4426 break;
4427 }
4428
4429 case SVGA_3D_CMD_SHADER_DESTROY:
4430 {
4431 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4433 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4434
4435 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4436 break;
4437 }
4438
4439 case SVGA_3D_CMD_SET_SHADER:
4440 {
4441 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4443 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4444
4445 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4446 break;
4447 }
4448
4449 case SVGA_3D_CMD_SET_SHADER_CONST:
4450 {
4451 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4452 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4453 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4454
4455 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4456 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4457 break;
4458 }
4459
4460 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4461 {
4462 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4464 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4465
4466 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4467 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4468 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4469 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4470 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4471
4472 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4473 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4474 RT_UNTRUSTED_VALIDATED_FENCE();
4475
4476 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4477 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4478 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4479
4480 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4481 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4482 pNumRange, cVertexDivisor, pVertexDivisor);
4483 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4484 break;
4485 }
4486
4487 case SVGA_3D_CMD_SETSCISSORRECT:
4488 {
4489 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4490 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4491 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4492
4493 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4494 break;
4495 }
4496
4497 case SVGA_3D_CMD_BEGIN_QUERY:
4498 {
4499 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4500 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4501 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4502
4503 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4504 break;
4505 }
4506
4507 case SVGA_3D_CMD_END_QUERY:
4508 {
4509 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4511 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4512
4513 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4514 break;
4515 }
4516
4517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4518 {
4519 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4520 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4522
4523 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4524 break;
4525 }
4526
4527 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4528 {
4529 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4530 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4532
4533 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4534 break;
4535 }
4536
4537 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4538 /* context id + surface id? */
4539 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4540 break;
4541
4542 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4543 /* context id + surface id? */
4544 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4545 break;
4546
4547 /*
4548 *
4549 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4550 *
4551 */
4552 case SVGA_3D_CMD_SCREEN_DMA:
4553 {
4554 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4555 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4556 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4557 break;
4558 }
4559
4560 case SVGA_3D_CMD_DEAD1:
4561 case SVGA_3D_CMD_DEAD2:
4562 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4563 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4564 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4565 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4566 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4567 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4568 {
4569 VMSVGA_3D_CMD_NOTIMPL();
4570 break;
4571 }
4572
4573 case SVGA_3D_CMD_SET_OTABLE_BASE:
4574 {
4575 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4576 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4578 break;
4579 }
4580
4581 case SVGA_3D_CMD_READBACK_OTABLE:
4582 {
4583 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4584 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4585 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4586 break;
4587 }
4588
4589 case SVGA_3D_CMD_DEFINE_GB_MOB:
4590 {
4591 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4592 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4593 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4594 break;
4595 }
4596
4597 case SVGA_3D_CMD_DESTROY_GB_MOB:
4598 {
4599 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4600 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4601 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4602 break;
4603 }
4604
4605 case SVGA_3D_CMD_DEAD3:
4606 {
4607 VMSVGA_3D_CMD_NOTIMPL();
4608 break;
4609 }
4610
4611 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4612 {
4613 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4614 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4616 break;
4617 }
4618
4619 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4620 {
4621 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4623 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4624 break;
4625 }
4626
4627 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4628 {
4629 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4631 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4632 break;
4633 }
4634
4635 case SVGA_3D_CMD_BIND_GB_SURFACE:
4636 {
4637 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4639 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4640 break;
4641 }
4642
4643 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4644 {
4645 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4647 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4648 break;
4649 }
4650
4651 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4652 {
4653 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4655 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4656 break;
4657 }
4658
4659 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4660 {
4661 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4662 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4663 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4664 break;
4665 }
4666
4667 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4668 {
4669 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4670 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4671 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4672 break;
4673 }
4674
4675 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4676 {
4677 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4678 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4679 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4680 break;
4681 }
4682
4683 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4684 {
4685 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4686 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4687 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4688 break;
4689 }
4690
4691 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4692 {
4693 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4694 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4695 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4696 break;
4697 }
4698
4699 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4700 {
4701 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4702 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4704 break;
4705 }
4706
4707 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4708 {
4709 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4710 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4711 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4712 break;
4713 }
4714
4715 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4716 {
4717 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4718 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4719 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4720 break;
4721 }
4722
4723 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4724 {
4725 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4726 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4727 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4728 break;
4729 }
4730
4731 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4732 {
4733 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4734 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4735 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4736 break;
4737 }
4738
4739 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4740 {
4741 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4742 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4743 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4744 break;
4745 }
4746
4747 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4748 {
4749 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4750 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4751 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4752 break;
4753 }
4754
4755 case SVGA_3D_CMD_BIND_GB_SHADER:
4756 {
4757 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4758 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4759 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4760 break;
4761 }
4762
4763 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4764 {
4765 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4766 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4767 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4768 break;
4769 }
4770
4771 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4772 {
4773 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4775 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4776 break;
4777 }
4778
4779 case SVGA_3D_CMD_END_GB_QUERY:
4780 {
4781 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4782 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4783 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4784 break;
4785 }
4786
4787 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4788 {
4789 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4790 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4791 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4792 break;
4793 }
4794
4795 case SVGA_3D_CMD_NOP:
4796 {
4797 /* Apparently there is nothing to do. */
4798 break;
4799 }
4800
4801 case SVGA_3D_CMD_ENABLE_GART:
4802 {
4803 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4804 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4805 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4806 break;
4807 }
4808
4809 case SVGA_3D_CMD_DISABLE_GART:
4810 {
4811 /* No corresponding SVGA3dCmd structure. */
4812 VMSVGA_3D_CMD_NOTIMPL();
4813 break;
4814 }
4815
4816 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4817 {
4818 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4819 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4820 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4821 break;
4822 }
4823
4824 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4825 {
4826 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4827 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4828 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4829 break;
4830 }
4831
4832 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4833 {
4834 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4835 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4836 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4837 break;
4838 }
4839
4840 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4841 {
4842 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4843 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4844 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4845 break;
4846 }
4847
4848 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4849 {
4850 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4851 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4852 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4853 break;
4854 }
4855
4856 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4857 {
4858 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4859 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4860 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4861 break;
4862 }
4863
4864 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4865 {
4866 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4867 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4868 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4869 break;
4870 }
4871
4872 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4873 {
4874 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4875 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4876 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4877 break;
4878 }
4879
4880 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4881 {
4882 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4883 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4884 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4885 break;
4886 }
4887
4888 case SVGA_3D_CMD_GB_SCREEN_DMA:
4889 {
4890 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4891 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4892 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4893 break;
4894 }
4895
4896 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4897 {
4898 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4899 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4900 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4901 break;
4902 }
4903
4904 case SVGA_3D_CMD_GB_MOB_FENCE:
4905 {
4906 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4907 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4908 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4909 break;
4910 }
4911
4912 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4913 {
4914 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4915 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4916 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4917 break;
4918 }
4919
4920 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4921 {
4922 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4923 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4924 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4925 break;
4926 }
4927
4928 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4929 {
4930 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4931 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4932 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4933 break;
4934 }
4935
4936 case SVGA_3D_CMD_NOP_ERROR:
4937 {
4938 /* Apparently there is nothing to do. */
4939 break;
4940 }
4941
4942 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4943 {
4944 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4946 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4947 break;
4948 }
4949
4950 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4951 {
4952 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4954 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4955 break;
4956 }
4957
4958 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4959 {
4960 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4962 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4963 break;
4964 }
4965
4966 case SVGA_3D_CMD_DRAW:
4967 {
4968 /* No corresponding SVGA3dCmd structure. */
4969 VMSVGA_3D_CMD_NOTIMPL();
4970 break;
4971 }
4972
4973 case SVGA_3D_CMD_DRAW_INDEXED:
4974 {
4975 /* No corresponding SVGA3dCmd structure. */
4976 VMSVGA_3D_CMD_NOTIMPL();
4977 break;
4978 }
4979
4980 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4981 {
4982 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4983 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4984 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4985 break;
4986 }
4987
4988 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4989 {
4990 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4992 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4993 break;
4994 }
4995
4996 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4997 {
4998 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4999 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5000 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5001 break;
5002 }
5003
5004 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5005 {
5006 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5007 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5008 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5009 break;
5010 }
5011
5012 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5013 {
5014 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5015 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5016 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5017 break;
5018 }
5019
5020 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5021 {
5022 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5024 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5025 break;
5026 }
5027
5028 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5029 {
5030 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5031 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5032 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5033 break;
5034 }
5035
5036 case SVGA_3D_CMD_DX_SET_SHADER:
5037 {
5038 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5039 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5040 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5041 break;
5042 }
5043
5044 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5045 {
5046 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5047 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5048 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5049 break;
5050 }
5051
5052 case SVGA_3D_CMD_DX_DRAW:
5053 {
5054 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5055 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5056 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5057 break;
5058 }
5059
5060 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5061 {
5062 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5063 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5064 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5065 break;
5066 }
5067
5068 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5069 {
5070 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5071 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5072 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5073 break;
5074 }
5075
5076 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5077 {
5078 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5079 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5080 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5081 break;
5082 }
5083
5084 case SVGA_3D_CMD_DX_DRAW_AUTO:
5085 {
5086 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5087 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5088 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5089 break;
5090 }
5091
5092 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5093 {
5094 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5095 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5096 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5097 break;
5098 }
5099
5100 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5101 {
5102 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5103 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5104 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5105 break;
5106 }
5107
5108 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5109 {
5110 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5111 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5112 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5113 break;
5114 }
5115
5116 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5117 {
5118 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5119 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5120 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5121 break;
5122 }
5123
5124 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5125 {
5126 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5127 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5128 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5129 break;
5130 }
5131
5132 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5133 {
5134 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5135 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5136 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5137 break;
5138 }
5139
5140 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5141 {
5142 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5143 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5144 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5145 break;
5146 }
5147
5148 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5149 {
5150 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5151 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5152 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5153 break;
5154 }
5155
5156 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5157 {
5158 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5159 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5160 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5161 break;
5162 }
5163
5164 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5165 {
5166 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5167 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5168 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5169 break;
5170 }
5171
5172 case SVGA_3D_CMD_DX_BIND_QUERY:
5173 {
5174 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5175 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5176 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5177 break;
5178 }
5179
5180 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5181 {
5182 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5183 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5184 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5185 break;
5186 }
5187
5188 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5189 {
5190 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5191 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5192 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5193 break;
5194 }
5195
5196 case SVGA_3D_CMD_DX_END_QUERY:
5197 {
5198 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5199 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5200 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5201 break;
5202 }
5203
5204 case SVGA_3D_CMD_DX_READBACK_QUERY:
5205 {
5206 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5207 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5208 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5209 break;
5210 }
5211
5212 case SVGA_3D_CMD_DX_SET_PREDICATION:
5213 {
5214 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5215 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5216 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5217 break;
5218 }
5219
5220 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5221 {
5222 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5223 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5224 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5225 break;
5226 }
5227
5228 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5229 {
5230 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5232 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5233 break;
5234 }
5235
5236 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5237 {
5238 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5239 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5240 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5241 break;
5242 }
5243
5244 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5245 {
5246 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5247 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5248 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5249 break;
5250 }
5251
5252 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5253 {
5254 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5255 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5256 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5257 break;
5258 }
5259
5260 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5261 {
5262 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5263 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5264 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5265 break;
5266 }
5267
5268 case SVGA_3D_CMD_DX_PRED_COPY:
5269 {
5270 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5271 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5272 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5273 break;
5274 }
5275
5276 case SVGA_3D_CMD_DX_PRESENTBLT:
5277 {
5278 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5279 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5280 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5281 break;
5282 }
5283
5284 case SVGA_3D_CMD_DX_GENMIPS:
5285 {
5286 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5287 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5288 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5289 break;
5290 }
5291
5292 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5293 {
5294 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5295 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5296 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5297 break;
5298 }
5299
5300 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5301 {
5302 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5303 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5304 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5305 break;
5306 }
5307
5308 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5309 {
5310 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5311 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5312 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5313 break;
5314 }
5315
5316 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5317 {
5318 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5319 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5320 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5321 break;
5322 }
5323
5324 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5325 {
5326 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5327 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5328 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5329 break;
5330 }
5331
5332 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5333 {
5334 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5335 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5336 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5337 break;
5338 }
5339
5340 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5341 {
5342 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5343 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5344 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5345 break;
5346 }
5347
5348 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5349 {
5350 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5351 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5352 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5353 break;
5354 }
5355
5356 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5357 {
5358 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5359 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5360 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5361 break;
5362 }
5363
5364 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5365 {
5366 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5367 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5368 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5369 break;
5370 }
5371
5372 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5373 {
5374 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5375 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5376 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5377 break;
5378 }
5379
5380 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5381 {
5382 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5383 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5384 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5385 break;
5386 }
5387
5388 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5389 {
5390 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5391 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5392 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5393 break;
5394 }
5395
5396 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5397 {
5398 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5399 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5400 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5401 break;
5402 }
5403
5404 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5405 {
5406 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5407 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5408 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5409 break;
5410 }
5411
5412 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5413 {
5414 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5415 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5416 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5417 break;
5418 }
5419
5420 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5421 {
5422 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5423 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5424 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5425 break;
5426 }
5427
5428 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5429 {
5430 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5431 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5432 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5433 break;
5434 }
5435
5436 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5437 {
5438 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5439 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5440 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5441 break;
5442 }
5443
5444 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5445 {
5446 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5447 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5448 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5449 break;
5450 }
5451
5452 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5453 {
5454 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5455 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5456 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5457 break;
5458 }
5459
5460 case SVGA_3D_CMD_DX_BIND_SHADER:
5461 {
5462 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5464 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5465 break;
5466 }
5467
5468 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5469 {
5470 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5471 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5472 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5473 break;
5474 }
5475
5476 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5477 {
5478 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5479 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5480 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5481 break;
5482 }
5483
5484 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5485 {
5486 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5488 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5489 break;
5490 }
5491
5492 case SVGA_3D_CMD_DX_SET_COTABLE:
5493 {
5494 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5495 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5496 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5497 break;
5498 }
5499
5500 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5501 {
5502 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5504 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5505 break;
5506 }
5507
5508 case SVGA_3D_CMD_DX_BUFFER_COPY:
5509 {
5510 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5511 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5512 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5513 break;
5514 }
5515
5516 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5517 {
5518 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5519 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5520 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5521 break;
5522 }
5523
5524 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5525 {
5526 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5528 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5529 break;
5530 }
5531
5532 case SVGA_3D_CMD_DX_MOVE_QUERY:
5533 {
5534 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5535 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5536 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5537 break;
5538 }
5539
5540 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5541 {
5542 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5543 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5544 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5545 break;
5546 }
5547
5548 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5549 {
5550 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5551 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5552 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5553 break;
5554 }
5555
5556 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5557 {
5558 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5559 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5560 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5561 break;
5562 }
5563
5564 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5565 {
5566 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5567 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5568 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5569 break;
5570 }
5571
5572 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5573 {
5574 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5575 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5576 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5577 break;
5578 }
5579
5580 case SVGA_3D_CMD_DX_HINT:
5581 {
5582 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5584 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5585 break;
5586 }
5587
5588 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5589 {
5590 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5592 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5593 break;
5594 }
5595
5596 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5597 {
5598 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5600 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5601 break;
5602 }
5603
5604 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5605 {
5606 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5607 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5608 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5609 break;
5610 }
5611
5612 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5613 {
5614 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5615 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5616 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5617 break;
5618 }
5619
5620 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5621 {
5622 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5624 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5625 break;
5626 }
5627
5628 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5629 {
5630 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5631 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5632 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5633 break;
5634 }
5635
5636 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5637 {
5638 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5639 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5640 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5641 break;
5642 }
5643
5644 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5645 {
5646 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5647 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5648 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5649 break;
5650 }
5651
5652 case SVGA_3D_CMD_SCREEN_COPY:
5653 {
5654 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5655 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5656 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5657 break;
5658 }
5659
5660 case SVGA_3D_CMD_RESERVED1:
5661 {
5662 VMSVGA_3D_CMD_NOTIMPL();
5663 break;
5664 }
5665
5666 case SVGA_3D_CMD_RESERVED2:
5667 {
5668 VMSVGA_3D_CMD_NOTIMPL();
5669 break;
5670 }
5671
5672 case SVGA_3D_CMD_RESERVED3:
5673 {
5674 VMSVGA_3D_CMD_NOTIMPL();
5675 break;
5676 }
5677
5678 case SVGA_3D_CMD_RESERVED4:
5679 {
5680 VMSVGA_3D_CMD_NOTIMPL();
5681 break;
5682 }
5683
5684 case SVGA_3D_CMD_RESERVED5:
5685 {
5686 VMSVGA_3D_CMD_NOTIMPL();
5687 break;
5688 }
5689
5690 case SVGA_3D_CMD_RESERVED6:
5691 {
5692 VMSVGA_3D_CMD_NOTIMPL();
5693 break;
5694 }
5695
5696 case SVGA_3D_CMD_RESERVED7:
5697 {
5698 VMSVGA_3D_CMD_NOTIMPL();
5699 break;
5700 }
5701
5702 case SVGA_3D_CMD_RESERVED8:
5703 {
5704 VMSVGA_3D_CMD_NOTIMPL();
5705 break;
5706 }
5707
5708 case SVGA_3D_CMD_GROW_OTABLE:
5709 {
5710 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5711 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5712 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5713 break;
5714 }
5715
5716 case SVGA_3D_CMD_DX_GROW_COTABLE:
5717 {
5718 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5719 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5720 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5721 break;
5722 }
5723
5724 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5725 {
5726 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5727 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5728 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5729 break;
5730 }
5731
5732 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5733 {
5734 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5735 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5736 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5737 break;
5738 }
5739
5740 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5741 {
5742 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5743 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5744 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5745 break;
5746 }
5747
5748 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5749 {
5750 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5751 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5752 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5753 break;
5754 }
5755
5756 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5757 {
5758 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5759 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5760 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5761 break;
5762 }
5763
5764 case SVGA_3D_CMD_DX_PRED_CONVERT:
5765 {
5766 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5767 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5768 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5769 break;
5770 }
5771
5772 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5773 {
5774 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5775 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5776 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5777 break;
5778 }
5779
5780 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5781 {
5782 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5783 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5784 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5785 break;
5786 }
5787
5788 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5789 {
5790 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5791 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5792 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5793 break;
5794 }
5795
5796 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5797 {
5798 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5799 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5800 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5801 break;
5802 }
5803
5804 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5805 {
5806 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5807 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5808 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5809 break;
5810 }
5811
5812 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5813 {
5814 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5815 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5816 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5817 break;
5818 }
5819
5820 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5821 {
5822 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5823 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5824 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5825 break;
5826 }
5827
5828 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5829 {
5830 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5831 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5832 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5833 break;
5834 }
5835
5836 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5837 {
5838 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5839 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5840 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5841 break;
5842 }
5843
5844 case SVGA_3D_CMD_DX_DISPATCH:
5845 {
5846 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5847 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5848 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5849 break;
5850 }
5851
5852 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5853 {
5854 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5855 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5856 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5857 break;
5858 }
5859
5860 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5861 {
5862 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5863 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5864 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5865 break;
5866 }
5867
5868 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5869 {
5870 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5871 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5872 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5873 break;
5874 }
5875
5876 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5877 {
5878 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5879 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5880 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5881 break;
5882 }
5883
5884 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5885 {
5886 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5887 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5888 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5889 break;
5890 }
5891
5892 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5893 {
5894 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5895 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5896 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5897 break;
5898 }
5899
5900 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5901 {
5902 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5903 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5904 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5905 break;
5906 }
5907
5908 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5909 {
5910 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5911 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5912 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5913 break;
5914 }
5915
5916 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5917 {
5918 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5919 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5920 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5921 break;
5922 }
5923
5924 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5925 {
5926 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5927 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5928 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5929 break;
5930 }
5931
5932 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5933 {
5934 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5935 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5936 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5937 break;
5938 }
5939
5940 case SVGA_3D_CMD_RESERVED2_1:
5941 {
5942 VMSVGA_3D_CMD_NOTIMPL();
5943 break;
5944 }
5945
5946 case SVGA_3D_CMD_RESERVED2_2:
5947 {
5948 VMSVGA_3D_CMD_NOTIMPL();
5949 break;
5950 }
5951
5952 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5953 {
5954 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5955 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5956 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5957 break;
5958 }
5959
5960 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5961 {
5962 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5964 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5965 break;
5966 }
5967
5968 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5969 {
5970 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5971 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5972 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5973 break;
5974 }
5975
5976 case SVGA_3D_CMD_RESERVED2_3:
5977 {
5978 VMSVGA_3D_CMD_NOTIMPL();
5979 break;
5980 }
5981
5982 case SVGA_3D_CMD_RESERVED2_4:
5983 {
5984 VMSVGA_3D_CMD_NOTIMPL();
5985 break;
5986 }
5987
5988 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5989 {
5990 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5992 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5993 break;
5994 }
5995
5996 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5997 {
5998 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5999 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6000 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6001 break;
6002 }
6003
6004 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6005 {
6006 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6007 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6008 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6009 break;
6010 }
6011
6012 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6013 {
6014 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6015 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6016 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6017 break;
6018 }
6019
6020 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6021 {
6022 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6024 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6025 break;
6026 }
6027
6028 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6029 {
6030 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6031 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6032 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6033 break;
6034 }
6035
6036 /* Unsupported commands. */
6037 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6038 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6039 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6040 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6041 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6042 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6043 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6044 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6045 /* Prevent the compiler warning. */
6046 case SVGA_3D_CMD_LEGACY_BASE:
6047 case SVGA_3D_CMD_MAX:
6048 case SVGA_3D_CMD_FUTURE_MAX:
6049 /* No 'default' case */
6050 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6051 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6052 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6053 rcParse = VERR_NOT_IMPLEMENTED;
6054 break;
6055 }
6056
6057 return VINF_SUCCESS;
6058// return rcParse;
6059}
6060# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6061#endif /* VBOX_WITH_VMSVGA3D */
6062
6063
6064/*
6065 *
6066 * Handlers for FIFO commands.
6067 *
6068 * Every handler takes the following parameters:
6069 *
6070 * pThis The shared VGA/VMSVGA state.
6071 * pThisCC The VGA/VMSVGA state for ring-3.
6072 * pCmd The command data.
6073 */
6074
6075
6076/* SVGA_CMD_UPDATE */
6077void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6078{
6079 RT_NOREF(pThis);
6080 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6081
6082 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6083 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6084
6085 /** @todo Multiple screens? */
6086 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6087 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6088 return;
6089
6090 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6091}
6092
6093
6094/* SVGA_CMD_UPDATE_VERBOSE */
6095void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6096{
6097 RT_NOREF(pThis);
6098 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6099
6100 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6101 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6102
6103 /** @todo Multiple screens? */
6104 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6105 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6106 return;
6107
6108 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6109}
6110
6111
6112/* SVGA_CMD_RECT_FILL */
6113void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6114{
6115 RT_NOREF(pThis, pCmd);
6116 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6117
6118 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6119 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6120 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6121}
6122
6123
6124/* SVGA_CMD_RECT_COPY */
6125void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6126{
6127 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6128
6129 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6130 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6131
6132 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6133 AssertPtrReturnVoid(pScreen);
6134
6135 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6136 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6137 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6138 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6139 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6140 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6141 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6142
6143 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6144 pCmd->width, pCmd->height, pThis->vram_size);
6145 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6146}
6147
6148
6149/* SVGA_CMD_RECT_ROP_COPY */
6150void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6151{
6152 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6153
6154 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6155 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6156
6157 if (pCmd->rop != SVGA_ROP_COPY)
6158 {
6159 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6160 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6161 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6162 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6163 */
6164 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6165 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6166 return;
6167 }
6168
6169 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6170 AssertPtrReturnVoid(pScreen);
6171
6172 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6173 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6174 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6175 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6176 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6177 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6178 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6179
6180 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6181 pCmd->width, pCmd->height, pThis->vram_size);
6182 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6183}
6184
6185
6186/* SVGA_CMD_DISPLAY_CURSOR */
6187void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6188{
6189 RT_NOREF(pThis, pCmd);
6190 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6191
6192 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6193 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6194 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6195}
6196
6197
6198/* SVGA_CMD_MOVE_CURSOR */
6199void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6200{
6201 RT_NOREF(pThis, pCmd);
6202 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6203
6204 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6205 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6206 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6207}
6208
6209
6210/* SVGA_CMD_DEFINE_CURSOR */
6211void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6212{
6213 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6214
6215 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6216 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6217 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6218
6219 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6220 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6221 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6222 RT_UNTRUSTED_VALIDATED_FENCE();
6223
6224 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6225 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6226 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6227
6228 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6229 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6230
6231 uint32_t const cx = pCmd->width;
6232 uint32_t const cy = pCmd->height;
6233
6234 /*
6235 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6236 * The AND data uses 8-bit aligned scanlines.
6237 * The XOR data must be starting on a 32-bit boundrary.
6238 */
6239 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6240 uint32_t cbDstAndMask = cbDstAndLine * cy;
6241 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6242 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6243
6244 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6245 AssertReturnVoid(pbCopy);
6246
6247 /* Convert the AND mask. */
6248 uint8_t *pbDst = pbCopy;
6249 uint8_t const *pbSrc = pbSrcAndMask;
6250 switch (pCmd->andMaskDepth)
6251 {
6252 case 1:
6253 if (cbSrcAndLine == cbDstAndLine)
6254 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6255 else
6256 {
6257 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6258 for (uint32_t y = 0; y < cy; y++)
6259 {
6260 memcpy(pbDst, pbSrc, cbDstAndLine);
6261 pbDst += cbDstAndLine;
6262 pbSrc += cbSrcAndLine;
6263 }
6264 }
6265 break;
6266 /* Should take the XOR mask into account for the multi-bit AND mask. */
6267 case 8:
6268 for (uint32_t y = 0; y < cy; y++)
6269 {
6270 for (uint32_t x = 0; x < cx; )
6271 {
6272 uint8_t bDst = 0;
6273 uint8_t fBit = 0x80;
6274 do
6275 {
6276 uintptr_t const idxPal = pbSrc[x] * 3;
6277 if ((( pThis->last_palette[idxPal]
6278 | (pThis->last_palette[idxPal] >> 8)
6279 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6280 bDst |= fBit;
6281 fBit >>= 1;
6282 x++;
6283 } while (x < cx && (x & 7));
6284 pbDst[(x - 1) / 8] = bDst;
6285 }
6286 pbDst += cbDstAndLine;
6287 pbSrc += cbSrcAndLine;
6288 }
6289 break;
6290 case 15:
6291 for (uint32_t y = 0; y < cy; y++)
6292 {
6293 for (uint32_t x = 0; x < cx; )
6294 {
6295 uint8_t bDst = 0;
6296 uint8_t fBit = 0x80;
6297 do
6298 {
6299 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6300 bDst |= fBit;
6301 fBit >>= 1;
6302 x++;
6303 } while (x < cx && (x & 7));
6304 pbDst[(x - 1) / 8] = bDst;
6305 }
6306 pbDst += cbDstAndLine;
6307 pbSrc += cbSrcAndLine;
6308 }
6309 break;
6310 case 16:
6311 for (uint32_t y = 0; y < cy; y++)
6312 {
6313 for (uint32_t x = 0; x < cx; )
6314 {
6315 uint8_t bDst = 0;
6316 uint8_t fBit = 0x80;
6317 do
6318 {
6319 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6320 bDst |= fBit;
6321 fBit >>= 1;
6322 x++;
6323 } while (x < cx && (x & 7));
6324 pbDst[(x - 1) / 8] = bDst;
6325 }
6326 pbDst += cbDstAndLine;
6327 pbSrc += cbSrcAndLine;
6328 }
6329 break;
6330 case 24:
6331 for (uint32_t y = 0; y < cy; y++)
6332 {
6333 for (uint32_t x = 0; x < cx; )
6334 {
6335 uint8_t bDst = 0;
6336 uint8_t fBit = 0x80;
6337 do
6338 {
6339 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6340 bDst |= fBit;
6341 fBit >>= 1;
6342 x++;
6343 } while (x < cx && (x & 7));
6344 pbDst[(x - 1) / 8] = bDst;
6345 }
6346 pbDst += cbDstAndLine;
6347 pbSrc += cbSrcAndLine;
6348 }
6349 break;
6350 case 32:
6351 for (uint32_t y = 0; y < cy; y++)
6352 {
6353 for (uint32_t x = 0; x < cx; )
6354 {
6355 uint8_t bDst = 0;
6356 uint8_t fBit = 0x80;
6357 do
6358 {
6359 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6360 bDst |= fBit;
6361 fBit >>= 1;
6362 x++;
6363 } while (x < cx && (x & 7));
6364 pbDst[(x - 1) / 8] = bDst;
6365 }
6366 pbDst += cbDstAndLine;
6367 pbSrc += cbSrcAndLine;
6368 }
6369 break;
6370 default:
6371 RTMemFreeZ(pbCopy, cbCopy);
6372 AssertFailedReturnVoid();
6373 }
6374
6375 /* Convert the XOR mask. */
6376 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6377 pbSrc = pbSrcXorMask;
6378 switch (pCmd->xorMaskDepth)
6379 {
6380 case 1:
6381 for (uint32_t y = 0; y < cy; y++)
6382 {
6383 for (uint32_t x = 0; x < cx; )
6384 {
6385 /* most significant bit is the left most one. */
6386 uint8_t bSrc = pbSrc[x / 8];
6387 do
6388 {
6389 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6390 bSrc <<= 1;
6391 x++;
6392 } while ((x & 7) && x < cx);
6393 }
6394 pbSrc += cbSrcXorLine;
6395 }
6396 break;
6397 case 8:
6398 for (uint32_t y = 0; y < cy; y++)
6399 {
6400 for (uint32_t x = 0; x < cx; x++)
6401 {
6402 uint32_t u = pThis->last_palette[pbSrc[x]];
6403 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6404 }
6405 pbSrc += cbSrcXorLine;
6406 }
6407 break;
6408 case 15: /* Src: RGB-5-5-5 */
6409 for (uint32_t y = 0; y < cy; y++)
6410 {
6411 for (uint32_t x = 0; x < cx; x++)
6412 {
6413 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6414 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6415 ((uValue >> 5) & 0x1f) << 3,
6416 ((uValue >> 10) & 0x1f) << 3, 0);
6417 }
6418 pbSrc += cbSrcXorLine;
6419 }
6420 break;
6421 case 16: /* Src: RGB-5-6-5 */
6422 for (uint32_t y = 0; y < cy; y++)
6423 {
6424 for (uint32_t x = 0; x < cx; x++)
6425 {
6426 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6427 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6428 ((uValue >> 5) & 0x3f) << 2,
6429 ((uValue >> 11) & 0x1f) << 3, 0);
6430 }
6431 pbSrc += cbSrcXorLine;
6432 }
6433 break;
6434 case 24:
6435 for (uint32_t y = 0; y < cy; y++)
6436 {
6437 for (uint32_t x = 0; x < cx; x++)
6438 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6439 pbSrc += cbSrcXorLine;
6440 }
6441 break;
6442 case 32:
6443 for (uint32_t y = 0; y < cy; y++)
6444 {
6445 for (uint32_t x = 0; x < cx; x++)
6446 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6447 pbSrc += cbSrcXorLine;
6448 }
6449 break;
6450 default:
6451 RTMemFreeZ(pbCopy, cbCopy);
6452 AssertFailedReturnVoid();
6453 }
6454
6455 /*
6456 * Pass it to the frontend/whatever.
6457 */
6458 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6459 cx, cy, pbCopy, cbCopy);
6460}
6461
6462
6463/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6464void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6465{
6466 RT_NOREF(pThis);
6467 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6468
6469 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6470 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6471
6472 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6473 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6474 RT_UNTRUSTED_VALIDATED_FENCE();
6475
6476 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6477 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6478 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6479 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6480 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6481
6482 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6483 AssertPtrReturnVoid(pCursorCopy);
6484
6485 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6486 memset(pCursorCopy, 0xff, cbAndMask);
6487 /* Colour data */
6488 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6489
6490 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6491 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6492}
6493
6494
6495/* SVGA_CMD_ESCAPE */
6496void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6497{
6498 RT_NOREF(pThis);
6499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6500
6501 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6502
6503 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6504 {
6505 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6506 RT_UNTRUSTED_VALIDATED_FENCE();
6507
6508 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6509 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6510
6511 switch (cmd)
6512 {
6513 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6514 {
6515 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6516 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6517 RT_UNTRUSTED_VALIDATED_FENCE();
6518
6519 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6520
6521 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6522 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6523 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6524 RT_NOREF_PV(pVideoCmd);
6525 break;
6526 }
6527
6528 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6529 {
6530 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6531 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6532 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6533 RT_NOREF_PV(pVideoCmd);
6534 break;
6535 }
6536
6537 default:
6538 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6539 break;
6540 }
6541 }
6542 else
6543 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6544}
6545
6546
6547/* SVGA_CMD_DEFINE_SCREEN */
6548void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6549{
6550 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6551
6552 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6553 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6554 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6555 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6556
6557 uint32_t const idScreen = pCmd->screen.id;
6558 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6559
6560 uint32_t const uWidth = pCmd->screen.size.width;
6561 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6562
6563 uint32_t const uHeight = pCmd->screen.size.height;
6564 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6565
6566 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6567 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6568 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6569
6570 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6571 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6572
6573 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6574 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6575 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6576 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6577 RT_UNTRUSTED_VALIDATED_FENCE();
6578
6579 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6580 pScreen->fDefined = true;
6581 pScreen->fModified = true;
6582 pScreen->fuScreen = pCmd->screen.flags;
6583 pScreen->idScreen = idScreen;
6584 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6585 {
6586 /* Not blanked. */
6587 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6588 RT_UNTRUSTED_VALIDATED_FENCE();
6589
6590 pScreen->xOrigin = pCmd->screen.root.x;
6591 pScreen->yOrigin = pCmd->screen.root.y;
6592 pScreen->cWidth = uWidth;
6593 pScreen->cHeight = uHeight;
6594 pScreen->offVRAM = uScreenOffset;
6595 pScreen->cbPitch = cbPitch;
6596 pScreen->cBpp = 32;
6597 }
6598 else
6599 {
6600 /* Screen blanked. Keep old values. */
6601 }
6602
6603 pThis->svga.fGFBRegisters = false;
6604 vmsvgaR3ChangeMode(pThis, pThisCC);
6605
6606#ifdef VBOX_WITH_VMSVGA3D
6607 if (RT_LIKELY(pThis->svga.f3DEnabled))
6608 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6609#endif
6610}
6611
6612
6613/* SVGA_CMD_DESTROY_SCREEN */
6614void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6615{
6616 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6617
6618 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6619 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6620
6621 uint32_t const idScreen = pCmd->screenId;
6622 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6623 RT_UNTRUSTED_VALIDATED_FENCE();
6624
6625 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6626 pScreen->fModified = true;
6627 pScreen->fDefined = false;
6628 pScreen->idScreen = idScreen;
6629
6630#ifdef VBOX_WITH_VMSVGA3D
6631 if (RT_LIKELY(pThis->svga.f3DEnabled))
6632 vmsvga3dDestroyScreen(pThisCC, pScreen);
6633#endif
6634 vmsvgaR3ChangeMode(pThis, pThisCC);
6635}
6636
6637
6638/* SVGA_CMD_DEFINE_GMRFB */
6639void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6640{
6641 RT_NOREF(pThis);
6642 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6643
6644 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6645 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6646 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6647
6648 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6649 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6650 pSvgaR3State->GMRFB.format = pCmd->format;
6651}
6652
6653
6654/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6655void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6656{
6657 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6658
6659 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6660 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6661 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6662
6663 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6664 RT_UNTRUSTED_VALIDATED_FENCE();
6665
6666 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6667 AssertPtrReturnVoid(pScreen);
6668
6669 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6670 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6671
6672 /* Clip destRect to the screen dimensions. */
6673 SVGASignedRect screenRect;
6674 screenRect.left = 0;
6675 screenRect.top = 0;
6676 screenRect.right = pScreen->cWidth;
6677 screenRect.bottom = pScreen->cHeight;
6678 SVGASignedRect clipRect = pCmd->destRect;
6679 vmsvgaR3ClipRect(&screenRect, &clipRect);
6680 RT_UNTRUSTED_VALIDATED_FENCE();
6681
6682 uint32_t const width = clipRect.right - clipRect.left;
6683 uint32_t const height = clipRect.bottom - clipRect.top;
6684
6685 if ( width == 0
6686 || height == 0)
6687 return; /* Nothing to do. */
6688
6689 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6690 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6691
6692 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6693 * Prepare parameters for vmsvgaR3GmrTransfer.
6694 */
6695 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6696
6697 /* Destination: host buffer which describes the screen 0 VRAM.
6698 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6699 */
6700 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6701 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6702 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6703 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6704 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6705 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6706 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6707 + cbScanline * clipRect.top;
6708 int32_t const cbHstPitch = cbScanline;
6709
6710 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6711 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6712 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6713 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6714 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6715
6716 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6717 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6718 gstPtr, offGst, cbGstPitch,
6719 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6720 AssertRC(rc);
6721 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6722}
6723
6724
6725/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6726void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6727{
6728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6729
6730 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6731 /* Note! This can fetch 3d render results as well!! */
6732 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6733 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6734
6735 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6736 RT_UNTRUSTED_VALIDATED_FENCE();
6737
6738 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6739 AssertPtrReturnVoid(pScreen);
6740
6741 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6742 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6743
6744 /* Clip destRect to the screen dimensions. */
6745 SVGASignedRect screenRect;
6746 screenRect.left = 0;
6747 screenRect.top = 0;
6748 screenRect.right = pScreen->cWidth;
6749 screenRect.bottom = pScreen->cHeight;
6750 SVGASignedRect clipRect = pCmd->srcRect;
6751 vmsvgaR3ClipRect(&screenRect, &clipRect);
6752 RT_UNTRUSTED_VALIDATED_FENCE();
6753
6754 uint32_t const width = clipRect.right - clipRect.left;
6755 uint32_t const height = clipRect.bottom - clipRect.top;
6756
6757 if ( width == 0
6758 || height == 0)
6759 return; /* Nothing to do. */
6760
6761 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6762 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6763
6764 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6765 * Prepare parameters for vmsvgaR3GmrTransfer.
6766 */
6767 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6768
6769 /* Source: host buffer which describes the screen 0 VRAM.
6770 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6771 */
6772 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6773 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6774 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6775 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6776 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6777 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6778 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6779 + cbScanline * clipRect.top;
6780 int32_t const cbHstPitch = cbScanline;
6781
6782 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6783 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6784 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6785 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6786 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6787
6788 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6789 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6790 gstPtr, offGst, cbGstPitch,
6791 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6792 AssertRC(rc);
6793}
6794
6795
6796/* SVGA_CMD_ANNOTATION_FILL */
6797void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6798{
6799 RT_NOREF(pThis);
6800 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6801
6802 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6803 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6804
6805 pSvgaR3State->colorAnnotation = pCmd->color;
6806}
6807
6808
6809/* SVGA_CMD_ANNOTATION_COPY */
6810void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6811{
6812 RT_NOREF(pThis, pCmd);
6813 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6814
6815 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6816 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6817
6818 AssertFailed();
6819}
6820
6821
6822#ifdef VBOX_WITH_VMSVGA3D
6823/* SVGA_CMD_DEFINE_GMR2 */
6824void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6825{
6826 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6827
6828 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6829 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6830
6831 /* Validate current GMR id. */
6832 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6833 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6834 RT_UNTRUSTED_VALIDATED_FENCE();
6835
6836 if (!pCmd->numPages)
6837 {
6838 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6839 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6840 }
6841 else
6842 {
6843 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6844 if (pGMR->cMaxPages)
6845 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6846
6847 /* Not sure if we should always free the descriptor, but for simplicity
6848 we do so if the new size is smaller than the current. */
6849 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6850 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6851 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6852
6853 pGMR->cMaxPages = pCmd->numPages;
6854 /* The rest is done by the REMAP_GMR2 command. */
6855 }
6856}
6857
6858
6859/* SVGA_CMD_REMAP_GMR2 */
6860void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6861{
6862 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6863
6864 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6865 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6866
6867 /* Validate current GMR id and size. */
6868 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6869 RT_UNTRUSTED_VALIDATED_FENCE();
6870 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6871 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6872 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6873 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6874
6875 if (pCmd->numPages == 0)
6876 return;
6877 RT_UNTRUSTED_VALIDATED_FENCE();
6878
6879 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6880 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6881
6882 /*
6883 * We flatten the existing descriptors into a page array, overwrite the
6884 * pages specified in this command and then recompress the descriptor.
6885 */
6886 /** @todo Optimize the GMR remap algorithm! */
6887
6888 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6889 uint64_t *paNewPage64 = NULL;
6890 if (pGMR->paDesc)
6891 {
6892 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6893
6894 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6895 AssertPtrReturnVoid(paNewPage64);
6896
6897 uint32_t idxPage = 0;
6898 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6899 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6900 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6901 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6902 RT_UNTRUSTED_VALIDATED_FENCE();
6903 }
6904
6905 /* Free the old GMR if present. */
6906 if (pGMR->paDesc)
6907 RTMemFree(pGMR->paDesc);
6908
6909 /* Allocate the maximum amount possible (everything non-continuous) */
6910 PVMSVGAGMRDESCRIPTOR paDescs;
6911 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6912 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6913
6914 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6915 {
6916 /** @todo */
6917 AssertFailed();
6918 pGMR->numDescriptors = 0;
6919 }
6920 else
6921 {
6922 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6923 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6924 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6925
6926 uint32_t cPages;
6927 if (paNewPage64)
6928 {
6929 /* Overwrite the old page array with the new page values. */
6930 if (fGCPhys64)
6931 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6932 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6933 else
6934 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6935 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6936
6937 /* Use the updated page array instead of the command data. */
6938 fGCPhys64 = true;
6939 paPages64 = paNewPage64;
6940 cPages = cNewTotalPages;
6941 }
6942 else
6943 cPages = pCmd->numPages;
6944
6945 /* The first page. */
6946 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6947 * applied to paNewPage64. */
6948 RTGCPHYS GCPhys;
6949 if (fGCPhys64)
6950 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6951 else
6952 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
6953 paDescs[0].GCPhys = GCPhys;
6954 paDescs[0].numPages = 1;
6955
6956 /* Subsequent pages. */
6957 uint32_t iDescriptor = 0;
6958 for (uint32_t i = 1; i < cPages; i++)
6959 {
6960 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6961 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6962 else
6963 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6964
6965 /* Continuous physical memory? */
6966 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6967 {
6968 Assert(paDescs[iDescriptor].numPages);
6969 paDescs[iDescriptor].numPages++;
6970 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6971 }
6972 else
6973 {
6974 iDescriptor++;
6975 paDescs[iDescriptor].GCPhys = GCPhys;
6976 paDescs[iDescriptor].numPages = 1;
6977 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6978 }
6979 }
6980
6981 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6982 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6983 pGMR->numDescriptors = iDescriptor + 1;
6984 }
6985
6986 if (paNewPage64)
6987 RTMemFree(paNewPage64);
6988}
6989
6990
6991/**
6992 * Free the specified GMR
6993 *
6994 * @param pThisCC The VGA/VMSVGA state for ring-3.
6995 * @param idGMR GMR id
6996 */
6997void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6998{
6999 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7000
7001 /* Free the old descriptor if present. */
7002 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7003 if ( pGMR->numDescriptors
7004 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7005 {
7006# ifdef DEBUG_GMR_ACCESS
7007 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7008# endif
7009
7010 Assert(pGMR->paDesc);
7011 RTMemFree(pGMR->paDesc);
7012 pGMR->paDesc = NULL;
7013 pGMR->numDescriptors = 0;
7014 pGMR->cbTotal = 0;
7015 pGMR->cMaxPages = 0;
7016 }
7017 Assert(!pGMR->cMaxPages);
7018 Assert(!pGMR->cbTotal);
7019}
7020#endif /* VBOX_WITH_VMSVGA3D */
7021
7022
7023/**
7024 * Copy between a GMR and a host memory buffer.
7025 *
7026 * @returns VBox status code.
7027 * @param pThis The shared VGA/VMSVGA instance data.
7028 * @param pThisCC The VGA/VMSVGA state for ring-3.
7029 * @param enmTransferType Transfer type (read/write)
7030 * @param pbHstBuf Host buffer pointer (valid)
7031 * @param cbHstBuf Size of host buffer (valid)
7032 * @param offHst Host buffer offset of the first scanline
7033 * @param cbHstPitch Destination buffer pitch
7034 * @param gstPtr GMR description
7035 * @param offGst Guest buffer offset of the first scanline
7036 * @param cbGstPitch Guest buffer pitch
7037 * @param cbWidth Width in bytes to copy
7038 * @param cHeight Number of scanllines to copy
7039 */
7040int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7041 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7042 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7043 uint32_t cbWidth, uint32_t cHeight)
7044{
7045 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7046 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7047 int rc;
7048
7049 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7050 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7051 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7052 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7053 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7054
7055 PGMR pGMR;
7056 uint32_t cbGmr; /* The GMR size in bytes. */
7057 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7058 {
7059 pGMR = NULL;
7060 cbGmr = pThis->vram_size;
7061 }
7062 else
7063 {
7064 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7065 RT_UNTRUSTED_VALIDATED_FENCE();
7066 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7067 cbGmr = pGMR->cbTotal;
7068 }
7069
7070 /*
7071 * GMR
7072 */
7073 /* Calculate GMR offset of the data to be copied. */
7074 AssertMsgReturn(gstPtr.offset < cbGmr,
7075 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7076 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7077 VERR_INVALID_PARAMETER);
7078 RT_UNTRUSTED_VALIDATED_FENCE();
7079 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7080 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7081 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7082 VERR_INVALID_PARAMETER);
7083 RT_UNTRUSTED_VALIDATED_FENCE();
7084 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7085
7086 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7087 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7088 AssertMsgReturn(cbGmrScanline != 0,
7089 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7090 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7091 VERR_INVALID_PARAMETER);
7092 RT_UNTRUSTED_VALIDATED_FENCE();
7093 AssertMsgReturn(cbWidth <= cbGmrScanline,
7094 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7095 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7096 VERR_INVALID_PARAMETER);
7097 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7098 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7099 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7100 VERR_INVALID_PARAMETER);
7101 RT_UNTRUSTED_VALIDATED_FENCE();
7102
7103 /* How many bytes are available for the data in the GMR. */
7104 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7105
7106 /* How many scanlines would fit into the available data. */
7107 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7108 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7109 if (cbWidth <= cbGmrLastScanline)
7110 ++cGmrScanlines;
7111
7112 if (cHeight > cGmrScanlines)
7113 cHeight = cGmrScanlines;
7114
7115 AssertMsgReturn(cHeight > 0,
7116 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7117 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7118 VERR_INVALID_PARAMETER);
7119 RT_UNTRUSTED_VALIDATED_FENCE();
7120
7121 /*
7122 * Host buffer.
7123 */
7124 AssertMsgReturn(offHst < cbHstBuf,
7125 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7126 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7127 VERR_INVALID_PARAMETER);
7128
7129 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7130 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7131 AssertMsgReturn(cbHstScanline != 0,
7132 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7133 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7134 VERR_INVALID_PARAMETER);
7135 AssertMsgReturn(cbWidth <= cbHstScanline,
7136 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7137 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7138 VERR_INVALID_PARAMETER);
7139 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7140 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7141 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7142 VERR_INVALID_PARAMETER);
7143
7144 /* How many bytes are available for the data in the buffer. */
7145 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7146
7147 /* How many scanlines would fit into the available data. */
7148 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7149 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7150 if (cbWidth <= cbHstLastScanline)
7151 ++cHstScanlines;
7152
7153 if (cHeight > cHstScanlines)
7154 cHeight = cHstScanlines;
7155
7156 AssertMsgReturn(cHeight > 0,
7157 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7158 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7159 VERR_INVALID_PARAMETER);
7160
7161 uint8_t *pbHst = pbHstBuf + offHst;
7162
7163 /* Shortcut for the framebuffer. */
7164 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7165 {
7166 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7167
7168 uint8_t const *pbSrc;
7169 int32_t cbSrcPitch;
7170 uint8_t *pbDst;
7171 int32_t cbDstPitch;
7172
7173 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7174 {
7175 pbSrc = pbHst;
7176 cbSrcPitch = cbHstPitch;
7177 pbDst = pbGst;
7178 cbDstPitch = cbGstPitch;
7179 }
7180 else
7181 {
7182 pbSrc = pbGst;
7183 cbSrcPitch = cbGstPitch;
7184 pbDst = pbHst;
7185 cbDstPitch = cbHstPitch;
7186 }
7187
7188 if ( cbWidth == (uint32_t)cbGstPitch
7189 && cbGstPitch == cbHstPitch)
7190 {
7191 /* Entire scanlines, positive pitch. */
7192 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7193 }
7194 else
7195 {
7196 for (uint32_t i = 0; i < cHeight; ++i)
7197 {
7198 memcpy(pbDst, pbSrc, cbWidth);
7199
7200 pbDst += cbDstPitch;
7201 pbSrc += cbSrcPitch;
7202 }
7203 }
7204 return VINF_SUCCESS;
7205 }
7206
7207 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7208 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7209
7210 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7211 uint32_t iDesc = 0; /* Index in the descriptor array. */
7212 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7213 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7214 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7215 for (uint32_t i = 0; i < cHeight; ++i)
7216 {
7217 uint32_t cbCurrentWidth = cbWidth;
7218 uint32_t offGmrCurrent = offGmrScanline;
7219 uint8_t *pbCurrentHost = pbHstScanline;
7220
7221 /* Find the right descriptor */
7222 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7223 {
7224 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7225 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7226 ++iDesc;
7227 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7228 }
7229
7230 while (cbCurrentWidth)
7231 {
7232 uint32_t cbToCopy;
7233
7234 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7235 cbToCopy = cbCurrentWidth;
7236 else
7237 {
7238 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7239 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7240 }
7241
7242 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7243
7244 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7245
7246 /*
7247 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7248 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7249 * see @bugref{9654#c75}.
7250 */
7251 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7252 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7253 else
7254 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7255 AssertRCBreak(rc);
7256
7257 cbCurrentWidth -= cbToCopy;
7258 offGmrCurrent += cbToCopy;
7259 pbCurrentHost += cbToCopy;
7260
7261 /* Go to the next descriptor if there's anything left. */
7262 if (cbCurrentWidth)
7263 {
7264 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7265 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7266 ++iDesc;
7267 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7268 }
7269 }
7270
7271 offGmrScanline += cbGstPitch;
7272 pbHstScanline += cbHstPitch;
7273 }
7274
7275 return VINF_SUCCESS;
7276}
7277
7278
7279/**
7280 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7281 *
7282 * @param pSizeSrc Source surface dimensions.
7283 * @param pSizeDest Destination surface dimensions.
7284 * @param pBox Coordinates to be clipped.
7285 */
7286void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7287{
7288 /* Src x, w */
7289 if (pBox->srcx > pSizeSrc->width)
7290 pBox->srcx = pSizeSrc->width;
7291 if (pBox->w > pSizeSrc->width - pBox->srcx)
7292 pBox->w = pSizeSrc->width - pBox->srcx;
7293
7294 /* Src y, h */
7295 if (pBox->srcy > pSizeSrc->height)
7296 pBox->srcy = pSizeSrc->height;
7297 if (pBox->h > pSizeSrc->height - pBox->srcy)
7298 pBox->h = pSizeSrc->height - pBox->srcy;
7299
7300 /* Src z, d */
7301 if (pBox->srcz > pSizeSrc->depth)
7302 pBox->srcz = pSizeSrc->depth;
7303 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7304 pBox->d = pSizeSrc->depth - pBox->srcz;
7305
7306 /* Dest x, w */
7307 if (pBox->x > pSizeDest->width)
7308 pBox->x = pSizeDest->width;
7309 if (pBox->w > pSizeDest->width - pBox->x)
7310 pBox->w = pSizeDest->width - pBox->x;
7311
7312 /* Dest y, h */
7313 if (pBox->y > pSizeDest->height)
7314 pBox->y = pSizeDest->height;
7315 if (pBox->h > pSizeDest->height - pBox->y)
7316 pBox->h = pSizeDest->height - pBox->y;
7317
7318 /* Dest z, d */
7319 if (pBox->z > pSizeDest->depth)
7320 pBox->z = pSizeDest->depth;
7321 if (pBox->d > pSizeDest->depth - pBox->z)
7322 pBox->d = pSizeDest->depth - pBox->z;
7323}
7324
7325
7326/**
7327 * Unsigned coordinates in pBox. Clip to [0; pSize).
7328 *
7329 * @param pSize Source surface dimensions.
7330 * @param pBox Coordinates to be clipped.
7331 */
7332void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7333{
7334 /* x, w */
7335 if (pBox->x > pSize->width)
7336 pBox->x = pSize->width;
7337 if (pBox->w > pSize->width - pBox->x)
7338 pBox->w = pSize->width - pBox->x;
7339
7340 /* y, h */
7341 if (pBox->y > pSize->height)
7342 pBox->y = pSize->height;
7343 if (pBox->h > pSize->height - pBox->y)
7344 pBox->h = pSize->height - pBox->y;
7345
7346 /* z, d */
7347 if (pBox->z > pSize->depth)
7348 pBox->z = pSize->depth;
7349 if (pBox->d > pSize->depth - pBox->z)
7350 pBox->d = pSize->depth - pBox->z;
7351}
7352
7353
7354/**
7355 * Clip.
7356 *
7357 * @param pBound Bounding rectangle.
7358 * @param pRect Rectangle to be clipped.
7359 */
7360void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7361{
7362 int32_t left;
7363 int32_t top;
7364 int32_t right;
7365 int32_t bottom;
7366
7367 /* Right order. */
7368 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7369 if (pRect->left < pRect->right)
7370 {
7371 left = pRect->left;
7372 right = pRect->right;
7373 }
7374 else
7375 {
7376 left = pRect->right;
7377 right = pRect->left;
7378 }
7379 if (pRect->top < pRect->bottom)
7380 {
7381 top = pRect->top;
7382 bottom = pRect->bottom;
7383 }
7384 else
7385 {
7386 top = pRect->bottom;
7387 bottom = pRect->top;
7388 }
7389
7390 if (left < pBound->left)
7391 left = pBound->left;
7392 if (right < pBound->left)
7393 right = pBound->left;
7394
7395 if (left > pBound->right)
7396 left = pBound->right;
7397 if (right > pBound->right)
7398 right = pBound->right;
7399
7400 if (top < pBound->top)
7401 top = pBound->top;
7402 if (bottom < pBound->top)
7403 bottom = pBound->top;
7404
7405 if (top > pBound->bottom)
7406 top = pBound->bottom;
7407 if (bottom > pBound->bottom)
7408 bottom = pBound->bottom;
7409
7410 pRect->left = left;
7411 pRect->right = right;
7412 pRect->top = top;
7413 pRect->bottom = bottom;
7414}
7415
7416
7417/**
7418 * Clip.
7419 *
7420 * @param pBound Bounding rectangle.
7421 * @param pRect Rectangle to be clipped.
7422 */
7423void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7424{
7425 uint32_t const leftBound = pBound->x;
7426 uint32_t const rightBound = pBound->x + pBound->w;
7427 uint32_t const topBound = pBound->y;
7428 uint32_t const bottomBound = pBound->y + pBound->h;
7429
7430 uint32_t x = pRect->x;
7431 uint32_t y = pRect->y;
7432 uint32_t w = pRect->w;
7433 uint32_t h = pRect->h;
7434
7435 /* Make sure that right and bottom coordinates can be safely computed. */
7436 if (x > rightBound)
7437 x = rightBound;
7438 if (w > rightBound - x)
7439 w = rightBound - x;
7440 if (y > bottomBound)
7441 y = bottomBound;
7442 if (h > bottomBound - y)
7443 h = bottomBound - y;
7444
7445 /* Switch from x, y, w, h to left, top, right, bottom. */
7446 uint32_t left = x;
7447 uint32_t right = x + w;
7448 uint32_t top = y;
7449 uint32_t bottom = y + h;
7450
7451 /* A standard left, right, bottom, top clipping. */
7452 if (left < leftBound)
7453 left = leftBound;
7454 if (right < leftBound)
7455 right = leftBound;
7456
7457 if (left > rightBound)
7458 left = rightBound;
7459 if (right > rightBound)
7460 right = rightBound;
7461
7462 if (top < topBound)
7463 top = topBound;
7464 if (bottom < topBound)
7465 bottom = topBound;
7466
7467 if (top > bottomBound)
7468 top = bottomBound;
7469 if (bottom > bottomBound)
7470 bottom = bottomBound;
7471
7472 /* Back to x, y, w, h representation. */
7473 pRect->x = left;
7474 pRect->y = top;
7475 pRect->w = right - left;
7476 pRect->h = bottom - top;
7477}
7478
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette