VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 94251

Last change on this file since 94251 was 94232, checked in by vboxsync, 3 years ago

Devices/Graphics: texture arrays: bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 273.5 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 94232 2022-03-15 08:47:10Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
818{
819 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
820 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
821}
822
823
824/*
825 *
826 * The guest's Memory OBjects (MOB).
827 *
828 */
829
830static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
831 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
832 bool fGCPhys64, PVMSVGAMOB pMob)
833{
834 RT_ZERO(*pMob);
835
836 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
837 SVGAOTableMobEntry entry;
838 entry.ptDepth = ptDepth;
839 entry.sizeInBytes = sizeInBytes;
840 entry.base = baseAddress;
841 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
842 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
843 if (RT_SUCCESS(rc))
844 {
845 /* Create the corresponding GBO. */
846 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
847 if (RT_SUCCESS(rc))
848 {
849 /* Add to the tree of known GBOs and the LRU list. */
850 pMob->Core.Key = mobid;
851 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
852 {
853 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
854 return VINF_SUCCESS;
855 }
856
857 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
858 }
859 }
860
861 return rc;
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
878 RTMemFree(pMob);
879 return VINF_SUCCESS;
880 }
881
882 return VERR_INVALID_PARAMETER;
883}
884
885
886PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
887{
888 if (mobid == SVGA_ID_INVALID)
889 return NULL;
890
891 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
892 if (pMob)
893 {
894 /* Move to the head of the LRU list. */
895 RTListNodeRemove(&pMob->nodeLRU);
896 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
897 }
898 else
899 ASSERT_GUEST_FAILED();
900
901 return pMob;
902}
903
904
905/** Create a host ring-3 pointer to the MOB data.
906 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
907 * @param pSvgaR3State R3 device state.
908 * @param pMob The MOB.
909 * @param cbValid How many bytes of the guest backing memory contain valid data.
910 * @return VBox status.
911 */
912/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
913int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
914{
915 AssertReturn(pMob, VERR_INVALID_PARAMETER);
916 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
917}
918
919
920void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
921{
922 if (pMob)
923 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
924}
925
926
927int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
928{
929 if (pMob)
930 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
931 return VERR_INVALID_PARAMETER;
932}
933
934
935int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
936{
937 if (pMob)
938 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
939 return VERR_INVALID_PARAMETER;
940}
941
942
943void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
944{
945 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
946 {
947 if (off <= pMob->Gbo.cbTotal)
948 return (uint8_t *)pMob->Gbo.pvHost + off;
949 }
950 return NULL;
951}
952
953
954int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
955{
956 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
957
958 SVGAOTableSurfaceEntry entrySurface;
959 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
960 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
961 if (RT_SUCCESS(rc))
962 {
963 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
964 if (pMob)
965 {
966 VMSVGA3D_MAPPED_SURFACE map;
967 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE, &map);
968 if (RT_SUCCESS(rc))
969 {
970 /* Copy MOB -> mapped surface. */
971 uint32_t offSrc = pBox->x * map.cbPixel
972 + pBox->y * entrySurface.size.width * map.cbPixel
973 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
974 uint8_t *pu8Dst = (uint8_t *)map.pvData;
975 for (uint32_t z = 0; z < pBox->d; ++z)
976 {
977 for (uint32_t y = 0; y < pBox->h; ++y)
978 {
979 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
980 if (RT_FAILURE(rc))
981 break;
982
983 pu8Dst += map.cbRowPitch;
984 offSrc += entrySurface.size.width * map.cbPixel;
985 }
986
987 pu8Dst += map.cbDepthPitch;
988 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
989 }
990
991 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
992 }
993 }
994 else
995 rc = VERR_INVALID_STATE;
996 }
997
998 return rc;
999}
1000
1001
1002int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
1003{
1004 /* pPtSrc must be verified by the caller. */
1005 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1006
1007 SVGAOTableSurfaceEntry entrySurface;
1008 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1009 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1010 if (RT_SUCCESS(rc))
1011 {
1012 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1013 if (pMob)
1014 {
1015 VMSVGA3D_MAPPED_SURFACE map;
1016 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE, &map);
1017 if (RT_SUCCESS(rc))
1018 {
1019 /* Copy MOB -> mapped surface. */
1020 uint32_t offSrc = pPtSrc->x * map.cbPixel
1021 + pPtSrc->y * entrySurface.size.width * map.cbPixel
1022 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1023 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1024 for (uint32_t z = 0; z < pBoxDst->d; ++z)
1025 {
1026 for (uint32_t y = 0; y < pBoxDst->h; ++y)
1027 {
1028 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1029 if (RT_FAILURE(rc))
1030 break;
1031
1032 pu8Dst += map.cbRowPitch;
1033 offSrc += entrySurface.size.width * map.cbPixel;
1034 }
1035
1036 pu8Dst += map.cbDepthPitch;
1037 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1038 }
1039
1040 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1041 }
1042 }
1043 else
1044 rc = VERR_INVALID_STATE;
1045 }
1046
1047 return rc;
1048}
1049
1050#endif /* VBOX_WITH_VMSVGA3D */
1051
1052/*
1053 * Screen objects.
1054 */
1055VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1056{
1057 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1058 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1059 && pSVGAState
1060 && pSVGAState->aScreens[idScreen].fDefined)
1061 {
1062 return &pSVGAState->aScreens[idScreen];
1063 }
1064 return NULL;
1065}
1066
1067void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1068{
1069#ifdef VBOX_WITH_VMSVGA3D
1070 if (pThis->svga.f3DEnabled)
1071 {
1072 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1073 {
1074 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1075 if (pScreen)
1076 vmsvga3dDestroyScreen(pThisCC, pScreen);
1077 }
1078 }
1079#else
1080 RT_NOREF(pThis, pThisCC);
1081#endif
1082}
1083
1084
1085/**
1086 * Copy a rectangle of pixels within guest VRAM.
1087 */
1088static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1089 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1090{
1091 if (!width || !height)
1092 return; /* Nothing to do, don't even bother. */
1093
1094 /*
1095 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1096 * corresponding to the current display mode.
1097 */
1098 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1099 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1100 uint8_t const *pSrc;
1101 uint8_t *pDst;
1102 unsigned const cbRectWidth = width * cbPixel;
1103 unsigned uMaxOffset;
1104
1105 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1106 if (uMaxOffset >= cbFrameBuffer)
1107 {
1108 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1109 return; /* Just don't listen to a bad guest. */
1110 }
1111
1112 pSrc = pDst = pThisCC->pbVRam;
1113 pSrc += srcY * cbScanline + srcX * cbPixel;
1114 pDst += dstY * cbScanline + dstX * cbPixel;
1115
1116 if (srcY >= dstY)
1117 {
1118 /* Source below destination, copy top to bottom. */
1119 for (; height > 0; height--)
1120 {
1121 memmove(pDst, pSrc, cbRectWidth);
1122 pSrc += cbScanline;
1123 pDst += cbScanline;
1124 }
1125 }
1126 else
1127 {
1128 /* Source above destination, copy bottom to top. */
1129 pSrc += cbScanline * (height - 1);
1130 pDst += cbScanline * (height - 1);
1131 for (; height > 0; height--)
1132 {
1133 memmove(pDst, pSrc, cbRectWidth);
1134 pSrc -= cbScanline;
1135 pDst -= cbScanline;
1136 }
1137 }
1138}
1139
1140
1141/**
1142 * Common worker for changing the pointer shape.
1143 *
1144 * @param pThisCC The VGA/VMSVGA state for ring-3.
1145 * @param pSVGAState The VMSVGA ring-3 instance data.
1146 * @param fAlpha Whether there is alpha or not.
1147 * @param xHot Hotspot x coordinate.
1148 * @param yHot Hotspot y coordinate.
1149 * @param cx Width.
1150 * @param cy Height.
1151 * @param pbData Heap copy of the cursor data. Consumed.
1152 * @param cbData The size of the data.
1153 */
1154static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1155 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1156{
1157 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1158#ifdef LOG_ENABLED
1159 if (LogIs2Enabled())
1160 {
1161 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1162 if (!fAlpha)
1163 {
1164 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1165 for (uint32_t y = 0; y < cy; y++)
1166 {
1167 Log2(("%3u:", y));
1168 uint8_t const *pbLine = &pbData[y * cbAndLine];
1169 for (uint32_t x = 0; x < cx; x += 8)
1170 {
1171 uint8_t b = pbLine[x / 8];
1172 char szByte[12];
1173 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1174 szByte[1] = b & 0x40 ? '*' : ' ';
1175 szByte[2] = b & 0x20 ? '*' : ' ';
1176 szByte[3] = b & 0x10 ? '*' : ' ';
1177 szByte[4] = b & 0x08 ? '*' : ' ';
1178 szByte[5] = b & 0x04 ? '*' : ' ';
1179 szByte[6] = b & 0x02 ? '*' : ' ';
1180 szByte[7] = b & 0x01 ? '*' : ' ';
1181 szByte[8] = '\0';
1182 Log2(("%s", szByte));
1183 }
1184 Log2(("\n"));
1185 }
1186 }
1187
1188 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1189 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1190 for (uint32_t y = 0; y < cy; y++)
1191 {
1192 Log2(("%3u:", y));
1193 uint32_t const *pu32Line = &pu32Xor[y * cx];
1194 for (uint32_t x = 0; x < cx; x++)
1195 Log2((" %08x", pu32Line[x]));
1196 Log2(("\n"));
1197 }
1198 }
1199#endif
1200
1201 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1202 AssertRC(rc);
1203
1204 if (pSVGAState->Cursor.fActive)
1205 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1206
1207 pSVGAState->Cursor.fActive = true;
1208 pSVGAState->Cursor.xHotspot = xHot;
1209 pSVGAState->Cursor.yHotspot = yHot;
1210 pSVGAState->Cursor.width = cx;
1211 pSVGAState->Cursor.height = cy;
1212 pSVGAState->Cursor.cbData = cbData;
1213 pSVGAState->Cursor.pData = pbData;
1214}
1215
1216
1217#ifdef VBOX_WITH_VMSVGA3D
1218
1219/*
1220 * SVGA_3D_CMD_* handlers.
1221 */
1222
1223
1224/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1225 *
1226 * @param pThisCC The VGA/VMSVGA state for the current context.
1227 * @param pCmd The VMSVGA command.
1228 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1229 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1230 */
1231static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1232 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1233{
1234 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1235 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1236 RT_UNTRUSTED_VALIDATED_FENCE();
1237
1238 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1239 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1240 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1241 */
1242 uint32_t cRemainingMipLevels = cMipLevelSizes;
1243 uint32_t cFaces = 0;
1244 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1245 {
1246 if (pCmd->face[i].numMipLevels == 0)
1247 break;
1248
1249 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1250 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1251
1252 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1253 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1254 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1255
1256 ++cFaces;
1257 }
1258 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1259 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1260
1261 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1262 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1263
1264 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1265 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1266 RT_UNTRUSTED_VALIDATED_FENCE();
1267
1268 /* Verify paMipLevelSizes */
1269 uint32_t cWidth = paMipLevelSizes[0].width;
1270 uint32_t cHeight = paMipLevelSizes[0].height;
1271 uint32_t cDepth = paMipLevelSizes[0].depth;
1272 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1273 {
1274 cWidth >>= 1;
1275 if (cWidth == 0) cWidth = 1;
1276 cHeight >>= 1;
1277 if (cHeight == 0) cHeight = 1;
1278 cDepth >>= 1;
1279 if (cDepth == 0) cDepth = 1;
1280 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1281 {
1282 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1283 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1284 && cHeight == paMipLevelSizes[iMipLevelSize].height
1285 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1286 }
1287 }
1288 RT_UNTRUSTED_VALIDATED_FENCE();
1289
1290 /* Create the surface. */
1291 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1292 pCmd->multisampleCount, pCmd->autogenFilter,
1293 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* fAllocMipLevels = */ true);
1294}
1295
1296
1297/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1298static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1299{
1300 DEBUG_BREAKPOINT_TEST();
1301 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1302
1303 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1304
1305 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1306 /* Allocate a structure for the MOB. */
1307 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1308 AssertPtrReturnVoid(pMob);
1309
1310 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1311 if (RT_SUCCESS(rc))
1312 {
1313 return;
1314 }
1315
1316 AssertFailed();
1317
1318 RTMemFree(pMob);
1319}
1320
1321
1322/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1323static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1324{
1325 //DEBUG_BREAKPOINT_TEST();
1326 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1327
1328 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1329
1330 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1331 if (RT_SUCCESS(rc))
1332 {
1333 return;
1334 }
1335
1336 AssertFailed();
1337}
1338
1339
1340/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1341static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1342{
1343 //DEBUG_BREAKPOINT_TEST();
1344 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1345
1346 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1347 SVGAOTableSurfaceEntry entry;
1348 RT_ZERO(entry);
1349 entry.format = pCmd->format;
1350 entry.surface1Flags = pCmd->surfaceFlags;
1351 entry.numMipLevels = pCmd->numMipLevels;
1352 entry.multisampleCount = pCmd->multisampleCount;
1353 entry.autogenFilter = pCmd->autogenFilter;
1354 entry.size = pCmd->size;
1355 entry.mobid = SVGA_ID_INVALID;
1356 // entry.arraySize = 0;
1357 // entry.mobPitch = 0;
1358 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1359 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1360 if (RT_SUCCESS(rc))
1361 {
1362 /* Create the host surface. */
1363 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1364 pCmd->multisampleCount, pCmd->autogenFilter,
1365 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* fAllocMipLevels = */ false);
1366 }
1367}
1368
1369
1370/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1371static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1372{
1373 //DEBUG_BREAKPOINT_TEST();
1374 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1375
1376 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1377 SVGAOTableSurfaceEntry entry;
1378 RT_ZERO(entry);
1379 entry.mobid = SVGA_ID_INVALID;
1380 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1381 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1382
1383 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1384}
1385
1386
1387/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1388static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1389{
1390 //DEBUG_BREAKPOINT_TEST();
1391 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1392
1393 /* Assign the mobid to the surface. */
1394 int rc = VINF_SUCCESS;
1395 if (pCmd->mobid != SVGA_ID_INVALID)
1396 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1397 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1398 if (RT_SUCCESS(rc))
1399 {
1400 SVGAOTableSurfaceEntry entry;
1401 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1402 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1403 if (RT_SUCCESS(rc))
1404 {
1405 entry.mobid = pCmd->mobid;
1406 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1407 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1408 if (RT_SUCCESS(rc))
1409 {
1410 /* */
1411 }
1412 }
1413 }
1414}
1415
1416
1417typedef union
1418{
1419 float f;
1420 uint32_t u;
1421} Unsigned2Float;
1422
1423float float16ToFloat(uint16_t f16)
1424{
1425 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1426 uint16_t const f = f16 & 0x3FF;
1427 uint16_t const e = (f16 >> 10) & 0x1F;
1428 uint16_t const s = (f16 >> 15) & 0x1;
1429 Unsigned2Float u2f;
1430
1431 if (e == 0)
1432 {
1433 if (f == 0)
1434 {
1435 /* zero, -0 */
1436 u2f.u = (s << 31) | (0 << 23) | 0;
1437 return u2f.f;
1438 }
1439
1440 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1441 float const k = 1.0f / 16384.0f; /* 2^-14 */
1442 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1443 }
1444
1445 if (e == 31)
1446 {
1447 if (f == 0)
1448 {
1449 /* +-infinity */
1450 u2f.u = (s << 31) | (0xFF << 23) | 0;
1451 return u2f.f;
1452 }
1453
1454 /* NaN */
1455 u2f.u = (s << 31) | (0xFF << 23) | 1;
1456 return u2f.f;
1457 }
1458
1459 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1460 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1461 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1462 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1463 return u2f.f;
1464}
1465
1466
1467static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1468{
1469 if (pMap->cbPixel != 4 && pMap->format != SVGA3D_R16G16B16A16_FLOAT)
1470 return VERR_NOT_SUPPORTED;
1471
1472 int const w = pMap->box.w;
1473 int const h = pMap->box.h;
1474
1475 const int cbBitmap = w * h * 4;
1476
1477 FILE *f = fopen(pszFilename, "wb");
1478 if (!f)
1479 return VERR_FILE_NOT_FOUND;
1480
1481 {
1482 BMPFILEHDR fileHdr;
1483 RT_ZERO(fileHdr);
1484 fileHdr.uType = BMP_HDR_MAGIC;
1485 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1486 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1487
1488 BMPWIN3XINFOHDR coreHdr;
1489 RT_ZERO(coreHdr);
1490 coreHdr.cbSize = sizeof(coreHdr);
1491 coreHdr.uWidth = w;
1492 coreHdr.uHeight = -h;
1493 coreHdr.cPlanes = 1;
1494 coreHdr.cBits = 32;
1495 coreHdr.cbSizeImage = cbBitmap;
1496
1497 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1498 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1499 }
1500
1501 if (pMap->cbPixel == 4)
1502 {
1503 const uint8_t *s = (uint8_t *)pMap->pvData;
1504 for (int32_t y = 0; y < h; ++y)
1505 {
1506 fwrite(s, 1, w * pMap->cbPixel, f);
1507
1508 s += pMap->cbRowPitch;
1509 }
1510 }
1511 else if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1512 {
1513 const uint8_t *s = (uint8_t *)pMap->pvData;
1514 for (int32_t y = 0; y < h; ++y)
1515 {
1516 for (int32_t x = 0; x < w; ++x)
1517 {
1518 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1519 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1520 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1521 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1522 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1523 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1524 fwrite(&u32Pixel, 1, 4, f);
1525 }
1526
1527 s += pMap->cbRowPitch;
1528 }
1529 }
1530
1531 fclose(f);
1532
1533 return VINF_SUCCESS;
1534}
1535
1536
1537void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1538{
1539 static int idxBitmap = 0;
1540 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1541 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1542 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1543 RTStrFree(pszFilename);
1544}
1545
1546
1547static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1548 PVMSVGAMOB pMob,
1549 SVGA3dSurfaceImageId const *pImage,
1550 SVGA3dBox const *pBox,
1551 SVGA3dTransferType enmTransfer)
1552{
1553 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1554
1555 VMSVGA3D_SURFACE_MAP enmMapType;
1556 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1557 enmMapType = pBox
1558 ? VMSVGA3D_SURFACE_MAP_WRITE
1559 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1560 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1561 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1562 else
1563 AssertFailedReturn(VERR_INVALID_PARAMETER);
1564
1565 VMSGA3D_BOX_DIMENSIONS dims;
1566 int rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1567 AssertRCReturn(rc, rc);
1568
1569 VMSVGA3D_MAPPED_SURFACE map;
1570 rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1571 if (RT_SUCCESS(rc))
1572 {
1573 /* Copy mapped surface <-> MOB. */
1574 uint8_t *pu8Map = (uint8_t *)map.pvData;
1575 uint32_t offMob = dims.offSubresource + dims.offBox;
1576 for (uint32_t z = 0; z < dims.cDepth; ++z)
1577 {
1578 for (uint32_t y = 0; y < dims.cyBlocks; ++y)
1579 {
1580 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1581 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1582 else
1583 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1584 AssertRCBreak(rc);
1585
1586 pu8Map += map.cbRowPitch;
1587 offMob += dims.cbPitch;
1588 }
1589 /** @todo Take into account map.cbDepthPitch */
1590 }
1591
1592 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1593
1594 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1595 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1596 }
1597
1598 return rc;
1599}
1600
1601
1602/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1603static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1604{
1605 //DEBUG_BREAKPOINT_TEST();
1606 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1607
1608 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1609 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1610
1611/*
1612 SVGA3dSurfaceFormat format;
1613 SVGA3dSurface1Flags surface1Flags;
1614 uint32 numMipLevels;
1615 uint32 multisampleCount;
1616 SVGA3dTextureFilter autogenFilter;
1617 SVGA3dSize size;
1618 SVGAMobId mobid;
1619 uint32 arraySize;
1620 uint32 mobPitch;
1621 SVGA3dSurface2Flags surface2Flags;
1622 uint8 multisamplePattern;
1623 uint8 qualityLevel;
1624 uint16 bufferByteStride;
1625 float minLOD;
1626*/
1627
1628 /* "update a surface from its backing MOB." */
1629 SVGAOTableSurfaceEntry entrySurface;
1630 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1631 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1632 if (RT_SUCCESS(rc))
1633 {
1634 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1635 if (pMob)
1636 {
1637 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1638 AssertRC(rc);
1639 }
1640 }
1641}
1642
1643
1644/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1645static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1646{
1647 //DEBUG_BREAKPOINT_TEST();
1648 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1649
1650 LogFlowFunc(("sid=%u\n",
1651 pCmd->sid));
1652
1653 /* "update a surface from its backing MOB." */
1654 SVGAOTableSurfaceEntry entrySurface;
1655 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1656 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1657 if (RT_SUCCESS(rc))
1658 {
1659 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1660 if (pMob)
1661 {
1662 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1663 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1664 {
1665 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1666 {
1667 SVGA3dSurfaceImageId image;
1668 image.sid = pCmd->sid;
1669 image.face = iArray;
1670 image.mipmap = iMipmap;
1671
1672 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1673 AssertRCBreak(rc);
1674 }
1675 }
1676 }
1677 }
1678}
1679
1680
1681/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1682static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1683{
1684 //DEBUG_BREAKPOINT_TEST();
1685 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1686
1687 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1688 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1689
1690 /* Read a surface to its backing MOB. */
1691 SVGAOTableSurfaceEntry entrySurface;
1692 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1693 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1694 if (RT_SUCCESS(rc))
1695 {
1696 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1697 if (pMob)
1698 {
1699 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1700 AssertRC(rc);
1701 }
1702 }
1703}
1704
1705
1706/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1707static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1708{
1709 //DEBUG_BREAKPOINT_TEST();
1710 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1711
1712 LogFlowFunc(("sid=%u\n",
1713 pCmd->sid));
1714
1715 /* Read a surface to its backing MOB. */
1716 SVGAOTableSurfaceEntry entrySurface;
1717 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1718 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1719 if (RT_SUCCESS(rc))
1720 {
1721 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1722 if (pMob)
1723 {
1724 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1725 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1726 {
1727 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1728 {
1729 SVGA3dSurfaceImageId image;
1730 image.sid = pCmd->sid;
1731 image.face = iArray;
1732 image.mipmap = iMipmap;
1733
1734 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1735 AssertRCBreak(rc);
1736 }
1737 }
1738 }
1739 }
1740}
1741
1742
1743/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1744static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1745{
1746 //DEBUG_BREAKPOINT_TEST();
1747 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1748}
1749
1750
1751/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1752static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1753{
1754 //DEBUG_BREAKPOINT_TEST();
1755 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1756}
1757
1758
1759/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1760static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1761{
1762 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1763
1764 /*
1765 * Create a GBO for the table.
1766 */
1767 PVMSVGAGBO pGbo;
1768 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1769 {
1770 RT_UNTRUSTED_VALIDATED_FENCE();
1771 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1772 }
1773 else
1774 {
1775 ASSERT_GUEST_FAILED();
1776 pGbo = NULL;
1777 }
1778
1779 if (pGbo)
1780 {
1781 /* Recreate. */
1782 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1783 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1784 AssertRC(rc);
1785 }
1786}
1787
1788
1789/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1790static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1791{
1792 //DEBUG_BREAKPOINT_TEST();
1793 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1794
1795 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1796 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1797 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1798 RT_UNTRUSTED_VALIDATED_FENCE();
1799
1800 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1801 SVGAOTableScreenTargetEntry entry;
1802 RT_ZERO(entry);
1803 entry.image.sid = SVGA_ID_INVALID;
1804 // entry.image.face = 0;
1805 // entry.image.mipmap = 0;
1806 entry.width = pCmd->width;
1807 entry.height = pCmd->height;
1808 entry.xRoot = pCmd->xRoot;
1809 entry.yRoot = pCmd->yRoot;
1810 entry.flags = pCmd->flags;
1811 entry.dpi = pCmd->dpi;
1812
1813 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1814 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1815 if (RT_SUCCESS(rc))
1816 {
1817 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1818 /** @todo Generic screen object/target interface. */
1819 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1820 pScreen->fDefined = true;
1821 pScreen->fModified = true;
1822 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1823 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1824 pScreen->idScreen = pCmd->stid;
1825
1826 pScreen->xOrigin = pCmd->xRoot;
1827 pScreen->yOrigin = pCmd->yRoot;
1828 pScreen->cWidth = pCmd->width;
1829 pScreen->cHeight = pCmd->height;
1830 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1831 pScreen->cbPitch = pCmd->width * 4;
1832 pScreen->cBpp = 32;
1833
1834 if (RT_LIKELY(pThis->svga.f3DEnabled))
1835 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1836
1837 if (!pScreen->pHwScreen)
1838 {
1839 /* System memory buffer. */
1840 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1841 }
1842
1843 pThis->svga.fGFBRegisters = false;
1844 vmsvgaR3ChangeMode(pThis, pThisCC);
1845 }
1846}
1847
1848
1849/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1850static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1851{
1852 //DEBUG_BREAKPOINT_TEST();
1853 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1854
1855 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1856 RT_UNTRUSTED_VALIDATED_FENCE();
1857
1858 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1859 SVGAOTableScreenTargetEntry entry;
1860 RT_ZERO(entry);
1861 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1862 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1863 if (RT_SUCCESS(rc))
1864 {
1865 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1866 /** @todo Generic screen object/target interface. */
1867 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1868 pScreen->fModified = true;
1869 pScreen->fDefined = false;
1870 pScreen->idScreen = pCmd->stid;
1871
1872 if (RT_LIKELY(pThis->svga.f3DEnabled))
1873 vmsvga3dDestroyScreen(pThisCC, pScreen);
1874
1875 vmsvgaR3ChangeMode(pThis, pThisCC);
1876
1877 RTMemFree(pScreen->pvScreenBitmap);
1878 pScreen->pvScreenBitmap = NULL;
1879 }
1880}
1881
1882
1883/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1884static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1885{
1886 //DEBUG_BREAKPOINT_TEST();
1887 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1888
1889 /* "Binding a surface to a Screen Target the same as flipping" */
1890
1891 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1892 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1893 RT_UNTRUSTED_VALIDATED_FENCE();
1894
1895 /* Assign the surface to the screen target. */
1896 int rc = VINF_SUCCESS;
1897 if (pCmd->image.sid != SVGA_ID_INVALID)
1898 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1899 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1900 if (RT_SUCCESS(rc))
1901 {
1902 SVGAOTableScreenTargetEntry entry;
1903 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1904 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1905 if (RT_SUCCESS(rc))
1906 {
1907 entry.image = pCmd->image;
1908 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1909 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1910 if (RT_SUCCESS(rc))
1911 {
1912 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1913 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1914 AssertRC(rc);
1915 }
1916 }
1917 }
1918}
1919
1920
1921/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1922static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1923{
1924 //DEBUG_BREAKPOINT_TEST();
1925 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1926
1927 /* Update the screen target from its backing surface. */
1928 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1929 RT_UNTRUSTED_VALIDATED_FENCE();
1930
1931 /* Get the screen target info. */
1932 SVGAOTableScreenTargetEntry entryScreenTarget;
1933 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1934 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1935 if (RT_SUCCESS(rc))
1936 {
1937 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1938 RT_UNTRUSTED_VALIDATED_FENCE();
1939
1940 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1941 {
1942 SVGAOTableSurfaceEntry entrySurface;
1943 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1944 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1945 if (RT_SUCCESS(rc))
1946 {
1947 /* Copy entrySurface.mobid content to the screen target. */
1948 if (entrySurface.mobid != SVGA_ID_INVALID)
1949 {
1950 RT_UNTRUSTED_VALIDATED_FENCE();
1951 SVGA3dRect targetRect = pCmd->rect;
1952
1953 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1954 if (pScreen->pHwScreen)
1955 {
1956 /* Copy the screen target surface to the backend's screen. */
1957 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1958 }
1959 else if (pScreen->pvScreenBitmap)
1960 {
1961 /* Copy the screen target surface to the memory buffer. */
1962 VMSVGA3D_MAPPED_SURFACE map;
1963 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1964 if (RT_SUCCESS(rc))
1965 {
1966 uint8_t const *pu8Src = (uint8_t *)map.pvData
1967 + targetRect.x * map.cbPixel
1968 + targetRect.y * map.cbRowPitch;
1969 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1970 + targetRect.x * map.cbPixel
1971 + targetRect.y * map.box.w * map.cbPixel;
1972 for (uint32_t y = 0; y < targetRect.h; ++y)
1973 {
1974 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1975
1976 pu8Src += map.cbRowPitch;
1977 pu8Dst += map.box.w * map.cbPixel;
1978 }
1979
1980 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1981
1982 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1983 }
1984 else
1985 AssertFailed();
1986 }
1987 }
1988 }
1989 }
1990 }
1991}
1992
1993
1994/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1995static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1996{
1997 //DEBUG_BREAKPOINT_TEST();
1998 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1999
2000 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
2001 SVGAOTableSurfaceEntry entry;
2002 RT_ZERO(entry);
2003 entry.format = pCmd->format;
2004 entry.surface1Flags = pCmd->surfaceFlags;
2005 entry.numMipLevels = pCmd->numMipLevels;
2006 entry.multisampleCount = pCmd->multisampleCount;
2007 entry.autogenFilter = pCmd->autogenFilter;
2008 entry.size = pCmd->size;
2009 entry.mobid = SVGA_ID_INVALID;
2010 entry.arraySize = pCmd->arraySize;
2011 // entry.mobPitch = 0;
2012 // ...
2013
2014 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2015 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
2016 if (RT_SUCCESS(rc))
2017 {
2018 /* Create the host surface. */
2019 /** @todo SVGAOTableSurfaceEntry as input parameter? */
2020 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
2021 pCmd->multisampleCount, pCmd->autogenFilter,
2022 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* fAllocMipLevels = */ false);
2023 }
2024}
2025
2026
2027/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
2028static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
2029{
2030 //DEBUG_BREAKPOINT_TEST();
2031 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2032
2033 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
2034
2035 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
2036 /* Allocate a structure for the MOB. */
2037 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
2038 AssertPtrReturnVoid(pMob);
2039
2040 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
2041 if (RT_SUCCESS(rc))
2042 {
2043 return;
2044 }
2045
2046 RTMemFree(pMob);
2047}
2048
2049
2050/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
2051static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
2052{
2053#ifdef VMSVGA3D_DX
2054 //DEBUG_BREAKPOINT_TEST();
2055 RT_NOREF(cbCmd);
2056
2057 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2058
2059 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2060 SVGAOTableDXContextEntry entry;
2061 RT_ZERO(entry);
2062 entry.cid = pCmd->cid;
2063 entry.mobid = SVGA_ID_INVALID;
2064 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2065 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2066 if (RT_SUCCESS(rc))
2067 {
2068 /* Create the host context. */
2069 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2070 }
2071
2072 return rc;
2073#else
2074 RT_NOREF(pThisCC, pCmd, cbCmd);
2075 return VERR_NOT_SUPPORTED;
2076#endif
2077}
2078
2079
2080/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2081static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2082{
2083#ifdef VMSVGA3D_DX
2084 //DEBUG_BREAKPOINT_TEST();
2085 RT_NOREF(cbCmd);
2086
2087 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2088
2089 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2090 SVGAOTableDXContextEntry entry;
2091 RT_ZERO(entry);
2092 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2093 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2094
2095 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2096#else
2097 RT_NOREF(pThisCC, pCmd, cbCmd);
2098 return VERR_NOT_SUPPORTED;
2099#endif
2100}
2101
2102
2103/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2104static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2105{
2106#ifdef VMSVGA3D_DX
2107 //DEBUG_BREAKPOINT_TEST();
2108 RT_NOREF(cbCmd);
2109
2110 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2111
2112 /* Assign a mobid to a cid. */
2113 int rc = VINF_SUCCESS;
2114 if (pCmd->mobid != SVGA_ID_INVALID)
2115 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2116 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2117 if (RT_SUCCESS(rc))
2118 {
2119 SVGAOTableDXContextEntry entry;
2120 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2121 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2122 if (RT_SUCCESS(rc))
2123 {
2124 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2125 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2126 {
2127 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2128 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2129 if (pSvgaDXContext)
2130 {
2131 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2132 if (RT_SUCCESS(rc))
2133 {
2134 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2135 if (pMob)
2136 {
2137 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2138 }
2139 }
2140
2141 RTMemFree(pSvgaDXContext);
2142 pSvgaDXContext = NULL;
2143 }
2144 }
2145
2146 if (pCmd->mobid != SVGA_ID_INVALID)
2147 {
2148 /* Bind a new context. Copy existing data from the guest backing memory. */
2149 if (pCmd->validContents)
2150 {
2151 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2152 if (pMob)
2153 {
2154 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2155 if (pSvgaDXContext)
2156 {
2157 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2158 if (RT_FAILURE(rc))
2159 {
2160 RTMemFree(pSvgaDXContext);
2161 pSvgaDXContext = NULL;
2162 }
2163 }
2164 }
2165 }
2166
2167 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2168
2169 RTMemFree(pSvgaDXContext);
2170 }
2171
2172 /* Update the object table. */
2173 entry.mobid = pCmd->mobid;
2174 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2175 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2176 }
2177 }
2178
2179 return rc;
2180#else
2181 RT_NOREF(pThisCC, pCmd, cbCmd);
2182 return VERR_NOT_SUPPORTED;
2183#endif
2184}
2185
2186
2187/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2188static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2189{
2190#ifdef VMSVGA3D_DX
2191 //DEBUG_BREAKPOINT_TEST();
2192 RT_NOREF(cbCmd);
2193
2194 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2195
2196 /* "Request that the device flush the contents back into guest memory." */
2197 SVGAOTableDXContextEntry entry;
2198 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2199 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2200 if (RT_SUCCESS(rc))
2201 {
2202 if (entry.mobid != SVGA_ID_INVALID)
2203 {
2204 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2205 if (pMob)
2206 {
2207 /* Get the content. */
2208 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2209 if (pSvgaDXContext)
2210 {
2211 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2212 if (RT_SUCCESS(rc))
2213 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2214
2215 RTMemFree(pSvgaDXContext);
2216 }
2217 else
2218 rc = VERR_NO_MEMORY;
2219 }
2220 }
2221 }
2222
2223 return rc;
2224#else
2225 RT_NOREF(pThisCC, pCmd, cbCmd);
2226 return VERR_NOT_SUPPORTED;
2227#endif
2228}
2229
2230
2231/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2232static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2233{
2234#ifdef VMSVGA3D_DX
2235 DEBUG_BREAKPOINT_TEST();
2236 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2237 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2238 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2239#else
2240 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2241 return VERR_NOT_SUPPORTED;
2242#endif
2243}
2244
2245
2246/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2247static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2248{
2249#ifdef VMSVGA3D_DX
2250 //DEBUG_BREAKPOINT_TEST();
2251 RT_NOREF(cbCmd);
2252 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2253#else
2254 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2255 return VERR_NOT_SUPPORTED;
2256#endif
2257}
2258
2259
2260/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2261static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2262{
2263#ifdef VMSVGA3D_DX
2264 //DEBUG_BREAKPOINT_TEST();
2265 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2266 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2267 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2268#else
2269 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2270 return VERR_NOT_SUPPORTED;
2271#endif
2272}
2273
2274
2275/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2276static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2277{
2278#ifdef VMSVGA3D_DX
2279 //DEBUG_BREAKPOINT_TEST();
2280 RT_NOREF(cbCmd);
2281 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2282#else
2283 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2284 return VERR_NOT_SUPPORTED;
2285#endif
2286}
2287
2288
2289/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2290static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2291{
2292#ifdef VMSVGA3D_DX
2293 //DEBUG_BREAKPOINT_TEST();
2294 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2295 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2296 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2297#else
2298 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2299 return VERR_NOT_SUPPORTED;
2300#endif
2301}
2302
2303
2304/* SVGA_3D_CMD_DX_DRAW 1152 */
2305static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2306{
2307#ifdef VMSVGA3D_DX
2308 //DEBUG_BREAKPOINT_TEST();
2309 RT_NOREF(cbCmd);
2310 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2311#else
2312 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2313 return VERR_NOT_SUPPORTED;
2314#endif
2315}
2316
2317
2318/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2319static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2320{
2321#ifdef VMSVGA3D_DX
2322 //DEBUG_BREAKPOINT_TEST();
2323 RT_NOREF(cbCmd);
2324 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2325#else
2326 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2327 return VERR_NOT_SUPPORTED;
2328#endif
2329}
2330
2331
2332/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2333static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2334{
2335#ifdef VMSVGA3D_DX
2336 //DEBUG_BREAKPOINT_TEST();
2337 RT_NOREF(cbCmd);
2338 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2339#else
2340 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2341 return VERR_NOT_SUPPORTED;
2342#endif
2343}
2344
2345
2346/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2347static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2348{
2349#ifdef VMSVGA3D_DX
2350 //DEBUG_BREAKPOINT_TEST();
2351 RT_NOREF(cbCmd);
2352 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2353#else
2354 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2355 return VERR_NOT_SUPPORTED;
2356#endif
2357}
2358
2359
2360/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2361static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2362{
2363#ifdef VMSVGA3D_DX
2364 DEBUG_BREAKPOINT_TEST();
2365 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2366 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2367 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2368#else
2369 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2370 return VERR_NOT_SUPPORTED;
2371#endif
2372}
2373
2374
2375/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2376static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2377{
2378#ifdef VMSVGA3D_DX
2379 //DEBUG_BREAKPOINT_TEST();
2380 RT_NOREF(cbCmd);
2381 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2382#else
2383 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2384 return VERR_NOT_SUPPORTED;
2385#endif
2386}
2387
2388
2389/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2390static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2391{
2392#ifdef VMSVGA3D_DX
2393 //DEBUG_BREAKPOINT_TEST();
2394 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2395 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2396 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2397#else
2398 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2399 return VERR_NOT_SUPPORTED;
2400#endif
2401}
2402
2403
2404/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2405static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2406{
2407#ifdef VMSVGA3D_DX
2408 //DEBUG_BREAKPOINT_TEST();
2409 RT_NOREF(cbCmd);
2410 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2411#else
2412 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2413 return VERR_NOT_SUPPORTED;
2414#endif
2415}
2416
2417
2418/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2419static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2420{
2421#ifdef VMSVGA3D_DX
2422 //DEBUG_BREAKPOINT_TEST();
2423 RT_NOREF(cbCmd);
2424 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2425#else
2426 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2427 return VERR_NOT_SUPPORTED;
2428#endif
2429}
2430
2431
2432/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2433static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2434{
2435#ifdef VMSVGA3D_DX
2436 //DEBUG_BREAKPOINT_TEST();
2437 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2438 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2439 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2440#else
2441 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2442 return VERR_NOT_SUPPORTED;
2443#endif
2444}
2445
2446
2447/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2448static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2449{
2450#ifdef VMSVGA3D_DX
2451 //DEBUG_BREAKPOINT_TEST();
2452 RT_NOREF(cbCmd);
2453 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2454#else
2455 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2456 return VERR_NOT_SUPPORTED;
2457#endif
2458}
2459
2460
2461/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2462static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2463{
2464#ifdef VMSVGA3D_DX
2465 //DEBUG_BREAKPOINT_TEST();
2466 RT_NOREF(cbCmd);
2467 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2468#else
2469 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2470 return VERR_NOT_SUPPORTED;
2471#endif
2472}
2473
2474
2475/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2476static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2477{
2478#ifdef VMSVGA3D_DX
2479 //DEBUG_BREAKPOINT_TEST();
2480 RT_NOREF(cbCmd);
2481 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2482#else
2483 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2484 return VERR_NOT_SUPPORTED;
2485#endif
2486}
2487
2488
2489/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2490static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2491{
2492#ifdef VMSVGA3D_DX
2493 DEBUG_BREAKPOINT_TEST();
2494 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2495 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2496 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2497#else
2498 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2499 return VERR_NOT_SUPPORTED;
2500#endif
2501}
2502
2503
2504/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2505static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2506{
2507#ifdef VMSVGA3D_DX
2508 DEBUG_BREAKPOINT_TEST();
2509 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2510 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2511 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2512#else
2513 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2514 return VERR_NOT_SUPPORTED;
2515#endif
2516}
2517
2518
2519/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2520static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2521{
2522#ifdef VMSVGA3D_DX
2523 DEBUG_BREAKPOINT_TEST();
2524 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2525 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2526 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2527#else
2528 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2529 return VERR_NOT_SUPPORTED;
2530#endif
2531}
2532
2533
2534/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2535static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2536{
2537#ifdef VMSVGA3D_DX
2538 DEBUG_BREAKPOINT_TEST();
2539 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2540 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2541 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2542#else
2543 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2544 return VERR_NOT_SUPPORTED;
2545#endif
2546}
2547
2548
2549/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2550static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2551{
2552#ifdef VMSVGA3D_DX
2553 DEBUG_BREAKPOINT_TEST();
2554 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2555 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2556 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2557#else
2558 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2559 return VERR_NOT_SUPPORTED;
2560#endif
2561}
2562
2563
2564/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2565static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2566{
2567#ifdef VMSVGA3D_DX
2568 DEBUG_BREAKPOINT_TEST();
2569 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2570 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2571 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2572#else
2573 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2574 return VERR_NOT_SUPPORTED;
2575#endif
2576}
2577
2578
2579/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2580static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2581{
2582#ifdef VMSVGA3D_DX
2583 DEBUG_BREAKPOINT_TEST();
2584 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2585 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2586 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2587#else
2588 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2589 return VERR_NOT_SUPPORTED;
2590#endif
2591}
2592
2593
2594/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2595static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2596{
2597#ifdef VMSVGA3D_DX
2598 DEBUG_BREAKPOINT_TEST();
2599 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2600 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2601 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2602#else
2603 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2604 return VERR_NOT_SUPPORTED;
2605#endif
2606}
2607
2608
2609/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2610static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2611{
2612#ifdef VMSVGA3D_DX
2613 //DEBUG_BREAKPOINT_TEST();
2614 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2615 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2616 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2617#else
2618 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2619 return VERR_NOT_SUPPORTED;
2620#endif
2621}
2622
2623
2624/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2625static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2626{
2627#ifdef VMSVGA3D_DX
2628 //DEBUG_BREAKPOINT_TEST();
2629 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2630 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2631 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2632#else
2633 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2634 return VERR_NOT_SUPPORTED;
2635#endif
2636}
2637
2638
2639/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2640static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2641{
2642#ifdef VMSVGA3D_DX
2643 //DEBUG_BREAKPOINT_TEST();
2644 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2645 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2646 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2647#else
2648 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2649 return VERR_NOT_SUPPORTED;
2650#endif
2651}
2652
2653
2654/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2655static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2656{
2657#ifdef VMSVGA3D_DX
2658 //DEBUG_BREAKPOINT_TEST();
2659 RT_NOREF(cbCmd);
2660 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2661#else
2662 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2663 return VERR_NOT_SUPPORTED;
2664#endif
2665}
2666
2667
2668/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2669static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2670{
2671#ifdef VMSVGA3D_DX
2672 //DEBUG_BREAKPOINT_TEST();
2673 RT_NOREF(cbCmd);
2674 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2675#else
2676 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2677 return VERR_NOT_SUPPORTED;
2678#endif
2679}
2680
2681
2682/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2683static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2684{
2685#ifdef VMSVGA3D_DX
2686 //DEBUG_BREAKPOINT_TEST();
2687 RT_NOREF(cbCmd);
2688 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2689#else
2690 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2691 return VERR_NOT_SUPPORTED;
2692#endif
2693}
2694
2695
2696/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2697static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2698{
2699#ifdef VMSVGA3D_DX
2700 DEBUG_BREAKPOINT_TEST();
2701 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2702 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2703 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2704#else
2705 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2706 return VERR_NOT_SUPPORTED;
2707#endif
2708}
2709
2710
2711/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2712static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2713{
2714#ifdef VMSVGA3D_DX
2715 DEBUG_BREAKPOINT_TEST();
2716 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2717 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2718 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2719#else
2720 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2721 return VERR_NOT_SUPPORTED;
2722#endif
2723}
2724
2725
2726/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2727static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2728{
2729#ifdef VMSVGA3D_DX
2730 //DEBUG_BREAKPOINT_TEST();
2731 RT_NOREF(cbCmd);
2732 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2733#else
2734 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2735 return VERR_NOT_SUPPORTED;
2736#endif
2737}
2738
2739
2740/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2741static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2742{
2743#ifdef VMSVGA3D_DX
2744 //DEBUG_BREAKPOINT_TEST();
2745 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2746 RT_NOREF(cbCmd);
2747
2748 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2749 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2750
2751 /* "Inform the device that the guest-contents have been updated." */
2752 SVGAOTableSurfaceEntry entrySurface;
2753 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2754 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2755 if (RT_SUCCESS(rc))
2756 {
2757 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2758 if (pMob)
2759 {
2760 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2761 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2762 /* pCmd->box will be verified by the mapping function. */
2763 RT_UNTRUSTED_VALIDATED_FENCE();
2764
2765 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2766 SVGA3dSurfaceImageId image;
2767 image.sid = pCmd->sid;
2768 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2769
2770 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2771 AssertRC(rc);
2772 }
2773 }
2774
2775 return rc;
2776#else
2777 RT_NOREF(pThisCC, pCmd, cbCmd);
2778 return VERR_NOT_SUPPORTED;
2779#endif
2780}
2781
2782
2783/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2784static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2785{
2786#ifdef VMSVGA3D_DX
2787 //DEBUG_BREAKPOINT_TEST();
2788 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2789 RT_NOREF(cbCmd);
2790
2791 LogFlowFunc(("sid=%u, subResource=%u\n",
2792 pCmd->sid, pCmd->subResource));
2793
2794 /* "Request the device to flush the dirty contents into the guest." */
2795 SVGAOTableSurfaceEntry entrySurface;
2796 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2797 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2798 if (RT_SUCCESS(rc))
2799 {
2800 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2801 if (pMob)
2802 {
2803 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2804 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2805 RT_UNTRUSTED_VALIDATED_FENCE();
2806
2807 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2808 SVGA3dSurfaceImageId image;
2809 image.sid = pCmd->sid;
2810 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2811
2812 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2813 AssertRC(rc);
2814 }
2815 }
2816
2817 return rc;
2818#else
2819 RT_NOREF(pThisCC, pCmd, cbCmd);
2820 return VERR_NOT_SUPPORTED;
2821#endif
2822}
2823
2824
2825/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2826static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2827{
2828#ifdef VMSVGA3D_DX
2829 DEBUG_BREAKPOINT_TEST();
2830 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2831 RT_NOREF(cbCmd);
2832
2833 LogFlowFunc(("sid=%u, subResource=%u\n",
2834 pCmd->sid, pCmd->subResource));
2835
2836 /* "Notify the device that the contents can be lost." */
2837 SVGAOTableSurfaceEntry entrySurface;
2838 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2839 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2840 if (RT_SUCCESS(rc))
2841 {
2842 uint32_t iFace;
2843 uint32_t iMipmap;
2844 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2845 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2846 }
2847
2848 return rc;
2849#else
2850 RT_NOREF(pThisCC, pCmd, cbCmd);
2851 return VERR_NOT_SUPPORTED;
2852#endif
2853}
2854
2855
2856/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2857static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2858{
2859#ifdef VMSVGA3D_DX
2860 //DEBUG_BREAKPOINT_TEST();
2861 RT_NOREF(cbCmd);
2862 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2863#else
2864 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2865 return VERR_NOT_SUPPORTED;
2866#endif
2867}
2868
2869
2870/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2871static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2872{
2873#ifdef VMSVGA3D_DX
2874 //DEBUG_BREAKPOINT_TEST();
2875 RT_NOREF(cbCmd);
2876 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2877#else
2878 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2879 return VERR_NOT_SUPPORTED;
2880#endif
2881}
2882
2883
2884/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2885static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2886{
2887#ifdef VMSVGA3D_DX
2888 //DEBUG_BREAKPOINT_TEST();
2889 RT_NOREF(cbCmd);
2890 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2891#else
2892 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2893 return VERR_NOT_SUPPORTED;
2894#endif
2895}
2896
2897
2898/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2899static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2900{
2901#ifdef VMSVGA3D_DX
2902 //DEBUG_BREAKPOINT_TEST();
2903 RT_NOREF(cbCmd);
2904 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2905#else
2906 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2907 return VERR_NOT_SUPPORTED;
2908#endif
2909}
2910
2911
2912/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2913static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2914{
2915#ifdef VMSVGA3D_DX
2916 //DEBUG_BREAKPOINT_TEST();
2917 RT_NOREF(cbCmd);
2918 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2919 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2920 cmd.sid = pCmd->sid;
2921 cmd.format = pCmd->format;
2922 cmd.resourceDimension = pCmd->resourceDimension;
2923 cmd.mipSlice = pCmd->mipSlice;
2924 cmd.firstArraySlice = pCmd->firstArraySlice;
2925 cmd.arraySize = pCmd->arraySize;
2926 cmd.flags = 0;
2927 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2928#else
2929 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2930 return VERR_NOT_SUPPORTED;
2931#endif
2932}
2933
2934
2935/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2936static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2937{
2938#ifdef VMSVGA3D_DX
2939 //DEBUG_BREAKPOINT_TEST();
2940 RT_NOREF(cbCmd);
2941 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2942#else
2943 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2944 return VERR_NOT_SUPPORTED;
2945#endif
2946}
2947
2948
2949/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2950static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2951{
2952#ifdef VMSVGA3D_DX
2953 //DEBUG_BREAKPOINT_TEST();
2954 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2955 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2956 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2957#else
2958 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2959 return VERR_NOT_SUPPORTED;
2960#endif
2961}
2962
2963
2964/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2965static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2966{
2967#ifdef VMSVGA3D_DX
2968 DEBUG_BREAKPOINT_TEST();
2969 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2970 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2971 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2972#else
2973 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2974 return VERR_NOT_SUPPORTED;
2975#endif
2976}
2977
2978
2979/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2980static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2981{
2982#ifdef VMSVGA3D_DX
2983 //DEBUG_BREAKPOINT_TEST();
2984 RT_NOREF(cbCmd);
2985 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2986#else
2987 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2988 return VERR_NOT_SUPPORTED;
2989#endif
2990}
2991
2992
2993/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2994static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2995{
2996#ifdef VMSVGA3D_DX
2997 DEBUG_BREAKPOINT_TEST();
2998 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2999 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3000 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
3001#else
3002 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3003 return VERR_NOT_SUPPORTED;
3004#endif
3005}
3006
3007
3008/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
3009static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
3010{
3011#ifdef VMSVGA3D_DX
3012 //DEBUG_BREAKPOINT_TEST();
3013 RT_NOREF(cbCmd);
3014 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
3015#else
3016 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3017 return VERR_NOT_SUPPORTED;
3018#endif
3019}
3020
3021
3022/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
3023static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
3024{
3025#ifdef VMSVGA3D_DX
3026 DEBUG_BREAKPOINT_TEST();
3027 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3028 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3029 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
3030#else
3031 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3032 return VERR_NOT_SUPPORTED;
3033#endif
3034}
3035
3036
3037/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
3038static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
3039{
3040#ifdef VMSVGA3D_DX
3041 //DEBUG_BREAKPOINT_TEST();
3042 RT_NOREF(cbCmd);
3043 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
3044#else
3045 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3046 return VERR_NOT_SUPPORTED;
3047#endif
3048}
3049
3050
3051/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
3052static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
3053{
3054#ifdef VMSVGA3D_DX
3055 DEBUG_BREAKPOINT_TEST();
3056 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3057 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3058 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
3059#else
3060 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3061 return VERR_NOT_SUPPORTED;
3062#endif
3063}
3064
3065
3066/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3067static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3068{
3069#ifdef VMSVGA3D_DX
3070 //DEBUG_BREAKPOINT_TEST();
3071 RT_NOREF(cbCmd);
3072 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3073#else
3074 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3075 return VERR_NOT_SUPPORTED;
3076#endif
3077}
3078
3079
3080/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3081static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3082{
3083#ifdef VMSVGA3D_DX
3084 DEBUG_BREAKPOINT_TEST();
3085 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3086 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3087 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
3088#else
3089 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3090 return VERR_NOT_SUPPORTED;
3091#endif
3092}
3093
3094
3095/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3096static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3097{
3098#ifdef VMSVGA3D_DX
3099 //DEBUG_BREAKPOINT_TEST();
3100 RT_NOREF(cbCmd);
3101 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3102#else
3103 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3104 return VERR_NOT_SUPPORTED;
3105#endif
3106}
3107
3108
3109/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3110static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3111{
3112#ifdef VMSVGA3D_DX
3113 //DEBUG_BREAKPOINT_TEST();
3114 RT_NOREF(cbCmd);
3115 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3116#else
3117 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3118 return VERR_NOT_SUPPORTED;
3119#endif
3120}
3121
3122
3123/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3124static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3125{
3126#ifdef VMSVGA3D_DX
3127 //DEBUG_BREAKPOINT_TEST();
3128 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3129 RT_NOREF(idDXContext, cbCmd);
3130 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3131 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3132 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3133#else
3134 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3135 return VERR_NOT_SUPPORTED;
3136#endif
3137}
3138
3139
3140/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3141static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3142{
3143#ifdef VMSVGA3D_DX
3144 //DEBUG_BREAKPOINT_TEST();
3145 RT_NOREF(cbCmd);
3146 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3147#else
3148 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3149 return VERR_NOT_SUPPORTED;
3150#endif
3151}
3152
3153
3154/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3155static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3156{
3157#ifdef VMSVGA3D_DX
3158 DEBUG_BREAKPOINT_TEST();
3159 RT_NOREF(cbCmd);
3160 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3161#else
3162 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3163 return VERR_NOT_SUPPORTED;
3164#endif
3165}
3166
3167
3168/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3169static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3170{
3171#ifdef VMSVGA3D_DX
3172 //DEBUG_BREAKPOINT_TEST();
3173 RT_NOREF(cbCmd);
3174 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3175#else
3176 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3177 return VERR_NOT_SUPPORTED;
3178#endif
3179}
3180
3181
3182/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3183static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3184{
3185#ifdef VMSVGA3D_DX
3186 //DEBUG_BREAKPOINT_TEST();
3187 RT_NOREF(cbCmd);
3188 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3189 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3190 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3191 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3192#else
3193 RT_NOREF(pThisCC, pCmd, cbCmd);
3194 return VERR_NOT_SUPPORTED;
3195#endif
3196}
3197
3198
3199/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3200static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3201{
3202#ifdef VMSVGA3D_DX
3203 //DEBUG_BREAKPOINT_TEST();
3204 RT_NOREF(idDXContext, cbCmd);
3205 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3206#else
3207 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3208 return VERR_NOT_SUPPORTED;
3209#endif
3210}
3211
3212
3213/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3214static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3215{
3216#ifdef VMSVGA3D_DX
3217 DEBUG_BREAKPOINT_TEST();
3218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3219 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3220 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
3221#else
3222 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3223 return VERR_NOT_SUPPORTED;
3224#endif
3225}
3226
3227
3228/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3229static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3230{
3231#ifdef VMSVGA3D_DX
3232 //DEBUG_BREAKPOINT_TEST();
3233 RT_NOREF(cbCmd);
3234
3235 /* Plan:
3236 * - map the buffer;
3237 * - map the surface;
3238 * - copy from buffer map to the surface map.
3239 */
3240
3241 int rc;
3242
3243 SVGA3dSurfaceImageId imageBuffer;
3244 imageBuffer.sid = pCmd->srcSid;
3245 imageBuffer.face = 0;
3246 imageBuffer.mipmap = 0;
3247
3248 SVGA3dSurfaceImageId imageSurface;
3249 imageSurface.sid = pCmd->destSid;
3250 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3251 AssertRCReturn(rc, rc);
3252
3253 /*
3254 * Map the buffer.
3255 */
3256 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3257 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3258 if (RT_SUCCESS(rc))
3259 {
3260 /*
3261 * Map the surface.
3262 */
3263 VMSVGA3D_MAPPED_SURFACE mapSurface;
3264 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3265 if (RT_SUCCESS(rc))
3266 {
3267 /*
3268 * Copy the mapped buffer to the surface.
3269 */
3270 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3271 uint32_t const cbBuffer = mapBuffer.box.w * mapBuffer.cbPixel;
3272
3273 if (pCmd->srcOffset <= cbBuffer)
3274 {
3275 RT_UNTRUSTED_VALIDATED_FENCE();
3276 uint8_t const *pu8BufferBegin = pu8Buffer;
3277 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3278
3279 pu8Buffer += pCmd->srcOffset;
3280
3281 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3282
3283 uint32_t const cbWidth = mapSurface.box.w * mapSurface.cbPixel;
3284 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3285 {
3286 uint8_t const *pu8BufferRow = pu8Buffer;
3287 uint8_t *pu8SurfaceRow = pu8Surface;
3288 for (uint32_t y = 0; y < mapSurface.box.h; ++y)
3289 {
3290 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3291 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3292 && (uintptr_t)(pu8BufferRow + cbWidth) > (uintptr_t)pu8BufferBegin
3293 && (uintptr_t)(pu8BufferRow + cbWidth) <= (uintptr_t)pu8BufferEnd,
3294 rc = VERR_INVALID_PARAMETER);
3295
3296 memcpy(pu8SurfaceRow, pu8BufferRow, cbWidth);
3297
3298 pu8SurfaceRow += mapSurface.cbRowPitch;
3299 pu8BufferRow += pCmd->srcPitch;
3300 }
3301
3302 pu8Buffer += pCmd->srcSlicePitch;
3303 pu8Surface += mapSurface.cbDepthPitch;
3304 }
3305 }
3306 else
3307 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3308
3309 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3310 }
3311
3312 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3313 }
3314
3315 return rc;
3316#else
3317 RT_NOREF(pThisCC, pCmd, cbCmd);
3318 return VERR_NOT_SUPPORTED;
3319#endif
3320}
3321
3322
3323/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3324static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3325{
3326#ifdef VMSVGA3D_DX
3327 DEBUG_BREAKPOINT_TEST();
3328 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3329 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3330 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3331#else
3332 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3333 return VERR_NOT_SUPPORTED;
3334#endif
3335}
3336
3337
3338/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3339static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3340{
3341#ifdef VMSVGA3D_DX
3342 DEBUG_BREAKPOINT_TEST();
3343 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3344 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3345 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3346#else
3347 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3348 return VERR_NOT_SUPPORTED;
3349#endif
3350}
3351
3352
3353/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3354static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3355{
3356#ifdef VMSVGA3D_DX
3357 DEBUG_BREAKPOINT_TEST();
3358 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3359 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3360 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
3361#else
3362 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3363 return VERR_NOT_SUPPORTED;
3364#endif
3365}
3366
3367
3368/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3369static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3370{
3371#ifdef VMSVGA3D_DX
3372 DEBUG_BREAKPOINT_TEST();
3373 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3374 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3375 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
3376#else
3377 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3378 return VERR_NOT_SUPPORTED;
3379#endif
3380}
3381
3382
3383/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3384static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3385{
3386#ifdef VMSVGA3D_DX
3387 //DEBUG_BREAKPOINT_TEST();
3388 RT_NOREF(idDXContext, cbCmd);
3389
3390 /* This command is executed in a context: "The context is implied from the command buffer header."
3391 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3392 */
3393 SVGA3dCmdDXTransferFromBuffer cmd;
3394 cmd.srcSid = pCmd->srcSid;
3395 cmd.srcOffset = pCmd->srcOffset;
3396 cmd.srcPitch = pCmd->srcPitch;
3397 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3398 cmd.destSid = pCmd->destSid;
3399 cmd.destSubResource = pCmd->destSubResource;
3400 cmd.destBox = pCmd->destBox;
3401 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3402#else
3403 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3404 return VERR_NOT_SUPPORTED;
3405#endif
3406}
3407
3408
3409/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3410static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3411{
3412#ifdef VMSVGA3D_DX
3413 DEBUG_BREAKPOINT_TEST();
3414 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3415 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3416 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3417#else
3418 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3419 return VERR_NOT_SUPPORTED;
3420#endif
3421}
3422
3423
3424/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3425static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3426{
3427#ifdef VMSVGA3D_DX
3428 DEBUG_BREAKPOINT_TEST();
3429 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3430 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3431 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3432#else
3433 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3434 return VERR_NOT_SUPPORTED;
3435#endif
3436}
3437
3438
3439/* SVGA_3D_CMD_DX_HINT 1218 */
3440static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3441{
3442#ifdef VMSVGA3D_DX
3443 DEBUG_BREAKPOINT_TEST();
3444 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3445 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3446 return vmsvga3dDXHint(pThisCC, idDXContext);
3447#else
3448 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3449 return VERR_NOT_SUPPORTED;
3450#endif
3451}
3452
3453
3454/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3455static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3456{
3457#ifdef VMSVGA3D_DX
3458 DEBUG_BREAKPOINT_TEST();
3459 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3460 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3461 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3462#else
3463 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3464 return VERR_NOT_SUPPORTED;
3465#endif
3466}
3467
3468
3469/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3470static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3471{
3472#ifdef VMSVGA3D_DX
3473 DEBUG_BREAKPOINT_TEST();
3474 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3475 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3476 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3477#else
3478 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3479 return VERR_NOT_SUPPORTED;
3480#endif
3481}
3482
3483
3484/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3485static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3486{
3487#ifdef VMSVGA3D_DX
3488 DEBUG_BREAKPOINT_TEST();
3489 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3490 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3491 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3492#else
3493 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3494 return VERR_NOT_SUPPORTED;
3495#endif
3496}
3497
3498
3499/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3500static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3501{
3502#ifdef VMSVGA3D_DX
3503 DEBUG_BREAKPOINT_TEST();
3504 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3505 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3506 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3507#else
3508 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3509 return VERR_NOT_SUPPORTED;
3510#endif
3511}
3512
3513
3514/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3515static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3516{
3517#ifdef VMSVGA3D_DX
3518 DEBUG_BREAKPOINT_TEST();
3519 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3520 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3521 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3522#else
3523 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3524 return VERR_NOT_SUPPORTED;
3525#endif
3526}
3527
3528
3529/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3530static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3531{
3532#ifdef VMSVGA3D_DX
3533 DEBUG_BREAKPOINT_TEST();
3534 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3535 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3536 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3537#else
3538 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3539 return VERR_NOT_SUPPORTED;
3540#endif
3541}
3542
3543
3544/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3545static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3546{
3547#ifdef VMSVGA3D_DX
3548 DEBUG_BREAKPOINT_TEST();
3549 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3550 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3551 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3552#else
3553 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3554 return VERR_NOT_SUPPORTED;
3555#endif
3556}
3557
3558
3559/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3560static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3561{
3562#ifdef VMSVGA3D_DX
3563 DEBUG_BREAKPOINT_TEST();
3564 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3565 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3566 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3567#else
3568 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3569 return VERR_NOT_SUPPORTED;
3570#endif
3571}
3572
3573
3574/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3575static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3576{
3577#ifdef VMSVGA3D_DX
3578 DEBUG_BREAKPOINT_TEST();
3579 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3580 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3581 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3582#else
3583 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3584 return VERR_NOT_SUPPORTED;
3585#endif
3586}
3587
3588
3589/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3590static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3591{
3592#ifdef VMSVGA3D_DX
3593 DEBUG_BREAKPOINT_TEST();
3594 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3595 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3596 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3597#else
3598 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3599 return VERR_NOT_SUPPORTED;
3600#endif
3601}
3602
3603
3604/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3605static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3606{
3607#ifdef VMSVGA3D_DX
3608 DEBUG_BREAKPOINT_TEST();
3609 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3610 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3611 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3612#else
3613 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3614 return VERR_NOT_SUPPORTED;
3615#endif
3616}
3617
3618
3619/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3620static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3621{
3622#ifdef VMSVGA3D_DX
3623 DEBUG_BREAKPOINT_TEST();
3624 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3625 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3626 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3627#else
3628 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3629 return VERR_NOT_SUPPORTED;
3630#endif
3631}
3632
3633
3634/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3635static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3636{
3637#ifdef VMSVGA3D_DX
3638 DEBUG_BREAKPOINT_TEST();
3639 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3640 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3641 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3642#else
3643 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3644 return VERR_NOT_SUPPORTED;
3645#endif
3646}
3647
3648
3649/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3650static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3651{
3652#ifdef VMSVGA3D_DX
3653 DEBUG_BREAKPOINT_TEST();
3654 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3655 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3656 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3657#else
3658 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3659 return VERR_NOT_SUPPORTED;
3660#endif
3661}
3662
3663
3664/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3665static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3666{
3667#ifdef VMSVGA3D_DX
3668 DEBUG_BREAKPOINT_TEST();
3669 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3670 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3671 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3672#else
3673 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3674 return VERR_NOT_SUPPORTED;
3675#endif
3676}
3677
3678
3679/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3680static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3681{
3682#ifdef VMSVGA3D_DX
3683 DEBUG_BREAKPOINT_TEST();
3684 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3685 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3686 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3687#else
3688 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3689 return VERR_NOT_SUPPORTED;
3690#endif
3691}
3692
3693
3694/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3695static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3696{
3697#ifdef VMSVGA3D_DX
3698 DEBUG_BREAKPOINT_TEST();
3699 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3700 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3701 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3702#else
3703 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3704 return VERR_NOT_SUPPORTED;
3705#endif
3706}
3707
3708
3709/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3710static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3711{
3712#ifdef VMSVGA3D_DX
3713 DEBUG_BREAKPOINT_TEST();
3714 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3715 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3716 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3717#else
3718 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3719 return VERR_NOT_SUPPORTED;
3720#endif
3721}
3722
3723
3724/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3725static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3726{
3727#ifdef VMSVGA3D_DX
3728 DEBUG_BREAKPOINT_TEST();
3729 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3730 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3731 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3732#else
3733 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3734 return VERR_NOT_SUPPORTED;
3735#endif
3736}
3737
3738
3739/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3740static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3741{
3742#ifdef VMSVGA3D_DX
3743 DEBUG_BREAKPOINT_TEST();
3744 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3745 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3746 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3747#else
3748 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3749 return VERR_NOT_SUPPORTED;
3750#endif
3751}
3752
3753
3754/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3755static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3756{
3757#ifdef VMSVGA3D_DX
3758 DEBUG_BREAKPOINT_TEST();
3759 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3760 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3761 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3762#else
3763 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3764 return VERR_NOT_SUPPORTED;
3765#endif
3766}
3767
3768
3769/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3770static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3771{
3772#ifdef VMSVGA3D_DX
3773 DEBUG_BREAKPOINT_TEST();
3774 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3775 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3776 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3777#else
3778 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3779 return VERR_NOT_SUPPORTED;
3780#endif
3781}
3782
3783
3784/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3785static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3786{
3787#ifdef VMSVGA3D_DX
3788 DEBUG_BREAKPOINT_TEST();
3789 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3790 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3791 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3792#else
3793 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3794 return VERR_NOT_SUPPORTED;
3795#endif
3796}
3797
3798
3799/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3800static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3801{
3802#ifdef VMSVGA3D_DX
3803 DEBUG_BREAKPOINT_TEST();
3804 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3805 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3806 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3807#else
3808 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3809 return VERR_NOT_SUPPORTED;
3810#endif
3811}
3812
3813
3814/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3815static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3816{
3817#ifdef VMSVGA3D_DX
3818 DEBUG_BREAKPOINT_TEST();
3819 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3820 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3821 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3822#else
3823 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3824 return VERR_NOT_SUPPORTED;
3825#endif
3826}
3827
3828
3829/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3830static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3831{
3832#ifdef VMSVGA3D_DX
3833 DEBUG_BREAKPOINT_TEST();
3834 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3835 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3836 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3837#else
3838 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3839 return VERR_NOT_SUPPORTED;
3840#endif
3841}
3842
3843
3844/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3845static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3846{
3847#ifdef VMSVGA3D_DX
3848 DEBUG_BREAKPOINT_TEST();
3849 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3850 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3851 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3852#else
3853 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3854 return VERR_NOT_SUPPORTED;
3855#endif
3856}
3857
3858
3859/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3860static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3861{
3862#ifdef VMSVGA3D_DX
3863 DEBUG_BREAKPOINT_TEST();
3864 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3865 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3866 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3867#else
3868 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3869 return VERR_NOT_SUPPORTED;
3870#endif
3871}
3872
3873
3874/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3875static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3876{
3877#ifdef VMSVGA3D_DX
3878 DEBUG_BREAKPOINT_TEST();
3879 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3880 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3881 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3882#else
3883 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3884 return VERR_NOT_SUPPORTED;
3885#endif
3886}
3887
3888
3889/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3890static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3891{
3892#ifdef VMSVGA3D_DX
3893 DEBUG_BREAKPOINT_TEST();
3894 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3895 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3896 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3897#else
3898 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3899 return VERR_NOT_SUPPORTED;
3900#endif
3901}
3902
3903
3904/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3905static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3906{
3907#ifdef VMSVGA3D_DX
3908 DEBUG_BREAKPOINT_TEST();
3909 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3910 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3911 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3912#else
3913 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3914 return VERR_NOT_SUPPORTED;
3915#endif
3916}
3917
3918
3919/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3920static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3921{
3922#ifdef VMSVGA3D_DX
3923 DEBUG_BREAKPOINT_TEST();
3924 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3925 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3926 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3927#else
3928 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3929 return VERR_NOT_SUPPORTED;
3930#endif
3931}
3932
3933
3934/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3935static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3936{
3937#ifdef VMSVGA3D_DX
3938 DEBUG_BREAKPOINT_TEST();
3939 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3940 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3941 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3942#else
3943 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3944 return VERR_NOT_SUPPORTED;
3945#endif
3946}
3947
3948
3949/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3950static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3951{
3952#ifdef VMSVGA3D_DX
3953 DEBUG_BREAKPOINT_TEST();
3954 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3955 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3956 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3957#else
3958 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3959 return VERR_NOT_SUPPORTED;
3960#endif
3961}
3962
3963
3964/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3965static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3966{
3967#ifdef VMSVGA3D_DX
3968 DEBUG_BREAKPOINT_TEST();
3969 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3970 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3971 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3972#else
3973 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3974 return VERR_NOT_SUPPORTED;
3975#endif
3976}
3977
3978
3979/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3980static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3981{
3982#ifdef VMSVGA3D_DX
3983 DEBUG_BREAKPOINT_TEST();
3984 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3985 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3986 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3987#else
3988 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3989 return VERR_NOT_SUPPORTED;
3990#endif
3991}
3992
3993
3994/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3995static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3996{
3997#ifdef VMSVGA3D_DX
3998 DEBUG_BREAKPOINT_TEST();
3999 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4000 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4001 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
4002#else
4003 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4004 return VERR_NOT_SUPPORTED;
4005#endif
4006}
4007
4008
4009/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
4010static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
4011{
4012#ifdef VMSVGA3D_DX
4013 DEBUG_BREAKPOINT_TEST();
4014 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4015 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4016 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4017#else
4018 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4019 return VERR_NOT_SUPPORTED;
4020#endif
4021}
4022
4023
4024/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4025static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
4026{
4027#ifdef VMSVGA3D_DX
4028 DEBUG_BREAKPOINT_TEST();
4029 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4030 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4031 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
4032#else
4033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4034 return VERR_NOT_SUPPORTED;
4035#endif
4036}
4037
4038
4039/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4040static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4041{
4042#ifdef VMSVGA3D_DX
4043 DEBUG_BREAKPOINT_TEST();
4044 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4045 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4046 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
4047#else
4048 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4049 return VERR_NOT_SUPPORTED;
4050#endif
4051}
4052
4053
4054/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4055static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4056{
4057#ifdef VMSVGA3D_DX
4058 DEBUG_BREAKPOINT_TEST();
4059 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4060 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4061 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4062#else
4063 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4064 return VERR_NOT_SUPPORTED;
4065#endif
4066}
4067
4068
4069/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4070static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4071{
4072#ifdef VMSVGA3D_DX
4073 //DEBUG_BREAKPOINT_TEST();
4074 RT_NOREF(cbCmd);
4075 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4076#else
4077 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4078 return VERR_NOT_SUPPORTED;
4079#endif
4080}
4081
4082
4083/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4084static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4085{
4086#ifdef VMSVGA3D_DX
4087 DEBUG_BREAKPOINT_TEST();
4088 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4089 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4090 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4091#else
4092 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4093 return VERR_NOT_SUPPORTED;
4094#endif
4095}
4096
4097
4098/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4099static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4100{
4101#ifdef VMSVGA3D_DX
4102 DEBUG_BREAKPOINT_TEST();
4103 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4104 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4105 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4106#else
4107 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4108 return VERR_NOT_SUPPORTED;
4109#endif
4110}
4111
4112
4113/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4114static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4115{
4116#ifdef VMSVGA3D_DX
4117 DEBUG_BREAKPOINT_TEST();
4118 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4119 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4120 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4121#else
4122 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4123 return VERR_NOT_SUPPORTED;
4124#endif
4125}
4126
4127
4128/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4129static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4130{
4131#ifdef VMSVGA3D_DX
4132 DEBUG_BREAKPOINT_TEST();
4133 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4134 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4135 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4136#else
4137 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4138 return VERR_NOT_SUPPORTED;
4139#endif
4140}
4141
4142
4143/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4144static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4145{
4146#ifdef VMSVGA3D_DX
4147 DEBUG_BREAKPOINT_TEST();
4148 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4149 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4150 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4151#else
4152 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4153 return VERR_NOT_SUPPORTED;
4154#endif
4155}
4156
4157
4158/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4159 * Check that the 3D command has at least a_cbMin of payload bytes after the
4160 * header. Will break out of the switch if it doesn't.
4161 */
4162# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4163 if (1) { \
4164 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4165 RT_UNTRUSTED_VALIDATED_FENCE(); \
4166 } else do {} while (0)
4167
4168# define VMSVGA_3D_CMD_NOTIMPL() \
4169 if (1) { \
4170 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4171 } else do {} while (0)
4172
4173/** SVGA_3D_CMD_* handler.
4174 * This function parses the command and calls the corresponding command handler.
4175 *
4176 * @param pThis The shared VGA/VMSVGA state.
4177 * @param pThisCC The VGA/VMSVGA state for the current context.
4178 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4179 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4180 * @param cbCmd Size of the command in bytes.
4181 * @param pvCmd Pointer to the command.
4182 * @returns VBox status code if an error was detected parsing a command.
4183 */
4184int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4185{
4186 if (enmCmdId > SVGA_3D_CMD_MAX)
4187 {
4188 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4189 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4190 }
4191
4192 int rcParse = VINF_SUCCESS;
4193 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4194
4195 switch (enmCmdId)
4196 {
4197 case SVGA_3D_CMD_SURFACE_DEFINE:
4198 {
4199 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4200 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4201 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4202
4203 SVGA3dCmdDefineSurface_v2 cmd;
4204 cmd.sid = pCmd->sid;
4205 cmd.surfaceFlags = pCmd->surfaceFlags;
4206 cmd.format = pCmd->format;
4207 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4208 cmd.multisampleCount = 0;
4209 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4210
4211 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4212 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4213# ifdef DEBUG_GMR_ACCESS
4214 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4215# endif
4216 break;
4217 }
4218
4219 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4220 {
4221 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4223 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4224
4225 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4226 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4227# ifdef DEBUG_GMR_ACCESS
4228 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4229# endif
4230 break;
4231 }
4232
4233 case SVGA_3D_CMD_SURFACE_DESTROY:
4234 {
4235 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4236 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4237 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4238
4239 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4240 break;
4241 }
4242
4243 case SVGA_3D_CMD_SURFACE_COPY:
4244 {
4245 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4246 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4247 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4248
4249 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4250 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4251 break;
4252 }
4253
4254 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4255 {
4256 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4258 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4259
4260 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4261 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4262 break;
4263 }
4264
4265 case SVGA_3D_CMD_SURFACE_DMA:
4266 {
4267 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4268 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4269 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4270
4271 uint64_t u64NanoTS = 0;
4272 if (LogRelIs3Enabled())
4273 u64NanoTS = RTTimeNanoTS();
4274 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4275 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4276 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4277 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4278 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4279 if (LogRelIs3Enabled())
4280 {
4281 if (cCopyBoxes)
4282 {
4283 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4284 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4285 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4286 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4287 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4288 }
4289 }
4290 break;
4291 }
4292
4293 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4294 {
4295 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4296 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4297 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4298
4299 static uint64_t u64FrameStartNanoTS = 0;
4300 static uint64_t u64ElapsedPerSecNano = 0;
4301 static int cFrames = 0;
4302 uint64_t u64NanoTS = 0;
4303 if (LogRelIs3Enabled())
4304 u64NanoTS = RTTimeNanoTS();
4305 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4306 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4307 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4308 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4309 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4310 if (LogRelIs3Enabled())
4311 {
4312 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4313 u64ElapsedPerSecNano += u64ElapsedNano;
4314
4315 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4316 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4317 (u64ElapsedNano) / 1000ULL, cRects,
4318 pFirstRect->left, pFirstRect->top,
4319 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4320
4321 ++cFrames;
4322 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4323 {
4324 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4325 cFrames, u64ElapsedPerSecNano / 1000ULL));
4326 u64FrameStartNanoTS = u64NanoTS;
4327 cFrames = 0;
4328 u64ElapsedPerSecNano = 0;
4329 }
4330 }
4331 break;
4332 }
4333
4334 case SVGA_3D_CMD_CONTEXT_DEFINE:
4335 {
4336 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4337 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4338 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4339
4340 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4341 break;
4342 }
4343
4344 case SVGA_3D_CMD_CONTEXT_DESTROY:
4345 {
4346 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4347 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4348 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4349
4350 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4351 break;
4352 }
4353
4354 case SVGA_3D_CMD_SETTRANSFORM:
4355 {
4356 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4357 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4358 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4359
4360 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4361 break;
4362 }
4363
4364 case SVGA_3D_CMD_SETZRANGE:
4365 {
4366 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4367 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4368 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4369
4370 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4371 break;
4372 }
4373
4374 case SVGA_3D_CMD_SETRENDERSTATE:
4375 {
4376 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4377 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4378 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4379
4380 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4381 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4382 break;
4383 }
4384
4385 case SVGA_3D_CMD_SETRENDERTARGET:
4386 {
4387 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4388 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4389 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4390
4391 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4392 break;
4393 }
4394
4395 case SVGA_3D_CMD_SETTEXTURESTATE:
4396 {
4397 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4399 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4400
4401 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4402 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4403 break;
4404 }
4405
4406 case SVGA_3D_CMD_SETMATERIAL:
4407 {
4408 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4409 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4410 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4411
4412 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4413 break;
4414 }
4415
4416 case SVGA_3D_CMD_SETLIGHTDATA:
4417 {
4418 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4419 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4420 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4421
4422 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4423 break;
4424 }
4425
4426 case SVGA_3D_CMD_SETLIGHTENABLED:
4427 {
4428 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4429 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4430 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4431
4432 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4433 break;
4434 }
4435
4436 case SVGA_3D_CMD_SETVIEWPORT:
4437 {
4438 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4439 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4440 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4441
4442 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4443 break;
4444 }
4445
4446 case SVGA_3D_CMD_SETCLIPPLANE:
4447 {
4448 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4449 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4450 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4451
4452 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4453 break;
4454 }
4455
4456 case SVGA_3D_CMD_CLEAR:
4457 {
4458 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4459 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4460 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4461
4462 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4463 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4464 break;
4465 }
4466
4467 case SVGA_3D_CMD_PRESENT:
4468 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4469 {
4470 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4471 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4472 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4473 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4474 else
4475 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4476
4477 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4478 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4479 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4480 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4481 break;
4482 }
4483
4484 case SVGA_3D_CMD_SHADER_DEFINE:
4485 {
4486 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4489
4490 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4491 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4492 break;
4493 }
4494
4495 case SVGA_3D_CMD_SHADER_DESTROY:
4496 {
4497 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4500
4501 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4502 break;
4503 }
4504
4505 case SVGA_3D_CMD_SET_SHADER:
4506 {
4507 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4508 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4509 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4510
4511 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4512 break;
4513 }
4514
4515 case SVGA_3D_CMD_SET_SHADER_CONST:
4516 {
4517 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4520
4521 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4522 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4523 break;
4524 }
4525
4526 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4527 {
4528 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4529 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4530 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4531
4532 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4533 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4534 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4535 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4536 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4537
4538 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4539 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4540 RT_UNTRUSTED_VALIDATED_FENCE();
4541
4542 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4543 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4544 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4545
4546 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4547 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4548 pNumRange, cVertexDivisor, pVertexDivisor);
4549 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4550 break;
4551 }
4552
4553 case SVGA_3D_CMD_SETSCISSORRECT:
4554 {
4555 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4556 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4557 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4558
4559 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4560 break;
4561 }
4562
4563 case SVGA_3D_CMD_BEGIN_QUERY:
4564 {
4565 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4566 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4567 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4568
4569 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4570 break;
4571 }
4572
4573 case SVGA_3D_CMD_END_QUERY:
4574 {
4575 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4576 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4578
4579 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4580 break;
4581 }
4582
4583 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4584 {
4585 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4586 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4587 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4588
4589 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4590 break;
4591 }
4592
4593 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4594 {
4595 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4596 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4597 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4598
4599 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4600 break;
4601 }
4602
4603 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4604 /* context id + surface id? */
4605 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4606 break;
4607
4608 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4609 /* context id + surface id? */
4610 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4611 break;
4612
4613 /*
4614 *
4615 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4616 *
4617 */
4618 case SVGA_3D_CMD_SCREEN_DMA:
4619 {
4620 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4622 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4623 break;
4624 }
4625
4626 case SVGA_3D_CMD_DEAD1:
4627 case SVGA_3D_CMD_DEAD2:
4628 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4629 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4630 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4631 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4632 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4633 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4634 {
4635 VMSVGA_3D_CMD_NOTIMPL();
4636 break;
4637 }
4638
4639 case SVGA_3D_CMD_SET_OTABLE_BASE:
4640 {
4641 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4642 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4643 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4644 break;
4645 }
4646
4647 case SVGA_3D_CMD_READBACK_OTABLE:
4648 {
4649 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4651 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4652 break;
4653 }
4654
4655 case SVGA_3D_CMD_DEFINE_GB_MOB:
4656 {
4657 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4658 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4659 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4660 break;
4661 }
4662
4663 case SVGA_3D_CMD_DESTROY_GB_MOB:
4664 {
4665 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4666 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4667 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4668 break;
4669 }
4670
4671 case SVGA_3D_CMD_DEAD3:
4672 {
4673 VMSVGA_3D_CMD_NOTIMPL();
4674 break;
4675 }
4676
4677 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4678 {
4679 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4680 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4681 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4682 break;
4683 }
4684
4685 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4686 {
4687 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4688 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4689 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4690 break;
4691 }
4692
4693 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4694 {
4695 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4696 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4697 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4698 break;
4699 }
4700
4701 case SVGA_3D_CMD_BIND_GB_SURFACE:
4702 {
4703 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4704 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4705 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4706 break;
4707 }
4708
4709 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4710 {
4711 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4712 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4713 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4714 break;
4715 }
4716
4717 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4718 {
4719 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4720 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4721 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4722 break;
4723 }
4724
4725 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4726 {
4727 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4728 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4729 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4730 break;
4731 }
4732
4733 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4734 {
4735 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4736 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4737 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4738 break;
4739 }
4740
4741 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4742 {
4743 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4744 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4745 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4746 break;
4747 }
4748
4749 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4750 {
4751 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4752 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4753 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4754 break;
4755 }
4756
4757 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4758 {
4759 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4760 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4761 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4762 break;
4763 }
4764
4765 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4766 {
4767 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4768 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4769 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4770 break;
4771 }
4772
4773 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4774 {
4775 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4776 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4777 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4778 break;
4779 }
4780
4781 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4782 {
4783 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4784 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4785 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4786 break;
4787 }
4788
4789 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4790 {
4791 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4792 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4793 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4794 break;
4795 }
4796
4797 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4798 {
4799 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4800 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4801 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4802 break;
4803 }
4804
4805 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4806 {
4807 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4808 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4809 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4810 break;
4811 }
4812
4813 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4814 {
4815 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4816 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4817 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4818 break;
4819 }
4820
4821 case SVGA_3D_CMD_BIND_GB_SHADER:
4822 {
4823 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4824 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4825 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4826 break;
4827 }
4828
4829 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4830 {
4831 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4832 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4833 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4834 break;
4835 }
4836
4837 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4838 {
4839 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4840 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4841 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4842 break;
4843 }
4844
4845 case SVGA_3D_CMD_END_GB_QUERY:
4846 {
4847 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4848 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4849 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4850 break;
4851 }
4852
4853 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4854 {
4855 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4856 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4857 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4858 break;
4859 }
4860
4861 case SVGA_3D_CMD_NOP:
4862 {
4863 /* Apparently there is nothing to do. */
4864 break;
4865 }
4866
4867 case SVGA_3D_CMD_ENABLE_GART:
4868 {
4869 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4870 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4871 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4872 break;
4873 }
4874
4875 case SVGA_3D_CMD_DISABLE_GART:
4876 {
4877 /* No corresponding SVGA3dCmd structure. */
4878 VMSVGA_3D_CMD_NOTIMPL();
4879 break;
4880 }
4881
4882 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4883 {
4884 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4885 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4886 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4887 break;
4888 }
4889
4890 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4891 {
4892 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4893 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4894 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4895 break;
4896 }
4897
4898 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4899 {
4900 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4901 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4902 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4903 break;
4904 }
4905
4906 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4907 {
4908 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4909 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4910 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4911 break;
4912 }
4913
4914 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4915 {
4916 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4917 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4918 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4919 break;
4920 }
4921
4922 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4923 {
4924 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4925 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4926 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4927 break;
4928 }
4929
4930 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4931 {
4932 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4933 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4934 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4935 break;
4936 }
4937
4938 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4939 {
4940 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4941 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4942 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4943 break;
4944 }
4945
4946 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4947 {
4948 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4949 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4950 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4951 break;
4952 }
4953
4954 case SVGA_3D_CMD_GB_SCREEN_DMA:
4955 {
4956 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4957 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4958 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4959 break;
4960 }
4961
4962 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4963 {
4964 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4965 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4966 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4967 break;
4968 }
4969
4970 case SVGA_3D_CMD_GB_MOB_FENCE:
4971 {
4972 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4973 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4974 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4975 break;
4976 }
4977
4978 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4979 {
4980 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4981 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4982 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4983 break;
4984 }
4985
4986 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4987 {
4988 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4989 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4990 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4991 break;
4992 }
4993
4994 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4995 {
4996 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4997 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4998 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4999 break;
5000 }
5001
5002 case SVGA_3D_CMD_NOP_ERROR:
5003 {
5004 /* Apparently there is nothing to do. */
5005 break;
5006 }
5007
5008 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5009 {
5010 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
5011 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5012 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5013 break;
5014 }
5015
5016 case SVGA_3D_CMD_SET_VERTEX_DECLS:
5017 {
5018 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
5019 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5020 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5021 break;
5022 }
5023
5024 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5025 {
5026 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
5027 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5028 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5029 break;
5030 }
5031
5032 case SVGA_3D_CMD_DRAW:
5033 {
5034 /* No corresponding SVGA3dCmd structure. */
5035 VMSVGA_3D_CMD_NOTIMPL();
5036 break;
5037 }
5038
5039 case SVGA_3D_CMD_DRAW_INDEXED:
5040 {
5041 /* No corresponding SVGA3dCmd structure. */
5042 VMSVGA_3D_CMD_NOTIMPL();
5043 break;
5044 }
5045
5046 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5047 {
5048 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5049 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5050 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5051 break;
5052 }
5053
5054 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5055 {
5056 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5058 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5059 break;
5060 }
5061
5062 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5063 {
5064 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5066 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5067 break;
5068 }
5069
5070 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5071 {
5072 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5074 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5075 break;
5076 }
5077
5078 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5079 {
5080 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5082 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5083 break;
5084 }
5085
5086 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5087 {
5088 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5089 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5090 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5091 break;
5092 }
5093
5094 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5095 {
5096 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5098 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5099 break;
5100 }
5101
5102 case SVGA_3D_CMD_DX_SET_SHADER:
5103 {
5104 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5105 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5106 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5107 break;
5108 }
5109
5110 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5111 {
5112 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5113 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5114 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5115 break;
5116 }
5117
5118 case SVGA_3D_CMD_DX_DRAW:
5119 {
5120 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5122 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5123 break;
5124 }
5125
5126 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5127 {
5128 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5129 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5130 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5131 break;
5132 }
5133
5134 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5135 {
5136 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5137 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5138 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5139 break;
5140 }
5141
5142 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5143 {
5144 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5145 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5146 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5147 break;
5148 }
5149
5150 case SVGA_3D_CMD_DX_DRAW_AUTO:
5151 {
5152 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5153 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5154 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5155 break;
5156 }
5157
5158 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5159 {
5160 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5161 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5162 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5163 break;
5164 }
5165
5166 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5167 {
5168 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5170 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5171 break;
5172 }
5173
5174 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5175 {
5176 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5177 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5178 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5179 break;
5180 }
5181
5182 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5183 {
5184 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5185 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5186 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5187 break;
5188 }
5189
5190 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5191 {
5192 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5193 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5194 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5195 break;
5196 }
5197
5198 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5199 {
5200 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5201 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5202 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5203 break;
5204 }
5205
5206 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5207 {
5208 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5209 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5210 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5211 break;
5212 }
5213
5214 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5215 {
5216 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5217 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5218 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5219 break;
5220 }
5221
5222 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5223 {
5224 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5225 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5226 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5227 break;
5228 }
5229
5230 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5231 {
5232 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5233 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5234 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5235 break;
5236 }
5237
5238 case SVGA_3D_CMD_DX_BIND_QUERY:
5239 {
5240 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5242 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5243 break;
5244 }
5245
5246 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5247 {
5248 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5249 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5250 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5251 break;
5252 }
5253
5254 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5255 {
5256 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5258 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5259 break;
5260 }
5261
5262 case SVGA_3D_CMD_DX_END_QUERY:
5263 {
5264 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5265 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5266 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5267 break;
5268 }
5269
5270 case SVGA_3D_CMD_DX_READBACK_QUERY:
5271 {
5272 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5273 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5274 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5275 break;
5276 }
5277
5278 case SVGA_3D_CMD_DX_SET_PREDICATION:
5279 {
5280 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5281 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5282 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5283 break;
5284 }
5285
5286 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5287 {
5288 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5289 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5290 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5291 break;
5292 }
5293
5294 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5295 {
5296 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5297 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5298 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5299 break;
5300 }
5301
5302 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5303 {
5304 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5305 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5306 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5307 break;
5308 }
5309
5310 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5311 {
5312 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5313 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5314 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5315 break;
5316 }
5317
5318 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5319 {
5320 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5321 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5322 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5323 break;
5324 }
5325
5326 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5327 {
5328 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5329 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5330 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5331 break;
5332 }
5333
5334 case SVGA_3D_CMD_DX_PRED_COPY:
5335 {
5336 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5337 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5338 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5339 break;
5340 }
5341
5342 case SVGA_3D_CMD_DX_PRESENTBLT:
5343 {
5344 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5346 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5347 break;
5348 }
5349
5350 case SVGA_3D_CMD_DX_GENMIPS:
5351 {
5352 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5354 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5355 break;
5356 }
5357
5358 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5359 {
5360 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5361 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5362 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5363 break;
5364 }
5365
5366 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5367 {
5368 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5369 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5370 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5371 break;
5372 }
5373
5374 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5375 {
5376 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5377 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5378 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5379 break;
5380 }
5381
5382 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5383 {
5384 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5385 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5386 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5387 break;
5388 }
5389
5390 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5391 {
5392 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5393 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5394 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5395 break;
5396 }
5397
5398 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5399 {
5400 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5402 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5403 break;
5404 }
5405
5406 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5407 {
5408 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5409 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5410 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5411 break;
5412 }
5413
5414 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5415 {
5416 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5417 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5418 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5419 break;
5420 }
5421
5422 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5423 {
5424 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5425 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5426 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5427 break;
5428 }
5429
5430 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5431 {
5432 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5433 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5434 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5435 break;
5436 }
5437
5438 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5439 {
5440 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5441 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5442 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5443 break;
5444 }
5445
5446 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5447 {
5448 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5449 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5450 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5451 break;
5452 }
5453
5454 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5455 {
5456 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5457 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5458 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5459 break;
5460 }
5461
5462 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5463 {
5464 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5465 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5466 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5467 break;
5468 }
5469
5470 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5471 {
5472 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5473 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5474 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5475 break;
5476 }
5477
5478 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5479 {
5480 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5481 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5482 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5483 break;
5484 }
5485
5486 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5487 {
5488 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5489 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5490 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5491 break;
5492 }
5493
5494 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5495 {
5496 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5497 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5498 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5499 break;
5500 }
5501
5502 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5503 {
5504 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5505 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5506 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5507 break;
5508 }
5509
5510 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5511 {
5512 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5513 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5514 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5515 break;
5516 }
5517
5518 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5519 {
5520 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5521 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5522 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5523 break;
5524 }
5525
5526 case SVGA_3D_CMD_DX_BIND_SHADER:
5527 {
5528 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5529 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5530 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5531 break;
5532 }
5533
5534 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5535 {
5536 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5537 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5538 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5539 break;
5540 }
5541
5542 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5543 {
5544 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5545 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5546 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5547 break;
5548 }
5549
5550 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5551 {
5552 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5553 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5554 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5555 break;
5556 }
5557
5558 case SVGA_3D_CMD_DX_SET_COTABLE:
5559 {
5560 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5561 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5562 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5563 break;
5564 }
5565
5566 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5567 {
5568 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5569 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5570 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5571 break;
5572 }
5573
5574 case SVGA_3D_CMD_DX_BUFFER_COPY:
5575 {
5576 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5577 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5578 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5579 break;
5580 }
5581
5582 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5583 {
5584 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5585 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5586 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5587 break;
5588 }
5589
5590 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5591 {
5592 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5593 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5594 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5595 break;
5596 }
5597
5598 case SVGA_3D_CMD_DX_MOVE_QUERY:
5599 {
5600 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5601 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5602 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5603 break;
5604 }
5605
5606 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5607 {
5608 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5609 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5610 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5611 break;
5612 }
5613
5614 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5615 {
5616 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5617 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5618 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5619 break;
5620 }
5621
5622 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5623 {
5624 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5625 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5626 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5627 break;
5628 }
5629
5630 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5631 {
5632 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5633 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5634 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5635 break;
5636 }
5637
5638 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5639 {
5640 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5641 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5642 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5643 break;
5644 }
5645
5646 case SVGA_3D_CMD_DX_HINT:
5647 {
5648 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5649 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5650 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5651 break;
5652 }
5653
5654 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5655 {
5656 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5657 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5658 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5659 break;
5660 }
5661
5662 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5663 {
5664 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5665 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5666 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5667 break;
5668 }
5669
5670 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5671 {
5672 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5673 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5674 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5675 break;
5676 }
5677
5678 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5679 {
5680 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5681 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5682 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5683 break;
5684 }
5685
5686 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5687 {
5688 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5689 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5690 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5691 break;
5692 }
5693
5694 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5695 {
5696 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5697 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5698 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5699 break;
5700 }
5701
5702 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5703 {
5704 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5705 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5706 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5707 break;
5708 }
5709
5710 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5711 {
5712 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5713 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5714 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5715 break;
5716 }
5717
5718 case SVGA_3D_CMD_SCREEN_COPY:
5719 {
5720 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5721 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5722 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5723 break;
5724 }
5725
5726 case SVGA_3D_CMD_RESERVED1:
5727 {
5728 VMSVGA_3D_CMD_NOTIMPL();
5729 break;
5730 }
5731
5732 case SVGA_3D_CMD_RESERVED2:
5733 {
5734 VMSVGA_3D_CMD_NOTIMPL();
5735 break;
5736 }
5737
5738 case SVGA_3D_CMD_RESERVED3:
5739 {
5740 VMSVGA_3D_CMD_NOTIMPL();
5741 break;
5742 }
5743
5744 case SVGA_3D_CMD_RESERVED4:
5745 {
5746 VMSVGA_3D_CMD_NOTIMPL();
5747 break;
5748 }
5749
5750 case SVGA_3D_CMD_RESERVED5:
5751 {
5752 VMSVGA_3D_CMD_NOTIMPL();
5753 break;
5754 }
5755
5756 case SVGA_3D_CMD_RESERVED6:
5757 {
5758 VMSVGA_3D_CMD_NOTIMPL();
5759 break;
5760 }
5761
5762 case SVGA_3D_CMD_RESERVED7:
5763 {
5764 VMSVGA_3D_CMD_NOTIMPL();
5765 break;
5766 }
5767
5768 case SVGA_3D_CMD_RESERVED8:
5769 {
5770 VMSVGA_3D_CMD_NOTIMPL();
5771 break;
5772 }
5773
5774 case SVGA_3D_CMD_GROW_OTABLE:
5775 {
5776 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5777 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5778 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5779 break;
5780 }
5781
5782 case SVGA_3D_CMD_DX_GROW_COTABLE:
5783 {
5784 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5785 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5786 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5787 break;
5788 }
5789
5790 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5791 {
5792 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5793 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5794 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5795 break;
5796 }
5797
5798 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5799 {
5800 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5802 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5803 break;
5804 }
5805
5806 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5807 {
5808 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5809 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5810 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5811 break;
5812 }
5813
5814 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5815 {
5816 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5817 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5818 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5819 break;
5820 }
5821
5822 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5823 {
5824 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5825 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5826 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5827 break;
5828 }
5829
5830 case SVGA_3D_CMD_DX_PRED_CONVERT:
5831 {
5832 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5834 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5835 break;
5836 }
5837
5838 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5839 {
5840 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5841 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5842 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5843 break;
5844 }
5845
5846 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5847 {
5848 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5850 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5851 break;
5852 }
5853
5854 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5855 {
5856 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5858 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5859 break;
5860 }
5861
5862 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5863 {
5864 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5865 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5866 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5867 break;
5868 }
5869
5870 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5871 {
5872 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5873 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5874 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5875 break;
5876 }
5877
5878 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5879 {
5880 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5881 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5882 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5883 break;
5884 }
5885
5886 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5887 {
5888 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5889 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5890 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5891 break;
5892 }
5893
5894 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5895 {
5896 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5897 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5898 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5899 break;
5900 }
5901
5902 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5903 {
5904 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5905 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5906 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5907 break;
5908 }
5909
5910 case SVGA_3D_CMD_DX_DISPATCH:
5911 {
5912 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5914 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5915 break;
5916 }
5917
5918 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5919 {
5920 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5921 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5922 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5923 break;
5924 }
5925
5926 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5927 {
5928 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5930 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5931 break;
5932 }
5933
5934 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5935 {
5936 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5937 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5938 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5939 break;
5940 }
5941
5942 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5943 {
5944 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5946 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5947 break;
5948 }
5949
5950 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5951 {
5952 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5954 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5955 break;
5956 }
5957
5958 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5959 {
5960 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5962 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5963 break;
5964 }
5965
5966 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5967 {
5968 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5969 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5970 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5971 break;
5972 }
5973
5974 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5975 {
5976 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5977 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5978 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5979 break;
5980 }
5981
5982 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5983 {
5984 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5985 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5986 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5987 break;
5988 }
5989
5990 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5991 {
5992 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5993 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5994 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5995 break;
5996 }
5997
5998 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5999 {
6000 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
6001 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6002 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6003 break;
6004 }
6005
6006 case SVGA_3D_CMD_RESERVED2_1:
6007 {
6008 VMSVGA_3D_CMD_NOTIMPL();
6009 break;
6010 }
6011
6012 case SVGA_3D_CMD_RESERVED2_2:
6013 {
6014 VMSVGA_3D_CMD_NOTIMPL();
6015 break;
6016 }
6017
6018 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6019 {
6020 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
6021 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6022 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
6023 break;
6024 }
6025
6026 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6027 {
6028 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
6029 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6030 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6031 break;
6032 }
6033
6034 case SVGA_3D_CMD_DX_SET_MIN_LOD:
6035 {
6036 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
6037 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6038 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6039 break;
6040 }
6041
6042 case SVGA_3D_CMD_RESERVED2_3:
6043 {
6044 VMSVGA_3D_CMD_NOTIMPL();
6045 break;
6046 }
6047
6048 case SVGA_3D_CMD_RESERVED2_4:
6049 {
6050 VMSVGA_3D_CMD_NOTIMPL();
6051 break;
6052 }
6053
6054 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6055 {
6056 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6058 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6059 break;
6060 }
6061
6062 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6063 {
6064 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6066 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6067 break;
6068 }
6069
6070 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6071 {
6072 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6074 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6075 break;
6076 }
6077
6078 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6079 {
6080 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6082 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6083 break;
6084 }
6085
6086 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6087 {
6088 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6089 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6090 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6091 break;
6092 }
6093
6094 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6095 {
6096 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6098 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6099 break;
6100 }
6101
6102 /* Unsupported commands. */
6103 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6104 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6105 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6106 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6107 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6108 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6109 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6110 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6111 /* Prevent the compiler warning. */
6112 case SVGA_3D_CMD_LEGACY_BASE:
6113 case SVGA_3D_CMD_MAX:
6114 case SVGA_3D_CMD_FUTURE_MAX:
6115 /* No 'default' case */
6116 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6117 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6118 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6119 rcParse = VERR_NOT_IMPLEMENTED;
6120 break;
6121 }
6122
6123 return VINF_SUCCESS;
6124// return rcParse;
6125}
6126# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6127#endif /* VBOX_WITH_VMSVGA3D */
6128
6129
6130/*
6131 *
6132 * Handlers for FIFO commands.
6133 *
6134 * Every handler takes the following parameters:
6135 *
6136 * pThis The shared VGA/VMSVGA state.
6137 * pThisCC The VGA/VMSVGA state for ring-3.
6138 * pCmd The command data.
6139 */
6140
6141
6142/* SVGA_CMD_UPDATE */
6143void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6144{
6145 RT_NOREF(pThis);
6146 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6147
6148 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6149 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6150
6151 /** @todo Multiple screens? */
6152 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6153 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6154 return;
6155
6156 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6157}
6158
6159
6160/* SVGA_CMD_UPDATE_VERBOSE */
6161void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6162{
6163 RT_NOREF(pThis);
6164 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6165
6166 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6167 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6168
6169 /** @todo Multiple screens? */
6170 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6171 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6172 return;
6173
6174 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6175}
6176
6177
6178/* SVGA_CMD_RECT_FILL */
6179void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6180{
6181 RT_NOREF(pThis, pCmd);
6182 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6183
6184 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6185 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6186 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6187}
6188
6189
6190/* SVGA_CMD_RECT_COPY */
6191void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6192{
6193 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6194
6195 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6196 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6197
6198 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6199 AssertPtrReturnVoid(pScreen);
6200
6201 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6202 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6203 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6204 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6205 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6206 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6207 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6208
6209 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6210 pCmd->width, pCmd->height, pThis->vram_size);
6211 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6212}
6213
6214
6215/* SVGA_CMD_RECT_ROP_COPY */
6216void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6217{
6218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6219
6220 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6221 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6222
6223 if (pCmd->rop != SVGA_ROP_COPY)
6224 {
6225 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6226 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6227 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6228 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6229 */
6230 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6231 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6232 return;
6233 }
6234
6235 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6236 AssertPtrReturnVoid(pScreen);
6237
6238 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6239 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6240 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6241 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6242 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6243 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6244 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6245
6246 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6247 pCmd->width, pCmd->height, pThis->vram_size);
6248 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6249}
6250
6251
6252/* SVGA_CMD_DISPLAY_CURSOR */
6253void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6254{
6255 RT_NOREF(pThis, pCmd);
6256 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6257
6258 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6259 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6260 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6261}
6262
6263
6264/* SVGA_CMD_MOVE_CURSOR */
6265void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6266{
6267 RT_NOREF(pThis, pCmd);
6268 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6269
6270 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6271 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6272 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6273}
6274
6275
6276/* SVGA_CMD_DEFINE_CURSOR */
6277void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6278{
6279 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6280
6281 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6282 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6283 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6284
6285 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6286 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6287 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6288 RT_UNTRUSTED_VALIDATED_FENCE();
6289
6290 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6291 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6292 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6293
6294 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6295 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6296
6297 uint32_t const cx = pCmd->width;
6298 uint32_t const cy = pCmd->height;
6299
6300 /*
6301 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6302 * The AND data uses 8-bit aligned scanlines.
6303 * The XOR data must be starting on a 32-bit boundrary.
6304 */
6305 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6306 uint32_t cbDstAndMask = cbDstAndLine * cy;
6307 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6308 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6309
6310 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6311 AssertReturnVoid(pbCopy);
6312
6313 /* Convert the AND mask. */
6314 uint8_t *pbDst = pbCopy;
6315 uint8_t const *pbSrc = pbSrcAndMask;
6316 switch (pCmd->andMaskDepth)
6317 {
6318 case 1:
6319 if (cbSrcAndLine == cbDstAndLine)
6320 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6321 else
6322 {
6323 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6324 for (uint32_t y = 0; y < cy; y++)
6325 {
6326 memcpy(pbDst, pbSrc, cbDstAndLine);
6327 pbDst += cbDstAndLine;
6328 pbSrc += cbSrcAndLine;
6329 }
6330 }
6331 break;
6332 /* Should take the XOR mask into account for the multi-bit AND mask. */
6333 case 8:
6334 for (uint32_t y = 0; y < cy; y++)
6335 {
6336 for (uint32_t x = 0; x < cx; )
6337 {
6338 uint8_t bDst = 0;
6339 uint8_t fBit = 0x80;
6340 do
6341 {
6342 uintptr_t const idxPal = pbSrc[x] * 3;
6343 if ((( pThis->last_palette[idxPal]
6344 | (pThis->last_palette[idxPal] >> 8)
6345 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6346 bDst |= fBit;
6347 fBit >>= 1;
6348 x++;
6349 } while (x < cx && (x & 7));
6350 pbDst[(x - 1) / 8] = bDst;
6351 }
6352 pbDst += cbDstAndLine;
6353 pbSrc += cbSrcAndLine;
6354 }
6355 break;
6356 case 15:
6357 for (uint32_t y = 0; y < cy; y++)
6358 {
6359 for (uint32_t x = 0; x < cx; )
6360 {
6361 uint8_t bDst = 0;
6362 uint8_t fBit = 0x80;
6363 do
6364 {
6365 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6366 bDst |= fBit;
6367 fBit >>= 1;
6368 x++;
6369 } while (x < cx && (x & 7));
6370 pbDst[(x - 1) / 8] = bDst;
6371 }
6372 pbDst += cbDstAndLine;
6373 pbSrc += cbSrcAndLine;
6374 }
6375 break;
6376 case 16:
6377 for (uint32_t y = 0; y < cy; y++)
6378 {
6379 for (uint32_t x = 0; x < cx; )
6380 {
6381 uint8_t bDst = 0;
6382 uint8_t fBit = 0x80;
6383 do
6384 {
6385 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6386 bDst |= fBit;
6387 fBit >>= 1;
6388 x++;
6389 } while (x < cx && (x & 7));
6390 pbDst[(x - 1) / 8] = bDst;
6391 }
6392 pbDst += cbDstAndLine;
6393 pbSrc += cbSrcAndLine;
6394 }
6395 break;
6396 case 24:
6397 for (uint32_t y = 0; y < cy; y++)
6398 {
6399 for (uint32_t x = 0; x < cx; )
6400 {
6401 uint8_t bDst = 0;
6402 uint8_t fBit = 0x80;
6403 do
6404 {
6405 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6406 bDst |= fBit;
6407 fBit >>= 1;
6408 x++;
6409 } while (x < cx && (x & 7));
6410 pbDst[(x - 1) / 8] = bDst;
6411 }
6412 pbDst += cbDstAndLine;
6413 pbSrc += cbSrcAndLine;
6414 }
6415 break;
6416 case 32:
6417 for (uint32_t y = 0; y < cy; y++)
6418 {
6419 for (uint32_t x = 0; x < cx; )
6420 {
6421 uint8_t bDst = 0;
6422 uint8_t fBit = 0x80;
6423 do
6424 {
6425 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6426 bDst |= fBit;
6427 fBit >>= 1;
6428 x++;
6429 } while (x < cx && (x & 7));
6430 pbDst[(x - 1) / 8] = bDst;
6431 }
6432 pbDst += cbDstAndLine;
6433 pbSrc += cbSrcAndLine;
6434 }
6435 break;
6436 default:
6437 RTMemFreeZ(pbCopy, cbCopy);
6438 AssertFailedReturnVoid();
6439 }
6440
6441 /* Convert the XOR mask. */
6442 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6443 pbSrc = pbSrcXorMask;
6444 switch (pCmd->xorMaskDepth)
6445 {
6446 case 1:
6447 for (uint32_t y = 0; y < cy; y++)
6448 {
6449 for (uint32_t x = 0; x < cx; )
6450 {
6451 /* most significant bit is the left most one. */
6452 uint8_t bSrc = pbSrc[x / 8];
6453 do
6454 {
6455 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6456 bSrc <<= 1;
6457 x++;
6458 } while ((x & 7) && x < cx);
6459 }
6460 pbSrc += cbSrcXorLine;
6461 }
6462 break;
6463 case 8:
6464 for (uint32_t y = 0; y < cy; y++)
6465 {
6466 for (uint32_t x = 0; x < cx; x++)
6467 {
6468 uint32_t u = pThis->last_palette[pbSrc[x]];
6469 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6470 }
6471 pbSrc += cbSrcXorLine;
6472 }
6473 break;
6474 case 15: /* Src: RGB-5-5-5 */
6475 for (uint32_t y = 0; y < cy; y++)
6476 {
6477 for (uint32_t x = 0; x < cx; x++)
6478 {
6479 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6480 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6481 ((uValue >> 5) & 0x1f) << 3,
6482 ((uValue >> 10) & 0x1f) << 3, 0);
6483 }
6484 pbSrc += cbSrcXorLine;
6485 }
6486 break;
6487 case 16: /* Src: RGB-5-6-5 */
6488 for (uint32_t y = 0; y < cy; y++)
6489 {
6490 for (uint32_t x = 0; x < cx; x++)
6491 {
6492 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6493 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6494 ((uValue >> 5) & 0x3f) << 2,
6495 ((uValue >> 11) & 0x1f) << 3, 0);
6496 }
6497 pbSrc += cbSrcXorLine;
6498 }
6499 break;
6500 case 24:
6501 for (uint32_t y = 0; y < cy; y++)
6502 {
6503 for (uint32_t x = 0; x < cx; x++)
6504 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6505 pbSrc += cbSrcXorLine;
6506 }
6507 break;
6508 case 32:
6509 for (uint32_t y = 0; y < cy; y++)
6510 {
6511 for (uint32_t x = 0; x < cx; x++)
6512 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6513 pbSrc += cbSrcXorLine;
6514 }
6515 break;
6516 default:
6517 RTMemFreeZ(pbCopy, cbCopy);
6518 AssertFailedReturnVoid();
6519 }
6520
6521 /*
6522 * Pass it to the frontend/whatever.
6523 */
6524 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6525 cx, cy, pbCopy, cbCopy);
6526}
6527
6528
6529/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6530void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6531{
6532 RT_NOREF(pThis);
6533 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6534
6535 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6536 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6537
6538 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6539 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6540 RT_UNTRUSTED_VALIDATED_FENCE();
6541
6542 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6543 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6544 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6545 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6546 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6547
6548 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6549 AssertPtrReturnVoid(pCursorCopy);
6550
6551 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6552 memset(pCursorCopy, 0xff, cbAndMask);
6553 /* Colour data */
6554 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6555
6556 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6557 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6558}
6559
6560
6561/* SVGA_CMD_ESCAPE */
6562void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6563{
6564 RT_NOREF(pThis);
6565 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6566
6567 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6568
6569 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6570 {
6571 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6572 RT_UNTRUSTED_VALIDATED_FENCE();
6573
6574 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6575 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6576
6577 switch (cmd)
6578 {
6579 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6580 {
6581 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6582 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6583 RT_UNTRUSTED_VALIDATED_FENCE();
6584
6585 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6586
6587 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6588 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6589 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6590 RT_NOREF_PV(pVideoCmd);
6591 break;
6592 }
6593
6594 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6595 {
6596 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6597 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6598 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6599 RT_NOREF_PV(pVideoCmd);
6600 break;
6601 }
6602
6603 default:
6604 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6605 break;
6606 }
6607 }
6608 else
6609 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6610}
6611
6612
6613/* SVGA_CMD_DEFINE_SCREEN */
6614void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6615{
6616 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6617
6618 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6619 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6620 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6621 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6622
6623 uint32_t const idScreen = pCmd->screen.id;
6624 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6625
6626 uint32_t const uWidth = pCmd->screen.size.width;
6627 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6628
6629 uint32_t const uHeight = pCmd->screen.size.height;
6630 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6631
6632 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6633 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6634 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6635
6636 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6637 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6638
6639 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6640 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6641 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6642 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6643 RT_UNTRUSTED_VALIDATED_FENCE();
6644
6645 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6646 pScreen->fDefined = true;
6647 pScreen->fModified = true;
6648 pScreen->fuScreen = pCmd->screen.flags;
6649 pScreen->idScreen = idScreen;
6650 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6651 {
6652 /* Not blanked. */
6653 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6654 RT_UNTRUSTED_VALIDATED_FENCE();
6655
6656 pScreen->xOrigin = pCmd->screen.root.x;
6657 pScreen->yOrigin = pCmd->screen.root.y;
6658 pScreen->cWidth = uWidth;
6659 pScreen->cHeight = uHeight;
6660 pScreen->offVRAM = uScreenOffset;
6661 pScreen->cbPitch = cbPitch;
6662 pScreen->cBpp = 32;
6663 }
6664 else
6665 {
6666 /* Screen blanked. Keep old values. */
6667 }
6668
6669 pThis->svga.fGFBRegisters = false;
6670 vmsvgaR3ChangeMode(pThis, pThisCC);
6671
6672#ifdef VBOX_WITH_VMSVGA3D
6673 if (RT_LIKELY(pThis->svga.f3DEnabled))
6674 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6675#endif
6676}
6677
6678
6679/* SVGA_CMD_DESTROY_SCREEN */
6680void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6681{
6682 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6683
6684 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6685 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6686
6687 uint32_t const idScreen = pCmd->screenId;
6688 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6689 RT_UNTRUSTED_VALIDATED_FENCE();
6690
6691 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6692 pScreen->fModified = true;
6693 pScreen->fDefined = false;
6694 pScreen->idScreen = idScreen;
6695
6696#ifdef VBOX_WITH_VMSVGA3D
6697 if (RT_LIKELY(pThis->svga.f3DEnabled))
6698 vmsvga3dDestroyScreen(pThisCC, pScreen);
6699#endif
6700 vmsvgaR3ChangeMode(pThis, pThisCC);
6701}
6702
6703
6704/* SVGA_CMD_DEFINE_GMRFB */
6705void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6706{
6707 RT_NOREF(pThis);
6708 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6709
6710 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6711 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6712 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6713
6714 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6715 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6716 pSvgaR3State->GMRFB.format = pCmd->format;
6717}
6718
6719
6720/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6721void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6722{
6723 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6724
6725 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6726 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6727 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6728
6729 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6730 RT_UNTRUSTED_VALIDATED_FENCE();
6731
6732 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6733 AssertPtrReturnVoid(pScreen);
6734
6735 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6736 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6737
6738 /* Clip destRect to the screen dimensions. */
6739 SVGASignedRect screenRect;
6740 screenRect.left = 0;
6741 screenRect.top = 0;
6742 screenRect.right = pScreen->cWidth;
6743 screenRect.bottom = pScreen->cHeight;
6744 SVGASignedRect clipRect = pCmd->destRect;
6745 vmsvgaR3ClipRect(&screenRect, &clipRect);
6746 RT_UNTRUSTED_VALIDATED_FENCE();
6747
6748 uint32_t const width = clipRect.right - clipRect.left;
6749 uint32_t const height = clipRect.bottom - clipRect.top;
6750
6751 if ( width == 0
6752 || height == 0)
6753 return; /* Nothing to do. */
6754
6755 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6756 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6757
6758 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6759 * Prepare parameters for vmsvgaR3GmrTransfer.
6760 */
6761 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6762
6763 /* Destination: host buffer which describes the screen 0 VRAM.
6764 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6765 */
6766 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6767 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6768 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6769 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6770 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6771 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6772 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6773 + cbScanline * clipRect.top;
6774 int32_t const cbHstPitch = cbScanline;
6775
6776 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6777 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6778 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6779 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6780 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6781
6782 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6783 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6784 gstPtr, offGst, cbGstPitch,
6785 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6786 AssertRC(rc);
6787 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6788}
6789
6790
6791/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6792void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6793{
6794 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6795
6796 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6797 /* Note! This can fetch 3d render results as well!! */
6798 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6799 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6800
6801 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6802 RT_UNTRUSTED_VALIDATED_FENCE();
6803
6804 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6805 AssertPtrReturnVoid(pScreen);
6806
6807 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6808 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6809
6810 /* Clip destRect to the screen dimensions. */
6811 SVGASignedRect screenRect;
6812 screenRect.left = 0;
6813 screenRect.top = 0;
6814 screenRect.right = pScreen->cWidth;
6815 screenRect.bottom = pScreen->cHeight;
6816 SVGASignedRect clipRect = pCmd->srcRect;
6817 vmsvgaR3ClipRect(&screenRect, &clipRect);
6818 RT_UNTRUSTED_VALIDATED_FENCE();
6819
6820 uint32_t const width = clipRect.right - clipRect.left;
6821 uint32_t const height = clipRect.bottom - clipRect.top;
6822
6823 if ( width == 0
6824 || height == 0)
6825 return; /* Nothing to do. */
6826
6827 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6828 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6829
6830 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6831 * Prepare parameters for vmsvgaR3GmrTransfer.
6832 */
6833 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6834
6835 /* Source: host buffer which describes the screen 0 VRAM.
6836 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6837 */
6838 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6839 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6840 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6841 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6842 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6843 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6844 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6845 + cbScanline * clipRect.top;
6846 int32_t const cbHstPitch = cbScanline;
6847
6848 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6849 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6850 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6851 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6852 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6853
6854 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6855 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6856 gstPtr, offGst, cbGstPitch,
6857 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6858 AssertRC(rc);
6859}
6860
6861
6862/* SVGA_CMD_ANNOTATION_FILL */
6863void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6864{
6865 RT_NOREF(pThis);
6866 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6867
6868 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6869 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6870
6871 pSvgaR3State->colorAnnotation = pCmd->color;
6872}
6873
6874
6875/* SVGA_CMD_ANNOTATION_COPY */
6876void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6877{
6878 RT_NOREF(pThis, pCmd);
6879 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6880
6881 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6882 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6883
6884 AssertFailed();
6885}
6886
6887
6888#ifdef VBOX_WITH_VMSVGA3D
6889/* SVGA_CMD_DEFINE_GMR2 */
6890void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6891{
6892 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6893
6894 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6895 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6896
6897 /* Validate current GMR id. */
6898 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6899 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6900 RT_UNTRUSTED_VALIDATED_FENCE();
6901
6902 if (!pCmd->numPages)
6903 {
6904 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6905 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6906 }
6907 else
6908 {
6909 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6910 if (pGMR->cMaxPages)
6911 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6912
6913 /* Not sure if we should always free the descriptor, but for simplicity
6914 we do so if the new size is smaller than the current. */
6915 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6916 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6917 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6918
6919 pGMR->cMaxPages = pCmd->numPages;
6920 /* The rest is done by the REMAP_GMR2 command. */
6921 }
6922}
6923
6924
6925/* SVGA_CMD_REMAP_GMR2 */
6926void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6927{
6928 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6929
6930 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6931 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6932
6933 /* Validate current GMR id and size. */
6934 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6935 RT_UNTRUSTED_VALIDATED_FENCE();
6936 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6937 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6938 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6939 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6940
6941 if (pCmd->numPages == 0)
6942 return;
6943 RT_UNTRUSTED_VALIDATED_FENCE();
6944
6945 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6946 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6947
6948 /*
6949 * We flatten the existing descriptors into a page array, overwrite the
6950 * pages specified in this command and then recompress the descriptor.
6951 */
6952 /** @todo Optimize the GMR remap algorithm! */
6953
6954 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6955 uint64_t *paNewPage64 = NULL;
6956 if (pGMR->paDesc)
6957 {
6958 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6959
6960 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6961 AssertPtrReturnVoid(paNewPage64);
6962
6963 uint32_t idxPage = 0;
6964 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6965 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6966 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6967 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6968 RT_UNTRUSTED_VALIDATED_FENCE();
6969 }
6970
6971 /* Free the old GMR if present. */
6972 if (pGMR->paDesc)
6973 RTMemFree(pGMR->paDesc);
6974
6975 /* Allocate the maximum amount possible (everything non-continuous) */
6976 PVMSVGAGMRDESCRIPTOR paDescs;
6977 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6978 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6979
6980 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6981 {
6982 /** @todo */
6983 AssertFailed();
6984 pGMR->numDescriptors = 0;
6985 }
6986 else
6987 {
6988 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6989 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6990 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6991
6992 uint32_t cPages;
6993 if (paNewPage64)
6994 {
6995 /* Overwrite the old page array with the new page values. */
6996 if (fGCPhys64)
6997 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6998 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6999 else
7000 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
7001 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
7002
7003 /* Use the updated page array instead of the command data. */
7004 fGCPhys64 = true;
7005 paPages64 = paNewPage64;
7006 cPages = cNewTotalPages;
7007 }
7008 else
7009 cPages = pCmd->numPages;
7010
7011 /* The first page. */
7012 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
7013 * applied to paNewPage64. */
7014 RTGCPHYS GCPhys;
7015 if (fGCPhys64)
7016 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7017 else
7018 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
7019 paDescs[0].GCPhys = GCPhys;
7020 paDescs[0].numPages = 1;
7021
7022 /* Subsequent pages. */
7023 uint32_t iDescriptor = 0;
7024 for (uint32_t i = 1; i < cPages; i++)
7025 {
7026 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
7027 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
7028 else
7029 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
7030
7031 /* Continuous physical memory? */
7032 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
7033 {
7034 Assert(paDescs[iDescriptor].numPages);
7035 paDescs[iDescriptor].numPages++;
7036 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
7037 }
7038 else
7039 {
7040 iDescriptor++;
7041 paDescs[iDescriptor].GCPhys = GCPhys;
7042 paDescs[iDescriptor].numPages = 1;
7043 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
7044 }
7045 }
7046
7047 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
7048 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
7049 pGMR->numDescriptors = iDescriptor + 1;
7050 }
7051
7052 if (paNewPage64)
7053 RTMemFree(paNewPage64);
7054}
7055
7056
7057/**
7058 * Free the specified GMR
7059 *
7060 * @param pThisCC The VGA/VMSVGA state for ring-3.
7061 * @param idGMR GMR id
7062 */
7063void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7064{
7065 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7066
7067 /* Free the old descriptor if present. */
7068 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7069 if ( pGMR->numDescriptors
7070 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7071 {
7072# ifdef DEBUG_GMR_ACCESS
7073 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7074# endif
7075
7076 Assert(pGMR->paDesc);
7077 RTMemFree(pGMR->paDesc);
7078 pGMR->paDesc = NULL;
7079 pGMR->numDescriptors = 0;
7080 pGMR->cbTotal = 0;
7081 pGMR->cMaxPages = 0;
7082 }
7083 Assert(!pGMR->cMaxPages);
7084 Assert(!pGMR->cbTotal);
7085}
7086#endif /* VBOX_WITH_VMSVGA3D */
7087
7088
7089/**
7090 * Copy between a GMR and a host memory buffer.
7091 *
7092 * @returns VBox status code.
7093 * @param pThis The shared VGA/VMSVGA instance data.
7094 * @param pThisCC The VGA/VMSVGA state for ring-3.
7095 * @param enmTransferType Transfer type (read/write)
7096 * @param pbHstBuf Host buffer pointer (valid)
7097 * @param cbHstBuf Size of host buffer (valid)
7098 * @param offHst Host buffer offset of the first scanline
7099 * @param cbHstPitch Destination buffer pitch
7100 * @param gstPtr GMR description
7101 * @param offGst Guest buffer offset of the first scanline
7102 * @param cbGstPitch Guest buffer pitch
7103 * @param cbWidth Width in bytes to copy
7104 * @param cHeight Number of scanllines to copy
7105 */
7106int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7107 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7108 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7109 uint32_t cbWidth, uint32_t cHeight)
7110{
7111 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7112 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7113 int rc;
7114
7115 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7116 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7117 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7118 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7119 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7120
7121 PGMR pGMR;
7122 uint32_t cbGmr; /* The GMR size in bytes. */
7123 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7124 {
7125 pGMR = NULL;
7126 cbGmr = pThis->vram_size;
7127 }
7128 else
7129 {
7130 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7131 RT_UNTRUSTED_VALIDATED_FENCE();
7132 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7133 cbGmr = pGMR->cbTotal;
7134 }
7135
7136 /*
7137 * GMR
7138 */
7139 /* Calculate GMR offset of the data to be copied. */
7140 AssertMsgReturn(gstPtr.offset < cbGmr,
7141 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7142 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7143 VERR_INVALID_PARAMETER);
7144 RT_UNTRUSTED_VALIDATED_FENCE();
7145 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7146 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7147 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7148 VERR_INVALID_PARAMETER);
7149 RT_UNTRUSTED_VALIDATED_FENCE();
7150 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7151
7152 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7153 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7154 AssertMsgReturn(cbGmrScanline != 0,
7155 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7156 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7157 VERR_INVALID_PARAMETER);
7158 RT_UNTRUSTED_VALIDATED_FENCE();
7159 AssertMsgReturn(cbWidth <= cbGmrScanline,
7160 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7161 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7162 VERR_INVALID_PARAMETER);
7163 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7164 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7165 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7166 VERR_INVALID_PARAMETER);
7167 RT_UNTRUSTED_VALIDATED_FENCE();
7168
7169 /* How many bytes are available for the data in the GMR. */
7170 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7171
7172 /* How many scanlines would fit into the available data. */
7173 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7174 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7175 if (cbWidth <= cbGmrLastScanline)
7176 ++cGmrScanlines;
7177
7178 if (cHeight > cGmrScanlines)
7179 cHeight = cGmrScanlines;
7180
7181 AssertMsgReturn(cHeight > 0,
7182 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7183 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7184 VERR_INVALID_PARAMETER);
7185 RT_UNTRUSTED_VALIDATED_FENCE();
7186
7187 /*
7188 * Host buffer.
7189 */
7190 AssertMsgReturn(offHst < cbHstBuf,
7191 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7192 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7193 VERR_INVALID_PARAMETER);
7194
7195 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7196 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7197 AssertMsgReturn(cbHstScanline != 0,
7198 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7199 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7200 VERR_INVALID_PARAMETER);
7201 AssertMsgReturn(cbWidth <= cbHstScanline,
7202 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7203 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7204 VERR_INVALID_PARAMETER);
7205 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7206 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7207 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7208 VERR_INVALID_PARAMETER);
7209
7210 /* How many bytes are available for the data in the buffer. */
7211 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7212
7213 /* How many scanlines would fit into the available data. */
7214 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7215 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7216 if (cbWidth <= cbHstLastScanline)
7217 ++cHstScanlines;
7218
7219 if (cHeight > cHstScanlines)
7220 cHeight = cHstScanlines;
7221
7222 AssertMsgReturn(cHeight > 0,
7223 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7224 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7225 VERR_INVALID_PARAMETER);
7226
7227 uint8_t *pbHst = pbHstBuf + offHst;
7228
7229 /* Shortcut for the framebuffer. */
7230 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7231 {
7232 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7233
7234 uint8_t const *pbSrc;
7235 int32_t cbSrcPitch;
7236 uint8_t *pbDst;
7237 int32_t cbDstPitch;
7238
7239 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7240 {
7241 pbSrc = pbHst;
7242 cbSrcPitch = cbHstPitch;
7243 pbDst = pbGst;
7244 cbDstPitch = cbGstPitch;
7245 }
7246 else
7247 {
7248 pbSrc = pbGst;
7249 cbSrcPitch = cbGstPitch;
7250 pbDst = pbHst;
7251 cbDstPitch = cbHstPitch;
7252 }
7253
7254 if ( cbWidth == (uint32_t)cbGstPitch
7255 && cbGstPitch == cbHstPitch)
7256 {
7257 /* Entire scanlines, positive pitch. */
7258 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7259 }
7260 else
7261 {
7262 for (uint32_t i = 0; i < cHeight; ++i)
7263 {
7264 memcpy(pbDst, pbSrc, cbWidth);
7265
7266 pbDst += cbDstPitch;
7267 pbSrc += cbSrcPitch;
7268 }
7269 }
7270 return VINF_SUCCESS;
7271 }
7272
7273 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7274 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7275
7276 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7277 uint32_t iDesc = 0; /* Index in the descriptor array. */
7278 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7279 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7280 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7281 for (uint32_t i = 0; i < cHeight; ++i)
7282 {
7283 uint32_t cbCurrentWidth = cbWidth;
7284 uint32_t offGmrCurrent = offGmrScanline;
7285 uint8_t *pbCurrentHost = pbHstScanline;
7286
7287 /* Find the right descriptor */
7288 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7289 {
7290 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7291 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7292 ++iDesc;
7293 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7294 }
7295
7296 while (cbCurrentWidth)
7297 {
7298 uint32_t cbToCopy;
7299
7300 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7301 cbToCopy = cbCurrentWidth;
7302 else
7303 {
7304 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7305 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7306 }
7307
7308 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7309
7310 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7311
7312 /*
7313 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7314 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7315 * see @bugref{9654#c75}.
7316 */
7317 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7318 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7319 else
7320 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7321 AssertRCBreak(rc);
7322
7323 cbCurrentWidth -= cbToCopy;
7324 offGmrCurrent += cbToCopy;
7325 pbCurrentHost += cbToCopy;
7326
7327 /* Go to the next descriptor if there's anything left. */
7328 if (cbCurrentWidth)
7329 {
7330 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7331 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7332 ++iDesc;
7333 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7334 }
7335 }
7336
7337 offGmrScanline += cbGstPitch;
7338 pbHstScanline += cbHstPitch;
7339 }
7340
7341 return VINF_SUCCESS;
7342}
7343
7344
7345/**
7346 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7347 *
7348 * @param pSizeSrc Source surface dimensions.
7349 * @param pSizeDest Destination surface dimensions.
7350 * @param pBox Coordinates to be clipped.
7351 */
7352void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7353{
7354 /* Src x, w */
7355 if (pBox->srcx > pSizeSrc->width)
7356 pBox->srcx = pSizeSrc->width;
7357 if (pBox->w > pSizeSrc->width - pBox->srcx)
7358 pBox->w = pSizeSrc->width - pBox->srcx;
7359
7360 /* Src y, h */
7361 if (pBox->srcy > pSizeSrc->height)
7362 pBox->srcy = pSizeSrc->height;
7363 if (pBox->h > pSizeSrc->height - pBox->srcy)
7364 pBox->h = pSizeSrc->height - pBox->srcy;
7365
7366 /* Src z, d */
7367 if (pBox->srcz > pSizeSrc->depth)
7368 pBox->srcz = pSizeSrc->depth;
7369 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7370 pBox->d = pSizeSrc->depth - pBox->srcz;
7371
7372 /* Dest x, w */
7373 if (pBox->x > pSizeDest->width)
7374 pBox->x = pSizeDest->width;
7375 if (pBox->w > pSizeDest->width - pBox->x)
7376 pBox->w = pSizeDest->width - pBox->x;
7377
7378 /* Dest y, h */
7379 if (pBox->y > pSizeDest->height)
7380 pBox->y = pSizeDest->height;
7381 if (pBox->h > pSizeDest->height - pBox->y)
7382 pBox->h = pSizeDest->height - pBox->y;
7383
7384 /* Dest z, d */
7385 if (pBox->z > pSizeDest->depth)
7386 pBox->z = pSizeDest->depth;
7387 if (pBox->d > pSizeDest->depth - pBox->z)
7388 pBox->d = pSizeDest->depth - pBox->z;
7389}
7390
7391
7392/**
7393 * Unsigned coordinates in pBox. Clip to [0; pSize).
7394 *
7395 * @param pSize Source surface dimensions.
7396 * @param pBox Coordinates to be clipped.
7397 */
7398void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7399{
7400 /* x, w */
7401 if (pBox->x > pSize->width)
7402 pBox->x = pSize->width;
7403 if (pBox->w > pSize->width - pBox->x)
7404 pBox->w = pSize->width - pBox->x;
7405
7406 /* y, h */
7407 if (pBox->y > pSize->height)
7408 pBox->y = pSize->height;
7409 if (pBox->h > pSize->height - pBox->y)
7410 pBox->h = pSize->height - pBox->y;
7411
7412 /* z, d */
7413 if (pBox->z > pSize->depth)
7414 pBox->z = pSize->depth;
7415 if (pBox->d > pSize->depth - pBox->z)
7416 pBox->d = pSize->depth - pBox->z;
7417}
7418
7419
7420/**
7421 * Clip.
7422 *
7423 * @param pBound Bounding rectangle.
7424 * @param pRect Rectangle to be clipped.
7425 */
7426void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7427{
7428 int32_t left;
7429 int32_t top;
7430 int32_t right;
7431 int32_t bottom;
7432
7433 /* Right order. */
7434 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7435 if (pRect->left < pRect->right)
7436 {
7437 left = pRect->left;
7438 right = pRect->right;
7439 }
7440 else
7441 {
7442 left = pRect->right;
7443 right = pRect->left;
7444 }
7445 if (pRect->top < pRect->bottom)
7446 {
7447 top = pRect->top;
7448 bottom = pRect->bottom;
7449 }
7450 else
7451 {
7452 top = pRect->bottom;
7453 bottom = pRect->top;
7454 }
7455
7456 if (left < pBound->left)
7457 left = pBound->left;
7458 if (right < pBound->left)
7459 right = pBound->left;
7460
7461 if (left > pBound->right)
7462 left = pBound->right;
7463 if (right > pBound->right)
7464 right = pBound->right;
7465
7466 if (top < pBound->top)
7467 top = pBound->top;
7468 if (bottom < pBound->top)
7469 bottom = pBound->top;
7470
7471 if (top > pBound->bottom)
7472 top = pBound->bottom;
7473 if (bottom > pBound->bottom)
7474 bottom = pBound->bottom;
7475
7476 pRect->left = left;
7477 pRect->right = right;
7478 pRect->top = top;
7479 pRect->bottom = bottom;
7480}
7481
7482
7483/**
7484 * Clip.
7485 *
7486 * @param pBound Bounding rectangle.
7487 * @param pRect Rectangle to be clipped.
7488 */
7489void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7490{
7491 uint32_t const leftBound = pBound->x;
7492 uint32_t const rightBound = pBound->x + pBound->w;
7493 uint32_t const topBound = pBound->y;
7494 uint32_t const bottomBound = pBound->y + pBound->h;
7495
7496 uint32_t x = pRect->x;
7497 uint32_t y = pRect->y;
7498 uint32_t w = pRect->w;
7499 uint32_t h = pRect->h;
7500
7501 /* Make sure that right and bottom coordinates can be safely computed. */
7502 if (x > rightBound)
7503 x = rightBound;
7504 if (w > rightBound - x)
7505 w = rightBound - x;
7506 if (y > bottomBound)
7507 y = bottomBound;
7508 if (h > bottomBound - y)
7509 h = bottomBound - y;
7510
7511 /* Switch from x, y, w, h to left, top, right, bottom. */
7512 uint32_t left = x;
7513 uint32_t right = x + w;
7514 uint32_t top = y;
7515 uint32_t bottom = y + h;
7516
7517 /* A standard left, right, bottom, top clipping. */
7518 if (left < leftBound)
7519 left = leftBound;
7520 if (right < leftBound)
7521 right = leftBound;
7522
7523 if (left > rightBound)
7524 left = rightBound;
7525 if (right > rightBound)
7526 right = rightBound;
7527
7528 if (top < topBound)
7529 top = topBound;
7530 if (bottom < topBound)
7531 bottom = topBound;
7532
7533 if (top > bottomBound)
7534 top = bottomBound;
7535 if (bottom > bottomBound)
7536 bottom = bottomBound;
7537
7538 /* Back to x, y, w, h representation. */
7539 pRect->x = left;
7540 pRect->y = top;
7541 pRect->w = right - left;
7542 pRect->h = bottom - top;
7543}
7544
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette