VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 86905

Last change on this file since 86905 was 86905, checked in by vboxsync, 4 years ago

Devices/Graphics: use new vmsvga headers, stubs for more commands. bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 229.8 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 86905 2020-11-17 23:36:12Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344#if !defined(VMSVGA3D_DX)
345# ifdef VBOX_WITH_VMSVGA3D
346/*
347 * Stub for old backends.
348 */
349int vmsvga3dQueryInterface(PVGASTATECC pThisCC, char const *pszInterfaceName, void *pvInterfaceFuncs, size_t cbInterfaceFuncs)
350{
351 RT_NOREF(pThisCC, pszInterfaceName, pvInterfaceFuncs, cbInterfaceFuncs);
352 return VERR_NOT_IMPLEMENTED;
353}
354# endif
355#endif
356
357
358/*
359 *
360 * Guest-Backed Objects (GBO).
361 *
362 */
363
364/**
365 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
366 *
367 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
368 * @param pVM VM Handle.
369 * @param pVCpu The cross context CPU structure for the calling EMT.
370 * @param GCPhys The physical address the guest is writing to.
371 * @param pvPhys The HC mapping of that address.
372 * @param pvBuf What the guest is reading/writing.
373 * @param cbBuf How much it's reading/writing.
374 * @param enmAccessType The access type.
375 * @param enmOrigin Who is making the access.
376 * @param pvUser User argument.
377 */
378DECLCALLBACK(VBOXSTRICTRC)
379vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
380 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
381{
382 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
383
384 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
385 return VINF_PGM_HANDLER_DO_DEFAULT;
386
387 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
388 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
389 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
390 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
391
392 /*
393 * The guest is not allowed to access the memory.
394 * Set the error condition.
395 */
396 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
397
398 /* Try to find the GBO which the guest is accessing. */
399 char const *pszTarget = NULL;
400 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
401 {
402 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
403 if (pGbo->cDescriptors)
404 {
405 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
406 {
407 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
408 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
409 {
410 switch (i)
411 {
412 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
413 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
414 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
415 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
416 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
417 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
418 default: pszTarget = "Unknown OTABLE"; break;
419 }
420 break;
421 }
422 }
423 }
424 }
425
426 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
427 "%.*Rhxd\n",
428 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
429
430 return VINF_PGM_HANDLER_DO_DEFAULT;
431}
432
433
434static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
435{
436 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
437
438 /*
439 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
440 * Content of the root page depends on the ptDepth value:
441 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
442 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
443 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
444 * The code below extracts the page addresses of the GBO.
445 */
446
447 /* Verify and normalize the ptDepth value. */
448 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
449 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
450 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
451 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
452 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
453 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
454 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
455 {
456 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
457 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
458 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
459 }
460 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
461 { }
462 else
463 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
464
465 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
466
467 pGbo->cbTotal = sizeInBytes;
468 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
469
470 /* Allocate the maximum amount possible (everything non-continuous) */
471 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
472 AssertReturn(paDescriptors, VERR_NO_MEMORY);
473
474 int rc = VINF_SUCCESS;
475 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
476 {
477 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
478 RTMemFree(paDescriptors),
479 VERR_INVALID_PARAMETER);
480
481 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
482 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
483 paDescriptors[0].GCPhys = GCPhys;
484 paDescriptors[0].cPages = 1;
485 }
486 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
487 {
488 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
489 RTMemFree(paDescriptors),
490 VERR_INVALID_PARAMETER);
491
492 /* Read the root page. */
493 uint8_t au8RootPage[X86_PAGE_SIZE];
494 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
495 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
496 if (RT_SUCCESS(rc))
497 {
498 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
499 PPN *paPPN32 = (PPN *)&au8RootPage[0];
500 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
501 {
502 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
503 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
504 paDescriptors[iPPN].GCPhys = GCPhys;
505 paDescriptors[iPPN].cPages = 1;
506 }
507 }
508 }
509 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
510 {
511 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
512 RTMemFree(paDescriptors),
513 VERR_INVALID_PARAMETER);
514
515 /* Read the Level2 root page. */
516 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
517 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
518 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
519 if (RT_SUCCESS(rc))
520 {
521 uint32_t cPagesLeft = pGbo->cTotalPages;
522
523 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
524 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
525
526 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
527 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
528 {
529 /* Read the Level1 root page. */
530 uint8_t au8RootPage[X86_PAGE_SIZE];
531 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
532 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
533 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
534 if (RT_SUCCESS(rc))
535 {
536 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
537 PPN *paPPN32 = (PPN *)&au8RootPage[0];
538
539 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
540 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
541 {
542 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
545 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
546 }
547 cPagesLeft -= cPPNs;
548 }
549 }
550 }
551 }
552 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
553 {
554 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
555 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
556 paDescriptors[0].GCPhys = GCPhys;
557 paDescriptors[0].cPages = pGbo->cTotalPages;
558 }
559 else
560 {
561 AssertFailed();
562 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
563 }
564
565 /* Compress the descriptors. */
566 if (ptDepth != SVGA3D_MOBFMT_RANGE)
567 {
568 uint32_t iDescriptor = 0;
569 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
570 {
571 /* Continuous physical memory? */
572 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
573 {
574 Assert(paDescriptors[iDescriptor].cPages);
575 paDescriptors[iDescriptor].cPages++;
576 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
577 }
578 else
579 {
580 iDescriptor++;
581 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
582 paDescriptors[iDescriptor].cPages = 1;
583 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
584 }
585 }
586
587 pGbo->cDescriptors = iDescriptor + 1;
588 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
589 }
590 else
591 pGbo->cDescriptors = 1;
592
593 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
594 {
595 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
596 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
597 }
598 else
599 pGbo->paDescriptors = paDescriptors;
600
601 if (fWriteProtected)
602 {
603 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
604 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
605 {
606 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
607 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
608 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
609 AssertRC(rc);
610 }
611 }
612
613 return VINF_SUCCESS;
614}
615
616
617static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
618{
619 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
620 {
621 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
622 {
623 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
624 {
625 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
626 AssertRC(rc);
627 }
628 }
629 RTMemFree(pGbo->paDescriptors);
630 RT_ZERO(pGbo);
631 }
632}
633
634
635typedef enum VMSVGAGboTransferDirection
636{
637 VMSVGAGboTransferDirection_Read,
638 VMSVGAGboTransferDirection_Write,
639} VMSVGAGboTransferDirection;
640
641static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
642 uint32_t off, void *pvData, uint32_t cbData,
643 VMSVGAGboTransferDirection enmDirection)
644{
645// ASMBreakpoint();
646 int rc = VINF_SUCCESS;
647 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
648
649 /* Find the right descriptor */
650 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
651 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
652 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
653 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
654 {
655 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
656 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
657 ++iDescriptor;
658 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
659 }
660
661 while (cbData)
662 {
663 uint32_t cbToCopy;
664 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
665 cbToCopy = cbData;
666 else
667 {
668 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
669 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
670 }
671
672 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
673 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
674
675 if (enmDirection == VMSVGAGboTransferDirection_Read)
676 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
677 else
678 rc = PDMDevHlpPCIPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
679 AssertRCBreak(rc);
680
681 cbData -= cbToCopy;
682 off += cbToCopy;
683 pu8CurrentHost += cbToCopy;
684
685 /* Go to the next descriptor if there's anything left. */
686 if (cbData)
687 {
688 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
689 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
690 ++iDescriptor;
691 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
692 }
693 }
694 return rc;
695}
696
697
698static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
699 uint32_t off, void const *pvData, uint32_t cbData)
700{
701 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
702 off, (void *)pvData, cbData,
703 VMSVGAGboTransferDirection_Write);
704}
705
706
707static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
708 uint32_t off, void *pvData, uint32_t cbData)
709{
710 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
711 off, pvData, cbData,
712 VMSVGAGboTransferDirection_Read);
713}
714
715
716/*
717 *
718 * Object Tables.
719 *
720 */
721
722static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
723 uint32_t idx, uint32_t cbEntry)
724{
725 RT_NOREF(pSvgaR3State);
726
727 /* The table must exist and the index must be within the table. */
728 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
729 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
730 RT_UNTRUSTED_VALIDATED_FENCE();
731 return VINF_SUCCESS;
732}
733
734
735static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
736 uint32_t idx, uint32_t cbEntry,
737 void *pvData, uint32_t cbData)
738{
739 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
740
741 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
742 if (RT_SUCCESS(rc))
743 {
744 uint32_t const off = idx * cbEntry;
745 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
746 }
747 return rc;
748}
749
750static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
751 uint32_t idx, uint32_t cbEntry,
752 void const *pvData, uint32_t cbData)
753{
754 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
755
756 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
757 if (RT_SUCCESS(rc))
758 {
759 uint32_t const off = idx * cbEntry;
760 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
761 }
762 return rc;
763}
764
765
766/*
767 *
768 * The guest's Memory OBjects (MOB).
769 *
770 */
771
772static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
773 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
774 bool fGCPhys64, PVMSVGAMOB pMob)
775{
776 RT_ZERO(*pMob);
777
778 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
779 SVGAOTableMobEntry entry;
780 entry.ptDepth = ptDepth;
781 entry.sizeInBytes = sizeInBytes;
782 entry.base = baseAddress;
783 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
784 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
785 if (RT_SUCCESS(rc))
786 {
787 /* Create the corresponding GBO. */
788 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
789 if (RT_SUCCESS(rc))
790 {
791 /* Add to the tree of known GBOs and the LRU list. */
792 pMob->Core.Key = mobid;
793 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
794 {
795 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
796 return VINF_SUCCESS;
797 }
798
799 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
800 }
801 }
802
803 return rc;
804}
805
806
807static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
808{
809 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
810 SVGAOTableMobEntry entry;
811 RT_ZERO(entry);
812 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
813 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
814
815 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
816 if (pMob)
817 {
818 RTListNodeRemove(&pMob->nodeLRU);
819 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
820 RTMemFree(pMob);
821 return VINF_SUCCESS;
822 }
823
824 return VERR_INVALID_PARAMETER;
825}
826
827
828static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
829{
830 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
831 if (pMob)
832 {
833 /* Move to the head of the LRU list. */
834 RTListNodeRemove(&pMob->nodeLRU);
835 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
836 }
837
838 return pMob;
839}
840
841/*
842 * Screen objects.
843 */
844VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
845{
846 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
847 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
848 && pSVGAState
849 && pSVGAState->aScreens[idScreen].fDefined)
850 {
851 return &pSVGAState->aScreens[idScreen];
852 }
853 return NULL;
854}
855
856void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
857{
858#ifdef VBOX_WITH_VMSVGA3D
859 if (pThis->svga.f3DEnabled)
860 {
861 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
862 {
863 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
864 if (pScreen)
865 vmsvga3dDestroyScreen(pThisCC, pScreen);
866 }
867 }
868#else
869 RT_NOREF(pThis, pThisCC);
870#endif
871}
872
873
874/**
875 * Copy a rectangle of pixels within guest VRAM.
876 */
877static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
878 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
879{
880 if (!width || !height)
881 return; /* Nothing to do, don't even bother. */
882
883 /*
884 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
885 * corresponding to the current display mode.
886 */
887 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
888 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
889 uint8_t const *pSrc;
890 uint8_t *pDst;
891 unsigned const cbRectWidth = width * cbPixel;
892 unsigned uMaxOffset;
893
894 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
895 if (uMaxOffset >= cbFrameBuffer)
896 {
897 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
898 return; /* Just don't listen to a bad guest. */
899 }
900
901 pSrc = pDst = pThisCC->pbVRam;
902 pSrc += srcY * cbScanline + srcX * cbPixel;
903 pDst += dstY * cbScanline + dstX * cbPixel;
904
905 if (srcY >= dstY)
906 {
907 /* Source below destination, copy top to bottom. */
908 for (; height > 0; height--)
909 {
910 memmove(pDst, pSrc, cbRectWidth);
911 pSrc += cbScanline;
912 pDst += cbScanline;
913 }
914 }
915 else
916 {
917 /* Source above destination, copy bottom to top. */
918 pSrc += cbScanline * (height - 1);
919 pDst += cbScanline * (height - 1);
920 for (; height > 0; height--)
921 {
922 memmove(pDst, pSrc, cbRectWidth);
923 pSrc -= cbScanline;
924 pDst -= cbScanline;
925 }
926 }
927}
928
929
930/**
931 * Common worker for changing the pointer shape.
932 *
933 * @param pThisCC The VGA/VMSVGA state for ring-3.
934 * @param pSVGAState The VMSVGA ring-3 instance data.
935 * @param fAlpha Whether there is alpha or not.
936 * @param xHot Hotspot x coordinate.
937 * @param yHot Hotspot y coordinate.
938 * @param cx Width.
939 * @param cy Height.
940 * @param pbData Heap copy of the cursor data. Consumed.
941 * @param cbData The size of the data.
942 */
943static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
944 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
945{
946 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
947#ifdef LOG_ENABLED
948 if (LogIs2Enabled())
949 {
950 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
951 if (!fAlpha)
952 {
953 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
954 for (uint32_t y = 0; y < cy; y++)
955 {
956 Log2(("%3u:", y));
957 uint8_t const *pbLine = &pbData[y * cbAndLine];
958 for (uint32_t x = 0; x < cx; x += 8)
959 {
960 uint8_t b = pbLine[x / 8];
961 char szByte[12];
962 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
963 szByte[1] = b & 0x40 ? '*' : ' ';
964 szByte[2] = b & 0x20 ? '*' : ' ';
965 szByte[3] = b & 0x10 ? '*' : ' ';
966 szByte[4] = b & 0x08 ? '*' : ' ';
967 szByte[5] = b & 0x04 ? '*' : ' ';
968 szByte[6] = b & 0x02 ? '*' : ' ';
969 szByte[7] = b & 0x01 ? '*' : ' ';
970 szByte[8] = '\0';
971 Log2(("%s", szByte));
972 }
973 Log2(("\n"));
974 }
975 }
976
977 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
978 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
979 for (uint32_t y = 0; y < cy; y++)
980 {
981 Log2(("%3u:", y));
982 uint32_t const *pu32Line = &pu32Xor[y * cx];
983 for (uint32_t x = 0; x < cx; x++)
984 Log2((" %08x", pu32Line[x]));
985 Log2(("\n"));
986 }
987 }
988#endif
989
990 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
991 AssertRC(rc);
992
993 if (pSVGAState->Cursor.fActive)
994 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
995
996 pSVGAState->Cursor.fActive = true;
997 pSVGAState->Cursor.xHotspot = xHot;
998 pSVGAState->Cursor.yHotspot = yHot;
999 pSVGAState->Cursor.width = cx;
1000 pSVGAState->Cursor.height = cy;
1001 pSVGAState->Cursor.cbData = cbData;
1002 pSVGAState->Cursor.pData = pbData;
1003}
1004
1005
1006#ifdef VBOX_WITH_VMSVGA3D
1007
1008/*
1009 * SVGA_3D_CMD_* handlers.
1010 */
1011
1012
1013/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1014 *
1015 * @param pThisCC The VGA/VMSVGA state for the current context.
1016 * @param pCmd The VMSVGA command.
1017 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1018 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1019 */
1020static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1021 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1022{
1023 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1024 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1025 RT_UNTRUSTED_VALIDATED_FENCE();
1026
1027 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1028 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1029 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1030 */
1031 uint32_t cRemainingMipLevels = cMipLevelSizes;
1032 uint32_t cFaces = 0;
1033 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1034 {
1035 if (pCmd->face[i].numMipLevels == 0)
1036 break;
1037
1038 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1039 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1040
1041 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1042 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1043 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1044
1045 ++cFaces;
1046 }
1047 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1048 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1049
1050 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1051 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1052
1053 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1054 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1055 RT_UNTRUSTED_VALIDATED_FENCE();
1056
1057 /* Verify paMipLevelSizes */
1058 uint32_t cWidth = paMipLevelSizes[0].width;
1059 uint32_t cHeight = paMipLevelSizes[0].height;
1060 uint32_t cDepth = paMipLevelSizes[0].depth;
1061 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1062 {
1063 cWidth >>= 1;
1064 if (cWidth == 0) cWidth = 1;
1065 cHeight >>= 1;
1066 if (cHeight == 0) cHeight = 1;
1067 cDepth >>= 1;
1068 if (cDepth == 0) cDepth = 1;
1069 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1070 {
1071 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1072 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1073 && cHeight == paMipLevelSizes[iMipLevelSize].height
1074 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1075 }
1076 }
1077 RT_UNTRUSTED_VALIDATED_FENCE();
1078
1079 /* Create the surface. */
1080 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1081 pCmd->multisampleCount, pCmd->autogenFilter,
1082 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1083}
1084
1085
1086/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1087static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1088{
1089 ASMBreakpoint();
1090 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1091
1092 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1093
1094 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1095 /* Allocate a structure for the MOB. */
1096 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1097 AssertPtrReturnVoid(pMob);
1098
1099 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1100 if (RT_SUCCESS(rc))
1101 {
1102 return;
1103 }
1104
1105 AssertFailed();
1106
1107 RTMemFree(pMob);
1108}
1109
1110
1111/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1112static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1113{
1114// ASMBreakpoint();
1115 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1116
1117 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1118
1119 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1120 if (RT_SUCCESS(rc))
1121 {
1122 return;
1123 }
1124
1125 AssertFailed();
1126}
1127
1128
1129/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1130static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1131{
1132// ASMBreakpoint();
1133 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1134
1135 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1136 SVGAOTableSurfaceEntry entry;
1137 RT_ZERO(entry);
1138 entry.format = pCmd->format;
1139 entry.surface1Flags = pCmd->surfaceFlags;
1140 entry.numMipLevels = pCmd->numMipLevels;
1141 entry.multisampleCount = pCmd->multisampleCount;
1142 entry.autogenFilter = pCmd->autogenFilter;
1143 entry.size = pCmd->size;
1144 entry.mobid = SVGA_ID_INVALID;
1145 // entry.arraySize = 0;
1146 // entry.mobPitch = 0;
1147 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1148 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1149 if (RT_SUCCESS(rc))
1150 {
1151 /* Create the host surface. */
1152 /** @todo fGBO = true flag. */
1153 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1154 pCmd->multisampleCount, pCmd->autogenFilter,
1155 pCmd->numMipLevels, &pCmd->size);
1156 }
1157}
1158
1159
1160/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1161static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1162{
1163// ASMBreakpoint();
1164 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1165
1166 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1167 SVGAOTableSurfaceEntry entry;
1168 RT_ZERO(entry);
1169 entry.mobid = SVGA_ID_INVALID;
1170 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1171 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1172
1173 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1174}
1175
1176
1177/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1178static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1179{
1180// ASMBreakpoint();
1181 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1182 RT_NOREF(pCmd, pSvgaR3State);
1183
1184 /* Assign the mobid to the surface. */
1185 int rc = VINF_SUCCESS;
1186 if (pCmd->mobid != SVGA_ID_INVALID)
1187 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1188 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1189 if (RT_SUCCESS(rc))
1190 {
1191 SVGAOTableSurfaceEntry entry;
1192 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1193 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1194 if (RT_SUCCESS(rc))
1195 {
1196 entry.mobid = pCmd->mobid;
1197 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1198 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1199 if (RT_SUCCESS(rc))
1200 {
1201 /* */
1202 }
1203 }
1204 }
1205}
1206
1207
1208#ifdef DUMP_BITMAPS
1209static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1210{
1211 if (pMap->cbPixel != 4)
1212 return VERR_NOT_SUPPORTED;
1213
1214 int const w = pMap->box.w;
1215 int const h = pMap->box.h;
1216
1217 const int cbBitmap = w * h * 4;
1218
1219 FILE *f = fopen(pszFilename, "wb");
1220 if (!f)
1221 return VERR_FILE_NOT_FOUND;
1222
1223 {
1224 BMPFILEHDR fileHdr;
1225 RT_ZERO(fileHdr);
1226 fileHdr.uType = BMP_HDR_MAGIC;
1227 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1228 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1229
1230 BMPWIN3XINFOHDR coreHdr;
1231 RT_ZERO(coreHdr);
1232 coreHdr.cbSize = sizeof(coreHdr);
1233 coreHdr.uWidth = w;
1234 coreHdr.uHeight = -h;
1235 coreHdr.cPlanes = 1;
1236 coreHdr.cBits = 32;
1237 coreHdr.cbSizeImage = cbBitmap;
1238
1239 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1240 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1241 }
1242
1243 if (pMap->cbPixel == 4)
1244 {
1245 const uint8_t *s = (uint8_t *)pMap->pvData;
1246 for (int32_t y = 0; y < h; ++y)
1247 {
1248 fwrite(s, 1, w * pMap->cbPixel, f);
1249
1250 s += pMap->cbRowPitch;
1251 }
1252 }
1253
1254 fclose(f);
1255
1256 return VINF_SUCCESS;
1257}
1258
1259
1260void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1261{
1262 static int idxBitmap = 0;
1263 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1264 vmsvga3dBmpWrite(pszFilename, pMap);
1265 RTStrFree(pszFilename);
1266}
1267#endif /* DUMP_BITMAPS */
1268
1269
1270/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1271static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1272{
1273// ASMBreakpoint();
1274 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1275
1276 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1277 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1278
1279 /* "update a surface from its backing MOB." */
1280 SVGAOTableSurfaceEntry entrySurface;
1281 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1282 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1283 if (RT_SUCCESS(rc))
1284 {
1285 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1286 if (pMob)
1287 {
1288 VMSVGA3D_MAPPED_SURFACE map;
1289 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1290 if (RT_SUCCESS(rc))
1291 {
1292 /* Copy MOB -> mapped surface. */
1293 uint32_t offSrc = pCmd->box.x * map.cbPixel
1294 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1295 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1296 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1297 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1298 {
1299 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1300 {
1301 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1302 if (RT_FAILURE(rc))
1303 break;
1304
1305 pu8Dst += map.cbRowPitch;
1306 offSrc += entrySurface.size.width * map.cbPixel;
1307 }
1308
1309 pu8Dst += map.cbDepthPitch;
1310 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1311 }
1312
1313 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1314
1315 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1316 }
1317 }
1318 }
1319}
1320
1321
1322/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1323static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1324{
1325// ASMBreakpoint();
1326 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1327 RT_NOREF(pSvgaR3State, pCmd);
1328 /** @todo Implement. */
1329}
1330
1331
1332/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1333static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1334{
1335 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1336
1337 /*
1338 * Create a GBO for the table.
1339 */
1340 PVMSVGAGBO pGbo;
1341 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1342 {
1343 RT_UNTRUSTED_VALIDATED_FENCE();
1344 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1345 }
1346 else
1347 {
1348 ASSERT_GUEST_FAILED();
1349 pGbo = NULL;
1350 }
1351
1352 if (pGbo)
1353 {
1354 /* Recreate. */
1355 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1356 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1357 AssertRC(rc);
1358 }
1359}
1360
1361
1362/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1363static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1364{
1365// ASMBreakpoint();
1366 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1367
1368 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1369 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1370 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1371 RT_UNTRUSTED_VALIDATED_FENCE();
1372
1373 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1374 SVGAOTableScreenTargetEntry entry;
1375 RT_ZERO(entry);
1376 entry.image.sid = SVGA_ID_INVALID;
1377 // entry.image.face = 0;
1378 // entry.image.mipmap = 0;
1379 entry.width = pCmd->width;
1380 entry.height = pCmd->height;
1381 entry.xRoot = pCmd->xRoot;
1382 entry.yRoot = pCmd->yRoot;
1383 entry.flags = pCmd->flags;
1384 entry.dpi = pCmd->dpi;
1385 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1386 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1387 if (RT_SUCCESS(rc))
1388 {
1389 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1390 /** @todo Generic screen object/target interface. */
1391 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1392 pScreen->fDefined = true;
1393 pScreen->fModified = true;
1394 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1395 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1396 pScreen->idScreen = pCmd->stid;
1397
1398 pScreen->xOrigin = pCmd->xRoot;
1399 pScreen->yOrigin = pCmd->yRoot;
1400 pScreen->cWidth = pCmd->width;
1401 pScreen->cHeight = pCmd->height;
1402 pScreen->offVRAM = 0; /* Always for screen targets, they use either a separate memory buffer or a host window. */
1403 pScreen->cbPitch = pCmd->width * 4;
1404 pScreen->cBpp = 32;
1405
1406 if (RT_LIKELY(pThis->svga.f3DEnabled))
1407 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1408
1409 if (!pScreen->pHwScreen)
1410 {
1411 /* System memory buffer. */
1412 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1413 }
1414
1415 pThis->svga.fGFBRegisters = false;
1416 vmsvgaR3ChangeMode(pThis, pThisCC);
1417 }
1418}
1419
1420
1421/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1422static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1423{
1424// ASMBreakpoint();
1425 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1426
1427 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1428 RT_UNTRUSTED_VALIDATED_FENCE();
1429
1430 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1431 SVGAOTableScreenTargetEntry entry;
1432 RT_ZERO(entry);
1433 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1434 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1435 if (RT_SUCCESS(rc))
1436 {
1437 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1438 /** @todo Generic screen object/target interface. */
1439 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1440 pScreen->fModified = true;
1441 pScreen->fDefined = false;
1442 pScreen->idScreen = pCmd->stid;
1443
1444 if (RT_LIKELY(pThis->svga.f3DEnabled))
1445 vmsvga3dDestroyScreen(pThisCC, pScreen);
1446
1447 vmsvgaR3ChangeMode(pThis, pThisCC);
1448
1449 RTMemFree(pScreen->pvScreenBitmap);
1450 pScreen->pvScreenBitmap = NULL;
1451 }
1452}
1453
1454
1455/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1456static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1457{
1458// ASMBreakpoint();
1459 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1460
1461 /* "Binding a surface to a Screen Target the same as flipping" */
1462
1463 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1464 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1465 RT_UNTRUSTED_VALIDATED_FENCE();
1466
1467 /* Assign the surface to the screen target. */
1468 int rc = VINF_SUCCESS;
1469 if (pCmd->image.sid != SVGA_ID_INVALID)
1470 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1471 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1472 if (RT_SUCCESS(rc))
1473 {
1474 SVGAOTableScreenTargetEntry entry;
1475 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1476 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1477 if (RT_SUCCESS(rc))
1478 {
1479 entry.image = pCmd->image;
1480 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1481 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1482 if (RT_SUCCESS(rc))
1483 {
1484 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1485 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1486 AssertRC(rc);
1487 }
1488 }
1489 }
1490}
1491
1492
1493/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1494static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1495{
1496// ASMBreakpoint();
1497 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1498
1499 /* Update the screen target from its backing surface. */
1500 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1501 RT_UNTRUSTED_VALIDATED_FENCE();
1502
1503 /* Get the screen target info. */
1504 SVGAOTableScreenTargetEntry entryScreenTarget;
1505 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1506 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1507 if (RT_SUCCESS(rc))
1508 {
1509 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1510 RT_UNTRUSTED_VALIDATED_FENCE();
1511
1512 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1513 {
1514 SVGAOTableSurfaceEntry entrySurface;
1515 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1516 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1517 if (RT_SUCCESS(rc))
1518 {
1519 /* Copy entrySurface.mobid content to the screen target. */
1520 if (entrySurface.mobid != SVGA_ID_INVALID)
1521 {
1522 RT_UNTRUSTED_VALIDATED_FENCE();
1523 SVGA3dRect targetRect = pCmd->rect;
1524
1525 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1526 if (pScreen->pHwScreen)
1527 {
1528 /* Copy the screen target surface to the backend's screen. */
1529 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1530 }
1531 else if (pScreen->pvScreenBitmap)
1532 {
1533 /* Copy the screen target surface to the memory buffer. */
1534 VMSVGA3D_MAPPED_SURFACE map;
1535 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1536 if (RT_SUCCESS(rc))
1537 {
1538 uint8_t const *pu8Src = (uint8_t *)map.pvData
1539 + targetRect.x * map.cbPixel
1540 + targetRect.y * map.cbRowPitch;
1541 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1542 + targetRect.x * map.cbPixel
1543 + targetRect.y * map.box.w * map.cbPixel;
1544 for (uint32_t y = 0; y < targetRect.h; ++y)
1545 {
1546 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1547
1548 pu8Src += map.cbRowPitch;
1549 pu8Dst += map.box.w * map.cbPixel;
1550 }
1551
1552 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1553
1554 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1555 }
1556 else
1557 AssertFailed();
1558 }
1559 }
1560 }
1561 }
1562 }
1563}
1564
1565
1566/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1567static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1568{
1569// ASMBreakpoint();
1570 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1571
1572 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1573
1574 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1575 /* Allocate a structure for the MOB. */
1576 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1577 AssertPtrReturnVoid(pMob);
1578
1579 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1580 if (RT_SUCCESS(rc))
1581 {
1582 return;
1583 }
1584
1585 RTMemFree(pMob);
1586}
1587
1588
1589/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1590static void vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd)
1591{
1592ASMBreakpoint();
1593 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1594 if (pSvgaR3State->pFuncsDX)
1595 {
1596 RT_NOREF(pCmd);
1597 pSvgaR3State->pFuncsDX->pfnDXDefineContext(pThisCC->svga.p3dState);
1598 }
1599}
1600
1601
1602/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1603static void vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd)
1604{
1605ASMBreakpoint();
1606 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1607 if (pSvgaR3State->pFuncsDX)
1608 {
1609 RT_NOREF(pCmd);
1610 pSvgaR3State->pFuncsDX->pfnDXDestroyContext(pThisCC->svga.p3dState);
1611 }
1612}
1613
1614
1615/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1616static void vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd)
1617{
1618ASMBreakpoint();
1619 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1620 if (pSvgaR3State->pFuncsDX)
1621 {
1622 RT_NOREF(pCmd);
1623 pSvgaR3State->pFuncsDX->pfnDXBindContext(pThisCC->svga.p3dState);
1624 }
1625}
1626
1627
1628/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1629static void vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd)
1630{
1631ASMBreakpoint();
1632 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1633 if (pSvgaR3State->pFuncsDX)
1634 {
1635 RT_NOREF(pCmd);
1636 pSvgaR3State->pFuncsDX->pfnDXReadbackContext(pThisCC->svga.p3dState);
1637 }
1638}
1639
1640
1641/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1642static void vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateContext const *pCmd)
1643{
1644ASMBreakpoint();
1645 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1646 if (pSvgaR3State->pFuncsDX)
1647 {
1648 RT_NOREF(pCmd);
1649 pSvgaR3State->pFuncsDX->pfnDXInvalidateContext(pThisCC->svga.p3dState);
1650 }
1651}
1652
1653
1654/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1655static void vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd)
1656{
1657ASMBreakpoint();
1658 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1659 if (pSvgaR3State->pFuncsDX)
1660 {
1661 RT_NOREF(pCmd);
1662 pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer(pThisCC->svga.p3dState);
1663 }
1664}
1665
1666
1667/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
1668static void vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, SVGA3dCmdDXSetShaderResources const *pCmd)
1669{
1670ASMBreakpoint();
1671 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1672 if (pSvgaR3State->pFuncsDX)
1673 {
1674 RT_NOREF(pCmd);
1675 pSvgaR3State->pFuncsDX->pfnDXSetShaderResources(pThisCC->svga.p3dState);
1676 }
1677}
1678
1679
1680/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
1681static void vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, SVGA3dCmdDXSetShader const *pCmd)
1682{
1683ASMBreakpoint();
1684 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1685 if (pSvgaR3State->pFuncsDX)
1686 {
1687 RT_NOREF(pCmd);
1688 pSvgaR3State->pFuncsDX->pfnDXSetShader(pThisCC->svga.p3dState);
1689 }
1690}
1691
1692
1693/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
1694static void vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, SVGA3dCmdDXSetSamplers const *pCmd)
1695{
1696ASMBreakpoint();
1697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1698 if (pSvgaR3State->pFuncsDX)
1699 {
1700 RT_NOREF(pCmd);
1701 pSvgaR3State->pFuncsDX->pfnDXSetSamplers(pThisCC->svga.p3dState);
1702 }
1703}
1704
1705
1706/* SVGA_3D_CMD_DX_DRAW 1152 */
1707static void vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, SVGA3dCmdDXDraw const *pCmd)
1708{
1709ASMBreakpoint();
1710 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1711 if (pSvgaR3State->pFuncsDX)
1712 {
1713 RT_NOREF(pCmd);
1714 pSvgaR3State->pFuncsDX->pfnDXDraw(pThisCC->svga.p3dState);
1715 }
1716}
1717
1718
1719/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
1720static void vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexed const *pCmd)
1721{
1722ASMBreakpoint();
1723 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1724 if (pSvgaR3State->pFuncsDX)
1725 {
1726 RT_NOREF(pCmd);
1727 pSvgaR3State->pFuncsDX->pfnDXDrawIndexed(pThisCC->svga.p3dState);
1728 }
1729}
1730
1731
1732/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
1733static void vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, SVGA3dCmdDXDrawInstanced const *pCmd)
1734{
1735ASMBreakpoint();
1736 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1737 if (pSvgaR3State->pFuncsDX)
1738 {
1739 RT_NOREF(pCmd);
1740 pSvgaR3State->pFuncsDX->pfnDXDrawInstanced(pThisCC->svga.p3dState);
1741 }
1742}
1743
1744
1745/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
1746static void vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexedInstanced const *pCmd)
1747{
1748ASMBreakpoint();
1749 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1750 if (pSvgaR3State->pFuncsDX)
1751 {
1752 RT_NOREF(pCmd);
1753 pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstanced(pThisCC->svga.p3dState);
1754 }
1755}
1756
1757
1758/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
1759static void vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, SVGA3dCmdDXDrawAuto const *pCmd)
1760{
1761ASMBreakpoint();
1762 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1763 if (pSvgaR3State->pFuncsDX)
1764 {
1765 RT_NOREF(pCmd);
1766 pSvgaR3State->pFuncsDX->pfnDXDrawAuto(pThisCC->svga.p3dState);
1767 }
1768}
1769
1770
1771/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
1772static void vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, SVGA3dCmdDXSetInputLayout const *pCmd)
1773{
1774ASMBreakpoint();
1775 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1776 if (pSvgaR3State->pFuncsDX)
1777 {
1778 RT_NOREF(pCmd);
1779 pSvgaR3State->pFuncsDX->pfnDXSetInputLayout(pThisCC->svga.p3dState);
1780 }
1781}
1782
1783
1784/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
1785static void vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, SVGA3dCmdDXSetVertexBuffers const *pCmd)
1786{
1787ASMBreakpoint();
1788 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1789 if (pSvgaR3State->pFuncsDX)
1790 {
1791 RT_NOREF(pCmd);
1792 pSvgaR3State->pFuncsDX->pfnDXSetVertexBuffers(pThisCC->svga.p3dState);
1793 }
1794}
1795
1796
1797/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
1798static void vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXSetIndexBuffer const *pCmd)
1799{
1800ASMBreakpoint();
1801 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1802 if (pSvgaR3State->pFuncsDX)
1803 {
1804 RT_NOREF(pCmd);
1805 pSvgaR3State->pFuncsDX->pfnDXSetIndexBuffer(pThisCC->svga.p3dState);
1806 }
1807}
1808
1809
1810/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
1811static void vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, SVGA3dCmdDXSetTopology const *pCmd)
1812{
1813ASMBreakpoint();
1814 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1815 if (pSvgaR3State->pFuncsDX)
1816 {
1817 RT_NOREF(pCmd);
1818 pSvgaR3State->pFuncsDX->pfnDXSetTopology(pThisCC->svga.p3dState);
1819 }
1820}
1821
1822
1823/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
1824static void vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, SVGA3dCmdDXSetRenderTargets const *pCmd)
1825{
1826ASMBreakpoint();
1827 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1828 if (pSvgaR3State->pFuncsDX)
1829 {
1830 RT_NOREF(pCmd);
1831 pSvgaR3State->pFuncsDX->pfnDXSetRenderTargets(pThisCC->svga.p3dState);
1832 }
1833}
1834
1835
1836/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
1837static void vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXSetBlendState const *pCmd)
1838{
1839ASMBreakpoint();
1840 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1841 if (pSvgaR3State->pFuncsDX)
1842 {
1843 RT_NOREF(pCmd);
1844 pSvgaR3State->pFuncsDX->pfnDXSetBlendState(pThisCC->svga.p3dState);
1845 }
1846}
1847
1848
1849/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
1850static void vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXSetDepthStencilState const *pCmd)
1851{
1852ASMBreakpoint();
1853 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1854 if (pSvgaR3State->pFuncsDX)
1855 {
1856 RT_NOREF(pCmd);
1857 pSvgaR3State->pFuncsDX->pfnDXSetDepthStencilState(pThisCC->svga.p3dState);
1858 }
1859}
1860
1861
1862/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
1863static void vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXSetRasterizerState const *pCmd)
1864{
1865ASMBreakpoint();
1866 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1867 if (pSvgaR3State->pFuncsDX)
1868 {
1869 RT_NOREF(pCmd);
1870 pSvgaR3State->pFuncsDX->pfnDXSetRasterizerState(pThisCC->svga.p3dState);
1871 }
1872}
1873
1874
1875/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
1876static void vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, SVGA3dCmdDXDefineQuery const *pCmd)
1877{
1878ASMBreakpoint();
1879 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1880 if (pSvgaR3State->pFuncsDX)
1881 {
1882 RT_NOREF(pCmd);
1883 pSvgaR3State->pFuncsDX->pfnDXDefineQuery(pThisCC->svga.p3dState);
1884 }
1885}
1886
1887
1888/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
1889static void vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyQuery const *pCmd)
1890{
1891ASMBreakpoint();
1892 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1893 if (pSvgaR3State->pFuncsDX)
1894 {
1895 RT_NOREF(pCmd);
1896 pSvgaR3State->pFuncsDX->pfnDXDestroyQuery(pThisCC->svga.p3dState);
1897 }
1898}
1899
1900
1901/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
1902static void vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBindQuery const *pCmd)
1903{
1904ASMBreakpoint();
1905 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1906 if (pSvgaR3State->pFuncsDX)
1907 {
1908 RT_NOREF(pCmd);
1909 pSvgaR3State->pFuncsDX->pfnDXBindQuery(pThisCC->svga.p3dState);
1910 }
1911}
1912
1913
1914/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
1915static void vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetQueryOffset const *pCmd)
1916{
1917ASMBreakpoint();
1918 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1919 if (pSvgaR3State->pFuncsDX)
1920 {
1921 RT_NOREF(pCmd);
1922 pSvgaR3State->pFuncsDX->pfnDXSetQueryOffset(pThisCC->svga.p3dState);
1923 }
1924}
1925
1926
1927/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
1928static void vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBeginQuery const *pCmd)
1929{
1930ASMBreakpoint();
1931 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1932 if (pSvgaR3State->pFuncsDX)
1933 {
1934 RT_NOREF(pCmd);
1935 pSvgaR3State->pFuncsDX->pfnDXBeginQuery(pThisCC->svga.p3dState);
1936 }
1937}
1938
1939
1940/* SVGA_3D_CMD_DX_END_QUERY 1170 */
1941static void vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, SVGA3dCmdDXEndQuery const *pCmd)
1942{
1943ASMBreakpoint();
1944 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1945 if (pSvgaR3State->pFuncsDX)
1946 {
1947 RT_NOREF(pCmd);
1948 pSvgaR3State->pFuncsDX->pfnDXEndQuery(pThisCC->svga.p3dState);
1949 }
1950}
1951
1952
1953/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
1954static void vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackQuery const *pCmd)
1955{
1956ASMBreakpoint();
1957 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1958 if (pSvgaR3State->pFuncsDX)
1959 {
1960 RT_NOREF(pCmd);
1961 pSvgaR3State->pFuncsDX->pfnDXReadbackQuery(pThisCC->svga.p3dState);
1962 }
1963}
1964
1965
1966/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
1967static void vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, SVGA3dCmdDXSetPredication const *pCmd)
1968{
1969ASMBreakpoint();
1970 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1971 if (pSvgaR3State->pFuncsDX)
1972 {
1973 RT_NOREF(pCmd);
1974 pSvgaR3State->pFuncsDX->pfnDXSetPredication(pThisCC->svga.p3dState);
1975 }
1976}
1977
1978
1979/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
1980static void vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, SVGA3dCmdDXSetSOTargets const *pCmd)
1981{
1982ASMBreakpoint();
1983 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1984 if (pSvgaR3State->pFuncsDX)
1985 {
1986 RT_NOREF(pCmd);
1987 pSvgaR3State->pFuncsDX->pfnDXSetSOTargets(pThisCC->svga.p3dState);
1988 }
1989}
1990
1991
1992/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
1993static void vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, SVGA3dCmdDXSetViewports const *pCmd)
1994{
1995ASMBreakpoint();
1996 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1997 if (pSvgaR3State->pFuncsDX)
1998 {
1999 RT_NOREF(pCmd);
2000 pSvgaR3State->pFuncsDX->pfnDXSetViewports(pThisCC->svga.p3dState);
2001 }
2002}
2003
2004
2005/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2006static void vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, SVGA3dCmdDXSetScissorRects const *pCmd)
2007{
2008ASMBreakpoint();
2009 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2010 if (pSvgaR3State->pFuncsDX)
2011 {
2012 RT_NOREF(pCmd);
2013 pSvgaR3State->pFuncsDX->pfnDXSetScissorRects(pThisCC->svga.p3dState);
2014 }
2015}
2016
2017
2018/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2019static void vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXClearRenderTargetView const *pCmd)
2020{
2021ASMBreakpoint();
2022 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2023 if (pSvgaR3State->pFuncsDX)
2024 {
2025 RT_NOREF(pCmd);
2026 pSvgaR3State->pFuncsDX->pfnDXClearRenderTargetView(pThisCC->svga.p3dState);
2027 }
2028}
2029
2030
2031/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2032static void vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXClearDepthStencilView const *pCmd)
2033{
2034ASMBreakpoint();
2035 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2036 if (pSvgaR3State->pFuncsDX)
2037 {
2038 RT_NOREF(pCmd);
2039 pSvgaR3State->pFuncsDX->pfnDXClearDepthStencilView(pThisCC->svga.p3dState);
2040 }
2041}
2042
2043
2044/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2045static void vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, SVGA3dCmdDXPredCopyRegion const *pCmd)
2046{
2047ASMBreakpoint();
2048 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2049 if (pSvgaR3State->pFuncsDX)
2050 {
2051 RT_NOREF(pCmd);
2052 pSvgaR3State->pFuncsDX->pfnDXPredCopyRegion(pThisCC->svga.p3dState);
2053 }
2054}
2055
2056
2057/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2058static void vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, SVGA3dCmdDXPredCopy const *pCmd)
2059{
2060ASMBreakpoint();
2061 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2062 if (pSvgaR3State->pFuncsDX)
2063 {
2064 RT_NOREF(pCmd);
2065 pSvgaR3State->pFuncsDX->pfnDXPredCopy(pThisCC->svga.p3dState);
2066 }
2067}
2068
2069
2070/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2071static void vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, SVGA3dCmdDXPresentBlt const *pCmd)
2072{
2073ASMBreakpoint();
2074 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2075 if (pSvgaR3State->pFuncsDX)
2076 {
2077 RT_NOREF(pCmd);
2078 pSvgaR3State->pFuncsDX->pfnDXPresentBlt(pThisCC->svga.p3dState);
2079 }
2080}
2081
2082
2083/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2084static void vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, SVGA3dCmdDXGenMips const *pCmd)
2085{
2086ASMBreakpoint();
2087 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2088 if (pSvgaR3State->pFuncsDX)
2089 {
2090 RT_NOREF(pCmd);
2091 pSvgaR3State->pFuncsDX->pfnDXGenMips(pThisCC->svga.p3dState);
2092 }
2093}
2094
2095
2096/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2097static void vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd)
2098{
2099ASMBreakpoint();
2100 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2101 if (pSvgaR3State->pFuncsDX)
2102 {
2103 RT_NOREF(pCmd);
2104 pSvgaR3State->pFuncsDX->pfnDXUpdateSubResource(pThisCC->svga.p3dState);
2105 }
2106}
2107
2108
2109/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2110static void vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd)
2111{
2112ASMBreakpoint();
2113 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2114 if (pSvgaR3State->pFuncsDX)
2115 {
2116 RT_NOREF(pCmd);
2117 pSvgaR3State->pFuncsDX->pfnDXReadbackSubResource(pThisCC->svga.p3dState);
2118 }
2119}
2120
2121
2122/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2123static void vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd)
2124{
2125ASMBreakpoint();
2126 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2127 if (pSvgaR3State->pFuncsDX)
2128 {
2129 RT_NOREF(pCmd);
2130 pSvgaR3State->pFuncsDX->pfnDXInvalidateSubResource(pThisCC->svga.p3dState);
2131 }
2132}
2133
2134
2135/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2136static void vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineShaderResourceView const *pCmd)
2137{
2138ASMBreakpoint();
2139 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2140 if (pSvgaR3State->pFuncsDX)
2141 {
2142 RT_NOREF(pCmd);
2143 pSvgaR3State->pFuncsDX->pfnDXDefineShaderResourceView(pThisCC->svga.p3dState);
2144 }
2145}
2146
2147
2148/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2149static void vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyShaderResourceView const *pCmd)
2150{
2151ASMBreakpoint();
2152 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2153 if (pSvgaR3State->pFuncsDX)
2154 {
2155 RT_NOREF(pCmd);
2156 pSvgaR3State->pFuncsDX->pfnDXDestroyShaderResourceView(pThisCC->svga.p3dState);
2157 }
2158}
2159
2160
2161/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2162static void vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineRenderTargetView const *pCmd)
2163{
2164ASMBreakpoint();
2165 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2166 if (pSvgaR3State->pFuncsDX)
2167 {
2168 RT_NOREF(pCmd);
2169 pSvgaR3State->pFuncsDX->pfnDXDefineRenderTargetView(pThisCC->svga.p3dState);
2170 }
2171}
2172
2173
2174/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2175static void vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyRenderTargetView const *pCmd)
2176{
2177ASMBreakpoint();
2178 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2179 if (pSvgaR3State->pFuncsDX)
2180 {
2181 RT_NOREF(pCmd);
2182 pSvgaR3State->pFuncsDX->pfnDXDestroyRenderTargetView(pThisCC->svga.p3dState);
2183 }
2184}
2185
2186
2187/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2188static void vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilView const *pCmd)
2189{
2190ASMBreakpoint();
2191 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2192 if (pSvgaR3State->pFuncsDX)
2193 {
2194 RT_NOREF(pCmd);
2195 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView(pThisCC->svga.p3dState);
2196 }
2197}
2198
2199
2200/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2201static void vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyDepthStencilView const *pCmd)
2202{
2203ASMBreakpoint();
2204 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2205 if (pSvgaR3State->pFuncsDX)
2206 {
2207 RT_NOREF(pCmd);
2208 pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilView(pThisCC->svga.p3dState);
2209 }
2210}
2211
2212
2213/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2214static void vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, SVGA3dCmdDXDefineElementLayout const *pCmd)
2215{
2216ASMBreakpoint();
2217 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2218 if (pSvgaR3State->pFuncsDX)
2219 {
2220 RT_NOREF(pCmd);
2221 pSvgaR3State->pFuncsDX->pfnDXDefineElementLayout(pThisCC->svga.p3dState);
2222 }
2223}
2224
2225
2226/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2227static void vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyElementLayout const *pCmd)
2228{
2229ASMBreakpoint();
2230 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2231 if (pSvgaR3State->pFuncsDX)
2232 {
2233 RT_NOREF(pCmd);
2234 pSvgaR3State->pFuncsDX->pfnDXDestroyElementLayout(pThisCC->svga.p3dState);
2235 }
2236}
2237
2238
2239/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2240static void vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineBlendState const *pCmd)
2241{
2242ASMBreakpoint();
2243 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2244 if (pSvgaR3State->pFuncsDX)
2245 {
2246 RT_NOREF(pCmd);
2247 pSvgaR3State->pFuncsDX->pfnDXDefineBlendState(pThisCC->svga.p3dState);
2248 }
2249}
2250
2251
2252/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2253static void vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyBlendState const *pCmd)
2254{
2255ASMBreakpoint();
2256 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2257 if (pSvgaR3State->pFuncsDX)
2258 {
2259 RT_NOREF(pCmd);
2260 pSvgaR3State->pFuncsDX->pfnDXDestroyBlendState(pThisCC->svga.p3dState);
2261 }
2262}
2263
2264
2265/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2266static void vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilState const *pCmd)
2267{
2268ASMBreakpoint();
2269 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2270 if (pSvgaR3State->pFuncsDX)
2271 {
2272 RT_NOREF(pCmd);
2273 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilState(pThisCC->svga.p3dState);
2274 }
2275}
2276
2277
2278/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2279static void vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyDepthStencilState const *pCmd)
2280{
2281ASMBreakpoint();
2282 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2283 if (pSvgaR3State->pFuncsDX)
2284 {
2285 RT_NOREF(pCmd);
2286 pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilState(pThisCC->svga.p3dState);
2287 }
2288}
2289
2290
2291/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2292static void vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineRasterizerState const *pCmd)
2293{
2294ASMBreakpoint();
2295 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2296 if (pSvgaR3State->pFuncsDX)
2297 {
2298 RT_NOREF(pCmd);
2299 pSvgaR3State->pFuncsDX->pfnDXDefineRasterizerState(pThisCC->svga.p3dState);
2300 }
2301}
2302
2303
2304/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2305static void vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyRasterizerState const *pCmd)
2306{
2307ASMBreakpoint();
2308 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2309 if (pSvgaR3State->pFuncsDX)
2310 {
2311 RT_NOREF(pCmd);
2312 pSvgaR3State->pFuncsDX->pfnDXDestroyRasterizerState(pThisCC->svga.p3dState);
2313 }
2314}
2315
2316
2317/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2318static void vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, SVGA3dCmdDXDefineSamplerState const *pCmd)
2319{
2320ASMBreakpoint();
2321 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2322 if (pSvgaR3State->pFuncsDX)
2323 {
2324 RT_NOREF(pCmd);
2325 pSvgaR3State->pFuncsDX->pfnDXDefineSamplerState(pThisCC->svga.p3dState);
2326 }
2327}
2328
2329
2330/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2331static void vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, SVGA3dCmdDXDestroySamplerState const *pCmd)
2332{
2333ASMBreakpoint();
2334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2335 if (pSvgaR3State->pFuncsDX)
2336 {
2337 RT_NOREF(pCmd);
2338 pSvgaR3State->pFuncsDX->pfnDXDestroySamplerState(pThisCC->svga.p3dState);
2339 }
2340}
2341
2342
2343/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2344static void vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, SVGA3dCmdDXDefineShader const *pCmd)
2345{
2346ASMBreakpoint();
2347 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2348 if (pSvgaR3State->pFuncsDX)
2349 {
2350 RT_NOREF(pCmd);
2351 pSvgaR3State->pFuncsDX->pfnDXDefineShader(pThisCC->svga.p3dState);
2352 }
2353}
2354
2355
2356/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2357static void vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyShader const *pCmd)
2358{
2359ASMBreakpoint();
2360 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2361 if (pSvgaR3State->pFuncsDX)
2362 {
2363 RT_NOREF(pCmd);
2364 pSvgaR3State->pFuncsDX->pfnDXDestroyShader(pThisCC->svga.p3dState);
2365 }
2366}
2367
2368
2369/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2370static void vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, SVGA3dCmdDXBindShader const *pCmd)
2371{
2372ASMBreakpoint();
2373 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2374 if (pSvgaR3State->pFuncsDX)
2375 {
2376 RT_NOREF(pCmd);
2377 pSvgaR3State->pFuncsDX->pfnDXBindShader(pThisCC->svga.p3dState);
2378 }
2379}
2380
2381
2382/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2383static void vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXDefineStreamOutput const *pCmd)
2384{
2385ASMBreakpoint();
2386 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2387 if (pSvgaR3State->pFuncsDX)
2388 {
2389 RT_NOREF(pCmd);
2390 pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutput(pThisCC->svga.p3dState);
2391 }
2392}
2393
2394
2395/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2396static void vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyStreamOutput const *pCmd)
2397{
2398ASMBreakpoint();
2399 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2400 if (pSvgaR3State->pFuncsDX)
2401 {
2402 RT_NOREF(pCmd);
2403 pSvgaR3State->pFuncsDX->pfnDXDestroyStreamOutput(pThisCC->svga.p3dState);
2404 }
2405}
2406
2407
2408/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2409static void vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXSetStreamOutput const *pCmd)
2410{
2411ASMBreakpoint();
2412 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2413 if (pSvgaR3State->pFuncsDX)
2414 {
2415 RT_NOREF(pCmd);
2416 pSvgaR3State->pFuncsDX->pfnDXSetStreamOutput(pThisCC->svga.p3dState);
2417 }
2418}
2419
2420
2421/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2422static void vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd)
2423{
2424ASMBreakpoint();
2425 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2426 if (pSvgaR3State->pFuncsDX)
2427 {
2428 RT_NOREF(pCmd);
2429 pSvgaR3State->pFuncsDX->pfnDXSetCOTable(pThisCC->svga.p3dState);
2430 }
2431}
2432
2433
2434/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2435static void vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackCOTable const *pCmd)
2436{
2437ASMBreakpoint();
2438 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2439 if (pSvgaR3State->pFuncsDX)
2440 {
2441 RT_NOREF(pCmd);
2442 pSvgaR3State->pFuncsDX->pfnDXReadbackCOTable(pThisCC->svga.p3dState);
2443 }
2444}
2445
2446
2447/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2448static void vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, SVGA3dCmdDXBufferCopy const *pCmd)
2449{
2450ASMBreakpoint();
2451 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2452 if (pSvgaR3State->pFuncsDX)
2453 {
2454 RT_NOREF(pCmd);
2455 pSvgaR3State->pFuncsDX->pfnDXBufferCopy(pThisCC->svga.p3dState);
2456 }
2457}
2458
2459
2460/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2461static void vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd)
2462{
2463ASMBreakpoint();
2464 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2465 if (pSvgaR3State->pFuncsDX)
2466 {
2467 RT_NOREF(pCmd);
2468 pSvgaR3State->pFuncsDX->pfnDXTransferFromBuffer(pThisCC->svga.p3dState);
2469 }
2470}
2471
2472
2473/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2474static void vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd)
2475{
2476ASMBreakpoint();
2477 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2478 if (pSvgaR3State->pFuncsDX)
2479 {
2480 RT_NOREF(pCmd);
2481 pSvgaR3State->pFuncsDX->pfnDXSurfaceCopyAndReadback(pThisCC->svga.p3dState);
2482 }
2483}
2484
2485
2486/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2487static void vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, SVGA3dCmdDXMoveQuery const *pCmd)
2488{
2489ASMBreakpoint();
2490 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2491 if (pSvgaR3State->pFuncsDX)
2492 {
2493 RT_NOREF(pCmd);
2494 pSvgaR3State->pFuncsDX->pfnDXMoveQuery(pThisCC->svga.p3dState);
2495 }
2496}
2497
2498
2499/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2500static void vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, SVGA3dCmdDXBindAllQuery const *pCmd)
2501{
2502ASMBreakpoint();
2503 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2504 if (pSvgaR3State->pFuncsDX)
2505 {
2506 RT_NOREF(pCmd);
2507 pSvgaR3State->pFuncsDX->pfnDXBindAllQuery(pThisCC->svga.p3dState);
2508 }
2509}
2510
2511
2512/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2513static void vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackAllQuery const *pCmd)
2514{
2515ASMBreakpoint();
2516 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2517 if (pSvgaR3State->pFuncsDX)
2518 {
2519 RT_NOREF(pCmd);
2520 pSvgaR3State->pFuncsDX->pfnDXReadbackAllQuery(pThisCC->svga.p3dState);
2521 }
2522}
2523
2524
2525/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2526static void vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXPredTransferFromBuffer const *pCmd)
2527{
2528ASMBreakpoint();
2529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2530 if (pSvgaR3State->pFuncsDX)
2531 {
2532 RT_NOREF(pCmd);
2533 pSvgaR3State->pFuncsDX->pfnDXPredTransferFromBuffer(pThisCC->svga.p3dState);
2534 }
2535}
2536
2537
2538/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
2539static void vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd)
2540{
2541ASMBreakpoint();
2542 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2543 if (pSvgaR3State->pFuncsDX)
2544 {
2545 RT_NOREF(pCmd);
2546 pSvgaR3State->pFuncsDX->pfnDXMobFence64(pThisCC->svga.p3dState);
2547 }
2548}
2549
2550
2551/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
2552static void vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, SVGA3dCmdDXBindAllShader const *pCmd)
2553{
2554ASMBreakpoint();
2555 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2556 if (pSvgaR3State->pFuncsDX)
2557 {
2558 RT_NOREF(pCmd);
2559 pSvgaR3State->pFuncsDX->pfnDXBindAllShader(pThisCC->svga.p3dState);
2560 }
2561}
2562
2563
2564/* SVGA_3D_CMD_DX_HINT 1218 */
2565static void vmsvga3dCmdDXHint(PVGASTATECC pThisCC, SVGA3dCmdDXHint const *pCmd)
2566{
2567ASMBreakpoint();
2568 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2569 if (pSvgaR3State->pFuncsDX)
2570 {
2571 RT_NOREF(pCmd);
2572 pSvgaR3State->pFuncsDX->pfnDXHint(pThisCC->svga.p3dState);
2573 }
2574}
2575
2576
2577/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
2578static void vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, SVGA3dCmdDXBufferUpdate const *pCmd)
2579{
2580ASMBreakpoint();
2581 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2582 if (pSvgaR3State->pFuncsDX)
2583 {
2584 RT_NOREF(pCmd);
2585 pSvgaR3State->pFuncsDX->pfnDXBufferUpdate(pThisCC->svga.p3dState);
2586 }
2587}
2588
2589
2590/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
2591static void vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd)
2592{
2593ASMBreakpoint();
2594 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2595 if (pSvgaR3State->pFuncsDX)
2596 {
2597 RT_NOREF(pCmd);
2598 pSvgaR3State->pFuncsDX->pfnDXSetVSConstantBufferOffset(pThisCC->svga.p3dState);
2599 }
2600}
2601
2602
2603/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
2604static void vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd)
2605{
2606ASMBreakpoint();
2607 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2608 if (pSvgaR3State->pFuncsDX)
2609 {
2610 RT_NOREF(pCmd);
2611 pSvgaR3State->pFuncsDX->pfnDXSetPSConstantBufferOffset(pThisCC->svga.p3dState);
2612 }
2613}
2614
2615
2616/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
2617static void vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd)
2618{
2619ASMBreakpoint();
2620 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2621 if (pSvgaR3State->pFuncsDX)
2622 {
2623 RT_NOREF(pCmd);
2624 pSvgaR3State->pFuncsDX->pfnDXSetGSConstantBufferOffset(pThisCC->svga.p3dState);
2625 }
2626}
2627
2628
2629/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
2630static void vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd)
2631{
2632ASMBreakpoint();
2633 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2634 if (pSvgaR3State->pFuncsDX)
2635 {
2636 RT_NOREF(pCmd);
2637 pSvgaR3State->pFuncsDX->pfnDXSetHSConstantBufferOffset(pThisCC->svga.p3dState);
2638 }
2639}
2640
2641
2642/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
2643static void vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd)
2644{
2645ASMBreakpoint();
2646 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2647 if (pSvgaR3State->pFuncsDX)
2648 {
2649 RT_NOREF(pCmd);
2650 pSvgaR3State->pFuncsDX->pfnDXSetDSConstantBufferOffset(pThisCC->svga.p3dState);
2651 }
2652}
2653
2654
2655/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
2656static void vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd)
2657{
2658ASMBreakpoint();
2659 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2660 if (pSvgaR3State->pFuncsDX)
2661 {
2662 RT_NOREF(pCmd);
2663 pSvgaR3State->pFuncsDX->pfnDXSetCSConstantBufferOffset(pThisCC->svga.p3dState);
2664 }
2665}
2666
2667
2668/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
2669static void vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, SVGA3dCmdDXCondBindAllShader const *pCmd)
2670{
2671ASMBreakpoint();
2672 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2673 if (pSvgaR3State->pFuncsDX)
2674 {
2675 RT_NOREF(pCmd);
2676 pSvgaR3State->pFuncsDX->pfnDXCondBindAllShader(pThisCC->svga.p3dState);
2677 }
2678}
2679
2680
2681/* SVGA_3D_CMD_SCREEN_COPY 1227 */
2682static void vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, SVGA3dCmdScreenCopy const *pCmd)
2683{
2684ASMBreakpoint();
2685 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2686 if (pSvgaR3State->pFuncsDX)
2687 {
2688 RT_NOREF(pCmd);
2689 pSvgaR3State->pFuncsDX->pfnScreenCopy(pThisCC->svga.p3dState);
2690 }
2691}
2692
2693
2694/* SVGA_3D_CMD_GROW_OTABLE 1236 */
2695static void vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd)
2696{
2697ASMBreakpoint();
2698 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2699 if (pSvgaR3State->pFuncsDX)
2700 {
2701 RT_NOREF(pCmd);
2702 pSvgaR3State->pFuncsDX->pfnGrowOTable(pThisCC->svga.p3dState);
2703 }
2704}
2705
2706
2707/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
2708static void vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd)
2709{
2710ASMBreakpoint();
2711 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2712 if (pSvgaR3State->pFuncsDX)
2713 {
2714 RT_NOREF(pCmd);
2715 pSvgaR3State->pFuncsDX->pfnDXGrowCOTable(pThisCC->svga.p3dState);
2716 }
2717}
2718
2719
2720/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
2721static void vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdIntraSurfaceCopy const *pCmd)
2722{
2723ASMBreakpoint();
2724 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2725 if (pSvgaR3State->pFuncsDX)
2726 {
2727 RT_NOREF(pCmd);
2728 pSvgaR3State->pFuncsDX->pfnIntraSurfaceCopy(pThisCC->svga.p3dState);
2729 }
2730}
2731
2732
2733/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
2734static void vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
2735{
2736ASMBreakpoint();
2737 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2738 if (pSvgaR3State->pFuncsDX)
2739 {
2740 RT_NOREF(pCmd);
2741 pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v3(pThisCC->svga.p3dState);
2742 }
2743}
2744
2745
2746/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
2747static void vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXResolveCopy const *pCmd)
2748{
2749ASMBreakpoint();
2750 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2751 if (pSvgaR3State->pFuncsDX)
2752 {
2753 RT_NOREF(pCmd);
2754 pSvgaR3State->pFuncsDX->pfnDXResolveCopy(pThisCC->svga.p3dState);
2755 }
2756}
2757
2758
2759/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
2760static void vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXPredResolveCopy const *pCmd)
2761{
2762ASMBreakpoint();
2763 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2764 if (pSvgaR3State->pFuncsDX)
2765 {
2766 RT_NOREF(pCmd);
2767 pSvgaR3State->pFuncsDX->pfnDXPredResolveCopy(pThisCC->svga.p3dState);
2768 }
2769}
2770
2771
2772/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
2773static void vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvertRegion const *pCmd)
2774{
2775ASMBreakpoint();
2776 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2777 if (pSvgaR3State->pFuncsDX)
2778 {
2779 RT_NOREF(pCmd);
2780 pSvgaR3State->pFuncsDX->pfnDXPredConvertRegion(pThisCC->svga.p3dState);
2781 }
2782}
2783
2784
2785/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
2786static void vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvert const *pCmd)
2787{
2788ASMBreakpoint();
2789 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2790 if (pSvgaR3State->pFuncsDX)
2791 {
2792 RT_NOREF(pCmd);
2793 pSvgaR3State->pFuncsDX->pfnDXPredConvert(pThisCC->svga.p3dState);
2794 }
2795}
2796
2797
2798/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
2799static void vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdWholeSurfaceCopy const *pCmd)
2800{
2801ASMBreakpoint();
2802 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2803 if (pSvgaR3State->pFuncsDX)
2804 {
2805 RT_NOREF(pCmd);
2806 pSvgaR3State->pFuncsDX->pfnWholeSurfaceCopy(pThisCC->svga.p3dState);
2807 }
2808}
2809
2810
2811/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
2812static void vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineUAView const *pCmd)
2813{
2814ASMBreakpoint();
2815 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2816 if (pSvgaR3State->pFuncsDX)
2817 {
2818 RT_NOREF(pCmd);
2819 pSvgaR3State->pFuncsDX->pfnDXDefineUAView(pThisCC->svga.p3dState);
2820 }
2821}
2822
2823
2824/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
2825static void vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyUAView const *pCmd)
2826{
2827ASMBreakpoint();
2828 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2829 if (pSvgaR3State->pFuncsDX)
2830 {
2831 RT_NOREF(pCmd);
2832 pSvgaR3State->pFuncsDX->pfnDXDestroyUAView(pThisCC->svga.p3dState);
2833 }
2834}
2835
2836
2837/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
2838static void vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewUint const *pCmd)
2839{
2840ASMBreakpoint();
2841 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2842 if (pSvgaR3State->pFuncsDX)
2843 {
2844 RT_NOREF(pCmd);
2845 pSvgaR3State->pFuncsDX->pfnDXClearUAViewUint(pThisCC->svga.p3dState);
2846 }
2847}
2848
2849
2850/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
2851static void vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewFloat const *pCmd)
2852{
2853ASMBreakpoint();
2854 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2855 if (pSvgaR3State->pFuncsDX)
2856 {
2857 RT_NOREF(pCmd);
2858 pSvgaR3State->pFuncsDX->pfnDXClearUAViewFloat(pThisCC->svga.p3dState);
2859 }
2860}
2861
2862
2863/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
2864static void vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXCopyStructureCount const *pCmd)
2865{
2866ASMBreakpoint();
2867 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2868 if (pSvgaR3State->pFuncsDX)
2869 {
2870 RT_NOREF(pCmd);
2871 pSvgaR3State->pFuncsDX->pfnDXCopyStructureCount(pThisCC->svga.p3dState);
2872 }
2873}
2874
2875
2876/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
2877static void vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetUAViews const *pCmd)
2878{
2879ASMBreakpoint();
2880 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2881 if (pSvgaR3State->pFuncsDX)
2882 {
2883 RT_NOREF(pCmd);
2884 pSvgaR3State->pFuncsDX->pfnDXSetUAViews(pThisCC->svga.p3dState);
2885 }
2886}
2887
2888
2889/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
2890static void vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd)
2891{
2892ASMBreakpoint();
2893 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2894 if (pSvgaR3State->pFuncsDX)
2895 {
2896 RT_NOREF(pCmd);
2897 pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstancedIndirect(pThisCC->svga.p3dState);
2898 }
2899}
2900
2901
2902/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
2903static void vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawInstancedIndirect const *pCmd)
2904{
2905ASMBreakpoint();
2906 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2907 if (pSvgaR3State->pFuncsDX)
2908 {
2909 RT_NOREF(pCmd);
2910 pSvgaR3State->pFuncsDX->pfnDXDrawInstancedIndirect(pThisCC->svga.p3dState);
2911 }
2912}
2913
2914
2915/* SVGA_3D_CMD_DX_DISPATCH 1253 */
2916static void vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, SVGA3dCmdDXDispatch const *pCmd)
2917{
2918ASMBreakpoint();
2919 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2920 if (pSvgaR3State->pFuncsDX)
2921 {
2922 RT_NOREF(pCmd);
2923 pSvgaR3State->pFuncsDX->pfnDXDispatch(pThisCC->svga.p3dState);
2924 }
2925}
2926
2927
2928/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
2929static void vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDispatchIndirect const *pCmd)
2930{
2931ASMBreakpoint();
2932 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2933 if (pSvgaR3State->pFuncsDX)
2934 {
2935 RT_NOREF(pCmd);
2936 pSvgaR3State->pFuncsDX->pfnDXDispatchIndirect(pThisCC->svga.p3dState);
2937 }
2938}
2939
2940
2941/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
2942static void vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdWriteZeroSurface const *pCmd)
2943{
2944ASMBreakpoint();
2945 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2946 if (pSvgaR3State->pFuncsDX)
2947 {
2948 RT_NOREF(pCmd);
2949 pSvgaR3State->pFuncsDX->pfnWriteZeroSurface(pThisCC->svga.p3dState);
2950 }
2951}
2952
2953
2954/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
2955static void vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdHintZeroSurface const *pCmd)
2956{
2957ASMBreakpoint();
2958 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2959 if (pSvgaR3State->pFuncsDX)
2960 {
2961 RT_NOREF(pCmd);
2962 pSvgaR3State->pFuncsDX->pfnHintZeroSurface(pThisCC->svga.p3dState);
2963 }
2964}
2965
2966
2967/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
2968static void vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferToBuffer const *pCmd)
2969{
2970ASMBreakpoint();
2971 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2972 if (pSvgaR3State->pFuncsDX)
2973 {
2974 RT_NOREF(pCmd);
2975 pSvgaR3State->pFuncsDX->pfnDXTransferToBuffer(pThisCC->svga.p3dState);
2976 }
2977}
2978
2979
2980/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
2981static void vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXSetStructureCount const *pCmd)
2982{
2983ASMBreakpoint();
2984 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2985 if (pSvgaR3State->pFuncsDX)
2986 {
2987 RT_NOREF(pCmd);
2988 pSvgaR3State->pFuncsDX->pfnDXSetStructureCount(pThisCC->svga.p3dState);
2989 }
2990}
2991
2992
2993/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
2994static void vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsBitBlt const *pCmd)
2995{
2996ASMBreakpoint();
2997 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2998 if (pSvgaR3State->pFuncsDX)
2999 {
3000 RT_NOREF(pCmd);
3001 pSvgaR3State->pFuncsDX->pfnLogicOpsBitBlt(pThisCC->svga.p3dState);
3002 }
3003}
3004
3005
3006/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3007static void vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsTransBlt const *pCmd)
3008{
3009ASMBreakpoint();
3010 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3011 if (pSvgaR3State->pFuncsDX)
3012 {
3013 RT_NOREF(pCmd);
3014 pSvgaR3State->pFuncsDX->pfnLogicOpsTransBlt(pThisCC->svga.p3dState);
3015 }
3016}
3017
3018
3019/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3020static void vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsStretchBlt const *pCmd)
3021{
3022ASMBreakpoint();
3023 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3024 if (pSvgaR3State->pFuncsDX)
3025 {
3026 RT_NOREF(pCmd);
3027 pSvgaR3State->pFuncsDX->pfnLogicOpsStretchBlt(pThisCC->svga.p3dState);
3028 }
3029}
3030
3031
3032/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3033static void vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsColorFill const *pCmd)
3034{
3035ASMBreakpoint();
3036 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3037 if (pSvgaR3State->pFuncsDX)
3038 {
3039 RT_NOREF(pCmd);
3040 pSvgaR3State->pFuncsDX->pfnLogicOpsColorFill(pThisCC->svga.p3dState);
3041 }
3042}
3043
3044
3045/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3046static void vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsAlphaBlend const *pCmd)
3047{
3048ASMBreakpoint();
3049 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3050 if (pSvgaR3State->pFuncsDX)
3051 {
3052 RT_NOREF(pCmd);
3053 pSvgaR3State->pFuncsDX->pfnLogicOpsAlphaBlend(pThisCC->svga.p3dState);
3054 }
3055}
3056
3057
3058/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3059static void vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd)
3060{
3061ASMBreakpoint();
3062 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3063 if (pSvgaR3State->pFuncsDX)
3064 {
3065 RT_NOREF(pCmd);
3066 pSvgaR3State->pFuncsDX->pfnLogicOpsClearTypeBlend(pThisCC->svga.p3dState);
3067 }
3068}
3069
3070
3071/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3072static void vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
3073{
3074ASMBreakpoint();
3075 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3076 if (pSvgaR3State->pFuncsDX)
3077 {
3078 RT_NOREF(pCmd);
3079 pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v4(pThisCC->svga.p3dState);
3080 }
3081}
3082
3083
3084/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3085static void vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSUAViews const *pCmd)
3086{
3087ASMBreakpoint();
3088 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3089 if (pSvgaR3State->pFuncsDX)
3090 {
3091 RT_NOREF(pCmd);
3092 pSvgaR3State->pFuncsDX->pfnDXSetCSUAViews(pThisCC->svga.p3dState);
3093 }
3094}
3095
3096
3097/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3098static void vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, SVGA3dCmdDXSetMinLOD const *pCmd)
3099{
3100ASMBreakpoint();
3101 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3102 if (pSvgaR3State->pFuncsDX)
3103 {
3104 RT_NOREF(pCmd);
3105 pSvgaR3State->pFuncsDX->pfnDXSetMinLOD(pThisCC->svga.p3dState);
3106 }
3107}
3108
3109
3110/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3111static void vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd)
3112{
3113ASMBreakpoint();
3114 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3115 if (pSvgaR3State->pFuncsDX)
3116 {
3117 RT_NOREF(pCmd);
3118 pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView_v2(pThisCC->svga.p3dState);
3119 }
3120}
3121
3122
3123/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3124static void vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd)
3125{
3126ASMBreakpoint();
3127 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3128 if (pSvgaR3State->pFuncsDX)
3129 {
3130 RT_NOREF(pCmd);
3131 pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutputWithMob(pThisCC->svga.p3dState);
3132 }
3133}
3134
3135
3136/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3137static void vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXSetShaderIface const *pCmd)
3138{
3139ASMBreakpoint();
3140 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3141 if (pSvgaR3State->pFuncsDX)
3142 {
3143 RT_NOREF(pCmd);
3144 pSvgaR3State->pFuncsDX->pfnDXSetShaderIface(pThisCC->svga.p3dState);
3145 }
3146}
3147
3148
3149/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3150static void vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXBindStreamOutput const *pCmd)
3151{
3152ASMBreakpoint();
3153 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3154 if (pSvgaR3State->pFuncsDX)
3155 {
3156 RT_NOREF(pCmd);
3157 pSvgaR3State->pFuncsDX->pfnDXBindStreamOutput(pThisCC->svga.p3dState);
3158 }
3159}
3160
3161
3162/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3163static void vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd)
3164{
3165ASMBreakpoint();
3166 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3167 if (pSvgaR3State->pFuncsDX)
3168 {
3169 RT_NOREF(pCmd);
3170 pSvgaR3State->pFuncsDX->pfnSurfaceStretchBltNonMSToMS(pThisCC->svga.p3dState);
3171 }
3172}
3173
3174
3175/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3176static void vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXBindShaderIface const *pCmd)
3177{
3178ASMBreakpoint();
3179 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3180 if (pSvgaR3State->pFuncsDX)
3181 {
3182 RT_NOREF(pCmd);
3183 pSvgaR3State->pFuncsDX->pfnDXBindShaderIface(pThisCC->svga.p3dState);
3184 }
3185}
3186
3187
3188/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3189 * Check that the 3D command has at least a_cbMin of payload bytes after the
3190 * header. Will break out of the switch if it doesn't.
3191 */
3192# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3193 if (1) { \
3194 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3195 RT_UNTRUSTED_VALIDATED_FENCE(); \
3196 } else do {} while (0)
3197
3198# define VMSVGA_3D_CMD_NOTIMPL() \
3199 if (1) { \
3200 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3201 } else do {} while (0)
3202
3203/** SVGA_3D_CMD_* handler.
3204 * This function parses the command and calls the corresponding command handler.
3205 *
3206 * @param pThis The shared VGA/VMSVGA state.
3207 * @param pThisCC The VGA/VMSVGA state for the current context.
3208 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3209 * @param cbCmd Size of the command in bytes.
3210 * @param pvCmd Pointer to the command.
3211 * @returns VBox status code if an error was detected parsing a command.
3212 */
3213int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3214{
3215 if (enmCmdId > SVGA_3D_CMD_MAX)
3216 {
3217 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3218 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3219 }
3220
3221 int rcParse = VINF_SUCCESS;
3222 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3223
3224 switch (enmCmdId)
3225 {
3226 case SVGA_3D_CMD_SURFACE_DEFINE:
3227 {
3228 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3229 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3230 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3231
3232 SVGA3dCmdDefineSurface_v2 cmd;
3233 cmd.sid = pCmd->sid;
3234 cmd.surfaceFlags = pCmd->surfaceFlags;
3235 cmd.format = pCmd->format;
3236 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3237 cmd.multisampleCount = 0;
3238 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3239
3240 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3241 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3242# ifdef DEBUG_GMR_ACCESS
3243 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3244# endif
3245 break;
3246 }
3247
3248 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3249 {
3250 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3251 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3252 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3253
3254 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3255 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3256# ifdef DEBUG_GMR_ACCESS
3257 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3258# endif
3259 break;
3260 }
3261
3262 case SVGA_3D_CMD_SURFACE_DESTROY:
3263 {
3264 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3265 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3266 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3267
3268 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3269 break;
3270 }
3271
3272 case SVGA_3D_CMD_SURFACE_COPY:
3273 {
3274 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3275 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3276 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3277
3278 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3279 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3280 break;
3281 }
3282
3283 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3284 {
3285 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3287 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3288
3289 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3290 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3291 break;
3292 }
3293
3294 case SVGA_3D_CMD_SURFACE_DMA:
3295 {
3296 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3297 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3298 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3299
3300 uint64_t u64NanoTS = 0;
3301 if (LogRelIs3Enabled())
3302 u64NanoTS = RTTimeNanoTS();
3303 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3304 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3305 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3306 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3307 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3308 if (LogRelIs3Enabled())
3309 {
3310 if (cCopyBoxes)
3311 {
3312 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3313 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3314 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3315 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3316 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3317 }
3318 }
3319 break;
3320 }
3321
3322 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3323 {
3324 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3325 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3326 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3327
3328 static uint64_t u64FrameStartNanoTS = 0;
3329 static uint64_t u64ElapsedPerSecNano = 0;
3330 static int cFrames = 0;
3331 uint64_t u64NanoTS = 0;
3332 if (LogRelIs3Enabled())
3333 u64NanoTS = RTTimeNanoTS();
3334 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3335 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3336 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3337 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3338 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3339 if (LogRelIs3Enabled())
3340 {
3341 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3342 u64ElapsedPerSecNano += u64ElapsedNano;
3343
3344 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3345 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3346 (u64ElapsedNano) / 1000ULL, cRects,
3347 pFirstRect->left, pFirstRect->top,
3348 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3349
3350 ++cFrames;
3351 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3352 {
3353 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3354 cFrames, u64ElapsedPerSecNano / 1000ULL));
3355 u64FrameStartNanoTS = u64NanoTS;
3356 cFrames = 0;
3357 u64ElapsedPerSecNano = 0;
3358 }
3359 }
3360 break;
3361 }
3362
3363 case SVGA_3D_CMD_CONTEXT_DEFINE:
3364 {
3365 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3367 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3368
3369 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3370 break;
3371 }
3372
3373 case SVGA_3D_CMD_CONTEXT_DESTROY:
3374 {
3375 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3376 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3377 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3378
3379 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3380 break;
3381 }
3382
3383 case SVGA_3D_CMD_SETTRANSFORM:
3384 {
3385 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3387 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3388
3389 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3390 break;
3391 }
3392
3393 case SVGA_3D_CMD_SETZRANGE:
3394 {
3395 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3396 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3397 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3398
3399 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3400 break;
3401 }
3402
3403 case SVGA_3D_CMD_SETRENDERSTATE:
3404 {
3405 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3407 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3408
3409 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3410 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3411 break;
3412 }
3413
3414 case SVGA_3D_CMD_SETRENDERTARGET:
3415 {
3416 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3417 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3418 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3419
3420 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3421 break;
3422 }
3423
3424 case SVGA_3D_CMD_SETTEXTURESTATE:
3425 {
3426 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3427 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3428 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3429
3430 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3431 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3432 break;
3433 }
3434
3435 case SVGA_3D_CMD_SETMATERIAL:
3436 {
3437 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3439 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3440
3441 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3442 break;
3443 }
3444
3445 case SVGA_3D_CMD_SETLIGHTDATA:
3446 {
3447 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3448 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3449 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3450
3451 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3452 break;
3453 }
3454
3455 case SVGA_3D_CMD_SETLIGHTENABLED:
3456 {
3457 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3459 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3460
3461 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3462 break;
3463 }
3464
3465 case SVGA_3D_CMD_SETVIEWPORT:
3466 {
3467 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
3468 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3469 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
3470
3471 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
3472 break;
3473 }
3474
3475 case SVGA_3D_CMD_SETCLIPPLANE:
3476 {
3477 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
3478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3479 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
3480
3481 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
3482 break;
3483 }
3484
3485 case SVGA_3D_CMD_CLEAR:
3486 {
3487 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
3488 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3489 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
3490
3491 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3492 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3493 break;
3494 }
3495
3496 case SVGA_3D_CMD_PRESENT:
3497 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3498 {
3499 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
3500 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3501 if (enmCmdId == SVGA_3D_CMD_PRESENT)
3502 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
3503 else
3504 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
3505
3506 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3507 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3508 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3509 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
3510 break;
3511 }
3512
3513 case SVGA_3D_CMD_SHADER_DEFINE:
3514 {
3515 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
3516 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3517 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
3518
3519 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
3520 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3521 break;
3522 }
3523
3524 case SVGA_3D_CMD_SHADER_DESTROY:
3525 {
3526 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
3527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3528 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
3529
3530 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
3531 break;
3532 }
3533
3534 case SVGA_3D_CMD_SET_SHADER:
3535 {
3536 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
3537 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3538 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
3539
3540 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3541 break;
3542 }
3543
3544 case SVGA_3D_CMD_SET_SHADER_CONST:
3545 {
3546 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
3547 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3548 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
3549
3550 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3551 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3552 break;
3553 }
3554
3555 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3556 {
3557 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
3558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3559 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
3560
3561 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
3562 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
3563 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
3564 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
3565 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
3566
3567 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
3568 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
3569 RT_UNTRUSTED_VALIDATED_FENCE();
3570
3571 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3572 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
3573 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
3574
3575 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3576 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
3577 pNumRange, cVertexDivisor, pVertexDivisor);
3578 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
3579 break;
3580 }
3581
3582 case SVGA_3D_CMD_SETSCISSORRECT:
3583 {
3584 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
3585 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3586 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
3587
3588 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
3589 break;
3590 }
3591
3592 case SVGA_3D_CMD_BEGIN_QUERY:
3593 {
3594 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
3595 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3596 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
3597
3598 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
3599 break;
3600 }
3601
3602 case SVGA_3D_CMD_END_QUERY:
3603 {
3604 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
3605 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3606 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
3607
3608 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3609 break;
3610 }
3611
3612 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3613 {
3614 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
3615 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3616 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
3617
3618 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
3619 break;
3620 }
3621
3622 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3623 {
3624 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
3625 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3626 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
3627
3628 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
3629 break;
3630 }
3631
3632 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3633 /* context id + surface id? */
3634 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
3635 break;
3636
3637 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3638 /* context id + surface id? */
3639 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
3640 break;
3641
3642 /*
3643 *
3644 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
3645 *
3646 */
3647 case SVGA_3D_CMD_SCREEN_DMA:
3648 {
3649 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
3650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3651 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3652 break;
3653 }
3654
3655 case SVGA_3D_CMD_DEAD1:
3656 case SVGA_3D_CMD_DEAD2:
3657 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
3658 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
3659 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
3660 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
3661 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
3662 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
3663 {
3664 VMSVGA_3D_CMD_NOTIMPL();
3665 break;
3666 }
3667
3668 case SVGA_3D_CMD_SET_OTABLE_BASE:
3669 {
3670 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
3671 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3672 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3673 break;
3674 }
3675
3676 case SVGA_3D_CMD_READBACK_OTABLE:
3677 {
3678 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
3679 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3680 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3681 break;
3682 }
3683
3684 case SVGA_3D_CMD_DEFINE_GB_MOB:
3685 {
3686 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
3687 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3688 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
3689 break;
3690 }
3691
3692 case SVGA_3D_CMD_DESTROY_GB_MOB:
3693 {
3694 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
3695 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3696 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
3697 break;
3698 }
3699
3700 case SVGA_3D_CMD_DEAD3:
3701 {
3702 VMSVGA_3D_CMD_NOTIMPL();
3703 break;
3704 }
3705
3706 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
3707 {
3708 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
3709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3710 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3711 break;
3712 }
3713
3714 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
3715 {
3716 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
3717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3718 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
3719 break;
3720 }
3721
3722 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
3723 {
3724 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
3725 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3726 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
3727 break;
3728 }
3729
3730 case SVGA_3D_CMD_BIND_GB_SURFACE:
3731 {
3732 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
3733 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3734 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
3735 break;
3736 }
3737
3738 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
3739 {
3740 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
3741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3742 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3743 break;
3744 }
3745
3746 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
3747 {
3748 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
3749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3750 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
3751 break;
3752 }
3753
3754 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
3755 {
3756 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
3757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3758 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3759 break;
3760 }
3761
3762 case SVGA_3D_CMD_READBACK_GB_IMAGE:
3763 {
3764 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
3765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3766 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3767 break;
3768 }
3769
3770 case SVGA_3D_CMD_READBACK_GB_SURFACE:
3771 {
3772 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
3773 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3774 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3775 break;
3776 }
3777
3778 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
3779 {
3780 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
3781 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3782 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3783 break;
3784 }
3785
3786 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
3787 {
3788 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
3789 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3790 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
3791 break;
3792 }
3793
3794 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
3795 {
3796 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
3797 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3798 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3799 break;
3800 }
3801
3802 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
3803 {
3804 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
3805 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3806 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3807 break;
3808 }
3809
3810 case SVGA_3D_CMD_BIND_GB_CONTEXT:
3811 {
3812 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
3813 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3814 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3815 break;
3816 }
3817
3818 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
3819 {
3820 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
3821 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3822 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3823 break;
3824 }
3825
3826 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
3827 {
3828 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
3829 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3830 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3831 break;
3832 }
3833
3834 case SVGA_3D_CMD_DEFINE_GB_SHADER:
3835 {
3836 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
3837 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3838 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3839 break;
3840 }
3841
3842 case SVGA_3D_CMD_DESTROY_GB_SHADER:
3843 {
3844 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
3845 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3846 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3847 break;
3848 }
3849
3850 case SVGA_3D_CMD_BIND_GB_SHADER:
3851 {
3852 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
3853 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3854 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3855 break;
3856 }
3857
3858 case SVGA_3D_CMD_SET_OTABLE_BASE64:
3859 {
3860 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
3861 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3862 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
3863 break;
3864 }
3865
3866 case SVGA_3D_CMD_BEGIN_GB_QUERY:
3867 {
3868 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
3869 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3870 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3871 break;
3872 }
3873
3874 case SVGA_3D_CMD_END_GB_QUERY:
3875 {
3876 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
3877 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3878 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3879 break;
3880 }
3881
3882 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
3883 {
3884 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
3885 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3886 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3887 break;
3888 }
3889
3890 case SVGA_3D_CMD_NOP:
3891 {
3892 /* Apparently there is nothing to do. */
3893 break;
3894 }
3895
3896 case SVGA_3D_CMD_ENABLE_GART:
3897 {
3898 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
3899 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3900 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3901 break;
3902 }
3903
3904 case SVGA_3D_CMD_DISABLE_GART:
3905 {
3906 /* No corresponding SVGA3dCmd structure. */
3907 VMSVGA_3D_CMD_NOTIMPL();
3908 break;
3909 }
3910
3911 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
3912 {
3913 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
3914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3915 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3916 break;
3917 }
3918
3919 case SVGA_3D_CMD_UNMAP_GART_RANGE:
3920 {
3921 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
3922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3923 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3924 break;
3925 }
3926
3927 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
3928 {
3929 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
3930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3931 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
3932 break;
3933 }
3934
3935 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
3936 {
3937 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
3938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3939 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
3940 break;
3941 }
3942
3943 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
3944 {
3945 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
3946 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3947 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
3948 break;
3949 }
3950
3951 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
3952 {
3953 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
3954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3955 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
3956 break;
3957 }
3958
3959 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
3960 {
3961 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
3962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3963 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3964 break;
3965 }
3966
3967 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
3968 {
3969 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
3970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3971 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3972 break;
3973 }
3974
3975 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
3976 {
3977 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
3978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3979 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3980 break;
3981 }
3982
3983 case SVGA_3D_CMD_GB_SCREEN_DMA:
3984 {
3985 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
3986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3987 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3988 break;
3989 }
3990
3991 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
3992 {
3993 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
3994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3995 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
3996 break;
3997 }
3998
3999 case SVGA_3D_CMD_GB_MOB_FENCE:
4000 {
4001 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4002 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4003 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4004 break;
4005 }
4006
4007 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4008 {
4009 /// @todo SVGA3dCmdDefineGBSurface_v2 is not defined in Mesa 17 header. Mesa 20 has it.
4010 //SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4011 //VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4012 VMSVGA_3D_CMD_NOTIMPL();
4013 break;
4014 }
4015
4016 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4017 {
4018 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4019 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4020 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4021 break;
4022 }
4023
4024 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4025 {
4026 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4027 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4028 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4029 break;
4030 }
4031
4032 case SVGA_3D_CMD_NOP_ERROR:
4033 {
4034 /* Apparently there is nothing to do. */
4035 break;
4036 }
4037
4038 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4039 {
4040 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4041 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4042 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4043 break;
4044 }
4045
4046 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4047 {
4048 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4049 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4050 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4051 break;
4052 }
4053
4054 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4055 {
4056 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4058 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4059 break;
4060 }
4061
4062 case SVGA_3D_CMD_DRAW:
4063 {
4064 /* No corresponding SVGA3dCmd structure. */
4065 VMSVGA_3D_CMD_NOTIMPL();
4066 break;
4067 }
4068
4069 case SVGA_3D_CMD_DRAW_INDEXED:
4070 {
4071 /* No corresponding SVGA3dCmd structure. */
4072 VMSVGA_3D_CMD_NOTIMPL();
4073 break;
4074 }
4075
4076 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4077 {
4078 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4079 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4080 vmsvga3dCmdDXDefineContext(pThisCC, pCmd);
4081 break;
4082 }
4083
4084 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4085 {
4086 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4087 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4088 vmsvga3dCmdDXDestroyContext(pThisCC, pCmd);
4089 break;
4090 }
4091
4092 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4093 {
4094 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4095 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4096 vmsvga3dCmdDXBindContext(pThisCC, pCmd);
4097 break;
4098 }
4099
4100 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4101 {
4102 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4103 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4104 vmsvga3dCmdDXReadbackContext(pThisCC, pCmd);
4105 break;
4106 }
4107
4108 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4109 {
4110 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4111 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4112 vmsvga3dCmdDXInvalidateContext(pThisCC, pCmd);
4113 break;
4114 }
4115
4116 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4117 {
4118 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4119 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4120 vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, pCmd);
4121 break;
4122 }
4123
4124 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4125 {
4126 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4127 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4128 vmsvga3dCmdDXSetShaderResources(pThisCC, pCmd);
4129 break;
4130 }
4131
4132 case SVGA_3D_CMD_DX_SET_SHADER:
4133 {
4134 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4135 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4136 vmsvga3dCmdDXSetShader(pThisCC, pCmd);
4137 break;
4138 }
4139
4140 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4141 {
4142 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4143 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4144 vmsvga3dCmdDXSetSamplers(pThisCC, pCmd);
4145 break;
4146 }
4147
4148 case SVGA_3D_CMD_DX_DRAW:
4149 {
4150 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4151 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4152 vmsvga3dCmdDXDraw(pThisCC, pCmd);
4153 break;
4154 }
4155
4156 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4157 {
4158 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4159 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4160 vmsvga3dCmdDXDrawIndexed(pThisCC, pCmd);
4161 break;
4162 }
4163
4164 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4165 {
4166 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4167 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4168 vmsvga3dCmdDXDrawInstanced(pThisCC, pCmd);
4169 break;
4170 }
4171
4172 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4173 {
4174 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4175 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4176 vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, pCmd);
4177 break;
4178 }
4179
4180 case SVGA_3D_CMD_DX_DRAW_AUTO:
4181 {
4182 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4183 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4184 vmsvga3dCmdDXDrawAuto(pThisCC, pCmd);
4185 break;
4186 }
4187
4188 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4189 {
4190 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4191 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4192 vmsvga3dCmdDXSetInputLayout(pThisCC, pCmd);
4193 break;
4194 }
4195
4196 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4197 {
4198 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4199 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4200 vmsvga3dCmdDXSetVertexBuffers(pThisCC, pCmd);
4201 break;
4202 }
4203
4204 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4205 {
4206 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4207 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4208 vmsvga3dCmdDXSetIndexBuffer(pThisCC, pCmd);
4209 break;
4210 }
4211
4212 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4213 {
4214 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4215 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4216 vmsvga3dCmdDXSetTopology(pThisCC, pCmd);
4217 break;
4218 }
4219
4220 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4221 {
4222 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4223 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4224 vmsvga3dCmdDXSetRenderTargets(pThisCC, pCmd);
4225 break;
4226 }
4227
4228 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4229 {
4230 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4232 vmsvga3dCmdDXSetBlendState(pThisCC, pCmd);
4233 break;
4234 }
4235
4236 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4237 {
4238 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4239 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4240 vmsvga3dCmdDXSetDepthStencilState(pThisCC, pCmd);
4241 break;
4242 }
4243
4244 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4245 {
4246 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4247 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4248 vmsvga3dCmdDXSetRasterizerState(pThisCC, pCmd);
4249 break;
4250 }
4251
4252 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4253 {
4254 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4255 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4256 vmsvga3dCmdDXDefineQuery(pThisCC, pCmd);
4257 break;
4258 }
4259
4260 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4261 {
4262 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4263 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4264 vmsvga3dCmdDXDestroyQuery(pThisCC, pCmd);
4265 break;
4266 }
4267
4268 case SVGA_3D_CMD_DX_BIND_QUERY:
4269 {
4270 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4271 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4272 vmsvga3dCmdDXBindQuery(pThisCC, pCmd);
4273 break;
4274 }
4275
4276 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4277 {
4278 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4279 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4280 vmsvga3dCmdDXSetQueryOffset(pThisCC, pCmd);
4281 break;
4282 }
4283
4284 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4285 {
4286 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4287 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4288 vmsvga3dCmdDXBeginQuery(pThisCC, pCmd);
4289 break;
4290 }
4291
4292 case SVGA_3D_CMD_DX_END_QUERY:
4293 {
4294 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4295 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4296 vmsvga3dCmdDXEndQuery(pThisCC, pCmd);
4297 break;
4298 }
4299
4300 case SVGA_3D_CMD_DX_READBACK_QUERY:
4301 {
4302 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4303 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4304 vmsvga3dCmdDXReadbackQuery(pThisCC, pCmd);
4305 break;
4306 }
4307
4308 case SVGA_3D_CMD_DX_SET_PREDICATION:
4309 {
4310 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4311 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4312 vmsvga3dCmdDXSetPredication(pThisCC, pCmd);
4313 break;
4314 }
4315
4316 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4317 {
4318 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4319 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4320 vmsvga3dCmdDXSetSOTargets(pThisCC, pCmd);
4321 break;
4322 }
4323
4324 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4325 {
4326 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4327 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4328 vmsvga3dCmdDXSetViewports(pThisCC, pCmd);
4329 break;
4330 }
4331
4332 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4333 {
4334 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4335 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4336 vmsvga3dCmdDXSetScissorRects(pThisCC, pCmd);
4337 break;
4338 }
4339
4340 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4341 {
4342 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4343 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4344 vmsvga3dCmdDXClearRenderTargetView(pThisCC, pCmd);
4345 break;
4346 }
4347
4348 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4349 {
4350 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4351 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4352 vmsvga3dCmdDXClearDepthStencilView(pThisCC, pCmd);
4353 break;
4354 }
4355
4356 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4357 {
4358 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4359 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4360 vmsvga3dCmdDXPredCopyRegion(pThisCC, pCmd);
4361 break;
4362 }
4363
4364 case SVGA_3D_CMD_DX_PRED_COPY:
4365 {
4366 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4367 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4368 vmsvga3dCmdDXPredCopy(pThisCC, pCmd);
4369 break;
4370 }
4371
4372 case SVGA_3D_CMD_DX_PRESENTBLT:
4373 {
4374 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4375 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4376 vmsvga3dCmdDXPresentBlt(pThisCC, pCmd);
4377 break;
4378 }
4379
4380 case SVGA_3D_CMD_DX_GENMIPS:
4381 {
4382 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4383 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4384 vmsvga3dCmdDXGenMips(pThisCC, pCmd);
4385 break;
4386 }
4387
4388 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4389 {
4390 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4391 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4392 vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd);
4393 break;
4394 }
4395
4396 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4397 {
4398 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4399 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4400 vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd);
4401 break;
4402 }
4403
4404 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4405 {
4406 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4407 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4408 vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd);
4409 break;
4410 }
4411
4412 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4413 {
4414 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4415 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4416 vmsvga3dCmdDXDefineShaderResourceView(pThisCC, pCmd);
4417 break;
4418 }
4419
4420 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4421 {
4422 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4423 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4424 vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, pCmd);
4425 break;
4426 }
4427
4428 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4429 {
4430 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4431 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4432 vmsvga3dCmdDXDefineRenderTargetView(pThisCC, pCmd);
4433 break;
4434 }
4435
4436 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
4437 {
4438 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
4439 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4440 vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, pCmd);
4441 break;
4442 }
4443
4444 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
4445 {
4446 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
4447 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448 vmsvga3dCmdDXDefineDepthStencilView(pThisCC, pCmd);
4449 break;
4450 }
4451
4452 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
4453 {
4454 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
4455 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456 vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, pCmd);
4457 break;
4458 }
4459
4460 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
4461 {
4462 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
4463 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4464 vmsvga3dCmdDXDefineElementLayout(pThisCC, pCmd);
4465 break;
4466 }
4467
4468 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
4469 {
4470 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
4471 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4472 vmsvga3dCmdDXDestroyElementLayout(pThisCC, pCmd);
4473 break;
4474 }
4475
4476 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
4477 {
4478 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
4479 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4480 vmsvga3dCmdDXDefineBlendState(pThisCC, pCmd);
4481 break;
4482 }
4483
4484 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
4485 {
4486 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
4487 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488 vmsvga3dCmdDXDestroyBlendState(pThisCC, pCmd);
4489 break;
4490 }
4491
4492 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
4493 {
4494 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
4495 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4496 vmsvga3dCmdDXDefineDepthStencilState(pThisCC, pCmd);
4497 break;
4498 }
4499
4500 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
4501 {
4502 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
4503 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504 vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, pCmd);
4505 break;
4506 }
4507
4508 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
4509 {
4510 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
4511 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4512 vmsvga3dCmdDXDefineRasterizerState(pThisCC, pCmd);
4513 break;
4514 }
4515
4516 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
4517 {
4518 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
4519 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4520 vmsvga3dCmdDXDestroyRasterizerState(pThisCC, pCmd);
4521 break;
4522 }
4523
4524 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
4525 {
4526 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
4527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4528 vmsvga3dCmdDXDefineSamplerState(pThisCC, pCmd);
4529 break;
4530 }
4531
4532 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
4533 {
4534 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
4535 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4536 vmsvga3dCmdDXDestroySamplerState(pThisCC, pCmd);
4537 break;
4538 }
4539
4540 case SVGA_3D_CMD_DX_DEFINE_SHADER:
4541 {
4542 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
4543 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544 vmsvga3dCmdDXDefineShader(pThisCC, pCmd);
4545 break;
4546 }
4547
4548 case SVGA_3D_CMD_DX_DESTROY_SHADER:
4549 {
4550 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
4551 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4552 vmsvga3dCmdDXDestroyShader(pThisCC, pCmd);
4553 break;
4554 }
4555
4556 case SVGA_3D_CMD_DX_BIND_SHADER:
4557 {
4558 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
4559 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4560 vmsvga3dCmdDXBindShader(pThisCC, pCmd);
4561 break;
4562 }
4563
4564 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
4565 {
4566 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
4567 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4568 vmsvga3dCmdDXDefineStreamOutput(pThisCC, pCmd);
4569 break;
4570 }
4571
4572 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
4573 {
4574 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
4575 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576 vmsvga3dCmdDXDestroyStreamOutput(pThisCC, pCmd);
4577 break;
4578 }
4579
4580 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
4581 {
4582 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
4583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584 vmsvga3dCmdDXSetStreamOutput(pThisCC, pCmd);
4585 break;
4586 }
4587
4588 case SVGA_3D_CMD_DX_SET_COTABLE:
4589 {
4590 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
4591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592 vmsvga3dCmdDXSetCOTable(pThisCC, pCmd);
4593 break;
4594 }
4595
4596 case SVGA_3D_CMD_DX_READBACK_COTABLE:
4597 {
4598 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
4599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600 vmsvga3dCmdDXReadbackCOTable(pThisCC, pCmd);
4601 break;
4602 }
4603
4604 case SVGA_3D_CMD_DX_BUFFER_COPY:
4605 {
4606 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
4607 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4608 vmsvga3dCmdDXBufferCopy(pThisCC, pCmd);
4609 break;
4610 }
4611
4612 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
4613 {
4614 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
4615 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4616 vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd);
4617 break;
4618 }
4619
4620 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
4621 {
4622 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
4623 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624 vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, pCmd);
4625 break;
4626 }
4627
4628 case SVGA_3D_CMD_DX_MOVE_QUERY:
4629 {
4630 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
4631 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4632 vmsvga3dCmdDXMoveQuery(pThisCC, pCmd);
4633 break;
4634 }
4635
4636 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
4637 {
4638 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
4639 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640 vmsvga3dCmdDXBindAllQuery(pThisCC, pCmd);
4641 break;
4642 }
4643
4644 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
4645 {
4646 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
4647 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4648 vmsvga3dCmdDXReadbackAllQuery(pThisCC, pCmd);
4649 break;
4650 }
4651
4652 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
4653 {
4654 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
4655 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4656 vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, pCmd);
4657 break;
4658 }
4659
4660 case SVGA_3D_CMD_DX_MOB_FENCE_64:
4661 {
4662 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
4663 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4664 vmsvga3dCmdDXMobFence64(pThisCC, pCmd);
4665 break;
4666 }
4667
4668 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
4669 {
4670 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
4671 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4672 vmsvga3dCmdDXBindAllShader(pThisCC, pCmd);
4673 break;
4674 }
4675
4676 case SVGA_3D_CMD_DX_HINT:
4677 {
4678 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
4679 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4680 vmsvga3dCmdDXHint(pThisCC, pCmd);
4681 break;
4682 }
4683
4684 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
4685 {
4686 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
4687 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4688 vmsvga3dCmdDXBufferUpdate(pThisCC, pCmd);
4689 break;
4690 }
4691
4692 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
4693 {
4694 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
4695 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4696 vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, pCmd);
4697 break;
4698 }
4699
4700 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
4701 {
4702 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
4703 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4704 vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, pCmd);
4705 break;
4706 }
4707
4708 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
4709 {
4710 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
4711 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4712 vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, pCmd);
4713 break;
4714 }
4715
4716 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
4717 {
4718 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
4719 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4720 vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, pCmd);
4721 break;
4722 }
4723
4724 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
4725 {
4726 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
4727 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4728 vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, pCmd);
4729 break;
4730 }
4731
4732 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
4733 {
4734 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
4735 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4736 vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, pCmd);
4737 break;
4738 }
4739
4740 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
4741 {
4742 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
4743 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4744 vmsvga3dCmdDXCondBindAllShader(pThisCC, pCmd);
4745 break;
4746 }
4747
4748 case SVGA_3D_CMD_SCREEN_COPY:
4749 {
4750 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
4751 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4752 vmsvga3dCmdScreenCopy(pThisCC, pCmd);
4753 break;
4754 }
4755
4756 case SVGA_3D_CMD_RESERVED1:
4757 {
4758 VMSVGA_3D_CMD_NOTIMPL();
4759 break;
4760 }
4761
4762 case SVGA_3D_CMD_RESERVED2:
4763 {
4764 VMSVGA_3D_CMD_NOTIMPL();
4765 break;
4766 }
4767
4768 case SVGA_3D_CMD_RESERVED3:
4769 {
4770 VMSVGA_3D_CMD_NOTIMPL();
4771 break;
4772 }
4773
4774 case SVGA_3D_CMD_RESERVED4:
4775 {
4776 VMSVGA_3D_CMD_NOTIMPL();
4777 break;
4778 }
4779
4780 case SVGA_3D_CMD_RESERVED5:
4781 {
4782 VMSVGA_3D_CMD_NOTIMPL();
4783 break;
4784 }
4785
4786 case SVGA_3D_CMD_RESERVED6:
4787 {
4788 VMSVGA_3D_CMD_NOTIMPL();
4789 break;
4790 }
4791
4792 case SVGA_3D_CMD_RESERVED7:
4793 {
4794 VMSVGA_3D_CMD_NOTIMPL();
4795 break;
4796 }
4797
4798 case SVGA_3D_CMD_RESERVED8:
4799 {
4800 VMSVGA_3D_CMD_NOTIMPL();
4801 break;
4802 }
4803
4804 case SVGA_3D_CMD_GROW_OTABLE:
4805 {
4806 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
4807 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4808 vmsvga3dCmdGrowOTable(pThisCC, pCmd);
4809 break;
4810 }
4811
4812 case SVGA_3D_CMD_DX_GROW_COTABLE:
4813 {
4814 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
4815 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4816 vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd);
4817 break;
4818 }
4819
4820 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
4821 {
4822 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
4823 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4824 vmsvga3dCmdIntraSurfaceCopy(pThisCC, pCmd);
4825 break;
4826 }
4827
4828 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
4829 {
4830 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
4831 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4832 vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
4833 break;
4834 }
4835
4836 case SVGA_3D_CMD_DX_RESOLVE_COPY:
4837 {
4838 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
4839 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4840 vmsvga3dCmdDXResolveCopy(pThisCC, pCmd);
4841 break;
4842 }
4843
4844 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
4845 {
4846 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
4847 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4848 vmsvga3dCmdDXPredResolveCopy(pThisCC, pCmd);
4849 break;
4850 }
4851
4852 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
4853 {
4854 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
4855 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4856 vmsvga3dCmdDXPredConvertRegion(pThisCC, pCmd);
4857 break;
4858 }
4859
4860 case SVGA_3D_CMD_DX_PRED_CONVERT:
4861 {
4862 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
4863 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4864 vmsvga3dCmdDXPredConvert(pThisCC, pCmd);
4865 break;
4866 }
4867
4868 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
4869 {
4870 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
4871 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4872 vmsvga3dCmdWholeSurfaceCopy(pThisCC, pCmd);
4873 break;
4874 }
4875
4876 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
4877 {
4878 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
4879 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4880 vmsvga3dCmdDXDefineUAView(pThisCC, pCmd);
4881 break;
4882 }
4883
4884 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
4885 {
4886 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
4887 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4888 vmsvga3dCmdDXDestroyUAView(pThisCC, pCmd);
4889 break;
4890 }
4891
4892 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
4893 {
4894 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
4895 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4896 vmsvga3dCmdDXClearUAViewUint(pThisCC, pCmd);
4897 break;
4898 }
4899
4900 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
4901 {
4902 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
4903 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4904 vmsvga3dCmdDXClearUAViewFloat(pThisCC, pCmd);
4905 break;
4906 }
4907
4908 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
4909 {
4910 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
4911 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4912 vmsvga3dCmdDXCopyStructureCount(pThisCC, pCmd);
4913 break;
4914 }
4915
4916 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
4917 {
4918 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
4919 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4920 vmsvga3dCmdDXSetUAViews(pThisCC, pCmd);
4921 break;
4922 }
4923
4924 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
4925 {
4926 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
4927 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4928 vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, pCmd);
4929 break;
4930 }
4931
4932 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
4933 {
4934 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
4935 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4936 vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, pCmd);
4937 break;
4938 }
4939
4940 case SVGA_3D_CMD_DX_DISPATCH:
4941 {
4942 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
4943 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4944 vmsvga3dCmdDXDispatch(pThisCC, pCmd);
4945 break;
4946 }
4947
4948 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
4949 {
4950 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
4951 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4952 vmsvga3dCmdDXDispatchIndirect(pThisCC, pCmd);
4953 break;
4954 }
4955
4956 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
4957 {
4958 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
4959 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4960 vmsvga3dCmdWriteZeroSurface(pThisCC, pCmd);
4961 break;
4962 }
4963
4964 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
4965 {
4966 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
4967 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4968 vmsvga3dCmdHintZeroSurface(pThisCC, pCmd);
4969 break;
4970 }
4971
4972 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
4973 {
4974 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
4975 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4976 vmsvga3dCmdDXTransferToBuffer(pThisCC, pCmd);
4977 break;
4978 }
4979
4980 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
4981 {
4982 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
4983 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4984 vmsvga3dCmdDXSetStructureCount(pThisCC, pCmd);
4985 break;
4986 }
4987
4988 case SVGA_3D_CMD_LOGICOPS_BITBLT:
4989 {
4990 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
4991 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4992 vmsvga3dCmdLogicOpsBitBlt(pThisCC, pCmd);
4993 break;
4994 }
4995
4996 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
4997 {
4998 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
4999 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5000 vmsvga3dCmdLogicOpsTransBlt(pThisCC, pCmd);
5001 break;
5002 }
5003
5004 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5005 {
5006 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5007 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5008 vmsvga3dCmdLogicOpsStretchBlt(pThisCC, pCmd);
5009 break;
5010 }
5011
5012 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5013 {
5014 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5015 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5016 vmsvga3dCmdLogicOpsColorFill(pThisCC, pCmd);
5017 break;
5018 }
5019
5020 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5021 {
5022 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5024 vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, pCmd);
5025 break;
5026 }
5027
5028 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5029 {
5030 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5031 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5032 vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, pCmd);
5033 break;
5034 }
5035
5036 case SVGA_3D_CMD_RESERVED2_1:
5037 {
5038 VMSVGA_3D_CMD_NOTIMPL();
5039 break;
5040 }
5041
5042 case SVGA_3D_CMD_RESERVED2_2:
5043 {
5044 VMSVGA_3D_CMD_NOTIMPL();
5045 break;
5046 }
5047
5048 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5049 {
5050 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5051 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5052 vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
5053 break;
5054 }
5055
5056 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5057 {
5058 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5059 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5060 vmsvga3dCmdDXSetCSUAViews(pThisCC, pCmd);
5061 break;
5062 }
5063
5064 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5065 {
5066 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5067 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5068 vmsvga3dCmdDXSetMinLOD(pThisCC, pCmd);
5069 break;
5070 }
5071
5072 case SVGA_3D_CMD_RESERVED2_3:
5073 {
5074 VMSVGA_3D_CMD_NOTIMPL();
5075 break;
5076 }
5077
5078 case SVGA_3D_CMD_RESERVED2_4:
5079 {
5080 VMSVGA_3D_CMD_NOTIMPL();
5081 break;
5082 }
5083
5084 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5085 {
5086 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5087 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5088 vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, pCmd);
5089 break;
5090 }
5091
5092 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5093 {
5094 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5095 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5096 vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, pCmd);
5097 break;
5098 }
5099
5100 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5101 {
5102 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5103 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5104 vmsvga3dCmdDXSetShaderIface(pThisCC, pCmd);
5105 break;
5106 }
5107
5108 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5109 {
5110 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5111 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5112 vmsvga3dCmdDXBindStreamOutput(pThisCC, pCmd);
5113 break;
5114 }
5115
5116 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5117 {
5118 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5119 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5120 vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, pCmd);
5121 break;
5122 }
5123
5124 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5125 {
5126 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5127 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5128 vmsvga3dCmdDXBindShaderIface(pThisCC, pCmd);
5129 break;
5130 }
5131
5132 /* Unsupported commands. */
5133 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5134 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5135 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5136 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5137 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5138 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5139 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5140 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5141 /* Prevent the compiler warning. */
5142 case SVGA_3D_CMD_LEGACY_BASE:
5143 case SVGA_3D_CMD_MAX:
5144 case SVGA_3D_CMD_FUTURE_MAX:
5145 /* No 'default' case */
5146 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5147 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5148 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5149 rcParse = VERR_NOT_IMPLEMENTED;
5150 break;
5151 }
5152
5153 return rcParse;
5154}
5155# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5156#endif /* VBOX_WITH_VMSVGA3D */
5157
5158
5159/*
5160 *
5161 * Handlers for FIFO commands.
5162 *
5163 * Every handler takes the following parameters:
5164 *
5165 * pThis The shared VGA/VMSVGA state.
5166 * pThisCC The VGA/VMSVGA state for ring-3.
5167 * pCmd The command data.
5168 */
5169
5170
5171/* SVGA_CMD_UPDATE */
5172void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5173{
5174 RT_NOREF(pThis);
5175 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5176
5177 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5178 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5179
5180 /** @todo Multiple screens? */
5181 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5182 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5183 return;
5184
5185 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5186}
5187
5188
5189/* SVGA_CMD_UPDATE_VERBOSE */
5190void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5191{
5192 RT_NOREF(pThis);
5193 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5194
5195 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5196 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5197
5198 /** @todo Multiple screens? */
5199 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5200 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5201 return;
5202
5203 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5204}
5205
5206
5207/* SVGA_CMD_RECT_FILL */
5208void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5209{
5210 RT_NOREF(pThis, pCmd);
5211 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5212
5213 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5214 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5215 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5216}
5217
5218
5219/* SVGA_CMD_RECT_COPY */
5220void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5221{
5222 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5223
5224 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5225 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5226
5227 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5228 AssertPtrReturnVoid(pScreen);
5229
5230 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5231 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5232 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5233 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5234 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5235 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5236 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5237
5238 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5239 pCmd->width, pCmd->height, pThis->vram_size);
5240 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5241}
5242
5243
5244/* SVGA_CMD_RECT_ROP_COPY */
5245void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5246{
5247 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5248
5249 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5250 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5251
5252 if (pCmd->rop != SVGA_ROP_COPY)
5253 {
5254 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5255 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5256 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5257 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5258 */
5259 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5260 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5261 return;
5262 }
5263
5264 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5265 AssertPtrReturnVoid(pScreen);
5266
5267 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5268 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5269 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5270 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5271 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5272 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5273 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5274
5275 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5276 pCmd->width, pCmd->height, pThis->vram_size);
5277 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5278}
5279
5280
5281/* SVGA_CMD_DISPLAY_CURSOR */
5282void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5283{
5284 RT_NOREF(pThis, pCmd);
5285 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5286
5287 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5288 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5289 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5290}
5291
5292
5293/* SVGA_CMD_MOVE_CURSOR */
5294void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5295{
5296 RT_NOREF(pThis, pCmd);
5297 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5298
5299 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5300 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5301 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5302}
5303
5304
5305/* SVGA_CMD_DEFINE_CURSOR */
5306void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5307{
5308 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5309
5310 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5311 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5312 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5313
5314 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5315 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5316 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5317 RT_UNTRUSTED_VALIDATED_FENCE();
5318
5319 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5320 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5321 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5322
5323 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5324 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5325
5326 uint32_t const cx = pCmd->width;
5327 uint32_t const cy = pCmd->height;
5328
5329 /*
5330 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5331 * The AND data uses 8-bit aligned scanlines.
5332 * The XOR data must be starting on a 32-bit boundrary.
5333 */
5334 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5335 uint32_t cbDstAndMask = cbDstAndLine * cy;
5336 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5337 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5338
5339 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5340 AssertReturnVoid(pbCopy);
5341
5342 /* Convert the AND mask. */
5343 uint8_t *pbDst = pbCopy;
5344 uint8_t const *pbSrc = pbSrcAndMask;
5345 switch (pCmd->andMaskDepth)
5346 {
5347 case 1:
5348 if (cbSrcAndLine == cbDstAndLine)
5349 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5350 else
5351 {
5352 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5353 for (uint32_t y = 0; y < cy; y++)
5354 {
5355 memcpy(pbDst, pbSrc, cbDstAndLine);
5356 pbDst += cbDstAndLine;
5357 pbSrc += cbSrcAndLine;
5358 }
5359 }
5360 break;
5361 /* Should take the XOR mask into account for the multi-bit AND mask. */
5362 case 8:
5363 for (uint32_t y = 0; y < cy; y++)
5364 {
5365 for (uint32_t x = 0; x < cx; )
5366 {
5367 uint8_t bDst = 0;
5368 uint8_t fBit = 0x80;
5369 do
5370 {
5371 uintptr_t const idxPal = pbSrc[x] * 3;
5372 if ((( pThis->last_palette[idxPal]
5373 | (pThis->last_palette[idxPal] >> 8)
5374 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5375 bDst |= fBit;
5376 fBit >>= 1;
5377 x++;
5378 } while (x < cx && (x & 7));
5379 pbDst[(x - 1) / 8] = bDst;
5380 }
5381 pbDst += cbDstAndLine;
5382 pbSrc += cbSrcAndLine;
5383 }
5384 break;
5385 case 15:
5386 for (uint32_t y = 0; y < cy; y++)
5387 {
5388 for (uint32_t x = 0; x < cx; )
5389 {
5390 uint8_t bDst = 0;
5391 uint8_t fBit = 0x80;
5392 do
5393 {
5394 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5395 bDst |= fBit;
5396 fBit >>= 1;
5397 x++;
5398 } while (x < cx && (x & 7));
5399 pbDst[(x - 1) / 8] = bDst;
5400 }
5401 pbDst += cbDstAndLine;
5402 pbSrc += cbSrcAndLine;
5403 }
5404 break;
5405 case 16:
5406 for (uint32_t y = 0; y < cy; y++)
5407 {
5408 for (uint32_t x = 0; x < cx; )
5409 {
5410 uint8_t bDst = 0;
5411 uint8_t fBit = 0x80;
5412 do
5413 {
5414 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5415 bDst |= fBit;
5416 fBit >>= 1;
5417 x++;
5418 } while (x < cx && (x & 7));
5419 pbDst[(x - 1) / 8] = bDst;
5420 }
5421 pbDst += cbDstAndLine;
5422 pbSrc += cbSrcAndLine;
5423 }
5424 break;
5425 case 24:
5426 for (uint32_t y = 0; y < cy; y++)
5427 {
5428 for (uint32_t x = 0; x < cx; )
5429 {
5430 uint8_t bDst = 0;
5431 uint8_t fBit = 0x80;
5432 do
5433 {
5434 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
5435 bDst |= fBit;
5436 fBit >>= 1;
5437 x++;
5438 } while (x < cx && (x & 7));
5439 pbDst[(x - 1) / 8] = bDst;
5440 }
5441 pbDst += cbDstAndLine;
5442 pbSrc += cbSrcAndLine;
5443 }
5444 break;
5445 case 32:
5446 for (uint32_t y = 0; y < cy; y++)
5447 {
5448 for (uint32_t x = 0; x < cx; )
5449 {
5450 uint8_t bDst = 0;
5451 uint8_t fBit = 0x80;
5452 do
5453 {
5454 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
5455 bDst |= fBit;
5456 fBit >>= 1;
5457 x++;
5458 } while (x < cx && (x & 7));
5459 pbDst[(x - 1) / 8] = bDst;
5460 }
5461 pbDst += cbDstAndLine;
5462 pbSrc += cbSrcAndLine;
5463 }
5464 break;
5465 default:
5466 RTMemFreeZ(pbCopy, cbCopy);
5467 AssertFailedReturnVoid();
5468 }
5469
5470 /* Convert the XOR mask. */
5471 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
5472 pbSrc = pbSrcXorMask;
5473 switch (pCmd->xorMaskDepth)
5474 {
5475 case 1:
5476 for (uint32_t y = 0; y < cy; y++)
5477 {
5478 for (uint32_t x = 0; x < cx; )
5479 {
5480 /* most significant bit is the left most one. */
5481 uint8_t bSrc = pbSrc[x / 8];
5482 do
5483 {
5484 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
5485 bSrc <<= 1;
5486 x++;
5487 } while ((x & 7) && x < cx);
5488 }
5489 pbSrc += cbSrcXorLine;
5490 }
5491 break;
5492 case 8:
5493 for (uint32_t y = 0; y < cy; y++)
5494 {
5495 for (uint32_t x = 0; x < cx; x++)
5496 {
5497 uint32_t u = pThis->last_palette[pbSrc[x]];
5498 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
5499 }
5500 pbSrc += cbSrcXorLine;
5501 }
5502 break;
5503 case 15: /* Src: RGB-5-5-5 */
5504 for (uint32_t y = 0; y < cy; y++)
5505 {
5506 for (uint32_t x = 0; x < cx; x++)
5507 {
5508 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
5509 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
5510 ((uValue >> 5) & 0x1f) << 3,
5511 ((uValue >> 10) & 0x1f) << 3, 0);
5512 }
5513 pbSrc += cbSrcXorLine;
5514 }
5515 break;
5516 case 16: /* Src: RGB-5-6-5 */
5517 for (uint32_t y = 0; y < cy; y++)
5518 {
5519 for (uint32_t x = 0; x < cx; x++)
5520 {
5521 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
5522 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
5523 ((uValue >> 5) & 0x3f) << 2,
5524 ((uValue >> 11) & 0x1f) << 3, 0);
5525 }
5526 pbSrc += cbSrcXorLine;
5527 }
5528 break;
5529 case 24:
5530 for (uint32_t y = 0; y < cy; y++)
5531 {
5532 for (uint32_t x = 0; x < cx; x++)
5533 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
5534 pbSrc += cbSrcXorLine;
5535 }
5536 break;
5537 case 32:
5538 for (uint32_t y = 0; y < cy; y++)
5539 {
5540 for (uint32_t x = 0; x < cx; x++)
5541 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
5542 pbSrc += cbSrcXorLine;
5543 }
5544 break;
5545 default:
5546 RTMemFreeZ(pbCopy, cbCopy);
5547 AssertFailedReturnVoid();
5548 }
5549
5550 /*
5551 * Pass it to the frontend/whatever.
5552 */
5553 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
5554 cx, cy, pbCopy, cbCopy);
5555}
5556
5557
5558/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
5559void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
5560{
5561 RT_NOREF(pThis);
5562 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5563
5564 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
5565 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
5566
5567 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
5568 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5569 RT_UNTRUSTED_VALIDATED_FENCE();
5570
5571 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
5572 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
5573 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
5574 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
5575 uint32_t cbCursorShape = cbAndMask + cbXorMask;
5576
5577 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
5578 AssertPtrReturnVoid(pCursorCopy);
5579
5580 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
5581 memset(pCursorCopy, 0xff, cbAndMask);
5582 /* Colour data */
5583 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
5584
5585 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
5586 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
5587}
5588
5589
5590/* SVGA_CMD_ESCAPE */
5591void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
5592{
5593 RT_NOREF(pThis);
5594 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5595
5596 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
5597
5598 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
5599 {
5600 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
5601 RT_UNTRUSTED_VALIDATED_FENCE();
5602
5603 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
5604 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
5605
5606 switch (cmd)
5607 {
5608 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
5609 {
5610 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
5611 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
5612 RT_UNTRUSTED_VALIDATED_FENCE();
5613
5614 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
5615
5616 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
5617 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
5618 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
5619 RT_NOREF_PV(pVideoCmd);
5620 break;
5621 }
5622
5623 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
5624 {
5625 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
5626 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
5627 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
5628 RT_NOREF_PV(pVideoCmd);
5629 break;
5630 }
5631
5632 default:
5633 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
5634 break;
5635 }
5636 }
5637 else
5638 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
5639}
5640
5641
5642/* SVGA_CMD_DEFINE_SCREEN */
5643void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
5644{
5645 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5646
5647 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
5648 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
5649 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
5650 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
5651
5652 uint32_t const idScreen = pCmd->screen.id;
5653 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
5654
5655 uint32_t const uWidth = pCmd->screen.size.width;
5656 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
5657
5658 uint32_t const uHeight = pCmd->screen.size.height;
5659 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
5660
5661 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
5662 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
5663 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
5664
5665 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
5666 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
5667
5668 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
5669 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
5670 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
5671 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
5672 RT_UNTRUSTED_VALIDATED_FENCE();
5673
5674 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
5675 pScreen->fDefined = true;
5676 pScreen->fModified = true;
5677 pScreen->fuScreen = pCmd->screen.flags;
5678 pScreen->idScreen = idScreen;
5679 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
5680 {
5681 /* Not blanked. */
5682 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
5683 RT_UNTRUSTED_VALIDATED_FENCE();
5684
5685 pScreen->xOrigin = pCmd->screen.root.x;
5686 pScreen->yOrigin = pCmd->screen.root.y;
5687 pScreen->cWidth = uWidth;
5688 pScreen->cHeight = uHeight;
5689 pScreen->offVRAM = uScreenOffset;
5690 pScreen->cbPitch = cbPitch;
5691 pScreen->cBpp = 32;
5692 }
5693 else
5694 {
5695 /* Screen blanked. Keep old values. */
5696 }
5697
5698 pThis->svga.fGFBRegisters = false;
5699 vmsvgaR3ChangeMode(pThis, pThisCC);
5700
5701#ifdef VBOX_WITH_VMSVGA3D
5702 if (RT_LIKELY(pThis->svga.f3DEnabled))
5703 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
5704#endif
5705}
5706
5707
5708/* SVGA_CMD_DESTROY_SCREEN */
5709void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
5710{
5711 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5712
5713 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
5714 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
5715
5716 uint32_t const idScreen = pCmd->screenId;
5717 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
5718 RT_UNTRUSTED_VALIDATED_FENCE();
5719
5720 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
5721 pScreen->fModified = true;
5722 pScreen->fDefined = false;
5723 pScreen->idScreen = idScreen;
5724
5725#ifdef VBOX_WITH_VMSVGA3D
5726 if (RT_LIKELY(pThis->svga.f3DEnabled))
5727 vmsvga3dDestroyScreen(pThisCC, pScreen);
5728#endif
5729 vmsvgaR3ChangeMode(pThis, pThisCC);
5730}
5731
5732
5733/* SVGA_CMD_DEFINE_GMRFB */
5734void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
5735{
5736 RT_NOREF(pThis);
5737 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5738
5739 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
5740 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
5741 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
5742
5743 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
5744 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
5745 pSvgaR3State->GMRFB.format = pCmd->format;
5746}
5747
5748
5749/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
5750void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
5751{
5752 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5753
5754 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
5755 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
5756 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
5757
5758 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
5759 RT_UNTRUSTED_VALIDATED_FENCE();
5760
5761 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
5762 AssertPtrReturnVoid(pScreen);
5763
5764 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
5765 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
5766
5767 /* Clip destRect to the screen dimensions. */
5768 SVGASignedRect screenRect;
5769 screenRect.left = 0;
5770 screenRect.top = 0;
5771 screenRect.right = pScreen->cWidth;
5772 screenRect.bottom = pScreen->cHeight;
5773 SVGASignedRect clipRect = pCmd->destRect;
5774 vmsvgaR3ClipRect(&screenRect, &clipRect);
5775 RT_UNTRUSTED_VALIDATED_FENCE();
5776
5777 uint32_t const width = clipRect.right - clipRect.left;
5778 uint32_t const height = clipRect.bottom - clipRect.top;
5779
5780 if ( width == 0
5781 || height == 0)
5782 return; /* Nothing to do. */
5783
5784 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
5785 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
5786
5787 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
5788 * Prepare parameters for vmsvgaR3GmrTransfer.
5789 */
5790 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
5791
5792 /* Destination: host buffer which describes the screen 0 VRAM.
5793 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
5794 */
5795 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
5796 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
5797 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
5798 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
5799 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
5800 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
5801 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
5802 + cbScanline * clipRect.top;
5803 int32_t const cbHstPitch = cbScanline;
5804
5805 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
5806 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
5807 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
5808 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
5809 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
5810
5811 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
5812 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5813 gstPtr, offGst, cbGstPitch,
5814 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
5815 AssertRC(rc);
5816 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
5817}
5818
5819
5820/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
5821void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
5822{
5823 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5824
5825 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
5826 /* Note! This can fetch 3d render results as well!! */
5827 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
5828 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
5829
5830 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
5831 RT_UNTRUSTED_VALIDATED_FENCE();
5832
5833 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
5834 AssertPtrReturnVoid(pScreen);
5835
5836 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
5837 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
5838
5839 /* Clip destRect to the screen dimensions. */
5840 SVGASignedRect screenRect;
5841 screenRect.left = 0;
5842 screenRect.top = 0;
5843 screenRect.right = pScreen->cWidth;
5844 screenRect.bottom = pScreen->cHeight;
5845 SVGASignedRect clipRect = pCmd->srcRect;
5846 vmsvgaR3ClipRect(&screenRect, &clipRect);
5847 RT_UNTRUSTED_VALIDATED_FENCE();
5848
5849 uint32_t const width = clipRect.right - clipRect.left;
5850 uint32_t const height = clipRect.bottom - clipRect.top;
5851
5852 if ( width == 0
5853 || height == 0)
5854 return; /* Nothing to do. */
5855
5856 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
5857 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
5858
5859 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
5860 * Prepare parameters for vmsvgaR3GmrTransfer.
5861 */
5862 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
5863
5864 /* Source: host buffer which describes the screen 0 VRAM.
5865 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
5866 */
5867 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
5868 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
5869 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
5870 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
5871 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
5872 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
5873 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
5874 + cbScanline * clipRect.top;
5875 int32_t const cbHstPitch = cbScanline;
5876
5877 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
5878 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
5879 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
5880 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
5881 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
5882
5883 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
5884 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5885 gstPtr, offGst, cbGstPitch,
5886 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
5887 AssertRC(rc);
5888}
5889
5890
5891/* SVGA_CMD_ANNOTATION_FILL */
5892void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
5893{
5894 RT_NOREF(pThis);
5895 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5896
5897 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
5898 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
5899
5900 pSvgaR3State->colorAnnotation = pCmd->color;
5901}
5902
5903
5904/* SVGA_CMD_ANNOTATION_COPY */
5905void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
5906{
5907 RT_NOREF(pThis, pCmd);
5908 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5909
5910 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
5911 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
5912
5913 AssertFailed();
5914}
5915
5916
5917#ifdef VBOX_WITH_VMSVGA3D
5918/* SVGA_CMD_DEFINE_GMR2 */
5919void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
5920{
5921 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5922
5923 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
5924 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
5925
5926 /* Validate current GMR id. */
5927 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
5928 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
5929 RT_UNTRUSTED_VALIDATED_FENCE();
5930
5931 if (!pCmd->numPages)
5932 {
5933 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
5934 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
5935 }
5936 else
5937 {
5938 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
5939 if (pGMR->cMaxPages)
5940 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
5941
5942 /* Not sure if we should always free the descriptor, but for simplicity
5943 we do so if the new size is smaller than the current. */
5944 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
5945 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
5946 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
5947
5948 pGMR->cMaxPages = pCmd->numPages;
5949 /* The rest is done by the REMAP_GMR2 command. */
5950 }
5951}
5952
5953
5954/* SVGA_CMD_REMAP_GMR2 */
5955void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
5956{
5957 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5958
5959 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
5960 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
5961
5962 /* Validate current GMR id and size. */
5963 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
5964 RT_UNTRUSTED_VALIDATED_FENCE();
5965 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
5966 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
5967 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
5968 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
5969
5970 if (pCmd->numPages == 0)
5971 return;
5972 RT_UNTRUSTED_VALIDATED_FENCE();
5973
5974 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
5975 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
5976
5977 /*
5978 * We flatten the existing descriptors into a page array, overwrite the
5979 * pages specified in this command and then recompress the descriptor.
5980 */
5981 /** @todo Optimize the GMR remap algorithm! */
5982
5983 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
5984 uint64_t *paNewPage64 = NULL;
5985 if (pGMR->paDesc)
5986 {
5987 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
5988
5989 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
5990 AssertPtrReturnVoid(paNewPage64);
5991
5992 uint32_t idxPage = 0;
5993 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
5994 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
5995 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
5996 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
5997 RT_UNTRUSTED_VALIDATED_FENCE();
5998 }
5999
6000 /* Free the old GMR if present. */
6001 if (pGMR->paDesc)
6002 RTMemFree(pGMR->paDesc);
6003
6004 /* Allocate the maximum amount possible (everything non-continuous) */
6005 PVMSVGAGMRDESCRIPTOR paDescs;
6006 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6007 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6008
6009 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6010 {
6011 /** @todo */
6012 AssertFailed();
6013 pGMR->numDescriptors = 0;
6014 }
6015 else
6016 {
6017 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6018 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6019 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6020
6021 uint32_t cPages;
6022 if (paNewPage64)
6023 {
6024 /* Overwrite the old page array with the new page values. */
6025 if (fGCPhys64)
6026 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6027 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6028 else
6029 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6030 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6031
6032 /* Use the updated page array instead of the command data. */
6033 fGCPhys64 = true;
6034 paPages64 = paNewPage64;
6035 cPages = cNewTotalPages;
6036 }
6037 else
6038 cPages = pCmd->numPages;
6039
6040 /* The first page. */
6041 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6042 * applied to paNewPage64. */
6043 RTGCPHYS GCPhys;
6044 if (fGCPhys64)
6045 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6046 else
6047 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6048 paDescs[0].GCPhys = GCPhys;
6049 paDescs[0].numPages = 1;
6050
6051 /* Subsequent pages. */
6052 uint32_t iDescriptor = 0;
6053 for (uint32_t i = 1; i < cPages; i++)
6054 {
6055 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6056 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6057 else
6058 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6059
6060 /* Continuous physical memory? */
6061 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6062 {
6063 Assert(paDescs[iDescriptor].numPages);
6064 paDescs[iDescriptor].numPages++;
6065 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6066 }
6067 else
6068 {
6069 iDescriptor++;
6070 paDescs[iDescriptor].GCPhys = GCPhys;
6071 paDescs[iDescriptor].numPages = 1;
6072 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6073 }
6074 }
6075
6076 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6077 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6078 pGMR->numDescriptors = iDescriptor + 1;
6079 }
6080
6081 if (paNewPage64)
6082 RTMemFree(paNewPage64);
6083}
6084
6085
6086/**
6087 * Free the specified GMR
6088 *
6089 * @param pThisCC The VGA/VMSVGA state for ring-3.
6090 * @param idGMR GMR id
6091 */
6092void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6093{
6094 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6095
6096 /* Free the old descriptor if present. */
6097 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6098 if ( pGMR->numDescriptors
6099 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6100 {
6101# ifdef DEBUG_GMR_ACCESS
6102 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6103# endif
6104
6105 Assert(pGMR->paDesc);
6106 RTMemFree(pGMR->paDesc);
6107 pGMR->paDesc = NULL;
6108 pGMR->numDescriptors = 0;
6109 pGMR->cbTotal = 0;
6110 pGMR->cMaxPages = 0;
6111 }
6112 Assert(!pGMR->cMaxPages);
6113 Assert(!pGMR->cbTotal);
6114}
6115#endif /* VBOX_WITH_VMSVGA3D */
6116
6117
6118/**
6119 * Copy between a GMR and a host memory buffer.
6120 *
6121 * @returns VBox status code.
6122 * @param pThis The shared VGA/VMSVGA instance data.
6123 * @param pThisCC The VGA/VMSVGA state for ring-3.
6124 * @param enmTransferType Transfer type (read/write)
6125 * @param pbHstBuf Host buffer pointer (valid)
6126 * @param cbHstBuf Size of host buffer (valid)
6127 * @param offHst Host buffer offset of the first scanline
6128 * @param cbHstPitch Destination buffer pitch
6129 * @param gstPtr GMR description
6130 * @param offGst Guest buffer offset of the first scanline
6131 * @param cbGstPitch Guest buffer pitch
6132 * @param cbWidth Width in bytes to copy
6133 * @param cHeight Number of scanllines to copy
6134 */
6135int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6136 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6137 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6138 uint32_t cbWidth, uint32_t cHeight)
6139{
6140 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6141 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6142 int rc;
6143
6144 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6145 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6146 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6147 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6148 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6149
6150 PGMR pGMR;
6151 uint32_t cbGmr; /* The GMR size in bytes. */
6152 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6153 {
6154 pGMR = NULL;
6155 cbGmr = pThis->vram_size;
6156 }
6157 else
6158 {
6159 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6160 RT_UNTRUSTED_VALIDATED_FENCE();
6161 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6162 cbGmr = pGMR->cbTotal;
6163 }
6164
6165 /*
6166 * GMR
6167 */
6168 /* Calculate GMR offset of the data to be copied. */
6169 AssertMsgReturn(gstPtr.offset < cbGmr,
6170 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6171 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6172 VERR_INVALID_PARAMETER);
6173 RT_UNTRUSTED_VALIDATED_FENCE();
6174 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6175 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6176 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6177 VERR_INVALID_PARAMETER);
6178 RT_UNTRUSTED_VALIDATED_FENCE();
6179 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6180
6181 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6182 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6183 AssertMsgReturn(cbGmrScanline != 0,
6184 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6185 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6186 VERR_INVALID_PARAMETER);
6187 RT_UNTRUSTED_VALIDATED_FENCE();
6188 AssertMsgReturn(cbWidth <= cbGmrScanline,
6189 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6190 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6191 VERR_INVALID_PARAMETER);
6192 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6193 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6194 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6195 VERR_INVALID_PARAMETER);
6196 RT_UNTRUSTED_VALIDATED_FENCE();
6197
6198 /* How many bytes are available for the data in the GMR. */
6199 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6200
6201 /* How many scanlines would fit into the available data. */
6202 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6203 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6204 if (cbWidth <= cbGmrLastScanline)
6205 ++cGmrScanlines;
6206
6207 if (cHeight > cGmrScanlines)
6208 cHeight = cGmrScanlines;
6209
6210 AssertMsgReturn(cHeight > 0,
6211 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6212 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6213 VERR_INVALID_PARAMETER);
6214 RT_UNTRUSTED_VALIDATED_FENCE();
6215
6216 /*
6217 * Host buffer.
6218 */
6219 AssertMsgReturn(offHst < cbHstBuf,
6220 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6221 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6222 VERR_INVALID_PARAMETER);
6223
6224 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6225 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6226 AssertMsgReturn(cbHstScanline != 0,
6227 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6228 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6229 VERR_INVALID_PARAMETER);
6230 AssertMsgReturn(cbWidth <= cbHstScanline,
6231 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6232 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6233 VERR_INVALID_PARAMETER);
6234 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6235 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6236 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6237 VERR_INVALID_PARAMETER);
6238
6239 /* How many bytes are available for the data in the buffer. */
6240 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6241
6242 /* How many scanlines would fit into the available data. */
6243 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6244 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6245 if (cbWidth <= cbHstLastScanline)
6246 ++cHstScanlines;
6247
6248 if (cHeight > cHstScanlines)
6249 cHeight = cHstScanlines;
6250
6251 AssertMsgReturn(cHeight > 0,
6252 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6253 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6254 VERR_INVALID_PARAMETER);
6255
6256 uint8_t *pbHst = pbHstBuf + offHst;
6257
6258 /* Shortcut for the framebuffer. */
6259 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6260 {
6261 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6262
6263 uint8_t const *pbSrc;
6264 int32_t cbSrcPitch;
6265 uint8_t *pbDst;
6266 int32_t cbDstPitch;
6267
6268 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6269 {
6270 pbSrc = pbHst;
6271 cbSrcPitch = cbHstPitch;
6272 pbDst = pbGst;
6273 cbDstPitch = cbGstPitch;
6274 }
6275 else
6276 {
6277 pbSrc = pbGst;
6278 cbSrcPitch = cbGstPitch;
6279 pbDst = pbHst;
6280 cbDstPitch = cbHstPitch;
6281 }
6282
6283 if ( cbWidth == (uint32_t)cbGstPitch
6284 && cbGstPitch == cbHstPitch)
6285 {
6286 /* Entire scanlines, positive pitch. */
6287 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6288 }
6289 else
6290 {
6291 for (uint32_t i = 0; i < cHeight; ++i)
6292 {
6293 memcpy(pbDst, pbSrc, cbWidth);
6294
6295 pbDst += cbDstPitch;
6296 pbSrc += cbSrcPitch;
6297 }
6298 }
6299 return VINF_SUCCESS;
6300 }
6301
6302 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6303 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6304
6305 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6306 uint32_t iDesc = 0; /* Index in the descriptor array. */
6307 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6308 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6309 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6310 for (uint32_t i = 0; i < cHeight; ++i)
6311 {
6312 uint32_t cbCurrentWidth = cbWidth;
6313 uint32_t offGmrCurrent = offGmrScanline;
6314 uint8_t *pbCurrentHost = pbHstScanline;
6315
6316 /* Find the right descriptor */
6317 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6318 {
6319 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6320 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6321 ++iDesc;
6322 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6323 }
6324
6325 while (cbCurrentWidth)
6326 {
6327 uint32_t cbToCopy;
6328
6329 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6330 {
6331 cbToCopy = cbCurrentWidth;
6332 }
6333 else
6334 {
6335 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6336 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6337 }
6338
6339 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6340
6341 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6342
6343 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6344 rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6345 else
6346 rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6347 AssertRCBreak(rc);
6348
6349 cbCurrentWidth -= cbToCopy;
6350 offGmrCurrent += cbToCopy;
6351 pbCurrentHost += cbToCopy;
6352
6353 /* Go to the next descriptor if there's anything left. */
6354 if (cbCurrentWidth)
6355 {
6356 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6357 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6358 ++iDesc;
6359 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6360 }
6361 }
6362
6363 offGmrScanline += cbGstPitch;
6364 pbHstScanline += cbHstPitch;
6365 }
6366
6367 return VINF_SUCCESS;
6368}
6369
6370
6371/**
6372 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6373 *
6374 * @param pSizeSrc Source surface dimensions.
6375 * @param pSizeDest Destination surface dimensions.
6376 * @param pBox Coordinates to be clipped.
6377 */
6378void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6379{
6380 /* Src x, w */
6381 if (pBox->srcx > pSizeSrc->width)
6382 pBox->srcx = pSizeSrc->width;
6383 if (pBox->w > pSizeSrc->width - pBox->srcx)
6384 pBox->w = pSizeSrc->width - pBox->srcx;
6385
6386 /* Src y, h */
6387 if (pBox->srcy > pSizeSrc->height)
6388 pBox->srcy = pSizeSrc->height;
6389 if (pBox->h > pSizeSrc->height - pBox->srcy)
6390 pBox->h = pSizeSrc->height - pBox->srcy;
6391
6392 /* Src z, d */
6393 if (pBox->srcz > pSizeSrc->depth)
6394 pBox->srcz = pSizeSrc->depth;
6395 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6396 pBox->d = pSizeSrc->depth - pBox->srcz;
6397
6398 /* Dest x, w */
6399 if (pBox->x > pSizeDest->width)
6400 pBox->x = pSizeDest->width;
6401 if (pBox->w > pSizeDest->width - pBox->x)
6402 pBox->w = pSizeDest->width - pBox->x;
6403
6404 /* Dest y, h */
6405 if (pBox->y > pSizeDest->height)
6406 pBox->y = pSizeDest->height;
6407 if (pBox->h > pSizeDest->height - pBox->y)
6408 pBox->h = pSizeDest->height - pBox->y;
6409
6410 /* Dest z, d */
6411 if (pBox->z > pSizeDest->depth)
6412 pBox->z = pSizeDest->depth;
6413 if (pBox->d > pSizeDest->depth - pBox->z)
6414 pBox->d = pSizeDest->depth - pBox->z;
6415}
6416
6417
6418/**
6419 * Unsigned coordinates in pBox. Clip to [0; pSize).
6420 *
6421 * @param pSize Source surface dimensions.
6422 * @param pBox Coordinates to be clipped.
6423 */
6424void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6425{
6426 /* x, w */
6427 if (pBox->x > pSize->width)
6428 pBox->x = pSize->width;
6429 if (pBox->w > pSize->width - pBox->x)
6430 pBox->w = pSize->width - pBox->x;
6431
6432 /* y, h */
6433 if (pBox->y > pSize->height)
6434 pBox->y = pSize->height;
6435 if (pBox->h > pSize->height - pBox->y)
6436 pBox->h = pSize->height - pBox->y;
6437
6438 /* z, d */
6439 if (pBox->z > pSize->depth)
6440 pBox->z = pSize->depth;
6441 if (pBox->d > pSize->depth - pBox->z)
6442 pBox->d = pSize->depth - pBox->z;
6443}
6444
6445
6446/**
6447 * Clip.
6448 *
6449 * @param pBound Bounding rectangle.
6450 * @param pRect Rectangle to be clipped.
6451 */
6452void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
6453{
6454 int32_t left;
6455 int32_t top;
6456 int32_t right;
6457 int32_t bottom;
6458
6459 /* Right order. */
6460 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
6461 if (pRect->left < pRect->right)
6462 {
6463 left = pRect->left;
6464 right = pRect->right;
6465 }
6466 else
6467 {
6468 left = pRect->right;
6469 right = pRect->left;
6470 }
6471 if (pRect->top < pRect->bottom)
6472 {
6473 top = pRect->top;
6474 bottom = pRect->bottom;
6475 }
6476 else
6477 {
6478 top = pRect->bottom;
6479 bottom = pRect->top;
6480 }
6481
6482 if (left < pBound->left)
6483 left = pBound->left;
6484 if (right < pBound->left)
6485 right = pBound->left;
6486
6487 if (left > pBound->right)
6488 left = pBound->right;
6489 if (right > pBound->right)
6490 right = pBound->right;
6491
6492 if (top < pBound->top)
6493 top = pBound->top;
6494 if (bottom < pBound->top)
6495 bottom = pBound->top;
6496
6497 if (top > pBound->bottom)
6498 top = pBound->bottom;
6499 if (bottom > pBound->bottom)
6500 bottom = pBound->bottom;
6501
6502 pRect->left = left;
6503 pRect->right = right;
6504 pRect->top = top;
6505 pRect->bottom = bottom;
6506}
6507
6508
6509/**
6510 * Clip.
6511 *
6512 * @param pBound Bounding rectangle.
6513 * @param pRect Rectangle to be clipped.
6514 */
6515void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
6516{
6517 uint32_t const leftBound = pBound->x;
6518 uint32_t const rightBound = pBound->x + pBound->w;
6519 uint32_t const topBound = pBound->y;
6520 uint32_t const bottomBound = pBound->y + pBound->h;
6521
6522 uint32_t x = pRect->x;
6523 uint32_t y = pRect->y;
6524 uint32_t w = pRect->w;
6525 uint32_t h = pRect->h;
6526
6527 /* Make sure that right and bottom coordinates can be safely computed. */
6528 if (x > rightBound)
6529 x = rightBound;
6530 if (w > rightBound - x)
6531 w = rightBound - x;
6532 if (y > bottomBound)
6533 y = bottomBound;
6534 if (h > bottomBound - y)
6535 h = bottomBound - y;
6536
6537 /* Switch from x, y, w, h to left, top, right, bottom. */
6538 uint32_t left = x;
6539 uint32_t right = x + w;
6540 uint32_t top = y;
6541 uint32_t bottom = y + h;
6542
6543 /* A standard left, right, bottom, top clipping. */
6544 if (left < leftBound)
6545 left = leftBound;
6546 if (right < leftBound)
6547 right = leftBound;
6548
6549 if (left > rightBound)
6550 left = rightBound;
6551 if (right > rightBound)
6552 right = rightBound;
6553
6554 if (top < topBound)
6555 top = topBound;
6556 if (bottom < topBound)
6557 bottom = topBound;
6558
6559 if (top > bottomBound)
6560 top = bottomBound;
6561 if (bottom > bottomBound)
6562 bottom = bottomBound;
6563
6564 /* Back to x, y, w, h representation. */
6565 pRect->x = left;
6566 pRect->y = top;
6567 pRect->w = right - left;
6568 pRect->h = bottom - top;
6569}
6570
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