VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 91441

Last change on this file since 91441 was 91441, checked in by vboxsync, 3 years ago

Devices/Graphics: staging buffer for transfers; stream output: bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 271.5 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 91441 2021-09-28 17:37:53Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344/*
345 *
346 * Guest-Backed Objects (GBO).
347 *
348 */
349
350/**
351 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
352 *
353 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
354 * @param pVM VM Handle.
355 * @param pVCpu The cross context CPU structure for the calling EMT.
356 * @param GCPhys The physical address the guest is writing to.
357 * @param pvPhys The HC mapping of that address.
358 * @param pvBuf What the guest is reading/writing.
359 * @param cbBuf How much it's reading/writing.
360 * @param enmAccessType The access type.
361 * @param enmOrigin Who is making the access.
362 * @param pvUser User argument.
363 */
364DECLCALLBACK(VBOXSTRICTRC)
365vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
366 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
367{
368 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
369
370 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
371 return VINF_PGM_HANDLER_DO_DEFAULT;
372
373 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
374 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
375 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
376 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
377
378 /*
379 * The guest is not allowed to access the memory.
380 * Set the error condition.
381 */
382 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
383
384 /* Try to find the GBO which the guest is accessing. */
385 char const *pszTarget = NULL;
386 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
387 {
388 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
389 if (pGbo->cDescriptors)
390 {
391 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
392 {
393 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
394 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
395 {
396 switch (i)
397 {
398 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
399 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
400 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
401 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
402 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
403 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
404 default: pszTarget = "Unknown OTABLE"; break;
405 }
406 break;
407 }
408 }
409 }
410 }
411
412 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
413 "%.*Rhxd\n",
414 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
415
416 return VINF_PGM_HANDLER_DO_DEFAULT;
417}
418
419
420#ifdef VBOX_WITH_VMSVGA3D
421static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
422{
423 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
424
425 /*
426 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
427 * Content of the root page depends on the ptDepth value:
428 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
429 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
431 * The code below extracts the page addresses of the GBO.
432 */
433
434 /* Verify and normalize the ptDepth value. */
435 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
436 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
438 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
439 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
440 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
442 {
443 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
444 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
445 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
446 }
447 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
448 { }
449 else
450 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
451
452 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
453
454 pGbo->cbTotal = sizeInBytes;
455 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
456
457 /* Allocate the maximum amount possible (everything non-continuous) */
458 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
459 AssertReturn(paDescriptors, VERR_NO_MEMORY);
460
461 int rc = VINF_SUCCESS;
462 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
463 {
464 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
465 RTMemFree(paDescriptors),
466 VERR_INVALID_PARAMETER);
467
468 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
469 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
470 paDescriptors[0].GCPhys = GCPhys;
471 paDescriptors[0].cPages = 1;
472 }
473 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
474 {
475 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
476 RTMemFree(paDescriptors),
477 VERR_INVALID_PARAMETER);
478
479 /* Read the root page. */
480 uint8_t au8RootPage[X86_PAGE_SIZE];
481 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
482 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
483 if (RT_SUCCESS(rc))
484 {
485 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
486 PPN *paPPN32 = (PPN *)&au8RootPage[0];
487 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
488 {
489 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
490 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
491 paDescriptors[iPPN].GCPhys = GCPhys;
492 paDescriptors[iPPN].cPages = 1;
493 }
494 }
495 }
496 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
497 {
498 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
499 RTMemFree(paDescriptors),
500 VERR_INVALID_PARAMETER);
501
502 /* Read the Level2 root page. */
503 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
504 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
505 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
506 if (RT_SUCCESS(rc))
507 {
508 uint32_t cPagesLeft = pGbo->cTotalPages;
509
510 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
511 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
512
513 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
514 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
515 {
516 /* Read the Level1 root page. */
517 uint8_t au8RootPage[X86_PAGE_SIZE];
518 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
519 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
520 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
521 if (RT_SUCCESS(rc))
522 {
523 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
524 PPN *paPPN32 = (PPN *)&au8RootPage[0];
525
526 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
527 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
528 {
529 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
530 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
531 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
533 }
534 cPagesLeft -= cPPNs;
535 }
536 }
537 }
538 }
539 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
540 {
541 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
542 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
543 paDescriptors[0].GCPhys = GCPhys;
544 paDescriptors[0].cPages = pGbo->cTotalPages;
545 }
546 else
547 {
548 AssertFailed();
549 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
550 }
551
552 /* Compress the descriptors. */
553 if (ptDepth != SVGA3D_MOBFMT_RANGE)
554 {
555 uint32_t iDescriptor = 0;
556 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
557 {
558 /* Continuous physical memory? */
559 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
560 {
561 Assert(paDescriptors[iDescriptor].cPages);
562 paDescriptors[iDescriptor].cPages++;
563 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
564 }
565 else
566 {
567 iDescriptor++;
568 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
569 paDescriptors[iDescriptor].cPages = 1;
570 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
571 }
572 }
573
574 pGbo->cDescriptors = iDescriptor + 1;
575 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
576 }
577 else
578 pGbo->cDescriptors = 1;
579
580 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
581 {
582 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
583 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
584 }
585 else
586 pGbo->paDescriptors = paDescriptors;
587
588#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
589fWriteProtected = false;
590#endif
591 if (fWriteProtected)
592 {
593 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
594 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
595 {
596 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
597 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
598 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
599 AssertRC(rc);
600 }
601 }
602
603 return VINF_SUCCESS;
604}
605
606
607static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
608{
609 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
610 {
611 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
612 {
613 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
614 {
615 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
616 AssertRC(rc);
617 }
618 }
619 RTMemFree(pGbo->paDescriptors);
620 RT_ZERO(pGbo);
621 }
622}
623
624/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
625
626typedef enum VMSVGAGboTransferDirection
627{
628 VMSVGAGboTransferDirection_Read,
629 VMSVGAGboTransferDirection_Write,
630} VMSVGAGboTransferDirection;
631
632static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
633 uint32_t off, void *pvData, uint32_t cbData,
634 VMSVGAGboTransferDirection enmDirection)
635{
636 //DEBUG_BREAKPOINT_TEST();
637 int rc = VINF_SUCCESS;
638 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
639
640 /* Find the right descriptor */
641 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
642 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
643 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
644 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
645 {
646 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
647 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
648 ++iDescriptor;
649 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
650 }
651
652 while (cbData)
653 {
654 uint32_t cbToCopy;
655 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
656 cbToCopy = cbData;
657 else
658 {
659 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
660 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
661 }
662
663 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
664 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
665
666 /*
667 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
668 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
669 * see @bugref{9654#c75}.
670 */
671 if (enmDirection == VMSVGAGboTransferDirection_Read)
672 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
673 else
674 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
675 AssertRCBreak(rc);
676
677 cbData -= cbToCopy;
678 off += cbToCopy;
679 pu8CurrentHost += cbToCopy;
680
681 /* Go to the next descriptor if there's anything left. */
682 if (cbData)
683 {
684 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
685 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
686 ++iDescriptor;
687 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
688 }
689 }
690 return rc;
691}
692
693
694static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
695 uint32_t off, void const *pvData, uint32_t cbData)
696{
697 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
698 off, (void *)pvData, cbData,
699 VMSVGAGboTransferDirection_Write);
700}
701
702
703static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
704 uint32_t off, void *pvData, uint32_t cbData)
705{
706 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
707 off, pvData, cbData,
708 VMSVGAGboTransferDirection_Read);
709}
710
711
712static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
713{
714 int rc;
715
716 /* Just reread the data if pvHost has been allocated already. */
717 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
718 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
719
720 if (pGbo->pvHost)
721 {
722 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
723 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
724 }
725 else
726 rc = VERR_NO_MEMORY;
727
728 if (RT_SUCCESS(rc))
729 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
730 else
731 {
732 RTMemFree(pGbo->pvHost);
733 pGbo->pvHost = NULL;
734 }
735 return rc;
736}
737
738
739static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
740{
741 RT_NOREF(pSvgaR3State);
742 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
743 RTMemFree(pGbo->pvHost);
744 pGbo->pvHost = NULL;
745 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
746}
747
748
749static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
750{
751 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
752 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
753}
754
755
756static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
757{
758 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
759 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
760}
761
762
763
764/*
765 *
766 * Object Tables.
767 *
768 */
769
770static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
771 uint32_t idx, uint32_t cbEntry)
772{
773 RT_NOREF(pSvgaR3State);
774
775 /* The table must exist and the index must be within the table. */
776 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
777 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
778 RT_UNTRUSTED_VALIDATED_FENCE();
779 return VINF_SUCCESS;
780}
781
782
783static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
784 uint32_t idx, uint32_t cbEntry,
785 void *pvData, uint32_t cbData)
786{
787 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
788
789 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
790 if (RT_SUCCESS(rc))
791 {
792 uint32_t const off = idx * cbEntry;
793 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
794 }
795 return rc;
796}
797
798static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
799 uint32_t idx, uint32_t cbEntry,
800 void const *pvData, uint32_t cbData)
801{
802 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
803
804 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
805 if (RT_SUCCESS(rc))
806 {
807 uint32_t const off = idx * cbEntry;
808 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
809 }
810 return rc;
811}
812
813
814/*
815 *
816 * The guest's Memory OBjects (MOB).
817 *
818 */
819
820static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
821 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
822 bool fGCPhys64, PVMSVGAMOB pMob)
823{
824 RT_ZERO(*pMob);
825
826 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
827 SVGAOTableMobEntry entry;
828 entry.ptDepth = ptDepth;
829 entry.sizeInBytes = sizeInBytes;
830 entry.base = baseAddress;
831 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
832 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
833 if (RT_SUCCESS(rc))
834 {
835 /* Create the corresponding GBO. */
836 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
837 if (RT_SUCCESS(rc))
838 {
839 /* Add to the tree of known GBOs and the LRU list. */
840 pMob->Core.Key = mobid;
841 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
842 {
843 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
844 return VINF_SUCCESS;
845 }
846
847 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
848 }
849 }
850
851 return rc;
852}
853
854
855static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
856{
857 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
858 SVGAOTableMobEntry entry;
859 RT_ZERO(entry);
860 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
861 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
862
863 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
864 if (pMob)
865 {
866 RTListNodeRemove(&pMob->nodeLRU);
867 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
868 RTMemFree(pMob);
869 return VINF_SUCCESS;
870 }
871
872 return VERR_INVALID_PARAMETER;
873}
874
875
876static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
877{
878 if (mobid == SVGA_ID_INVALID)
879 return NULL;
880
881 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
882 if (pMob)
883 {
884 /* Move to the head of the LRU list. */
885 RTListNodeRemove(&pMob->nodeLRU);
886 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
887 }
888 else
889 ASSERT_GUEST_FAILED();
890
891 return pMob;
892}
893
894
895/** Create a host ring-3 pointer to the MOB data.
896 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
897 * @param pSvgaR3State R3 device state.
898 * @param pMob The MOB.
899 * @param cbValid How many bytes of the guest backing memory contain valid data.
900 * @return VBox status.
901 */
902/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
903int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
904{
905 AssertReturn(pMob, VERR_INVALID_PARAMETER);
906 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
907}
908
909
910void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
911{
912 if (pMob)
913 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
914}
915
916
917int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
918{
919 if (pMob)
920 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
921 return VERR_INVALID_PARAMETER;
922}
923
924
925int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
926{
927 if (pMob)
928 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
929 return VERR_INVALID_PARAMETER;
930}
931
932
933void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
934{
935 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
936 {
937 if (off <= pMob->Gbo.cbTotal)
938 return (uint8_t *)pMob->Gbo.pvHost + off;
939 }
940 return NULL;
941}
942
943
944int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
945{
946 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
947
948 SVGAOTableSurfaceEntry entrySurface;
949 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
950 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
951 if (RT_SUCCESS(rc))
952 {
953 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
954 if (pMob)
955 {
956 VMSVGA3D_MAPPED_SURFACE map;
957 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE, &map);
958 if (RT_SUCCESS(rc))
959 {
960 /* Copy MOB -> mapped surface. */
961 uint32_t offSrc = pBox->x * map.cbPixel
962 + pBox->y * entrySurface.size.width * map.cbPixel
963 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
964 uint8_t *pu8Dst = (uint8_t *)map.pvData;
965 for (uint32_t z = 0; z < pBox->d; ++z)
966 {
967 for (uint32_t y = 0; y < pBox->h; ++y)
968 {
969 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
970 if (RT_FAILURE(rc))
971 break;
972
973 pu8Dst += map.cbRowPitch;
974 offSrc += entrySurface.size.width * map.cbPixel;
975 }
976
977 pu8Dst += map.cbDepthPitch;
978 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
979 }
980
981 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
982 }
983 }
984 else
985 rc = VERR_INVALID_STATE;
986 }
987
988 return rc;
989}
990
991
992int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
993{
994 /* pPtSrc must be verified by the caller. */
995 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
996
997 SVGAOTableSurfaceEntry entrySurface;
998 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
999 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1000 if (RT_SUCCESS(rc))
1001 {
1002 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1003 if (pMob)
1004 {
1005 VMSVGA3D_MAPPED_SURFACE map;
1006 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE, &map);
1007 if (RT_SUCCESS(rc))
1008 {
1009 /* Copy MOB -> mapped surface. */
1010 uint32_t offSrc = pPtSrc->x * map.cbPixel
1011 + pPtSrc->y * entrySurface.size.width * map.cbPixel
1012 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1013 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1014 for (uint32_t z = 0; z < pBoxDst->d; ++z)
1015 {
1016 for (uint32_t y = 0; y < pBoxDst->h; ++y)
1017 {
1018 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1019 if (RT_FAILURE(rc))
1020 break;
1021
1022 pu8Dst += map.cbRowPitch;
1023 offSrc += entrySurface.size.width * map.cbPixel;
1024 }
1025
1026 pu8Dst += map.cbDepthPitch;
1027 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1028 }
1029
1030 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1031 }
1032 }
1033 else
1034 rc = VERR_INVALID_STATE;
1035 }
1036
1037 return rc;
1038}
1039#endif /* VBOX_WITH_VMSVGA3D */
1040
1041
1042/*
1043 * Screen objects.
1044 */
1045VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1046{
1047 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1048 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1049 && pSVGAState
1050 && pSVGAState->aScreens[idScreen].fDefined)
1051 {
1052 return &pSVGAState->aScreens[idScreen];
1053 }
1054 return NULL;
1055}
1056
1057void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1058{
1059#ifdef VBOX_WITH_VMSVGA3D
1060 if (pThis->svga.f3DEnabled)
1061 {
1062 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1063 {
1064 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1065 if (pScreen)
1066 vmsvga3dDestroyScreen(pThisCC, pScreen);
1067 }
1068 }
1069#else
1070 RT_NOREF(pThis, pThisCC);
1071#endif
1072}
1073
1074
1075/**
1076 * Copy a rectangle of pixels within guest VRAM.
1077 */
1078static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1079 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1080{
1081 if (!width || !height)
1082 return; /* Nothing to do, don't even bother. */
1083
1084 /*
1085 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1086 * corresponding to the current display mode.
1087 */
1088 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1089 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1090 uint8_t const *pSrc;
1091 uint8_t *pDst;
1092 unsigned const cbRectWidth = width * cbPixel;
1093 unsigned uMaxOffset;
1094
1095 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1096 if (uMaxOffset >= cbFrameBuffer)
1097 {
1098 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1099 return; /* Just don't listen to a bad guest. */
1100 }
1101
1102 pSrc = pDst = pThisCC->pbVRam;
1103 pSrc += srcY * cbScanline + srcX * cbPixel;
1104 pDst += dstY * cbScanline + dstX * cbPixel;
1105
1106 if (srcY >= dstY)
1107 {
1108 /* Source below destination, copy top to bottom. */
1109 for (; height > 0; height--)
1110 {
1111 memmove(pDst, pSrc, cbRectWidth);
1112 pSrc += cbScanline;
1113 pDst += cbScanline;
1114 }
1115 }
1116 else
1117 {
1118 /* Source above destination, copy bottom to top. */
1119 pSrc += cbScanline * (height - 1);
1120 pDst += cbScanline * (height - 1);
1121 for (; height > 0; height--)
1122 {
1123 memmove(pDst, pSrc, cbRectWidth);
1124 pSrc -= cbScanline;
1125 pDst -= cbScanline;
1126 }
1127 }
1128}
1129
1130
1131/**
1132 * Common worker for changing the pointer shape.
1133 *
1134 * @param pThisCC The VGA/VMSVGA state for ring-3.
1135 * @param pSVGAState The VMSVGA ring-3 instance data.
1136 * @param fAlpha Whether there is alpha or not.
1137 * @param xHot Hotspot x coordinate.
1138 * @param yHot Hotspot y coordinate.
1139 * @param cx Width.
1140 * @param cy Height.
1141 * @param pbData Heap copy of the cursor data. Consumed.
1142 * @param cbData The size of the data.
1143 */
1144static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1145 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1146{
1147 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1148#ifdef LOG_ENABLED
1149 if (LogIs2Enabled())
1150 {
1151 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1152 if (!fAlpha)
1153 {
1154 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1155 for (uint32_t y = 0; y < cy; y++)
1156 {
1157 Log2(("%3u:", y));
1158 uint8_t const *pbLine = &pbData[y * cbAndLine];
1159 for (uint32_t x = 0; x < cx; x += 8)
1160 {
1161 uint8_t b = pbLine[x / 8];
1162 char szByte[12];
1163 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1164 szByte[1] = b & 0x40 ? '*' : ' ';
1165 szByte[2] = b & 0x20 ? '*' : ' ';
1166 szByte[3] = b & 0x10 ? '*' : ' ';
1167 szByte[4] = b & 0x08 ? '*' : ' ';
1168 szByte[5] = b & 0x04 ? '*' : ' ';
1169 szByte[6] = b & 0x02 ? '*' : ' ';
1170 szByte[7] = b & 0x01 ? '*' : ' ';
1171 szByte[8] = '\0';
1172 Log2(("%s", szByte));
1173 }
1174 Log2(("\n"));
1175 }
1176 }
1177
1178 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1179 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1180 for (uint32_t y = 0; y < cy; y++)
1181 {
1182 Log2(("%3u:", y));
1183 uint32_t const *pu32Line = &pu32Xor[y * cx];
1184 for (uint32_t x = 0; x < cx; x++)
1185 Log2((" %08x", pu32Line[x]));
1186 Log2(("\n"));
1187 }
1188 }
1189#endif
1190
1191 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1192 AssertRC(rc);
1193
1194 if (pSVGAState->Cursor.fActive)
1195 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1196
1197 pSVGAState->Cursor.fActive = true;
1198 pSVGAState->Cursor.xHotspot = xHot;
1199 pSVGAState->Cursor.yHotspot = yHot;
1200 pSVGAState->Cursor.width = cx;
1201 pSVGAState->Cursor.height = cy;
1202 pSVGAState->Cursor.cbData = cbData;
1203 pSVGAState->Cursor.pData = pbData;
1204}
1205
1206
1207#ifdef VBOX_WITH_VMSVGA3D
1208
1209/*
1210 * SVGA_3D_CMD_* handlers.
1211 */
1212
1213
1214/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1215 *
1216 * @param pThisCC The VGA/VMSVGA state for the current context.
1217 * @param pCmd The VMSVGA command.
1218 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1219 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1220 */
1221static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1222 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1223{
1224 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1225 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1226 RT_UNTRUSTED_VALIDATED_FENCE();
1227
1228 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1229 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1230 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1231 */
1232 uint32_t cRemainingMipLevels = cMipLevelSizes;
1233 uint32_t cFaces = 0;
1234 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1235 {
1236 if (pCmd->face[i].numMipLevels == 0)
1237 break;
1238
1239 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1240 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1241
1242 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1243 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1244 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1245
1246 ++cFaces;
1247 }
1248 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1249 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1250
1251 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1252 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1253
1254 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1255 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1256 RT_UNTRUSTED_VALIDATED_FENCE();
1257
1258 /* Verify paMipLevelSizes */
1259 uint32_t cWidth = paMipLevelSizes[0].width;
1260 uint32_t cHeight = paMipLevelSizes[0].height;
1261 uint32_t cDepth = paMipLevelSizes[0].depth;
1262 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1263 {
1264 cWidth >>= 1;
1265 if (cWidth == 0) cWidth = 1;
1266 cHeight >>= 1;
1267 if (cHeight == 0) cHeight = 1;
1268 cDepth >>= 1;
1269 if (cDepth == 0) cDepth = 1;
1270 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1271 {
1272 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1273 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1274 && cHeight == paMipLevelSizes[iMipLevelSize].height
1275 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1276 }
1277 }
1278 RT_UNTRUSTED_VALIDATED_FENCE();
1279
1280 /* Create the surface. */
1281 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1282 pCmd->multisampleCount, pCmd->autogenFilter,
1283 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* fAllocMipLevels = */ true);
1284}
1285
1286
1287/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1288static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1289{
1290 DEBUG_BREAKPOINT_TEST();
1291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1292
1293 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1294
1295 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1296 /* Allocate a structure for the MOB. */
1297 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1298 AssertPtrReturnVoid(pMob);
1299
1300 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1301 if (RT_SUCCESS(rc))
1302 {
1303 return;
1304 }
1305
1306 AssertFailed();
1307
1308 RTMemFree(pMob);
1309}
1310
1311
1312/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1313static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1314{
1315 //DEBUG_BREAKPOINT_TEST();
1316 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1317
1318 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1319
1320 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1321 if (RT_SUCCESS(rc))
1322 {
1323 return;
1324 }
1325
1326 AssertFailed();
1327}
1328
1329
1330/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1331static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1332{
1333 //DEBUG_BREAKPOINT_TEST();
1334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1335
1336 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1337 SVGAOTableSurfaceEntry entry;
1338 RT_ZERO(entry);
1339 entry.format = pCmd->format;
1340 entry.surface1Flags = pCmd->surfaceFlags;
1341 entry.numMipLevels = pCmd->numMipLevels;
1342 entry.multisampleCount = pCmd->multisampleCount;
1343 entry.autogenFilter = pCmd->autogenFilter;
1344 entry.size = pCmd->size;
1345 entry.mobid = SVGA_ID_INVALID;
1346 // entry.arraySize = 0;
1347 // entry.mobPitch = 0;
1348 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1349 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1350 if (RT_SUCCESS(rc))
1351 {
1352 /* Create the host surface. */
1353 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1354 pCmd->multisampleCount, pCmd->autogenFilter,
1355 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1356 }
1357}
1358
1359
1360/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1361static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1362{
1363 //DEBUG_BREAKPOINT_TEST();
1364 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1365
1366 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1367 SVGAOTableSurfaceEntry entry;
1368 RT_ZERO(entry);
1369 entry.mobid = SVGA_ID_INVALID;
1370 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1371 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1372
1373 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1374}
1375
1376
1377/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1378static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1379{
1380 //DEBUG_BREAKPOINT_TEST();
1381 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1382
1383 /* Assign the mobid to the surface. */
1384 int rc = VINF_SUCCESS;
1385 if (pCmd->mobid != SVGA_ID_INVALID)
1386 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1387 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1388 if (RT_SUCCESS(rc))
1389 {
1390 SVGAOTableSurfaceEntry entry;
1391 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1392 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1393 if (RT_SUCCESS(rc))
1394 {
1395 entry.mobid = pCmd->mobid;
1396 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1397 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1398 if (RT_SUCCESS(rc))
1399 {
1400 /* */
1401 }
1402 }
1403 }
1404}
1405
1406
1407#ifdef DUMP_BITMAPS
1408static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1409{
1410 if (pMap->cbPixel != 4)
1411 return VERR_NOT_SUPPORTED;
1412
1413 int const w = pMap->box.w;
1414 int const h = pMap->box.h;
1415
1416 const int cbBitmap = w * h * 4;
1417
1418 FILE *f = fopen(pszFilename, "wb");
1419 if (!f)
1420 return VERR_FILE_NOT_FOUND;
1421
1422 {
1423 BMPFILEHDR fileHdr;
1424 RT_ZERO(fileHdr);
1425 fileHdr.uType = BMP_HDR_MAGIC;
1426 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1427 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1428
1429 BMPWIN3XINFOHDR coreHdr;
1430 RT_ZERO(coreHdr);
1431 coreHdr.cbSize = sizeof(coreHdr);
1432 coreHdr.uWidth = w;
1433 coreHdr.uHeight = -h;
1434 coreHdr.cPlanes = 1;
1435 coreHdr.cBits = 32;
1436 coreHdr.cbSizeImage = cbBitmap;
1437
1438 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1439 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1440 }
1441
1442 if (pMap->cbPixel == 4)
1443 {
1444 const uint8_t *s = (uint8_t *)pMap->pvData;
1445 for (int32_t y = 0; y < h; ++y)
1446 {
1447 fwrite(s, 1, w * pMap->cbPixel, f);
1448
1449 s += pMap->cbRowPitch;
1450 }
1451 }
1452
1453 fclose(f);
1454
1455 return VINF_SUCCESS;
1456}
1457
1458
1459void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1460{
1461 static int idxBitmap = 0;
1462 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1463 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1464 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1465 RTStrFree(pszFilename);
1466}
1467#endif /* DUMP_BITMAPS */
1468
1469
1470static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1471 PVMSVGAMOB pMob,
1472 SVGA3dSurfaceImageId const *pImage,
1473 SVGA3dBox const *pBox,
1474 SVGA3dTransferType enmTransfer)
1475{
1476 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1477
1478 VMSVGA3D_SURFACE_MAP enmMapType;
1479 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1480 enmMapType = pBox
1481 ? VMSVGA3D_SURFACE_MAP_WRITE
1482 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1483 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1484 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1485 else
1486 AssertFailedReturn(VERR_INVALID_PARAMETER);
1487
1488 VMSGA3D_BOX_DIMENSIONS dims;
1489 int rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1490 AssertRCReturn(rc, rc);
1491
1492 VMSVGA3D_MAPPED_SURFACE map;
1493 rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1494 if (RT_SUCCESS(rc))
1495 {
1496 /* Copy mapped surface <-> MOB. */
1497 uint8_t *pu8Map = (uint8_t *)map.pvData;
1498 uint32_t offMob = dims.offSubresource + dims.offBox;
1499 for (uint32_t z = 0; z < dims.cDepth; ++z)
1500 {
1501 for (uint32_t y = 0; y < dims.cyBlocks; ++y)
1502 {
1503 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1504 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1505 else
1506 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1507 if (RT_FAILURE(rc))
1508 break;
1509
1510 pu8Map += map.cbRowPitch;
1511 offMob += dims.cbPitch;
1512 }
1513 }
1514
1515 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1516
1517 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1518 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1519 }
1520
1521 return rc;
1522}
1523
1524
1525/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1526static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1527{
1528 //DEBUG_BREAKPOINT_TEST();
1529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1530
1531 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1532 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1533
1534/*
1535 SVGA3dSurfaceFormat format;
1536 SVGA3dSurface1Flags surface1Flags;
1537 uint32 numMipLevels;
1538 uint32 multisampleCount;
1539 SVGA3dTextureFilter autogenFilter;
1540 SVGA3dSize size;
1541 SVGAMobId mobid;
1542 uint32 arraySize;
1543 uint32 mobPitch;
1544 SVGA3dSurface2Flags surface2Flags;
1545 uint8 multisamplePattern;
1546 uint8 qualityLevel;
1547 uint16 bufferByteStride;
1548 float minLOD;
1549*/
1550
1551 /* "update a surface from its backing MOB." */
1552 SVGAOTableSurfaceEntry entrySurface;
1553 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1554 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1555 if (RT_SUCCESS(rc))
1556 {
1557 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1558 if (pMob)
1559 {
1560 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1561 AssertRC(rc);
1562 }
1563 }
1564}
1565
1566
1567/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1568static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1569{
1570 //DEBUG_BREAKPOINT_TEST();
1571 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1572
1573 LogFlowFunc(("sid=%u\n",
1574 pCmd->sid));
1575
1576 /* "update a surface from its backing MOB." */
1577 SVGAOTableSurfaceEntry entrySurface;
1578 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1579 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1580 if (RT_SUCCESS(rc))
1581 {
1582 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1583 if (pMob)
1584 {
1585 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1586 ? SVGA3D_MAX_SURFACE_FACES
1587 : RT_MAX(entrySurface.arraySize, 1);
1588 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1589 {
1590 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1591 {
1592 SVGA3dSurfaceImageId image;
1593 image.sid = pCmd->sid;
1594 image.face = iArray;
1595 image.mipmap = iMipmap;
1596
1597 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1598 AssertRCBreak(rc);
1599 }
1600 }
1601 }
1602 }
1603}
1604
1605
1606/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1607static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1608{
1609 //DEBUG_BREAKPOINT_TEST();
1610 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1611
1612 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1613 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1614
1615 /* Read a surface to its backing MOB. */
1616 SVGAOTableSurfaceEntry entrySurface;
1617 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1618 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1619 if (RT_SUCCESS(rc))
1620 {
1621 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1622 if (pMob)
1623 {
1624 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1625 AssertRC(rc);
1626 }
1627 }
1628}
1629
1630
1631/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1632static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1633{
1634 //DEBUG_BREAKPOINT_TEST();
1635 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1636
1637 LogFlowFunc(("sid=%u\n",
1638 pCmd->sid));
1639
1640 /* Read a surface to its backing MOB. */
1641 SVGAOTableSurfaceEntry entrySurface;
1642 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1643 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1644 if (RT_SUCCESS(rc))
1645 {
1646 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1647 if (pMob)
1648 {
1649 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1650 ? SVGA3D_MAX_SURFACE_FACES
1651 : RT_MAX(entrySurface.arraySize, 1);
1652 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1653 {
1654 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1655 {
1656 SVGA3dSurfaceImageId image;
1657 image.sid = pCmd->sid;
1658 image.face = iArray;
1659 image.mipmap = iMipmap;
1660
1661 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1662 AssertRCBreak(rc);
1663 }
1664 }
1665 }
1666 }
1667}
1668
1669
1670/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1671static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1672{
1673 //DEBUG_BREAKPOINT_TEST();
1674 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1675}
1676
1677
1678/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1679static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1680{
1681 //DEBUG_BREAKPOINT_TEST();
1682 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1683}
1684
1685
1686/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1687static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1688{
1689 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1690
1691 /*
1692 * Create a GBO for the table.
1693 */
1694 PVMSVGAGBO pGbo;
1695 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1696 {
1697 RT_UNTRUSTED_VALIDATED_FENCE();
1698 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1699 }
1700 else
1701 {
1702 ASSERT_GUEST_FAILED();
1703 pGbo = NULL;
1704 }
1705
1706 if (pGbo)
1707 {
1708 /* Recreate. */
1709 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1710 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1711 AssertRC(rc);
1712 }
1713}
1714
1715
1716/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1717static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1718{
1719 //DEBUG_BREAKPOINT_TEST();
1720 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1721
1722 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1723 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1724 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1725 RT_UNTRUSTED_VALIDATED_FENCE();
1726
1727 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1728 SVGAOTableScreenTargetEntry entry;
1729 RT_ZERO(entry);
1730 entry.image.sid = SVGA_ID_INVALID;
1731 // entry.image.face = 0;
1732 // entry.image.mipmap = 0;
1733 entry.width = pCmd->width;
1734 entry.height = pCmd->height;
1735 entry.xRoot = pCmd->xRoot;
1736 entry.yRoot = pCmd->yRoot;
1737 entry.flags = pCmd->flags;
1738 entry.dpi = pCmd->dpi;
1739
1740 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1741 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1742 if (RT_SUCCESS(rc))
1743 {
1744 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1745 /** @todo Generic screen object/target interface. */
1746 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1747 pScreen->fDefined = true;
1748 pScreen->fModified = true;
1749 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1750 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1751 pScreen->idScreen = pCmd->stid;
1752
1753 pScreen->xOrigin = pCmd->xRoot;
1754 pScreen->yOrigin = pCmd->yRoot;
1755 pScreen->cWidth = pCmd->width;
1756 pScreen->cHeight = pCmd->height;
1757 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1758 pScreen->cbPitch = pCmd->width * 4;
1759 pScreen->cBpp = 32;
1760
1761 if (RT_LIKELY(pThis->svga.f3DEnabled))
1762 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1763
1764 if (!pScreen->pHwScreen)
1765 {
1766 /* System memory buffer. */
1767 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1768 }
1769
1770 pThis->svga.fGFBRegisters = false;
1771 vmsvgaR3ChangeMode(pThis, pThisCC);
1772 }
1773}
1774
1775
1776/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1777static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1778{
1779 //DEBUG_BREAKPOINT_TEST();
1780 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1781
1782 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1783 RT_UNTRUSTED_VALIDATED_FENCE();
1784
1785 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1786 SVGAOTableScreenTargetEntry entry;
1787 RT_ZERO(entry);
1788 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1789 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1790 if (RT_SUCCESS(rc))
1791 {
1792 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1793 /** @todo Generic screen object/target interface. */
1794 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1795 pScreen->fModified = true;
1796 pScreen->fDefined = false;
1797 pScreen->idScreen = pCmd->stid;
1798
1799 if (RT_LIKELY(pThis->svga.f3DEnabled))
1800 vmsvga3dDestroyScreen(pThisCC, pScreen);
1801
1802 vmsvgaR3ChangeMode(pThis, pThisCC);
1803
1804 RTMemFree(pScreen->pvScreenBitmap);
1805 pScreen->pvScreenBitmap = NULL;
1806 }
1807}
1808
1809
1810/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1811static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1812{
1813 //DEBUG_BREAKPOINT_TEST();
1814 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1815
1816 /* "Binding a surface to a Screen Target the same as flipping" */
1817
1818 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1819 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1820 RT_UNTRUSTED_VALIDATED_FENCE();
1821
1822 /* Assign the surface to the screen target. */
1823 int rc = VINF_SUCCESS;
1824 if (pCmd->image.sid != SVGA_ID_INVALID)
1825 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1826 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1827 if (RT_SUCCESS(rc))
1828 {
1829 SVGAOTableScreenTargetEntry entry;
1830 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1831 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1832 if (RT_SUCCESS(rc))
1833 {
1834 entry.image = pCmd->image;
1835 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1836 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1837 if (RT_SUCCESS(rc))
1838 {
1839 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1840 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1841 AssertRC(rc);
1842 }
1843 }
1844 }
1845}
1846
1847
1848/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1849static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1850{
1851 //DEBUG_BREAKPOINT_TEST();
1852 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1853
1854 /* Update the screen target from its backing surface. */
1855 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1856 RT_UNTRUSTED_VALIDATED_FENCE();
1857
1858 /* Get the screen target info. */
1859 SVGAOTableScreenTargetEntry entryScreenTarget;
1860 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1861 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1862 if (RT_SUCCESS(rc))
1863 {
1864 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1865 RT_UNTRUSTED_VALIDATED_FENCE();
1866
1867 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1868 {
1869 SVGAOTableSurfaceEntry entrySurface;
1870 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1871 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1872 if (RT_SUCCESS(rc))
1873 {
1874 /* Copy entrySurface.mobid content to the screen target. */
1875 if (entrySurface.mobid != SVGA_ID_INVALID)
1876 {
1877 RT_UNTRUSTED_VALIDATED_FENCE();
1878 SVGA3dRect targetRect = pCmd->rect;
1879
1880 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1881 if (pScreen->pHwScreen)
1882 {
1883 /* Copy the screen target surface to the backend's screen. */
1884 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1885 }
1886 else if (pScreen->pvScreenBitmap)
1887 {
1888 /* Copy the screen target surface to the memory buffer. */
1889 VMSVGA3D_MAPPED_SURFACE map;
1890 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1891 if (RT_SUCCESS(rc))
1892 {
1893 uint8_t const *pu8Src = (uint8_t *)map.pvData
1894 + targetRect.x * map.cbPixel
1895 + targetRect.y * map.cbRowPitch;
1896 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1897 + targetRect.x * map.cbPixel
1898 + targetRect.y * map.box.w * map.cbPixel;
1899 for (uint32_t y = 0; y < targetRect.h; ++y)
1900 {
1901 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1902
1903 pu8Src += map.cbRowPitch;
1904 pu8Dst += map.box.w * map.cbPixel;
1905 }
1906
1907 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1908
1909 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1910 }
1911 else
1912 AssertFailed();
1913 }
1914 }
1915 }
1916 }
1917 }
1918}
1919
1920
1921/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1922static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1923{
1924 //DEBUG_BREAKPOINT_TEST();
1925 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1926
1927 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1928 SVGAOTableSurfaceEntry entry;
1929 RT_ZERO(entry);
1930 entry.format = pCmd->format;
1931 entry.surface1Flags = pCmd->surfaceFlags;
1932 entry.numMipLevels = pCmd->numMipLevels;
1933 entry.multisampleCount = pCmd->multisampleCount;
1934 entry.autogenFilter = pCmd->autogenFilter;
1935 entry.size = pCmd->size;
1936 entry.mobid = SVGA_ID_INVALID;
1937 entry.arraySize = pCmd->arraySize;
1938 // entry.mobPitch = 0;
1939 // ...
1940Assert( pCmd->arraySize == 0
1941 || pCmd->arraySize == 1
1942 || (pCmd->arraySize == 6 && (pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP)));
1943 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1944 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1945 if (RT_SUCCESS(rc))
1946 {
1947 /* Create the host surface. */
1948 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1949 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1950 pCmd->multisampleCount, pCmd->autogenFilter,
1951 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1952 }
1953}
1954
1955
1956/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1957static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1958{
1959 //DEBUG_BREAKPOINT_TEST();
1960 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1961
1962 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1963
1964 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1965 /* Allocate a structure for the MOB. */
1966 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1967 AssertPtrReturnVoid(pMob);
1968
1969 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1970 if (RT_SUCCESS(rc))
1971 {
1972 return;
1973 }
1974
1975 RTMemFree(pMob);
1976}
1977
1978
1979/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1980static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1981{
1982#ifdef VMSVGA3D_DX
1983 //DEBUG_BREAKPOINT_TEST();
1984 RT_NOREF(cbCmd);
1985
1986 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1987
1988 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1989 SVGAOTableDXContextEntry entry;
1990 RT_ZERO(entry);
1991 entry.cid = pCmd->cid;
1992 entry.mobid = SVGA_ID_INVALID;
1993 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1994 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1995 if (RT_SUCCESS(rc))
1996 {
1997 /* Create the host context. */
1998 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1999 }
2000
2001 return rc;
2002#else
2003 RT_NOREF(pThisCC, pCmd, cbCmd);
2004 return VERR_NOT_SUPPORTED;
2005#endif
2006}
2007
2008
2009/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2010static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2011{
2012#ifdef VMSVGA3D_DX
2013 //DEBUG_BREAKPOINT_TEST();
2014 RT_NOREF(cbCmd);
2015
2016 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2017
2018 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2019 SVGAOTableDXContextEntry entry;
2020 RT_ZERO(entry);
2021 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2022 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2023
2024 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2025#else
2026 RT_NOREF(pThisCC, pCmd, cbCmd);
2027 return VERR_NOT_SUPPORTED;
2028#endif
2029}
2030
2031
2032/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2033static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2034{
2035#ifdef VMSVGA3D_DX
2036 //DEBUG_BREAKPOINT_TEST();
2037 RT_NOREF(cbCmd);
2038
2039 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2040
2041 /* Assign a mobid to a cid. */
2042 int rc = VINF_SUCCESS;
2043 if (pCmd->mobid != SVGA_ID_INVALID)
2044 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2045 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2046 if (RT_SUCCESS(rc))
2047 {
2048 SVGAOTableDXContextEntry entry;
2049 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2050 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2051 if (RT_SUCCESS(rc))
2052 {
2053 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2054 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2055 {
2056 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2057 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2058 if (pSvgaDXContext)
2059 {
2060 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2061 if (RT_SUCCESS(rc))
2062 {
2063 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2064 if (pMob)
2065 {
2066 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2067 }
2068 }
2069
2070 RTMemFree(pSvgaDXContext);
2071 pSvgaDXContext = NULL;
2072 }
2073 }
2074
2075 if (pCmd->mobid != SVGA_ID_INVALID)
2076 {
2077 /* Bind a new context. Copy existing data from the guest backing memory. */
2078 if (pCmd->validContents)
2079 {
2080 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2081 if (pMob)
2082 {
2083 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2084 if (pSvgaDXContext)
2085 {
2086 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2087 if (RT_FAILURE(rc))
2088 {
2089 RTMemFree(pSvgaDXContext);
2090 pSvgaDXContext = NULL;
2091 }
2092 }
2093 }
2094 }
2095
2096 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2097
2098 RTMemFree(pSvgaDXContext);
2099 }
2100
2101 /* Update the object table. */
2102 entry.mobid = pCmd->mobid;
2103 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2104 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2105 }
2106 }
2107
2108 return rc;
2109#else
2110 RT_NOREF(pThisCC, pCmd, cbCmd);
2111 return VERR_NOT_SUPPORTED;
2112#endif
2113}
2114
2115
2116/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2117static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2118{
2119#ifdef VMSVGA3D_DX
2120 //DEBUG_BREAKPOINT_TEST();
2121 RT_NOREF(cbCmd);
2122
2123 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2124
2125 /* "Request that the device flush the contents back into guest memory." */
2126 SVGAOTableDXContextEntry entry;
2127 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2128 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2129 if (RT_SUCCESS(rc))
2130 {
2131 if (entry.mobid != SVGA_ID_INVALID)
2132 {
2133 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2134 if (pMob)
2135 {
2136 /* Get the content. */
2137 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2138 if (pSvgaDXContext)
2139 {
2140 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2141 if (RT_SUCCESS(rc))
2142 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2143
2144 RTMemFree(pSvgaDXContext);
2145 }
2146 else
2147 rc = VERR_NO_MEMORY;
2148 }
2149 }
2150 }
2151
2152 return rc;
2153#else
2154 RT_NOREF(pThisCC, pCmd, cbCmd);
2155 return VERR_NOT_SUPPORTED;
2156#endif
2157}
2158
2159
2160/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2161static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2162{
2163#ifdef VMSVGA3D_DX
2164 DEBUG_BREAKPOINT_TEST();
2165 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2166 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2167 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2168#else
2169 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2170 return VERR_NOT_SUPPORTED;
2171#endif
2172}
2173
2174
2175/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2176static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2177{
2178#ifdef VMSVGA3D_DX
2179 //DEBUG_BREAKPOINT_TEST();
2180 RT_NOREF(cbCmd);
2181 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2182#else
2183 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2184 return VERR_NOT_SUPPORTED;
2185#endif
2186}
2187
2188
2189/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2190static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2191{
2192#ifdef VMSVGA3D_DX
2193 //DEBUG_BREAKPOINT_TEST();
2194 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2195 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2196 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2197#else
2198 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2199 return VERR_NOT_SUPPORTED;
2200#endif
2201}
2202
2203
2204/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2205static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2206{
2207#ifdef VMSVGA3D_DX
2208 //DEBUG_BREAKPOINT_TEST();
2209 RT_NOREF(cbCmd);
2210 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2211#else
2212 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2213 return VERR_NOT_SUPPORTED;
2214#endif
2215}
2216
2217
2218/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2219static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2220{
2221#ifdef VMSVGA3D_DX
2222 //DEBUG_BREAKPOINT_TEST();
2223 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2224 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2225 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2226#else
2227 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2228 return VERR_NOT_SUPPORTED;
2229#endif
2230}
2231
2232
2233/* SVGA_3D_CMD_DX_DRAW 1152 */
2234static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2235{
2236#ifdef VMSVGA3D_DX
2237 //DEBUG_BREAKPOINT_TEST();
2238 RT_NOREF(cbCmd);
2239 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2240#else
2241 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2242 return VERR_NOT_SUPPORTED;
2243#endif
2244}
2245
2246
2247/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2248static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2249{
2250#ifdef VMSVGA3D_DX
2251 //DEBUG_BREAKPOINT_TEST();
2252 RT_NOREF(cbCmd);
2253 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2254#else
2255 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2256 return VERR_NOT_SUPPORTED;
2257#endif
2258}
2259
2260
2261/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2262static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2263{
2264#ifdef VMSVGA3D_DX
2265 //DEBUG_BREAKPOINT_TEST();
2266 RT_NOREF(cbCmd);
2267 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2268#else
2269 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2270 return VERR_NOT_SUPPORTED;
2271#endif
2272}
2273
2274
2275/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2276static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2277{
2278#ifdef VMSVGA3D_DX
2279 //DEBUG_BREAKPOINT_TEST();
2280 RT_NOREF(cbCmd);
2281 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2282#else
2283 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2284 return VERR_NOT_SUPPORTED;
2285#endif
2286}
2287
2288
2289/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2290static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2291{
2292#ifdef VMSVGA3D_DX
2293 DEBUG_BREAKPOINT_TEST();
2294 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2295 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2296 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2297#else
2298 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2299 return VERR_NOT_SUPPORTED;
2300#endif
2301}
2302
2303
2304/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2305static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2306{
2307#ifdef VMSVGA3D_DX
2308 //DEBUG_BREAKPOINT_TEST();
2309 RT_NOREF(cbCmd);
2310 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2311#else
2312 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2313 return VERR_NOT_SUPPORTED;
2314#endif
2315}
2316
2317
2318/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2319static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2320{
2321#ifdef VMSVGA3D_DX
2322 //DEBUG_BREAKPOINT_TEST();
2323 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2324 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2325 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2326#else
2327 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2328 return VERR_NOT_SUPPORTED;
2329#endif
2330}
2331
2332
2333/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2334static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2335{
2336#ifdef VMSVGA3D_DX
2337 //DEBUG_BREAKPOINT_TEST();
2338 RT_NOREF(cbCmd);
2339 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2340#else
2341 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2342 return VERR_NOT_SUPPORTED;
2343#endif
2344}
2345
2346
2347/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2348static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2349{
2350#ifdef VMSVGA3D_DX
2351 //DEBUG_BREAKPOINT_TEST();
2352 RT_NOREF(cbCmd);
2353 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2354#else
2355 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2356 return VERR_NOT_SUPPORTED;
2357#endif
2358}
2359
2360
2361/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2362static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2363{
2364#ifdef VMSVGA3D_DX
2365 //DEBUG_BREAKPOINT_TEST();
2366 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2367 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2368 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2369#else
2370 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2371 return VERR_NOT_SUPPORTED;
2372#endif
2373}
2374
2375
2376/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2377static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2378{
2379#ifdef VMSVGA3D_DX
2380 //DEBUG_BREAKPOINT_TEST();
2381 RT_NOREF(cbCmd);
2382 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2383#else
2384 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2385 return VERR_NOT_SUPPORTED;
2386#endif
2387}
2388
2389
2390/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2391static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2392{
2393#ifdef VMSVGA3D_DX
2394 //DEBUG_BREAKPOINT_TEST();
2395 RT_NOREF(cbCmd);
2396 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2397#else
2398 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2399 return VERR_NOT_SUPPORTED;
2400#endif
2401}
2402
2403
2404/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2405static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2406{
2407#ifdef VMSVGA3D_DX
2408 //DEBUG_BREAKPOINT_TEST();
2409 RT_NOREF(cbCmd);
2410 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2411#else
2412 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2413 return VERR_NOT_SUPPORTED;
2414#endif
2415}
2416
2417
2418/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2419static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2420{
2421#ifdef VMSVGA3D_DX
2422 DEBUG_BREAKPOINT_TEST();
2423 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2424 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2425 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2426#else
2427 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2428 return VERR_NOT_SUPPORTED;
2429#endif
2430}
2431
2432
2433/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2434static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2435{
2436#ifdef VMSVGA3D_DX
2437 DEBUG_BREAKPOINT_TEST();
2438 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2439 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2440 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2441#else
2442 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2443 return VERR_NOT_SUPPORTED;
2444#endif
2445}
2446
2447
2448/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2449static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2450{
2451#ifdef VMSVGA3D_DX
2452 DEBUG_BREAKPOINT_TEST();
2453 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2454 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2455 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2456#else
2457 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2458 return VERR_NOT_SUPPORTED;
2459#endif
2460}
2461
2462
2463/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2464static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2465{
2466#ifdef VMSVGA3D_DX
2467 DEBUG_BREAKPOINT_TEST();
2468 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2469 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2470 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2471#else
2472 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2473 return VERR_NOT_SUPPORTED;
2474#endif
2475}
2476
2477
2478/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2479static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2480{
2481#ifdef VMSVGA3D_DX
2482 DEBUG_BREAKPOINT_TEST();
2483 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2484 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2485 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2486#else
2487 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2488 return VERR_NOT_SUPPORTED;
2489#endif
2490}
2491
2492
2493/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2494static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2495{
2496#ifdef VMSVGA3D_DX
2497 DEBUG_BREAKPOINT_TEST();
2498 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2499 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2500 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2501#else
2502 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2503 return VERR_NOT_SUPPORTED;
2504#endif
2505}
2506
2507
2508/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2509static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2510{
2511#ifdef VMSVGA3D_DX
2512 DEBUG_BREAKPOINT_TEST();
2513 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2514 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2515 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2516#else
2517 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2518 return VERR_NOT_SUPPORTED;
2519#endif
2520}
2521
2522
2523/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2524static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2525{
2526#ifdef VMSVGA3D_DX
2527 DEBUG_BREAKPOINT_TEST();
2528 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2529 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2530 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2531#else
2532 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2533 return VERR_NOT_SUPPORTED;
2534#endif
2535}
2536
2537
2538/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2539static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2540{
2541#ifdef VMSVGA3D_DX
2542 //DEBUG_BREAKPOINT_TEST();
2543 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2544 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2545 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2546#else
2547 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2548 return VERR_NOT_SUPPORTED;
2549#endif
2550}
2551
2552
2553/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2554static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2555{
2556#ifdef VMSVGA3D_DX
2557 //DEBUG_BREAKPOINT_TEST();
2558 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2559 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2560 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2561#else
2562 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2563 return VERR_NOT_SUPPORTED;
2564#endif
2565}
2566
2567
2568/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2569static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2570{
2571#ifdef VMSVGA3D_DX
2572 //DEBUG_BREAKPOINT_TEST();
2573 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2574 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2575 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2576#else
2577 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2578 return VERR_NOT_SUPPORTED;
2579#endif
2580}
2581
2582
2583/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2584static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2585{
2586#ifdef VMSVGA3D_DX
2587 //DEBUG_BREAKPOINT_TEST();
2588 RT_NOREF(cbCmd);
2589 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2590#else
2591 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2592 return VERR_NOT_SUPPORTED;
2593#endif
2594}
2595
2596
2597/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2598static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2599{
2600#ifdef VMSVGA3D_DX
2601 //DEBUG_BREAKPOINT_TEST();
2602 RT_NOREF(cbCmd);
2603 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2604#else
2605 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2606 return VERR_NOT_SUPPORTED;
2607#endif
2608}
2609
2610
2611/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2612static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2613{
2614#ifdef VMSVGA3D_DX
2615 //DEBUG_BREAKPOINT_TEST();
2616 RT_NOREF(cbCmd);
2617 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2618#else
2619 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2620 return VERR_NOT_SUPPORTED;
2621#endif
2622}
2623
2624
2625/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2626static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2627{
2628#ifdef VMSVGA3D_DX
2629 DEBUG_BREAKPOINT_TEST();
2630 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2631 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2632 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2633#else
2634 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2635 return VERR_NOT_SUPPORTED;
2636#endif
2637}
2638
2639
2640/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2641static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2642{
2643#ifdef VMSVGA3D_DX
2644 DEBUG_BREAKPOINT_TEST();
2645 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2646 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2647 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2648#else
2649 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2650 return VERR_NOT_SUPPORTED;
2651#endif
2652}
2653
2654
2655/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2656static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2657{
2658#ifdef VMSVGA3D_DX
2659 //DEBUG_BREAKPOINT_TEST();
2660 RT_NOREF(cbCmd);
2661 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2662#else
2663 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2664 return VERR_NOT_SUPPORTED;
2665#endif
2666}
2667
2668
2669/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2670static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2671{
2672#ifdef VMSVGA3D_DX
2673 //DEBUG_BREAKPOINT_TEST();
2674 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2675 RT_NOREF(cbCmd);
2676
2677 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2678 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2679
2680 /* "Inform the device that the guest-contents have been updated." */
2681 SVGAOTableSurfaceEntry entrySurface;
2682 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2683 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2684 if (RT_SUCCESS(rc))
2685 {
2686 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2687 if (pMob)
2688 {
2689 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2690 ? SVGA3D_MAX_SURFACE_FACES
2691 : RT_MAX(entrySurface.arraySize, 1);
2692 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2693 /* pCmd->box will be verified by the mapping function. */
2694 RT_UNTRUSTED_VALIDATED_FENCE();
2695
2696 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2697 SVGA3dSurfaceImageId image;
2698 image.sid = pCmd->sid;
2699 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2700
2701 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2702 AssertRC(rc);
2703 }
2704 }
2705
2706 return rc;
2707#else
2708 RT_NOREF(pThisCC, pCmd, cbCmd);
2709 return VERR_NOT_SUPPORTED;
2710#endif
2711}
2712
2713
2714/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2715static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2716{
2717#ifdef VMSVGA3D_DX
2718 //DEBUG_BREAKPOINT_TEST();
2719 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2720 RT_NOREF(cbCmd);
2721
2722 LogFlowFunc(("sid=%u, subResource=%u\n",
2723 pCmd->sid, pCmd->subResource));
2724
2725 /* "Request the device to flush the dirty contents into the guest." */
2726 SVGAOTableSurfaceEntry entrySurface;
2727 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2728 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2729 if (RT_SUCCESS(rc))
2730 {
2731 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2732 if (pMob)
2733 {
2734 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2735 ? SVGA3D_MAX_SURFACE_FACES
2736 : RT_MAX(entrySurface.arraySize, 1);
2737 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2738 RT_UNTRUSTED_VALIDATED_FENCE();
2739
2740 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2741 SVGA3dSurfaceImageId image;
2742 image.sid = pCmd->sid;
2743 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2744
2745 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2746 AssertRC(rc);
2747 }
2748 }
2749
2750 return rc;
2751#else
2752 RT_NOREF(pThisCC, pCmd, cbCmd);
2753 return VERR_NOT_SUPPORTED;
2754#endif
2755}
2756
2757
2758/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2759static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2760{
2761#ifdef VMSVGA3D_DX
2762 DEBUG_BREAKPOINT_TEST();
2763 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2764 RT_NOREF(cbCmd);
2765
2766 LogFlowFunc(("sid=%u, subResource=%u\n",
2767 pCmd->sid, pCmd->subResource));
2768
2769 /* "Notify the device that the contents can be lost." */
2770 SVGAOTableSurfaceEntry entrySurface;
2771 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2772 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2773 if (RT_SUCCESS(rc))
2774 {
2775 uint32_t iFace;
2776 uint32_t iMipmap;
2777 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2778 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2779 }
2780
2781 return rc;
2782#else
2783 RT_NOREF(pThisCC, pCmd, cbCmd);
2784 return VERR_NOT_SUPPORTED;
2785#endif
2786}
2787
2788
2789/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2790static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2791{
2792#ifdef VMSVGA3D_DX
2793 //DEBUG_BREAKPOINT_TEST();
2794 RT_NOREF(cbCmd);
2795 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2796#else
2797 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2798 return VERR_NOT_SUPPORTED;
2799#endif
2800}
2801
2802
2803/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2804static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2805{
2806#ifdef VMSVGA3D_DX
2807 //DEBUG_BREAKPOINT_TEST();
2808 RT_NOREF(cbCmd);
2809 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2810#else
2811 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2812 return VERR_NOT_SUPPORTED;
2813#endif
2814}
2815
2816
2817/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2818static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2819{
2820#ifdef VMSVGA3D_DX
2821 //DEBUG_BREAKPOINT_TEST();
2822 RT_NOREF(cbCmd);
2823 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2824#else
2825 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2826 return VERR_NOT_SUPPORTED;
2827#endif
2828}
2829
2830
2831/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2832static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2833{
2834#ifdef VMSVGA3D_DX
2835 //DEBUG_BREAKPOINT_TEST();
2836 RT_NOREF(cbCmd);
2837 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2838#else
2839 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2840 return VERR_NOT_SUPPORTED;
2841#endif
2842}
2843
2844
2845/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2846static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2847{
2848#ifdef VMSVGA3D_DX
2849 //DEBUG_BREAKPOINT_TEST();
2850 RT_NOREF(cbCmd);
2851 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2852 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2853 cmd.sid = pCmd->sid;
2854 cmd.format = pCmd->format;
2855 cmd.resourceDimension = pCmd->resourceDimension;
2856 cmd.mipSlice = pCmd->mipSlice;
2857 cmd.firstArraySlice = pCmd->firstArraySlice;
2858 cmd.arraySize = pCmd->arraySize;
2859 cmd.flags = 0;
2860 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2861#else
2862 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2863 return VERR_NOT_SUPPORTED;
2864#endif
2865}
2866
2867
2868/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2869static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2870{
2871#ifdef VMSVGA3D_DX
2872 //DEBUG_BREAKPOINT_TEST();
2873 RT_NOREF(cbCmd);
2874 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2875#else
2876 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2877 return VERR_NOT_SUPPORTED;
2878#endif
2879}
2880
2881
2882/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2883static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2884{
2885#ifdef VMSVGA3D_DX
2886 //DEBUG_BREAKPOINT_TEST();
2887 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2888 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2889 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2890#else
2891 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2892 return VERR_NOT_SUPPORTED;
2893#endif
2894}
2895
2896
2897/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2898static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2899{
2900#ifdef VMSVGA3D_DX
2901 DEBUG_BREAKPOINT_TEST();
2902 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2903 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2904 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2905#else
2906 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2907 return VERR_NOT_SUPPORTED;
2908#endif
2909}
2910
2911
2912/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2913static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2914{
2915#ifdef VMSVGA3D_DX
2916 //DEBUG_BREAKPOINT_TEST();
2917 RT_NOREF(cbCmd);
2918 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2919#else
2920 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2921 return VERR_NOT_SUPPORTED;
2922#endif
2923}
2924
2925
2926/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2927static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2928{
2929#ifdef VMSVGA3D_DX
2930 DEBUG_BREAKPOINT_TEST();
2931 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2932 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2933 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2934#else
2935 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2936 return VERR_NOT_SUPPORTED;
2937#endif
2938}
2939
2940
2941/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2942static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2943{
2944#ifdef VMSVGA3D_DX
2945 //DEBUG_BREAKPOINT_TEST();
2946 RT_NOREF(cbCmd);
2947 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2948#else
2949 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2950 return VERR_NOT_SUPPORTED;
2951#endif
2952}
2953
2954
2955/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2956static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2957{
2958#ifdef VMSVGA3D_DX
2959 DEBUG_BREAKPOINT_TEST();
2960 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2961 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2962 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2963#else
2964 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2965 return VERR_NOT_SUPPORTED;
2966#endif
2967}
2968
2969
2970/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2971static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2972{
2973#ifdef VMSVGA3D_DX
2974 //DEBUG_BREAKPOINT_TEST();
2975 RT_NOREF(cbCmd);
2976 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2977#else
2978 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2979 return VERR_NOT_SUPPORTED;
2980#endif
2981}
2982
2983
2984/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2985static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2986{
2987#ifdef VMSVGA3D_DX
2988 DEBUG_BREAKPOINT_TEST();
2989 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2990 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2991 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2992#else
2993 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2994 return VERR_NOT_SUPPORTED;
2995#endif
2996}
2997
2998
2999/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3000static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3001{
3002#ifdef VMSVGA3D_DX
3003 //DEBUG_BREAKPOINT_TEST();
3004 RT_NOREF(cbCmd);
3005 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3006#else
3007 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3008 return VERR_NOT_SUPPORTED;
3009#endif
3010}
3011
3012
3013/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3014static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3015{
3016#ifdef VMSVGA3D_DX
3017 DEBUG_BREAKPOINT_TEST();
3018 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3019 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3020 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
3021#else
3022 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3023 return VERR_NOT_SUPPORTED;
3024#endif
3025}
3026
3027
3028/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3029static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3030{
3031#ifdef VMSVGA3D_DX
3032 //DEBUG_BREAKPOINT_TEST();
3033 RT_NOREF(cbCmd);
3034 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3035#else
3036 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3037 return VERR_NOT_SUPPORTED;
3038#endif
3039}
3040
3041
3042/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3043static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3044{
3045#ifdef VMSVGA3D_DX
3046 //DEBUG_BREAKPOINT_TEST();
3047 RT_NOREF(cbCmd);
3048 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3049#else
3050 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3051 return VERR_NOT_SUPPORTED;
3052#endif
3053}
3054
3055
3056/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3057static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3058{
3059#ifdef VMSVGA3D_DX
3060 //DEBUG_BREAKPOINT_TEST();
3061 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3062 RT_NOREF(idDXContext, cbCmd);
3063 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3064 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3065 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3066#else
3067 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3068 return VERR_NOT_SUPPORTED;
3069#endif
3070}
3071
3072
3073/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3074static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3075{
3076#ifdef VMSVGA3D_DX
3077 //DEBUG_BREAKPOINT_TEST();
3078 RT_NOREF(cbCmd);
3079 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3080#else
3081 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3082 return VERR_NOT_SUPPORTED;
3083#endif
3084}
3085
3086
3087/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3088static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3089{
3090#ifdef VMSVGA3D_DX
3091 DEBUG_BREAKPOINT_TEST();
3092 RT_NOREF(cbCmd);
3093 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3094#else
3095 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3096 return VERR_NOT_SUPPORTED;
3097#endif
3098}
3099
3100
3101/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3102static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3103{
3104#ifdef VMSVGA3D_DX
3105 //DEBUG_BREAKPOINT_TEST();
3106 RT_NOREF(cbCmd);
3107 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3108#else
3109 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3110 return VERR_NOT_SUPPORTED;
3111#endif
3112}
3113
3114
3115/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3116static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3117{
3118#ifdef VMSVGA3D_DX
3119 //DEBUG_BREAKPOINT_TEST();
3120 RT_NOREF(cbCmd);
3121 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3122 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3123 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3124 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3125#else
3126 RT_NOREF(pThisCC, pCmd, cbCmd);
3127 return VERR_NOT_SUPPORTED;
3128#endif
3129}
3130
3131
3132/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3133static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3134{
3135#ifdef VMSVGA3D_DX
3136 //DEBUG_BREAKPOINT_TEST();
3137 RT_NOREF(idDXContext, cbCmd);
3138 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3139#else
3140 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3141 return VERR_NOT_SUPPORTED;
3142#endif
3143}
3144
3145
3146/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3147static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3148{
3149#ifdef VMSVGA3D_DX
3150 DEBUG_BREAKPOINT_TEST();
3151 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3152 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3153 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
3154#else
3155 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3156 return VERR_NOT_SUPPORTED;
3157#endif
3158}
3159
3160
3161/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3162static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3163{
3164#ifdef VMSVGA3D_DX
3165 //DEBUG_BREAKPOINT_TEST();
3166 RT_NOREF(cbCmd);
3167
3168 /* Plan:
3169 * - map the buffer;
3170 * - map the surface;
3171 * - copy from buffer map to the surface map.
3172 */
3173
3174 int rc;
3175
3176 SVGA3dSurfaceImageId imageBuffer;
3177 imageBuffer.sid = pCmd->srcSid;
3178 imageBuffer.face = 0;
3179 imageBuffer.mipmap = 0;
3180
3181 SVGA3dSurfaceImageId imageSurface;
3182 imageSurface.sid = pCmd->destSid;
3183 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3184 AssertRCReturn(rc, rc);
3185
3186 /*
3187 * Map the buffer.
3188 */
3189 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3190 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3191 if (RT_SUCCESS(rc))
3192 {
3193 /*
3194 * Map the surface.
3195 */
3196 VMSVGA3D_MAPPED_SURFACE mapSurface;
3197 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3198 if (RT_SUCCESS(rc))
3199 {
3200 /*
3201 * Copy the mapped buffer to the surface.
3202 */
3203 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3204 uint32_t const cbBuffer = mapBuffer.box.w * mapBuffer.cbPixel;
3205
3206 if (pCmd->srcOffset <= cbBuffer)
3207 {
3208 RT_UNTRUSTED_VALIDATED_FENCE();
3209 uint8_t const *pu8BufferBegin = pu8Buffer;
3210 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3211
3212 pu8Buffer += pCmd->srcOffset;
3213
3214 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3215
3216 uint32_t const cbWidth = mapSurface.box.w * mapSurface.cbPixel;
3217 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3218 {
3219 uint8_t const *pu8BufferRow = pu8Buffer;
3220 uint8_t *pu8SurfaceRow = pu8Surface;
3221 for (uint32_t y = 0; y < mapSurface.box.h; ++y)
3222 {
3223 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3224 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3225 && (uintptr_t)(pu8BufferRow + cbWidth) > (uintptr_t)pu8BufferBegin
3226 && (uintptr_t)(pu8BufferRow + cbWidth) <= (uintptr_t)pu8BufferEnd,
3227 rc = VERR_INVALID_PARAMETER);
3228
3229 memcpy(pu8SurfaceRow, pu8BufferRow, cbWidth);
3230
3231 pu8SurfaceRow += mapSurface.cbRowPitch;
3232 pu8BufferRow += pCmd->srcPitch;
3233 }
3234
3235 pu8Buffer += pCmd->srcSlicePitch;
3236 pu8Surface += mapSurface.cbDepthPitch;
3237 }
3238 }
3239 else
3240 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3241
3242 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3243 }
3244
3245 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3246 }
3247
3248 return rc;
3249#else
3250 RT_NOREF(pThisCC, pCmd, cbCmd);
3251 return VERR_NOT_SUPPORTED;
3252#endif
3253}
3254
3255
3256/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3257static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3258{
3259#ifdef VMSVGA3D_DX
3260 DEBUG_BREAKPOINT_TEST();
3261 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3262 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3263 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3264#else
3265 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3266 return VERR_NOT_SUPPORTED;
3267#endif
3268}
3269
3270
3271/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3272static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3273{
3274#ifdef VMSVGA3D_DX
3275 DEBUG_BREAKPOINT_TEST();
3276 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3277 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3278 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3279#else
3280 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3281 return VERR_NOT_SUPPORTED;
3282#endif
3283}
3284
3285
3286/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3287static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3288{
3289#ifdef VMSVGA3D_DX
3290 DEBUG_BREAKPOINT_TEST();
3291 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3292 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3293 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
3294#else
3295 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3296 return VERR_NOT_SUPPORTED;
3297#endif
3298}
3299
3300
3301/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3302static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3303{
3304#ifdef VMSVGA3D_DX
3305 DEBUG_BREAKPOINT_TEST();
3306 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3307 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3308 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
3309#else
3310 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3311 return VERR_NOT_SUPPORTED;
3312#endif
3313}
3314
3315
3316/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3317static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3318{
3319#ifdef VMSVGA3D_DX
3320 //DEBUG_BREAKPOINT_TEST();
3321 RT_NOREF(idDXContext, cbCmd);
3322
3323 /* This command is executed in a context: "The context is implied from the command buffer header."
3324 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3325 */
3326 SVGA3dCmdDXTransferFromBuffer cmd;
3327 cmd.srcSid = pCmd->srcSid;
3328 cmd.srcOffset = pCmd->srcOffset;
3329 cmd.srcPitch = pCmd->srcPitch;
3330 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3331 cmd.destSid = pCmd->destSid;
3332 cmd.destSubResource = pCmd->destSubResource;
3333 cmd.destBox = pCmd->destBox;
3334 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3335#else
3336 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3337 return VERR_NOT_SUPPORTED;
3338#endif
3339}
3340
3341
3342/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3343static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3344{
3345#ifdef VMSVGA3D_DX
3346 DEBUG_BREAKPOINT_TEST();
3347 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3348 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3349 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3350#else
3351 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3352 return VERR_NOT_SUPPORTED;
3353#endif
3354}
3355
3356
3357/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3358static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3359{
3360#ifdef VMSVGA3D_DX
3361 DEBUG_BREAKPOINT_TEST();
3362 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3363 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3364 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3365#else
3366 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3367 return VERR_NOT_SUPPORTED;
3368#endif
3369}
3370
3371
3372/* SVGA_3D_CMD_DX_HINT 1218 */
3373static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3374{
3375#ifdef VMSVGA3D_DX
3376 DEBUG_BREAKPOINT_TEST();
3377 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3378 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3379 return vmsvga3dDXHint(pThisCC, idDXContext);
3380#else
3381 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3382 return VERR_NOT_SUPPORTED;
3383#endif
3384}
3385
3386
3387/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3388static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3389{
3390#ifdef VMSVGA3D_DX
3391 DEBUG_BREAKPOINT_TEST();
3392 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3393 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3394 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3395#else
3396 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3397 return VERR_NOT_SUPPORTED;
3398#endif
3399}
3400
3401
3402/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3403static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3404{
3405#ifdef VMSVGA3D_DX
3406 DEBUG_BREAKPOINT_TEST();
3407 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3408 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3409 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3410#else
3411 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3412 return VERR_NOT_SUPPORTED;
3413#endif
3414}
3415
3416
3417/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3418static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3419{
3420#ifdef VMSVGA3D_DX
3421 DEBUG_BREAKPOINT_TEST();
3422 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3423 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3424 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3425#else
3426 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3427 return VERR_NOT_SUPPORTED;
3428#endif
3429}
3430
3431
3432/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3433static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3434{
3435#ifdef VMSVGA3D_DX
3436 DEBUG_BREAKPOINT_TEST();
3437 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3438 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3439 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3440#else
3441 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3442 return VERR_NOT_SUPPORTED;
3443#endif
3444}
3445
3446
3447/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3448static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3449{
3450#ifdef VMSVGA3D_DX
3451 DEBUG_BREAKPOINT_TEST();
3452 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3453 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3454 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3455#else
3456 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3457 return VERR_NOT_SUPPORTED;
3458#endif
3459}
3460
3461
3462/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3463static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3464{
3465#ifdef VMSVGA3D_DX
3466 DEBUG_BREAKPOINT_TEST();
3467 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3468 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3469 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3470#else
3471 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3472 return VERR_NOT_SUPPORTED;
3473#endif
3474}
3475
3476
3477/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3478static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3479{
3480#ifdef VMSVGA3D_DX
3481 DEBUG_BREAKPOINT_TEST();
3482 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3483 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3484 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3485#else
3486 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3487 return VERR_NOT_SUPPORTED;
3488#endif
3489}
3490
3491
3492/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3493static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3494{
3495#ifdef VMSVGA3D_DX
3496 DEBUG_BREAKPOINT_TEST();
3497 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3498 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3499 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3500#else
3501 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3502 return VERR_NOT_SUPPORTED;
3503#endif
3504}
3505
3506
3507/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3508static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3509{
3510#ifdef VMSVGA3D_DX
3511 DEBUG_BREAKPOINT_TEST();
3512 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3513 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3514 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3515#else
3516 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3517 return VERR_NOT_SUPPORTED;
3518#endif
3519}
3520
3521
3522/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3523static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3524{
3525#ifdef VMSVGA3D_DX
3526 DEBUG_BREAKPOINT_TEST();
3527 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3528 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3529 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3530#else
3531 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3532 return VERR_NOT_SUPPORTED;
3533#endif
3534}
3535
3536
3537/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3538static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3539{
3540#ifdef VMSVGA3D_DX
3541 DEBUG_BREAKPOINT_TEST();
3542 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3543 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3544 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3545#else
3546 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3547 return VERR_NOT_SUPPORTED;
3548#endif
3549}
3550
3551
3552/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3553static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3554{
3555#ifdef VMSVGA3D_DX
3556 DEBUG_BREAKPOINT_TEST();
3557 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3558 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3559 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3560#else
3561 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3562 return VERR_NOT_SUPPORTED;
3563#endif
3564}
3565
3566
3567/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3568static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3569{
3570#ifdef VMSVGA3D_DX
3571 DEBUG_BREAKPOINT_TEST();
3572 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3573 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3574 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3575#else
3576 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3577 return VERR_NOT_SUPPORTED;
3578#endif
3579}
3580
3581
3582/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3583static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3584{
3585#ifdef VMSVGA3D_DX
3586 DEBUG_BREAKPOINT_TEST();
3587 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3588 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3589 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3590#else
3591 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3592 return VERR_NOT_SUPPORTED;
3593#endif
3594}
3595
3596
3597/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3598static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3599{
3600#ifdef VMSVGA3D_DX
3601 DEBUG_BREAKPOINT_TEST();
3602 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3603 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3604 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3605#else
3606 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3607 return VERR_NOT_SUPPORTED;
3608#endif
3609}
3610
3611
3612/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3613static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3614{
3615#ifdef VMSVGA3D_DX
3616 DEBUG_BREAKPOINT_TEST();
3617 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3618 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3619 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3620#else
3621 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3622 return VERR_NOT_SUPPORTED;
3623#endif
3624}
3625
3626
3627/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3628static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3629{
3630#ifdef VMSVGA3D_DX
3631 DEBUG_BREAKPOINT_TEST();
3632 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3633 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3634 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3635#else
3636 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3637 return VERR_NOT_SUPPORTED;
3638#endif
3639}
3640
3641
3642/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3643static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3644{
3645#ifdef VMSVGA3D_DX
3646 DEBUG_BREAKPOINT_TEST();
3647 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3648 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3649 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3650#else
3651 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3652 return VERR_NOT_SUPPORTED;
3653#endif
3654}
3655
3656
3657/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3658static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3659{
3660#ifdef VMSVGA3D_DX
3661 DEBUG_BREAKPOINT_TEST();
3662 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3663 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3664 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3665#else
3666 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3667 return VERR_NOT_SUPPORTED;
3668#endif
3669}
3670
3671
3672/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3673static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3674{
3675#ifdef VMSVGA3D_DX
3676 DEBUG_BREAKPOINT_TEST();
3677 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3678 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3679 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3680#else
3681 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3682 return VERR_NOT_SUPPORTED;
3683#endif
3684}
3685
3686
3687/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3688static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3689{
3690#ifdef VMSVGA3D_DX
3691 DEBUG_BREAKPOINT_TEST();
3692 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3693 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3694 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3695#else
3696 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3697 return VERR_NOT_SUPPORTED;
3698#endif
3699}
3700
3701
3702/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3703static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3704{
3705#ifdef VMSVGA3D_DX
3706 DEBUG_BREAKPOINT_TEST();
3707 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3708 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3709 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3710#else
3711 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3712 return VERR_NOT_SUPPORTED;
3713#endif
3714}
3715
3716
3717/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3718static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3719{
3720#ifdef VMSVGA3D_DX
3721 DEBUG_BREAKPOINT_TEST();
3722 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3723 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3724 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3725#else
3726 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3727 return VERR_NOT_SUPPORTED;
3728#endif
3729}
3730
3731
3732/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3733static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3734{
3735#ifdef VMSVGA3D_DX
3736 DEBUG_BREAKPOINT_TEST();
3737 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3738 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3739 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3740#else
3741 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3742 return VERR_NOT_SUPPORTED;
3743#endif
3744}
3745
3746
3747/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3748static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3749{
3750#ifdef VMSVGA3D_DX
3751 DEBUG_BREAKPOINT_TEST();
3752 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3753 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3754 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3755#else
3756 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3757 return VERR_NOT_SUPPORTED;
3758#endif
3759}
3760
3761
3762/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3763static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3764{
3765#ifdef VMSVGA3D_DX
3766 DEBUG_BREAKPOINT_TEST();
3767 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3768 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3769 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3770#else
3771 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3772 return VERR_NOT_SUPPORTED;
3773#endif
3774}
3775
3776
3777/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3778static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3779{
3780#ifdef VMSVGA3D_DX
3781 DEBUG_BREAKPOINT_TEST();
3782 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3783 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3784 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3785#else
3786 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3787 return VERR_NOT_SUPPORTED;
3788#endif
3789}
3790
3791
3792/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3793static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3794{
3795#ifdef VMSVGA3D_DX
3796 DEBUG_BREAKPOINT_TEST();
3797 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3798 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3799 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3800#else
3801 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3802 return VERR_NOT_SUPPORTED;
3803#endif
3804}
3805
3806
3807/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3808static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3809{
3810#ifdef VMSVGA3D_DX
3811 DEBUG_BREAKPOINT_TEST();
3812 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3813 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3814 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3815#else
3816 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3817 return VERR_NOT_SUPPORTED;
3818#endif
3819}
3820
3821
3822/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3823static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3824{
3825#ifdef VMSVGA3D_DX
3826 DEBUG_BREAKPOINT_TEST();
3827 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3828 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3829 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3830#else
3831 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3832 return VERR_NOT_SUPPORTED;
3833#endif
3834}
3835
3836
3837/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3838static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3839{
3840#ifdef VMSVGA3D_DX
3841 DEBUG_BREAKPOINT_TEST();
3842 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3843 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3844 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3845#else
3846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3847 return VERR_NOT_SUPPORTED;
3848#endif
3849}
3850
3851
3852/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3853static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3854{
3855#ifdef VMSVGA3D_DX
3856 DEBUG_BREAKPOINT_TEST();
3857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3858 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3859 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3860#else
3861 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3862 return VERR_NOT_SUPPORTED;
3863#endif
3864}
3865
3866
3867/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3868static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3869{
3870#ifdef VMSVGA3D_DX
3871 DEBUG_BREAKPOINT_TEST();
3872 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3873 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3874 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3875#else
3876 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3877 return VERR_NOT_SUPPORTED;
3878#endif
3879}
3880
3881
3882/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3883static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3884{
3885#ifdef VMSVGA3D_DX
3886 DEBUG_BREAKPOINT_TEST();
3887 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3888 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3889 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3890#else
3891 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3892 return VERR_NOT_SUPPORTED;
3893#endif
3894}
3895
3896
3897/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3898static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3899{
3900#ifdef VMSVGA3D_DX
3901 DEBUG_BREAKPOINT_TEST();
3902 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3903 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3904 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3905#else
3906 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3907 return VERR_NOT_SUPPORTED;
3908#endif
3909}
3910
3911
3912/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3913static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3914{
3915#ifdef VMSVGA3D_DX
3916 DEBUG_BREAKPOINT_TEST();
3917 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3918 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3919 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3920#else
3921 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3922 return VERR_NOT_SUPPORTED;
3923#endif
3924}
3925
3926
3927/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3928static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3929{
3930#ifdef VMSVGA3D_DX
3931 DEBUG_BREAKPOINT_TEST();
3932 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3933 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3934 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3935#else
3936 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3937 return VERR_NOT_SUPPORTED;
3938#endif
3939}
3940
3941
3942/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3943static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3944{
3945#ifdef VMSVGA3D_DX
3946 DEBUG_BREAKPOINT_TEST();
3947 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3948 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3949 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3950#else
3951 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3952 return VERR_NOT_SUPPORTED;
3953#endif
3954}
3955
3956
3957/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3958static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3959{
3960#ifdef VMSVGA3D_DX
3961 DEBUG_BREAKPOINT_TEST();
3962 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3963 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3964 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3965#else
3966 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3967 return VERR_NOT_SUPPORTED;
3968#endif
3969}
3970
3971
3972/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3973static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3974{
3975#ifdef VMSVGA3D_DX
3976 DEBUG_BREAKPOINT_TEST();
3977 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3978 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3979 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3980#else
3981 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3982 return VERR_NOT_SUPPORTED;
3983#endif
3984}
3985
3986
3987/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3988static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3989{
3990#ifdef VMSVGA3D_DX
3991 DEBUG_BREAKPOINT_TEST();
3992 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3993 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3994 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3995#else
3996 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3997 return VERR_NOT_SUPPORTED;
3998#endif
3999}
4000
4001
4002/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4003static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4004{
4005#ifdef VMSVGA3D_DX
4006 //DEBUG_BREAKPOINT_TEST();
4007 RT_NOREF(cbCmd);
4008 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4009#else
4010 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4011 return VERR_NOT_SUPPORTED;
4012#endif
4013}
4014
4015
4016/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4017static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4018{
4019#ifdef VMSVGA3D_DX
4020 DEBUG_BREAKPOINT_TEST();
4021 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4022 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4023 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4024#else
4025 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4026 return VERR_NOT_SUPPORTED;
4027#endif
4028}
4029
4030
4031/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4032static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4033{
4034#ifdef VMSVGA3D_DX
4035 DEBUG_BREAKPOINT_TEST();
4036 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4037 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4038 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4039#else
4040 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4041 return VERR_NOT_SUPPORTED;
4042#endif
4043}
4044
4045
4046/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4047static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4048{
4049#ifdef VMSVGA3D_DX
4050 DEBUG_BREAKPOINT_TEST();
4051 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4052 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4053 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4054#else
4055 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4056 return VERR_NOT_SUPPORTED;
4057#endif
4058}
4059
4060
4061/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4062static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4063{
4064#ifdef VMSVGA3D_DX
4065 DEBUG_BREAKPOINT_TEST();
4066 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4067 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4068 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4069#else
4070 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4071 return VERR_NOT_SUPPORTED;
4072#endif
4073}
4074
4075
4076/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4077static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4078{
4079#ifdef VMSVGA3D_DX
4080 DEBUG_BREAKPOINT_TEST();
4081 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4082 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4083 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4084#else
4085 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4086 return VERR_NOT_SUPPORTED;
4087#endif
4088}
4089
4090
4091/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4092 * Check that the 3D command has at least a_cbMin of payload bytes after the
4093 * header. Will break out of the switch if it doesn't.
4094 */
4095# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4096 if (1) { \
4097 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4098 RT_UNTRUSTED_VALIDATED_FENCE(); \
4099 } else do {} while (0)
4100
4101# define VMSVGA_3D_CMD_NOTIMPL() \
4102 if (1) { \
4103 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4104 } else do {} while (0)
4105
4106/** SVGA_3D_CMD_* handler.
4107 * This function parses the command and calls the corresponding command handler.
4108 *
4109 * @param pThis The shared VGA/VMSVGA state.
4110 * @param pThisCC The VGA/VMSVGA state for the current context.
4111 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4112 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4113 * @param cbCmd Size of the command in bytes.
4114 * @param pvCmd Pointer to the command.
4115 * @returns VBox status code if an error was detected parsing a command.
4116 */
4117int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4118{
4119 if (enmCmdId > SVGA_3D_CMD_MAX)
4120 {
4121 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4122 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4123 }
4124
4125 int rcParse = VINF_SUCCESS;
4126 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4127
4128 switch (enmCmdId)
4129 {
4130 case SVGA_3D_CMD_SURFACE_DEFINE:
4131 {
4132 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4133 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4134 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4135
4136 SVGA3dCmdDefineSurface_v2 cmd;
4137 cmd.sid = pCmd->sid;
4138 cmd.surfaceFlags = pCmd->surfaceFlags;
4139 cmd.format = pCmd->format;
4140 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4141 cmd.multisampleCount = 0;
4142 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4143
4144 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4145 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4146# ifdef DEBUG_GMR_ACCESS
4147 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4148# endif
4149 break;
4150 }
4151
4152 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4153 {
4154 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4155 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4156 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4157
4158 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4159 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4160# ifdef DEBUG_GMR_ACCESS
4161 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4162# endif
4163 break;
4164 }
4165
4166 case SVGA_3D_CMD_SURFACE_DESTROY:
4167 {
4168 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4170 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4171
4172 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4173 break;
4174 }
4175
4176 case SVGA_3D_CMD_SURFACE_COPY:
4177 {
4178 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4180 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4181
4182 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4183 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4184 break;
4185 }
4186
4187 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4188 {
4189 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4191 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4192
4193 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4194 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4195 break;
4196 }
4197
4198 case SVGA_3D_CMD_SURFACE_DMA:
4199 {
4200 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4201 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4202 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4203
4204 uint64_t u64NanoTS = 0;
4205 if (LogRelIs3Enabled())
4206 u64NanoTS = RTTimeNanoTS();
4207 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4208 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4209 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4210 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4211 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4212 if (LogRelIs3Enabled())
4213 {
4214 if (cCopyBoxes)
4215 {
4216 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4217 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4218 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4219 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4220 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4221 }
4222 }
4223 break;
4224 }
4225
4226 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4227 {
4228 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4229 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4230 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4231
4232 static uint64_t u64FrameStartNanoTS = 0;
4233 static uint64_t u64ElapsedPerSecNano = 0;
4234 static int cFrames = 0;
4235 uint64_t u64NanoTS = 0;
4236 if (LogRelIs3Enabled())
4237 u64NanoTS = RTTimeNanoTS();
4238 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4239 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4240 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4241 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4242 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4243 if (LogRelIs3Enabled())
4244 {
4245 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4246 u64ElapsedPerSecNano += u64ElapsedNano;
4247
4248 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4249 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4250 (u64ElapsedNano) / 1000ULL, cRects,
4251 pFirstRect->left, pFirstRect->top,
4252 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4253
4254 ++cFrames;
4255 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4256 {
4257 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4258 cFrames, u64ElapsedPerSecNano / 1000ULL));
4259 u64FrameStartNanoTS = u64NanoTS;
4260 cFrames = 0;
4261 u64ElapsedPerSecNano = 0;
4262 }
4263 }
4264 break;
4265 }
4266
4267 case SVGA_3D_CMD_CONTEXT_DEFINE:
4268 {
4269 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4271 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4272
4273 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4274 break;
4275 }
4276
4277 case SVGA_3D_CMD_CONTEXT_DESTROY:
4278 {
4279 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4280 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4281 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4282
4283 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4284 break;
4285 }
4286
4287 case SVGA_3D_CMD_SETTRANSFORM:
4288 {
4289 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4290 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4291 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4292
4293 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4294 break;
4295 }
4296
4297 case SVGA_3D_CMD_SETZRANGE:
4298 {
4299 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4300 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4301 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4302
4303 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4304 break;
4305 }
4306
4307 case SVGA_3D_CMD_SETRENDERSTATE:
4308 {
4309 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4310 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4311 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4312
4313 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4314 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4315 break;
4316 }
4317
4318 case SVGA_3D_CMD_SETRENDERTARGET:
4319 {
4320 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4321 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4322 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4323
4324 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4325 break;
4326 }
4327
4328 case SVGA_3D_CMD_SETTEXTURESTATE:
4329 {
4330 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4331 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4332 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4333
4334 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4335 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4336 break;
4337 }
4338
4339 case SVGA_3D_CMD_SETMATERIAL:
4340 {
4341 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4343 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4344
4345 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4346 break;
4347 }
4348
4349 case SVGA_3D_CMD_SETLIGHTDATA:
4350 {
4351 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4352 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4353 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4354
4355 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4356 break;
4357 }
4358
4359 case SVGA_3D_CMD_SETLIGHTENABLED:
4360 {
4361 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4363 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4364
4365 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4366 break;
4367 }
4368
4369 case SVGA_3D_CMD_SETVIEWPORT:
4370 {
4371 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4372 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4373 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4374
4375 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4376 break;
4377 }
4378
4379 case SVGA_3D_CMD_SETCLIPPLANE:
4380 {
4381 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4382 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4383 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4384
4385 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4386 break;
4387 }
4388
4389 case SVGA_3D_CMD_CLEAR:
4390 {
4391 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4392 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4393 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4394
4395 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4396 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4397 break;
4398 }
4399
4400 case SVGA_3D_CMD_PRESENT:
4401 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4402 {
4403 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4404 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4405 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4406 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4407 else
4408 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4409
4410 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4411 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4412 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4413 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4414 break;
4415 }
4416
4417 case SVGA_3D_CMD_SHADER_DEFINE:
4418 {
4419 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4420 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4421 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4422
4423 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4424 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4425 break;
4426 }
4427
4428 case SVGA_3D_CMD_SHADER_DESTROY:
4429 {
4430 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4431 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4432 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4433
4434 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4435 break;
4436 }
4437
4438 case SVGA_3D_CMD_SET_SHADER:
4439 {
4440 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4441 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4442 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4443
4444 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4445 break;
4446 }
4447
4448 case SVGA_3D_CMD_SET_SHADER_CONST:
4449 {
4450 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4451 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4452 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4453
4454 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4455 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4456 break;
4457 }
4458
4459 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4460 {
4461 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4463 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4464
4465 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4466 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4467 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4468 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4469 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4470
4471 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4472 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4473 RT_UNTRUSTED_VALIDATED_FENCE();
4474
4475 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4476 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4477 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4478
4479 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4480 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4481 pNumRange, cVertexDivisor, pVertexDivisor);
4482 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4483 break;
4484 }
4485
4486 case SVGA_3D_CMD_SETSCISSORRECT:
4487 {
4488 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4489 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4490 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4491
4492 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4493 break;
4494 }
4495
4496 case SVGA_3D_CMD_BEGIN_QUERY:
4497 {
4498 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4499 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4500 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4501
4502 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4503 break;
4504 }
4505
4506 case SVGA_3D_CMD_END_QUERY:
4507 {
4508 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4509 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4510 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4511
4512 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4513 break;
4514 }
4515
4516 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4517 {
4518 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4519 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4520 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4521
4522 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4523 break;
4524 }
4525
4526 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4527 {
4528 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4529 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4530 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4531
4532 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4533 break;
4534 }
4535
4536 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4537 /* context id + surface id? */
4538 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4539 break;
4540
4541 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4542 /* context id + surface id? */
4543 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4544 break;
4545
4546 /*
4547 *
4548 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4549 *
4550 */
4551 case SVGA_3D_CMD_SCREEN_DMA:
4552 {
4553 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4555 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4556 break;
4557 }
4558
4559 case SVGA_3D_CMD_DEAD1:
4560 case SVGA_3D_CMD_DEAD2:
4561 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4562 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4563 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4564 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4565 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4566 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4567 {
4568 VMSVGA_3D_CMD_NOTIMPL();
4569 break;
4570 }
4571
4572 case SVGA_3D_CMD_SET_OTABLE_BASE:
4573 {
4574 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4575 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4577 break;
4578 }
4579
4580 case SVGA_3D_CMD_READBACK_OTABLE:
4581 {
4582 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4585 break;
4586 }
4587
4588 case SVGA_3D_CMD_DEFINE_GB_MOB:
4589 {
4590 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4593 break;
4594 }
4595
4596 case SVGA_3D_CMD_DESTROY_GB_MOB:
4597 {
4598 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4601 break;
4602 }
4603
4604 case SVGA_3D_CMD_DEAD3:
4605 {
4606 VMSVGA_3D_CMD_NOTIMPL();
4607 break;
4608 }
4609
4610 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4611 {
4612 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4614 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4615 break;
4616 }
4617
4618 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4619 {
4620 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4622 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4623 break;
4624 }
4625
4626 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4627 {
4628 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4629 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4630 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4631 break;
4632 }
4633
4634 case SVGA_3D_CMD_BIND_GB_SURFACE:
4635 {
4636 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4637 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4638 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4639 break;
4640 }
4641
4642 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4643 {
4644 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4645 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4646 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4647 break;
4648 }
4649
4650 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4651 {
4652 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4654 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4655 break;
4656 }
4657
4658 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4659 {
4660 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4662 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4663 break;
4664 }
4665
4666 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4667 {
4668 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4669 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4671 break;
4672 }
4673
4674 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4675 {
4676 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4677 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4679 break;
4680 }
4681
4682 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4683 {
4684 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4685 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4686 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4687 break;
4688 }
4689
4690 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4691 {
4692 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4693 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4694 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4695 break;
4696 }
4697
4698 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4699 {
4700 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4702 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4703 break;
4704 }
4705
4706 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4707 {
4708 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4711 break;
4712 }
4713
4714 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4715 {
4716 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4718 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4719 break;
4720 }
4721
4722 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4723 {
4724 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4725 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4726 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4727 break;
4728 }
4729
4730 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4731 {
4732 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4733 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4734 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4735 break;
4736 }
4737
4738 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4739 {
4740 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4742 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4743 break;
4744 }
4745
4746 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4747 {
4748 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4750 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4751 break;
4752 }
4753
4754 case SVGA_3D_CMD_BIND_GB_SHADER:
4755 {
4756 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4758 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4759 break;
4760 }
4761
4762 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4763 {
4764 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4766 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4767 break;
4768 }
4769
4770 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4771 {
4772 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4773 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4774 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4775 break;
4776 }
4777
4778 case SVGA_3D_CMD_END_GB_QUERY:
4779 {
4780 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4781 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4782 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4783 break;
4784 }
4785
4786 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4787 {
4788 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4789 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4790 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4791 break;
4792 }
4793
4794 case SVGA_3D_CMD_NOP:
4795 {
4796 /* Apparently there is nothing to do. */
4797 break;
4798 }
4799
4800 case SVGA_3D_CMD_ENABLE_GART:
4801 {
4802 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4803 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4805 break;
4806 }
4807
4808 case SVGA_3D_CMD_DISABLE_GART:
4809 {
4810 /* No corresponding SVGA3dCmd structure. */
4811 VMSVGA_3D_CMD_NOTIMPL();
4812 break;
4813 }
4814
4815 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4816 {
4817 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4819 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4820 break;
4821 }
4822
4823 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4824 {
4825 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4827 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4828 break;
4829 }
4830
4831 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4832 {
4833 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4835 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4836 break;
4837 }
4838
4839 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4840 {
4841 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4843 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4844 break;
4845 }
4846
4847 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4848 {
4849 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4851 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4852 break;
4853 }
4854
4855 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4856 {
4857 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4859 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4860 break;
4861 }
4862
4863 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4864 {
4865 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4867 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4868 break;
4869 }
4870
4871 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4872 {
4873 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4875 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4876 break;
4877 }
4878
4879 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4880 {
4881 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4883 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4884 break;
4885 }
4886
4887 case SVGA_3D_CMD_GB_SCREEN_DMA:
4888 {
4889 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4891 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4892 break;
4893 }
4894
4895 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4896 {
4897 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4899 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4900 break;
4901 }
4902
4903 case SVGA_3D_CMD_GB_MOB_FENCE:
4904 {
4905 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4907 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4908 break;
4909 }
4910
4911 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4912 {
4913 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4915 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4916 break;
4917 }
4918
4919 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4920 {
4921 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4923 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4924 break;
4925 }
4926
4927 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4928 {
4929 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4931 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4932 break;
4933 }
4934
4935 case SVGA_3D_CMD_NOP_ERROR:
4936 {
4937 /* Apparently there is nothing to do. */
4938 break;
4939 }
4940
4941 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4942 {
4943 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4944 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4945 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4946 break;
4947 }
4948
4949 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4950 {
4951 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4952 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4953 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4954 break;
4955 }
4956
4957 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4958 {
4959 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4960 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4961 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4962 break;
4963 }
4964
4965 case SVGA_3D_CMD_DRAW:
4966 {
4967 /* No corresponding SVGA3dCmd structure. */
4968 VMSVGA_3D_CMD_NOTIMPL();
4969 break;
4970 }
4971
4972 case SVGA_3D_CMD_DRAW_INDEXED:
4973 {
4974 /* No corresponding SVGA3dCmd structure. */
4975 VMSVGA_3D_CMD_NOTIMPL();
4976 break;
4977 }
4978
4979 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4980 {
4981 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4982 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4983 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4984 break;
4985 }
4986
4987 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4988 {
4989 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4991 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4992 break;
4993 }
4994
4995 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4996 {
4997 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4999 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5004 {
5005 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5012 {
5013 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5020 {
5021 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5028 {
5029 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_DX_SET_SHADER:
5036 {
5037 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5044 {
5045 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_DX_DRAW:
5052 {
5053 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5060 {
5061 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5064 break;
5065 }
5066
5067 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5068 {
5069 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5071 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5072 break;
5073 }
5074
5075 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5076 {
5077 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DX_DRAW_AUTO:
5084 {
5085 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5087 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5088 break;
5089 }
5090
5091 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5092 {
5093 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5095 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5096 break;
5097 }
5098
5099 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5100 {
5101 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5104 break;
5105 }
5106
5107 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5108 {
5109 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5110 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5111 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5112 break;
5113 }
5114
5115 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5116 {
5117 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5119 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5120 break;
5121 }
5122
5123 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5124 {
5125 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5127 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5128 break;
5129 }
5130
5131 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5132 {
5133 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5135 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5136 break;
5137 }
5138
5139 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5140 {
5141 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5143 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5144 break;
5145 }
5146
5147 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5148 {
5149 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5151 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5152 break;
5153 }
5154
5155 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5156 {
5157 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5158 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5159 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5160 break;
5161 }
5162
5163 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5164 {
5165 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5166 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5167 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5168 break;
5169 }
5170
5171 case SVGA_3D_CMD_DX_BIND_QUERY:
5172 {
5173 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5175 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5176 break;
5177 }
5178
5179 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5180 {
5181 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5183 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5184 break;
5185 }
5186
5187 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5188 {
5189 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5191 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5192 break;
5193 }
5194
5195 case SVGA_3D_CMD_DX_END_QUERY:
5196 {
5197 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5198 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5199 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5200 break;
5201 }
5202
5203 case SVGA_3D_CMD_DX_READBACK_QUERY:
5204 {
5205 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5206 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5207 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5208 break;
5209 }
5210
5211 case SVGA_3D_CMD_DX_SET_PREDICATION:
5212 {
5213 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5215 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5216 break;
5217 }
5218
5219 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5220 {
5221 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5223 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5224 break;
5225 }
5226
5227 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5228 {
5229 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5230 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5231 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5232 break;
5233 }
5234
5235 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5236 {
5237 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5238 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5239 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5240 break;
5241 }
5242
5243 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5244 {
5245 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5246 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5247 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5248 break;
5249 }
5250
5251 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5252 {
5253 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5255 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5256 break;
5257 }
5258
5259 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5260 {
5261 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5262 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5263 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5264 break;
5265 }
5266
5267 case SVGA_3D_CMD_DX_PRED_COPY:
5268 {
5269 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5271 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5272 break;
5273 }
5274
5275 case SVGA_3D_CMD_DX_PRESENTBLT:
5276 {
5277 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5278 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5279 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5280 break;
5281 }
5282
5283 case SVGA_3D_CMD_DX_GENMIPS:
5284 {
5285 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5287 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5288 break;
5289 }
5290
5291 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5292 {
5293 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5294 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5295 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5296 break;
5297 }
5298
5299 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5300 {
5301 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5302 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5303 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5304 break;
5305 }
5306
5307 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5308 {
5309 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5310 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5311 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5312 break;
5313 }
5314
5315 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5316 {
5317 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5318 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5319 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5320 break;
5321 }
5322
5323 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5324 {
5325 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5326 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5327 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5328 break;
5329 }
5330
5331 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5332 {
5333 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5334 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5335 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5336 break;
5337 }
5338
5339 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5340 {
5341 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5343 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5344 break;
5345 }
5346
5347 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5348 {
5349 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5350 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5351 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5352 break;
5353 }
5354
5355 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5356 {
5357 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5359 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5360 break;
5361 }
5362
5363 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5364 {
5365 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5367 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5368 break;
5369 }
5370
5371 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5372 {
5373 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5374 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5375 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5376 break;
5377 }
5378
5379 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5380 {
5381 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5382 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5383 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5384 break;
5385 }
5386
5387 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5388 {
5389 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5390 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5391 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5392 break;
5393 }
5394
5395 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5396 {
5397 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5399 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5400 break;
5401 }
5402
5403 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5404 {
5405 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5407 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5408 break;
5409 }
5410
5411 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5412 {
5413 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5415 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5416 break;
5417 }
5418
5419 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5420 {
5421 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5422 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5423 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5424 break;
5425 }
5426
5427 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5428 {
5429 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5430 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5431 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5432 break;
5433 }
5434
5435 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5436 {
5437 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5439 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5440 break;
5441 }
5442
5443 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5444 {
5445 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5446 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5447 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5448 break;
5449 }
5450
5451 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5452 {
5453 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5454 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5455 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5456 break;
5457 }
5458
5459 case SVGA_3D_CMD_DX_BIND_SHADER:
5460 {
5461 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5463 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5464 break;
5465 }
5466
5467 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5468 {
5469 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5471 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5472 break;
5473 }
5474
5475 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5476 {
5477 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5479 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5480 break;
5481 }
5482
5483 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5484 {
5485 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5487 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5488 break;
5489 }
5490
5491 case SVGA_3D_CMD_DX_SET_COTABLE:
5492 {
5493 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5494 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5495 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5496 break;
5497 }
5498
5499 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5500 {
5501 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5502 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5503 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5504 break;
5505 }
5506
5507 case SVGA_3D_CMD_DX_BUFFER_COPY:
5508 {
5509 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5511 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5512 break;
5513 }
5514
5515 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5516 {
5517 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5519 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5520 break;
5521 }
5522
5523 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5524 {
5525 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5526 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5527 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5528 break;
5529 }
5530
5531 case SVGA_3D_CMD_DX_MOVE_QUERY:
5532 {
5533 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5535 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5536 break;
5537 }
5538
5539 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5540 {
5541 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5543 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5544 break;
5545 }
5546
5547 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5548 {
5549 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5550 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5551 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5552 break;
5553 }
5554
5555 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5556 {
5557 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5559 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5560 break;
5561 }
5562
5563 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5564 {
5565 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5566 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5567 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5568 break;
5569 }
5570
5571 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5572 {
5573 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5574 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5575 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5576 break;
5577 }
5578
5579 case SVGA_3D_CMD_DX_HINT:
5580 {
5581 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5582 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5583 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5584 break;
5585 }
5586
5587 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5588 {
5589 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5591 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5592 break;
5593 }
5594
5595 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5596 {
5597 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5598 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5599 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5600 break;
5601 }
5602
5603 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5604 {
5605 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5606 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5607 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5608 break;
5609 }
5610
5611 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5612 {
5613 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5614 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5615 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5616 break;
5617 }
5618
5619 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5620 {
5621 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5623 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5624 break;
5625 }
5626
5627 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5628 {
5629 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5631 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5632 break;
5633 }
5634
5635 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5636 {
5637 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5639 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5640 break;
5641 }
5642
5643 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5644 {
5645 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5647 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5648 break;
5649 }
5650
5651 case SVGA_3D_CMD_SCREEN_COPY:
5652 {
5653 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5655 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5656 break;
5657 }
5658
5659 case SVGA_3D_CMD_RESERVED1:
5660 {
5661 VMSVGA_3D_CMD_NOTIMPL();
5662 break;
5663 }
5664
5665 case SVGA_3D_CMD_RESERVED2:
5666 {
5667 VMSVGA_3D_CMD_NOTIMPL();
5668 break;
5669 }
5670
5671 case SVGA_3D_CMD_RESERVED3:
5672 {
5673 VMSVGA_3D_CMD_NOTIMPL();
5674 break;
5675 }
5676
5677 case SVGA_3D_CMD_RESERVED4:
5678 {
5679 VMSVGA_3D_CMD_NOTIMPL();
5680 break;
5681 }
5682
5683 case SVGA_3D_CMD_RESERVED5:
5684 {
5685 VMSVGA_3D_CMD_NOTIMPL();
5686 break;
5687 }
5688
5689 case SVGA_3D_CMD_RESERVED6:
5690 {
5691 VMSVGA_3D_CMD_NOTIMPL();
5692 break;
5693 }
5694
5695 case SVGA_3D_CMD_RESERVED7:
5696 {
5697 VMSVGA_3D_CMD_NOTIMPL();
5698 break;
5699 }
5700
5701 case SVGA_3D_CMD_RESERVED8:
5702 {
5703 VMSVGA_3D_CMD_NOTIMPL();
5704 break;
5705 }
5706
5707 case SVGA_3D_CMD_GROW_OTABLE:
5708 {
5709 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5710 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5711 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5712 break;
5713 }
5714
5715 case SVGA_3D_CMD_DX_GROW_COTABLE:
5716 {
5717 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5718 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5719 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5720 break;
5721 }
5722
5723 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5724 {
5725 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5726 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5727 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5728 break;
5729 }
5730
5731 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5732 {
5733 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5734 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5735 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5736 break;
5737 }
5738
5739 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5740 {
5741 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5742 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5743 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5744 break;
5745 }
5746
5747 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5748 {
5749 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5750 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5751 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5752 break;
5753 }
5754
5755 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5756 {
5757 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5758 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5759 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5760 break;
5761 }
5762
5763 case SVGA_3D_CMD_DX_PRED_CONVERT:
5764 {
5765 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5766 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5767 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5768 break;
5769 }
5770
5771 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5772 {
5773 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5775 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5776 break;
5777 }
5778
5779 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5780 {
5781 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5782 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5783 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5784 break;
5785 }
5786
5787 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5788 {
5789 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5790 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5791 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5792 break;
5793 }
5794
5795 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5796 {
5797 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5799 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5800 break;
5801 }
5802
5803 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5804 {
5805 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5806 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5807 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5808 break;
5809 }
5810
5811 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5812 {
5813 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5814 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5815 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5816 break;
5817 }
5818
5819 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5820 {
5821 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5822 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5823 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5824 break;
5825 }
5826
5827 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5828 {
5829 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5831 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5832 break;
5833 }
5834
5835 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5836 {
5837 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5838 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5839 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5840 break;
5841 }
5842
5843 case SVGA_3D_CMD_DX_DISPATCH:
5844 {
5845 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5846 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5847 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5848 break;
5849 }
5850
5851 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5852 {
5853 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5854 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5855 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5856 break;
5857 }
5858
5859 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5860 {
5861 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5862 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5863 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5864 break;
5865 }
5866
5867 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5868 {
5869 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5870 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5871 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5872 break;
5873 }
5874
5875 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5876 {
5877 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5878 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5879 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5880 break;
5881 }
5882
5883 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5884 {
5885 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5886 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5887 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5888 break;
5889 }
5890
5891 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5892 {
5893 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5894 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5895 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5896 break;
5897 }
5898
5899 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5900 {
5901 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5903 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5904 break;
5905 }
5906
5907 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5908 {
5909 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5910 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5911 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5912 break;
5913 }
5914
5915 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5916 {
5917 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5919 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5920 break;
5921 }
5922
5923 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5924 {
5925 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5926 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5927 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5928 break;
5929 }
5930
5931 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5932 {
5933 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5934 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5935 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5936 break;
5937 }
5938
5939 case SVGA_3D_CMD_RESERVED2_1:
5940 {
5941 VMSVGA_3D_CMD_NOTIMPL();
5942 break;
5943 }
5944
5945 case SVGA_3D_CMD_RESERVED2_2:
5946 {
5947 VMSVGA_3D_CMD_NOTIMPL();
5948 break;
5949 }
5950
5951 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5952 {
5953 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5955 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5956 break;
5957 }
5958
5959 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5960 {
5961 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5963 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5964 break;
5965 }
5966
5967 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5968 {
5969 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5971 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5972 break;
5973 }
5974
5975 case SVGA_3D_CMD_RESERVED2_3:
5976 {
5977 VMSVGA_3D_CMD_NOTIMPL();
5978 break;
5979 }
5980
5981 case SVGA_3D_CMD_RESERVED2_4:
5982 {
5983 VMSVGA_3D_CMD_NOTIMPL();
5984 break;
5985 }
5986
5987 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5988 {
5989 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5991 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5992 break;
5993 }
5994
5995 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5996 {
5997 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5999 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6000 break;
6001 }
6002
6003 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6004 {
6005 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6007 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6008 break;
6009 }
6010
6011 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6012 {
6013 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6015 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6016 break;
6017 }
6018
6019 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6020 {
6021 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6023 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6024 break;
6025 }
6026
6027 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6028 {
6029 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6031 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6032 break;
6033 }
6034
6035 /* Unsupported commands. */
6036 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6037 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6038 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6039 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6040 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6041 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6042 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6043 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6044 /* Prevent the compiler warning. */
6045 case SVGA_3D_CMD_LEGACY_BASE:
6046 case SVGA_3D_CMD_MAX:
6047 case SVGA_3D_CMD_FUTURE_MAX:
6048 /* No 'default' case */
6049 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6050 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6051 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6052 rcParse = VERR_NOT_IMPLEMENTED;
6053 break;
6054 }
6055
6056 return VINF_SUCCESS;
6057// return rcParse;
6058}
6059# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6060#endif /* VBOX_WITH_VMSVGA3D */
6061
6062
6063/*
6064 *
6065 * Handlers for FIFO commands.
6066 *
6067 * Every handler takes the following parameters:
6068 *
6069 * pThis The shared VGA/VMSVGA state.
6070 * pThisCC The VGA/VMSVGA state for ring-3.
6071 * pCmd The command data.
6072 */
6073
6074
6075/* SVGA_CMD_UPDATE */
6076void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6077{
6078 RT_NOREF(pThis);
6079 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6080
6081 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6082 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6083
6084 /** @todo Multiple screens? */
6085 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6086 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6087 return;
6088
6089 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6090}
6091
6092
6093/* SVGA_CMD_UPDATE_VERBOSE */
6094void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6095{
6096 RT_NOREF(pThis);
6097 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6098
6099 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6100 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6101
6102 /** @todo Multiple screens? */
6103 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6104 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6105 return;
6106
6107 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6108}
6109
6110
6111/* SVGA_CMD_RECT_FILL */
6112void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6113{
6114 RT_NOREF(pThis, pCmd);
6115 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6116
6117 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6118 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6119 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6120}
6121
6122
6123/* SVGA_CMD_RECT_COPY */
6124void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6125{
6126 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6127
6128 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6129 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6130
6131 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6132 AssertPtrReturnVoid(pScreen);
6133
6134 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6135 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6136 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6137 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6138 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6139 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6140 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6141
6142 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6143 pCmd->width, pCmd->height, pThis->vram_size);
6144 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6145}
6146
6147
6148/* SVGA_CMD_RECT_ROP_COPY */
6149void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6150{
6151 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6152
6153 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6154 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6155
6156 if (pCmd->rop != SVGA_ROP_COPY)
6157 {
6158 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6159 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6160 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6161 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6162 */
6163 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6164 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6165 return;
6166 }
6167
6168 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6169 AssertPtrReturnVoid(pScreen);
6170
6171 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6172 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6173 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6174 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6175 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6176 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6177 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6178
6179 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6180 pCmd->width, pCmd->height, pThis->vram_size);
6181 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6182}
6183
6184
6185/* SVGA_CMD_DISPLAY_CURSOR */
6186void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6187{
6188 RT_NOREF(pThis, pCmd);
6189 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6190
6191 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6192 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6193 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6194}
6195
6196
6197/* SVGA_CMD_MOVE_CURSOR */
6198void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6199{
6200 RT_NOREF(pThis, pCmd);
6201 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6202
6203 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6204 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6205 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6206}
6207
6208
6209/* SVGA_CMD_DEFINE_CURSOR */
6210void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6211{
6212 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6213
6214 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6215 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6216 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6217
6218 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6219 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6220 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6221 RT_UNTRUSTED_VALIDATED_FENCE();
6222
6223 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6224 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6225 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6226
6227 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6228 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6229
6230 uint32_t const cx = pCmd->width;
6231 uint32_t const cy = pCmd->height;
6232
6233 /*
6234 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6235 * The AND data uses 8-bit aligned scanlines.
6236 * The XOR data must be starting on a 32-bit boundrary.
6237 */
6238 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6239 uint32_t cbDstAndMask = cbDstAndLine * cy;
6240 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6241 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6242
6243 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6244 AssertReturnVoid(pbCopy);
6245
6246 /* Convert the AND mask. */
6247 uint8_t *pbDst = pbCopy;
6248 uint8_t const *pbSrc = pbSrcAndMask;
6249 switch (pCmd->andMaskDepth)
6250 {
6251 case 1:
6252 if (cbSrcAndLine == cbDstAndLine)
6253 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6254 else
6255 {
6256 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6257 for (uint32_t y = 0; y < cy; y++)
6258 {
6259 memcpy(pbDst, pbSrc, cbDstAndLine);
6260 pbDst += cbDstAndLine;
6261 pbSrc += cbSrcAndLine;
6262 }
6263 }
6264 break;
6265 /* Should take the XOR mask into account for the multi-bit AND mask. */
6266 case 8:
6267 for (uint32_t y = 0; y < cy; y++)
6268 {
6269 for (uint32_t x = 0; x < cx; )
6270 {
6271 uint8_t bDst = 0;
6272 uint8_t fBit = 0x80;
6273 do
6274 {
6275 uintptr_t const idxPal = pbSrc[x] * 3;
6276 if ((( pThis->last_palette[idxPal]
6277 | (pThis->last_palette[idxPal] >> 8)
6278 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6279 bDst |= fBit;
6280 fBit >>= 1;
6281 x++;
6282 } while (x < cx && (x & 7));
6283 pbDst[(x - 1) / 8] = bDst;
6284 }
6285 pbDst += cbDstAndLine;
6286 pbSrc += cbSrcAndLine;
6287 }
6288 break;
6289 case 15:
6290 for (uint32_t y = 0; y < cy; y++)
6291 {
6292 for (uint32_t x = 0; x < cx; )
6293 {
6294 uint8_t bDst = 0;
6295 uint8_t fBit = 0x80;
6296 do
6297 {
6298 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6299 bDst |= fBit;
6300 fBit >>= 1;
6301 x++;
6302 } while (x < cx && (x & 7));
6303 pbDst[(x - 1) / 8] = bDst;
6304 }
6305 pbDst += cbDstAndLine;
6306 pbSrc += cbSrcAndLine;
6307 }
6308 break;
6309 case 16:
6310 for (uint32_t y = 0; y < cy; y++)
6311 {
6312 for (uint32_t x = 0; x < cx; )
6313 {
6314 uint8_t bDst = 0;
6315 uint8_t fBit = 0x80;
6316 do
6317 {
6318 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6319 bDst |= fBit;
6320 fBit >>= 1;
6321 x++;
6322 } while (x < cx && (x & 7));
6323 pbDst[(x - 1) / 8] = bDst;
6324 }
6325 pbDst += cbDstAndLine;
6326 pbSrc += cbSrcAndLine;
6327 }
6328 break;
6329 case 24:
6330 for (uint32_t y = 0; y < cy; y++)
6331 {
6332 for (uint32_t x = 0; x < cx; )
6333 {
6334 uint8_t bDst = 0;
6335 uint8_t fBit = 0x80;
6336 do
6337 {
6338 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6339 bDst |= fBit;
6340 fBit >>= 1;
6341 x++;
6342 } while (x < cx && (x & 7));
6343 pbDst[(x - 1) / 8] = bDst;
6344 }
6345 pbDst += cbDstAndLine;
6346 pbSrc += cbSrcAndLine;
6347 }
6348 break;
6349 case 32:
6350 for (uint32_t y = 0; y < cy; y++)
6351 {
6352 for (uint32_t x = 0; x < cx; )
6353 {
6354 uint8_t bDst = 0;
6355 uint8_t fBit = 0x80;
6356 do
6357 {
6358 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6359 bDst |= fBit;
6360 fBit >>= 1;
6361 x++;
6362 } while (x < cx && (x & 7));
6363 pbDst[(x - 1) / 8] = bDst;
6364 }
6365 pbDst += cbDstAndLine;
6366 pbSrc += cbSrcAndLine;
6367 }
6368 break;
6369 default:
6370 RTMemFreeZ(pbCopy, cbCopy);
6371 AssertFailedReturnVoid();
6372 }
6373
6374 /* Convert the XOR mask. */
6375 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6376 pbSrc = pbSrcXorMask;
6377 switch (pCmd->xorMaskDepth)
6378 {
6379 case 1:
6380 for (uint32_t y = 0; y < cy; y++)
6381 {
6382 for (uint32_t x = 0; x < cx; )
6383 {
6384 /* most significant bit is the left most one. */
6385 uint8_t bSrc = pbSrc[x / 8];
6386 do
6387 {
6388 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6389 bSrc <<= 1;
6390 x++;
6391 } while ((x & 7) && x < cx);
6392 }
6393 pbSrc += cbSrcXorLine;
6394 }
6395 break;
6396 case 8:
6397 for (uint32_t y = 0; y < cy; y++)
6398 {
6399 for (uint32_t x = 0; x < cx; x++)
6400 {
6401 uint32_t u = pThis->last_palette[pbSrc[x]];
6402 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6403 }
6404 pbSrc += cbSrcXorLine;
6405 }
6406 break;
6407 case 15: /* Src: RGB-5-5-5 */
6408 for (uint32_t y = 0; y < cy; y++)
6409 {
6410 for (uint32_t x = 0; x < cx; x++)
6411 {
6412 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6413 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6414 ((uValue >> 5) & 0x1f) << 3,
6415 ((uValue >> 10) & 0x1f) << 3, 0);
6416 }
6417 pbSrc += cbSrcXorLine;
6418 }
6419 break;
6420 case 16: /* Src: RGB-5-6-5 */
6421 for (uint32_t y = 0; y < cy; y++)
6422 {
6423 for (uint32_t x = 0; x < cx; x++)
6424 {
6425 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6426 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6427 ((uValue >> 5) & 0x3f) << 2,
6428 ((uValue >> 11) & 0x1f) << 3, 0);
6429 }
6430 pbSrc += cbSrcXorLine;
6431 }
6432 break;
6433 case 24:
6434 for (uint32_t y = 0; y < cy; y++)
6435 {
6436 for (uint32_t x = 0; x < cx; x++)
6437 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6438 pbSrc += cbSrcXorLine;
6439 }
6440 break;
6441 case 32:
6442 for (uint32_t y = 0; y < cy; y++)
6443 {
6444 for (uint32_t x = 0; x < cx; x++)
6445 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6446 pbSrc += cbSrcXorLine;
6447 }
6448 break;
6449 default:
6450 RTMemFreeZ(pbCopy, cbCopy);
6451 AssertFailedReturnVoid();
6452 }
6453
6454 /*
6455 * Pass it to the frontend/whatever.
6456 */
6457 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6458 cx, cy, pbCopy, cbCopy);
6459}
6460
6461
6462/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6463void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6464{
6465 RT_NOREF(pThis);
6466 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6467
6468 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6469 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6470
6471 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6472 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6473 RT_UNTRUSTED_VALIDATED_FENCE();
6474
6475 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6476 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6477 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6478 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6479 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6480
6481 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6482 AssertPtrReturnVoid(pCursorCopy);
6483
6484 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6485 memset(pCursorCopy, 0xff, cbAndMask);
6486 /* Colour data */
6487 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6488
6489 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6490 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6491}
6492
6493
6494/* SVGA_CMD_ESCAPE */
6495void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6496{
6497 RT_NOREF(pThis);
6498 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6499
6500 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6501
6502 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6503 {
6504 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6505 RT_UNTRUSTED_VALIDATED_FENCE();
6506
6507 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6508 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6509
6510 switch (cmd)
6511 {
6512 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6513 {
6514 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6515 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6516 RT_UNTRUSTED_VALIDATED_FENCE();
6517
6518 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6519
6520 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6521 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6522 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6523 RT_NOREF_PV(pVideoCmd);
6524 break;
6525 }
6526
6527 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6528 {
6529 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6530 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6531 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6532 RT_NOREF_PV(pVideoCmd);
6533 break;
6534 }
6535
6536 default:
6537 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6538 break;
6539 }
6540 }
6541 else
6542 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6543}
6544
6545
6546/* SVGA_CMD_DEFINE_SCREEN */
6547void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6548{
6549 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6550
6551 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6552 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6553 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6554 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6555
6556 uint32_t const idScreen = pCmd->screen.id;
6557 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6558
6559 uint32_t const uWidth = pCmd->screen.size.width;
6560 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6561
6562 uint32_t const uHeight = pCmd->screen.size.height;
6563 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6564
6565 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6566 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6567 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6568
6569 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6570 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6571
6572 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6573 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6574 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6575 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6576 RT_UNTRUSTED_VALIDATED_FENCE();
6577
6578 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6579 pScreen->fDefined = true;
6580 pScreen->fModified = true;
6581 pScreen->fuScreen = pCmd->screen.flags;
6582 pScreen->idScreen = idScreen;
6583 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6584 {
6585 /* Not blanked. */
6586 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6587 RT_UNTRUSTED_VALIDATED_FENCE();
6588
6589 pScreen->xOrigin = pCmd->screen.root.x;
6590 pScreen->yOrigin = pCmd->screen.root.y;
6591 pScreen->cWidth = uWidth;
6592 pScreen->cHeight = uHeight;
6593 pScreen->offVRAM = uScreenOffset;
6594 pScreen->cbPitch = cbPitch;
6595 pScreen->cBpp = 32;
6596 }
6597 else
6598 {
6599 /* Screen blanked. Keep old values. */
6600 }
6601
6602 pThis->svga.fGFBRegisters = false;
6603 vmsvgaR3ChangeMode(pThis, pThisCC);
6604
6605#ifdef VBOX_WITH_VMSVGA3D
6606 if (RT_LIKELY(pThis->svga.f3DEnabled))
6607 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6608#endif
6609}
6610
6611
6612/* SVGA_CMD_DESTROY_SCREEN */
6613void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6614{
6615 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6616
6617 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6618 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6619
6620 uint32_t const idScreen = pCmd->screenId;
6621 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6622 RT_UNTRUSTED_VALIDATED_FENCE();
6623
6624 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6625 pScreen->fModified = true;
6626 pScreen->fDefined = false;
6627 pScreen->idScreen = idScreen;
6628
6629#ifdef VBOX_WITH_VMSVGA3D
6630 if (RT_LIKELY(pThis->svga.f3DEnabled))
6631 vmsvga3dDestroyScreen(pThisCC, pScreen);
6632#endif
6633 vmsvgaR3ChangeMode(pThis, pThisCC);
6634}
6635
6636
6637/* SVGA_CMD_DEFINE_GMRFB */
6638void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6639{
6640 RT_NOREF(pThis);
6641 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6642
6643 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6644 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6645 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6646
6647 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6648 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6649 pSvgaR3State->GMRFB.format = pCmd->format;
6650}
6651
6652
6653/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6654void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6655{
6656 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6657
6658 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6659 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6660 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6661
6662 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6663 RT_UNTRUSTED_VALIDATED_FENCE();
6664
6665 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6666 AssertPtrReturnVoid(pScreen);
6667
6668 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6669 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6670
6671 /* Clip destRect to the screen dimensions. */
6672 SVGASignedRect screenRect;
6673 screenRect.left = 0;
6674 screenRect.top = 0;
6675 screenRect.right = pScreen->cWidth;
6676 screenRect.bottom = pScreen->cHeight;
6677 SVGASignedRect clipRect = pCmd->destRect;
6678 vmsvgaR3ClipRect(&screenRect, &clipRect);
6679 RT_UNTRUSTED_VALIDATED_FENCE();
6680
6681 uint32_t const width = clipRect.right - clipRect.left;
6682 uint32_t const height = clipRect.bottom - clipRect.top;
6683
6684 if ( width == 0
6685 || height == 0)
6686 return; /* Nothing to do. */
6687
6688 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6689 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6690
6691 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6692 * Prepare parameters for vmsvgaR3GmrTransfer.
6693 */
6694 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6695
6696 /* Destination: host buffer which describes the screen 0 VRAM.
6697 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6698 */
6699 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6700 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6701 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6702 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6703 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6704 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6705 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6706 + cbScanline * clipRect.top;
6707 int32_t const cbHstPitch = cbScanline;
6708
6709 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6710 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6711 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6712 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6713 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6714
6715 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6716 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6717 gstPtr, offGst, cbGstPitch,
6718 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6719 AssertRC(rc);
6720 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6721}
6722
6723
6724/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6725void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6726{
6727 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6728
6729 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6730 /* Note! This can fetch 3d render results as well!! */
6731 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6732 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6733
6734 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6735 RT_UNTRUSTED_VALIDATED_FENCE();
6736
6737 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6738 AssertPtrReturnVoid(pScreen);
6739
6740 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6741 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6742
6743 /* Clip destRect to the screen dimensions. */
6744 SVGASignedRect screenRect;
6745 screenRect.left = 0;
6746 screenRect.top = 0;
6747 screenRect.right = pScreen->cWidth;
6748 screenRect.bottom = pScreen->cHeight;
6749 SVGASignedRect clipRect = pCmd->srcRect;
6750 vmsvgaR3ClipRect(&screenRect, &clipRect);
6751 RT_UNTRUSTED_VALIDATED_FENCE();
6752
6753 uint32_t const width = clipRect.right - clipRect.left;
6754 uint32_t const height = clipRect.bottom - clipRect.top;
6755
6756 if ( width == 0
6757 || height == 0)
6758 return; /* Nothing to do. */
6759
6760 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6761 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6762
6763 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6764 * Prepare parameters for vmsvgaR3GmrTransfer.
6765 */
6766 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6767
6768 /* Source: host buffer which describes the screen 0 VRAM.
6769 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6770 */
6771 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6772 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6773 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6774 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6775 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6776 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6777 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6778 + cbScanline * clipRect.top;
6779 int32_t const cbHstPitch = cbScanline;
6780
6781 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6782 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6783 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6784 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6785 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6786
6787 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6788 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6789 gstPtr, offGst, cbGstPitch,
6790 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6791 AssertRC(rc);
6792}
6793
6794
6795/* SVGA_CMD_ANNOTATION_FILL */
6796void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6797{
6798 RT_NOREF(pThis);
6799 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6800
6801 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6802 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6803
6804 pSvgaR3State->colorAnnotation = pCmd->color;
6805}
6806
6807
6808/* SVGA_CMD_ANNOTATION_COPY */
6809void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6810{
6811 RT_NOREF(pThis, pCmd);
6812 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6813
6814 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6815 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6816
6817 AssertFailed();
6818}
6819
6820
6821#ifdef VBOX_WITH_VMSVGA3D
6822/* SVGA_CMD_DEFINE_GMR2 */
6823void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6824{
6825 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6826
6827 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6828 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6829
6830 /* Validate current GMR id. */
6831 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6832 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6833 RT_UNTRUSTED_VALIDATED_FENCE();
6834
6835 if (!pCmd->numPages)
6836 {
6837 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6838 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6839 }
6840 else
6841 {
6842 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6843 if (pGMR->cMaxPages)
6844 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6845
6846 /* Not sure if we should always free the descriptor, but for simplicity
6847 we do so if the new size is smaller than the current. */
6848 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6849 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6850 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6851
6852 pGMR->cMaxPages = pCmd->numPages;
6853 /* The rest is done by the REMAP_GMR2 command. */
6854 }
6855}
6856
6857
6858/* SVGA_CMD_REMAP_GMR2 */
6859void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6860{
6861 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6862
6863 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6864 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6865
6866 /* Validate current GMR id and size. */
6867 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6868 RT_UNTRUSTED_VALIDATED_FENCE();
6869 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6870 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6871 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6872 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6873
6874 if (pCmd->numPages == 0)
6875 return;
6876 RT_UNTRUSTED_VALIDATED_FENCE();
6877
6878 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6879 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6880
6881 /*
6882 * We flatten the existing descriptors into a page array, overwrite the
6883 * pages specified in this command and then recompress the descriptor.
6884 */
6885 /** @todo Optimize the GMR remap algorithm! */
6886
6887 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6888 uint64_t *paNewPage64 = NULL;
6889 if (pGMR->paDesc)
6890 {
6891 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6892
6893 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6894 AssertPtrReturnVoid(paNewPage64);
6895
6896 uint32_t idxPage = 0;
6897 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6898 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6899 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6900 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6901 RT_UNTRUSTED_VALIDATED_FENCE();
6902 }
6903
6904 /* Free the old GMR if present. */
6905 if (pGMR->paDesc)
6906 RTMemFree(pGMR->paDesc);
6907
6908 /* Allocate the maximum amount possible (everything non-continuous) */
6909 PVMSVGAGMRDESCRIPTOR paDescs;
6910 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6911 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6912
6913 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6914 {
6915 /** @todo */
6916 AssertFailed();
6917 pGMR->numDescriptors = 0;
6918 }
6919 else
6920 {
6921 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6922 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6923 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6924
6925 uint32_t cPages;
6926 if (paNewPage64)
6927 {
6928 /* Overwrite the old page array with the new page values. */
6929 if (fGCPhys64)
6930 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6931 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6932 else
6933 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6934 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6935
6936 /* Use the updated page array instead of the command data. */
6937 fGCPhys64 = true;
6938 paPages64 = paNewPage64;
6939 cPages = cNewTotalPages;
6940 }
6941 else
6942 cPages = pCmd->numPages;
6943
6944 /* The first page. */
6945 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6946 * applied to paNewPage64. */
6947 RTGCPHYS GCPhys;
6948 if (fGCPhys64)
6949 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6950 else
6951 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6952 paDescs[0].GCPhys = GCPhys;
6953 paDescs[0].numPages = 1;
6954
6955 /* Subsequent pages. */
6956 uint32_t iDescriptor = 0;
6957 for (uint32_t i = 1; i < cPages; i++)
6958 {
6959 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6960 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6961 else
6962 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6963
6964 /* Continuous physical memory? */
6965 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6966 {
6967 Assert(paDescs[iDescriptor].numPages);
6968 paDescs[iDescriptor].numPages++;
6969 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6970 }
6971 else
6972 {
6973 iDescriptor++;
6974 paDescs[iDescriptor].GCPhys = GCPhys;
6975 paDescs[iDescriptor].numPages = 1;
6976 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6977 }
6978 }
6979
6980 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6981 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6982 pGMR->numDescriptors = iDescriptor + 1;
6983 }
6984
6985 if (paNewPage64)
6986 RTMemFree(paNewPage64);
6987}
6988
6989
6990/**
6991 * Free the specified GMR
6992 *
6993 * @param pThisCC The VGA/VMSVGA state for ring-3.
6994 * @param idGMR GMR id
6995 */
6996void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6997{
6998 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6999
7000 /* Free the old descriptor if present. */
7001 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7002 if ( pGMR->numDescriptors
7003 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7004 {
7005# ifdef DEBUG_GMR_ACCESS
7006 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7007# endif
7008
7009 Assert(pGMR->paDesc);
7010 RTMemFree(pGMR->paDesc);
7011 pGMR->paDesc = NULL;
7012 pGMR->numDescriptors = 0;
7013 pGMR->cbTotal = 0;
7014 pGMR->cMaxPages = 0;
7015 }
7016 Assert(!pGMR->cMaxPages);
7017 Assert(!pGMR->cbTotal);
7018}
7019#endif /* VBOX_WITH_VMSVGA3D */
7020
7021
7022/**
7023 * Copy between a GMR and a host memory buffer.
7024 *
7025 * @returns VBox status code.
7026 * @param pThis The shared VGA/VMSVGA instance data.
7027 * @param pThisCC The VGA/VMSVGA state for ring-3.
7028 * @param enmTransferType Transfer type (read/write)
7029 * @param pbHstBuf Host buffer pointer (valid)
7030 * @param cbHstBuf Size of host buffer (valid)
7031 * @param offHst Host buffer offset of the first scanline
7032 * @param cbHstPitch Destination buffer pitch
7033 * @param gstPtr GMR description
7034 * @param offGst Guest buffer offset of the first scanline
7035 * @param cbGstPitch Guest buffer pitch
7036 * @param cbWidth Width in bytes to copy
7037 * @param cHeight Number of scanllines to copy
7038 */
7039int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7040 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7041 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7042 uint32_t cbWidth, uint32_t cHeight)
7043{
7044 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7045 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7046 int rc;
7047
7048 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7049 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7050 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7051 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7052 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7053
7054 PGMR pGMR;
7055 uint32_t cbGmr; /* The GMR size in bytes. */
7056 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7057 {
7058 pGMR = NULL;
7059 cbGmr = pThis->vram_size;
7060 }
7061 else
7062 {
7063 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7064 RT_UNTRUSTED_VALIDATED_FENCE();
7065 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7066 cbGmr = pGMR->cbTotal;
7067 }
7068
7069 /*
7070 * GMR
7071 */
7072 /* Calculate GMR offset of the data to be copied. */
7073 AssertMsgReturn(gstPtr.offset < cbGmr,
7074 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7075 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7076 VERR_INVALID_PARAMETER);
7077 RT_UNTRUSTED_VALIDATED_FENCE();
7078 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7079 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7080 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7081 VERR_INVALID_PARAMETER);
7082 RT_UNTRUSTED_VALIDATED_FENCE();
7083 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7084
7085 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7086 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7087 AssertMsgReturn(cbGmrScanline != 0,
7088 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7089 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7090 VERR_INVALID_PARAMETER);
7091 RT_UNTRUSTED_VALIDATED_FENCE();
7092 AssertMsgReturn(cbWidth <= cbGmrScanline,
7093 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7094 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7095 VERR_INVALID_PARAMETER);
7096 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7097 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7098 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7099 VERR_INVALID_PARAMETER);
7100 RT_UNTRUSTED_VALIDATED_FENCE();
7101
7102 /* How many bytes are available for the data in the GMR. */
7103 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7104
7105 /* How many scanlines would fit into the available data. */
7106 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7107 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7108 if (cbWidth <= cbGmrLastScanline)
7109 ++cGmrScanlines;
7110
7111 if (cHeight > cGmrScanlines)
7112 cHeight = cGmrScanlines;
7113
7114 AssertMsgReturn(cHeight > 0,
7115 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7116 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7117 VERR_INVALID_PARAMETER);
7118 RT_UNTRUSTED_VALIDATED_FENCE();
7119
7120 /*
7121 * Host buffer.
7122 */
7123 AssertMsgReturn(offHst < cbHstBuf,
7124 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7125 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7126 VERR_INVALID_PARAMETER);
7127
7128 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7129 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7130 AssertMsgReturn(cbHstScanline != 0,
7131 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7132 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7133 VERR_INVALID_PARAMETER);
7134 AssertMsgReturn(cbWidth <= cbHstScanline,
7135 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7136 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7137 VERR_INVALID_PARAMETER);
7138 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7139 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7140 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7141 VERR_INVALID_PARAMETER);
7142
7143 /* How many bytes are available for the data in the buffer. */
7144 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7145
7146 /* How many scanlines would fit into the available data. */
7147 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7148 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7149 if (cbWidth <= cbHstLastScanline)
7150 ++cHstScanlines;
7151
7152 if (cHeight > cHstScanlines)
7153 cHeight = cHstScanlines;
7154
7155 AssertMsgReturn(cHeight > 0,
7156 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7157 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7158 VERR_INVALID_PARAMETER);
7159
7160 uint8_t *pbHst = pbHstBuf + offHst;
7161
7162 /* Shortcut for the framebuffer. */
7163 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7164 {
7165 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7166
7167 uint8_t const *pbSrc;
7168 int32_t cbSrcPitch;
7169 uint8_t *pbDst;
7170 int32_t cbDstPitch;
7171
7172 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7173 {
7174 pbSrc = pbHst;
7175 cbSrcPitch = cbHstPitch;
7176 pbDst = pbGst;
7177 cbDstPitch = cbGstPitch;
7178 }
7179 else
7180 {
7181 pbSrc = pbGst;
7182 cbSrcPitch = cbGstPitch;
7183 pbDst = pbHst;
7184 cbDstPitch = cbHstPitch;
7185 }
7186
7187 if ( cbWidth == (uint32_t)cbGstPitch
7188 && cbGstPitch == cbHstPitch)
7189 {
7190 /* Entire scanlines, positive pitch. */
7191 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7192 }
7193 else
7194 {
7195 for (uint32_t i = 0; i < cHeight; ++i)
7196 {
7197 memcpy(pbDst, pbSrc, cbWidth);
7198
7199 pbDst += cbDstPitch;
7200 pbSrc += cbSrcPitch;
7201 }
7202 }
7203 return VINF_SUCCESS;
7204 }
7205
7206 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7207 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7208
7209 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7210 uint32_t iDesc = 0; /* Index in the descriptor array. */
7211 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7212 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7213 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7214 for (uint32_t i = 0; i < cHeight; ++i)
7215 {
7216 uint32_t cbCurrentWidth = cbWidth;
7217 uint32_t offGmrCurrent = offGmrScanline;
7218 uint8_t *pbCurrentHost = pbHstScanline;
7219
7220 /* Find the right descriptor */
7221 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
7222 {
7223 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7224 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7225 ++iDesc;
7226 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7227 }
7228
7229 while (cbCurrentWidth)
7230 {
7231 uint32_t cbToCopy;
7232
7233 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
7234 {
7235 cbToCopy = cbCurrentWidth;
7236 }
7237 else
7238 {
7239 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
7240 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7241 }
7242
7243 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7244
7245 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7246
7247 /*
7248 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7249 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7250 * see @bugref{9654#c75}.
7251 */
7252 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7253 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7254 else
7255 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7256 AssertRCBreak(rc);
7257
7258 cbCurrentWidth -= cbToCopy;
7259 offGmrCurrent += cbToCopy;
7260 pbCurrentHost += cbToCopy;
7261
7262 /* Go to the next descriptor if there's anything left. */
7263 if (cbCurrentWidth)
7264 {
7265 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
7266 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7267 ++iDesc;
7268 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7269 }
7270 }
7271
7272 offGmrScanline += cbGstPitch;
7273 pbHstScanline += cbHstPitch;
7274 }
7275
7276 return VINF_SUCCESS;
7277}
7278
7279
7280/**
7281 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7282 *
7283 * @param pSizeSrc Source surface dimensions.
7284 * @param pSizeDest Destination surface dimensions.
7285 * @param pBox Coordinates to be clipped.
7286 */
7287void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7288{
7289 /* Src x, w */
7290 if (pBox->srcx > pSizeSrc->width)
7291 pBox->srcx = pSizeSrc->width;
7292 if (pBox->w > pSizeSrc->width - pBox->srcx)
7293 pBox->w = pSizeSrc->width - pBox->srcx;
7294
7295 /* Src y, h */
7296 if (pBox->srcy > pSizeSrc->height)
7297 pBox->srcy = pSizeSrc->height;
7298 if (pBox->h > pSizeSrc->height - pBox->srcy)
7299 pBox->h = pSizeSrc->height - pBox->srcy;
7300
7301 /* Src z, d */
7302 if (pBox->srcz > pSizeSrc->depth)
7303 pBox->srcz = pSizeSrc->depth;
7304 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7305 pBox->d = pSizeSrc->depth - pBox->srcz;
7306
7307 /* Dest x, w */
7308 if (pBox->x > pSizeDest->width)
7309 pBox->x = pSizeDest->width;
7310 if (pBox->w > pSizeDest->width - pBox->x)
7311 pBox->w = pSizeDest->width - pBox->x;
7312
7313 /* Dest y, h */
7314 if (pBox->y > pSizeDest->height)
7315 pBox->y = pSizeDest->height;
7316 if (pBox->h > pSizeDest->height - pBox->y)
7317 pBox->h = pSizeDest->height - pBox->y;
7318
7319 /* Dest z, d */
7320 if (pBox->z > pSizeDest->depth)
7321 pBox->z = pSizeDest->depth;
7322 if (pBox->d > pSizeDest->depth - pBox->z)
7323 pBox->d = pSizeDest->depth - pBox->z;
7324}
7325
7326
7327/**
7328 * Unsigned coordinates in pBox. Clip to [0; pSize).
7329 *
7330 * @param pSize Source surface dimensions.
7331 * @param pBox Coordinates to be clipped.
7332 */
7333void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7334{
7335 /* x, w */
7336 if (pBox->x > pSize->width)
7337 pBox->x = pSize->width;
7338 if (pBox->w > pSize->width - pBox->x)
7339 pBox->w = pSize->width - pBox->x;
7340
7341 /* y, h */
7342 if (pBox->y > pSize->height)
7343 pBox->y = pSize->height;
7344 if (pBox->h > pSize->height - pBox->y)
7345 pBox->h = pSize->height - pBox->y;
7346
7347 /* z, d */
7348 if (pBox->z > pSize->depth)
7349 pBox->z = pSize->depth;
7350 if (pBox->d > pSize->depth - pBox->z)
7351 pBox->d = pSize->depth - pBox->z;
7352}
7353
7354
7355/**
7356 * Clip.
7357 *
7358 * @param pBound Bounding rectangle.
7359 * @param pRect Rectangle to be clipped.
7360 */
7361void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7362{
7363 int32_t left;
7364 int32_t top;
7365 int32_t right;
7366 int32_t bottom;
7367
7368 /* Right order. */
7369 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7370 if (pRect->left < pRect->right)
7371 {
7372 left = pRect->left;
7373 right = pRect->right;
7374 }
7375 else
7376 {
7377 left = pRect->right;
7378 right = pRect->left;
7379 }
7380 if (pRect->top < pRect->bottom)
7381 {
7382 top = pRect->top;
7383 bottom = pRect->bottom;
7384 }
7385 else
7386 {
7387 top = pRect->bottom;
7388 bottom = pRect->top;
7389 }
7390
7391 if (left < pBound->left)
7392 left = pBound->left;
7393 if (right < pBound->left)
7394 right = pBound->left;
7395
7396 if (left > pBound->right)
7397 left = pBound->right;
7398 if (right > pBound->right)
7399 right = pBound->right;
7400
7401 if (top < pBound->top)
7402 top = pBound->top;
7403 if (bottom < pBound->top)
7404 bottom = pBound->top;
7405
7406 if (top > pBound->bottom)
7407 top = pBound->bottom;
7408 if (bottom > pBound->bottom)
7409 bottom = pBound->bottom;
7410
7411 pRect->left = left;
7412 pRect->right = right;
7413 pRect->top = top;
7414 pRect->bottom = bottom;
7415}
7416
7417
7418/**
7419 * Clip.
7420 *
7421 * @param pBound Bounding rectangle.
7422 * @param pRect Rectangle to be clipped.
7423 */
7424void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7425{
7426 uint32_t const leftBound = pBound->x;
7427 uint32_t const rightBound = pBound->x + pBound->w;
7428 uint32_t const topBound = pBound->y;
7429 uint32_t const bottomBound = pBound->y + pBound->h;
7430
7431 uint32_t x = pRect->x;
7432 uint32_t y = pRect->y;
7433 uint32_t w = pRect->w;
7434 uint32_t h = pRect->h;
7435
7436 /* Make sure that right and bottom coordinates can be safely computed. */
7437 if (x > rightBound)
7438 x = rightBound;
7439 if (w > rightBound - x)
7440 w = rightBound - x;
7441 if (y > bottomBound)
7442 y = bottomBound;
7443 if (h > bottomBound - y)
7444 h = bottomBound - y;
7445
7446 /* Switch from x, y, w, h to left, top, right, bottom. */
7447 uint32_t left = x;
7448 uint32_t right = x + w;
7449 uint32_t top = y;
7450 uint32_t bottom = y + h;
7451
7452 /* A standard left, right, bottom, top clipping. */
7453 if (left < leftBound)
7454 left = leftBound;
7455 if (right < leftBound)
7456 right = leftBound;
7457
7458 if (left > rightBound)
7459 left = rightBound;
7460 if (right > rightBound)
7461 right = rightBound;
7462
7463 if (top < topBound)
7464 top = topBound;
7465 if (bottom < topBound)
7466 bottom = topBound;
7467
7468 if (top > bottomBound)
7469 top = bottomBound;
7470 if (bottom > bottomBound)
7471 bottom = bottomBound;
7472
7473 /* Back to x, y, w, h representation. */
7474 pRect->x = left;
7475 pRect->y = top;
7476 pRect->w = right - left;
7477 pRect->h = bottom - top;
7478}
7479
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