VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 94205

Last change on this file since 94205 was 94205, checked in by vboxsync, 3 years ago

Devices/Graphics: saved state: bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 272.1 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 94205 2022-03-12 20:12:21Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#include <iprt/formats/bmp.h>
40#include <stdio.h>
41
42#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
43# define SVGA_CASE_ID2STR(idx) case idx: return #idx
44
45static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
46{
47 switch (enmCmdId)
48 {
49 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
50 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
290 }
291 return "UNKNOWN_3D";
292}
293
294/**
295 * FIFO command name lookup
296 *
297 * @returns FIFO command string or "UNKNOWN"
298 * @param u32Cmd FIFO command
299 */
300const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
301{
302 switch (u32Cmd)
303 {
304 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
305 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
306 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
307 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
309 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
310 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
311 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
314 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
315 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
316 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
317 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
318 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
320 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
323 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
324 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
325 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
327 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
328 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
329 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
330 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
331 default:
332 if ( u32Cmd >= SVGA_3D_CMD_BASE
333 && u32Cmd < SVGA_3D_CMD_MAX)
334 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
335 }
336 return "UNKNOWN";
337}
338# undef SVGA_CASE_ID2STR
339#endif /* LOG_ENABLED || VBOX_STRICT */
340
341
342/*
343 *
344 * Guest-Backed Objects (GBO).
345 *
346 */
347
348/**
349 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
350 *
351 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
352 * @param pVM VM Handle.
353 * @param pVCpu The cross context CPU structure for the calling EMT.
354 * @param GCPhys The physical address the guest is writing to.
355 * @param pvPhys The HC mapping of that address.
356 * @param pvBuf What the guest is reading/writing.
357 * @param cbBuf How much it's reading/writing.
358 * @param enmAccessType The access type.
359 * @param enmOrigin Who is making the access.
360 * @param uUser The VMM automatically sets this to the address of
361 * the device instance.
362 */
363DECLCALLBACK(VBOXSTRICTRC)
364vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
365 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, uint64_t uUser)
366{
367 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
368
369 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
370 return VINF_PGM_HANDLER_DO_DEFAULT;
371
372 PPDMDEVINS pDevIns = (PPDMDEVINS)uUser;
373 AssertPtrReturn(pDevIns, VERR_INTERNAL_ERROR_4);
374 AssertReturn(pDevIns->u32Version == PDM_DEVINSR3_VERSION, VERR_INTERNAL_ERROR_5);
375 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
376 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
377 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
378
379 /*
380 * The guest is not allowed to access the memory.
381 * Set the error condition.
382 */
383 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
384
385 /* Try to find the GBO which the guest is accessing. */
386 char const *pszTarget = NULL;
387 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
388 {
389 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
390 if (pGbo->cDescriptors)
391 {
392 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
393 {
394 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
395 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * GUEST_PAGE_SIZE)
396 {
397 switch (i)
398 {
399 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
400 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
401 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
402 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
403 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
404 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
405 default: pszTarget = "Unknown OTABLE"; break;
406 }
407 break;
408 }
409 }
410 }
411 }
412
413 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
414 "%.*Rhxd\n",
415 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
416
417 return VINF_PGM_HANDLER_DO_DEFAULT;
418}
419
420#ifdef VBOX_WITH_VMSVGA3D
421
422static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
423{
424 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
425
426 /*
427 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
428 * Content of the root page depends on the ptDepth value:
429 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
430 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
431 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
432 * The code below extracts the page addresses of the GBO.
433 */
434
435 /* Verify and normalize the ptDepth value. */
436 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
437 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
438 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
439 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
440 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
441 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
442 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
443 {
444 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
445 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
446 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
447 }
448 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
449 { }
450 else
451 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
452
453 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
454
455 pGbo->cbTotal = sizeInBytes;
456 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
457
458 /* Allocate the maximum amount possible (everything non-continuous) */
459 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
460 AssertReturn(paDescriptors, VERR_NO_MEMORY);
461
462 int rc = VINF_SUCCESS;
463 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
464 {
465 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
466 RTMemFree(paDescriptors),
467 VERR_INVALID_PARAMETER);
468
469 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
470 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
471 paDescriptors[0].GCPhys = GCPhys;
472 paDescriptors[0].cPages = 1;
473 }
474 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
475 {
476 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
477 RTMemFree(paDescriptors),
478 VERR_INVALID_PARAMETER);
479
480 /* Read the root page. */
481 uint8_t au8RootPage[X86_PAGE_SIZE];
482 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
483 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
484 if (RT_SUCCESS(rc))
485 {
486 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
487 PPN *paPPN32 = (PPN *)&au8RootPage[0];
488 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
489 {
490 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
491 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
492 paDescriptors[iPPN].GCPhys = GCPhys;
493 paDescriptors[iPPN].cPages = 1;
494 }
495 }
496 }
497 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
498 {
499 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
500 RTMemFree(paDescriptors),
501 VERR_INVALID_PARAMETER);
502
503 /* Read the Level2 root page. */
504 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
505 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
506 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
507 if (RT_SUCCESS(rc))
508 {
509 uint32_t cPagesLeft = pGbo->cTotalPages;
510
511 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
512 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
513
514 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
515 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
516 {
517 /* Read the Level1 root page. */
518 uint8_t au8RootPage[X86_PAGE_SIZE];
519 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
520 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
521 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
522 if (RT_SUCCESS(rc))
523 {
524 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
525 PPN *paPPN32 = (PPN *)&au8RootPage[0];
526
527 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
528 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
529 {
530 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
531 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
532 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
533 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
534 }
535 cPagesLeft -= cPPNs;
536 }
537 }
538 }
539 }
540 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
541 {
542 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
543 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
544 paDescriptors[0].GCPhys = GCPhys;
545 paDescriptors[0].cPages = pGbo->cTotalPages;
546 }
547 else
548 {
549 AssertFailed();
550 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
551 }
552
553 /* Compress the descriptors. */
554 if (ptDepth != SVGA3D_MOBFMT_RANGE)
555 {
556 uint32_t iDescriptor = 0;
557 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
558 {
559 /* Continuous physical memory? */
560 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
561 {
562 Assert(paDescriptors[iDescriptor].cPages);
563 paDescriptors[iDescriptor].cPages++;
564 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
565 }
566 else
567 {
568 iDescriptor++;
569 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
570 paDescriptors[iDescriptor].cPages = 1;
571 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
572 }
573 }
574
575 pGbo->cDescriptors = iDescriptor + 1;
576 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
577 }
578 else
579 pGbo->cDescriptors = 1;
580
581 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
582 {
583 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
584 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
585 }
586 else
587 pGbo->paDescriptors = paDescriptors;
588
589#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
590fWriteProtected = false;
591#endif
592 if (fWriteProtected)
593 {
594 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
595 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
596 {
597 rc = PDMDevHlpPGMHandlerPhysicalRegister(pSvgaR3State->pDevIns,
598 pGbo->paDescriptors[i].GCPhys,
599 pGbo->paDescriptors[i].GCPhys
600 + pGbo->paDescriptors[i].cPages * GUEST_PAGE_SIZE - 1,
601 pSvgaR3State->hGboAccessHandlerType, "VMSVGA GBO");
602 AssertRC(rc);
603 }
604 }
605
606 return VINF_SUCCESS;
607}
608
609
610static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
611{
612 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
613 {
614 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
615 {
616 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
617 {
618 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pSvgaR3State->pDevIns, pGbo->paDescriptors[i].GCPhys);
619 AssertRC(rc);
620 }
621 }
622 RTMemFree(pGbo->paDescriptors);
623 RT_ZERO(pGbo);
624 }
625}
626
627/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
628
629typedef enum VMSVGAGboTransferDirection
630{
631 VMSVGAGboTransferDirection_Read,
632 VMSVGAGboTransferDirection_Write,
633} VMSVGAGboTransferDirection;
634
635static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
636 uint32_t off, void *pvData, uint32_t cbData,
637 VMSVGAGboTransferDirection enmDirection)
638{
639 //DEBUG_BREAKPOINT_TEST();
640 int rc = VINF_SUCCESS;
641 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
642
643 /* Find the right descriptor */
644 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
645 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
646 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
647 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
648 {
649 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
650 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
651 ++iDescriptor;
652 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
653 }
654
655 while (cbData)
656 {
657 uint32_t cbToCopy;
658 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
659 cbToCopy = cbData;
660 else
661 {
662 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
663 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
664 }
665
666 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
667 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
668
669 /*
670 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
671 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
672 * see @bugref{9654#c75}.
673 */
674 if (enmDirection == VMSVGAGboTransferDirection_Read)
675 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
676 else
677 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
678 AssertRCBreak(rc);
679
680 cbData -= cbToCopy;
681 off += cbToCopy;
682 pu8CurrentHost += cbToCopy;
683
684 /* Go to the next descriptor if there's anything left. */
685 if (cbData)
686 {
687 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
688 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
689 ++iDescriptor;
690 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
691 }
692 }
693 return rc;
694}
695
696
697static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
698 uint32_t off, void const *pvData, uint32_t cbData)
699{
700 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
701 off, (void *)pvData, cbData,
702 VMSVGAGboTransferDirection_Write);
703}
704
705
706static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
707 uint32_t off, void *pvData, uint32_t cbData)
708{
709 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
710 off, pvData, cbData,
711 VMSVGAGboTransferDirection_Read);
712}
713
714
715static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
716{
717 int rc;
718
719 /* Just reread the data if pvHost has been allocated already. */
720 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
721 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
722
723 if (pGbo->pvHost)
724 {
725 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
726 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
727 }
728 else
729 rc = VERR_NO_MEMORY;
730
731 if (RT_SUCCESS(rc))
732 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
733 else
734 {
735 RTMemFree(pGbo->pvHost);
736 pGbo->pvHost = NULL;
737 }
738 return rc;
739}
740
741
742static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
743{
744 RT_NOREF(pSvgaR3State);
745 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
746 RTMemFree(pGbo->pvHost);
747 pGbo->pvHost = NULL;
748 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
749}
750
751
752static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
753{
754 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
755 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
756}
757
758
759static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
760{
761 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
762 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
763}
764
765
766
767/*
768 *
769 * Object Tables.
770 *
771 */
772
773static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
774 uint32_t idx, uint32_t cbEntry)
775{
776 RT_NOREF(pSvgaR3State);
777
778 /* The table must exist and the index must be within the table. */
779 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
780 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
781 RT_UNTRUSTED_VALIDATED_FENCE();
782 return VINF_SUCCESS;
783}
784
785
786static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
787 uint32_t idx, uint32_t cbEntry,
788 void *pvData, uint32_t cbData)
789{
790 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
791
792 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
793 if (RT_SUCCESS(rc))
794 {
795 uint32_t const off = idx * cbEntry;
796 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
797 }
798 return rc;
799}
800
801static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
802 uint32_t idx, uint32_t cbEntry,
803 void const *pvData, uint32_t cbData)
804{
805 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
806
807 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
808 if (RT_SUCCESS(rc))
809 {
810 uint32_t const off = idx * cbEntry;
811 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
812 }
813 return rc;
814}
815
816
817int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
818{
819 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
820 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
821}
822
823
824/*
825 *
826 * The guest's Memory OBjects (MOB).
827 *
828 */
829
830static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
831 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
832 bool fGCPhys64, PVMSVGAMOB pMob)
833{
834 RT_ZERO(*pMob);
835
836 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
837 SVGAOTableMobEntry entry;
838 entry.ptDepth = ptDepth;
839 entry.sizeInBytes = sizeInBytes;
840 entry.base = baseAddress;
841 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
842 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
843 if (RT_SUCCESS(rc))
844 {
845 /* Create the corresponding GBO. */
846 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
847 if (RT_SUCCESS(rc))
848 {
849 /* Add to the tree of known GBOs and the LRU list. */
850 pMob->Core.Key = mobid;
851 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
852 {
853 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
854 return VINF_SUCCESS;
855 }
856
857 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
858 }
859 }
860
861 return rc;
862}
863
864
865static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
866{
867 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
868 SVGAOTableMobEntry entry;
869 RT_ZERO(entry);
870 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
871 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
872
873 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
874 if (pMob)
875 {
876 RTListNodeRemove(&pMob->nodeLRU);
877 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
878 RTMemFree(pMob);
879 return VINF_SUCCESS;
880 }
881
882 return VERR_INVALID_PARAMETER;
883}
884
885
886PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
887{
888 if (mobid == SVGA_ID_INVALID)
889 return NULL;
890
891 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
892 if (pMob)
893 {
894 /* Move to the head of the LRU list. */
895 RTListNodeRemove(&pMob->nodeLRU);
896 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
897 }
898 else
899 ASSERT_GUEST_FAILED();
900
901 return pMob;
902}
903
904
905/** Create a host ring-3 pointer to the MOB data.
906 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
907 * @param pSvgaR3State R3 device state.
908 * @param pMob The MOB.
909 * @param cbValid How many bytes of the guest backing memory contain valid data.
910 * @return VBox status.
911 */
912/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
913int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
914{
915 AssertReturn(pMob, VERR_INVALID_PARAMETER);
916 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
917}
918
919
920void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
921{
922 if (pMob)
923 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
924}
925
926
927int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
928{
929 if (pMob)
930 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
931 return VERR_INVALID_PARAMETER;
932}
933
934
935int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
936{
937 if (pMob)
938 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
939 return VERR_INVALID_PARAMETER;
940}
941
942
943void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
944{
945 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
946 {
947 if (off <= pMob->Gbo.cbTotal)
948 return (uint8_t *)pMob->Gbo.pvHost + off;
949 }
950 return NULL;
951}
952
953
954int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
955{
956 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
957
958 SVGAOTableSurfaceEntry entrySurface;
959 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
960 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
961 if (RT_SUCCESS(rc))
962 {
963 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
964 if (pMob)
965 {
966 VMSVGA3D_MAPPED_SURFACE map;
967 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE, &map);
968 if (RT_SUCCESS(rc))
969 {
970 /* Copy MOB -> mapped surface. */
971 uint32_t offSrc = pBox->x * map.cbPixel
972 + pBox->y * entrySurface.size.width * map.cbPixel
973 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
974 uint8_t *pu8Dst = (uint8_t *)map.pvData;
975 for (uint32_t z = 0; z < pBox->d; ++z)
976 {
977 for (uint32_t y = 0; y < pBox->h; ++y)
978 {
979 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
980 if (RT_FAILURE(rc))
981 break;
982
983 pu8Dst += map.cbRowPitch;
984 offSrc += entrySurface.size.width * map.cbPixel;
985 }
986
987 pu8Dst += map.cbDepthPitch;
988 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
989 }
990
991 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
992 }
993 }
994 else
995 rc = VERR_INVALID_STATE;
996 }
997
998 return rc;
999}
1000
1001
1002int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
1003{
1004 /* pPtSrc must be verified by the caller. */
1005 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1006
1007 SVGAOTableSurfaceEntry entrySurface;
1008 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1009 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1010 if (RT_SUCCESS(rc))
1011 {
1012 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1013 if (pMob)
1014 {
1015 VMSVGA3D_MAPPED_SURFACE map;
1016 rc = vmsvga3dSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE, &map);
1017 if (RT_SUCCESS(rc))
1018 {
1019 /* Copy MOB -> mapped surface. */
1020 uint32_t offSrc = pPtSrc->x * map.cbPixel
1021 + pPtSrc->y * entrySurface.size.width * map.cbPixel
1022 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1023 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1024 for (uint32_t z = 0; z < pBoxDst->d; ++z)
1025 {
1026 for (uint32_t y = 0; y < pBoxDst->h; ++y)
1027 {
1028 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
1029 if (RT_FAILURE(rc))
1030 break;
1031
1032 pu8Dst += map.cbRowPitch;
1033 offSrc += entrySurface.size.width * map.cbPixel;
1034 }
1035
1036 pu8Dst += map.cbDepthPitch;
1037 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1038 }
1039
1040 vmsvga3dSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
1041 }
1042 }
1043 else
1044 rc = VERR_INVALID_STATE;
1045 }
1046
1047 return rc;
1048}
1049
1050#endif /* VBOX_WITH_VMSVGA3D */
1051
1052/*
1053 * Screen objects.
1054 */
1055VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1056{
1057 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1058 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1059 && pSVGAState
1060 && pSVGAState->aScreens[idScreen].fDefined)
1061 {
1062 return &pSVGAState->aScreens[idScreen];
1063 }
1064 return NULL;
1065}
1066
1067void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1068{
1069#ifdef VBOX_WITH_VMSVGA3D
1070 if (pThis->svga.f3DEnabled)
1071 {
1072 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1073 {
1074 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1075 if (pScreen)
1076 vmsvga3dDestroyScreen(pThisCC, pScreen);
1077 }
1078 }
1079#else
1080 RT_NOREF(pThis, pThisCC);
1081#endif
1082}
1083
1084
1085/**
1086 * Copy a rectangle of pixels within guest VRAM.
1087 */
1088static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1089 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1090{
1091 if (!width || !height)
1092 return; /* Nothing to do, don't even bother. */
1093
1094 /*
1095 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1096 * corresponding to the current display mode.
1097 */
1098 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1099 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1100 uint8_t const *pSrc;
1101 uint8_t *pDst;
1102 unsigned const cbRectWidth = width * cbPixel;
1103 unsigned uMaxOffset;
1104
1105 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1106 if (uMaxOffset >= cbFrameBuffer)
1107 {
1108 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1109 return; /* Just don't listen to a bad guest. */
1110 }
1111
1112 pSrc = pDst = pThisCC->pbVRam;
1113 pSrc += srcY * cbScanline + srcX * cbPixel;
1114 pDst += dstY * cbScanline + dstX * cbPixel;
1115
1116 if (srcY >= dstY)
1117 {
1118 /* Source below destination, copy top to bottom. */
1119 for (; height > 0; height--)
1120 {
1121 memmove(pDst, pSrc, cbRectWidth);
1122 pSrc += cbScanline;
1123 pDst += cbScanline;
1124 }
1125 }
1126 else
1127 {
1128 /* Source above destination, copy bottom to top. */
1129 pSrc += cbScanline * (height - 1);
1130 pDst += cbScanline * (height - 1);
1131 for (; height > 0; height--)
1132 {
1133 memmove(pDst, pSrc, cbRectWidth);
1134 pSrc -= cbScanline;
1135 pDst -= cbScanline;
1136 }
1137 }
1138}
1139
1140
1141/**
1142 * Common worker for changing the pointer shape.
1143 *
1144 * @param pThisCC The VGA/VMSVGA state for ring-3.
1145 * @param pSVGAState The VMSVGA ring-3 instance data.
1146 * @param fAlpha Whether there is alpha or not.
1147 * @param xHot Hotspot x coordinate.
1148 * @param yHot Hotspot y coordinate.
1149 * @param cx Width.
1150 * @param cy Height.
1151 * @param pbData Heap copy of the cursor data. Consumed.
1152 * @param cbData The size of the data.
1153 */
1154static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1155 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1156{
1157 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1158#ifdef LOG_ENABLED
1159 if (LogIs2Enabled())
1160 {
1161 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1162 if (!fAlpha)
1163 {
1164 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1165 for (uint32_t y = 0; y < cy; y++)
1166 {
1167 Log2(("%3u:", y));
1168 uint8_t const *pbLine = &pbData[y * cbAndLine];
1169 for (uint32_t x = 0; x < cx; x += 8)
1170 {
1171 uint8_t b = pbLine[x / 8];
1172 char szByte[12];
1173 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1174 szByte[1] = b & 0x40 ? '*' : ' ';
1175 szByte[2] = b & 0x20 ? '*' : ' ';
1176 szByte[3] = b & 0x10 ? '*' : ' ';
1177 szByte[4] = b & 0x08 ? '*' : ' ';
1178 szByte[5] = b & 0x04 ? '*' : ' ';
1179 szByte[6] = b & 0x02 ? '*' : ' ';
1180 szByte[7] = b & 0x01 ? '*' : ' ';
1181 szByte[8] = '\0';
1182 Log2(("%s", szByte));
1183 }
1184 Log2(("\n"));
1185 }
1186 }
1187
1188 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1189 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1190 for (uint32_t y = 0; y < cy; y++)
1191 {
1192 Log2(("%3u:", y));
1193 uint32_t const *pu32Line = &pu32Xor[y * cx];
1194 for (uint32_t x = 0; x < cx; x++)
1195 Log2((" %08x", pu32Line[x]));
1196 Log2(("\n"));
1197 }
1198 }
1199#endif
1200
1201 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1202 AssertRC(rc);
1203
1204 if (pSVGAState->Cursor.fActive)
1205 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1206
1207 pSVGAState->Cursor.fActive = true;
1208 pSVGAState->Cursor.xHotspot = xHot;
1209 pSVGAState->Cursor.yHotspot = yHot;
1210 pSVGAState->Cursor.width = cx;
1211 pSVGAState->Cursor.height = cy;
1212 pSVGAState->Cursor.cbData = cbData;
1213 pSVGAState->Cursor.pData = pbData;
1214}
1215
1216
1217#ifdef VBOX_WITH_VMSVGA3D
1218
1219/*
1220 * SVGA_3D_CMD_* handlers.
1221 */
1222
1223
1224/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1225 *
1226 * @param pThisCC The VGA/VMSVGA state for the current context.
1227 * @param pCmd The VMSVGA command.
1228 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1229 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1230 */
1231static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1232 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1233{
1234 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1235 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1236 RT_UNTRUSTED_VALIDATED_FENCE();
1237
1238 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1239 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1240 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1241 */
1242 uint32_t cRemainingMipLevels = cMipLevelSizes;
1243 uint32_t cFaces = 0;
1244 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1245 {
1246 if (pCmd->face[i].numMipLevels == 0)
1247 break;
1248
1249 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1250 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1251
1252 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1253 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1254 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1255
1256 ++cFaces;
1257 }
1258 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1259 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1260
1261 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1262 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1263
1264 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1265 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1266 RT_UNTRUSTED_VALIDATED_FENCE();
1267
1268 /* Verify paMipLevelSizes */
1269 uint32_t cWidth = paMipLevelSizes[0].width;
1270 uint32_t cHeight = paMipLevelSizes[0].height;
1271 uint32_t cDepth = paMipLevelSizes[0].depth;
1272 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1273 {
1274 cWidth >>= 1;
1275 if (cWidth == 0) cWidth = 1;
1276 cHeight >>= 1;
1277 if (cHeight == 0) cHeight = 1;
1278 cDepth >>= 1;
1279 if (cDepth == 0) cDepth = 1;
1280 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1281 {
1282 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1283 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1284 && cHeight == paMipLevelSizes[iMipLevelSize].height
1285 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1286 }
1287 }
1288 RT_UNTRUSTED_VALIDATED_FENCE();
1289
1290 /* Create the surface. */
1291 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1292 pCmd->multisampleCount, pCmd->autogenFilter,
1293 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* fAllocMipLevels = */ true);
1294}
1295
1296
1297/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1298static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1299{
1300 DEBUG_BREAKPOINT_TEST();
1301 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1302
1303 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1304
1305 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1306 /* Allocate a structure for the MOB. */
1307 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1308 AssertPtrReturnVoid(pMob);
1309
1310 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1311 if (RT_SUCCESS(rc))
1312 {
1313 return;
1314 }
1315
1316 AssertFailed();
1317
1318 RTMemFree(pMob);
1319}
1320
1321
1322/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1323static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1324{
1325 //DEBUG_BREAKPOINT_TEST();
1326 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1327
1328 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1329
1330 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1331 if (RT_SUCCESS(rc))
1332 {
1333 return;
1334 }
1335
1336 AssertFailed();
1337}
1338
1339
1340/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1341static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1342{
1343 //DEBUG_BREAKPOINT_TEST();
1344 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1345
1346 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1347 SVGAOTableSurfaceEntry entry;
1348 RT_ZERO(entry);
1349 entry.format = pCmd->format;
1350 entry.surface1Flags = pCmd->surfaceFlags;
1351 entry.numMipLevels = pCmd->numMipLevels;
1352 entry.multisampleCount = pCmd->multisampleCount;
1353 entry.autogenFilter = pCmd->autogenFilter;
1354 entry.size = pCmd->size;
1355 entry.mobid = SVGA_ID_INVALID;
1356 // entry.arraySize = 0;
1357 // entry.mobPitch = 0;
1358 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1359 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1360 if (RT_SUCCESS(rc))
1361 {
1362 /* Create the host surface. */
1363 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1364 pCmd->multisampleCount, pCmd->autogenFilter,
1365 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1366 }
1367}
1368
1369
1370/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1371static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1372{
1373 //DEBUG_BREAKPOINT_TEST();
1374 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1375
1376 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1377 SVGAOTableSurfaceEntry entry;
1378 RT_ZERO(entry);
1379 entry.mobid = SVGA_ID_INVALID;
1380 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1381 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1382
1383 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1384}
1385
1386
1387/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1388static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1389{
1390 //DEBUG_BREAKPOINT_TEST();
1391 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1392
1393 /* Assign the mobid to the surface. */
1394 int rc = VINF_SUCCESS;
1395 if (pCmd->mobid != SVGA_ID_INVALID)
1396 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1397 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1398 if (RT_SUCCESS(rc))
1399 {
1400 SVGAOTableSurfaceEntry entry;
1401 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1402 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1403 if (RT_SUCCESS(rc))
1404 {
1405 entry.mobid = pCmd->mobid;
1406 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1407 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1408 if (RT_SUCCESS(rc))
1409 {
1410 /* */
1411 }
1412 }
1413 }
1414}
1415
1416
1417static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1418{
1419 if (pMap->cbPixel != 4)
1420 return VERR_NOT_SUPPORTED;
1421
1422 int const w = pMap->box.w;
1423 int const h = pMap->box.h;
1424
1425 const int cbBitmap = w * h * 4;
1426
1427 FILE *f = fopen(pszFilename, "wb");
1428 if (!f)
1429 return VERR_FILE_NOT_FOUND;
1430
1431 {
1432 BMPFILEHDR fileHdr;
1433 RT_ZERO(fileHdr);
1434 fileHdr.uType = BMP_HDR_MAGIC;
1435 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1436 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1437
1438 BMPWIN3XINFOHDR coreHdr;
1439 RT_ZERO(coreHdr);
1440 coreHdr.cbSize = sizeof(coreHdr);
1441 coreHdr.uWidth = w;
1442 coreHdr.uHeight = -h;
1443 coreHdr.cPlanes = 1;
1444 coreHdr.cBits = 32;
1445 coreHdr.cbSizeImage = cbBitmap;
1446
1447 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1448 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1449 }
1450
1451 if (pMap->cbPixel == 4)
1452 {
1453 const uint8_t *s = (uint8_t *)pMap->pvData;
1454 for (int32_t y = 0; y < h; ++y)
1455 {
1456 fwrite(s, 1, w * pMap->cbPixel, f);
1457
1458 s += pMap->cbRowPitch;
1459 }
1460 }
1461
1462 fclose(f);
1463
1464 return VINF_SUCCESS;
1465}
1466
1467
1468void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1469{
1470 static int idxBitmap = 0;
1471 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1472 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1473 Log(("WriteBmpFile %s %Rrc\n", pszFilename, rc)); RT_NOREF(rc);
1474 RTStrFree(pszFilename);
1475}
1476
1477
1478static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1479 PVMSVGAMOB pMob,
1480 SVGA3dSurfaceImageId const *pImage,
1481 SVGA3dBox const *pBox,
1482 SVGA3dTransferType enmTransfer)
1483{
1484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1485
1486 VMSVGA3D_SURFACE_MAP enmMapType;
1487 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1488 enmMapType = pBox
1489 ? VMSVGA3D_SURFACE_MAP_WRITE
1490 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1491 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1492 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1493 else
1494 AssertFailedReturn(VERR_INVALID_PARAMETER);
1495
1496 VMSGA3D_BOX_DIMENSIONS dims;
1497 int rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1498 AssertRCReturn(rc, rc);
1499
1500 VMSVGA3D_MAPPED_SURFACE map;
1501 rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1502 if (RT_SUCCESS(rc))
1503 {
1504 /* Copy mapped surface <-> MOB. */
1505 uint8_t *pu8Map = (uint8_t *)map.pvData;
1506 uint32_t offMob = dims.offSubresource + dims.offBox;
1507 for (uint32_t z = 0; z < dims.cDepth; ++z)
1508 {
1509 for (uint32_t y = 0; y < dims.cyBlocks; ++y)
1510 {
1511 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1512 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1513 else
1514 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1515 AssertRCBreak(rc);
1516
1517 pu8Map += map.cbRowPitch;
1518 offMob += dims.cbPitch;
1519 }
1520 /** @todo Take into account map.cbDepthPitch */
1521 }
1522
1523 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1524
1525 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1526 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1527 }
1528
1529 return rc;
1530}
1531
1532
1533/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1534static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1535{
1536 //DEBUG_BREAKPOINT_TEST();
1537 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1538
1539 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1540 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1541
1542/*
1543 SVGA3dSurfaceFormat format;
1544 SVGA3dSurface1Flags surface1Flags;
1545 uint32 numMipLevels;
1546 uint32 multisampleCount;
1547 SVGA3dTextureFilter autogenFilter;
1548 SVGA3dSize size;
1549 SVGAMobId mobid;
1550 uint32 arraySize;
1551 uint32 mobPitch;
1552 SVGA3dSurface2Flags surface2Flags;
1553 uint8 multisamplePattern;
1554 uint8 qualityLevel;
1555 uint16 bufferByteStride;
1556 float minLOD;
1557*/
1558
1559 /* "update a surface from its backing MOB." */
1560 SVGAOTableSurfaceEntry entrySurface;
1561 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1562 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1563 if (RT_SUCCESS(rc))
1564 {
1565 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1566 if (pMob)
1567 {
1568 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1569 AssertRC(rc);
1570 }
1571 }
1572}
1573
1574
1575/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1576static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1577{
1578 //DEBUG_BREAKPOINT_TEST();
1579 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1580
1581 LogFlowFunc(("sid=%u\n",
1582 pCmd->sid));
1583
1584 /* "update a surface from its backing MOB." */
1585 SVGAOTableSurfaceEntry entrySurface;
1586 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1587 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1588 if (RT_SUCCESS(rc))
1589 {
1590 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1591 if (pMob)
1592 {
1593 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1594 ? SVGA3D_MAX_SURFACE_FACES
1595 : RT_MAX(entrySurface.arraySize, 1);
1596 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1597 {
1598 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1599 {
1600 SVGA3dSurfaceImageId image;
1601 image.sid = pCmd->sid;
1602 image.face = iArray;
1603 image.mipmap = iMipmap;
1604
1605 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1606 AssertRCBreak(rc);
1607 }
1608 }
1609 }
1610 }
1611}
1612
1613
1614/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1615static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1616{
1617 //DEBUG_BREAKPOINT_TEST();
1618 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1619
1620 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1621 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1622
1623 /* Read a surface to its backing MOB. */
1624 SVGAOTableSurfaceEntry entrySurface;
1625 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1626 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1627 if (RT_SUCCESS(rc))
1628 {
1629 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1630 if (pMob)
1631 {
1632 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1633 AssertRC(rc);
1634 }
1635 }
1636}
1637
1638
1639/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1640static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1641{
1642 //DEBUG_BREAKPOINT_TEST();
1643 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1644
1645 LogFlowFunc(("sid=%u\n",
1646 pCmd->sid));
1647
1648 /* Read a surface to its backing MOB. */
1649 SVGAOTableSurfaceEntry entrySurface;
1650 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1651 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1652 if (RT_SUCCESS(rc))
1653 {
1654 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1655 if (pMob)
1656 {
1657 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
1658 ? SVGA3D_MAX_SURFACE_FACES
1659 : RT_MAX(entrySurface.arraySize, 1);
1660 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1661 {
1662 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1663 {
1664 SVGA3dSurfaceImageId image;
1665 image.sid = pCmd->sid;
1666 image.face = iArray;
1667 image.mipmap = iMipmap;
1668
1669 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1670 AssertRCBreak(rc);
1671 }
1672 }
1673 }
1674 }
1675}
1676
1677
1678/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1679static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1680{
1681 //DEBUG_BREAKPOINT_TEST();
1682 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1683}
1684
1685
1686/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1687static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1688{
1689 //DEBUG_BREAKPOINT_TEST();
1690 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1691}
1692
1693
1694/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1695static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1696{
1697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1698
1699 /*
1700 * Create a GBO for the table.
1701 */
1702 PVMSVGAGBO pGbo;
1703 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1704 {
1705 RT_UNTRUSTED_VALIDATED_FENCE();
1706 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1707 }
1708 else
1709 {
1710 ASSERT_GUEST_FAILED();
1711 pGbo = NULL;
1712 }
1713
1714 if (pGbo)
1715 {
1716 /* Recreate. */
1717 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1718 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1719 AssertRC(rc);
1720 }
1721}
1722
1723
1724/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1725static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1726{
1727 //DEBUG_BREAKPOINT_TEST();
1728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1729
1730 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1731 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1732 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1733 RT_UNTRUSTED_VALIDATED_FENCE();
1734
1735 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1736 SVGAOTableScreenTargetEntry entry;
1737 RT_ZERO(entry);
1738 entry.image.sid = SVGA_ID_INVALID;
1739 // entry.image.face = 0;
1740 // entry.image.mipmap = 0;
1741 entry.width = pCmd->width;
1742 entry.height = pCmd->height;
1743 entry.xRoot = pCmd->xRoot;
1744 entry.yRoot = pCmd->yRoot;
1745 entry.flags = pCmd->flags;
1746 entry.dpi = pCmd->dpi;
1747
1748 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1749 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1750 if (RT_SUCCESS(rc))
1751 {
1752 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1753 /** @todo Generic screen object/target interface. */
1754 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1755 pScreen->fDefined = true;
1756 pScreen->fModified = true;
1757 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1758 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1759 pScreen->idScreen = pCmd->stid;
1760
1761 pScreen->xOrigin = pCmd->xRoot;
1762 pScreen->yOrigin = pCmd->yRoot;
1763 pScreen->cWidth = pCmd->width;
1764 pScreen->cHeight = pCmd->height;
1765 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1766 pScreen->cbPitch = pCmd->width * 4;
1767 pScreen->cBpp = 32;
1768
1769 if (RT_LIKELY(pThis->svga.f3DEnabled))
1770 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1771
1772 if (!pScreen->pHwScreen)
1773 {
1774 /* System memory buffer. */
1775 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1776 }
1777
1778 pThis->svga.fGFBRegisters = false;
1779 vmsvgaR3ChangeMode(pThis, pThisCC);
1780 }
1781}
1782
1783
1784/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1785static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1786{
1787 //DEBUG_BREAKPOINT_TEST();
1788 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1789
1790 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1791 RT_UNTRUSTED_VALIDATED_FENCE();
1792
1793 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1794 SVGAOTableScreenTargetEntry entry;
1795 RT_ZERO(entry);
1796 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1797 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1798 if (RT_SUCCESS(rc))
1799 {
1800 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1801 /** @todo Generic screen object/target interface. */
1802 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1803 pScreen->fModified = true;
1804 pScreen->fDefined = false;
1805 pScreen->idScreen = pCmd->stid;
1806
1807 if (RT_LIKELY(pThis->svga.f3DEnabled))
1808 vmsvga3dDestroyScreen(pThisCC, pScreen);
1809
1810 vmsvgaR3ChangeMode(pThis, pThisCC);
1811
1812 RTMemFree(pScreen->pvScreenBitmap);
1813 pScreen->pvScreenBitmap = NULL;
1814 }
1815}
1816
1817
1818/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1819static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1820{
1821 //DEBUG_BREAKPOINT_TEST();
1822 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1823
1824 /* "Binding a surface to a Screen Target the same as flipping" */
1825
1826 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1827 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1828 RT_UNTRUSTED_VALIDATED_FENCE();
1829
1830 /* Assign the surface to the screen target. */
1831 int rc = VINF_SUCCESS;
1832 if (pCmd->image.sid != SVGA_ID_INVALID)
1833 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1834 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1835 if (RT_SUCCESS(rc))
1836 {
1837 SVGAOTableScreenTargetEntry entry;
1838 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1839 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1840 if (RT_SUCCESS(rc))
1841 {
1842 entry.image = pCmd->image;
1843 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1844 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1845 if (RT_SUCCESS(rc))
1846 {
1847 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1848 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1849 AssertRC(rc);
1850 }
1851 }
1852 }
1853}
1854
1855
1856/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1857static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1858{
1859 //DEBUG_BREAKPOINT_TEST();
1860 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1861
1862 /* Update the screen target from its backing surface. */
1863 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1864 RT_UNTRUSTED_VALIDATED_FENCE();
1865
1866 /* Get the screen target info. */
1867 SVGAOTableScreenTargetEntry entryScreenTarget;
1868 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1869 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1870 if (RT_SUCCESS(rc))
1871 {
1872 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1873 RT_UNTRUSTED_VALIDATED_FENCE();
1874
1875 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1876 {
1877 SVGAOTableSurfaceEntry entrySurface;
1878 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1879 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1880 if (RT_SUCCESS(rc))
1881 {
1882 /* Copy entrySurface.mobid content to the screen target. */
1883 if (entrySurface.mobid != SVGA_ID_INVALID)
1884 {
1885 RT_UNTRUSTED_VALIDATED_FENCE();
1886 SVGA3dRect targetRect = pCmd->rect;
1887
1888 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1889 if (pScreen->pHwScreen)
1890 {
1891 /* Copy the screen target surface to the backend's screen. */
1892 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1893 }
1894 else if (pScreen->pvScreenBitmap)
1895 {
1896 /* Copy the screen target surface to the memory buffer. */
1897 VMSVGA3D_MAPPED_SURFACE map;
1898 rc = vmsvga3dSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1899 if (RT_SUCCESS(rc))
1900 {
1901 uint8_t const *pu8Src = (uint8_t *)map.pvData
1902 + targetRect.x * map.cbPixel
1903 + targetRect.y * map.cbRowPitch;
1904 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1905 + targetRect.x * map.cbPixel
1906 + targetRect.y * map.box.w * map.cbPixel;
1907 for (uint32_t y = 0; y < targetRect.h; ++y)
1908 {
1909 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1910
1911 pu8Src += map.cbRowPitch;
1912 pu8Dst += map.box.w * map.cbPixel;
1913 }
1914
1915 vmsvga3dSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1916
1917 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1918 }
1919 else
1920 AssertFailed();
1921 }
1922 }
1923 }
1924 }
1925 }
1926}
1927
1928
1929/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1930static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1931{
1932 //DEBUG_BREAKPOINT_TEST();
1933 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1934
1935 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1936 SVGAOTableSurfaceEntry entry;
1937 RT_ZERO(entry);
1938 entry.format = pCmd->format;
1939 entry.surface1Flags = pCmd->surfaceFlags;
1940 entry.numMipLevels = pCmd->numMipLevels;
1941 entry.multisampleCount = pCmd->multisampleCount;
1942 entry.autogenFilter = pCmd->autogenFilter;
1943 entry.size = pCmd->size;
1944 entry.mobid = SVGA_ID_INVALID;
1945 entry.arraySize = pCmd->arraySize;
1946 // entry.mobPitch = 0;
1947 // ...
1948Assert( pCmd->arraySize == 0
1949 || pCmd->arraySize == 1
1950 || (pCmd->arraySize == 6 && (pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP)));
1951 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1952 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1953 if (RT_SUCCESS(rc))
1954 {
1955 /* Create the host surface. */
1956 /** @todo SVGAOTableSurfaceEntry as input parameter? */
1957 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1958 pCmd->multisampleCount, pCmd->autogenFilter,
1959 pCmd->numMipLevels, &pCmd->size, /* fAllocMipLevels = */ false);
1960 }
1961}
1962
1963
1964/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1965static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1966{
1967 //DEBUG_BREAKPOINT_TEST();
1968 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1969
1970 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1971
1972 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1973 /* Allocate a structure for the MOB. */
1974 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1975 AssertPtrReturnVoid(pMob);
1976
1977 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1978 if (RT_SUCCESS(rc))
1979 {
1980 return;
1981 }
1982
1983 RTMemFree(pMob);
1984}
1985
1986
1987/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1988static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1989{
1990#ifdef VMSVGA3D_DX
1991 //DEBUG_BREAKPOINT_TEST();
1992 RT_NOREF(cbCmd);
1993
1994 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1995
1996 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1997 SVGAOTableDXContextEntry entry;
1998 RT_ZERO(entry);
1999 entry.cid = pCmd->cid;
2000 entry.mobid = SVGA_ID_INVALID;
2001 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2002 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2003 if (RT_SUCCESS(rc))
2004 {
2005 /* Create the host context. */
2006 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2007 }
2008
2009 return rc;
2010#else
2011 RT_NOREF(pThisCC, pCmd, cbCmd);
2012 return VERR_NOT_SUPPORTED;
2013#endif
2014}
2015
2016
2017/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2018static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2019{
2020#ifdef VMSVGA3D_DX
2021 //DEBUG_BREAKPOINT_TEST();
2022 RT_NOREF(cbCmd);
2023
2024 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2025
2026 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2027 SVGAOTableDXContextEntry entry;
2028 RT_ZERO(entry);
2029 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2030 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2031
2032 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2033#else
2034 RT_NOREF(pThisCC, pCmd, cbCmd);
2035 return VERR_NOT_SUPPORTED;
2036#endif
2037}
2038
2039
2040/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2041static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2042{
2043#ifdef VMSVGA3D_DX
2044 //DEBUG_BREAKPOINT_TEST();
2045 RT_NOREF(cbCmd);
2046
2047 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2048
2049 /* Assign a mobid to a cid. */
2050 int rc = VINF_SUCCESS;
2051 if (pCmd->mobid != SVGA_ID_INVALID)
2052 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2053 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2054 if (RT_SUCCESS(rc))
2055 {
2056 SVGAOTableDXContextEntry entry;
2057 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2058 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2059 if (RT_SUCCESS(rc))
2060 {
2061 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2062 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2063 {
2064 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2065 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2066 if (pSvgaDXContext)
2067 {
2068 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2069 if (RT_SUCCESS(rc))
2070 {
2071 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2072 if (pMob)
2073 {
2074 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2075 }
2076 }
2077
2078 RTMemFree(pSvgaDXContext);
2079 pSvgaDXContext = NULL;
2080 }
2081 }
2082
2083 if (pCmd->mobid != SVGA_ID_INVALID)
2084 {
2085 /* Bind a new context. Copy existing data from the guest backing memory. */
2086 if (pCmd->validContents)
2087 {
2088 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2089 if (pMob)
2090 {
2091 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2092 if (pSvgaDXContext)
2093 {
2094 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2095 if (RT_FAILURE(rc))
2096 {
2097 RTMemFree(pSvgaDXContext);
2098 pSvgaDXContext = NULL;
2099 }
2100 }
2101 }
2102 }
2103
2104 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2105
2106 RTMemFree(pSvgaDXContext);
2107 }
2108
2109 /* Update the object table. */
2110 entry.mobid = pCmd->mobid;
2111 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2112 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2113 }
2114 }
2115
2116 return rc;
2117#else
2118 RT_NOREF(pThisCC, pCmd, cbCmd);
2119 return VERR_NOT_SUPPORTED;
2120#endif
2121}
2122
2123
2124/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2125static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2126{
2127#ifdef VMSVGA3D_DX
2128 //DEBUG_BREAKPOINT_TEST();
2129 RT_NOREF(cbCmd);
2130
2131 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2132
2133 /* "Request that the device flush the contents back into guest memory." */
2134 SVGAOTableDXContextEntry entry;
2135 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2136 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2137 if (RT_SUCCESS(rc))
2138 {
2139 if (entry.mobid != SVGA_ID_INVALID)
2140 {
2141 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2142 if (pMob)
2143 {
2144 /* Get the content. */
2145 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2146 if (pSvgaDXContext)
2147 {
2148 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2149 if (RT_SUCCESS(rc))
2150 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2151
2152 RTMemFree(pSvgaDXContext);
2153 }
2154 else
2155 rc = VERR_NO_MEMORY;
2156 }
2157 }
2158 }
2159
2160 return rc;
2161#else
2162 RT_NOREF(pThisCC, pCmd, cbCmd);
2163 return VERR_NOT_SUPPORTED;
2164#endif
2165}
2166
2167
2168/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2169static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2170{
2171#ifdef VMSVGA3D_DX
2172 DEBUG_BREAKPOINT_TEST();
2173 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2174 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2175 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2176#else
2177 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2178 return VERR_NOT_SUPPORTED;
2179#endif
2180}
2181
2182
2183/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2184static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2185{
2186#ifdef VMSVGA3D_DX
2187 //DEBUG_BREAKPOINT_TEST();
2188 RT_NOREF(cbCmd);
2189 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2190#else
2191 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2192 return VERR_NOT_SUPPORTED;
2193#endif
2194}
2195
2196
2197/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2198static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2199{
2200#ifdef VMSVGA3D_DX
2201 //DEBUG_BREAKPOINT_TEST();
2202 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2203 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2204 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2205#else
2206 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2207 return VERR_NOT_SUPPORTED;
2208#endif
2209}
2210
2211
2212/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2213static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2214{
2215#ifdef VMSVGA3D_DX
2216 //DEBUG_BREAKPOINT_TEST();
2217 RT_NOREF(cbCmd);
2218 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2219#else
2220 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2221 return VERR_NOT_SUPPORTED;
2222#endif
2223}
2224
2225
2226/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2227static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2228{
2229#ifdef VMSVGA3D_DX
2230 //DEBUG_BREAKPOINT_TEST();
2231 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2232 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2233 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2234#else
2235 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2236 return VERR_NOT_SUPPORTED;
2237#endif
2238}
2239
2240
2241/* SVGA_3D_CMD_DX_DRAW 1152 */
2242static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2243{
2244#ifdef VMSVGA3D_DX
2245 //DEBUG_BREAKPOINT_TEST();
2246 RT_NOREF(cbCmd);
2247 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2248#else
2249 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2250 return VERR_NOT_SUPPORTED;
2251#endif
2252}
2253
2254
2255/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2256static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2257{
2258#ifdef VMSVGA3D_DX
2259 //DEBUG_BREAKPOINT_TEST();
2260 RT_NOREF(cbCmd);
2261 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2262#else
2263 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2264 return VERR_NOT_SUPPORTED;
2265#endif
2266}
2267
2268
2269/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2270static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2271{
2272#ifdef VMSVGA3D_DX
2273 //DEBUG_BREAKPOINT_TEST();
2274 RT_NOREF(cbCmd);
2275 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2276#else
2277 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2278 return VERR_NOT_SUPPORTED;
2279#endif
2280}
2281
2282
2283/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2284static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2285{
2286#ifdef VMSVGA3D_DX
2287 //DEBUG_BREAKPOINT_TEST();
2288 RT_NOREF(cbCmd);
2289 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2290#else
2291 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2292 return VERR_NOT_SUPPORTED;
2293#endif
2294}
2295
2296
2297/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2298static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2299{
2300#ifdef VMSVGA3D_DX
2301 DEBUG_BREAKPOINT_TEST();
2302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2303 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2304 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2305#else
2306 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2307 return VERR_NOT_SUPPORTED;
2308#endif
2309}
2310
2311
2312/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2313static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2314{
2315#ifdef VMSVGA3D_DX
2316 //DEBUG_BREAKPOINT_TEST();
2317 RT_NOREF(cbCmd);
2318 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2319#else
2320 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2321 return VERR_NOT_SUPPORTED;
2322#endif
2323}
2324
2325
2326/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2327static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2328{
2329#ifdef VMSVGA3D_DX
2330 //DEBUG_BREAKPOINT_TEST();
2331 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2332 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2333 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2334#else
2335 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2336 return VERR_NOT_SUPPORTED;
2337#endif
2338}
2339
2340
2341/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2342static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2343{
2344#ifdef VMSVGA3D_DX
2345 //DEBUG_BREAKPOINT_TEST();
2346 RT_NOREF(cbCmd);
2347 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2348#else
2349 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2350 return VERR_NOT_SUPPORTED;
2351#endif
2352}
2353
2354
2355/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2356static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2357{
2358#ifdef VMSVGA3D_DX
2359 //DEBUG_BREAKPOINT_TEST();
2360 RT_NOREF(cbCmd);
2361 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2362#else
2363 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2364 return VERR_NOT_SUPPORTED;
2365#endif
2366}
2367
2368
2369/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2370static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2371{
2372#ifdef VMSVGA3D_DX
2373 //DEBUG_BREAKPOINT_TEST();
2374 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2375 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2376 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2377#else
2378 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2379 return VERR_NOT_SUPPORTED;
2380#endif
2381}
2382
2383
2384/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2385static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2386{
2387#ifdef VMSVGA3D_DX
2388 //DEBUG_BREAKPOINT_TEST();
2389 RT_NOREF(cbCmd);
2390 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2391#else
2392 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2393 return VERR_NOT_SUPPORTED;
2394#endif
2395}
2396
2397
2398/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2399static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2400{
2401#ifdef VMSVGA3D_DX
2402 //DEBUG_BREAKPOINT_TEST();
2403 RT_NOREF(cbCmd);
2404 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2405#else
2406 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2407 return VERR_NOT_SUPPORTED;
2408#endif
2409}
2410
2411
2412/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2413static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2414{
2415#ifdef VMSVGA3D_DX
2416 //DEBUG_BREAKPOINT_TEST();
2417 RT_NOREF(cbCmd);
2418 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2419#else
2420 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2421 return VERR_NOT_SUPPORTED;
2422#endif
2423}
2424
2425
2426/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2427static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2428{
2429#ifdef VMSVGA3D_DX
2430 DEBUG_BREAKPOINT_TEST();
2431 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2432 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2433 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2434#else
2435 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2436 return VERR_NOT_SUPPORTED;
2437#endif
2438}
2439
2440
2441/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2442static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2443{
2444#ifdef VMSVGA3D_DX
2445 DEBUG_BREAKPOINT_TEST();
2446 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2447 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2448 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2449#else
2450 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2451 return VERR_NOT_SUPPORTED;
2452#endif
2453}
2454
2455
2456/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2457static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2458{
2459#ifdef VMSVGA3D_DX
2460 DEBUG_BREAKPOINT_TEST();
2461 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2462 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2463 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2464#else
2465 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2466 return VERR_NOT_SUPPORTED;
2467#endif
2468}
2469
2470
2471/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2472static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2473{
2474#ifdef VMSVGA3D_DX
2475 DEBUG_BREAKPOINT_TEST();
2476 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2477 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2478 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2479#else
2480 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2481 return VERR_NOT_SUPPORTED;
2482#endif
2483}
2484
2485
2486/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2487static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2488{
2489#ifdef VMSVGA3D_DX
2490 DEBUG_BREAKPOINT_TEST();
2491 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2492 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2493 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2494#else
2495 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2496 return VERR_NOT_SUPPORTED;
2497#endif
2498}
2499
2500
2501/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2502static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2503{
2504#ifdef VMSVGA3D_DX
2505 DEBUG_BREAKPOINT_TEST();
2506 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2507 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2508 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2509#else
2510 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2511 return VERR_NOT_SUPPORTED;
2512#endif
2513}
2514
2515
2516/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2517static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2518{
2519#ifdef VMSVGA3D_DX
2520 DEBUG_BREAKPOINT_TEST();
2521 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2522 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2523 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2524#else
2525 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2526 return VERR_NOT_SUPPORTED;
2527#endif
2528}
2529
2530
2531/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2532static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2533{
2534#ifdef VMSVGA3D_DX
2535 DEBUG_BREAKPOINT_TEST();
2536 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2537 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2538 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2539#else
2540 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2541 return VERR_NOT_SUPPORTED;
2542#endif
2543}
2544
2545
2546/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2547static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2548{
2549#ifdef VMSVGA3D_DX
2550 //DEBUG_BREAKPOINT_TEST();
2551 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2552 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2553 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2554#else
2555 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2556 return VERR_NOT_SUPPORTED;
2557#endif
2558}
2559
2560
2561/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2562static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2563{
2564#ifdef VMSVGA3D_DX
2565 //DEBUG_BREAKPOINT_TEST();
2566 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2567 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2568 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2569#else
2570 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2571 return VERR_NOT_SUPPORTED;
2572#endif
2573}
2574
2575
2576/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2577static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2578{
2579#ifdef VMSVGA3D_DX
2580 //DEBUG_BREAKPOINT_TEST();
2581 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2582 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2583 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2584#else
2585 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2586 return VERR_NOT_SUPPORTED;
2587#endif
2588}
2589
2590
2591/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2592static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2593{
2594#ifdef VMSVGA3D_DX
2595 //DEBUG_BREAKPOINT_TEST();
2596 RT_NOREF(cbCmd);
2597 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2598#else
2599 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2600 return VERR_NOT_SUPPORTED;
2601#endif
2602}
2603
2604
2605/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2606static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2607{
2608#ifdef VMSVGA3D_DX
2609 //DEBUG_BREAKPOINT_TEST();
2610 RT_NOREF(cbCmd);
2611 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2612#else
2613 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2614 return VERR_NOT_SUPPORTED;
2615#endif
2616}
2617
2618
2619/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2620static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2621{
2622#ifdef VMSVGA3D_DX
2623 //DEBUG_BREAKPOINT_TEST();
2624 RT_NOREF(cbCmd);
2625 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2626#else
2627 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2628 return VERR_NOT_SUPPORTED;
2629#endif
2630}
2631
2632
2633/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2634static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2635{
2636#ifdef VMSVGA3D_DX
2637 DEBUG_BREAKPOINT_TEST();
2638 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2639 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2640 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2641#else
2642 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2643 return VERR_NOT_SUPPORTED;
2644#endif
2645}
2646
2647
2648/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2649static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2650{
2651#ifdef VMSVGA3D_DX
2652 DEBUG_BREAKPOINT_TEST();
2653 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2654 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2655 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2656#else
2657 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2658 return VERR_NOT_SUPPORTED;
2659#endif
2660}
2661
2662
2663/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2664static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2665{
2666#ifdef VMSVGA3D_DX
2667 //DEBUG_BREAKPOINT_TEST();
2668 RT_NOREF(cbCmd);
2669 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2670#else
2671 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2672 return VERR_NOT_SUPPORTED;
2673#endif
2674}
2675
2676
2677/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2678static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2679{
2680#ifdef VMSVGA3D_DX
2681 //DEBUG_BREAKPOINT_TEST();
2682 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2683 RT_NOREF(cbCmd);
2684
2685 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2686 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.z));
2687
2688 /* "Inform the device that the guest-contents have been updated." */
2689 SVGAOTableSurfaceEntry entrySurface;
2690 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2691 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2692 if (RT_SUCCESS(rc))
2693 {
2694 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2695 if (pMob)
2696 {
2697 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2698 ? SVGA3D_MAX_SURFACE_FACES
2699 : RT_MAX(entrySurface.arraySize, 1);
2700 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2701 /* pCmd->box will be verified by the mapping function. */
2702 RT_UNTRUSTED_VALIDATED_FENCE();
2703
2704 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2705 SVGA3dSurfaceImageId image;
2706 image.sid = pCmd->sid;
2707 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2708
2709 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2710 AssertRC(rc);
2711 }
2712 }
2713
2714 return rc;
2715#else
2716 RT_NOREF(pThisCC, pCmd, cbCmd);
2717 return VERR_NOT_SUPPORTED;
2718#endif
2719}
2720
2721
2722/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2723static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2724{
2725#ifdef VMSVGA3D_DX
2726 //DEBUG_BREAKPOINT_TEST();
2727 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2728 RT_NOREF(cbCmd);
2729
2730 LogFlowFunc(("sid=%u, subResource=%u\n",
2731 pCmd->sid, pCmd->subResource));
2732
2733 /* "Request the device to flush the dirty contents into the guest." */
2734 SVGAOTableSurfaceEntry entrySurface;
2735 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2736 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2737 if (RT_SUCCESS(rc))
2738 {
2739 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2740 if (pMob)
2741 {
2742 uint32 const arraySize = (entrySurface.surface1Flags & SVGA3D_SURFACE_CUBEMAP)
2743 ? SVGA3D_MAX_SURFACE_FACES
2744 : RT_MAX(entrySurface.arraySize, 1);
2745 ASSERT_GUEST_RETURN(pCmd->subResource < arraySize * entrySurface.numMipLevels, VERR_INVALID_PARAMETER);
2746 RT_UNTRUSTED_VALIDATED_FENCE();
2747
2748 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2749 SVGA3dSurfaceImageId image;
2750 image.sid = pCmd->sid;
2751 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2752
2753 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2754 AssertRC(rc);
2755 }
2756 }
2757
2758 return rc;
2759#else
2760 RT_NOREF(pThisCC, pCmd, cbCmd);
2761 return VERR_NOT_SUPPORTED;
2762#endif
2763}
2764
2765
2766/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2767static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2768{
2769#ifdef VMSVGA3D_DX
2770 DEBUG_BREAKPOINT_TEST();
2771 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2772 RT_NOREF(cbCmd);
2773
2774 LogFlowFunc(("sid=%u, subResource=%u\n",
2775 pCmd->sid, pCmd->subResource));
2776
2777 /* "Notify the device that the contents can be lost." */
2778 SVGAOTableSurfaceEntry entrySurface;
2779 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2780 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2781 if (RT_SUCCESS(rc))
2782 {
2783 uint32_t iFace;
2784 uint32_t iMipmap;
2785 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2786 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2787 }
2788
2789 return rc;
2790#else
2791 RT_NOREF(pThisCC, pCmd, cbCmd);
2792 return VERR_NOT_SUPPORTED;
2793#endif
2794}
2795
2796
2797/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2798static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2799{
2800#ifdef VMSVGA3D_DX
2801 //DEBUG_BREAKPOINT_TEST();
2802 RT_NOREF(cbCmd);
2803 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2804#else
2805 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2806 return VERR_NOT_SUPPORTED;
2807#endif
2808}
2809
2810
2811/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2812static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2813{
2814#ifdef VMSVGA3D_DX
2815 //DEBUG_BREAKPOINT_TEST();
2816 RT_NOREF(cbCmd);
2817 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2818#else
2819 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2820 return VERR_NOT_SUPPORTED;
2821#endif
2822}
2823
2824
2825/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2826static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2827{
2828#ifdef VMSVGA3D_DX
2829 //DEBUG_BREAKPOINT_TEST();
2830 RT_NOREF(cbCmd);
2831 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2832#else
2833 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2834 return VERR_NOT_SUPPORTED;
2835#endif
2836}
2837
2838
2839/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2840static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2841{
2842#ifdef VMSVGA3D_DX
2843 //DEBUG_BREAKPOINT_TEST();
2844 RT_NOREF(cbCmd);
2845 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2846#else
2847 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2848 return VERR_NOT_SUPPORTED;
2849#endif
2850}
2851
2852
2853/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2854static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2855{
2856#ifdef VMSVGA3D_DX
2857 //DEBUG_BREAKPOINT_TEST();
2858 RT_NOREF(cbCmd);
2859 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2860 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2861 cmd.sid = pCmd->sid;
2862 cmd.format = pCmd->format;
2863 cmd.resourceDimension = pCmd->resourceDimension;
2864 cmd.mipSlice = pCmd->mipSlice;
2865 cmd.firstArraySlice = pCmd->firstArraySlice;
2866 cmd.arraySize = pCmd->arraySize;
2867 cmd.flags = 0;
2868 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2869#else
2870 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2871 return VERR_NOT_SUPPORTED;
2872#endif
2873}
2874
2875
2876/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2877static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2878{
2879#ifdef VMSVGA3D_DX
2880 //DEBUG_BREAKPOINT_TEST();
2881 RT_NOREF(cbCmd);
2882 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
2883#else
2884 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2885 return VERR_NOT_SUPPORTED;
2886#endif
2887}
2888
2889
2890/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2891static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2892{
2893#ifdef VMSVGA3D_DX
2894 //DEBUG_BREAKPOINT_TEST();
2895 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2896 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2897 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2898#else
2899 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2900 return VERR_NOT_SUPPORTED;
2901#endif
2902}
2903
2904
2905/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2906static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2907{
2908#ifdef VMSVGA3D_DX
2909 DEBUG_BREAKPOINT_TEST();
2910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2911 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2912 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2913#else
2914 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2915 return VERR_NOT_SUPPORTED;
2916#endif
2917}
2918
2919
2920/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2921static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2922{
2923#ifdef VMSVGA3D_DX
2924 //DEBUG_BREAKPOINT_TEST();
2925 RT_NOREF(cbCmd);
2926 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2927#else
2928 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2929 return VERR_NOT_SUPPORTED;
2930#endif
2931}
2932
2933
2934/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2935static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2936{
2937#ifdef VMSVGA3D_DX
2938 DEBUG_BREAKPOINT_TEST();
2939 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2940 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2941 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2942#else
2943 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2944 return VERR_NOT_SUPPORTED;
2945#endif
2946}
2947
2948
2949/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2950static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2951{
2952#ifdef VMSVGA3D_DX
2953 //DEBUG_BREAKPOINT_TEST();
2954 RT_NOREF(cbCmd);
2955 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2956#else
2957 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2958 return VERR_NOT_SUPPORTED;
2959#endif
2960}
2961
2962
2963/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2964static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2965{
2966#ifdef VMSVGA3D_DX
2967 DEBUG_BREAKPOINT_TEST();
2968 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2969 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2970 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2971#else
2972 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2973 return VERR_NOT_SUPPORTED;
2974#endif
2975}
2976
2977
2978/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2979static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2980{
2981#ifdef VMSVGA3D_DX
2982 //DEBUG_BREAKPOINT_TEST();
2983 RT_NOREF(cbCmd);
2984 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2985#else
2986 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2987 return VERR_NOT_SUPPORTED;
2988#endif
2989}
2990
2991
2992/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2993static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2994{
2995#ifdef VMSVGA3D_DX
2996 DEBUG_BREAKPOINT_TEST();
2997 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2998 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2999 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
3000#else
3001 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3002 return VERR_NOT_SUPPORTED;
3003#endif
3004}
3005
3006
3007/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3008static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3009{
3010#ifdef VMSVGA3D_DX
3011 //DEBUG_BREAKPOINT_TEST();
3012 RT_NOREF(cbCmd);
3013 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3014#else
3015 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3016 return VERR_NOT_SUPPORTED;
3017#endif
3018}
3019
3020
3021/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3022static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3023{
3024#ifdef VMSVGA3D_DX
3025 DEBUG_BREAKPOINT_TEST();
3026 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3027 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3028 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
3029#else
3030 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3031 return VERR_NOT_SUPPORTED;
3032#endif
3033}
3034
3035
3036/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3037static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3038{
3039#ifdef VMSVGA3D_DX
3040 //DEBUG_BREAKPOINT_TEST();
3041 RT_NOREF(cbCmd);
3042 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3043#else
3044 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3045 return VERR_NOT_SUPPORTED;
3046#endif
3047}
3048
3049
3050/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3051static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3052{
3053#ifdef VMSVGA3D_DX
3054 //DEBUG_BREAKPOINT_TEST();
3055 RT_NOREF(cbCmd);
3056 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3057#else
3058 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3059 return VERR_NOT_SUPPORTED;
3060#endif
3061}
3062
3063
3064/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3065static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3066{
3067#ifdef VMSVGA3D_DX
3068 //DEBUG_BREAKPOINT_TEST();
3069 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3070 RT_NOREF(idDXContext, cbCmd);
3071 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3072 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3073 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3074#else
3075 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3076 return VERR_NOT_SUPPORTED;
3077#endif
3078}
3079
3080
3081/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3082static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3083{
3084#ifdef VMSVGA3D_DX
3085 //DEBUG_BREAKPOINT_TEST();
3086 RT_NOREF(cbCmd);
3087 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3088#else
3089 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3090 return VERR_NOT_SUPPORTED;
3091#endif
3092}
3093
3094
3095/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3096static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3097{
3098#ifdef VMSVGA3D_DX
3099 DEBUG_BREAKPOINT_TEST();
3100 RT_NOREF(cbCmd);
3101 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3102#else
3103 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3104 return VERR_NOT_SUPPORTED;
3105#endif
3106}
3107
3108
3109/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3110static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3111{
3112#ifdef VMSVGA3D_DX
3113 //DEBUG_BREAKPOINT_TEST();
3114 RT_NOREF(cbCmd);
3115 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3116#else
3117 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3118 return VERR_NOT_SUPPORTED;
3119#endif
3120}
3121
3122
3123/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3124static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3125{
3126#ifdef VMSVGA3D_DX
3127 //DEBUG_BREAKPOINT_TEST();
3128 RT_NOREF(cbCmd);
3129 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3130 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3131 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3132 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3133#else
3134 RT_NOREF(pThisCC, pCmd, cbCmd);
3135 return VERR_NOT_SUPPORTED;
3136#endif
3137}
3138
3139
3140/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3141static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3142{
3143#ifdef VMSVGA3D_DX
3144 //DEBUG_BREAKPOINT_TEST();
3145 RT_NOREF(idDXContext, cbCmd);
3146 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3147#else
3148 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3149 return VERR_NOT_SUPPORTED;
3150#endif
3151}
3152
3153
3154/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3155static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3156{
3157#ifdef VMSVGA3D_DX
3158 DEBUG_BREAKPOINT_TEST();
3159 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3160 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3161 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
3162#else
3163 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3164 return VERR_NOT_SUPPORTED;
3165#endif
3166}
3167
3168
3169/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3170static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3171{
3172#ifdef VMSVGA3D_DX
3173 //DEBUG_BREAKPOINT_TEST();
3174 RT_NOREF(cbCmd);
3175
3176 /* Plan:
3177 * - map the buffer;
3178 * - map the surface;
3179 * - copy from buffer map to the surface map.
3180 */
3181
3182 int rc;
3183
3184 SVGA3dSurfaceImageId imageBuffer;
3185 imageBuffer.sid = pCmd->srcSid;
3186 imageBuffer.face = 0;
3187 imageBuffer.mipmap = 0;
3188
3189 SVGA3dSurfaceImageId imageSurface;
3190 imageSurface.sid = pCmd->destSid;
3191 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3192 AssertRCReturn(rc, rc);
3193
3194 /*
3195 * Map the buffer.
3196 */
3197 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3198 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3199 if (RT_SUCCESS(rc))
3200 {
3201 /*
3202 * Map the surface.
3203 */
3204 VMSVGA3D_MAPPED_SURFACE mapSurface;
3205 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3206 if (RT_SUCCESS(rc))
3207 {
3208 /*
3209 * Copy the mapped buffer to the surface.
3210 */
3211 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3212 uint32_t const cbBuffer = mapBuffer.box.w * mapBuffer.cbPixel;
3213
3214 if (pCmd->srcOffset <= cbBuffer)
3215 {
3216 RT_UNTRUSTED_VALIDATED_FENCE();
3217 uint8_t const *pu8BufferBegin = pu8Buffer;
3218 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3219
3220 pu8Buffer += pCmd->srcOffset;
3221
3222 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3223
3224 uint32_t const cbWidth = mapSurface.box.w * mapSurface.cbPixel;
3225 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3226 {
3227 uint8_t const *pu8BufferRow = pu8Buffer;
3228 uint8_t *pu8SurfaceRow = pu8Surface;
3229 for (uint32_t y = 0; y < mapSurface.box.h; ++y)
3230 {
3231 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3232 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3233 && (uintptr_t)(pu8BufferRow + cbWidth) > (uintptr_t)pu8BufferBegin
3234 && (uintptr_t)(pu8BufferRow + cbWidth) <= (uintptr_t)pu8BufferEnd,
3235 rc = VERR_INVALID_PARAMETER);
3236
3237 memcpy(pu8SurfaceRow, pu8BufferRow, cbWidth);
3238
3239 pu8SurfaceRow += mapSurface.cbRowPitch;
3240 pu8BufferRow += pCmd->srcPitch;
3241 }
3242
3243 pu8Buffer += pCmd->srcSlicePitch;
3244 pu8Surface += mapSurface.cbDepthPitch;
3245 }
3246 }
3247 else
3248 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3249
3250 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3251 }
3252
3253 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3254 }
3255
3256 return rc;
3257#else
3258 RT_NOREF(pThisCC, pCmd, cbCmd);
3259 return VERR_NOT_SUPPORTED;
3260#endif
3261}
3262
3263
3264/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3265static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3266{
3267#ifdef VMSVGA3D_DX
3268 DEBUG_BREAKPOINT_TEST();
3269 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3270 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3271 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3272#else
3273 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3274 return VERR_NOT_SUPPORTED;
3275#endif
3276}
3277
3278
3279/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3280static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3281{
3282#ifdef VMSVGA3D_DX
3283 DEBUG_BREAKPOINT_TEST();
3284 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3285 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3286 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3287#else
3288 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3289 return VERR_NOT_SUPPORTED;
3290#endif
3291}
3292
3293
3294/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3295static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3296{
3297#ifdef VMSVGA3D_DX
3298 DEBUG_BREAKPOINT_TEST();
3299 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3300 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3301 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
3302#else
3303 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3304 return VERR_NOT_SUPPORTED;
3305#endif
3306}
3307
3308
3309/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3310static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3311{
3312#ifdef VMSVGA3D_DX
3313 DEBUG_BREAKPOINT_TEST();
3314 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3315 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3316 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
3317#else
3318 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3319 return VERR_NOT_SUPPORTED;
3320#endif
3321}
3322
3323
3324/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3325static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3326{
3327#ifdef VMSVGA3D_DX
3328 //DEBUG_BREAKPOINT_TEST();
3329 RT_NOREF(idDXContext, cbCmd);
3330
3331 /* This command is executed in a context: "The context is implied from the command buffer header."
3332 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3333 */
3334 SVGA3dCmdDXTransferFromBuffer cmd;
3335 cmd.srcSid = pCmd->srcSid;
3336 cmd.srcOffset = pCmd->srcOffset;
3337 cmd.srcPitch = pCmd->srcPitch;
3338 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3339 cmd.destSid = pCmd->destSid;
3340 cmd.destSubResource = pCmd->destSubResource;
3341 cmd.destBox = pCmd->destBox;
3342 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3343#else
3344 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3345 return VERR_NOT_SUPPORTED;
3346#endif
3347}
3348
3349
3350/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3351static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3352{
3353#ifdef VMSVGA3D_DX
3354 DEBUG_BREAKPOINT_TEST();
3355 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3356 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3357 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
3358#else
3359 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3360 return VERR_NOT_SUPPORTED;
3361#endif
3362}
3363
3364
3365/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3366static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3367{
3368#ifdef VMSVGA3D_DX
3369 DEBUG_BREAKPOINT_TEST();
3370 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3371 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3372 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3373#else
3374 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3375 return VERR_NOT_SUPPORTED;
3376#endif
3377}
3378
3379
3380/* SVGA_3D_CMD_DX_HINT 1218 */
3381static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3382{
3383#ifdef VMSVGA3D_DX
3384 DEBUG_BREAKPOINT_TEST();
3385 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3386 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3387 return vmsvga3dDXHint(pThisCC, idDXContext);
3388#else
3389 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3390 return VERR_NOT_SUPPORTED;
3391#endif
3392}
3393
3394
3395/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3396static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3397{
3398#ifdef VMSVGA3D_DX
3399 DEBUG_BREAKPOINT_TEST();
3400 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3401 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3402 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3403#else
3404 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3405 return VERR_NOT_SUPPORTED;
3406#endif
3407}
3408
3409
3410/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3411static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3412{
3413#ifdef VMSVGA3D_DX
3414 DEBUG_BREAKPOINT_TEST();
3415 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3416 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3417 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3418#else
3419 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3420 return VERR_NOT_SUPPORTED;
3421#endif
3422}
3423
3424
3425/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3426static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3427{
3428#ifdef VMSVGA3D_DX
3429 DEBUG_BREAKPOINT_TEST();
3430 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3431 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3432 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3433#else
3434 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3435 return VERR_NOT_SUPPORTED;
3436#endif
3437}
3438
3439
3440/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3441static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3442{
3443#ifdef VMSVGA3D_DX
3444 DEBUG_BREAKPOINT_TEST();
3445 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3446 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3447 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3448#else
3449 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3450 return VERR_NOT_SUPPORTED;
3451#endif
3452}
3453
3454
3455/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3456static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3457{
3458#ifdef VMSVGA3D_DX
3459 DEBUG_BREAKPOINT_TEST();
3460 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3461 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3462 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3463#else
3464 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3465 return VERR_NOT_SUPPORTED;
3466#endif
3467}
3468
3469
3470/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3471static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3472{
3473#ifdef VMSVGA3D_DX
3474 DEBUG_BREAKPOINT_TEST();
3475 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3476 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3477 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3478#else
3479 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3480 return VERR_NOT_SUPPORTED;
3481#endif
3482}
3483
3484
3485/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3486static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3487{
3488#ifdef VMSVGA3D_DX
3489 DEBUG_BREAKPOINT_TEST();
3490 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3491 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3492 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3493#else
3494 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3495 return VERR_NOT_SUPPORTED;
3496#endif
3497}
3498
3499
3500/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3501static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3502{
3503#ifdef VMSVGA3D_DX
3504 DEBUG_BREAKPOINT_TEST();
3505 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3506 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3507 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3508#else
3509 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3510 return VERR_NOT_SUPPORTED;
3511#endif
3512}
3513
3514
3515/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3516static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3517{
3518#ifdef VMSVGA3D_DX
3519 DEBUG_BREAKPOINT_TEST();
3520 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3521 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3522 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3523#else
3524 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3525 return VERR_NOT_SUPPORTED;
3526#endif
3527}
3528
3529
3530/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3531static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3532{
3533#ifdef VMSVGA3D_DX
3534 DEBUG_BREAKPOINT_TEST();
3535 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3536 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3537 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3538#else
3539 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3540 return VERR_NOT_SUPPORTED;
3541#endif
3542}
3543
3544
3545/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3546static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3547{
3548#ifdef VMSVGA3D_DX
3549 DEBUG_BREAKPOINT_TEST();
3550 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3551 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3552 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3553#else
3554 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3555 return VERR_NOT_SUPPORTED;
3556#endif
3557}
3558
3559
3560/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3561static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3562{
3563#ifdef VMSVGA3D_DX
3564 DEBUG_BREAKPOINT_TEST();
3565 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3566 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3567 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3568#else
3569 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3570 return VERR_NOT_SUPPORTED;
3571#endif
3572}
3573
3574
3575/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3576static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3577{
3578#ifdef VMSVGA3D_DX
3579 DEBUG_BREAKPOINT_TEST();
3580 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3581 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3582 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3583#else
3584 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3585 return VERR_NOT_SUPPORTED;
3586#endif
3587}
3588
3589
3590/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3591static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3592{
3593#ifdef VMSVGA3D_DX
3594 DEBUG_BREAKPOINT_TEST();
3595 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3596 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3597 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3598#else
3599 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3600 return VERR_NOT_SUPPORTED;
3601#endif
3602}
3603
3604
3605/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3606static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3607{
3608#ifdef VMSVGA3D_DX
3609 DEBUG_BREAKPOINT_TEST();
3610 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3611 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3612 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3613#else
3614 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3615 return VERR_NOT_SUPPORTED;
3616#endif
3617}
3618
3619
3620/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3621static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3622{
3623#ifdef VMSVGA3D_DX
3624 DEBUG_BREAKPOINT_TEST();
3625 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3626 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3627 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3628#else
3629 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3630 return VERR_NOT_SUPPORTED;
3631#endif
3632}
3633
3634
3635/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3636static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3637{
3638#ifdef VMSVGA3D_DX
3639 DEBUG_BREAKPOINT_TEST();
3640 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3641 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3642 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3643#else
3644 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3645 return VERR_NOT_SUPPORTED;
3646#endif
3647}
3648
3649
3650/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3651static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3652{
3653#ifdef VMSVGA3D_DX
3654 DEBUG_BREAKPOINT_TEST();
3655 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3656 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3657 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3658#else
3659 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3660 return VERR_NOT_SUPPORTED;
3661#endif
3662}
3663
3664
3665/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3666static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3667{
3668#ifdef VMSVGA3D_DX
3669 DEBUG_BREAKPOINT_TEST();
3670 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3671 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3672 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3673#else
3674 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3675 return VERR_NOT_SUPPORTED;
3676#endif
3677}
3678
3679
3680/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3681static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3682{
3683#ifdef VMSVGA3D_DX
3684 DEBUG_BREAKPOINT_TEST();
3685 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3686 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3687 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3688#else
3689 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3690 return VERR_NOT_SUPPORTED;
3691#endif
3692}
3693
3694
3695/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3696static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3697{
3698#ifdef VMSVGA3D_DX
3699 DEBUG_BREAKPOINT_TEST();
3700 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3701 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3702 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3703#else
3704 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3705 return VERR_NOT_SUPPORTED;
3706#endif
3707}
3708
3709
3710/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3711static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3712{
3713#ifdef VMSVGA3D_DX
3714 DEBUG_BREAKPOINT_TEST();
3715 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3716 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3717 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3718#else
3719 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3720 return VERR_NOT_SUPPORTED;
3721#endif
3722}
3723
3724
3725/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3726static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3727{
3728#ifdef VMSVGA3D_DX
3729 DEBUG_BREAKPOINT_TEST();
3730 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3731 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3732 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3733#else
3734 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3735 return VERR_NOT_SUPPORTED;
3736#endif
3737}
3738
3739
3740/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3741static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3742{
3743#ifdef VMSVGA3D_DX
3744 DEBUG_BREAKPOINT_TEST();
3745 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3746 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3747 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3748#else
3749 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3750 return VERR_NOT_SUPPORTED;
3751#endif
3752}
3753
3754
3755/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3756static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3757{
3758#ifdef VMSVGA3D_DX
3759 DEBUG_BREAKPOINT_TEST();
3760 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3761 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3762 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3763#else
3764 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3765 return VERR_NOT_SUPPORTED;
3766#endif
3767}
3768
3769
3770/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3771static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3772{
3773#ifdef VMSVGA3D_DX
3774 DEBUG_BREAKPOINT_TEST();
3775 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3776 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3777 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3778#else
3779 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3780 return VERR_NOT_SUPPORTED;
3781#endif
3782}
3783
3784
3785/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3786static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3787{
3788#ifdef VMSVGA3D_DX
3789 DEBUG_BREAKPOINT_TEST();
3790 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3791 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3792 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3793#else
3794 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3795 return VERR_NOT_SUPPORTED;
3796#endif
3797}
3798
3799
3800/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3801static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3802{
3803#ifdef VMSVGA3D_DX
3804 DEBUG_BREAKPOINT_TEST();
3805 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3806 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3807 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3808#else
3809 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3810 return VERR_NOT_SUPPORTED;
3811#endif
3812}
3813
3814
3815/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3816static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3817{
3818#ifdef VMSVGA3D_DX
3819 DEBUG_BREAKPOINT_TEST();
3820 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3821 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3822 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3823#else
3824 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3825 return VERR_NOT_SUPPORTED;
3826#endif
3827}
3828
3829
3830/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3831static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3832{
3833#ifdef VMSVGA3D_DX
3834 DEBUG_BREAKPOINT_TEST();
3835 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3836 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3837 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3838#else
3839 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3840 return VERR_NOT_SUPPORTED;
3841#endif
3842}
3843
3844
3845/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3846static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3847{
3848#ifdef VMSVGA3D_DX
3849 DEBUG_BREAKPOINT_TEST();
3850 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3851 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3852 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3853#else
3854 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3855 return VERR_NOT_SUPPORTED;
3856#endif
3857}
3858
3859
3860/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3861static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3862{
3863#ifdef VMSVGA3D_DX
3864 DEBUG_BREAKPOINT_TEST();
3865 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3866 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3867 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3868#else
3869 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3870 return VERR_NOT_SUPPORTED;
3871#endif
3872}
3873
3874
3875/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3876static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3877{
3878#ifdef VMSVGA3D_DX
3879 DEBUG_BREAKPOINT_TEST();
3880 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3881 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3882 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3883#else
3884 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3885 return VERR_NOT_SUPPORTED;
3886#endif
3887}
3888
3889
3890/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3891static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3892{
3893#ifdef VMSVGA3D_DX
3894 DEBUG_BREAKPOINT_TEST();
3895 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3896 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3897 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3898#else
3899 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3900 return VERR_NOT_SUPPORTED;
3901#endif
3902}
3903
3904
3905/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3906static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3907{
3908#ifdef VMSVGA3D_DX
3909 DEBUG_BREAKPOINT_TEST();
3910 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3911 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3912 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3913#else
3914 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3915 return VERR_NOT_SUPPORTED;
3916#endif
3917}
3918
3919
3920/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3921static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3922{
3923#ifdef VMSVGA3D_DX
3924 DEBUG_BREAKPOINT_TEST();
3925 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3926 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3927 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3928#else
3929 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3930 return VERR_NOT_SUPPORTED;
3931#endif
3932}
3933
3934
3935/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3936static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3937{
3938#ifdef VMSVGA3D_DX
3939 DEBUG_BREAKPOINT_TEST();
3940 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3941 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3942 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3943#else
3944 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3945 return VERR_NOT_SUPPORTED;
3946#endif
3947}
3948
3949
3950/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3951static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3952{
3953#ifdef VMSVGA3D_DX
3954 DEBUG_BREAKPOINT_TEST();
3955 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3956 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3957 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3958#else
3959 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3960 return VERR_NOT_SUPPORTED;
3961#endif
3962}
3963
3964
3965/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3966static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3967{
3968#ifdef VMSVGA3D_DX
3969 DEBUG_BREAKPOINT_TEST();
3970 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3971 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3972 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3973#else
3974 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3975 return VERR_NOT_SUPPORTED;
3976#endif
3977}
3978
3979
3980/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3981static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3982{
3983#ifdef VMSVGA3D_DX
3984 DEBUG_BREAKPOINT_TEST();
3985 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3986 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3987 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3988#else
3989 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3990 return VERR_NOT_SUPPORTED;
3991#endif
3992}
3993
3994
3995/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3996static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3997{
3998#ifdef VMSVGA3D_DX
3999 DEBUG_BREAKPOINT_TEST();
4000 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4001 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4002 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4003#else
4004 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4005 return VERR_NOT_SUPPORTED;
4006#endif
4007}
4008
4009
4010/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4011static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4012{
4013#ifdef VMSVGA3D_DX
4014 //DEBUG_BREAKPOINT_TEST();
4015 RT_NOREF(cbCmd);
4016 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4017#else
4018 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4019 return VERR_NOT_SUPPORTED;
4020#endif
4021}
4022
4023
4024/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4025static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4026{
4027#ifdef VMSVGA3D_DX
4028 DEBUG_BREAKPOINT_TEST();
4029 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4030 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4031 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
4032#else
4033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4034 return VERR_NOT_SUPPORTED;
4035#endif
4036}
4037
4038
4039/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4040static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4041{
4042#ifdef VMSVGA3D_DX
4043 DEBUG_BREAKPOINT_TEST();
4044 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4045 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4046 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4047#else
4048 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4049 return VERR_NOT_SUPPORTED;
4050#endif
4051}
4052
4053
4054/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4055static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4056{
4057#ifdef VMSVGA3D_DX
4058 DEBUG_BREAKPOINT_TEST();
4059 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4060 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4061 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
4062#else
4063 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4064 return VERR_NOT_SUPPORTED;
4065#endif
4066}
4067
4068
4069/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4070static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4071{
4072#ifdef VMSVGA3D_DX
4073 DEBUG_BREAKPOINT_TEST();
4074 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4075 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4076 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4077#else
4078 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4079 return VERR_NOT_SUPPORTED;
4080#endif
4081}
4082
4083
4084/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4085static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4086{
4087#ifdef VMSVGA3D_DX
4088 DEBUG_BREAKPOINT_TEST();
4089 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4090 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4091 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4092#else
4093 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4094 return VERR_NOT_SUPPORTED;
4095#endif
4096}
4097
4098
4099/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4100 * Check that the 3D command has at least a_cbMin of payload bytes after the
4101 * header. Will break out of the switch if it doesn't.
4102 */
4103# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4104 if (1) { \
4105 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4106 RT_UNTRUSTED_VALIDATED_FENCE(); \
4107 } else do {} while (0)
4108
4109# define VMSVGA_3D_CMD_NOTIMPL() \
4110 if (1) { \
4111 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4112 } else do {} while (0)
4113
4114/** SVGA_3D_CMD_* handler.
4115 * This function parses the command and calls the corresponding command handler.
4116 *
4117 * @param pThis The shared VGA/VMSVGA state.
4118 * @param pThisCC The VGA/VMSVGA state for the current context.
4119 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4120 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4121 * @param cbCmd Size of the command in bytes.
4122 * @param pvCmd Pointer to the command.
4123 * @returns VBox status code if an error was detected parsing a command.
4124 */
4125int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4126{
4127 if (enmCmdId > SVGA_3D_CMD_MAX)
4128 {
4129 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
4130 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
4131 }
4132
4133 int rcParse = VINF_SUCCESS;
4134 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4135
4136 switch (enmCmdId)
4137 {
4138 case SVGA_3D_CMD_SURFACE_DEFINE:
4139 {
4140 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4142 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4143
4144 SVGA3dCmdDefineSurface_v2 cmd;
4145 cmd.sid = pCmd->sid;
4146 cmd.surfaceFlags = pCmd->surfaceFlags;
4147 cmd.format = pCmd->format;
4148 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4149 cmd.multisampleCount = 0;
4150 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4151
4152 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4153 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4154# ifdef DEBUG_GMR_ACCESS
4155 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4156# endif
4157 break;
4158 }
4159
4160 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4161 {
4162 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4163 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4164 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4165
4166 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4167 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4168# ifdef DEBUG_GMR_ACCESS
4169 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4170# endif
4171 break;
4172 }
4173
4174 case SVGA_3D_CMD_SURFACE_DESTROY:
4175 {
4176 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4177 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4178 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4179
4180 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4181 break;
4182 }
4183
4184 case SVGA_3D_CMD_SURFACE_COPY:
4185 {
4186 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4187 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4188 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4189
4190 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4191 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4192 break;
4193 }
4194
4195 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4196 {
4197 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4198 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4199 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4200
4201 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4202 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4203 break;
4204 }
4205
4206 case SVGA_3D_CMD_SURFACE_DMA:
4207 {
4208 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4209 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4210 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4211
4212 uint64_t u64NanoTS = 0;
4213 if (LogRelIs3Enabled())
4214 u64NanoTS = RTTimeNanoTS();
4215 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4216 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4217 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4218 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4219 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4220 if (LogRelIs3Enabled())
4221 {
4222 if (cCopyBoxes)
4223 {
4224 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
4225 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4226 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4227 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4228 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4229 }
4230 }
4231 break;
4232 }
4233
4234 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4235 {
4236 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
4237 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4238 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
4239
4240 static uint64_t u64FrameStartNanoTS = 0;
4241 static uint64_t u64ElapsedPerSecNano = 0;
4242 static int cFrames = 0;
4243 uint64_t u64NanoTS = 0;
4244 if (LogRelIs3Enabled())
4245 u64NanoTS = RTTimeNanoTS();
4246 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4247 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4248 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4249 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4250 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4251 if (LogRelIs3Enabled())
4252 {
4253 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4254 u64ElapsedPerSecNano += u64ElapsedNano;
4255
4256 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
4257 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4258 (u64ElapsedNano) / 1000ULL, cRects,
4259 pFirstRect->left, pFirstRect->top,
4260 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4261
4262 ++cFrames;
4263 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4264 {
4265 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4266 cFrames, u64ElapsedPerSecNano / 1000ULL));
4267 u64FrameStartNanoTS = u64NanoTS;
4268 cFrames = 0;
4269 u64ElapsedPerSecNano = 0;
4270 }
4271 }
4272 break;
4273 }
4274
4275 case SVGA_3D_CMD_CONTEXT_DEFINE:
4276 {
4277 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
4278 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4279 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
4280
4281 vmsvga3dContextDefine(pThisCC, pCmd->cid);
4282 break;
4283 }
4284
4285 case SVGA_3D_CMD_CONTEXT_DESTROY:
4286 {
4287 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
4288 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4289 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
4290
4291 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4292 break;
4293 }
4294
4295 case SVGA_3D_CMD_SETTRANSFORM:
4296 {
4297 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
4298 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4299 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
4300
4301 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4302 break;
4303 }
4304
4305 case SVGA_3D_CMD_SETZRANGE:
4306 {
4307 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
4308 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4309 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
4310
4311 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4312 break;
4313 }
4314
4315 case SVGA_3D_CMD_SETRENDERSTATE:
4316 {
4317 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
4318 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4319 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
4320
4321 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4322 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4323 break;
4324 }
4325
4326 case SVGA_3D_CMD_SETRENDERTARGET:
4327 {
4328 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
4329 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4330 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
4331
4332 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4333 break;
4334 }
4335
4336 case SVGA_3D_CMD_SETTEXTURESTATE:
4337 {
4338 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
4339 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4340 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
4341
4342 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4343 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4344 break;
4345 }
4346
4347 case SVGA_3D_CMD_SETMATERIAL:
4348 {
4349 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
4350 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4351 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
4352
4353 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4354 break;
4355 }
4356
4357 case SVGA_3D_CMD_SETLIGHTDATA:
4358 {
4359 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
4360 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4361 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
4362
4363 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4364 break;
4365 }
4366
4367 case SVGA_3D_CMD_SETLIGHTENABLED:
4368 {
4369 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
4370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
4372
4373 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4374 break;
4375 }
4376
4377 case SVGA_3D_CMD_SETVIEWPORT:
4378 {
4379 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4380 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4382
4383 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4384 break;
4385 }
4386
4387 case SVGA_3D_CMD_SETCLIPPLANE:
4388 {
4389 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4390 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4391 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4392
4393 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4394 break;
4395 }
4396
4397 case SVGA_3D_CMD_CLEAR:
4398 {
4399 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4400 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4401 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4402
4403 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4404 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4405 break;
4406 }
4407
4408 case SVGA_3D_CMD_PRESENT:
4409 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4410 {
4411 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4412 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4413 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4414 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4415 else
4416 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4417
4418 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4419 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4420 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4421 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4422 break;
4423 }
4424
4425 case SVGA_3D_CMD_SHADER_DEFINE:
4426 {
4427 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4428 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4429 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4430
4431 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4432 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4433 break;
4434 }
4435
4436 case SVGA_3D_CMD_SHADER_DESTROY:
4437 {
4438 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4439 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4440 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4441
4442 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4443 break;
4444 }
4445
4446 case SVGA_3D_CMD_SET_SHADER:
4447 {
4448 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4449 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4450 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4451
4452 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4453 break;
4454 }
4455
4456 case SVGA_3D_CMD_SET_SHADER_CONST:
4457 {
4458 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4459 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4460 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4461
4462 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4463 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4464 break;
4465 }
4466
4467 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4468 {
4469 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4471 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4472
4473 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4474 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4475 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4476 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4477 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4478
4479 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4480 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4481 RT_UNTRUSTED_VALIDATED_FENCE();
4482
4483 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4484 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4485 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4486
4487 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4488 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4489 pNumRange, cVertexDivisor, pVertexDivisor);
4490 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4491 break;
4492 }
4493
4494 case SVGA_3D_CMD_SETSCISSORRECT:
4495 {
4496 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4497 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4498 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4499
4500 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4501 break;
4502 }
4503
4504 case SVGA_3D_CMD_BEGIN_QUERY:
4505 {
4506 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4507 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4508 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4509
4510 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4511 break;
4512 }
4513
4514 case SVGA_3D_CMD_END_QUERY:
4515 {
4516 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4517 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4518 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4519
4520 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
4521 break;
4522 }
4523
4524 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4525 {
4526 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4527 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4528 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4529
4530 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
4531 break;
4532 }
4533
4534 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4535 {
4536 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4537 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4538 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4539
4540 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4541 break;
4542 }
4543
4544 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4545 /* context id + surface id? */
4546 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4547 break;
4548
4549 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4550 /* context id + surface id? */
4551 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4552 break;
4553
4554 /*
4555 *
4556 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4557 *
4558 */
4559 case SVGA_3D_CMD_SCREEN_DMA:
4560 {
4561 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4563 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4564 break;
4565 }
4566
4567 case SVGA_3D_CMD_DEAD1:
4568 case SVGA_3D_CMD_DEAD2:
4569 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4570 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4571 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4572 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4573 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4574 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4575 {
4576 VMSVGA_3D_CMD_NOTIMPL();
4577 break;
4578 }
4579
4580 case SVGA_3D_CMD_SET_OTABLE_BASE:
4581 {
4582 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4583 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4585 break;
4586 }
4587
4588 case SVGA_3D_CMD_READBACK_OTABLE:
4589 {
4590 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4591 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4593 break;
4594 }
4595
4596 case SVGA_3D_CMD_DEFINE_GB_MOB:
4597 {
4598 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4599 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4601 break;
4602 }
4603
4604 case SVGA_3D_CMD_DESTROY_GB_MOB:
4605 {
4606 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4607 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4608 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4609 break;
4610 }
4611
4612 case SVGA_3D_CMD_DEAD3:
4613 {
4614 VMSVGA_3D_CMD_NOTIMPL();
4615 break;
4616 }
4617
4618 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4619 {
4620 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4622 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4623 break;
4624 }
4625
4626 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4627 {
4628 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4629 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4630 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4631 break;
4632 }
4633
4634 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4635 {
4636 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4637 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4638 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4639 break;
4640 }
4641
4642 case SVGA_3D_CMD_BIND_GB_SURFACE:
4643 {
4644 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4645 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4646 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4647 break;
4648 }
4649
4650 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4651 {
4652 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4654 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4655 break;
4656 }
4657
4658 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4659 {
4660 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4662 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4663 break;
4664 }
4665
4666 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4667 {
4668 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4669 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
4671 break;
4672 }
4673
4674 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4675 {
4676 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4677 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
4679 break;
4680 }
4681
4682 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4683 {
4684 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4685 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4686 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
4687 break;
4688 }
4689
4690 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4691 {
4692 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4693 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4694 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4695 break;
4696 }
4697
4698 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4699 {
4700 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4702 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4703 break;
4704 }
4705
4706 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4707 {
4708 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4711 break;
4712 }
4713
4714 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4715 {
4716 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4718 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4719 break;
4720 }
4721
4722 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4723 {
4724 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4725 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4726 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4727 break;
4728 }
4729
4730 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4731 {
4732 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4733 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4734 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4735 break;
4736 }
4737
4738 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4739 {
4740 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4742 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4743 break;
4744 }
4745
4746 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4747 {
4748 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4750 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4751 break;
4752 }
4753
4754 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4755 {
4756 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4758 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4759 break;
4760 }
4761
4762 case SVGA_3D_CMD_BIND_GB_SHADER:
4763 {
4764 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4765 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4766 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4767 break;
4768 }
4769
4770 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4771 {
4772 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4773 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4774 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4775 break;
4776 }
4777
4778 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4779 {
4780 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4781 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4782 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4783 break;
4784 }
4785
4786 case SVGA_3D_CMD_END_GB_QUERY:
4787 {
4788 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4789 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4790 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4791 break;
4792 }
4793
4794 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4795 {
4796 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4797 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4798 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4799 break;
4800 }
4801
4802 case SVGA_3D_CMD_NOP:
4803 {
4804 /* Apparently there is nothing to do. */
4805 break;
4806 }
4807
4808 case SVGA_3D_CMD_ENABLE_GART:
4809 {
4810 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4811 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4812 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4813 break;
4814 }
4815
4816 case SVGA_3D_CMD_DISABLE_GART:
4817 {
4818 /* No corresponding SVGA3dCmd structure. */
4819 VMSVGA_3D_CMD_NOTIMPL();
4820 break;
4821 }
4822
4823 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4824 {
4825 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4827 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4828 break;
4829 }
4830
4831 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4832 {
4833 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4835 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4836 break;
4837 }
4838
4839 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4840 {
4841 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4843 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4844 break;
4845 }
4846
4847 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4848 {
4849 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4851 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4852 break;
4853 }
4854
4855 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4856 {
4857 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4859 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4860 break;
4861 }
4862
4863 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4864 {
4865 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4867 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4868 break;
4869 }
4870
4871 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4872 {
4873 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4875 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4876 break;
4877 }
4878
4879 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4880 {
4881 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4883 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4884 break;
4885 }
4886
4887 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4888 {
4889 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4891 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4892 break;
4893 }
4894
4895 case SVGA_3D_CMD_GB_SCREEN_DMA:
4896 {
4897 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4899 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4900 break;
4901 }
4902
4903 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4904 {
4905 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4907 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4908 break;
4909 }
4910
4911 case SVGA_3D_CMD_GB_MOB_FENCE:
4912 {
4913 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4915 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4916 break;
4917 }
4918
4919 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4920 {
4921 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4923 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4924 break;
4925 }
4926
4927 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4928 {
4929 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4931 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4932 break;
4933 }
4934
4935 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4936 {
4937 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4939 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4940 break;
4941 }
4942
4943 case SVGA_3D_CMD_NOP_ERROR:
4944 {
4945 /* Apparently there is nothing to do. */
4946 break;
4947 }
4948
4949 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4950 {
4951 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4952 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4953 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4954 break;
4955 }
4956
4957 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4958 {
4959 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4960 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4961 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4962 break;
4963 }
4964
4965 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4966 {
4967 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4968 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4969 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4970 break;
4971 }
4972
4973 case SVGA_3D_CMD_DRAW:
4974 {
4975 /* No corresponding SVGA3dCmd structure. */
4976 VMSVGA_3D_CMD_NOTIMPL();
4977 break;
4978 }
4979
4980 case SVGA_3D_CMD_DRAW_INDEXED:
4981 {
4982 /* No corresponding SVGA3dCmd structure. */
4983 VMSVGA_3D_CMD_NOTIMPL();
4984 break;
4985 }
4986
4987 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4988 {
4989 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4991 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4992 break;
4993 }
4994
4995 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4996 {
4997 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4999 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5000 break;
5001 }
5002
5003 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5004 {
5005 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5008 break;
5009 }
5010
5011 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5012 {
5013 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5016 break;
5017 }
5018
5019 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5020 {
5021 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5023 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5024 break;
5025 }
5026
5027 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5028 {
5029 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5031 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5032 break;
5033 }
5034
5035 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5036 {
5037 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5039 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5040 break;
5041 }
5042
5043 case SVGA_3D_CMD_DX_SET_SHADER:
5044 {
5045 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5046 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5047 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5048 break;
5049 }
5050
5051 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5052 {
5053 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5054 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5055 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5056 break;
5057 }
5058
5059 case SVGA_3D_CMD_DX_DRAW:
5060 {
5061 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5064 break;
5065 }
5066
5067 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5068 {
5069 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5070 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5071 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5072 break;
5073 }
5074
5075 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5076 {
5077 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5080 break;
5081 }
5082
5083 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5084 {
5085 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5086 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5087 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5088 break;
5089 }
5090
5091 case SVGA_3D_CMD_DX_DRAW_AUTO:
5092 {
5093 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5094 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5095 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5096 break;
5097 }
5098
5099 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5100 {
5101 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5104 break;
5105 }
5106
5107 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5108 {
5109 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5110 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5111 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5112 break;
5113 }
5114
5115 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5116 {
5117 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5119 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5120 break;
5121 }
5122
5123 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5124 {
5125 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5126 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5127 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5128 break;
5129 }
5130
5131 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5132 {
5133 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5134 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5135 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5136 break;
5137 }
5138
5139 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5140 {
5141 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5143 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5144 break;
5145 }
5146
5147 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5148 {
5149 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5150 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5151 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5152 break;
5153 }
5154
5155 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5156 {
5157 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5158 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5159 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5160 break;
5161 }
5162
5163 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5164 {
5165 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5166 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5167 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5168 break;
5169 }
5170
5171 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5172 {
5173 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5175 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5176 break;
5177 }
5178
5179 case SVGA_3D_CMD_DX_BIND_QUERY:
5180 {
5181 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5183 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5184 break;
5185 }
5186
5187 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5188 {
5189 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5191 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5192 break;
5193 }
5194
5195 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5196 {
5197 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5198 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5199 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5200 break;
5201 }
5202
5203 case SVGA_3D_CMD_DX_END_QUERY:
5204 {
5205 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5206 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5207 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5208 break;
5209 }
5210
5211 case SVGA_3D_CMD_DX_READBACK_QUERY:
5212 {
5213 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5215 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5216 break;
5217 }
5218
5219 case SVGA_3D_CMD_DX_SET_PREDICATION:
5220 {
5221 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
5222 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5223 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
5224 break;
5225 }
5226
5227 case SVGA_3D_CMD_DX_SET_SOTARGETS:
5228 {
5229 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
5230 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5231 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
5232 break;
5233 }
5234
5235 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
5236 {
5237 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
5238 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5239 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
5240 break;
5241 }
5242
5243 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
5244 {
5245 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
5246 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5247 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
5248 break;
5249 }
5250
5251 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
5252 {
5253 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
5254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5255 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5256 break;
5257 }
5258
5259 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
5260 {
5261 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
5262 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5263 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5264 break;
5265 }
5266
5267 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
5268 {
5269 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
5270 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5271 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
5272 break;
5273 }
5274
5275 case SVGA_3D_CMD_DX_PRED_COPY:
5276 {
5277 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
5278 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5279 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
5280 break;
5281 }
5282
5283 case SVGA_3D_CMD_DX_PRESENTBLT:
5284 {
5285 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
5286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5287 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
5288 break;
5289 }
5290
5291 case SVGA_3D_CMD_DX_GENMIPS:
5292 {
5293 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
5294 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5295 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
5296 break;
5297 }
5298
5299 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
5300 {
5301 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
5302 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5303 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
5304 break;
5305 }
5306
5307 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
5308 {
5309 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
5310 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5311 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
5312 break;
5313 }
5314
5315 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
5316 {
5317 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
5318 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5319 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
5320 break;
5321 }
5322
5323 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
5324 {
5325 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
5326 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5327 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5328 break;
5329 }
5330
5331 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
5332 {
5333 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
5334 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5335 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
5336 break;
5337 }
5338
5339 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
5340 {
5341 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
5342 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5343 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5344 break;
5345 }
5346
5347 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
5348 {
5349 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
5350 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5351 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
5352 break;
5353 }
5354
5355 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
5356 {
5357 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
5358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5359 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5360 break;
5361 }
5362
5363 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
5364 {
5365 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
5366 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5367 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
5368 break;
5369 }
5370
5371 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
5372 {
5373 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
5374 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5375 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5376 break;
5377 }
5378
5379 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5380 {
5381 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5382 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5383 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5384 break;
5385 }
5386
5387 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5388 {
5389 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5390 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5391 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5392 break;
5393 }
5394
5395 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5396 {
5397 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5399 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5400 break;
5401 }
5402
5403 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5404 {
5405 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5406 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5407 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5408 break;
5409 }
5410
5411 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5412 {
5413 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5415 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5416 break;
5417 }
5418
5419 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5420 {
5421 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5422 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5423 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5424 break;
5425 }
5426
5427 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5428 {
5429 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5430 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5431 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5432 break;
5433 }
5434
5435 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5436 {
5437 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5438 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5439 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5440 break;
5441 }
5442
5443 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5444 {
5445 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5446 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5447 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5448 break;
5449 }
5450
5451 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5452 {
5453 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5454 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5455 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5456 break;
5457 }
5458
5459 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5460 {
5461 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5463 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5464 break;
5465 }
5466
5467 case SVGA_3D_CMD_DX_BIND_SHADER:
5468 {
5469 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5471 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5472 break;
5473 }
5474
5475 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5476 {
5477 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5479 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5480 break;
5481 }
5482
5483 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5484 {
5485 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5487 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5488 break;
5489 }
5490
5491 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5492 {
5493 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5494 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5495 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5496 break;
5497 }
5498
5499 case SVGA_3D_CMD_DX_SET_COTABLE:
5500 {
5501 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5502 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5503 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5504 break;
5505 }
5506
5507 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5508 {
5509 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5511 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5512 break;
5513 }
5514
5515 case SVGA_3D_CMD_DX_BUFFER_COPY:
5516 {
5517 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5519 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5520 break;
5521 }
5522
5523 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5524 {
5525 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5526 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5527 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
5528 break;
5529 }
5530
5531 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5532 {
5533 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5535 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5536 break;
5537 }
5538
5539 case SVGA_3D_CMD_DX_MOVE_QUERY:
5540 {
5541 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5543 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5544 break;
5545 }
5546
5547 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5548 {
5549 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5550 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5551 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5552 break;
5553 }
5554
5555 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5556 {
5557 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5559 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5560 break;
5561 }
5562
5563 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5564 {
5565 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5566 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5567 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5568 break;
5569 }
5570
5571 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5572 {
5573 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5574 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5575 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5576 break;
5577 }
5578
5579 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5580 {
5581 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5582 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5583 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5584 break;
5585 }
5586
5587 case SVGA_3D_CMD_DX_HINT:
5588 {
5589 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5591 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5592 break;
5593 }
5594
5595 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5596 {
5597 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5598 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5599 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5600 break;
5601 }
5602
5603 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5604 {
5605 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5606 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5607 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5608 break;
5609 }
5610
5611 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5612 {
5613 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5614 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5615 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5616 break;
5617 }
5618
5619 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5620 {
5621 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5622 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5623 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5624 break;
5625 }
5626
5627 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5628 {
5629 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5630 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5631 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5632 break;
5633 }
5634
5635 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5636 {
5637 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5638 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5639 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5640 break;
5641 }
5642
5643 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5644 {
5645 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5646 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5647 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5648 break;
5649 }
5650
5651 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5652 {
5653 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5654 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5655 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5656 break;
5657 }
5658
5659 case SVGA_3D_CMD_SCREEN_COPY:
5660 {
5661 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5662 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5663 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5664 break;
5665 }
5666
5667 case SVGA_3D_CMD_RESERVED1:
5668 {
5669 VMSVGA_3D_CMD_NOTIMPL();
5670 break;
5671 }
5672
5673 case SVGA_3D_CMD_RESERVED2:
5674 {
5675 VMSVGA_3D_CMD_NOTIMPL();
5676 break;
5677 }
5678
5679 case SVGA_3D_CMD_RESERVED3:
5680 {
5681 VMSVGA_3D_CMD_NOTIMPL();
5682 break;
5683 }
5684
5685 case SVGA_3D_CMD_RESERVED4:
5686 {
5687 VMSVGA_3D_CMD_NOTIMPL();
5688 break;
5689 }
5690
5691 case SVGA_3D_CMD_RESERVED5:
5692 {
5693 VMSVGA_3D_CMD_NOTIMPL();
5694 break;
5695 }
5696
5697 case SVGA_3D_CMD_RESERVED6:
5698 {
5699 VMSVGA_3D_CMD_NOTIMPL();
5700 break;
5701 }
5702
5703 case SVGA_3D_CMD_RESERVED7:
5704 {
5705 VMSVGA_3D_CMD_NOTIMPL();
5706 break;
5707 }
5708
5709 case SVGA_3D_CMD_RESERVED8:
5710 {
5711 VMSVGA_3D_CMD_NOTIMPL();
5712 break;
5713 }
5714
5715 case SVGA_3D_CMD_GROW_OTABLE:
5716 {
5717 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5718 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5719 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5720 break;
5721 }
5722
5723 case SVGA_3D_CMD_DX_GROW_COTABLE:
5724 {
5725 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5726 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5727 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5728 break;
5729 }
5730
5731 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5732 {
5733 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5734 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5735 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5736 break;
5737 }
5738
5739 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5740 {
5741 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5742 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5743 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5744 break;
5745 }
5746
5747 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5748 {
5749 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5750 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5751 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5752 break;
5753 }
5754
5755 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5756 {
5757 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5758 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5759 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5760 break;
5761 }
5762
5763 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5764 {
5765 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5766 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5767 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5768 break;
5769 }
5770
5771 case SVGA_3D_CMD_DX_PRED_CONVERT:
5772 {
5773 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5775 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5776 break;
5777 }
5778
5779 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5780 {
5781 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5782 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5783 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5784 break;
5785 }
5786
5787 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5788 {
5789 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5790 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5791 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5792 break;
5793 }
5794
5795 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5796 {
5797 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5799 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5800 break;
5801 }
5802
5803 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5804 {
5805 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5806 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5807 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5808 break;
5809 }
5810
5811 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5812 {
5813 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5814 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5815 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5816 break;
5817 }
5818
5819 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5820 {
5821 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5822 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5823 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5824 break;
5825 }
5826
5827 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5828 {
5829 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5830 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5831 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5832 break;
5833 }
5834
5835 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5836 {
5837 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5838 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5839 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5840 break;
5841 }
5842
5843 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5844 {
5845 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5846 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5847 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5848 break;
5849 }
5850
5851 case SVGA_3D_CMD_DX_DISPATCH:
5852 {
5853 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5854 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5855 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5856 break;
5857 }
5858
5859 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5860 {
5861 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5862 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5863 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5864 break;
5865 }
5866
5867 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5868 {
5869 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5870 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5871 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5872 break;
5873 }
5874
5875 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5876 {
5877 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5878 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5879 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5880 break;
5881 }
5882
5883 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5884 {
5885 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5886 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5887 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5888 break;
5889 }
5890
5891 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5892 {
5893 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5894 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5895 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5896 break;
5897 }
5898
5899 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5900 {
5901 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5903 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5904 break;
5905 }
5906
5907 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5908 {
5909 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5910 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5911 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5912 break;
5913 }
5914
5915 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5916 {
5917 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5919 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5920 break;
5921 }
5922
5923 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5924 {
5925 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5926 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5927 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5928 break;
5929 }
5930
5931 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5932 {
5933 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5934 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5935 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5936 break;
5937 }
5938
5939 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5940 {
5941 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5943 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5944 break;
5945 }
5946
5947 case SVGA_3D_CMD_RESERVED2_1:
5948 {
5949 VMSVGA_3D_CMD_NOTIMPL();
5950 break;
5951 }
5952
5953 case SVGA_3D_CMD_RESERVED2_2:
5954 {
5955 VMSVGA_3D_CMD_NOTIMPL();
5956 break;
5957 }
5958
5959 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5960 {
5961 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5963 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5964 break;
5965 }
5966
5967 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5968 {
5969 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5971 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5972 break;
5973 }
5974
5975 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5976 {
5977 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5979 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5980 break;
5981 }
5982
5983 case SVGA_3D_CMD_RESERVED2_3:
5984 {
5985 VMSVGA_3D_CMD_NOTIMPL();
5986 break;
5987 }
5988
5989 case SVGA_3D_CMD_RESERVED2_4:
5990 {
5991 VMSVGA_3D_CMD_NOTIMPL();
5992 break;
5993 }
5994
5995 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5996 {
5997 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5998 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5999 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6000 break;
6001 }
6002
6003 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6004 {
6005 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6006 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6007 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6008 break;
6009 }
6010
6011 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6012 {
6013 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6014 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6015 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6016 break;
6017 }
6018
6019 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6020 {
6021 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6022 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6023 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6024 break;
6025 }
6026
6027 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6028 {
6029 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6030 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6031 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6032 break;
6033 }
6034
6035 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6036 {
6037 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6038 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6039 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6040 break;
6041 }
6042
6043 /* Unsupported commands. */
6044 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
6045 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
6046 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
6047 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
6048 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
6049 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
6050 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
6051 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
6052 /* Prevent the compiler warning. */
6053 case SVGA_3D_CMD_LEGACY_BASE:
6054 case SVGA_3D_CMD_MAX:
6055 case SVGA_3D_CMD_FUTURE_MAX:
6056 /* No 'default' case */
6057 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
6058 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
6059 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
6060 rcParse = VERR_NOT_IMPLEMENTED;
6061 break;
6062 }
6063
6064 return VINF_SUCCESS;
6065// return rcParse;
6066}
6067# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
6068#endif /* VBOX_WITH_VMSVGA3D */
6069
6070
6071/*
6072 *
6073 * Handlers for FIFO commands.
6074 *
6075 * Every handler takes the following parameters:
6076 *
6077 * pThis The shared VGA/VMSVGA state.
6078 * pThisCC The VGA/VMSVGA state for ring-3.
6079 * pCmd The command data.
6080 */
6081
6082
6083/* SVGA_CMD_UPDATE */
6084void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
6085{
6086 RT_NOREF(pThis);
6087 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6088
6089 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
6090 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
6091
6092 /** @todo Multiple screens? */
6093 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6094 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6095 return;
6096
6097 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6098}
6099
6100
6101/* SVGA_CMD_UPDATE_VERBOSE */
6102void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
6103{
6104 RT_NOREF(pThis);
6105 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6106
6107 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
6108 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
6109
6110 /** @todo Multiple screens? */
6111 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6112 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
6113 return;
6114
6115 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
6116}
6117
6118
6119/* SVGA_CMD_RECT_FILL */
6120void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
6121{
6122 RT_NOREF(pThis, pCmd);
6123 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6124
6125 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
6126 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6127 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
6128}
6129
6130
6131/* SVGA_CMD_RECT_COPY */
6132void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
6133{
6134 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6135
6136 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
6137 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
6138
6139 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6140 AssertPtrReturnVoid(pScreen);
6141
6142 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6143 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6144 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6145 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6146 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6147 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6148 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6149
6150 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6151 pCmd->width, pCmd->height, pThis->vram_size);
6152 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6153}
6154
6155
6156/* SVGA_CMD_RECT_ROP_COPY */
6157void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
6158{
6159 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6160
6161 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
6162 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6163
6164 if (pCmd->rop != SVGA_ROP_COPY)
6165 {
6166 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
6167 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
6168 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
6169 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
6170 */
6171 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
6172 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
6173 return;
6174 }
6175
6176 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
6177 AssertPtrReturnVoid(pScreen);
6178
6179 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
6180 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
6181 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
6182 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
6183 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
6184 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
6185 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
6186
6187 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
6188 pCmd->width, pCmd->height, pThis->vram_size);
6189 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
6190}
6191
6192
6193/* SVGA_CMD_DISPLAY_CURSOR */
6194void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
6195{
6196 RT_NOREF(pThis, pCmd);
6197 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6198
6199 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
6200 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
6201 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
6202}
6203
6204
6205/* SVGA_CMD_MOVE_CURSOR */
6206void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
6207{
6208 RT_NOREF(pThis, pCmd);
6209 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6210
6211 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
6212 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
6213 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
6214}
6215
6216
6217/* SVGA_CMD_DEFINE_CURSOR */
6218void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
6219{
6220 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6221
6222 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
6223 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
6224 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
6225
6226 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6227 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
6228 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
6229 RT_UNTRUSTED_VALIDATED_FENCE();
6230
6231 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
6232 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
6233 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
6234
6235 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
6236 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
6237
6238 uint32_t const cx = pCmd->width;
6239 uint32_t const cy = pCmd->height;
6240
6241 /*
6242 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
6243 * The AND data uses 8-bit aligned scanlines.
6244 * The XOR data must be starting on a 32-bit boundrary.
6245 */
6246 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
6247 uint32_t cbDstAndMask = cbDstAndLine * cy;
6248 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
6249 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
6250
6251 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
6252 AssertReturnVoid(pbCopy);
6253
6254 /* Convert the AND mask. */
6255 uint8_t *pbDst = pbCopy;
6256 uint8_t const *pbSrc = pbSrcAndMask;
6257 switch (pCmd->andMaskDepth)
6258 {
6259 case 1:
6260 if (cbSrcAndLine == cbDstAndLine)
6261 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
6262 else
6263 {
6264 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
6265 for (uint32_t y = 0; y < cy; y++)
6266 {
6267 memcpy(pbDst, pbSrc, cbDstAndLine);
6268 pbDst += cbDstAndLine;
6269 pbSrc += cbSrcAndLine;
6270 }
6271 }
6272 break;
6273 /* Should take the XOR mask into account for the multi-bit AND mask. */
6274 case 8:
6275 for (uint32_t y = 0; y < cy; y++)
6276 {
6277 for (uint32_t x = 0; x < cx; )
6278 {
6279 uint8_t bDst = 0;
6280 uint8_t fBit = 0x80;
6281 do
6282 {
6283 uintptr_t const idxPal = pbSrc[x] * 3;
6284 if ((( pThis->last_palette[idxPal]
6285 | (pThis->last_palette[idxPal] >> 8)
6286 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
6287 bDst |= fBit;
6288 fBit >>= 1;
6289 x++;
6290 } while (x < cx && (x & 7));
6291 pbDst[(x - 1) / 8] = bDst;
6292 }
6293 pbDst += cbDstAndLine;
6294 pbSrc += cbSrcAndLine;
6295 }
6296 break;
6297 case 15:
6298 for (uint32_t y = 0; y < cy; y++)
6299 {
6300 for (uint32_t x = 0; x < cx; )
6301 {
6302 uint8_t bDst = 0;
6303 uint8_t fBit = 0x80;
6304 do
6305 {
6306 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
6307 bDst |= fBit;
6308 fBit >>= 1;
6309 x++;
6310 } while (x < cx && (x & 7));
6311 pbDst[(x - 1) / 8] = bDst;
6312 }
6313 pbDst += cbDstAndLine;
6314 pbSrc += cbSrcAndLine;
6315 }
6316 break;
6317 case 16:
6318 for (uint32_t y = 0; y < cy; y++)
6319 {
6320 for (uint32_t x = 0; x < cx; )
6321 {
6322 uint8_t bDst = 0;
6323 uint8_t fBit = 0x80;
6324 do
6325 {
6326 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
6327 bDst |= fBit;
6328 fBit >>= 1;
6329 x++;
6330 } while (x < cx && (x & 7));
6331 pbDst[(x - 1) / 8] = bDst;
6332 }
6333 pbDst += cbDstAndLine;
6334 pbSrc += cbSrcAndLine;
6335 }
6336 break;
6337 case 24:
6338 for (uint32_t y = 0; y < cy; y++)
6339 {
6340 for (uint32_t x = 0; x < cx; )
6341 {
6342 uint8_t bDst = 0;
6343 uint8_t fBit = 0x80;
6344 do
6345 {
6346 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
6347 bDst |= fBit;
6348 fBit >>= 1;
6349 x++;
6350 } while (x < cx && (x & 7));
6351 pbDst[(x - 1) / 8] = bDst;
6352 }
6353 pbDst += cbDstAndLine;
6354 pbSrc += cbSrcAndLine;
6355 }
6356 break;
6357 case 32:
6358 for (uint32_t y = 0; y < cy; y++)
6359 {
6360 for (uint32_t x = 0; x < cx; )
6361 {
6362 uint8_t bDst = 0;
6363 uint8_t fBit = 0x80;
6364 do
6365 {
6366 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
6367 bDst |= fBit;
6368 fBit >>= 1;
6369 x++;
6370 } while (x < cx && (x & 7));
6371 pbDst[(x - 1) / 8] = bDst;
6372 }
6373 pbDst += cbDstAndLine;
6374 pbSrc += cbSrcAndLine;
6375 }
6376 break;
6377 default:
6378 RTMemFreeZ(pbCopy, cbCopy);
6379 AssertFailedReturnVoid();
6380 }
6381
6382 /* Convert the XOR mask. */
6383 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6384 pbSrc = pbSrcXorMask;
6385 switch (pCmd->xorMaskDepth)
6386 {
6387 case 1:
6388 for (uint32_t y = 0; y < cy; y++)
6389 {
6390 for (uint32_t x = 0; x < cx; )
6391 {
6392 /* most significant bit is the left most one. */
6393 uint8_t bSrc = pbSrc[x / 8];
6394 do
6395 {
6396 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6397 bSrc <<= 1;
6398 x++;
6399 } while ((x & 7) && x < cx);
6400 }
6401 pbSrc += cbSrcXorLine;
6402 }
6403 break;
6404 case 8:
6405 for (uint32_t y = 0; y < cy; y++)
6406 {
6407 for (uint32_t x = 0; x < cx; x++)
6408 {
6409 uint32_t u = pThis->last_palette[pbSrc[x]];
6410 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6411 }
6412 pbSrc += cbSrcXorLine;
6413 }
6414 break;
6415 case 15: /* Src: RGB-5-5-5 */
6416 for (uint32_t y = 0; y < cy; y++)
6417 {
6418 for (uint32_t x = 0; x < cx; x++)
6419 {
6420 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6421 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6422 ((uValue >> 5) & 0x1f) << 3,
6423 ((uValue >> 10) & 0x1f) << 3, 0);
6424 }
6425 pbSrc += cbSrcXorLine;
6426 }
6427 break;
6428 case 16: /* Src: RGB-5-6-5 */
6429 for (uint32_t y = 0; y < cy; y++)
6430 {
6431 for (uint32_t x = 0; x < cx; x++)
6432 {
6433 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6434 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6435 ((uValue >> 5) & 0x3f) << 2,
6436 ((uValue >> 11) & 0x1f) << 3, 0);
6437 }
6438 pbSrc += cbSrcXorLine;
6439 }
6440 break;
6441 case 24:
6442 for (uint32_t y = 0; y < cy; y++)
6443 {
6444 for (uint32_t x = 0; x < cx; x++)
6445 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6446 pbSrc += cbSrcXorLine;
6447 }
6448 break;
6449 case 32:
6450 for (uint32_t y = 0; y < cy; y++)
6451 {
6452 for (uint32_t x = 0; x < cx; x++)
6453 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6454 pbSrc += cbSrcXorLine;
6455 }
6456 break;
6457 default:
6458 RTMemFreeZ(pbCopy, cbCopy);
6459 AssertFailedReturnVoid();
6460 }
6461
6462 /*
6463 * Pass it to the frontend/whatever.
6464 */
6465 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6466 cx, cy, pbCopy, cbCopy);
6467}
6468
6469
6470/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6471void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6472{
6473 RT_NOREF(pThis);
6474 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6475
6476 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6477 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6478
6479 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6480 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6481 RT_UNTRUSTED_VALIDATED_FENCE();
6482
6483 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6484 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6485 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6486 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6487 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6488
6489 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6490 AssertPtrReturnVoid(pCursorCopy);
6491
6492 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6493 memset(pCursorCopy, 0xff, cbAndMask);
6494 /* Colour data */
6495 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6496
6497 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6498 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6499}
6500
6501
6502/* SVGA_CMD_ESCAPE */
6503void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6504{
6505 RT_NOREF(pThis);
6506 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6507
6508 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6509
6510 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6511 {
6512 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6513 RT_UNTRUSTED_VALIDATED_FENCE();
6514
6515 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6516 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6517
6518 switch (cmd)
6519 {
6520 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6521 {
6522 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6523 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6524 RT_UNTRUSTED_VALIDATED_FENCE();
6525
6526 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6527
6528 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6529 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6530 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6531 RT_NOREF_PV(pVideoCmd);
6532 break;
6533 }
6534
6535 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6536 {
6537 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6538 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6539 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6540 RT_NOREF_PV(pVideoCmd);
6541 break;
6542 }
6543
6544 default:
6545 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6546 break;
6547 }
6548 }
6549 else
6550 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6551}
6552
6553
6554/* SVGA_CMD_DEFINE_SCREEN */
6555void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6556{
6557 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6558
6559 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6560 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6561 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6562 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6563
6564 uint32_t const idScreen = pCmd->screen.id;
6565 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6566
6567 uint32_t const uWidth = pCmd->screen.size.width;
6568 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6569
6570 uint32_t const uHeight = pCmd->screen.size.height;
6571 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6572
6573 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6574 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6575 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6576
6577 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6578 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6579
6580 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6581 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6582 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6583 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6584 RT_UNTRUSTED_VALIDATED_FENCE();
6585
6586 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6587 pScreen->fDefined = true;
6588 pScreen->fModified = true;
6589 pScreen->fuScreen = pCmd->screen.flags;
6590 pScreen->idScreen = idScreen;
6591 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6592 {
6593 /* Not blanked. */
6594 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6595 RT_UNTRUSTED_VALIDATED_FENCE();
6596
6597 pScreen->xOrigin = pCmd->screen.root.x;
6598 pScreen->yOrigin = pCmd->screen.root.y;
6599 pScreen->cWidth = uWidth;
6600 pScreen->cHeight = uHeight;
6601 pScreen->offVRAM = uScreenOffset;
6602 pScreen->cbPitch = cbPitch;
6603 pScreen->cBpp = 32;
6604 }
6605 else
6606 {
6607 /* Screen blanked. Keep old values. */
6608 }
6609
6610 pThis->svga.fGFBRegisters = false;
6611 vmsvgaR3ChangeMode(pThis, pThisCC);
6612
6613#ifdef VBOX_WITH_VMSVGA3D
6614 if (RT_LIKELY(pThis->svga.f3DEnabled))
6615 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6616#endif
6617}
6618
6619
6620/* SVGA_CMD_DESTROY_SCREEN */
6621void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6622{
6623 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6624
6625 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6626 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6627
6628 uint32_t const idScreen = pCmd->screenId;
6629 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6630 RT_UNTRUSTED_VALIDATED_FENCE();
6631
6632 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6633 pScreen->fModified = true;
6634 pScreen->fDefined = false;
6635 pScreen->idScreen = idScreen;
6636
6637#ifdef VBOX_WITH_VMSVGA3D
6638 if (RT_LIKELY(pThis->svga.f3DEnabled))
6639 vmsvga3dDestroyScreen(pThisCC, pScreen);
6640#endif
6641 vmsvgaR3ChangeMode(pThis, pThisCC);
6642}
6643
6644
6645/* SVGA_CMD_DEFINE_GMRFB */
6646void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6647{
6648 RT_NOREF(pThis);
6649 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6650
6651 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6652 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6653 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6654
6655 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6656 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6657 pSvgaR3State->GMRFB.format = pCmd->format;
6658}
6659
6660
6661/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6662void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6663{
6664 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6665
6666 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6667 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6668 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6669
6670 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6671 RT_UNTRUSTED_VALIDATED_FENCE();
6672
6673 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6674 AssertPtrReturnVoid(pScreen);
6675
6676 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6677 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6678
6679 /* Clip destRect to the screen dimensions. */
6680 SVGASignedRect screenRect;
6681 screenRect.left = 0;
6682 screenRect.top = 0;
6683 screenRect.right = pScreen->cWidth;
6684 screenRect.bottom = pScreen->cHeight;
6685 SVGASignedRect clipRect = pCmd->destRect;
6686 vmsvgaR3ClipRect(&screenRect, &clipRect);
6687 RT_UNTRUSTED_VALIDATED_FENCE();
6688
6689 uint32_t const width = clipRect.right - clipRect.left;
6690 uint32_t const height = clipRect.bottom - clipRect.top;
6691
6692 if ( width == 0
6693 || height == 0)
6694 return; /* Nothing to do. */
6695
6696 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6697 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6698
6699 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6700 * Prepare parameters for vmsvgaR3GmrTransfer.
6701 */
6702 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6703
6704 /* Destination: host buffer which describes the screen 0 VRAM.
6705 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6706 */
6707 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6708 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6709 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6710 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6711 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6712 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6713 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6714 + cbScanline * clipRect.top;
6715 int32_t const cbHstPitch = cbScanline;
6716
6717 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6718 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6719 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6720 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6721 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6722
6723 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6724 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6725 gstPtr, offGst, cbGstPitch,
6726 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6727 AssertRC(rc);
6728 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6729}
6730
6731
6732/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6733void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6734{
6735 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6736
6737 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6738 /* Note! This can fetch 3d render results as well!! */
6739 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6740 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6741
6742 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6743 RT_UNTRUSTED_VALIDATED_FENCE();
6744
6745 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6746 AssertPtrReturnVoid(pScreen);
6747
6748 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6749 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6750
6751 /* Clip destRect to the screen dimensions. */
6752 SVGASignedRect screenRect;
6753 screenRect.left = 0;
6754 screenRect.top = 0;
6755 screenRect.right = pScreen->cWidth;
6756 screenRect.bottom = pScreen->cHeight;
6757 SVGASignedRect clipRect = pCmd->srcRect;
6758 vmsvgaR3ClipRect(&screenRect, &clipRect);
6759 RT_UNTRUSTED_VALIDATED_FENCE();
6760
6761 uint32_t const width = clipRect.right - clipRect.left;
6762 uint32_t const height = clipRect.bottom - clipRect.top;
6763
6764 if ( width == 0
6765 || height == 0)
6766 return; /* Nothing to do. */
6767
6768 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6769 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6770
6771 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6772 * Prepare parameters for vmsvgaR3GmrTransfer.
6773 */
6774 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6775
6776 /* Source: host buffer which describes the screen 0 VRAM.
6777 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6778 */
6779 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6780 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6781 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6782 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6783 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6784 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6785 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6786 + cbScanline * clipRect.top;
6787 int32_t const cbHstPitch = cbScanline;
6788
6789 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6790 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6791 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6792 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6793 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6794
6795 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6796 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6797 gstPtr, offGst, cbGstPitch,
6798 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6799 AssertRC(rc);
6800}
6801
6802
6803/* SVGA_CMD_ANNOTATION_FILL */
6804void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6805{
6806 RT_NOREF(pThis);
6807 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6808
6809 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6810 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6811
6812 pSvgaR3State->colorAnnotation = pCmd->color;
6813}
6814
6815
6816/* SVGA_CMD_ANNOTATION_COPY */
6817void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6818{
6819 RT_NOREF(pThis, pCmd);
6820 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6821
6822 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6823 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6824
6825 AssertFailed();
6826}
6827
6828
6829#ifdef VBOX_WITH_VMSVGA3D
6830/* SVGA_CMD_DEFINE_GMR2 */
6831void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6832{
6833 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6834
6835 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6836 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6837
6838 /* Validate current GMR id. */
6839 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6840 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6841 RT_UNTRUSTED_VALIDATED_FENCE();
6842
6843 if (!pCmd->numPages)
6844 {
6845 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6846 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6847 }
6848 else
6849 {
6850 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6851 if (pGMR->cMaxPages)
6852 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6853
6854 /* Not sure if we should always free the descriptor, but for simplicity
6855 we do so if the new size is smaller than the current. */
6856 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6857 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
6858 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6859
6860 pGMR->cMaxPages = pCmd->numPages;
6861 /* The rest is done by the REMAP_GMR2 command. */
6862 }
6863}
6864
6865
6866/* SVGA_CMD_REMAP_GMR2 */
6867void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6868{
6869 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6870
6871 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6872 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6873
6874 /* Validate current GMR id and size. */
6875 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6876 RT_UNTRUSTED_VALIDATED_FENCE();
6877 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6878 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6879 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6880 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6881
6882 if (pCmd->numPages == 0)
6883 return;
6884 RT_UNTRUSTED_VALIDATED_FENCE();
6885
6886 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6887 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6888
6889 /*
6890 * We flatten the existing descriptors into a page array, overwrite the
6891 * pages specified in this command and then recompress the descriptor.
6892 */
6893 /** @todo Optimize the GMR remap algorithm! */
6894
6895 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6896 uint64_t *paNewPage64 = NULL;
6897 if (pGMR->paDesc)
6898 {
6899 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6900
6901 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6902 AssertPtrReturnVoid(paNewPage64);
6903
6904 uint32_t idxPage = 0;
6905 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6906 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6907 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6908 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6909 RT_UNTRUSTED_VALIDATED_FENCE();
6910 }
6911
6912 /* Free the old GMR if present. */
6913 if (pGMR->paDesc)
6914 RTMemFree(pGMR->paDesc);
6915
6916 /* Allocate the maximum amount possible (everything non-continuous) */
6917 PVMSVGAGMRDESCRIPTOR paDescs;
6918 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6919 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6920
6921 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6922 {
6923 /** @todo */
6924 AssertFailed();
6925 pGMR->numDescriptors = 0;
6926 }
6927 else
6928 {
6929 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6930 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6931 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6932
6933 uint32_t cPages;
6934 if (paNewPage64)
6935 {
6936 /* Overwrite the old page array with the new page values. */
6937 if (fGCPhys64)
6938 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6939 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6940 else
6941 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6942 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6943
6944 /* Use the updated page array instead of the command data. */
6945 fGCPhys64 = true;
6946 paPages64 = paNewPage64;
6947 cPages = cNewTotalPages;
6948 }
6949 else
6950 cPages = pCmd->numPages;
6951
6952 /* The first page. */
6953 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6954 * applied to paNewPage64. */
6955 RTGCPHYS GCPhys;
6956 if (fGCPhys64)
6957 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6958 else
6959 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
6960 paDescs[0].GCPhys = GCPhys;
6961 paDescs[0].numPages = 1;
6962
6963 /* Subsequent pages. */
6964 uint32_t iDescriptor = 0;
6965 for (uint32_t i = 1; i < cPages; i++)
6966 {
6967 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6968 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6969 else
6970 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6971
6972 /* Continuous physical memory? */
6973 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6974 {
6975 Assert(paDescs[iDescriptor].numPages);
6976 paDescs[iDescriptor].numPages++;
6977 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6978 }
6979 else
6980 {
6981 iDescriptor++;
6982 paDescs[iDescriptor].GCPhys = GCPhys;
6983 paDescs[iDescriptor].numPages = 1;
6984 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6985 }
6986 }
6987
6988 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6989 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6990 pGMR->numDescriptors = iDescriptor + 1;
6991 }
6992
6993 if (paNewPage64)
6994 RTMemFree(paNewPage64);
6995}
6996
6997
6998/**
6999 * Free the specified GMR
7000 *
7001 * @param pThisCC The VGA/VMSVGA state for ring-3.
7002 * @param idGMR GMR id
7003 */
7004void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
7005{
7006 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7007
7008 /* Free the old descriptor if present. */
7009 PGMR pGMR = &pSVGAState->paGMR[idGMR];
7010 if ( pGMR->numDescriptors
7011 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
7012 {
7013# ifdef DEBUG_GMR_ACCESS
7014 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
7015# endif
7016
7017 Assert(pGMR->paDesc);
7018 RTMemFree(pGMR->paDesc);
7019 pGMR->paDesc = NULL;
7020 pGMR->numDescriptors = 0;
7021 pGMR->cbTotal = 0;
7022 pGMR->cMaxPages = 0;
7023 }
7024 Assert(!pGMR->cMaxPages);
7025 Assert(!pGMR->cbTotal);
7026}
7027#endif /* VBOX_WITH_VMSVGA3D */
7028
7029
7030/**
7031 * Copy between a GMR and a host memory buffer.
7032 *
7033 * @returns VBox status code.
7034 * @param pThis The shared VGA/VMSVGA instance data.
7035 * @param pThisCC The VGA/VMSVGA state for ring-3.
7036 * @param enmTransferType Transfer type (read/write)
7037 * @param pbHstBuf Host buffer pointer (valid)
7038 * @param cbHstBuf Size of host buffer (valid)
7039 * @param offHst Host buffer offset of the first scanline
7040 * @param cbHstPitch Destination buffer pitch
7041 * @param gstPtr GMR description
7042 * @param offGst Guest buffer offset of the first scanline
7043 * @param cbGstPitch Guest buffer pitch
7044 * @param cbWidth Width in bytes to copy
7045 * @param cHeight Number of scanllines to copy
7046 */
7047int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
7048 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
7049 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
7050 uint32_t cbWidth, uint32_t cHeight)
7051{
7052 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7053 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
7054 int rc;
7055
7056 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
7057 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
7058 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7059 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
7060 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
7061
7062 PGMR pGMR;
7063 uint32_t cbGmr; /* The GMR size in bytes. */
7064 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7065 {
7066 pGMR = NULL;
7067 cbGmr = pThis->vram_size;
7068 }
7069 else
7070 {
7071 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
7072 RT_UNTRUSTED_VALIDATED_FENCE();
7073 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
7074 cbGmr = pGMR->cbTotal;
7075 }
7076
7077 /*
7078 * GMR
7079 */
7080 /* Calculate GMR offset of the data to be copied. */
7081 AssertMsgReturn(gstPtr.offset < cbGmr,
7082 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7083 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7084 VERR_INVALID_PARAMETER);
7085 RT_UNTRUSTED_VALIDATED_FENCE();
7086 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
7087 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7088 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7089 VERR_INVALID_PARAMETER);
7090 RT_UNTRUSTED_VALIDATED_FENCE();
7091 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
7092
7093 /* Verify that cbWidth is less than scanline and fits into the GMR. */
7094 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
7095 AssertMsgReturn(cbGmrScanline != 0,
7096 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7097 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7098 VERR_INVALID_PARAMETER);
7099 RT_UNTRUSTED_VALIDATED_FENCE();
7100 AssertMsgReturn(cbWidth <= cbGmrScanline,
7101 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7102 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7103 VERR_INVALID_PARAMETER);
7104 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
7105 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7106 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7107 VERR_INVALID_PARAMETER);
7108 RT_UNTRUSTED_VALIDATED_FENCE();
7109
7110 /* How many bytes are available for the data in the GMR. */
7111 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
7112
7113 /* How many scanlines would fit into the available data. */
7114 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
7115 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
7116 if (cbWidth <= cbGmrLastScanline)
7117 ++cGmrScanlines;
7118
7119 if (cHeight > cGmrScanlines)
7120 cHeight = cGmrScanlines;
7121
7122 AssertMsgReturn(cHeight > 0,
7123 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
7124 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
7125 VERR_INVALID_PARAMETER);
7126 RT_UNTRUSTED_VALIDATED_FENCE();
7127
7128 /*
7129 * Host buffer.
7130 */
7131 AssertMsgReturn(offHst < cbHstBuf,
7132 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7133 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7134 VERR_INVALID_PARAMETER);
7135
7136 /* Verify that cbWidth is less than scanline and fits into the buffer. */
7137 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
7138 AssertMsgReturn(cbHstScanline != 0,
7139 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7140 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7141 VERR_INVALID_PARAMETER);
7142 AssertMsgReturn(cbWidth <= cbHstScanline,
7143 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7144 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7145 VERR_INVALID_PARAMETER);
7146 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
7147 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7148 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7149 VERR_INVALID_PARAMETER);
7150
7151 /* How many bytes are available for the data in the buffer. */
7152 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
7153
7154 /* How many scanlines would fit into the available data. */
7155 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
7156 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
7157 if (cbWidth <= cbHstLastScanline)
7158 ++cHstScanlines;
7159
7160 if (cHeight > cHstScanlines)
7161 cHeight = cHstScanlines;
7162
7163 AssertMsgReturn(cHeight > 0,
7164 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
7165 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
7166 VERR_INVALID_PARAMETER);
7167
7168 uint8_t *pbHst = pbHstBuf + offHst;
7169
7170 /* Shortcut for the framebuffer. */
7171 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
7172 {
7173 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
7174
7175 uint8_t const *pbSrc;
7176 int32_t cbSrcPitch;
7177 uint8_t *pbDst;
7178 int32_t cbDstPitch;
7179
7180 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
7181 {
7182 pbSrc = pbHst;
7183 cbSrcPitch = cbHstPitch;
7184 pbDst = pbGst;
7185 cbDstPitch = cbGstPitch;
7186 }
7187 else
7188 {
7189 pbSrc = pbGst;
7190 cbSrcPitch = cbGstPitch;
7191 pbDst = pbHst;
7192 cbDstPitch = cbHstPitch;
7193 }
7194
7195 if ( cbWidth == (uint32_t)cbGstPitch
7196 && cbGstPitch == cbHstPitch)
7197 {
7198 /* Entire scanlines, positive pitch. */
7199 memcpy(pbDst, pbSrc, cbWidth * cHeight);
7200 }
7201 else
7202 {
7203 for (uint32_t i = 0; i < cHeight; ++i)
7204 {
7205 memcpy(pbDst, pbSrc, cbWidth);
7206
7207 pbDst += cbDstPitch;
7208 pbSrc += cbSrcPitch;
7209 }
7210 }
7211 return VINF_SUCCESS;
7212 }
7213
7214 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
7215 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
7216
7217 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
7218 uint32_t iDesc = 0; /* Index in the descriptor array. */
7219 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
7220 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
7221 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
7222 for (uint32_t i = 0; i < cHeight; ++i)
7223 {
7224 uint32_t cbCurrentWidth = cbWidth;
7225 uint32_t offGmrCurrent = offGmrScanline;
7226 uint8_t *pbCurrentHost = pbHstScanline;
7227
7228 /* Find the right descriptor */
7229 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
7230 {
7231 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7232 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
7233 ++iDesc;
7234 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7235 }
7236
7237 while (cbCurrentWidth)
7238 {
7239 uint32_t cbToCopy;
7240
7241 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
7242 cbToCopy = cbCurrentWidth;
7243 else
7244 {
7245 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
7246 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
7247 }
7248
7249 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
7250
7251 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
7252
7253 /*
7254 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
7255 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
7256 * see @bugref{9654#c75}.
7257 */
7258 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
7259 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7260 else
7261 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
7262 AssertRCBreak(rc);
7263
7264 cbCurrentWidth -= cbToCopy;
7265 offGmrCurrent += cbToCopy;
7266 pbCurrentHost += cbToCopy;
7267
7268 /* Go to the next descriptor if there's anything left. */
7269 if (cbCurrentWidth)
7270 {
7271 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
7272 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
7273 ++iDesc;
7274 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
7275 }
7276 }
7277
7278 offGmrScanline += cbGstPitch;
7279 pbHstScanline += cbHstPitch;
7280 }
7281
7282 return VINF_SUCCESS;
7283}
7284
7285
7286/**
7287 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
7288 *
7289 * @param pSizeSrc Source surface dimensions.
7290 * @param pSizeDest Destination surface dimensions.
7291 * @param pBox Coordinates to be clipped.
7292 */
7293void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
7294{
7295 /* Src x, w */
7296 if (pBox->srcx > pSizeSrc->width)
7297 pBox->srcx = pSizeSrc->width;
7298 if (pBox->w > pSizeSrc->width - pBox->srcx)
7299 pBox->w = pSizeSrc->width - pBox->srcx;
7300
7301 /* Src y, h */
7302 if (pBox->srcy > pSizeSrc->height)
7303 pBox->srcy = pSizeSrc->height;
7304 if (pBox->h > pSizeSrc->height - pBox->srcy)
7305 pBox->h = pSizeSrc->height - pBox->srcy;
7306
7307 /* Src z, d */
7308 if (pBox->srcz > pSizeSrc->depth)
7309 pBox->srcz = pSizeSrc->depth;
7310 if (pBox->d > pSizeSrc->depth - pBox->srcz)
7311 pBox->d = pSizeSrc->depth - pBox->srcz;
7312
7313 /* Dest x, w */
7314 if (pBox->x > pSizeDest->width)
7315 pBox->x = pSizeDest->width;
7316 if (pBox->w > pSizeDest->width - pBox->x)
7317 pBox->w = pSizeDest->width - pBox->x;
7318
7319 /* Dest y, h */
7320 if (pBox->y > pSizeDest->height)
7321 pBox->y = pSizeDest->height;
7322 if (pBox->h > pSizeDest->height - pBox->y)
7323 pBox->h = pSizeDest->height - pBox->y;
7324
7325 /* Dest z, d */
7326 if (pBox->z > pSizeDest->depth)
7327 pBox->z = pSizeDest->depth;
7328 if (pBox->d > pSizeDest->depth - pBox->z)
7329 pBox->d = pSizeDest->depth - pBox->z;
7330}
7331
7332
7333/**
7334 * Unsigned coordinates in pBox. Clip to [0; pSize).
7335 *
7336 * @param pSize Source surface dimensions.
7337 * @param pBox Coordinates to be clipped.
7338 */
7339void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
7340{
7341 /* x, w */
7342 if (pBox->x > pSize->width)
7343 pBox->x = pSize->width;
7344 if (pBox->w > pSize->width - pBox->x)
7345 pBox->w = pSize->width - pBox->x;
7346
7347 /* y, h */
7348 if (pBox->y > pSize->height)
7349 pBox->y = pSize->height;
7350 if (pBox->h > pSize->height - pBox->y)
7351 pBox->h = pSize->height - pBox->y;
7352
7353 /* z, d */
7354 if (pBox->z > pSize->depth)
7355 pBox->z = pSize->depth;
7356 if (pBox->d > pSize->depth - pBox->z)
7357 pBox->d = pSize->depth - pBox->z;
7358}
7359
7360
7361/**
7362 * Clip.
7363 *
7364 * @param pBound Bounding rectangle.
7365 * @param pRect Rectangle to be clipped.
7366 */
7367void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
7368{
7369 int32_t left;
7370 int32_t top;
7371 int32_t right;
7372 int32_t bottom;
7373
7374 /* Right order. */
7375 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
7376 if (pRect->left < pRect->right)
7377 {
7378 left = pRect->left;
7379 right = pRect->right;
7380 }
7381 else
7382 {
7383 left = pRect->right;
7384 right = pRect->left;
7385 }
7386 if (pRect->top < pRect->bottom)
7387 {
7388 top = pRect->top;
7389 bottom = pRect->bottom;
7390 }
7391 else
7392 {
7393 top = pRect->bottom;
7394 bottom = pRect->top;
7395 }
7396
7397 if (left < pBound->left)
7398 left = pBound->left;
7399 if (right < pBound->left)
7400 right = pBound->left;
7401
7402 if (left > pBound->right)
7403 left = pBound->right;
7404 if (right > pBound->right)
7405 right = pBound->right;
7406
7407 if (top < pBound->top)
7408 top = pBound->top;
7409 if (bottom < pBound->top)
7410 bottom = pBound->top;
7411
7412 if (top > pBound->bottom)
7413 top = pBound->bottom;
7414 if (bottom > pBound->bottom)
7415 bottom = pBound->bottom;
7416
7417 pRect->left = left;
7418 pRect->right = right;
7419 pRect->top = top;
7420 pRect->bottom = bottom;
7421}
7422
7423
7424/**
7425 * Clip.
7426 *
7427 * @param pBound Bounding rectangle.
7428 * @param pRect Rectangle to be clipped.
7429 */
7430void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7431{
7432 uint32_t const leftBound = pBound->x;
7433 uint32_t const rightBound = pBound->x + pBound->w;
7434 uint32_t const topBound = pBound->y;
7435 uint32_t const bottomBound = pBound->y + pBound->h;
7436
7437 uint32_t x = pRect->x;
7438 uint32_t y = pRect->y;
7439 uint32_t w = pRect->w;
7440 uint32_t h = pRect->h;
7441
7442 /* Make sure that right and bottom coordinates can be safely computed. */
7443 if (x > rightBound)
7444 x = rightBound;
7445 if (w > rightBound - x)
7446 w = rightBound - x;
7447 if (y > bottomBound)
7448 y = bottomBound;
7449 if (h > bottomBound - y)
7450 h = bottomBound - y;
7451
7452 /* Switch from x, y, w, h to left, top, right, bottom. */
7453 uint32_t left = x;
7454 uint32_t right = x + w;
7455 uint32_t top = y;
7456 uint32_t bottom = y + h;
7457
7458 /* A standard left, right, bottom, top clipping. */
7459 if (left < leftBound)
7460 left = leftBound;
7461 if (right < leftBound)
7462 right = leftBound;
7463
7464 if (left > rightBound)
7465 left = rightBound;
7466 if (right > rightBound)
7467 right = rightBound;
7468
7469 if (top < topBound)
7470 top = topBound;
7471 if (bottom < topBound)
7472 bottom = topBound;
7473
7474 if (top > bottomBound)
7475 top = bottomBound;
7476 if (bottom > bottomBound)
7477 bottom = bottomBound;
7478
7479 /* Back to x, y, w, h representation. */
7480 pRect->x = left;
7481 pRect->y = top;
7482 pRect->w = right - left;
7483 pRect->h = bottom - top;
7484}
7485
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