VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 63277

Last change on this file since 63277 was 63218, checked in by vboxsync, 9 years ago

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1/* $Id: DevVGA-SVGA.cpp 63218 2016-08-09 15:52:35Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2016 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295#ifdef LOG_ENABLED
296
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417#ifdef IN_RING3
418/**
419 * FIFO command name lookup
420 *
421 * @returns FIFO command string or "UNKNOWN"
422 * @param u32Cmd FIFO command
423 */
424static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
425{
426 switch (u32Cmd)
427 {
428 case SVGA_CMD_INVALID_CMD:
429 return "SVGA_CMD_INVALID_CMD";
430 case SVGA_CMD_UPDATE:
431 return "SVGA_CMD_UPDATE";
432 case SVGA_CMD_RECT_COPY:
433 return "SVGA_CMD_RECT_COPY";
434 case SVGA_CMD_DEFINE_CURSOR:
435 return "SVGA_CMD_DEFINE_CURSOR";
436 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
437 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
438 case SVGA_CMD_UPDATE_VERBOSE:
439 return "SVGA_CMD_UPDATE_VERBOSE";
440 case SVGA_CMD_FRONT_ROP_FILL:
441 return "SVGA_CMD_FRONT_ROP_FILL";
442 case SVGA_CMD_FENCE:
443 return "SVGA_CMD_FENCE";
444 case SVGA_CMD_ESCAPE:
445 return "SVGA_CMD_ESCAPE";
446 case SVGA_CMD_DEFINE_SCREEN:
447 return "SVGA_CMD_DEFINE_SCREEN";
448 case SVGA_CMD_DESTROY_SCREEN:
449 return "SVGA_CMD_DESTROY_SCREEN";
450 case SVGA_CMD_DEFINE_GMRFB:
451 return "SVGA_CMD_DEFINE_GMRFB";
452 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
453 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
454 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
455 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
456 case SVGA_CMD_ANNOTATION_FILL:
457 return "SVGA_CMD_ANNOTATION_FILL";
458 case SVGA_CMD_ANNOTATION_COPY:
459 return "SVGA_CMD_ANNOTATION_COPY";
460 case SVGA_CMD_DEFINE_GMR2:
461 return "SVGA_CMD_DEFINE_GMR2";
462 case SVGA_CMD_REMAP_GMR2:
463 return "SVGA_CMD_REMAP_GMR2";
464 case SVGA_3D_CMD_SURFACE_DEFINE:
465 return "SVGA_3D_CMD_SURFACE_DEFINE";
466 case SVGA_3D_CMD_SURFACE_DESTROY:
467 return "SVGA_3D_CMD_SURFACE_DESTROY";
468 case SVGA_3D_CMD_SURFACE_COPY:
469 return "SVGA_3D_CMD_SURFACE_COPY";
470 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
471 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
472 case SVGA_3D_CMD_SURFACE_DMA:
473 return "SVGA_3D_CMD_SURFACE_DMA";
474 case SVGA_3D_CMD_CONTEXT_DEFINE:
475 return "SVGA_3D_CMD_CONTEXT_DEFINE";
476 case SVGA_3D_CMD_CONTEXT_DESTROY:
477 return "SVGA_3D_CMD_CONTEXT_DESTROY";
478 case SVGA_3D_CMD_SETTRANSFORM:
479 return "SVGA_3D_CMD_SETTRANSFORM";
480 case SVGA_3D_CMD_SETZRANGE:
481 return "SVGA_3D_CMD_SETZRANGE";
482 case SVGA_3D_CMD_SETRENDERSTATE:
483 return "SVGA_3D_CMD_SETRENDERSTATE";
484 case SVGA_3D_CMD_SETRENDERTARGET:
485 return "SVGA_3D_CMD_SETRENDERTARGET";
486 case SVGA_3D_CMD_SETTEXTURESTATE:
487 return "SVGA_3D_CMD_SETTEXTURESTATE";
488 case SVGA_3D_CMD_SETMATERIAL:
489 return "SVGA_3D_CMD_SETMATERIAL";
490 case SVGA_3D_CMD_SETLIGHTDATA:
491 return "SVGA_3D_CMD_SETLIGHTDATA";
492 case SVGA_3D_CMD_SETLIGHTENABLED:
493 return "SVGA_3D_CMD_SETLIGHTENABLED";
494 case SVGA_3D_CMD_SETVIEWPORT:
495 return "SVGA_3D_CMD_SETVIEWPORT";
496 case SVGA_3D_CMD_SETCLIPPLANE:
497 return "SVGA_3D_CMD_SETCLIPPLANE";
498 case SVGA_3D_CMD_CLEAR:
499 return "SVGA_3D_CMD_CLEAR";
500 case SVGA_3D_CMD_PRESENT:
501 return "SVGA_3D_CMD_PRESENT";
502 case SVGA_3D_CMD_SHADER_DEFINE:
503 return "SVGA_3D_CMD_SHADER_DEFINE";
504 case SVGA_3D_CMD_SHADER_DESTROY:
505 return "SVGA_3D_CMD_SHADER_DESTROY";
506 case SVGA_3D_CMD_SET_SHADER:
507 return "SVGA_3D_CMD_SET_SHADER";
508 case SVGA_3D_CMD_SET_SHADER_CONST:
509 return "SVGA_3D_CMD_SET_SHADER_CONST";
510 case SVGA_3D_CMD_DRAW_PRIMITIVES:
511 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
512 case SVGA_3D_CMD_SETSCISSORRECT:
513 return "SVGA_3D_CMD_SETSCISSORRECT";
514 case SVGA_3D_CMD_BEGIN_QUERY:
515 return "SVGA_3D_CMD_BEGIN_QUERY";
516 case SVGA_3D_CMD_END_QUERY:
517 return "SVGA_3D_CMD_END_QUERY";
518 case SVGA_3D_CMD_WAIT_FOR_QUERY:
519 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
520 case SVGA_3D_CMD_PRESENT_READBACK:
521 return "SVGA_3D_CMD_PRESENT_READBACK";
522 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
523 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
524 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
525 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
526 case SVGA_3D_CMD_GENERATE_MIPMAPS:
527 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
528 case SVGA_3D_CMD_ACTIVATE_SURFACE:
529 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
530 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
531 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
532 default:
533 return "UNKNOWN";
534 }
535}
536# endif /* IN_RING3 */
537
538#endif /* LOG_ENABLED */
539
540#ifdef IN_RING3
541/**
542 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
543 */
544DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
545{
546 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
547
548 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
549 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
550
551 if (x < pThis->svga.uWidth)
552 {
553 pThis->svga.viewport.x = x;
554 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
555 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
556 }
557 else
558 {
559 pThis->svga.viewport.x = pThis->svga.uWidth;
560 pThis->svga.viewport.cx = 0;
561 pThis->svga.viewport.xRight = pThis->svga.uWidth;
562 }
563 if (y < pThis->svga.uHeight)
564 {
565 pThis->svga.viewport.y = y;
566 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
567 pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
568 pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
569 }
570 else
571 {
572 pThis->svga.viewport.y = pThis->svga.uHeight;
573 pThis->svga.viewport.cy = 0;
574 pThis->svga.viewport.yLowWC = 0;
575 pThis->svga.viewport.yHighWC = 0;
576 }
577
578# ifdef VBOX_WITH_VMSVGA3D
579 /*
580 * Now inform the 3D backend.
581 */
582 if (pThis->svga.f3DEnabled)
583 vmsvga3dUpdateHostScreenViewport(pThis, uScreenId, &OldViewport);
584# endif
585}
586#endif /* IN_RING3 */
587
588/**
589 * Read port register
590 *
591 * @returns VBox status code.
592 * @param pThis VMSVGA State
593 * @param pu32 Where to store the read value
594 */
595PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
596{
597 int rc = VINF_SUCCESS;
598
599 *pu32 = 0;
600 switch (pThis->svga.u32IndexReg)
601 {
602 case SVGA_REG_ID:
603 *pu32 = pThis->svga.u32SVGAId;
604 break;
605
606 case SVGA_REG_ENABLE:
607 *pu32 = pThis->svga.fEnabled;
608 break;
609
610 case SVGA_REG_WIDTH:
611 {
612 if ( pThis->svga.fEnabled
613 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
614 {
615 *pu32 = pThis->svga.uWidth;
616 }
617 else
618 {
619#ifndef IN_RING3
620 rc = VINF_IOM_R3_IOPORT_READ;
621#else
622 *pu32 = pThis->pDrv->cx;
623#endif
624 }
625 break;
626 }
627
628 case SVGA_REG_HEIGHT:
629 {
630 if ( pThis->svga.fEnabled
631 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
632 {
633 *pu32 = pThis->svga.uHeight;
634 }
635 else
636 {
637#ifndef IN_RING3
638 rc = VINF_IOM_R3_IOPORT_READ;
639#else
640 *pu32 = pThis->pDrv->cy;
641#endif
642 }
643 break;
644 }
645
646 case SVGA_REG_MAX_WIDTH:
647 *pu32 = pThis->svga.u32MaxWidth;
648 break;
649
650 case SVGA_REG_MAX_HEIGHT:
651 *pu32 = pThis->svga.u32MaxHeight;
652 break;
653
654 case SVGA_REG_DEPTH:
655 /* This returns the color depth of the current mode. */
656 switch (pThis->svga.uBpp)
657 {
658 case 15:
659 case 16:
660 case 24:
661 *pu32 = pThis->svga.uBpp;
662 break;
663
664 default:
665 case 32:
666 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
667 break;
668 }
669 break;
670
671 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
672 if ( pThis->svga.fEnabled
673 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
674 {
675 *pu32 = pThis->svga.uBpp;
676 }
677 else
678 {
679#ifndef IN_RING3
680 rc = VINF_IOM_R3_IOPORT_READ;
681#else
682 *pu32 = pThis->pDrv->cBits;
683#endif
684 }
685 break;
686
687 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
688 if ( pThis->svga.fEnabled
689 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
690 {
691 *pu32 = (pThis->svga.uBpp + 7) & ~7;
692 }
693 else
694 {
695#ifndef IN_RING3
696 rc = VINF_IOM_R3_IOPORT_READ;
697#else
698 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
699#endif
700 }
701 break;
702
703 case SVGA_REG_PSEUDOCOLOR:
704 *pu32 = 0;
705 break;
706
707 case SVGA_REG_RED_MASK:
708 case SVGA_REG_GREEN_MASK:
709 case SVGA_REG_BLUE_MASK:
710 {
711 uint32_t uBpp;
712
713 if ( pThis->svga.fEnabled
714 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
715 {
716 uBpp = pThis->svga.uBpp;
717 }
718 else
719 {
720#ifndef IN_RING3
721 rc = VINF_IOM_R3_IOPORT_READ;
722 break;
723#else
724 uBpp = pThis->pDrv->cBits;
725#endif
726 }
727 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
728 switch (uBpp)
729 {
730 case 8:
731 u32RedMask = 0x07;
732 u32GreenMask = 0x38;
733 u32BlueMask = 0xc0;
734 break;
735
736 case 15:
737 u32RedMask = 0x0000001f;
738 u32GreenMask = 0x000003e0;
739 u32BlueMask = 0x00007c00;
740 break;
741
742 case 16:
743 u32RedMask = 0x0000001f;
744 u32GreenMask = 0x000007e0;
745 u32BlueMask = 0x0000f800;
746 break;
747
748 case 24:
749 case 32:
750 default:
751 u32RedMask = 0x00ff0000;
752 u32GreenMask = 0x0000ff00;
753 u32BlueMask = 0x000000ff;
754 break;
755 }
756 switch (pThis->svga.u32IndexReg)
757 {
758 case SVGA_REG_RED_MASK:
759 *pu32 = u32RedMask;
760 break;
761
762 case SVGA_REG_GREEN_MASK:
763 *pu32 = u32GreenMask;
764 break;
765
766 case SVGA_REG_BLUE_MASK:
767 *pu32 = u32BlueMask;
768 break;
769 }
770 break;
771 }
772
773 case SVGA_REG_BYTES_PER_LINE:
774 {
775 if ( pThis->svga.fEnabled
776 && pThis->svga.cbScanline)
777 {
778 *pu32 = pThis->svga.cbScanline;
779 }
780 else
781 {
782#ifndef IN_RING3
783 rc = VINF_IOM_R3_IOPORT_READ;
784#else
785 *pu32 = pThis->pDrv->cbScanline;
786#endif
787 }
788 break;
789 }
790
791 case SVGA_REG_VRAM_SIZE: /* VRAM size */
792 *pu32 = pThis->vram_size;
793 break;
794
795 case SVGA_REG_FB_START: /* Frame buffer physical address. */
796 Assert(pThis->GCPhysVRAM <= 0xffffffff);
797 *pu32 = pThis->GCPhysVRAM;
798 break;
799
800 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
801 /* Always zero in our case. */
802 *pu32 = 0;
803 break;
804
805 case SVGA_REG_FB_SIZE: /* Frame buffer size */
806 {
807#ifndef IN_RING3
808 rc = VINF_IOM_R3_IOPORT_READ;
809#else
810 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
811 if ( pThis->svga.fEnabled
812 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
813 {
814 /* Hardware enabled; return real framebuffer size .*/
815 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
816 }
817 else
818 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
819
820 *pu32 = RT_MIN(pThis->vram_size, *pu32);
821 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
822#endif
823 break;
824 }
825
826 case SVGA_REG_CAPABILITIES:
827 *pu32 = pThis->svga.u32RegCaps;
828 break;
829
830 case SVGA_REG_MEM_START: /* FIFO start */
831 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
832 *pu32 = pThis->svga.GCPhysFIFO;
833 break;
834
835 case SVGA_REG_MEM_SIZE: /* FIFO size */
836 *pu32 = pThis->svga.cbFIFO;
837 break;
838
839 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
840 *pu32 = pThis->svga.fConfigured;
841 break;
842
843 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
844 *pu32 = 0;
845 break;
846
847 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
848 if (pThis->svga.fBusy)
849 {
850#ifndef IN_RING3
851 /* Go to ring-3 and halt the CPU. */
852 rc = VINF_IOM_R3_IOPORT_READ;
853 break;
854#else
855# if defined(VMSVGA_USE_EMT_HALT_CODE)
856 /* The guest is basically doing a HLT via the device here, but with
857 a special wake up condition on FIFO completion. */
858 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
859 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
860 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
861 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
862 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
863 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
864 if (pThis->svga.fBusy)
865 rc = VMR3WaitForDeviceReady(pVM, idCpu);
866 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
867 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
868# else
869
870 /* Delay the EMT a bit so the FIFO and others can get some work done.
871 This used to be a crude 50 ms sleep. The current code tries to be
872 more efficient, but the consept is still very crude. */
873 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
874 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
875 RTThreadYield();
876 if (pThis->svga.fBusy)
877 {
878 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
879
880 if (pThis->svga.fBusy && cRefs == 1)
881 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
882 if (pThis->svga.fBusy)
883 {
884 /** @todo If this code is going to stay, we need to call into the halt/wait
885 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
886 * suffer when the guest is polling on a busy FIFO. */
887 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
888 if (cNsMaxWait >= RT_NS_100US)
889 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
890 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
891 RT_MIN(cNsMaxWait, RT_NS_10MS));
892 }
893
894 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
895 }
896 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
897# endif
898 *pu32 = pThis->svga.fBusy != 0;
899#endif
900 }
901 else
902 *pu32 = false;
903 break;
904
905 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
906 *pu32 = pThis->svga.u32GuestId;
907 break;
908
909 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
910 *pu32 = pThis->svga.cScratchRegion;
911 break;
912
913 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
914 *pu32 = SVGA_FIFO_NUM_REGS;
915 break;
916
917 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
918 *pu32 = pThis->svga.u32PitchLock;
919 break;
920
921 case SVGA_REG_IRQMASK: /* Interrupt mask */
922 *pu32 = pThis->svga.u32IrqMask;
923 break;
924
925 /* See "Guest memory regions" below. */
926 case SVGA_REG_GMR_ID:
927 *pu32 = pThis->svga.u32CurrentGMRId;
928 break;
929
930 case SVGA_REG_GMR_DESCRIPTOR:
931 /* Write only */
932 *pu32 = 0;
933 break;
934
935 case SVGA_REG_GMR_MAX_IDS:
936 *pu32 = VMSVGA_MAX_GMR_IDS;
937 break;
938
939 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
940 *pu32 = VMSVGA_MAX_GMR_PAGES;
941 break;
942
943 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
944 *pu32 = pThis->svga.fTraces;
945 break;
946
947 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
948 *pu32 = VMSVGA_MAX_GMR_PAGES;
949 break;
950
951 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
952 *pu32 = VMSVGA_SURFACE_SIZE;
953 break;
954
955 case SVGA_REG_TOP: /* Must be 1 more than the last register */
956 break;
957
958 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
959 break;
960 /* Next 768 (== 256*3) registers exist for colormap */
961
962 /* Mouse cursor support. */
963 case SVGA_REG_CURSOR_ID:
964 case SVGA_REG_CURSOR_X:
965 case SVGA_REG_CURSOR_Y:
966 case SVGA_REG_CURSOR_ON:
967 break;
968
969 /* Legacy multi-monitor support */
970 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
971 *pu32 = 1;
972 break;
973
974 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
975 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
976 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
977 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
978 *pu32 = 0;
979 break;
980
981 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
982 *pu32 = pThis->svga.uWidth;
983 break;
984
985 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
986 *pu32 = pThis->svga.uHeight;
987 break;
988
989 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
990 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
991 break;
992
993 default:
994 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
995 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
996 {
997 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
998 }
999 break;
1000 }
1001 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
1002 return rc;
1003}
1004
1005#ifdef IN_RING3
1006/**
1007 * Apply the current resolution settings to change the video mode.
1008 *
1009 * @returns VBox status code.
1010 * @param pThis VMSVGA State
1011 */
1012int vmsvgaChangeMode(PVGASTATE pThis)
1013{
1014 int rc;
1015
1016 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1017 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1018 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1019 {
1020 /* Mode change in progress; wait for all values to be set. */
1021 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1022 return VINF_SUCCESS;
1023 }
1024
1025 if ( pThis->svga.uWidth == 0
1026 || pThis->svga.uHeight == 0
1027 || pThis->svga.uBpp == 0)
1028 {
1029 /* Invalid mode change - BB does this early in the boot up. */
1030 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1031 return VINF_SUCCESS;
1032 }
1033
1034 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1035 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1036 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1037 && pThis->last_width == (unsigned)pThis->svga.uWidth
1038 && pThis->last_height == (unsigned)pThis->svga.uHeight
1039 )
1040 {
1041 /* Nothing to do. */
1042 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1043 return VINF_SUCCESS;
1044 }
1045
1046 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1047 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1048
1049 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1050 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1051 AssertRC(rc);
1052 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1053
1054 /* last stuff */
1055 pThis->last_bpp = pThis->svga.uBpp;
1056 pThis->last_scr_width = pThis->svga.uWidth;
1057 pThis->last_scr_height = pThis->svga.uHeight;
1058 pThis->last_width = pThis->svga.uWidth;
1059 pThis->last_height = pThis->svga.uHeight;
1060
1061 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1062
1063 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1064 if ( pThis->svga.viewport.cx == 0
1065 && pThis->svga.viewport.cy == 0)
1066 {
1067 pThis->svga.viewport.cx = pThis->svga.uWidth;
1068 pThis->svga.viewport.xRight = pThis->svga.uWidth;
1069 pThis->svga.viewport.cy = pThis->svga.uHeight;
1070 pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1071 pThis->svga.viewport.yLowWC = 0;
1072 }
1073 return VINF_SUCCESS;
1074}
1075#endif /* IN_RING3 */
1076
1077#if defined(IN_RING0) || defined(IN_RING3)
1078/**
1079 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1080 *
1081 * @param pThis The VMSVGA state.
1082 * @param fState The busy state.
1083 */
1084DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1085{
1086 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1087
1088 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1089 {
1090 /* Race / unfortunately scheduling. Highly unlikly. */
1091 uint32_t cLoops = 64;
1092 do
1093 {
1094 ASMNopPause();
1095 fState = (pThis->svga.fBusy != 0);
1096 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1097 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1098 }
1099}
1100#endif
1101
1102/**
1103 * Write port register
1104 *
1105 * @returns VBox status code.
1106 * @param pThis VMSVGA State
1107 * @param u32 Value to write
1108 */
1109PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1110{
1111#ifdef IN_RING3
1112 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1113#endif
1114 int rc = VINF_SUCCESS;
1115
1116 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1117 switch (pThis->svga.u32IndexReg)
1118 {
1119 case SVGA_REG_ID:
1120 if ( u32 == SVGA_ID_0
1121 || u32 == SVGA_ID_1
1122 || u32 == SVGA_ID_2)
1123 pThis->svga.u32SVGAId = u32;
1124 break;
1125
1126 case SVGA_REG_ENABLE:
1127 if ( pThis->svga.fEnabled == u32
1128 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1129 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1130 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1131 && pThis->last_width == (unsigned)pThis->svga.uWidth
1132 && pThis->last_height == (unsigned)pThis->svga.uHeight
1133 )
1134 /* Nothing to do. */
1135 break;
1136
1137#ifdef IN_RING3
1138 if ( u32 == 1
1139 && pThis->svga.fEnabled == false)
1140 {
1141 /* Make a backup copy of the first 32k in order to save font data etc. */
1142 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1143 }
1144
1145 pThis->svga.fEnabled = u32;
1146 if (pThis->svga.fEnabled)
1147 {
1148 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1149 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1150 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1151 {
1152 /* Keep the current mode. */
1153 pThis->svga.uWidth = pThis->pDrv->cx;
1154 pThis->svga.uHeight = pThis->pDrv->cy;
1155 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1156 }
1157
1158 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1159 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1160 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1161 {
1162 rc = vmsvgaChangeMode(pThis);
1163 AssertRCReturn(rc, rc);
1164 }
1165# ifdef LOG_ENABLED
1166 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1167 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1168 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1169# endif
1170
1171 /* Disable or enable dirty page tracking according to the current fTraces value. */
1172 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1173 }
1174 else
1175 {
1176 /* Restore the text mode backup. */
1177 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1178
1179/* pThis->svga.uHeight = -1;
1180 pThis->svga.uWidth = -1;
1181 pThis->svga.uBpp = -1;
1182 pThis->svga.cbScanline = 0; */
1183 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1184
1185 /* Enable dirty page tracking again when going into legacy mode. */
1186 vmsvgaSetTraces(pThis, true);
1187 }
1188#else
1189 rc = VINF_IOM_R3_IOPORT_WRITE;
1190#endif
1191 break;
1192
1193 case SVGA_REG_WIDTH:
1194 if (pThis->svga.uWidth != u32)
1195 {
1196 if (pThis->svga.fEnabled)
1197 {
1198#ifdef IN_RING3
1199 pThis->svga.uWidth = u32;
1200 rc = vmsvgaChangeMode(pThis);
1201 AssertRCReturn(rc, rc);
1202#else
1203 rc = VINF_IOM_R3_IOPORT_WRITE;
1204#endif
1205 }
1206 else
1207 pThis->svga.uWidth = u32;
1208 }
1209 /* else: nop */
1210 break;
1211
1212 case SVGA_REG_HEIGHT:
1213 if (pThis->svga.uHeight != u32)
1214 {
1215 if (pThis->svga.fEnabled)
1216 {
1217#ifdef IN_RING3
1218 pThis->svga.uHeight = u32;
1219 rc = vmsvgaChangeMode(pThis);
1220 AssertRCReturn(rc, rc);
1221#else
1222 rc = VINF_IOM_R3_IOPORT_WRITE;
1223#endif
1224 }
1225 else
1226 pThis->svga.uHeight = u32;
1227 }
1228 /* else: nop */
1229 break;
1230
1231 case SVGA_REG_DEPTH:
1232 /** @todo read-only?? */
1233 break;
1234
1235 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1236 if (pThis->svga.uBpp != u32)
1237 {
1238 if (pThis->svga.fEnabled)
1239 {
1240#ifdef IN_RING3
1241 pThis->svga.uBpp = u32;
1242 rc = vmsvgaChangeMode(pThis);
1243 AssertRCReturn(rc, rc);
1244#else
1245 rc = VINF_IOM_R3_IOPORT_WRITE;
1246#endif
1247 }
1248 else
1249 pThis->svga.uBpp = u32;
1250 }
1251 /* else: nop */
1252 break;
1253
1254 case SVGA_REG_PSEUDOCOLOR:
1255 break;
1256
1257 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1258#ifdef IN_RING3
1259 pThis->svga.fConfigured = u32;
1260 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1261 if (!pThis->svga.fConfigured)
1262 {
1263 pThis->svga.fTraces = true;
1264 }
1265 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1266#else
1267 rc = VINF_IOM_R3_IOPORT_WRITE;
1268#endif
1269 break;
1270
1271 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1272 if ( pThis->svga.fEnabled
1273 && pThis->svga.fConfigured)
1274 {
1275#if defined(IN_RING3) || defined(IN_RING0)
1276 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1277 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1278 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1279 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1280
1281 /* Kick the FIFO thread to start processing commands again. */
1282 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1283#else
1284 rc = VINF_IOM_R3_IOPORT_WRITE;
1285#endif
1286 }
1287 /* else nothing to do. */
1288 else
1289 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1290
1291 break;
1292
1293 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1294 break;
1295
1296 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1297 pThis->svga.u32GuestId = u32;
1298 break;
1299
1300 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1301 pThis->svga.u32PitchLock = u32;
1302 break;
1303
1304 case SVGA_REG_IRQMASK: /* Interrupt mask */
1305 pThis->svga.u32IrqMask = u32;
1306
1307 /* Irq pending after the above change? */
1308 if (pThis->svga.u32IrqStatus & u32)
1309 {
1310 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1311 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1312 }
1313 else
1314 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1315 break;
1316
1317 /* Mouse cursor support */
1318 case SVGA_REG_CURSOR_ID:
1319 case SVGA_REG_CURSOR_X:
1320 case SVGA_REG_CURSOR_Y:
1321 case SVGA_REG_CURSOR_ON:
1322 break;
1323
1324 /* Legacy multi-monitor support */
1325 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1326 break;
1327 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1328 break;
1329 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1330 break;
1331 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1332 break;
1333 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1334 break;
1335 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1336 break;
1337 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1338 break;
1339#ifdef VBOX_WITH_VMSVGA3D
1340 /* See "Guest memory regions" below. */
1341 case SVGA_REG_GMR_ID:
1342 pThis->svga.u32CurrentGMRId = u32;
1343 break;
1344
1345 case SVGA_REG_GMR_DESCRIPTOR:
1346# ifndef IN_RING3
1347 rc = VINF_IOM_R3_IOPORT_WRITE;
1348 break;
1349# else /* IN_RING3 */
1350 {
1351 SVGAGuestMemDescriptor desc;
1352 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1353 RTGCPHYS GCPhysBase = GCPhys;
1354 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1355 uint32_t cDescriptorsAllocated = 16;
1356 uint32_t iDescriptor = 0;
1357
1358 /* Validate current GMR id. */
1359 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1360
1361 /* Free the old GMR if present. */
1362 vmsvgaGMRFree(pThis, idGMR);
1363
1364 /* Just undefine the GMR? */
1365 if (GCPhys == 0)
1366 break;
1367
1368 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1369 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1370
1371 /* Never cross a page boundary automatically. */
1372 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1373 {
1374 /* Read descriptor. */
1375 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1376 AssertRCBreak(rc);
1377
1378 if ( desc.ppn == 0
1379 && desc.numPages == 0)
1380 break; /* terminator */
1381
1382 if ( desc.ppn != 0
1383 && desc.numPages == 0)
1384 {
1385 /* Pointer to the next physical page of descriptors. */
1386 GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1387 }
1388 else
1389 {
1390 if (iDescriptor == cDescriptorsAllocated)
1391 {
1392 cDescriptorsAllocated += 16;
1393 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1394 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1395 }
1396
1397 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1398 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1399 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1400
1401 /* Continue with the next descriptor. */
1402 GCPhys += sizeof(desc);
1403 }
1404 }
1405 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1406 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1407
1408 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1409 {
1410 AssertFailed();
1411 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1412 pSVGAState->aGMR[idGMR].paDesc = NULL;
1413 }
1414 AssertRC(rc);
1415 break;
1416 }
1417# endif /* IN_RING3 */
1418#endif // VBOX_WITH_VMSVGA3D
1419
1420 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1421 if (pThis->svga.fTraces == u32)
1422 break; /* nothing to do */
1423
1424#ifdef IN_RING3
1425 vmsvgaSetTraces(pThis, !!u32);
1426#else
1427 rc = VINF_IOM_R3_IOPORT_WRITE;
1428#endif
1429 break;
1430
1431 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1432 break;
1433
1434 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1435 break;
1436 /* Next 768 (== 256*3) registers exist for colormap */
1437
1438 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1439 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1440 break;
1441
1442 case SVGA_REG_FB_START:
1443 case SVGA_REG_MEM_START:
1444 case SVGA_REG_HOST_BITS_PER_PIXEL:
1445 case SVGA_REG_MAX_WIDTH:
1446 case SVGA_REG_MAX_HEIGHT:
1447 case SVGA_REG_VRAM_SIZE:
1448 case SVGA_REG_FB_SIZE:
1449 case SVGA_REG_CAPABILITIES:
1450 case SVGA_REG_MEM_SIZE:
1451 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1452 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1453 case SVGA_REG_BYTES_PER_LINE:
1454 case SVGA_REG_FB_OFFSET:
1455 case SVGA_REG_RED_MASK:
1456 case SVGA_REG_GREEN_MASK:
1457 case SVGA_REG_BLUE_MASK:
1458 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1459 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1460 case SVGA_REG_GMR_MAX_IDS:
1461 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1462 /* Read only - ignore. */
1463 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1464 break;
1465
1466 default:
1467 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1468 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1469 {
1470 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1471 }
1472 break;
1473 }
1474 return rc;
1475}
1476
1477/**
1478 * Port I/O Handler for IN operations.
1479 *
1480 * @returns VINF_SUCCESS or VINF_EM_*.
1481 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1482 *
1483 * @param pDevIns The device instance.
1484 * @param pvUser User argument.
1485 * @param uPort Port number used for the IN operation.
1486 * @param pu32 Where to store the result. This is always a 32-bit
1487 * variable regardless of what @a cb might say.
1488 * @param cb Number of bytes read.
1489 */
1490PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1491{
1492 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1493 RT_NOREF_PV(pvUser);
1494
1495 /* Ignore non-dword accesses. */
1496 if (cb != 4)
1497 {
1498 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1499 *pu32 = UINT32_MAX;
1500 return VINF_SUCCESS;
1501 }
1502
1503 switch (Port - pThis->svga.BasePort)
1504 {
1505 case SVGA_INDEX_PORT:
1506 *pu32 = pThis->svga.u32IndexReg;
1507 break;
1508
1509 case SVGA_VALUE_PORT:
1510 return vmsvgaReadPort(pThis, pu32);
1511
1512 case SVGA_BIOS_PORT:
1513 Log(("Ignoring BIOS port read\n"));
1514 *pu32 = 0;
1515 break;
1516
1517 case SVGA_IRQSTATUS_PORT:
1518 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1519 *pu32 = pThis->svga.u32IrqStatus;
1520 break;
1521 }
1522
1523 return VINF_SUCCESS;
1524}
1525
1526/**
1527 * Port I/O Handler for OUT operations.
1528 *
1529 * @returns VINF_SUCCESS or VINF_EM_*.
1530 *
1531 * @param pDevIns The device instance.
1532 * @param pvUser User argument.
1533 * @param uPort Port number used for the OUT operation.
1534 * @param u32 The value to output.
1535 * @param cb The value size in bytes.
1536 */
1537PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1538{
1539 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1540 RT_NOREF_PV(pvUser);
1541
1542 /* Ignore non-dword accesses. */
1543 if (cb != 4)
1544 {
1545 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1546 return VINF_SUCCESS;
1547 }
1548
1549 switch (Port - pThis->svga.BasePort)
1550 {
1551 case SVGA_INDEX_PORT:
1552 pThis->svga.u32IndexReg = u32;
1553 break;
1554
1555 case SVGA_VALUE_PORT:
1556 return vmsvgaWritePort(pThis, u32);
1557
1558 case SVGA_BIOS_PORT:
1559 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1560 break;
1561
1562 case SVGA_IRQSTATUS_PORT:
1563 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1564 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1565 /* Clear the irq in case all events have been cleared. */
1566 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1567 {
1568 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1569 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1570 }
1571 break;
1572 }
1573 return VINF_SUCCESS;
1574}
1575
1576#ifdef DEBUG_FIFO_ACCESS
1577
1578# ifdef IN_RING3
1579/**
1580 * Handle LFB access.
1581 * @returns VBox status code.
1582 * @param pVM VM handle.
1583 * @param pThis VGA device instance data.
1584 * @param GCPhys The access physical address.
1585 * @param fWriteAccess Read or write access
1586 */
1587static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1588{
1589 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1590 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1591
1592 switch (GCPhysOffset >> 2)
1593 {
1594 case SVGA_FIFO_MIN:
1595 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1596 break;
1597 case SVGA_FIFO_MAX:
1598 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1599 break;
1600 case SVGA_FIFO_NEXT_CMD:
1601 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1602 break;
1603 case SVGA_FIFO_STOP:
1604 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1605 break;
1606 case SVGA_FIFO_CAPABILITIES:
1607 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1608 break;
1609 case SVGA_FIFO_FLAGS:
1610 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1611 break;
1612 case SVGA_FIFO_FENCE:
1613 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1614 break;
1615 case SVGA_FIFO_3D_HWVERSION:
1616 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1617 break;
1618 case SVGA_FIFO_PITCHLOCK:
1619 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1620 break;
1621 case SVGA_FIFO_CURSOR_ON:
1622 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1623 break;
1624 case SVGA_FIFO_CURSOR_X:
1625 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1626 break;
1627 case SVGA_FIFO_CURSOR_Y:
1628 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1629 break;
1630 case SVGA_FIFO_CURSOR_COUNT:
1631 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1632 break;
1633 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1634 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1635 break;
1636 case SVGA_FIFO_RESERVED:
1637 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1638 break;
1639 case SVGA_FIFO_CURSOR_SCREEN_ID:
1640 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1641 break;
1642 case SVGA_FIFO_DEAD:
1643 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1644 break;
1645 case SVGA_FIFO_3D_HWVERSION_REVISED:
1646 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1647 break;
1648 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1649 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1650 break;
1651 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1652 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1653 break;
1654 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1655 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1656 break;
1657 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1658 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1659 break;
1660 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1661 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1662 break;
1663 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1664 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1665 break;
1666 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1667 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1668 break;
1669 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1670 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1671 break;
1672 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1673 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1674 break;
1675 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1676 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1677 break;
1678 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1679 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1680 break;
1681 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1682 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1683 break;
1684 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1685 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1686 break;
1687 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1688 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1689 break;
1690 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1691 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1692 break;
1693 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1694 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1695 break;
1696 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1697 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1698 break;
1699 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1700 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1701 break;
1702 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1703 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1704 break;
1705 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1706 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1707 break;
1708 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1709 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1710 break;
1711 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1712 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1713 break;
1714 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1715 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1716 break;
1717 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1718 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1719 break;
1720 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1721 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1722 break;
1723 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1724 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1725 break;
1726 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1727 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1728 break;
1729 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1730 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1731 break;
1732 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1733 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1734 break;
1735 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1736 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1737 break;
1738 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1739 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1740 break;
1741 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1742 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1743 break;
1744 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1745 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1746 break;
1747 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1748 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1749 break;
1750 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1751 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1752 break;
1753 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1754 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1755 break;
1756 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1757 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1758 break;
1759 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1760 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1761 break;
1762 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1763 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1764 break;
1765 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1766 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1767 break;
1768 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1769 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1770 break;
1771 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1772 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1773 break;
1774 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1775 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1776 break;
1777 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1778 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1779 break;
1780 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1781 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1782 break;
1783 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1784 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1785 break;
1786 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1787 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1788 break;
1789 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1790 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1791 break;
1792 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1793 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1794 break;
1795 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1796 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1797 break;
1798 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1799 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1800 break;
1801 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1802 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1803 break;
1804 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1805 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1806 break;
1807 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1808 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1809 break;
1810 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1811 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1812 break;
1813 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1814 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1815 break;
1816 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1817 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1818 break;
1819 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1820 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1821 break;
1822 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1823 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1824 break;
1825 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1826 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1827 break;
1828 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1829 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1830 break;
1831 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1832 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1833 break;
1834 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1835 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1836 break;
1837 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1838 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1839 break;
1840 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1841 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1842 break;
1843 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1844 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1845 break;
1846 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1847 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1848 break;
1849 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1850 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1851 break;
1852 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1853 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1854 break;
1855 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1856 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1857 break;
1858 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1859 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1860 break;
1861 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1862 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1863 break;
1864 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1865 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1866 break;
1867 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1868 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1869 break;
1870 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1871 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1872 break;
1873 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1874 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1875 break;
1876 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1877 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1878 break;
1879 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1880 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1881 break;
1882 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1883 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1884 break;
1885 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1886 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1887 break;
1888 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1889 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1890 break;
1891 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1892 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1893 break;
1894 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1895 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1896 break;
1897 case SVGA_FIFO_3D_CAPS_LAST:
1898 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1899 break;
1900 case SVGA_FIFO_GUEST_3D_HWVERSION:
1901 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1902 break;
1903 case SVGA_FIFO_FENCE_GOAL:
1904 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1905 break;
1906 case SVGA_FIFO_BUSY:
1907 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1908 break;
1909 default:
1910 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1911 break;
1912 }
1913
1914 return VINF_EM_RAW_EMULATE_INSTR;
1915}
1916
1917/**
1918 * HC access handler for the FIFO.
1919 *
1920 * @returns VINF_SUCCESS if the handler have carried out the operation.
1921 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1922 * @param pVM VM Handle.
1923 * @param pVCpu The cross context CPU structure for the calling EMT.
1924 * @param GCPhys The physical address the guest is writing to.
1925 * @param pvPhys The HC mapping of that address.
1926 * @param pvBuf What the guest is reading/writing.
1927 * @param cbBuf How much it's reading/writing.
1928 * @param enmAccessType The access type.
1929 * @param enmOrigin Who is making the access.
1930 * @param pvUser User argument.
1931 */
1932static DECLCALLBACK(VBOXSTRICTRC)
1933vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1934 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1935{
1936 PVGASTATE pThis = (PVGASTATE)pvUser;
1937 int rc;
1938 Assert(pThis);
1939 Assert(GCPhys >= pThis->GCPhysVRAM);
1940 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1941
1942 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1943 if (RT_SUCCESS(rc))
1944 return VINF_PGM_HANDLER_DO_DEFAULT;
1945 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1946 return rc;
1947}
1948
1949# endif /* IN_RING3 */
1950#endif /* DEBUG_FIFO_ACCESS */
1951
1952#ifdef DEBUG_GMR_ACCESS
1953/**
1954 * HC access handler for the FIFO.
1955 *
1956 * @returns VINF_SUCCESS if the handler have carried out the operation.
1957 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1958 * @param pVM VM Handle.
1959 * @param pVCpu The cross context CPU structure for the calling EMT.
1960 * @param GCPhys The physical address the guest is writing to.
1961 * @param pvPhys The HC mapping of that address.
1962 * @param pvBuf What the guest is reading/writing.
1963 * @param cbBuf How much it's reading/writing.
1964 * @param enmAccessType The access type.
1965 * @param enmOrigin Who is making the access.
1966 * @param pvUser User argument.
1967 */
1968static DECLCALLBACK(VBOXSTRICTRC)
1969vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1970 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1971{
1972 PVGASTATE pThis = (PVGASTATE)pvUser;
1973 Assert(pThis);
1974 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1975 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1976
1977 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1978
1979 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1980 {
1981 PGMR pGMR = &pSVGAState->aGMR[i];
1982
1983 if (pGMR->numDescriptors)
1984 {
1985 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1986 {
1987 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1988 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1989 {
1990 /*
1991 * Turn off the write handler for this particular page and make it R/W.
1992 * Then return telling the caller to restart the guest instruction.
1993 */
1994 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1995 goto end;
1996 }
1997 }
1998 }
1999 }
2000end:
2001 return VINF_PGM_HANDLER_DO_DEFAULT;
2002}
2003
2004# ifdef IN_RING3
2005
2006/* Callback handler for VMR3ReqCallWait */
2007static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2008{
2009 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2010 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2011 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2012 int rc;
2013
2014 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2015 {
2016 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2017 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2018 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2019 AssertRC(rc);
2020 }
2021 return VINF_SUCCESS;
2022}
2023
2024/* Callback handler for VMR3ReqCallWait */
2025static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2026{
2027 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2028 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2029 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2030
2031 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2032 {
2033 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2034 AssertRC(rc);
2035 }
2036 return VINF_SUCCESS;
2037}
2038
2039/* Callback handler for VMR3ReqCallWait */
2040static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2041{
2042 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2043
2044 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2045 {
2046 PGMR pGMR = &pSVGAState->aGMR[i];
2047
2048 if (pGMR->numDescriptors)
2049 {
2050 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2051 {
2052 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2053 AssertRC(rc);
2054 }
2055 }
2056 }
2057 return VINF_SUCCESS;
2058}
2059
2060# endif /* IN_RING3 */
2061#endif /* DEBUG_GMR_ACCESS */
2062
2063/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2064
2065#ifdef IN_RING3
2066
2067/**
2068 * Worker for vmsvgaR3FifoThread that handles an external command.
2069 *
2070 * @param pThis VGA device instance data.
2071 */
2072static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2073{
2074 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2075 switch (pThis->svga.u8FIFOExtCommand)
2076 {
2077 case VMSVGA_FIFO_EXTCMD_RESET:
2078 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2079 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2080# ifdef VBOX_WITH_VMSVGA3D
2081 if (pThis->svga.f3DEnabled)
2082 {
2083 /* The 3d subsystem must be reset from the fifo thread. */
2084 vmsvga3dReset(pThis);
2085 }
2086# endif
2087 break;
2088
2089 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2090 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2091 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2092# ifdef VBOX_WITH_VMSVGA3D
2093 if (pThis->svga.f3DEnabled)
2094 {
2095 /* The 3d subsystem must be shut down from the fifo thread. */
2096 vmsvga3dTerminate(pThis);
2097 }
2098# endif
2099 break;
2100
2101 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2102 {
2103 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2104# ifdef VBOX_WITH_VMSVGA3D
2105 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2106 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2107 vmsvga3dSaveExec(pThis, pSSM);
2108# endif
2109 break;
2110 }
2111
2112 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2113 {
2114 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2115# ifdef VBOX_WITH_VMSVGA3D
2116 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2117 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2118 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2119# endif
2120 break;
2121 }
2122
2123 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2124 {
2125# ifdef VBOX_WITH_VMSVGA3D
2126 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2127 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2128 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2129# endif
2130 break;
2131 }
2132
2133
2134 default:
2135 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2136 break;
2137 }
2138
2139 /*
2140 * Signal the end of the external command.
2141 */
2142 pThis->svga.pvFIFOExtCmdParam = NULL;
2143 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2144 ASMMemoryFence(); /* paranoia^2 */
2145 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2146 AssertLogRelRC(rc);
2147}
2148
2149/**
2150 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2151 * doing a job on the FIFO thread (even when it's officially suspended).
2152 *
2153 * @returns VBox status code (fully asserted).
2154 * @param pThis VGA device instance data.
2155 * @param uExtCmd The command to execute on the FIFO thread.
2156 * @param pvParam Pointer to command parameters.
2157 * @param cMsWait The time to wait for the command, given in
2158 * milliseconds.
2159 */
2160static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2161{
2162 Assert(cMsWait >= RT_MS_1SEC * 5);
2163 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2164 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2165
2166 int rc;
2167 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2168 PDMTHREADSTATE enmState = pThread->enmState;
2169 if (enmState == PDMTHREADSTATE_SUSPENDED)
2170 {
2171 /*
2172 * The thread is suspended, we have to temporarily wake it up so it can
2173 * perform the task.
2174 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2175 */
2176 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2177 /* Post the request. */
2178 pThis->svga.fFifoExtCommandWakeup = true;
2179 pThis->svga.pvFIFOExtCmdParam = pvParam;
2180 pThis->svga.u8FIFOExtCommand = uExtCmd;
2181 ASMMemoryFence(); /* paranoia^3 */
2182
2183 /* Resume the thread. */
2184 rc = PDMR3ThreadResume(pThread);
2185 AssertLogRelRC(rc);
2186 if (RT_SUCCESS(rc))
2187 {
2188 /* Wait. Take care in case the semaphore was already posted (same as below). */
2189 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2190 if ( rc == VINF_SUCCESS
2191 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2192 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2193 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2194 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2195
2196 /* suspend the thread */
2197 pThis->svga.fFifoExtCommandWakeup = false;
2198 int rc2 = PDMR3ThreadSuspend(pThread);
2199 AssertLogRelRC(rc2);
2200 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2201 rc = rc2;
2202 }
2203 pThis->svga.fFifoExtCommandWakeup = false;
2204 pThis->svga.pvFIFOExtCmdParam = NULL;
2205 }
2206 else if (enmState == PDMTHREADSTATE_RUNNING)
2207 {
2208 /*
2209 * The thread is running, should only happen during reset and vmsvga3dsfc.
2210 * We ASSUME not racing code here, both wrt thread state and ext commands.
2211 */
2212 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2213 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2214
2215 /* Post the request. */
2216 pThis->svga.pvFIFOExtCmdParam = pvParam;
2217 pThis->svga.u8FIFOExtCommand = uExtCmd;
2218 ASMMemoryFence(); /* paranoia^2 */
2219 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2220 AssertLogRelRC(rc);
2221
2222 /* Wait. Take care in case the semaphore was already posted (same as above). */
2223 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2224 if ( rc == VINF_SUCCESS
2225 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2226 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2227 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2228 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2229
2230 pThis->svga.pvFIFOExtCmdParam = NULL;
2231 }
2232 else
2233 {
2234 /*
2235 * Something is wrong with the thread!
2236 */
2237 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2238 rc = VERR_INVALID_STATE;
2239 }
2240 return rc;
2241}
2242
2243
2244/**
2245 * Marks the FIFO non-busy, notifying any waiting EMTs.
2246 *
2247 * @param pThis The VGA state.
2248 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2249 * @param offFifoMin The start byte offset of the command FIFO.
2250 */
2251static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2252{
2253 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2254 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2255 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2256
2257 /* Wake up any waiting EMTs. */
2258 if (pSVGAState->cBusyDelayedEmts > 0)
2259 {
2260#ifdef VMSVGA_USE_EMT_HALT_CODE
2261 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2262 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2263 if (idCpu != NIL_VMCPUID)
2264 {
2265 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2266 while (idCpu-- > 0)
2267 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2268 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2269 }
2270#else
2271 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2272 AssertRC(rc2);
2273#endif
2274 }
2275}
2276
2277/**
2278 * Reads (more) payload into the command buffer.
2279 *
2280 * @returns pbBounceBuf on success
2281 * @retval (void *)1 if the thread was requested to stop.
2282 * @retval NULL on FIFO error.
2283 *
2284 * @param cbPayloadReq The number of bytes of payload requested.
2285 * @param pFIFO The FIFO.
2286 * @param offCurrentCmd The FIFO byte offset of the current command.
2287 * @param offFifoMin The start byte offset of the command FIFO.
2288 * @param offFifoMax The end byte offset of the command FIFO.
2289 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2290 * always sufficient size.
2291 * @param pcbAlreadyRead How much payload we've already read into the bounce
2292 * buffer. (We will NEVER re-read anything.)
2293 * @param pThread The calling PDM thread handle.
2294 * @param pThis The VGA state.
2295 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2296 * statistics collection.
2297 */
2298static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2299 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2300 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2301 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2302{
2303 Assert(pbBounceBuf);
2304 Assert(pcbAlreadyRead);
2305 Assert(offFifoMin < offFifoMax);
2306 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2307 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2308
2309 /*
2310 * Check if the requested payload size has already been satisfied .
2311 * .
2312 * When called to read more, the caller is responsible for making sure the .
2313 * new command size (cbRequsted) never is smaller than what has already .
2314 * been read.
2315 */
2316 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2317 if (cbPayloadReq <= cbAlreadyRead)
2318 {
2319 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2320 return pbBounceBuf;
2321 }
2322
2323 /*
2324 * Commands bigger than the fifo buffer are invalid.
2325 */
2326 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2327 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2328 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2329 NULL);
2330
2331 /*
2332 * Move offCurrentCmd past the command dword.
2333 */
2334 offCurrentCmd += sizeof(uint32_t);
2335 if (offCurrentCmd >= offFifoMax)
2336 offCurrentCmd = offFifoMin;
2337
2338 /*
2339 * Do we have sufficient payload data available already?
2340 */
2341 uint32_t cbAfter, cbBefore;
2342 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2343 if (offNextCmd > offCurrentCmd)
2344 {
2345 if (RT_LIKELY(offNextCmd < offFifoMax))
2346 cbAfter = offNextCmd - offCurrentCmd;
2347 else
2348 {
2349 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2350 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2351 offNextCmd, offFifoMin, offFifoMax));
2352 cbAfter = offFifoMax - offCurrentCmd;
2353 }
2354 cbBefore = 0;
2355 }
2356 else
2357 {
2358 cbAfter = offFifoMax - offCurrentCmd;
2359 if (offNextCmd >= offFifoMin)
2360 cbBefore = offNextCmd - offFifoMin;
2361 else
2362 {
2363 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2364 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2365 offNextCmd, offFifoMin, offFifoMax));
2366 cbBefore = 0;
2367 }
2368 }
2369 if (cbAfter + cbBefore < cbPayloadReq)
2370 {
2371 /*
2372 * Insufficient, must wait for it to arrive.
2373 */
2374/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2375 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2376 for (uint32_t i = 0;; i++)
2377 {
2378 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2379 {
2380 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2381 return (void *)(uintptr_t)1;
2382 }
2383 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2384 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2385
2386 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2387
2388 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2389 if (offNextCmd > offCurrentCmd)
2390 {
2391 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2392 cbBefore = 0;
2393 }
2394 else
2395 {
2396 cbAfter = offFifoMax - offCurrentCmd;
2397 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2398 }
2399
2400 if (cbAfter + cbBefore >= cbPayloadReq)
2401 break;
2402 }
2403 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2404 }
2405
2406 /*
2407 * Copy out the memory and update what pcbAlreadyRead points to.
2408 */
2409 if (cbAfter >= cbPayloadReq)
2410 memcpy(pbBounceBuf + cbAlreadyRead,
2411 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2412 cbPayloadReq - cbAlreadyRead);
2413 else
2414 {
2415 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2416 if (cbAlreadyRead < cbAfter)
2417 {
2418 memcpy(pbBounceBuf + cbAlreadyRead,
2419 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2420 cbAfter - cbAlreadyRead);
2421 cbAlreadyRead = cbAfter;
2422 }
2423 memcpy(pbBounceBuf + cbAlreadyRead,
2424 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2425 cbPayloadReq - cbAlreadyRead);
2426 }
2427 *pcbAlreadyRead = cbPayloadReq;
2428 return pbBounceBuf;
2429}
2430
2431/* The async FIFO handling thread. */
2432static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2433{
2434 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2435 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2436 int rc;
2437
2438 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2439 return VINF_SUCCESS;
2440
2441 /*
2442 * Special mode where we only execute an external command and the go back
2443 * to being suspended. Currently, all ext cmds ends up here, with the reset
2444 * one also being eligble for runtime execution further down as well.
2445 */
2446 if (pThis->svga.fFifoExtCommandWakeup)
2447 {
2448 vmsvgaR3FifoHandleExtCmd(pThis);
2449 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2450 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2451 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2452 else
2453 vmsvgaR3FifoHandleExtCmd(pThis);
2454 return VINF_SUCCESS;
2455 }
2456
2457
2458 /*
2459 * Signal the semaphore to make sure we don't wait for 250ms after a
2460 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2461 */
2462 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2463
2464 /*
2465 * Allocate a bounce buffer for command we get from the FIFO.
2466 * (All code must return via the end of the function to free this buffer.)
2467 */
2468 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2469 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2470
2471 /*
2472 * Polling/sleep interval config.
2473 *
2474 * We wait for an a short interval if the guest has recently given us work
2475 * to do, but the interval increases the longer we're kept idle. With the
2476 * current parameters we'll be at a 64ms poll interval after 1 idle second,
2477 * at 90ms after 2 seconds, and reach the max 250ms interval after about
2478 * 16 seconds.
2479 */
2480 RTMSINTERVAL const cMsMinSleep = 16;
2481 RTMSINTERVAL const cMsIncSleep = 2;
2482 RTMSINTERVAL const cMsMaxSleep = 250;
2483 RTMSINTERVAL cMsSleep = cMsMaxSleep;
2484
2485 /*
2486 * The FIFO loop.
2487 */
2488 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2489 bool fBadOrDisabledFifo = false;
2490 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2491 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2492 {
2493# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2494 /*
2495 * Should service the run loop every so often.
2496 */
2497 if (pThis->svga.f3DEnabled)
2498 vmsvga3dCocoaServiceRunLoop();
2499# endif
2500
2501 /*
2502 * Unless there's already work pending, go to sleep for a short while.
2503 * (See polling/sleep interval config above.)
2504 */
2505 if ( fBadOrDisabledFifo
2506 || pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2507 {
2508 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
2509 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2510 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2511 {
2512 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2513 break;
2514 }
2515 }
2516 else
2517 rc = VINF_SUCCESS;
2518 fBadOrDisabledFifo = false;
2519 if (rc == VERR_TIMEOUT)
2520 {
2521 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2522 {
2523 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
2524 continue;
2525 }
2526 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2527
2528 Log(("vmsvgaFIFOLoop: timeout\n"));
2529 }
2530 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2531 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2532 cMsSleep = cMsMinSleep;
2533
2534 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2535 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2536 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2537
2538 /*
2539 * Handle external commands (currently only reset).
2540 */
2541 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2542 {
2543 vmsvgaR3FifoHandleExtCmd(pThis);
2544 continue;
2545 }
2546
2547 /*
2548 * The device must be enabled and configured.
2549 */
2550 if ( !pThis->svga.fEnabled
2551 || !pThis->svga.fConfigured)
2552 {
2553 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2554 fBadOrDisabledFifo = true;
2555 continue;
2556 }
2557
2558 /*
2559 * Get and check the min/max values. We ASSUME that they will remain
2560 * unchanged while we process requests. A further ASSUMPTION is that
2561 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2562 * we don't read it back while in the loop.
2563 */
2564 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2565 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2566 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2567 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2568 || offFifoMax <= offFifoMin
2569 || offFifoMax > VMSVGA_FIFO_SIZE
2570 || (offFifoMax & 3) != 0
2571 || (offFifoMin & 3) != 0
2572 || offCurrentCmd < offFifoMin
2573 || offCurrentCmd > offFifoMax))
2574 {
2575 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2576 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2577 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2578 fBadOrDisabledFifo = true;
2579 continue;
2580 }
2581 if (RT_UNLIKELY(offCurrentCmd & 3))
2582 {
2583 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2584 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2585 offCurrentCmd = ~UINT32_C(3);
2586 }
2587
2588/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
2589 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2590 *
2591 * Will break out of the switch on failure.
2592 * Will restart and quit the loop if the thread was requested to stop.
2593 *
2594 * @param a_PtrVar Request variable pointer.
2595 * @param a_Type Request typedef (not pointer) for casting.
2596 * @param a_cbPayloadReq How much payload to fetch.
2597 * @remarks Accesses a bunch of variables in the current scope!
2598 */
2599# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2600 if (1) { \
2601 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2602 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2603 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2604 } else do {} while (0)
2605/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
2606 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2607 * buffer after figuring out the actual command size.
2608 *
2609 * Will break out of the switch on failure.
2610 *
2611 * @param a_PtrVar Request variable pointer.
2612 * @param a_Type Request typedef (not pointer) for casting.
2613 * @param a_cbPayloadReq How much payload to fetch.
2614 * @remarks Accesses a bunch of variables in the current scope!
2615 */
2616# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2617 if (1) { \
2618 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2619 } else do {} while (0)
2620
2621 /*
2622 * Mark the FIFO as busy.
2623 */
2624 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2625 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2626 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2627
2628 /*
2629 * Execute all queued FIFO commands.
2630 * Quit if pending external command or changes in the thread state.
2631 */
2632 bool fDone = false;
2633 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2634 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2635 {
2636 uint32_t cbPayload = 0;
2637 uint32_t u32IrqStatus = 0;
2638
2639 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2640
2641 /* First check any pending actions. */
2642 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2643# ifdef VBOX_WITH_VMSVGA3D
2644 vmsvga3dChangeMode(pThis);
2645# else
2646 {/*nothing*/}
2647# endif
2648 /* Check for pending external commands (reset). */
2649 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2650 break;
2651
2652 /*
2653 * Process the command.
2654 */
2655 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2656 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2657 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2658 switch (enmCmdId)
2659 {
2660 case SVGA_CMD_INVALID_CMD:
2661 /* Nothing to do. */
2662 break;
2663
2664 case SVGA_CMD_FENCE:
2665 {
2666 SVGAFifoCmdFence *pCmdFence;
2667 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2668 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2669 {
2670 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2671 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2672
2673 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2674 {
2675 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2676 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2677 }
2678 else
2679 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2680 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2681 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2682 {
2683 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2684 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2685 }
2686 }
2687 else
2688 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2689 break;
2690 }
2691 case SVGA_CMD_UPDATE:
2692 case SVGA_CMD_UPDATE_VERBOSE:
2693 {
2694 SVGAFifoCmdUpdate *pUpdate;
2695 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2696 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2697 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2698 break;
2699 }
2700
2701 case SVGA_CMD_DEFINE_CURSOR:
2702 {
2703 /* Followed by bitmap data. */
2704 SVGAFifoCmdDefineCursor *pCursor;
2705 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2706 AssertFailed(); /** @todo implement when necessary. */
2707 break;
2708 }
2709
2710 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2711 {
2712 /* Followed by bitmap data. */
2713 uint32_t cbCursorShape, cbAndMask;
2714 uint8_t *pCursorCopy;
2715 uint32_t cbCmd;
2716
2717 SVGAFifoCmdDefineAlphaCursor *pCursor;
2718 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2719
2720 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2721
2722 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2723 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2724
2725 /* Refetch the bitmap data as well. */
2726 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2727 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2728 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2729
2730 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2731 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2732 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2733 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2734
2735 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2736 AssertBreak(pCursorCopy);
2737
2738 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2739
2740 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2741 memset(pCursorCopy, 0xff, cbAndMask);
2742 /* Colour data */
2743 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2744
2745 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2746 true,
2747 true,
2748 pCursor->hotspotX,
2749 pCursor->hotspotY,
2750 pCursor->width,
2751 pCursor->height,
2752 pCursorCopy);
2753 AssertRC(rc);
2754
2755 if (pSVGAState->Cursor.fActive)
2756 RTMemFree(pSVGAState->Cursor.pData);
2757
2758 pSVGAState->Cursor.fActive = true;
2759 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2760 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2761 pSVGAState->Cursor.width = pCursor->width;
2762 pSVGAState->Cursor.height = pCursor->height;
2763 pSVGAState->Cursor.cbData = cbCursorShape;
2764 pSVGAState->Cursor.pData = pCursorCopy;
2765 break;
2766 }
2767
2768 case SVGA_CMD_ESCAPE:
2769 {
2770 /* Followed by nsize bytes of data. */
2771 SVGAFifoCmdEscape *pEscape;
2772 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2773
2774 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2775 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2776 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2777 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2778
2779 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2780 {
2781 AssertBreak(pEscape->size >= sizeof(uint32_t));
2782 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2783 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2784
2785 switch (cmd)
2786 {
2787 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2788 {
2789 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2790 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2791 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2792
2793 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2794 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2795 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2796
2797 RT_NOREF_PV(pVideoCmd);
2798 break;
2799
2800 }
2801
2802 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2803 {
2804 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2805 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2806 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2807 RT_NOREF_PV(pVideoCmd);
2808 break;
2809 }
2810 }
2811 }
2812 else
2813 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2814
2815 break;
2816 }
2817# ifdef VBOX_WITH_VMSVGA3D
2818 case SVGA_CMD_DEFINE_GMR2:
2819 {
2820 SVGAFifoCmdDefineGMR2 *pCmd;
2821 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2822 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2823
2824 /* Validate current GMR id. */
2825 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2826 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2827
2828 if (!pCmd->numPages)
2829 {
2830 vmsvgaGMRFree(pThis, pCmd->gmrId);
2831 }
2832 else
2833 {
2834 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2835 pGMR->cMaxPages = pCmd->numPages;
2836 }
2837 /* everything done in remap */
2838 break;
2839 }
2840
2841 case SVGA_CMD_REMAP_GMR2:
2842 {
2843 /* Followed by page descriptors or guest ptr. */
2844 SVGAFifoCmdRemapGMR2 *pCmd;
2845 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2846 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2847 uint32_t cbCmd;
2848 uint64_t *paNewPage64 = NULL;
2849
2850 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2851 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2852
2853 /* Calculate the size of what comes after next and fetch it. */
2854 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2855 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2856 cbCmd += sizeof(SVGAGuestPtr);
2857 else
2858 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2859 {
2860 cbCmd += cbPageDesc;
2861 pCmd->numPages = 1;
2862 }
2863 else
2864 {
2865 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2866 cbCmd += cbPageDesc * pCmd->numPages;
2867 }
2868 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2869
2870 /* Validate current GMR id. */
2871 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2872 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2873 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2874 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2875
2876 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2877 if (pGMR->paDesc)
2878 {
2879 uint32_t idxPage = 0;
2880 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2881 AssertBreak(paNewPage64);
2882
2883 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2884 {
2885 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2886 {
2887 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2888 }
2889 }
2890 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2891 }
2892
2893 /* Free the old GMR if present. */
2894 if (pGMR->paDesc)
2895 RTMemFree(pGMR->paDesc);
2896
2897 /* Allocate the maximum amount possible (everything non-continuous) */
2898 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2899 AssertBreak(pGMR->paDesc);
2900
2901 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2902 {
2903 /** @todo */
2904 AssertFailed();
2905 }
2906 else
2907 {
2908 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2909 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2910 uint32_t iDescriptor = 0;
2911 RTGCPHYS GCPhys;
2912 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2913
2914 if (paNewPage64)
2915 {
2916 /* Overwrite the old page array with the new page values. */
2917 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2918 {
2919 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2920 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2921 else
2922 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2923 }
2924 /* Use the updated page array instead of the command data. */
2925 fGCPhys64 = true;
2926 pPage64 = paNewPage64;
2927 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2928 }
2929
2930 if (fGCPhys64)
2931 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2932 else
2933 GCPhys = (RTGCPHYS)pPage32[0] << PAGE_SHIFT;
2934
2935 pGMR->paDesc[0].GCPhys = GCPhys;
2936 pGMR->paDesc[0].numPages = 1;
2937 pGMR->cbTotal = PAGE_SIZE;
2938
2939 for (uint32_t i = 1; i < pCmd->numPages; i++)
2940 {
2941 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2942 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2943 else
2944 GCPhys = (RTGCPHYS)pPage32[i] << PAGE_SHIFT;
2945
2946 /* Continuous physical memory? */
2947 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2948 {
2949 Assert(pGMR->paDesc[iDescriptor].numPages);
2950 pGMR->paDesc[iDescriptor].numPages++;
2951 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2952 }
2953 else
2954 {
2955 iDescriptor++;
2956 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2957 pGMR->paDesc[iDescriptor].numPages = 1;
2958 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2959 }
2960
2961 pGMR->cbTotal += PAGE_SIZE;
2962 }
2963 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2964 pGMR->numDescriptors = iDescriptor + 1;
2965 }
2966
2967 if (paNewPage64)
2968 RTMemFree(paNewPage64);
2969
2970# ifdef DEBUG_GMR_ACCESS
2971 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2972# endif
2973 break;
2974 }
2975# endif // VBOX_WITH_VMSVGA3D
2976 case SVGA_CMD_DEFINE_SCREEN:
2977 {
2978 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2979 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2980 SVGAFifoCmdDefineScreen *pCmd;
2981 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2982 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2983 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2984
2985 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2986 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2987 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2988 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2989 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2990 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2991 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2992 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2993 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2994 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2995 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2996
2997 /** @todo multi monitor support and screen object capabilities. */
2998 pThis->svga.uWidth = pCmd->screen.size.width;
2999 pThis->svga.uHeight = pCmd->screen.size.height;
3000 vmsvgaChangeMode(pThis);
3001 break;
3002 }
3003
3004 case SVGA_CMD_DESTROY_SCREEN:
3005 {
3006 SVGAFifoCmdDestroyScreen *pCmd;
3007 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3008
3009 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3010 break;
3011 }
3012# ifdef VBOX_WITH_VMSVGA3D
3013 case SVGA_CMD_DEFINE_GMRFB:
3014 {
3015 SVGAFifoCmdDefineGMRFB *pCmd;
3016 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3017
3018 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3019 pSVGAState->GMRFB.ptr = pCmd->ptr;
3020 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3021 pSVGAState->GMRFB.format = pCmd->format;
3022 break;
3023 }
3024
3025 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3026 {
3027 uint32_t width, height;
3028 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3029 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3030
3031 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3032
3033 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3034 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3035 AssertBreak(pCmd->destScreenId == 0);
3036
3037 if (pCmd->destRect.left < 0)
3038 pCmd->destRect.left = 0;
3039 if (pCmd->destRect.top < 0)
3040 pCmd->destRect.top = 0;
3041 if (pCmd->destRect.right < 0)
3042 pCmd->destRect.right = 0;
3043 if (pCmd->destRect.bottom < 0)
3044 pCmd->destRect.bottom = 0;
3045
3046 width = pCmd->destRect.right - pCmd->destRect.left;
3047 height = pCmd->destRect.bottom - pCmd->destRect.top;
3048
3049 if ( width == 0
3050 || height == 0)
3051 break; /* Nothing to do. */
3052
3053 /* Clip to screen dimensions. */
3054 if (width > pThis->svga.uWidth)
3055 width = pThis->svga.uWidth;
3056 if (height > pThis->svga.uHeight)
3057 height = pThis->svga.uHeight;
3058
3059 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3060 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3061 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3062
3063 AssertBreak(offsetDest < pThis->vram_size);
3064
3065 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3066 AssertRC(rc);
3067 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3068 break;
3069 }
3070
3071 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3072 {
3073 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3074 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3075
3076 /* Note! This can fetch 3d render results as well!! */
3077 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3078 AssertFailed();
3079 break;
3080 }
3081# endif // VBOX_WITH_VMSVGA3D
3082 case SVGA_CMD_ANNOTATION_FILL:
3083 {
3084 SVGAFifoCmdAnnotationFill *pCmd;
3085 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3086
3087 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3088 pSVGAState->colorAnnotation = pCmd->color;
3089 break;
3090 }
3091
3092 case SVGA_CMD_ANNOTATION_COPY:
3093 {
3094 SVGAFifoCmdAnnotationCopy *pCmd;
3095 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3096
3097 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3098 AssertFailed();
3099 break;
3100 }
3101
3102 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3103
3104 default:
3105# ifdef VBOX_WITH_VMSVGA3D
3106 if ( enmCmdId >= SVGA_3D_CMD_BASE
3107 && enmCmdId < SVGA_3D_CMD_MAX)
3108 {
3109 /* All 3d commands start with a common header, which defines the size of the command. */
3110 SVGA3dCmdHeader *pHdr;
3111 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3112 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3113 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3114 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3115
3116/**
3117 * Check that the 3D command has at least a_cbMin of payload bytes after the
3118 * header. Will break out of the switch if it doesn't.
3119 */
3120# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3121 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3122 switch ((int)enmCmdId)
3123 {
3124 case SVGA_3D_CMD_SURFACE_DEFINE:
3125 {
3126 uint32_t cMipLevels;
3127 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3128 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3129
3130 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3131 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3132 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3133# ifdef DEBUG_GMR_ACCESS
3134 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3135# endif
3136 break;
3137 }
3138
3139 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3140 {
3141 uint32_t cMipLevels;
3142 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3143 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3144
3145 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3146 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3147 pCmd->multisampleCount, pCmd->autogenFilter,
3148 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3149 break;
3150 }
3151
3152 case SVGA_3D_CMD_SURFACE_DESTROY:
3153 {
3154 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3155 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3156 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3157 break;
3158 }
3159
3160 case SVGA_3D_CMD_SURFACE_COPY:
3161 {
3162 uint32_t cCopyBoxes;
3163 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3164 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3165
3166 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3167 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3168 break;
3169 }
3170
3171 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3172 {
3173 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3175
3176 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3177 break;
3178 }
3179
3180 case SVGA_3D_CMD_SURFACE_DMA:
3181 {
3182 uint32_t cCopyBoxes;
3183 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3184 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3185
3186 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3187 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3188 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3189 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3190 break;
3191 }
3192
3193 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3194 {
3195 uint32_t cRects;
3196 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3197 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3198
3199 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3200 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3201 break;
3202 }
3203
3204 case SVGA_3D_CMD_CONTEXT_DEFINE:
3205 {
3206 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3207 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3208
3209 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3210 break;
3211 }
3212
3213 case SVGA_3D_CMD_CONTEXT_DESTROY:
3214 {
3215 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3216 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3217
3218 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3219 break;
3220 }
3221
3222 case SVGA_3D_CMD_SETTRANSFORM:
3223 {
3224 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3225 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3226
3227 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3228 break;
3229 }
3230
3231 case SVGA_3D_CMD_SETZRANGE:
3232 {
3233 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3234 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3235
3236 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3237 break;
3238 }
3239
3240 case SVGA_3D_CMD_SETRENDERSTATE:
3241 {
3242 uint32_t cRenderStates;
3243 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3244 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3245
3246 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3247 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3248 break;
3249 }
3250
3251 case SVGA_3D_CMD_SETRENDERTARGET:
3252 {
3253 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3255
3256 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3257 break;
3258 }
3259
3260 case SVGA_3D_CMD_SETTEXTURESTATE:
3261 {
3262 uint32_t cTextureStates;
3263 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3264 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3265
3266 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3267 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3268 break;
3269 }
3270
3271 case SVGA_3D_CMD_SETMATERIAL:
3272 {
3273 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3275
3276 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3277 break;
3278 }
3279
3280 case SVGA_3D_CMD_SETLIGHTDATA:
3281 {
3282 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3283 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3284
3285 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3286 break;
3287 }
3288
3289 case SVGA_3D_CMD_SETLIGHTENABLED:
3290 {
3291 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3292 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3293
3294 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3295 break;
3296 }
3297
3298 case SVGA_3D_CMD_SETVIEWPORT:
3299 {
3300 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3301 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3302
3303 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3304 break;
3305 }
3306
3307 case SVGA_3D_CMD_SETCLIPPLANE:
3308 {
3309 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3310 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3311
3312 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3313 break;
3314 }
3315
3316 case SVGA_3D_CMD_CLEAR:
3317 {
3318 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3319 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3320 uint32_t cRects;
3321
3322 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3323 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3324 break;
3325 }
3326
3327 case SVGA_3D_CMD_PRESENT:
3328 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3329 {
3330 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3331 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3332 uint32_t cRects;
3333
3334 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3335
3336 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3337 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3338 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3339 break;
3340 }
3341
3342 case SVGA_3D_CMD_SHADER_DEFINE:
3343 {
3344 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3346 uint32_t cbData;
3347
3348 cbData = (pHdr->size - sizeof(*pCmd));
3349 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3350 break;
3351 }
3352
3353 case SVGA_3D_CMD_SHADER_DESTROY:
3354 {
3355 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3356 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3357
3358 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3359 break;
3360 }
3361
3362 case SVGA_3D_CMD_SET_SHADER:
3363 {
3364 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3365 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3366
3367 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3368 break;
3369 }
3370
3371 case SVGA_3D_CMD_SET_SHADER_CONST:
3372 {
3373 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3374 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3375
3376 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3377 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3378 break;
3379 }
3380
3381 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3382 {
3383 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3384 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3385 uint32_t cVertexDivisor;
3386
3387 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3388 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3389 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3390 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3391
3392 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3393 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3394 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3395
3396 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3397 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3398 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3399 break;
3400 }
3401
3402 case SVGA_3D_CMD_SETSCISSORRECT:
3403 {
3404 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3405 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3406
3407 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3408 break;
3409 }
3410
3411 case SVGA_3D_CMD_BEGIN_QUERY:
3412 {
3413 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3414 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3415
3416 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3417 break;
3418 }
3419
3420 case SVGA_3D_CMD_END_QUERY:
3421 {
3422 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3423 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3424
3425 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3426 break;
3427 }
3428
3429 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3430 {
3431 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3433
3434 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3435 break;
3436 }
3437
3438 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3439 {
3440 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3441 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3442
3443 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3444 break;
3445 }
3446
3447 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3448 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3449 /* context id + surface id? */
3450 break;
3451
3452 default:
3453 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3454 AssertFailed();
3455 break;
3456 }
3457 }
3458 else
3459# endif // VBOX_WITH_VMSVGA3D
3460 {
3461 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3462 AssertFailed();
3463 }
3464 }
3465
3466 /* Go to the next slot */
3467 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3468 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3469 if (offCurrentCmd >= offFifoMax)
3470 {
3471 offCurrentCmd -= offFifoMax - offFifoMin;
3472 Assert(offCurrentCmd >= offFifoMin);
3473 Assert(offCurrentCmd < offFifoMax);
3474 }
3475 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3476 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3477
3478 /*
3479 * Raise IRQ if required. Must enter the critical section here
3480 * before making final decisions here, otherwise cubebench and
3481 * others may end up waiting forever.
3482 */
3483 if ( u32IrqStatus
3484 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3485 {
3486 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3487
3488 /* FIFO progress might trigger an interrupt. */
3489 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3490 {
3491 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3492 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3493 }
3494
3495 /* Unmasked IRQ pending? */
3496 if (pThis->svga.u32IrqMask & u32IrqStatus)
3497 {
3498 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3499 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3500 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3501 }
3502
3503 PDMCritSectLeave(&pThis->CritSect);
3504 }
3505 }
3506
3507 /* If really done, clear the busy flag. */
3508 if (fDone)
3509 {
3510 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3511 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3512 }
3513 }
3514
3515 /*
3516 * Free the bounce buffer. (There are no returns above!)
3517 */
3518 RTMemFree(pbBounceBuf);
3519
3520 return VINF_SUCCESS;
3521}
3522
3523/**
3524 * Free the specified GMR
3525 *
3526 * @param pThis VGA device instance data.
3527 * @param idGMR GMR id
3528 */
3529void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3530{
3531 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3532
3533 /* Free the old descriptor if present. */
3534 if (pSVGAState->aGMR[idGMR].numDescriptors)
3535 {
3536 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3537# ifdef DEBUG_GMR_ACCESS
3538 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3539# endif
3540
3541 Assert(pGMR->paDesc);
3542 RTMemFree(pGMR->paDesc);
3543 pGMR->paDesc = NULL;
3544 pGMR->numDescriptors = 0;
3545 pGMR->cbTotal = 0;
3546 pGMR->cMaxPages = 0;
3547 }
3548 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3549}
3550
3551/**
3552 * Copy from a GMR to host memory or vice versa
3553 *
3554 * @returns VBox status code.
3555 * @param pThis VGA device instance data.
3556 * @param enmTransferType Transfer type (read/write)
3557 * @param pbDst Host destination pointer
3558 * @param cbDestPitch Destination buffer pitch
3559 * @param src GMR description
3560 * @param offSrc Source buffer offset
3561 * @param cbSrcPitch Source buffer pitch
3562 * @param cbWidth Source width in bytes
3563 * @param cHeight Source height
3564 */
3565int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3566 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3567{
3568 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3569 PGMR pGMR;
3570 int rc;
3571 PVMSVGAGMRDESCRIPTOR pDesc;
3572 unsigned offDesc = 0;
3573
3574 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3575 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3576 Assert(cbWidth && cHeight);
3577
3578 /* Shortcut for the framebuffer. */
3579 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3580 {
3581 offSrc += src.offset;
3582 AssertMsgReturn(src.offset < pThis->vram_size,
3583 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3584 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3585 VERR_INVALID_PARAMETER);
3586 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3587 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3588 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3589 VERR_INVALID_PARAMETER);
3590
3591 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3592
3593 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3594 {
3595 /* switch src & dest */
3596 uint8_t *pTemp = pbDst;
3597 int32_t cbTempPitch = cbDestPitch;
3598
3599 pbDst = pSrc;
3600 pSrc = pTemp;
3601
3602 cbDestPitch = cbSrcPitch;
3603 cbSrcPitch = cbTempPitch;
3604 }
3605
3606 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3607 && cbWidth == (uint32_t)cbDestPitch
3608 && cbSrcPitch == cbDestPitch)
3609 {
3610 memcpy(pbDst, pSrc, cbWidth * cHeight);
3611 }
3612 else
3613 {
3614 for(uint32_t i = 0; i < cHeight; i++)
3615 {
3616 memcpy(pbDst, pSrc, cbWidth);
3617
3618 pbDst += cbDestPitch;
3619 pSrc += cbSrcPitch;
3620 }
3621 }
3622 return VINF_SUCCESS;
3623 }
3624
3625 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3626 pGMR = &pSVGAState->aGMR[src.gmrId];
3627 pDesc = pGMR->paDesc;
3628
3629 offSrc += src.offset;
3630 AssertMsgReturn(src.offset < pGMR->cbTotal,
3631 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3632 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3633 VERR_INVALID_PARAMETER);
3634 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3635 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3636 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3637 VERR_INVALID_PARAMETER);
3638
3639 for (uint32_t i = 0; i < cHeight; i++)
3640 {
3641 uint32_t cbCurrentWidth = cbWidth;
3642 uint32_t offCurrent = offSrc;
3643 uint8_t *pCurrentDest = pbDst;
3644
3645 /* Find the right descriptor */
3646 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3647 {
3648 offDesc += pDesc->numPages * PAGE_SIZE;
3649 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3650 pDesc++;
3651 }
3652
3653 while (cbCurrentWidth)
3654 {
3655 uint32_t cbToCopy;
3656
3657 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3658 {
3659 cbToCopy = cbCurrentWidth;
3660 }
3661 else
3662 {
3663 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3664 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3665 }
3666
3667 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3668
3669 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3670 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3671 else
3672 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3673 AssertRCBreak(rc);
3674
3675 cbCurrentWidth -= cbToCopy;
3676 offCurrent += cbToCopy;
3677 pCurrentDest += cbToCopy;
3678
3679 /* Go to the next descriptor if there's anything left. */
3680 if (cbCurrentWidth)
3681 {
3682 offDesc += pDesc->numPages * PAGE_SIZE;
3683 pDesc++;
3684 }
3685 }
3686
3687 offSrc += cbSrcPitch;
3688 pbDst += cbDestPitch;
3689 }
3690
3691 return VINF_SUCCESS;
3692}
3693
3694/**
3695 * Unblock the FIFO I/O thread so it can respond to a state change.
3696 *
3697 * @returns VBox status code.
3698 * @param pDevIns The VGA device instance.
3699 * @param pThread The send thread.
3700 */
3701static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3702{
3703 RT_NOREF(pDevIns);
3704 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3705 Log(("vmsvgaFIFOLoopWakeUp\n"));
3706 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3707}
3708
3709/**
3710 * Enables or disables dirty page tracking for the framebuffer
3711 *
3712 * @param pThis VGA device instance data.
3713 * @param fTraces Enable/disable traces
3714 */
3715static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3716{
3717 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3718 && !fTraces)
3719 {
3720 //Assert(pThis->svga.fTraces);
3721 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3722 return;
3723 }
3724
3725 pThis->svga.fTraces = fTraces;
3726 if (pThis->svga.fTraces)
3727 {
3728 unsigned cbFrameBuffer = pThis->vram_size;
3729
3730 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3731 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3732 {
3733#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3734 Assert(pThis->svga.cbScanline);
3735#endif
3736 /* Hardware enabled; return real framebuffer size .*/
3737 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3738 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3739 }
3740
3741 if (!pThis->svga.fVRAMTracking)
3742 {
3743 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3744 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3745 pThis->svga.fVRAMTracking = true;
3746 }
3747 }
3748 else
3749 {
3750 if (pThis->svga.fVRAMTracking)
3751 {
3752 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3753 vgaR3UnregisterVRAMHandler(pThis);
3754 pThis->svga.fVRAMTracking = false;
3755 }
3756 }
3757}
3758
3759/**
3760 * Callback function for mapping a PCI I/O region.
3761 *
3762 * @return VBox status code.
3763 * @param pPciDev Pointer to PCI device.
3764 * Use pPciDev->pDevIns to get the device instance.
3765 * @param iRegion The region number.
3766 * @param GCPhysAddress Physical address of the region.
3767 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3768 * I/O port, else it's a physical address.
3769 * This address is *NOT* relative
3770 * to pci_mem_base like earlier!
3771 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3772 */
3773DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3774{
3775 int rc;
3776 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3777 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3778
3779 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3780 if (enmType == PCI_ADDRESS_SPACE_IO)
3781 {
3782 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3783 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3784 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3785 if (RT_FAILURE(rc))
3786 return rc;
3787 if (pThis->fR0Enabled)
3788 {
3789 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3790 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3791 if (RT_FAILURE(rc))
3792 return rc;
3793 }
3794 if (pThis->fGCEnabled)
3795 {
3796 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3797 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3798 if (RT_FAILURE(rc))
3799 return rc;
3800 }
3801
3802 pThis->svga.BasePort = GCPhysAddress;
3803 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3804 }
3805 else
3806 {
3807 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3808 if (GCPhysAddress != NIL_RTGCPHYS)
3809 {
3810 /*
3811 * Mapping the FIFO RAM.
3812 */
3813 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3814 AssertRC(rc);
3815
3816# ifdef DEBUG_FIFO_ACCESS
3817 if (RT_SUCCESS(rc))
3818 {
3819 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3820 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3821 "VMSVGA FIFO");
3822 AssertRC(rc);
3823 }
3824# endif
3825 if (RT_SUCCESS(rc))
3826 {
3827 pThis->svga.GCPhysFIFO = GCPhysAddress;
3828 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3829 }
3830 }
3831 else
3832 {
3833 Assert(pThis->svga.GCPhysFIFO);
3834# ifdef DEBUG_FIFO_ACCESS
3835 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3836 AssertRC(rc);
3837# endif
3838 pThis->svga.GCPhysFIFO = 0;
3839 }
3840
3841 }
3842 return VINF_SUCCESS;
3843}
3844
3845# ifdef VBOX_WITH_VMSVGA3D
3846
3847/**
3848 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3849 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3850 *
3851 * @param pThis The VGA device instance data.
3852 * @param sid Either UINT32_MAX or the ID of a specific
3853 * surface. If UINT32_MAX is used, all surfaces
3854 * are processed.
3855 */
3856void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3857{
3858 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3859 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3860}
3861
3862
3863/**
3864 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3865 */
3866DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3867{
3868 /* There might be a specific context ID at the start of the
3869 arguments, if not show all contexts. */
3870 uint32_t cid = UINT32_MAX;
3871 if (pszArgs)
3872 pszArgs = RTStrStripL(pszArgs);
3873 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3874 cid = RTStrToUInt32(pszArgs);
3875
3876 /* Verbose or terse display, we default to verbose. */
3877 bool fVerbose = true;
3878 if (RTStrIStr(pszArgs, "terse"))
3879 fVerbose = false;
3880
3881 /* The size of the ascii art (x direction, y is 3/4 of x). */
3882 uint32_t cxAscii = 80;
3883 if (RTStrIStr(pszArgs, "gigantic"))
3884 cxAscii = 300;
3885 else if (RTStrIStr(pszArgs, "huge"))
3886 cxAscii = 180;
3887 else if (RTStrIStr(pszArgs, "big"))
3888 cxAscii = 132;
3889 else if (RTStrIStr(pszArgs, "normal"))
3890 cxAscii = 80;
3891 else if (RTStrIStr(pszArgs, "medium"))
3892 cxAscii = 64;
3893 else if (RTStrIStr(pszArgs, "small"))
3894 cxAscii = 48;
3895 else if (RTStrIStr(pszArgs, "tiny"))
3896 cxAscii = 24;
3897
3898 /* Y invert the image when producing the ASCII art. */
3899 bool fInvY = false;
3900 if (RTStrIStr(pszArgs, "invy"))
3901 fInvY = true;
3902
3903 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3904}
3905
3906
3907/**
3908 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3909 */
3910DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3911{
3912 /* There might be a specific surface ID at the start of the
3913 arguments, if not show all contexts. */
3914 uint32_t sid = UINT32_MAX;
3915 if (pszArgs)
3916 pszArgs = RTStrStripL(pszArgs);
3917 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3918 sid = RTStrToUInt32(pszArgs);
3919
3920 /* Verbose or terse display, we default to verbose. */
3921 bool fVerbose = true;
3922 if (RTStrIStr(pszArgs, "terse"))
3923 fVerbose = false;
3924
3925 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3926}
3927
3928# endif /* VBOX_WITH_VMSVGA3D */
3929
3930/**
3931 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3932 */
3933static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3934{
3935 RT_NOREF(pszArgs);
3936 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3937 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3938
3939 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3940 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3941 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3942 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3943 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3944 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3945 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3946 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3947 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3948 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3949 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3950 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3951 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3952 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3953 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3954 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3955 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3956 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3957 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3958 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3959 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3960 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3961
3962 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3963 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3964 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3965 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3966
3967# ifdef VBOX_WITH_VMSVGA3D
3968 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3969 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3970 if (pThis->svga.u64HostWindowId != 0)
3971 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3972# endif
3973}
3974
3975
3976/**
3977 * @copydoc FNSSMDEVLOADEXEC
3978 */
3979int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3980{
3981 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3982 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3983 int rc;
3984
3985 /* Load our part of the VGAState */
3986 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3987 AssertRCReturn(rc, rc);
3988
3989 /* Load the framebuffer backup. */
3990 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3991 AssertRCReturn(rc, rc);
3992
3993 /* Load the VMSVGA state. */
3994 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3995 AssertRCReturn(rc, rc);
3996
3997 /* Load the active cursor bitmaps. */
3998 if (pSVGAState->Cursor.fActive)
3999 {
4000 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
4001 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
4002
4003 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4004 AssertRCReturn(rc, rc);
4005 }
4006
4007 /* Load the GMR state */
4008 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4009 {
4010 PGMR pGMR = &pSVGAState->aGMR[i];
4011
4012 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4013 AssertRCReturn(rc, rc);
4014
4015 if (pGMR->numDescriptors)
4016 {
4017 /* Allocate the maximum amount possible (everything non-continuous) */
4018 Assert(pGMR->cMaxPages || pGMR->cbTotal);
4019 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
4020 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4021
4022 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
4023 {
4024 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4025 AssertRCReturn(rc, rc);
4026 }
4027 }
4028 }
4029
4030# ifdef VBOX_WITH_VMSVGA3D
4031 if (pThis->svga.f3DEnabled)
4032 {
4033# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4034 vmsvga3dPowerOn(pThis);
4035# endif
4036
4037 VMSVGA_STATE_LOAD LoadState;
4038 LoadState.pSSM = pSSM;
4039 LoadState.uVersion = uVersion;
4040 LoadState.uPass = uPass;
4041 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4042 AssertLogRelRCReturn(rc, rc);
4043 }
4044# endif
4045
4046 return VINF_SUCCESS;
4047}
4048
4049/**
4050 * Reinit the video mode after the state has been loaded.
4051 */
4052int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4053{
4054 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4055 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4056
4057 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4058 vmsvgaChangeMode(pThis);
4059
4060 /* Set the active cursor. */
4061 if (pSVGAState->Cursor.fActive)
4062 {
4063 int rc;
4064
4065 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4066 true,
4067 true,
4068 pSVGAState->Cursor.xHotspot,
4069 pSVGAState->Cursor.yHotspot,
4070 pSVGAState->Cursor.width,
4071 pSVGAState->Cursor.height,
4072 pSVGAState->Cursor.pData);
4073 AssertRC(rc);
4074 }
4075 return VINF_SUCCESS;
4076}
4077
4078/**
4079 * @copydoc FNSSMDEVSAVEEXEC
4080 */
4081int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4082{
4083 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4084 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4085 int rc;
4086
4087 /* Save our part of the VGAState */
4088 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4089 AssertLogRelRCReturn(rc, rc);
4090
4091 /* Save the framebuffer backup. */
4092 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4093 AssertLogRelRCReturn(rc, rc);
4094
4095 /* Save the VMSVGA state. */
4096 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4097 AssertLogRelRCReturn(rc, rc);
4098
4099 /* Save the active cursor bitmaps. */
4100 if (pSVGAState->Cursor.fActive)
4101 {
4102 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4103 AssertLogRelRCReturn(rc, rc);
4104 }
4105
4106 /* Save the GMR state */
4107 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4108 {
4109 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4110 AssertLogRelRCReturn(rc, rc);
4111
4112 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4113 {
4114 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4115 AssertLogRelRCReturn(rc, rc);
4116 }
4117 }
4118
4119# ifdef VBOX_WITH_VMSVGA3D
4120 /*
4121 * Must save the 3d state in the FIFO thread.
4122 */
4123 if (pThis->svga.f3DEnabled)
4124 {
4125 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4126 AssertLogRelRCReturn(rc, rc);
4127 }
4128# endif
4129 return VINF_SUCCESS;
4130}
4131
4132/**
4133 * Resets the SVGA hardware state
4134 *
4135 * @returns VBox status code.
4136 * @param pDevIns The device instance.
4137 */
4138int vmsvgaReset(PPDMDEVINS pDevIns)
4139{
4140 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4141 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4142
4143 /* Reset before init? */
4144 if (!pSVGAState)
4145 return VINF_SUCCESS;
4146
4147 Log(("vmsvgaReset\n"));
4148
4149
4150 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4151 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4152 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4153
4154 /* Reset other stuff. */
4155 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4156 RT_ZERO(pThis->svga.au32ScratchRegion);
4157 RT_ZERO(*pThis->svga.pSvgaR3State);
4158 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4159
4160 /* Register caps. */
4161 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4162# ifdef VBOX_WITH_VMSVGA3D
4163 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4164# endif
4165
4166 /* Setup FIFO capabilities. */
4167 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4168
4169 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4170 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4171
4172 /* VRAM tracking is enabled by default during bootup. */
4173 pThis->svga.fVRAMTracking = true;
4174 pThis->svga.fEnabled = false;
4175
4176 /* Invalidate current settings. */
4177 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4178 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4179 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4180 pThis->svga.cbScanline = 0;
4181
4182 return rc;
4183}
4184
4185/**
4186 * Cleans up the SVGA hardware state
4187 *
4188 * @returns VBox status code.
4189 * @param pDevIns The device instance.
4190 */
4191int vmsvgaDestruct(PPDMDEVINS pDevIns)
4192{
4193 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4194
4195 /*
4196 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4197 */
4198 if (pThis->svga.pFIFOIOThread)
4199 {
4200 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4201 AssertLogRelRC(rc);
4202
4203 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4204 AssertLogRelRC(rc);
4205 pThis->svga.pFIFOIOThread = NULL;
4206 }
4207
4208 /*
4209 * Destroy the special SVGA state.
4210 */
4211 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4212 if (pSVGAState)
4213 {
4214# ifndef VMSVGA_USE_EMT_HALT_CODE
4215 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4216 {
4217 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4218 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4219 }
4220# endif
4221 if (pSVGAState->Cursor.fActive)
4222 RTMemFree(pSVGAState->Cursor.pData);
4223
4224 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4225 if (pSVGAState->aGMR[i].paDesc)
4226 RTMemFree(pSVGAState->aGMR[i].paDesc);
4227
4228 RTMemFree(pSVGAState);
4229 pThis->svga.pSvgaR3State = NULL;
4230 }
4231
4232 /*
4233 * Free our resources residing in the VGA state.
4234 */
4235 if (pThis->svga.pFrameBufferBackup)
4236 RTMemFree(pThis->svga.pFrameBufferBackup);
4237 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4238 {
4239 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4240 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4241 }
4242 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4243 {
4244 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4245 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4246 }
4247
4248 return VINF_SUCCESS;
4249}
4250
4251/**
4252 * Initialize the SVGA hardware state
4253 *
4254 * @returns VBox status code.
4255 * @param pDevIns The device instance.
4256 */
4257int vmsvgaInit(PPDMDEVINS pDevIns)
4258{
4259 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4260 PVMSVGAR3STATE pSVGAState;
4261 PVM pVM = PDMDevHlpGetVM(pDevIns);
4262 int rc;
4263
4264 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4265 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4266
4267 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4268 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4269 pSVGAState = pThis->svga.pSvgaR3State;
4270
4271 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4272 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4273 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4274
4275 /* Create event semaphore. */
4276 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4277
4278 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4279 if (RT_FAILURE(rc))
4280 {
4281 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4282 return rc;
4283 }
4284
4285 /* Create event semaphore. */
4286 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4287 if (RT_FAILURE(rc))
4288 {
4289 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4290 return rc;
4291 }
4292
4293# ifndef VMSVGA_USE_EMT_HALT_CODE
4294 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4295 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4296 AssertRCReturn(rc, rc);
4297# endif
4298
4299 /* Register caps. */
4300 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4301# ifdef VBOX_WITH_VMSVGA3D
4302 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4303# endif
4304
4305 /* Setup FIFO capabilities. */
4306 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4307
4308 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4309 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4310
4311 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4312# ifdef VBOX_WITH_VMSVGA3D
4313 if (pThis->svga.f3DEnabled)
4314 {
4315 rc = vmsvga3dInit(pThis);
4316 if (RT_FAILURE(rc))
4317 {
4318 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4319 pThis->svga.f3DEnabled = false;
4320 }
4321 }
4322# endif
4323 /* VRAM tracking is enabled by default during bootup. */
4324 pThis->svga.fVRAMTracking = true;
4325
4326 /* Invalidate current settings. */
4327 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4328 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4329 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4330 pThis->svga.cbScanline = 0;
4331
4332 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4333 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4334 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4335 {
4336 pThis->svga.u32MaxWidth -= 256;
4337 pThis->svga.u32MaxHeight -= 256;
4338 }
4339 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4340
4341# ifdef DEBUG_GMR_ACCESS
4342 /* Register the GMR access handler type. */
4343 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4344 vmsvgaR3GMRAccessHandler,
4345 NULL, NULL, NULL,
4346 NULL, NULL, NULL,
4347 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4348 AssertRCReturn(rc, rc);
4349# endif
4350# ifdef DEBUG_FIFO_ACCESS
4351 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4352 vmsvgaR3FIFOAccessHandler,
4353 NULL, NULL, NULL,
4354 NULL, NULL, NULL,
4355 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4356 AssertRCReturn(rc, rc);
4357#endif
4358
4359 /* Create the async IO thread. */
4360 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4361 RTTHREADTYPE_IO, "VMSVGA FIFO");
4362 if (RT_FAILURE(rc))
4363 {
4364 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4365 return rc;
4366 }
4367
4368 /*
4369 * Statistics.
4370 */
4371 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4372 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4373 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4374 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4375 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4376 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4377 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4378 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4379 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4380 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4381
4382 /*
4383 * Info handlers.
4384 */
4385 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4386# ifdef VBOX_WITH_VMSVGA3D
4387 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4388 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4389 "VMSVGA 3d surface details. "
4390 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4391 vmsvgaR3Info3dSurface);
4392# endif
4393
4394 return VINF_SUCCESS;
4395}
4396
4397# ifdef VBOX_WITH_VMSVGA3D
4398/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4399static const char * const g_apszVmSvgaDevCapNames[] =
4400{
4401 "x3D", /* = 0 */
4402 "xMAX_LIGHTS",
4403 "xMAX_TEXTURES",
4404 "xMAX_CLIP_PLANES",
4405 "xVERTEX_SHADER_VERSION",
4406 "xVERTEX_SHADER",
4407 "xFRAGMENT_SHADER_VERSION",
4408 "xFRAGMENT_SHADER",
4409 "xMAX_RENDER_TARGETS",
4410 "xS23E8_TEXTURES",
4411 "xS10E5_TEXTURES",
4412 "xMAX_FIXED_VERTEXBLEND",
4413 "xD16_BUFFER_FORMAT",
4414 "xD24S8_BUFFER_FORMAT",
4415 "xD24X8_BUFFER_FORMAT",
4416 "xQUERY_TYPES",
4417 "xTEXTURE_GRADIENT_SAMPLING",
4418 "rMAX_POINT_SIZE",
4419 "xMAX_SHADER_TEXTURES",
4420 "xMAX_TEXTURE_WIDTH",
4421 "xMAX_TEXTURE_HEIGHT",
4422 "xMAX_VOLUME_EXTENT",
4423 "xMAX_TEXTURE_REPEAT",
4424 "xMAX_TEXTURE_ASPECT_RATIO",
4425 "xMAX_TEXTURE_ANISOTROPY",
4426 "xMAX_PRIMITIVE_COUNT",
4427 "xMAX_VERTEX_INDEX",
4428 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4429 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4430 "xMAX_VERTEX_SHADER_TEMPS",
4431 "xMAX_FRAGMENT_SHADER_TEMPS",
4432 "xTEXTURE_OPS",
4433 "xSURFACEFMT_X8R8G8B8",
4434 "xSURFACEFMT_A8R8G8B8",
4435 "xSURFACEFMT_A2R10G10B10",
4436 "xSURFACEFMT_X1R5G5B5",
4437 "xSURFACEFMT_A1R5G5B5",
4438 "xSURFACEFMT_A4R4G4B4",
4439 "xSURFACEFMT_R5G6B5",
4440 "xSURFACEFMT_LUMINANCE16",
4441 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4442 "xSURFACEFMT_ALPHA8",
4443 "xSURFACEFMT_LUMINANCE8",
4444 "xSURFACEFMT_Z_D16",
4445 "xSURFACEFMT_Z_D24S8",
4446 "xSURFACEFMT_Z_D24X8",
4447 "xSURFACEFMT_DXT1",
4448 "xSURFACEFMT_DXT2",
4449 "xSURFACEFMT_DXT3",
4450 "xSURFACEFMT_DXT4",
4451 "xSURFACEFMT_DXT5",
4452 "xSURFACEFMT_BUMPX8L8V8U8",
4453 "xSURFACEFMT_A2W10V10U10",
4454 "xSURFACEFMT_BUMPU8V8",
4455 "xSURFACEFMT_Q8W8V8U8",
4456 "xSURFACEFMT_CxV8U8",
4457 "xSURFACEFMT_R_S10E5",
4458 "xSURFACEFMT_R_S23E8",
4459 "xSURFACEFMT_RG_S10E5",
4460 "xSURFACEFMT_RG_S23E8",
4461 "xSURFACEFMT_ARGB_S10E5",
4462 "xSURFACEFMT_ARGB_S23E8",
4463 "xMISSING62",
4464 "xMAX_VERTEX_SHADER_TEXTURES",
4465 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4466 "xSURFACEFMT_V16U16",
4467 "xSURFACEFMT_G16R16",
4468 "xSURFACEFMT_A16B16G16R16",
4469 "xSURFACEFMT_UYVY",
4470 "xSURFACEFMT_YUY2",
4471 "xMULTISAMPLE_NONMASKABLESAMPLES",
4472 "xMULTISAMPLE_MASKABLESAMPLES",
4473 "xALPHATOCOVERAGE",
4474 "xSUPERSAMPLE",
4475 "xAUTOGENMIPMAPS",
4476 "xSURFACEFMT_NV12",
4477 "xSURFACEFMT_AYUV",
4478 "xMAX_CONTEXT_IDS",
4479 "xMAX_SURFACE_IDS",
4480 "xSURFACEFMT_Z_DF16",
4481 "xSURFACEFMT_Z_DF24",
4482 "xSURFACEFMT_Z_D24S8_INT",
4483 "xSURFACEFMT_BC4_UNORM",
4484 "xSURFACEFMT_BC5_UNORM", /* 83 */
4485};
4486# endif
4487
4488
4489/**
4490 * Power On notification.
4491 *
4492 * @returns VBox status code.
4493 * @param pDevIns The device instance data.
4494 *
4495 * @remarks Caller enters the device critical section.
4496 */
4497DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4498{
4499 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4500 int rc;
4501
4502# ifdef VBOX_WITH_VMSVGA3D
4503 if (pThis->svga.f3DEnabled)
4504 {
4505 rc = vmsvga3dPowerOn(pThis);
4506
4507 if (RT_SUCCESS(rc))
4508 {
4509 bool fSavedBuffering = RTLogRelSetBuffering(true);
4510 SVGA3dCapsRecord *pCaps;
4511 SVGA3dCapPair *pData;
4512 uint32_t idxCap = 0;
4513
4514 /* 3d hardware version; latest and greatest */
4515 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4516 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4517
4518 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4519 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4520 pData = (SVGA3dCapPair *)&pCaps->data;
4521
4522 /* Fill out all 3d capabilities. */
4523 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4524 {
4525 uint32_t val = 0;
4526
4527 rc = vmsvga3dQueryCaps(pThis, i, &val);
4528 if (RT_SUCCESS(rc))
4529 {
4530 pData[idxCap][0] = i;
4531 pData[idxCap][1] = val;
4532 idxCap++;
4533 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4534 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4535 else
4536 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4537 &g_apszVmSvgaDevCapNames[i][1]));
4538 }
4539 else
4540 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4541 }
4542 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4543 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4544
4545 /* Mark end of record array. */
4546 pCaps->header.length = 0;
4547
4548 RTLogRelSetBuffering(fSavedBuffering);
4549 }
4550 }
4551# endif // VBOX_WITH_VMSVGA3D
4552}
4553
4554#endif /* IN_RING3 */
4555
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