DevVGA-SVGA.cpp@ 77918

Last change on this file since 77918 was 77915, checked in by vboxsync, 6 years ago
VMSVGA: Calculate pitch when width or bpp is set. See bugref:9424
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1	/* $Id: DevVGA-SVGA.cpp 77915 2019-03-27 12:41:27Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
249	STAMPROFILE StatBusyDelayEmts;
250
251	STAMPROFILE StatR3Cmd3dPresentProf;
252	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
253	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
254	STAMCOUNTER StatR3CmdDefineGmr2;
255	STAMCOUNTER StatR3CmdDefineGmr2Free;
256	STAMCOUNTER StatR3CmdDefineGmr2Modify;
257	STAMCOUNTER StatR3CmdRemapGmr2;
258	STAMCOUNTER StatR3CmdRemapGmr2Modify;
259	STAMCOUNTER StatR3CmdInvalidCmd;
260	STAMCOUNTER StatR3CmdFence;
261	STAMCOUNTER StatR3CmdUpdate;
262	STAMCOUNTER StatR3CmdUpdateVerbose;
263	STAMCOUNTER StatR3CmdDefineCursor;
264	STAMCOUNTER StatR3CmdDefineAlphaCursor;
265	STAMCOUNTER StatR3CmdEscape;
266	STAMCOUNTER StatR3CmdDefineScreen;
267	STAMCOUNTER StatR3CmdDestroyScreen;
268	STAMCOUNTER StatR3CmdDefineGmrFb;
269	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
270	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
271	STAMCOUNTER StatR3CmdAnnotationFill;
272	STAMCOUNTER StatR3CmdAnnotationCopy;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
275	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
276	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
277	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
278	STAMCOUNTER StatR3Cmd3dSurfaceDma;
279	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
280	STAMCOUNTER StatR3Cmd3dContextDefine;
281	STAMCOUNTER StatR3Cmd3dContextDestroy;
282	STAMCOUNTER StatR3Cmd3dSetTransform;
283	STAMCOUNTER StatR3Cmd3dSetZRange;
284	STAMCOUNTER StatR3Cmd3dSetRenderState;
285	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
286	STAMCOUNTER StatR3Cmd3dSetTextureState;
287	STAMCOUNTER StatR3Cmd3dSetMaterial;
288	STAMCOUNTER StatR3Cmd3dSetLightData;
289	STAMCOUNTER StatR3Cmd3dSetLightEnable;
290	STAMCOUNTER StatR3Cmd3dSetViewPort;
291	STAMCOUNTER StatR3Cmd3dSetClipPlane;
292	STAMCOUNTER StatR3Cmd3dClear;
293	STAMCOUNTER StatR3Cmd3dPresent;
294	STAMCOUNTER StatR3Cmd3dPresentReadBack;
295	STAMCOUNTER StatR3Cmd3dShaderDefine;
296	STAMCOUNTER StatR3Cmd3dShaderDestroy;
297	STAMCOUNTER StatR3Cmd3dSetShader;
298	STAMCOUNTER StatR3Cmd3dSetShaderConst;
299	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
300	STAMCOUNTER StatR3Cmd3dSetScissorRect;
301	STAMCOUNTER StatR3Cmd3dBeginQuery;
302	STAMCOUNTER StatR3Cmd3dEndQuery;
303	STAMCOUNTER StatR3Cmd3dWaitForQuery;
304	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
305	STAMCOUNTER StatR3Cmd3dActivateSurface;
306	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
307
308	STAMCOUNTER StatR3RegConfigDoneWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
311	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
312
313	STAMCOUNTER StatFifoCommands;
314	STAMCOUNTER StatFifoErrors;
315	STAMCOUNTER StatFifoUnkCmds;
316	STAMCOUNTER StatFifoTodoTimeout;
317	STAMCOUNTER StatFifoTodoWoken;
318	STAMPROFILE StatFifoStalls;
319	STAMPROFILE StatFifoExtendedSleep;
320	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
321	STAMCOUNTER StatFifoAccessHandler;
322	# endif
323	STAMCOUNTER StatFifoCursorFetchAgain;
324	STAMCOUNTER StatFifoCursorNoChange;
325	STAMCOUNTER StatFifoCursorPosition;
326	STAMCOUNTER StatFifoCursorVisiblity;
327	STAMCOUNTER StatFifoWatchdogWakeUps;
328	} VMSVGAR3STATE, *PVMSVGAR3STATE;
329	#endif /* IN_RING3 */
330
331
332	/*********************************************************************************************************************************
333	* Internal Functions *
334	*********************************************************************************************************************************/
335	#ifdef IN_RING3
336	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
337	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
338	# endif
339	# ifdef DEBUG_GMR_ACCESS
340	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
341	# endif
342	#endif
343
344
345	/*********************************************************************************************************************************
346	* Global Variables *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349
350	/**
351	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
352	*/
353	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
354	{
355	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
356	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
357	SSMFIELD_ENTRY_TERM()
358	};
359
360	/**
361	* SSM descriptor table for the GMR structure.
362	*/
363	static SSMFIELD const g_aGMRFields[] =
364	{
365	SSMFIELD_ENTRY( GMR, cMaxPages),
366	SSMFIELD_ENTRY( GMR, cbTotal),
367	SSMFIELD_ENTRY( GMR, numDescriptors),
368	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
369	SSMFIELD_ENTRY_TERM()
370	};
371
372	/**
373	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
374	*/
375	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
376	{
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
388	SSMFIELD_ENTRY_TERM()
389	};
390
391	/**
392	* SSM descriptor table for the VMSVGAR3STATE structure.
393	*/
394	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
395	{
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
397	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
404	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
407	#ifdef VMSVGA_USE_EMT_HALT_CODE
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
409	#else
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
411	#endif
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
469
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
474
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
482	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
484	# endif
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
489
490	SSMFIELD_ENTRY_TERM()
491	};
492
493	/**
494	* SSM descriptor table for the VGAState.svga structure.
495	*/
496	static SSMFIELD const g_aVGAStateSVGAFields[] =
497	{
498	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	{
811	*pu32 = pThis->svga.uWidth;
812	}
813	else
814	{
815	#ifndef IN_RING3
816	rc = VINF_IOM_R3_IOPORT_READ;
817	#else
818	*pu32 = pThis->pDrv->cx;
819	#endif
820	}
821	break;
822	}
823
824	case SVGA_REG_HEIGHT:
825	{
826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
827	if ( pThis->svga.fEnabled
828	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
829	{
830	*pu32 = pThis->svga.uHeight;
831	}
832	else
833	{
834	#ifndef IN_RING3
835	rc = VINF_IOM_R3_IOPORT_READ;
836	#else
837	*pu32 = pThis->pDrv->cy;
838	#endif
839	}
840	break;
841	}
842
843	case SVGA_REG_MAX_WIDTH:
844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
845	*pu32 = pThis->svga.u32MaxWidth;
846	break;
847
848	case SVGA_REG_MAX_HEIGHT:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
850	*pu32 = pThis->svga.u32MaxHeight;
851	break;
852
853	case SVGA_REG_DEPTH:
854	/* This returns the color depth of the current mode. */
855	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
856	switch (pThis->svga.uBpp)
857	{
858	case 15:
859	case 16:
860	case 24:
861	*pu32 = pThis->svga.uBpp;
862	break;
863
864	default:
865	case 32:
866	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
867	break;
868	}
869	break;
870
871	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
873	if ( pThis->svga.fEnabled
874	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
875	{
876	*pu32 = pThis->svga.uBpp;
877	}
878	else
879	{
880	#ifndef IN_RING3
881	rc = VINF_IOM_R3_IOPORT_READ;
882	#else
883	*pu32 = pThis->pDrv->cBits;
884	#endif
885	}
886	break;
887
888	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
890	if ( pThis->svga.fEnabled
891	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
892	{
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	}
895	else
896	{
897	#ifndef IN_RING3
898	rc = VINF_IOM_R3_IOPORT_READ;
899	#else
900	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
901	#endif
902	}
903	break;
904
905	case SVGA_REG_PSEUDOCOLOR:
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
907	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
908	break;
909
910	case SVGA_REG_RED_MASK:
911	case SVGA_REG_GREEN_MASK:
912	case SVGA_REG_BLUE_MASK:
913	{
914	uint32_t uBpp;
915
916	if ( pThis->svga.fEnabled
917	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
918	{
919	uBpp = pThis->svga.uBpp;
920	}
921	else
922	{
923	#ifndef IN_RING3
924	rc = VINF_IOM_R3_IOPORT_READ;
925	break;
926	#else
927	uBpp = pThis->pDrv->cBits;
928	#endif
929	}
930	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
931	switch (uBpp)
932	{
933	case 8:
934	u32RedMask = 0x07;
935	u32GreenMask = 0x38;
936	u32BlueMask = 0xc0;
937	break;
938
939	case 15:
940	u32RedMask = 0x0000001f;
941	u32GreenMask = 0x000003e0;
942	u32BlueMask = 0x00007c00;
943	break;
944
945	case 16:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000007e0;
948	u32BlueMask = 0x0000f800;
949	break;
950
951	case 24:
952	case 32:
953	default:
954	u32RedMask = 0x00ff0000;
955	u32GreenMask = 0x0000ff00;
956	u32BlueMask = 0x000000ff;
957	break;
958	}
959	switch (idxReg)
960	{
961	case SVGA_REG_RED_MASK:
962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
963	*pu32 = u32RedMask;
964	break;
965
966	case SVGA_REG_GREEN_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
968	*pu32 = u32GreenMask;
969	break;
970
971	case SVGA_REG_BLUE_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
973	*pu32 = u32BlueMask;
974	break;
975	}
976	break;
977	}
978
979	case SVGA_REG_BYTES_PER_LINE:
980	{
981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
982	if ( pThis->svga.fEnabled
983	&& pThis->svga.cbScanline)
984	{
985	*pu32 = pThis->svga.cbScanline;
986	}
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThis->pDrv->cbScanline;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_VRAM_SIZE: /* VRAM size */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1000	*pu32 = pThis->vram_size;
1001	break;
1002
1003	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1005	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1006	*pu32 = pThis->GCPhysVRAM;
1007	break;
1008
1009	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1011	/* Always zero in our case. */
1012	*pu32 = 0;
1013	break;
1014
1015	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1016	{
1017	#ifndef IN_RING3
1018	rc = VINF_IOM_R3_IOPORT_READ;
1019	#else
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1021
1022	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1023	if ( pThis->svga.fEnabled
1024	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1025	{
1026	/* Hardware enabled; return real framebuffer size .*/
1027	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1028	}
1029	else
1030	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1031
1032	pu32 = RT_MIN(pThis->vram_size, pu32);
1033	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1034	#endif
1035	break;
1036	}
1037
1038	case SVGA_REG_CAPABILITIES:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1040	*pu32 = pThis->svga.u32RegCaps;
1041	break;
1042
1043	case SVGA_REG_MEM_START: /* FIFO start */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1045	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1046	*pu32 = pThis->svga.GCPhysFIFO;
1047	break;
1048
1049	case SVGA_REG_MEM_SIZE: /* FIFO size */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1051	*pu32 = pThis->svga.cbFIFO;
1052	break;
1053
1054	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1056	*pu32 = pThis->svga.fConfigured;
1057	break;
1058
1059	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1061	*pu32 = 0;
1062	break;
1063
1064	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1066	if (pThis->svga.fBusy)
1067	{
1068	#ifndef IN_RING3
1069	/* Go to ring-3 and halt the CPU. */
1070	rc = VINF_IOM_R3_IOPORT_READ;
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	if (pThis->svga.fGFBRegisters)
1422	{
1423	vgaR3UpdateDisplay(pThis, x, y, w, h);
1424	}
1425	else
1426	{
1427	VBVACMDHDR cmd;
1428	cmd.x = (int16_t)(pScreen->xOrigin + x);
1429	cmd.y = (int16_t)(pScreen->yOrigin + y);
1430	cmd.w = (uint16_t)w;
1431	cmd.h = (uint16_t)h;
1432
1433	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1434	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1435	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1436	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1437	}
1438
1439	return VINF_SUCCESS;
1440	}
1441
1442	#endif /* IN_RING3 */
1443
1444	#if defined(IN_RING0) \|\| defined(IN_RING3)
1445	/**
1446	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1447	*
1448	* @param pThis The VMSVGA state.
1449	* @param fState The busy state.
1450	*/
1451	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1452	{
1453	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1454
1455	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1456	{
1457	/* Race / unfortunately scheduling. Highly unlikly. */
1458	uint32_t cLoops = 64;
1459	do
1460	{
1461	ASMNopPause();
1462	fState = (pThis->svga.fBusy != 0);
1463	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1464	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1465	}
1466	}
1467	#endif
1468
1469	/**
1470	* Write port register
1471	*
1472	* @returns VBox status code.
1473	* @param pThis VMSVGA State
1474	* @param u32 Value to write
1475	*/
1476	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1477	{
1478	#ifdef IN_RING3
1479	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1480	#endif
1481	int rc = VINF_SUCCESS;
1482
1483	/* Rough index register validation. */
1484	uint32_t idxReg = pThis->svga.u32IndexReg;
1485	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1486	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1487	VINF_IOM_R3_IOPORT_WRITE);
1488	#else
1489	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1491	VINF_SUCCESS);
1492	#endif
1493	RT_UNTRUSTED_VALIDATED_FENCE();
1494
1495	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1496	if ( idxReg >= SVGA_REG_CAPABILITIES
1497	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1498	{
1499	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1500	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1501	}
1502	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1503	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1504	switch (idxReg)
1505	{
1506	case SVGA_REG_WIDTH:
1507	case SVGA_REG_HEIGHT:
1508	case SVGA_REG_PITCHLOCK:
1509	case SVGA_REG_BITS_PER_PIXEL:
1510	pThis->svga.fGFBRegisters = true;
1511	break;
1512	default:
1513	break;
1514	}
1515
1516	switch (idxReg)
1517	{
1518	case SVGA_REG_ID:
1519	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1520	if ( u32 == SVGA_ID_0
1521	\|\| u32 == SVGA_ID_1
1522	\|\| u32 == SVGA_ID_2)
1523	pThis->svga.u32SVGAId = u32;
1524	else
1525	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1526	break;
1527
1528	case SVGA_REG_ENABLE:
1529	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1530	#ifdef IN_RING3
1531	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1532	&& pThis->svga.fEnabled == false)
1533	{
1534	/* Make a backup copy of the first 512kb in order to save font data etc. */
1535	/** @todo should probably swap here, rather than copy + zero */
1536	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1537	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1538	}
1539
1540	pThis->svga.fEnabled = u32;
1541	if (pThis->svga.fEnabled)
1542	{
1543	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1544	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1545	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1546	{
1547	/* Keep the current mode. */
1548	pThis->svga.uWidth = pThis->pDrv->cx;
1549	pThis->svga.uHeight = pThis->pDrv->cy;
1550	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1551	}
1552
1553	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1554	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1555	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1556	{
1557	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1558	}
1559	# ifdef LOG_ENABLED
1560	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1561	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1562	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1563	# endif
1564
1565	/* Disable or enable dirty page tracking according to the current fTraces value. */
1566	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1567
1568	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1569	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1570	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1571	}
1572	else
1573	{
1574	/* Restore the text mode backup. */
1575	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1576
1577	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1578
1579	/* Enable dirty page tracking again when going into legacy mode. */
1580	vmsvgaSetTraces(pThis, true);
1581
1582	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1583	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1584	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1585	}
1586	#else /* !IN_RING3 */
1587	rc = VINF_IOM_R3_IOPORT_WRITE;
1588	#endif /* !IN_RING3 */
1589	break;
1590
1591	case SVGA_REG_WIDTH:
1592	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1593	if (pThis->svga.uWidth != u32)
1594	{
1595	pThis->svga.uWidth = u32;
1596	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1597	if (pThis->svga.fEnabled)
1598	{
1599	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1600	}
1601	}
1602	/* else: nop */
1603	break;
1604
1605	case SVGA_REG_HEIGHT:
1606	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1607	if (pThis->svga.uHeight != u32)
1608	{
1609	pThis->svga.uHeight = u32;
1610	if (pThis->svga.fEnabled)
1611	{
1612	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1613	}
1614	}
1615	/* else: nop */
1616	break;
1617
1618	case SVGA_REG_DEPTH:
1619	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1620	/** @todo read-only?? */
1621	break;
1622
1623	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1624	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1625	if (pThis->svga.uBpp != u32)
1626	{
1627	pThis->svga.uBpp = u32;
1628	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1629	if (pThis->svga.fEnabled)
1630	{
1631	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1632	}
1633	}
1634	/* else: nop */
1635	break;
1636
1637	case SVGA_REG_PSEUDOCOLOR:
1638	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1639	break;
1640
1641	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1642	#ifdef IN_RING3
1643	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1644	pThis->svga.fConfigured = u32;
1645	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1646	if (!pThis->svga.fConfigured)
1647	{
1648	pThis->svga.fTraces = true;
1649	}
1650	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1651	#else
1652	rc = VINF_IOM_R3_IOPORT_WRITE;
1653	#endif
1654	break;
1655
1656	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1657	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1658	if ( pThis->svga.fEnabled
1659	&& pThis->svga.fConfigured)
1660	{
1661	#if defined(IN_RING3) \|\| defined(IN_RING0)
1662	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1663	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1664	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1665	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1666
1667	/* Kick the FIFO thread to start processing commands again. */
1668	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1669	#else
1670	rc = VINF_IOM_R3_IOPORT_WRITE;
1671	#endif
1672	}
1673	/* else nothing to do. */
1674	else
1675	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1676
1677	break;
1678
1679	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1680	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1681	break;
1682
1683	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1684	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1685	pThis->svga.u32GuestId = u32;
1686	break;
1687
1688	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1689	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1690	pThis->svga.u32PitchLock = u32;
1691	break;
1692
1693	case SVGA_REG_IRQMASK: /* Interrupt mask */
1694	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1695	pThis->svga.u32IrqMask = u32;
1696
1697	/* Irq pending after the above change? */
1698	if (pThis->svga.u32IrqStatus & u32)
1699	{
1700	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1701	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1702	}
1703	else
1704	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1705	break;
1706
1707	/* Mouse cursor support */
1708	case SVGA_REG_CURSOR_ID:
1709	case SVGA_REG_CURSOR_X:
1710	case SVGA_REG_CURSOR_Y:
1711	case SVGA_REG_CURSOR_ON:
1712	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1713	break;
1714
1715	/* Legacy multi-monitor support */
1716	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1717	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1718	break;
1719	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1720	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1721	break;
1722	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1724	break;
1725	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1726	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1727	break;
1728	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1729	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1730	break;
1731	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1732	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1733	break;
1734	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1736	break;
1737	#ifdef VBOX_WITH_VMSVGA3D
1738	/* See "Guest memory regions" below. */
1739	case SVGA_REG_GMR_ID:
1740	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1741	pThis->svga.u32CurrentGMRId = u32;
1742	break;
1743
1744	case SVGA_REG_GMR_DESCRIPTOR:
1745	# ifndef IN_RING3
1746	rc = VINF_IOM_R3_IOPORT_WRITE;
1747	break;
1748	# else /* IN_RING3 */
1749	{
1750	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1751
1752	/* Validate current GMR id. */
1753	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1754	AssertBreak(idGMR < pThis->svga.cGMR);
1755	RT_UNTRUSTED_VALIDATED_FENCE();
1756
1757	/* Free the old GMR if present. */
1758	vmsvgaGMRFree(pThis, idGMR);
1759
1760	/* Just undefine the GMR? */
1761	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1762	if (GCPhys == 0)
1763	{
1764	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1765	break;
1766	}
1767
1768
1769	/* Never cross a page boundary automatically. */
1770	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1771	uint32_t cPagesTotal = 0;
1772	uint32_t iDesc = 0;
1773	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1774	uint32_t cLoops = 0;
1775	RTGCPHYS GCPhysBase = GCPhys;
1776	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1777	{
1778	/* Read descriptor. */
1779	SVGAGuestMemDescriptor desc;
1780	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1781	AssertRCBreak(rc);
1782
1783	if (desc.numPages != 0)
1784	{
1785	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1786	cPagesTotal += desc.numPages;
1787	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1788
1789	if ((iDesc & 15) == 0)
1790	{
1791	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1792	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1793	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1794	}
1795
1796	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1797	paDescs[iDesc++].numPages = desc.numPages;
1798
1799	/* Continue with the next descriptor. */
1800	GCPhys += sizeof(desc);
1801	}
1802	else if (desc.ppn == 0)
1803	break; /* terminator */
1804	else /* Pointer to the next physical page of descriptors. */
1805	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1806
1807	cLoops++;
1808	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1809	}
1810
1811	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1812	if (RT_SUCCESS(rc))
1813	{
1814	/* Commit the GMR. */
1815	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1816	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1817	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1818	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1819	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1820	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1821	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1822	}
1823	else
1824	{
1825	RTMemFree(paDescs);
1826	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1827	}
1828	break;
1829	}
1830	# endif /* IN_RING3 */
1831	#endif // VBOX_WITH_VMSVGA3D
1832
1833	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1834	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1835	if (pThis->svga.fTraces == u32)
1836	break; /* nothing to do */
1837
1838	#ifdef IN_RING3
1839	vmsvgaSetTraces(pThis, !!u32);
1840	#else
1841	rc = VINF_IOM_R3_IOPORT_WRITE;
1842	#endif
1843	break;
1844
1845	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1846	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1847	break;
1848
1849	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1851	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1852	break;
1853
1854	case SVGA_REG_FB_START:
1855	case SVGA_REG_MEM_START:
1856	case SVGA_REG_HOST_BITS_PER_PIXEL:
1857	case SVGA_REG_MAX_WIDTH:
1858	case SVGA_REG_MAX_HEIGHT:
1859	case SVGA_REG_VRAM_SIZE:
1860	case SVGA_REG_FB_SIZE:
1861	case SVGA_REG_CAPABILITIES:
1862	case SVGA_REG_MEM_SIZE:
1863	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1864	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1865	case SVGA_REG_BYTES_PER_LINE:
1866	case SVGA_REG_FB_OFFSET:
1867	case SVGA_REG_RED_MASK:
1868	case SVGA_REG_GREEN_MASK:
1869	case SVGA_REG_BLUE_MASK:
1870	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1871	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1872	case SVGA_REG_GMR_MAX_IDS:
1873	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1874	/* Read only - ignore. */
1875	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1876	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1877	break;
1878
1879	default:
1880	{
1881	uint32_t offReg;
1882	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1883	{
1884	RT_UNTRUSTED_VALIDATED_FENCE();
1885	pThis->svga.au32ScratchRegion[offReg] = u32;
1886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1887	}
1888	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1889	{
1890	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1891	Btw, see rgb_to_pixel32. */
1892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1893	u32 &= 0xff;
1894	RT_UNTRUSTED_VALIDATED_FENCE();
1895	uint32_t uRgb = pThis->last_palette[offReg / 3];
1896	switch (offReg % 3)
1897	{
1898	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1899	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1900	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1901	}
1902	pThis->last_palette[offReg / 3] = uRgb;
1903	}
1904	else
1905	{
1906	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1907	rc = VINF_IOM_R3_IOPORT_WRITE;
1908	#else
1909	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1910	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1911	#endif
1912	}
1913	break;
1914	}
1915	}
1916	return rc;
1917	}
1918
1919	/**
1920	* Port I/O Handler for IN operations.
1921	*
1922	* @returns VINF_SUCCESS or VINF_EM_*.
1923	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1924	*
1925	* @param pDevIns The device instance.
1926	* @param pvUser User argument.
1927	* @param uPort Port number used for the IN operation.
1928	* @param pu32 Where to store the result. This is always a 32-bit
1929	* variable regardless of what @a cb might say.
1930	* @param cb Number of bytes read.
1931	*/
1932	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1933	{
1934	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1935	RT_NOREF_PV(pvUser);
1936
1937	/* Ignore non-dword accesses. */
1938	if (cb != 4)
1939	{
1940	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1941	*pu32 = UINT32_MAX;
1942	return VINF_SUCCESS;
1943	}
1944
1945	switch (uPort - pThis->svga.BasePort)
1946	{
1947	case SVGA_INDEX_PORT:
1948	*pu32 = pThis->svga.u32IndexReg;
1949	break;
1950
1951	case SVGA_VALUE_PORT:
1952	return vmsvgaReadPort(pThis, pu32);
1953
1954	case SVGA_BIOS_PORT:
1955	Log(("Ignoring BIOS port read\n"));
1956	*pu32 = 0;
1957	break;
1958
1959	case SVGA_IRQSTATUS_PORT:
1960	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1961	*pu32 = pThis->svga.u32IrqStatus;
1962	break;
1963
1964	default:
1965	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1966	*pu32 = UINT32_MAX;
1967	break;
1968	}
1969
1970	return VINF_SUCCESS;
1971	}
1972
1973	/**
1974	* Port I/O Handler for OUT operations.
1975	*
1976	* @returns VINF_SUCCESS or VINF_EM_*.
1977	*
1978	* @param pDevIns The device instance.
1979	* @param pvUser User argument.
1980	* @param uPort Port number used for the OUT operation.
1981	* @param u32 The value to output.
1982	* @param cb The value size in bytes.
1983	*/
1984	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1985	{
1986	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1987	RT_NOREF_PV(pvUser);
1988
1989	/* Ignore non-dword accesses. */
1990	if (cb != 4)
1991	{
1992	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1993	return VINF_SUCCESS;
1994	}
1995
1996	switch (uPort - pThis->svga.BasePort)
1997	{
1998	case SVGA_INDEX_PORT:
1999	pThis->svga.u32IndexReg = u32;
2000	break;
2001
2002	case SVGA_VALUE_PORT:
2003	return vmsvgaWritePort(pThis, u32);
2004
2005	case SVGA_BIOS_PORT:
2006	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2007	break;
2008
2009	case SVGA_IRQSTATUS_PORT:
2010	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2011	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2012	/* Clear the irq in case all events have been cleared. */
2013	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2014	{
2015	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2016	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2017	}
2018	break;
2019
2020	default:
2021	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2022	uPort - pThis->svga.BasePort, uPort, u32, cb));
2023	break;
2024	}
2025	return VINF_SUCCESS;
2026	}
2027
2028	#ifdef IN_RING3
2029
2030	# ifdef DEBUG_FIFO_ACCESS
2031	/**
2032	* Handle FIFO memory access.
2033	* @returns VBox status code.
2034	* @param pVM VM handle.
2035	* @param pThis VGA device instance data.
2036	* @param GCPhys The access physical address.
2037	* @param fWriteAccess Read or write access
2038	*/
2039	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2040	{
2041	RT_NOREF(pVM);
2042	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2043	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2044
2045	switch (GCPhysOffset >> 2)
2046	{
2047	case SVGA_FIFO_MIN:
2048	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2049	break;
2050	case SVGA_FIFO_MAX:
2051	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2052	break;
2053	case SVGA_FIFO_NEXT_CMD:
2054	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2055	break;
2056	case SVGA_FIFO_STOP:
2057	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2058	break;
2059	case SVGA_FIFO_CAPABILITIES:
2060	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2061	break;
2062	case SVGA_FIFO_FLAGS:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_FENCE:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_3D_HWVERSION:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_PITCHLOCK:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_CURSOR_ON:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_CURSOR_X:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_CURSOR_Y:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_CURSOR_COUNT:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_RESERVED:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_CURSOR_SCREEN_ID:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_DEAD:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_3D_HWVERSION_REVISED:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS_LAST:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_GUEST_3D_HWVERSION:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_FENCE_GOAL:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_BUSY:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	default:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	}
2366
2367	return VINF_EM_RAW_EMULATE_INSTR;
2368	}
2369	# endif /* DEBUG_FIFO_ACCESS */
2370
2371	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2372	/**
2373	* HC access handler for the FIFO.
2374	*
2375	* @returns VINF_SUCCESS if the handler have carried out the operation.
2376	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2377	* @param pVM VM Handle.
2378	* @param pVCpu The cross context CPU structure for the calling EMT.
2379	* @param GCPhys The physical address the guest is writing to.
2380	* @param pvPhys The HC mapping of that address.
2381	* @param pvBuf What the guest is reading/writing.
2382	* @param cbBuf How much it's reading/writing.
2383	* @param enmAccessType The access type.
2384	* @param enmOrigin Who is making the access.
2385	* @param pvUser User argument.
2386	*/
2387	static DECLCALLBACK(VBOXSTRICTRC)
2388	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2389	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2390	{
2391	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2392	PVGASTATE pThis = (PVGASTATE)pvUser;
2393	AssertPtr(pThis);
2394
2395	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2396	/*
2397	* Wake up the FIFO thread as it might have work to do now.
2398	*/
2399	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2400	AssertLogRelRC(rc);
2401	# endif
2402
2403	# ifdef DEBUG_FIFO_ACCESS
2404	/*
2405	* When in debug-fifo-access mode, we do not disable the access handler,
2406	* but leave it on as we wish to catch all access.
2407	*/
2408	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2409	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2410	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2411	/*
2412	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2413	*/
2414	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2415	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2416	# endif
2417	if (RT_SUCCESS(rc))
2418	return VINF_PGM_HANDLER_DO_DEFAULT;
2419	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2420	return rc;
2421	}
2422	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2423
2424	#endif /* IN_RING3 */
2425
2426	#ifdef DEBUG_GMR_ACCESS
2427	# ifdef IN_RING3
2428
2429	/**
2430	* HC access handler for the FIFO.
2431	*
2432	* @returns VINF_SUCCESS if the handler have carried out the operation.
2433	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2434	* @param pVM VM Handle.
2435	* @param pVCpu The cross context CPU structure for the calling EMT.
2436	* @param GCPhys The physical address the guest is writing to.
2437	* @param pvPhys The HC mapping of that address.
2438	* @param pvBuf What the guest is reading/writing.
2439	* @param cbBuf How much it's reading/writing.
2440	* @param enmAccessType The access type.
2441	* @param enmOrigin Who is making the access.
2442	* @param pvUser User argument.
2443	*/
2444	static DECLCALLBACK(VBOXSTRICTRC)
2445	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2446	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2447	{
2448	PVGASTATE pThis = (PVGASTATE)pvUser;
2449	Assert(pThis);
2450	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2451	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2452
2453	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2454
2455	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2456	{
2457	PGMR pGMR = &pSVGAState->paGMR[i];
2458
2459	if (pGMR->numDescriptors)
2460	{
2461	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2462	{
2463	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2464	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2465	{
2466	/*
2467	* Turn off the write handler for this particular page and make it R/W.
2468	* Then return telling the caller to restart the guest instruction.
2469	*/
2470	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2471	AssertRC(rc);
2472	goto end;
2473	}
2474	}
2475	}
2476	}
2477	end:
2478	return VINF_PGM_HANDLER_DO_DEFAULT;
2479	}
2480
2481	/* Callback handler for VMR3ReqCallWaitU */
2482	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2483	{
2484	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2485	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2486	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2487	int rc;
2488
2489	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2490	{
2491	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2492	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2493	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2494	AssertRC(rc);
2495	}
2496	return VINF_SUCCESS;
2497	}
2498
2499	/* Callback handler for VMR3ReqCallWaitU */
2500	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2501	{
2502	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2503	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2504	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2505
2506	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2507	{
2508	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2509	AssertRC(rc);
2510	}
2511	return VINF_SUCCESS;
2512	}
2513
2514	/* Callback handler for VMR3ReqCallWaitU */
2515	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2516	{
2517	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2518
2519	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2520	{
2521	PGMR pGMR = &pSVGAState->paGMR[i];
2522
2523	if (pGMR->numDescriptors)
2524	{
2525	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2526	{
2527	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2528	AssertRC(rc);
2529	}
2530	}
2531	}
2532	return VINF_SUCCESS;
2533	}
2534
2535	# endif /* IN_RING3 */
2536	#endif /* DEBUG_GMR_ACCESS */
2537
2538	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2539
2540	#ifdef IN_RING3
2541
2542
2543	/**
2544	* Common worker for changing the pointer shape.
2545	*
2546	* @param pThis The VGA instance data.
2547	* @param pSVGAState The VMSVGA ring-3 instance data.
2548	* @param fAlpha Whether there is alpha or not.
2549	* @param xHot Hotspot x coordinate.
2550	* @param yHot Hotspot y coordinate.
2551	* @param cx Width.
2552	* @param cy Height.
2553	* @param pbData Heap copy of the cursor data. Consumed.
2554	* @param cbData The size of the data.
2555	*/
2556	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2557	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2558	{
2559	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2560	#ifdef LOG_ENABLED
2561	if (LogIs2Enabled())
2562	{
2563	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2564	if (!fAlpha)
2565	{
2566	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2567	for (uint32_t y = 0; y < cy; y++)
2568	{
2569	Log2(("%3u:", y));
2570	uint8_t const pbLine = &pbData[y cbAndLine];
2571	for (uint32_t x = 0; x < cx; x += 8)
2572	{
2573	uint8_t b = pbLine[x / 8];
2574	char szByte[12];
2575	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2576	szByte[1] = b & 0x40 ? '*' : ' ';
2577	szByte[2] = b & 0x20 ? '*' : ' ';
2578	szByte[3] = b & 0x10 ? '*' : ' ';
2579	szByte[4] = b & 0x08 ? '*' : ' ';
2580	szByte[5] = b & 0x04 ? '*' : ' ';
2581	szByte[6] = b & 0x02 ? '*' : ' ';
2582	szByte[7] = b & 0x01 ? '*' : ' ';
2583	szByte[8] = '\0';
2584	Log2(("%s", szByte));
2585	}
2586	Log2(("\n"));
2587	}
2588	}
2589
2590	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2591	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2592	for (uint32_t y = 0; y < cy; y++)
2593	{
2594	Log2(("%3u:", y));
2595	uint32_t const pu32Line = &pu32Xor[y cx];
2596	for (uint32_t x = 0; x < cx; x++)
2597	Log2((" %08x", pu32Line[x]));
2598	Log2(("\n"));
2599	}
2600	}
2601	#endif
2602
2603	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2604	AssertRC(rc);
2605
2606	if (pSVGAState->Cursor.fActive)
2607	RTMemFree(pSVGAState->Cursor.pData);
2608
2609	pSVGAState->Cursor.fActive = true;
2610	pSVGAState->Cursor.xHotspot = xHot;
2611	pSVGAState->Cursor.yHotspot = yHot;
2612	pSVGAState->Cursor.width = cx;
2613	pSVGAState->Cursor.height = cy;
2614	pSVGAState->Cursor.cbData = cbData;
2615	pSVGAState->Cursor.pData = pbData;
2616	}
2617
2618
2619	/**
2620	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2621	*
2622	* @param pThis The VGA instance data.
2623	* @param pSVGAState The VMSVGA ring-3 instance data.
2624	* @param pCursor The cursor.
2625	* @param pbSrcAndMask The AND mask.
2626	* @param cbSrcAndLine The scanline length of the AND mask.
2627	* @param pbSrcXorMask The XOR mask.
2628	* @param cbSrcXorLine The scanline length of the XOR mask.
2629	*/
2630	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2631	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2632	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2633	{
2634	uint32_t const cx = pCursor->width;
2635	uint32_t const cy = pCursor->height;
2636
2637	/*
2638	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2639	* The AND data uses 8-bit aligned scanlines.
2640	* The XOR data must be starting on a 32-bit boundrary.
2641	*/
2642	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2643	uint32_t cbDstAndMask = cbDstAndLine * cy;
2644	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2645	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2646
2647	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2648	AssertReturnVoid(pbCopy);
2649
2650	/* Convert the AND mask. */
2651	uint8_t *pbDst = pbCopy;
2652	uint8_t const *pbSrc = pbSrcAndMask;
2653	switch (pCursor->andMaskDepth)
2654	{
2655	case 1:
2656	if (cbSrcAndLine == cbDstAndLine)
2657	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2658	else
2659	{
2660	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2661	for (uint32_t y = 0; y < cy; y++)
2662	{
2663	memcpy(pbDst, pbSrc, cbDstAndLine);
2664	pbDst += cbDstAndLine;
2665	pbSrc += cbSrcAndLine;
2666	}
2667	}
2668	break;
2669	/* Should take the XOR mask into account for the multi-bit AND mask. */
2670	case 8:
2671	for (uint32_t y = 0; y < cy; y++)
2672	{
2673	for (uint32_t x = 0; x < cx; )
2674	{
2675	uint8_t bDst = 0;
2676	uint8_t fBit = 1;
2677	do
2678	{
2679	uintptr_t const idxPal = pbSrc[x] * 3;
2680	if ((( pThis->last_palette[idxPal]
2681	\| (pThis->last_palette[idxPal] >> 8)
2682	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2683	bDst \|= fBit;
2684	fBit <<= 1;
2685	x++;
2686	} while (x < cx && (x & 7));
2687	pbDst[(x - 1) / 8] = bDst;
2688	}
2689	pbDst += cbDstAndLine;
2690	pbSrc += cbSrcAndLine;
2691	}
2692	break;
2693	case 15:
2694	for (uint32_t y = 0; y < cy; y++)
2695	{
2696	for (uint32_t x = 0; x < cx; )
2697	{
2698	uint8_t bDst = 0;
2699	uint8_t fBit = 1;
2700	do
2701	{
2702	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2703	bDst \|= fBit;
2704	fBit <<= 1;
2705	x++;
2706	} while (x < cx && (x & 7));
2707	pbDst[(x - 1) / 8] = bDst;
2708	}
2709	pbDst += cbDstAndLine;
2710	pbSrc += cbSrcAndLine;
2711	}
2712	break;
2713	case 16:
2714	for (uint32_t y = 0; y < cy; y++)
2715	{
2716	for (uint32_t x = 0; x < cx; )
2717	{
2718	uint8_t bDst = 0;
2719	uint8_t fBit = 1;
2720	do
2721	{
2722	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2723	bDst \|= fBit;
2724	fBit <<= 1;
2725	x++;
2726	} while (x < cx && (x & 7));
2727	pbDst[(x - 1) / 8] = bDst;
2728	}
2729	pbDst += cbDstAndLine;
2730	pbSrc += cbSrcAndLine;
2731	}
2732	break;
2733	case 24:
2734	for (uint32_t y = 0; y < cy; y++)
2735	{
2736	for (uint32_t x = 0; x < cx; )
2737	{
2738	uint8_t bDst = 0;
2739	uint8_t fBit = 1;
2740	do
2741	{
2742	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2743	bDst \|= fBit;
2744	fBit <<= 1;
2745	x++;
2746	} while (x < cx && (x & 7));
2747	pbDst[(x - 1) / 8] = bDst;
2748	}
2749	pbDst += cbDstAndLine;
2750	pbSrc += cbSrcAndLine;
2751	}
2752	break;
2753	case 32:
2754	for (uint32_t y = 0; y < cy; y++)
2755	{
2756	for (uint32_t x = 0; x < cx; )
2757	{
2758	uint8_t bDst = 0;
2759	uint8_t fBit = 1;
2760	do
2761	{
2762	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2763	bDst \|= fBit;
2764	fBit <<= 1;
2765	x++;
2766	} while (x < cx && (x & 7));
2767	pbDst[(x - 1) / 8] = bDst;
2768	}
2769	pbDst += cbDstAndLine;
2770	pbSrc += cbSrcAndLine;
2771	}
2772	break;
2773	default:
2774	RTMemFree(pbCopy);
2775	AssertFailedReturnVoid();
2776	}
2777
2778	/* Convert the XOR mask. */
2779	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2780	pbSrc = pbSrcXorMask;
2781	switch (pCursor->xorMaskDepth)
2782	{
2783	case 1:
2784	for (uint32_t y = 0; y < cy; y++)
2785	{
2786	for (uint32_t x = 0; x < cx; )
2787	{
2788	/* most significant bit is the left most one. */
2789	uint8_t bSrc = pbSrc[x / 8];
2790	do
2791	{
2792	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2793	bSrc <<= 1;
2794	x++;
2795	} while ((x & 7) && x < cx);
2796	}
2797	pbSrc += cbSrcXorLine;
2798	}
2799	break;
2800	case 8:
2801	for (uint32_t y = 0; y < cy; y++)
2802	{
2803	for (uint32_t x = 0; x < cx; x++)
2804	{
2805	uint32_t u = pThis->last_palette[pbSrc[x]];
2806	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2807	}
2808	pbSrc += cbSrcXorLine;
2809	}
2810	break;
2811	case 15: /* Src: RGB-5-5-5 */
2812	for (uint32_t y = 0; y < cy; y++)
2813	{
2814	for (uint32_t x = 0; x < cx; x++)
2815	{
2816	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2817	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2818	((uValue >> 5) & 0x1f) << 3,
2819	((uValue >> 10) & 0x1f) << 3, 0);
2820	}
2821	pbSrc += cbSrcXorLine;
2822	}
2823	break;
2824	case 16: /* Src: RGB-5-6-5 */
2825	for (uint32_t y = 0; y < cy; y++)
2826	{
2827	for (uint32_t x = 0; x < cx; x++)
2828	{
2829	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2830	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2831	((uValue >> 5) & 0x3f) << 2,
2832	((uValue >> 11) & 0x1f) << 3, 0);
2833	}
2834	pbSrc += cbSrcXorLine;
2835	}
2836	break;
2837	case 24:
2838	for (uint32_t y = 0; y < cy; y++)
2839	{
2840	for (uint32_t x = 0; x < cx; x++)
2841	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2842	pbSrc += cbSrcXorLine;
2843	}
2844	break;
2845	case 32:
2846	for (uint32_t y = 0; y < cy; y++)
2847	{
2848	for (uint32_t x = 0; x < cx; x++)
2849	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2850	pbSrc += cbSrcXorLine;
2851	}
2852	break;
2853	default:
2854	RTMemFree(pbCopy);
2855	AssertFailedReturnVoid();
2856	}
2857
2858	/*
2859	* Pass it to the frontend/whatever.
2860	*/
2861	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2862	}
2863
2864
2865	/**
2866	* Worker for vmsvgaR3FifoThread that handles an external command.
2867	*
2868	* @param pThis VGA device instance data.
2869	*/
2870	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2871	{
2872	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2873	switch (pThis->svga.u8FIFOExtCommand)
2874	{
2875	case VMSVGA_FIFO_EXTCMD_RESET:
2876	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2877	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2878	# ifdef VBOX_WITH_VMSVGA3D
2879	if (pThis->svga.f3DEnabled)
2880	{
2881	/* The 3d subsystem must be reset from the fifo thread. */
2882	vmsvga3dReset(pThis);
2883	}
2884	# endif
2885	break;
2886
2887	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2888	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2889	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2890	# ifdef VBOX_WITH_VMSVGA3D
2891	if (pThis->svga.f3DEnabled)
2892	{
2893	/* The 3d subsystem must be shut down from the fifo thread. */
2894	vmsvga3dTerminate(pThis);
2895	}
2896	# endif
2897	break;
2898
2899	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2900	{
2901	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2902	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2903	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2904	vmsvgaSaveExecFifo(pThis, pSSM);
2905	# ifdef VBOX_WITH_VMSVGA3D
2906	if (pThis->svga.f3DEnabled)
2907	vmsvga3dSaveExec(pThis, pSSM);
2908	# endif
2909	break;
2910	}
2911
2912	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2913	{
2914	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2915	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2916	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2917	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2918	# ifdef VBOX_WITH_VMSVGA3D
2919	if (pThis->svga.f3DEnabled)
2920	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2921	# endif
2922	break;
2923	}
2924
2925	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2926	{
2927	# ifdef VBOX_WITH_VMSVGA3D
2928	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2929	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2930	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2931	# endif
2932	break;
2933	}
2934
2935
2936	default:
2937	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2938	break;
2939	}
2940
2941	/*
2942	* Signal the end of the external command.
2943	*/
2944	pThis->svga.pvFIFOExtCmdParam = NULL;
2945	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2946	ASMMemoryFence(); /* paranoia^2 */
2947	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2948	AssertLogRelRC(rc);
2949	}
2950
2951	/**
2952	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2953	* doing a job on the FIFO thread (even when it's officially suspended).
2954	*
2955	* @returns VBox status code (fully asserted).
2956	* @param pThis VGA device instance data.
2957	* @param uExtCmd The command to execute on the FIFO thread.
2958	* @param pvParam Pointer to command parameters.
2959	* @param cMsWait The time to wait for the command, given in
2960	* milliseconds.
2961	*/
2962	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2963	{
2964	Assert(cMsWait >= RT_MS_1SEC * 5);
2965	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2966	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2967
2968	int rc;
2969	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2970	PDMTHREADSTATE enmState = pThread->enmState;
2971	if (enmState == PDMTHREADSTATE_SUSPENDED)
2972	{
2973	/*
2974	* The thread is suspended, we have to temporarily wake it up so it can
2975	* perform the task.
2976	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2977	*/
2978	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2979	/* Post the request. */
2980	pThis->svga.fFifoExtCommandWakeup = true;
2981	pThis->svga.pvFIFOExtCmdParam = pvParam;
2982	pThis->svga.u8FIFOExtCommand = uExtCmd;
2983	ASMMemoryFence(); /* paranoia^3 */
2984
2985	/* Resume the thread. */
2986	rc = PDMR3ThreadResume(pThread);
2987	AssertLogRelRC(rc);
2988	if (RT_SUCCESS(rc))
2989	{
2990	/* Wait. Take care in case the semaphore was already posted (same as below). */
2991	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2992	if ( rc == VINF_SUCCESS
2993	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2994	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2995	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2996	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2997
2998	/* suspend the thread */
2999	pThis->svga.fFifoExtCommandWakeup = false;
3000	int rc2 = PDMR3ThreadSuspend(pThread);
3001	AssertLogRelRC(rc2);
3002	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3003	rc = rc2;
3004	}
3005	pThis->svga.fFifoExtCommandWakeup = false;
3006	pThis->svga.pvFIFOExtCmdParam = NULL;
3007	}
3008	else if (enmState == PDMTHREADSTATE_RUNNING)
3009	{
3010	/*
3011	* The thread is running, should only happen during reset and vmsvga3dsfc.
3012	* We ASSUME not racing code here, both wrt thread state and ext commands.
3013	*/
3014	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3015	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3016
3017	/* Post the request. */
3018	pThis->svga.pvFIFOExtCmdParam = pvParam;
3019	pThis->svga.u8FIFOExtCommand = uExtCmd;
3020	ASMMemoryFence(); /* paranoia^2 */
3021	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3022	AssertLogRelRC(rc);
3023
3024	/* Wait. Take care in case the semaphore was already posted (same as above). */
3025	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3026	if ( rc == VINF_SUCCESS
3027	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3028	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3029	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3030	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3031
3032	pThis->svga.pvFIFOExtCmdParam = NULL;
3033	}
3034	else
3035	{
3036	/*
3037	* Something is wrong with the thread!
3038	*/
3039	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3040	rc = VERR_INVALID_STATE;
3041	}
3042	return rc;
3043	}
3044
3045
3046	/**
3047	* Marks the FIFO non-busy, notifying any waiting EMTs.
3048	*
3049	* @param pThis The VGA state.
3050	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3051	* @param offFifoMin The start byte offset of the command FIFO.
3052	*/
3053	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3054	{
3055	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3056	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3057	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3058
3059	/* Wake up any waiting EMTs. */
3060	if (pSVGAState->cBusyDelayedEmts > 0)
3061	{
3062	#ifdef VMSVGA_USE_EMT_HALT_CODE
3063	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3064	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3065	if (idCpu != NIL_VMCPUID)
3066	{
3067	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3068	while (idCpu-- > 0)
3069	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3070	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3071	}
3072	#else
3073	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3074	AssertRC(rc2);
3075	#endif
3076	}
3077	}
3078
3079	/**
3080	* Reads (more) payload into the command buffer.
3081	*
3082	* @returns pbBounceBuf on success
3083	* @retval (void *)1 if the thread was requested to stop.
3084	* @retval NULL on FIFO error.
3085	*
3086	* @param cbPayloadReq The number of bytes of payload requested.
3087	* @param pFIFO The FIFO.
3088	* @param offCurrentCmd The FIFO byte offset of the current command.
3089	* @param offFifoMin The start byte offset of the command FIFO.
3090	* @param offFifoMax The end byte offset of the command FIFO.
3091	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3092	* always sufficient size.
3093	* @param pcbAlreadyRead How much payload we've already read into the bounce
3094	* buffer. (We will NEVER re-read anything.)
3095	* @param pThread The calling PDM thread handle.
3096	* @param pThis The VGA state.
3097	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3098	* statistics collection.
3099	*/
3100	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3101	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3102	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3103	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3104	{
3105	Assert(pbBounceBuf);
3106	Assert(pcbAlreadyRead);
3107	Assert(offFifoMin < offFifoMax);
3108	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3109	Assert(offFifoMax <= pThis->svga.cbFIFO);
3110
3111	/*
3112	* Check if the requested payload size has already been satisfied .
3113	* .
3114	* When called to read more, the caller is responsible for making sure the .
3115	* new command size (cbRequsted) never is smaller than what has already .
3116	* been read.
3117	*/
3118	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3119	if (cbPayloadReq <= cbAlreadyRead)
3120	{
3121	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3122	return pbBounceBuf;
3123	}
3124
3125	/*
3126	* Commands bigger than the fifo buffer are invalid.
3127	*/
3128	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3129	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3130	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3131	NULL);
3132
3133	/*
3134	* Move offCurrentCmd past the command dword.
3135	*/
3136	offCurrentCmd += sizeof(uint32_t);
3137	if (offCurrentCmd >= offFifoMax)
3138	offCurrentCmd = offFifoMin;
3139
3140	/*
3141	* Do we have sufficient payload data available already?
3142	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3143	*/
3144	uint32_t cbAfter, cbBefore;
3145	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3146	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3147	if (offNextCmd >= offCurrentCmd)
3148	{
3149	if (RT_LIKELY(offNextCmd < offFifoMax))
3150	cbAfter = offNextCmd - offCurrentCmd;
3151	else
3152	{
3153	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3154	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3155	offNextCmd, offFifoMin, offFifoMax));
3156	cbAfter = offFifoMax - offCurrentCmd;
3157	}
3158	cbBefore = 0;
3159	}
3160	else
3161	{
3162	cbAfter = offFifoMax - offCurrentCmd;
3163	if (offNextCmd >= offFifoMin)
3164	cbBefore = offNextCmd - offFifoMin;
3165	else
3166	{
3167	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3168	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3169	offNextCmd, offFifoMin, offFifoMax));
3170	cbBefore = 0;
3171	}
3172	}
3173	if (cbAfter + cbBefore < cbPayloadReq)
3174	{
3175	/*
3176	* Insufficient, must wait for it to arrive.
3177	*/
3178	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3179	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3180	for (uint32_t i = 0;; i++)
3181	{
3182	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3183	{
3184	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3185	return (void *)(uintptr_t)1;
3186	}
3187	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3188	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3189
3190	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3191
3192	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3193	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3194	if (offNextCmd >= offCurrentCmd)
3195	{
3196	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3197	cbBefore = 0;
3198	}
3199	else
3200	{
3201	cbAfter = offFifoMax - offCurrentCmd;
3202	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3203	}
3204
3205	if (cbAfter + cbBefore >= cbPayloadReq)
3206	break;
3207	}
3208	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3209	}
3210
3211	/*
3212	* Copy out the memory and update what pcbAlreadyRead points to.
3213	*/
3214	if (cbAfter >= cbPayloadReq)
3215	memcpy(pbBounceBuf + cbAlreadyRead,
3216	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3217	cbPayloadReq - cbAlreadyRead);
3218	else
3219	{
3220	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3221	if (cbAlreadyRead < cbAfter)
3222	{
3223	memcpy(pbBounceBuf + cbAlreadyRead,
3224	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3225	cbAfter - cbAlreadyRead);
3226	cbAlreadyRead = cbAfter;
3227	}
3228	memcpy(pbBounceBuf + cbAlreadyRead,
3229	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3230	cbPayloadReq - cbAlreadyRead);
3231	}
3232	*pcbAlreadyRead = cbPayloadReq;
3233	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3234	return pbBounceBuf;
3235	}
3236
3237
3238	/**
3239	* Sends cursor position and visibility information from the FIFO to the front-end.
3240	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3241	*/
3242	static uint32_t
3243	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3244	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3245	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3246	{
3247	/*
3248	* Check if the cursor update counter has changed and try get a stable
3249	* set of values if it has. This is race-prone, especially consindering
3250	* the screen ID, but little we can do about that.
3251	*/
3252	uint32_t x, y, fVisible, idScreen;
3253	for (uint32_t i = 0; ; i++)
3254	{
3255	x = pFIFO[SVGA_FIFO_CURSOR_X];
3256	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3257	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3258	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3259	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3260	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3261	\|\| i > 3)
3262	break;
3263	if (i == 0)
3264	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3265	ASMNopPause();
3266	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3267	}
3268
3269	/*
3270	* Check if anything has changed, as calling into pDrv is not light-weight.
3271	*/
3272	if ( *pxLast == x
3273	&& *pyLast == y
3274	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3275	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3276	else
3277	{
3278	/*
3279	* Detected changes.
3280	*
3281	* We handle global, not per-screen visibility information by sending
3282	* pfnVBVAMousePointerShape without shape data.
3283	*/
3284	*pxLast = x;
3285	*pyLast = y;
3286	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3287	if (idScreen != SVGA_ID_INVALID)
3288	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3289	else if (*pfLastVisible != fVisible)
3290	{
3291	*pfLastVisible = fVisible;
3292	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3293	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3294	}
3295	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3296	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3297	}
3298
3299	/*
3300	* Update done. Signal this to the guest.
3301	*/
3302	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3303
3304	return uCursorUpdateCount;
3305	}
3306
3307
3308	/**
3309	* Checks if there is work to be done, either cursor updating or FIFO commands.
3310	*
3311	* @returns true if pending work, false if not.
3312	* @param pFIFO The FIFO to examine.
3313	* @param uLastCursorCount The last cursor update counter value.
3314	*/
3315	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3316	{
3317	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3318	return true;
3319
3320	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3321	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3322	return true;
3323
3324	return false;
3325	}
3326
3327
3328	/**
3329	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3330	*
3331	* @param pThis The VGA state.
3332	*/
3333	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3334	{
3335	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3336	to recheck it before doing the signalling. */
3337	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3338	AssertReturnVoid(pThis->svga.pFIFOR3);
3339	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3340	&& pThis->svga.fFIFOThreadSleeping)
3341	{
3342	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3343	AssertRC(rc);
3344	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3345	}
3346	}
3347
3348
3349	/* The async FIFO handling thread. */
3350	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3351	{
3352	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3353	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3354	int rc;
3355
3356	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3357	return VINF_SUCCESS;
3358
3359	/*
3360	* Special mode where we only execute an external command and the go back
3361	* to being suspended. Currently, all ext cmds ends up here, with the reset
3362	* one also being eligble for runtime execution further down as well.
3363	*/
3364	if (pThis->svga.fFifoExtCommandWakeup)
3365	{
3366	vmsvgaR3FifoHandleExtCmd(pThis);
3367	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3368	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3369	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3370	else
3371	vmsvgaR3FifoHandleExtCmd(pThis);
3372	return VINF_SUCCESS;
3373	}
3374
3375
3376	/*
3377	* Signal the semaphore to make sure we don't wait for 250ms after a
3378	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3379	*/
3380	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3381
3382	/*
3383	* Allocate a bounce buffer for command we get from the FIFO.
3384	* (All code must return via the end of the function to free this buffer.)
3385	*/
3386	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3387	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3388
3389	/*
3390	* Polling/sleep interval config.
3391	*
3392	* We wait for an a short interval if the guest has recently given us work
3393	* to do, but the interval increases the longer we're kept idle. Once we've
3394	* reached the refresh timer interval, we'll switch to extended waits,
3395	* depending on it or the guest to kick us into action when needed.
3396	*
3397	* Should the refresh time go fishing, we'll just continue increasing the
3398	* sleep length till we reaches the 250 ms max after about 16 seconds.
3399	*/
3400	RTMSINTERVAL const cMsMinSleep = 16;
3401	RTMSINTERVAL const cMsIncSleep = 2;
3402	RTMSINTERVAL const cMsMaxSleep = 250;
3403	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3404	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3405
3406	/*
3407	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3408	*
3409	* Initialize with values that will detect an update from the guest.
3410	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3411	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3412	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3413	*/
3414	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3415	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3416	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3417	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3418	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3419
3420	/*
3421	* The FIFO loop.
3422	*/
3423	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3424	bool fBadOrDisabledFifo = false;
3425	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3426	{
3427	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3428	/*
3429	* Should service the run loop every so often.
3430	*/
3431	if (pThis->svga.f3DEnabled)
3432	vmsvga3dCocoaServiceRunLoop();
3433	# endif
3434
3435	/*
3436	* Unless there's already work pending, go to sleep for a short while.
3437	* (See polling/sleep interval config above.)
3438	*/
3439	if ( fBadOrDisabledFifo
3440	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3441	{
3442	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3443	Assert(pThis->cMilliesRefreshInterval > 0);
3444	if (cMsSleep < pThis->cMilliesRefreshInterval)
3445	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3446	else
3447	{
3448	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3449	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3450	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3451	# endif
3452	if ( !fBadOrDisabledFifo
3453	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3454	rc = VINF_SUCCESS;
3455	else
3456	{
3457	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3458	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3459	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3460	}
3461	}
3462	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3463	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3464	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3465	{
3466	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3467	break;
3468	}
3469	}
3470	else
3471	rc = VINF_SUCCESS;
3472	fBadOrDisabledFifo = false;
3473	if (rc == VERR_TIMEOUT)
3474	{
3475	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3476	{
3477	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3478	continue;
3479	}
3480	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3481
3482	Log(("vmsvgaFIFOLoop: timeout\n"));
3483	}
3484	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3485	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3486	cMsSleep = cMsMinSleep;
3487
3488	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3489	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3490	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3491
3492	/*
3493	* Handle external commands (currently only reset).
3494	*/
3495	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3496	{
3497	vmsvgaR3FifoHandleExtCmd(pThis);
3498	continue;
3499	}
3500
3501	/*
3502	* The device must be enabled and configured.
3503	*/
3504	if ( !pThis->svga.fEnabled
3505	\|\| !pThis->svga.fConfigured)
3506	{
3507	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3508	fBadOrDisabledFifo = true;
3509	cMsSleep = cMsMaxSleep; /* cheat */
3510	continue;
3511	}
3512
3513	/*
3514	* Get and check the min/max values. We ASSUME that they will remain
3515	* unchanged while we process requests. A further ASSUMPTION is that
3516	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3517	* we don't read it back while in the loop.
3518	*/
3519	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3520	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3521	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3522	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3523	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3524	\|\| offFifoMax <= offFifoMin
3525	\|\| offFifoMax > pThis->svga.cbFIFO
3526	\|\| (offFifoMax & 3) != 0
3527	\|\| (offFifoMin & 3) != 0
3528	\|\| offCurrentCmd < offFifoMin
3529	\|\| offCurrentCmd > offFifoMax))
3530	{
3531	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3532	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3533	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3534	fBadOrDisabledFifo = true;
3535	continue;
3536	}
3537	RT_UNTRUSTED_VALIDATED_FENCE();
3538	if (RT_UNLIKELY(offCurrentCmd & 3))
3539	{
3540	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3541	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3542	offCurrentCmd = ~UINT32_C(3);
3543	}
3544
3545	/*
3546	* Update the cursor position before we start on the FIFO commands.
3547	*/
3548	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3549	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3550	{
3551	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3552	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3553	{ /* halfways likely */ }
3554	else
3555	{
3556	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3557	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3558	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3559	}
3560	}
3561
3562	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3563	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3564	*
3565	* Will break out of the switch on failure.
3566	* Will restart and quit the loop if the thread was requested to stop.
3567	*
3568	* @param a_PtrVar Request variable pointer.
3569	* @param a_Type Request typedef (not pointer) for casting.
3570	* @param a_cbPayloadReq How much payload to fetch.
3571	* @remarks Accesses a bunch of variables in the current scope!
3572	*/
3573	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3574	if (1) { \
3575	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3576	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3577	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3578	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3579	} else do {} while (0)
3580	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3581	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3582	* buffer after figuring out the actual command size.
3583	*
3584	* Will break out of the switch on failure.
3585	*
3586	* @param a_PtrVar Request variable pointer.
3587	* @param a_Type Request typedef (not pointer) for casting.
3588	* @param a_cbPayloadReq How much payload to fetch.
3589	* @remarks Accesses a bunch of variables in the current scope!
3590	*/
3591	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3592	if (1) { \
3593	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3594	} else do {} while (0)
3595
3596	/*
3597	* Mark the FIFO as busy.
3598	*/
3599	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3600	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3601	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3602
3603	/*
3604	* Execute all queued FIFO commands.
3605	* Quit if pending external command or changes in the thread state.
3606	*/
3607	bool fDone = false;
3608	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3609	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3610	{
3611	uint32_t cbPayload = 0;
3612	uint32_t u32IrqStatus = 0;
3613
3614	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3615
3616	/* First check any pending actions. */
3617	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3618	{
3619	vmsvgaChangeMode(pThis);
3620	# ifdef VBOX_WITH_VMSVGA3D
3621	if (pThis->svga.p3dState != NULL)
3622	vmsvga3dChangeMode(pThis);
3623	# endif
3624	}
3625
3626	/* Check for pending external commands (reset). */
3627	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3628	break;
3629
3630	/*
3631	* Process the command.
3632	*/
3633	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3634	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3635	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3636	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3637	switch (enmCmdId)
3638	{
3639	case SVGA_CMD_INVALID_CMD:
3640	/* Nothing to do. */
3641	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3642	break;
3643
3644	case SVGA_CMD_FENCE:
3645	{
3646	SVGAFifoCmdFence *pCmdFence;
3647	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3648	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3649	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3650	{
3651	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3652	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3653
3654	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3655	{
3656	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3657	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3658	}
3659	else
3660	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3661	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3662	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3663	{
3664	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3665	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3666	}
3667	}
3668	else
3669	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3670	break;
3671	}
3672	case SVGA_CMD_UPDATE:
3673	case SVGA_CMD_UPDATE_VERBOSE:
3674	{
3675	SVGAFifoCmdUpdate *pUpdate;
3676	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3677	if (enmCmdId == SVGA_CMD_UPDATE)
3678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3679	else
3680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3681	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3682	/** @todo Multiple screens? */
3683	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3684	AssertBreak(pScreen);
3685	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3686	break;
3687	}
3688
3689	case SVGA_CMD_DEFINE_CURSOR:
3690	{
3691	/* Followed by bitmap data. */
3692	SVGAFifoCmdDefineCursor *pCursor;
3693	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3694	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3695
3696	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3697	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3698	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3699	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3700	AssertBreak(pCursor->andMaskDepth <= 32);
3701	AssertBreak(pCursor->xorMaskDepth <= 32);
3702	RT_UNTRUSTED_VALIDATED_FENCE();
3703
3704	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3705	uint32_t cbAndMask = cbAndLine * pCursor->height;
3706	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3707	uint32_t cbXorMask = cbXorLine * pCursor->height;
3708	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3709
3710	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3711	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3712	break;
3713	}
3714
3715	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3716	{
3717	/* Followed by bitmap data. */
3718	uint32_t cbCursorShape, cbAndMask;
3719	uint8_t *pCursorCopy;
3720	uint32_t cbCmd;
3721
3722	SVGAFifoCmdDefineAlphaCursor *pCursor;
3723	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3724	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3725
3726	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3727
3728	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3729	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3730	RT_UNTRUSTED_VALIDATED_FENCE();
3731
3732	/* Refetch the bitmap data as well. */
3733	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3734	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3735	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3736
3737	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3738	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3739	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3740	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3741
3742	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3743	AssertBreak(pCursorCopy);
3744
3745	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3746	memset(pCursorCopy, 0xff, cbAndMask);
3747	/* Colour data */
3748	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3749
3750	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3751	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3752	break;
3753	}
3754
3755	case SVGA_CMD_ESCAPE:
3756	{
3757	/* Followed by nsize bytes of data. */
3758	SVGAFifoCmdEscape *pEscape;
3759	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3760	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3761
3762	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3763	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3764	RT_UNTRUSTED_VALIDATED_FENCE();
3765	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3766	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3767
3768	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3769	{
3770	AssertBreak(pEscape->size >= sizeof(uint32_t));
3771	RT_UNTRUSTED_VALIDATED_FENCE();
3772	uint32_t cmd = (uint32_t )(pEscape + 1);
3773	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3774
3775	switch (cmd)
3776	{
3777	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3778	{
3779	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3780	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3781	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3782
3783	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3784	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3785	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3786
3787	RT_NOREF_PV(pVideoCmd);
3788	break;
3789
3790	}
3791
3792	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3793	{
3794	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3795	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3796	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3797	RT_NOREF_PV(pVideoCmd);
3798	break;
3799	}
3800
3801	default:
3802	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3803	break;
3804	}
3805	}
3806	else
3807	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3808
3809	break;
3810	}
3811	# ifdef VBOX_WITH_VMSVGA3D
3812	case SVGA_CMD_DEFINE_GMR2:
3813	{
3814	SVGAFifoCmdDefineGMR2 *pCmd;
3815	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3816	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3817	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3818
3819	/* Validate current GMR id. */
3820	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3821	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3822	RT_UNTRUSTED_VALIDATED_FENCE();
3823
3824	if (!pCmd->numPages)
3825	{
3826	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3827	vmsvgaGMRFree(pThis, pCmd->gmrId);
3828	}
3829	else
3830	{
3831	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3832	if (pGMR->cMaxPages)
3833	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3834
3835	/* Not sure if we should always free the descriptor, but for simplicity
3836	we do so if the new size is smaller than the current. */
3837	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3838	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3839	vmsvgaGMRFree(pThis, pCmd->gmrId);
3840
3841	pGMR->cMaxPages = pCmd->numPages;
3842	/* The rest is done by the REMAP_GMR2 command. */
3843	}
3844	break;
3845	}
3846
3847	case SVGA_CMD_REMAP_GMR2:
3848	{
3849	/* Followed by page descriptors or guest ptr. */
3850	SVGAFifoCmdRemapGMR2 *pCmd;
3851	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3852	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3853
3854	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3855	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3856	RT_UNTRUSTED_VALIDATED_FENCE();
3857
3858	/* Calculate the size of what comes after next and fetch it. */
3859	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3860	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3861	cbCmd += sizeof(SVGAGuestPtr);
3862	else
3863	{
3864	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3865	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3866	{
3867	cbCmd += cbPageDesc;
3868	pCmd->numPages = 1;
3869	}
3870	else
3871	{
3872	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3873	cbCmd += cbPageDesc * pCmd->numPages;
3874	}
3875	}
3876	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3877
3878	/* Validate current GMR id and size. */
3879	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3880	RT_UNTRUSTED_VALIDATED_FENCE();
3881	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3882	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3883	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3884	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3885
3886	if (pCmd->numPages == 0)
3887	break;
3888
3889	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3890	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3891
3892	/*
3893	* We flatten the existing descriptors into a page array, overwrite the
3894	* pages specified in this command and then recompress the descriptor.
3895	*/
3896	/** @todo Optimize the GMR remap algorithm! */
3897
3898	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3899	uint64_t *paNewPage64 = NULL;
3900	if (pGMR->paDesc)
3901	{
3902	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3903
3904	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3905	AssertBreak(paNewPage64);
3906
3907	uint32_t idxPage = 0;
3908	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3909	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3910	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3911	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3912	RT_UNTRUSTED_VALIDATED_FENCE();
3913	}
3914
3915	/* Free the old GMR if present. */
3916	if (pGMR->paDesc)
3917	RTMemFree(pGMR->paDesc);
3918
3919	/* Allocate the maximum amount possible (everything non-continuous) */
3920	PVMSVGAGMRDESCRIPTOR paDescs;
3921	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3922	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3923
3924	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3925	{
3926	/** @todo */
3927	AssertFailed();
3928	pGMR->numDescriptors = 0;
3929	}
3930	else
3931	{
3932	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3933	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3934	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3935
3936	if (paNewPage64)
3937	{
3938	/* Overwrite the old page array with the new page values. */
3939	if (fGCPhys64)
3940	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3941	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3942	else
3943	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3944	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3945
3946	/* Use the updated page array instead of the command data. */
3947	fGCPhys64 = true;
3948	paPages64 = paNewPage64;
3949	pCmd->numPages = cNewTotalPages;
3950	}
3951
3952	/* The first page. */
3953	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3954	* applied to paNewPage64. */
3955	RTGCPHYS GCPhys;
3956	if (fGCPhys64)
3957	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3958	else
3959	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3960	paDescs[0].GCPhys = GCPhys;
3961	paDescs[0].numPages = 1;
3962
3963	/* Subsequent pages. */
3964	uint32_t iDescriptor = 0;
3965	for (uint32_t i = 1; i < pCmd->numPages; i++)
3966	{
3967	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3968	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3969	else
3970	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3971
3972	/* Continuous physical memory? */
3973	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3974	{
3975	Assert(paDescs[iDescriptor].numPages);
3976	paDescs[iDescriptor].numPages++;
3977	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3978	}
3979	else
3980	{
3981	iDescriptor++;
3982	paDescs[iDescriptor].GCPhys = GCPhys;
3983	paDescs[iDescriptor].numPages = 1;
3984	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3985	}
3986	}
3987
3988	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3989	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3990	pGMR->numDescriptors = iDescriptor + 1;
3991	}
3992
3993	if (paNewPage64)
3994	RTMemFree(paNewPage64);
3995
3996	# ifdef DEBUG_GMR_ACCESS
3997	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3998	# endif
3999	break;
4000	}
4001	# endif // VBOX_WITH_VMSVGA3D
4002	case SVGA_CMD_DEFINE_SCREEN:
4003	{
4004	/* The size of this command is specified by the guest and depends on capabilities. */
4005	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4006
4007	SVGAFifoCmdDefineScreen *pCmd;
4008	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4009	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4010	RT_UNTRUSTED_VALIDATED_FENCE();
4011
4012	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4013	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4014	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4015
4016	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4017	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4018	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4019
4020	uint32_t const idScreen = pCmd->screen.id;
4021	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4022
4023	uint32_t const uWidth = pCmd->screen.size.width;
4024	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4025
4026	uint32_t const uHeight = pCmd->screen.size.height;
4027	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4028
4029	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4030	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4031	AssertBreak(cbWidth <= cbPitch);
4032
4033	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4034	AssertBreak(uScreenOffset < pThis->vram_size);
4035
4036	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4037	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4038	AssertBreak( (uHeight == 0 && cbPitch == 0)
4039	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4040	RT_UNTRUSTED_VALIDATED_FENCE();
4041
4042	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4043
4044	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4045
4046	pScreen->fDefined = true;
4047	pScreen->fModified = true;
4048	pScreen->fuScreen = pCmd->screen.flags;
4049	pScreen->idScreen = idScreen;
4050	if (!fBlank)
4051	{
4052	AssertBreak(uWidth > 0 && uHeight > 0);
4053
4054	pScreen->xOrigin = pCmd->screen.root.x;
4055	pScreen->yOrigin = pCmd->screen.root.y;
4056	pScreen->cWidth = uWidth;
4057	pScreen->cHeight = uHeight;
4058	pScreen->offVRAM = uScreenOffset;
4059	pScreen->cbPitch = cbPitch;
4060	pScreen->cBpp = 32;
4061	}
4062	else
4063	{
4064	/* Keep old values. */
4065	}
4066
4067	pThis->svga.fGFBRegisters = false;
4068	vmsvgaChangeMode(pThis);
4069	break;
4070	}
4071
4072	case SVGA_CMD_DESTROY_SCREEN:
4073	{
4074	SVGAFifoCmdDestroyScreen *pCmd;
4075	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4076	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4077
4078	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4079
4080	uint32_t const idScreen = pCmd->screenId;
4081	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4082	RT_UNTRUSTED_VALIDATED_FENCE();
4083
4084	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4085	pScreen->fModified = true;
4086	pScreen->fDefined = false;
4087	pScreen->idScreen = idScreen;
4088
4089	vmsvgaChangeMode(pThis);
4090	break;
4091	}
4092
4093	case SVGA_CMD_DEFINE_GMRFB:
4094	{
4095	SVGAFifoCmdDefineGMRFB *pCmd;
4096	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4097	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4098
4099	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4100	pSVGAState->GMRFB.ptr = pCmd->ptr;
4101	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4102	pSVGAState->GMRFB.format = pCmd->format;
4103	break;
4104	}
4105
4106	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4107	{
4108	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4109	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4110	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4111
4112	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4113	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4114
4115	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4116	RT_UNTRUSTED_VALIDATED_FENCE();
4117
4118	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4119	AssertBreak(pScreen);
4120
4121	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4122	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4123
4124	/* Clip destRect to the screen dimensions. */
4125	SVGASignedRect screenRect;
4126	screenRect.left = 0;
4127	screenRect.top = 0;
4128	screenRect.right = pScreen->cWidth;
4129	screenRect.bottom = pScreen->cHeight;
4130	SVGASignedRect clipRect = pCmd->destRect;
4131	vmsvgaClipRect(&screenRect, &clipRect);
4132	RT_UNTRUSTED_VALIDATED_FENCE();
4133
4134	uint32_t const width = clipRect.right - clipRect.left;
4135	uint32_t const height = clipRect.bottom - clipRect.top;
4136
4137	if ( width == 0
4138	\|\| height == 0)
4139	break; /* Nothing to do. */
4140
4141	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4142	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4143
4144	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4145	* Prepare parameters for vmsvgaGMRTransfer.
4146	*/
4147	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4148
4149	/* Destination: host buffer which describes the screen 0 VRAM.
4150	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4151	*/
4152	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4153	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4154	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4155	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4156	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4157	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4158	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4159	+ cbScanline * clipRect.top;
4160	int32_t const cbHstPitch = cbScanline;
4161
4162	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4163	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4164	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4165	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4166	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4167
4168	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4169	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4170	gstPtr, offGst, cbGstPitch,
4171	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4172	AssertRC(rc);
4173	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4174	break;
4175	}
4176
4177	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4178	{
4179	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4180	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4181	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4182
4183	/* Note! This can fetch 3d render results as well!! */
4184	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4185	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4186
4187	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4188	RT_UNTRUSTED_VALIDATED_FENCE();
4189
4190	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4191	AssertBreak(pScreen);
4192
4193	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4194	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4195
4196	/* Clip destRect to the screen dimensions. */
4197	SVGASignedRect screenRect;
4198	screenRect.left = 0;
4199	screenRect.top = 0;
4200	screenRect.right = pScreen->cWidth;
4201	screenRect.bottom = pScreen->cHeight;
4202	SVGASignedRect clipRect = pCmd->srcRect;
4203	vmsvgaClipRect(&screenRect, &clipRect);
4204	RT_UNTRUSTED_VALIDATED_FENCE();
4205
4206	uint32_t const width = clipRect.right - clipRect.left;
4207	uint32_t const height = clipRect.bottom - clipRect.top;
4208
4209	if ( width == 0
4210	\|\| height == 0)
4211	break; /* Nothing to do. */
4212
4213	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4214	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4215
4216	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4217	* Prepare parameters for vmsvgaGMRTransfer.
4218	*/
4219	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4220
4221	/* Source: host buffer which describes the screen 0 VRAM.
4222	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4223	*/
4224	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4225	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4226	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4227	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4228	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4229	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4230	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4231	+ cbScanline * clipRect.top;
4232	int32_t const cbHstPitch = cbScanline;
4233
4234	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4235	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4236	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4237	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4238	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4239
4240	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4241	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4242	gstPtr, offGst, cbGstPitch,
4243	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4244	AssertRC(rc);
4245	break;
4246	}
4247
4248	case SVGA_CMD_ANNOTATION_FILL:
4249	{
4250	SVGAFifoCmdAnnotationFill *pCmd;
4251	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4252	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4253
4254	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4255	pSVGAState->colorAnnotation = pCmd->color;
4256	break;
4257	}
4258
4259	case SVGA_CMD_ANNOTATION_COPY:
4260	{
4261	SVGAFifoCmdAnnotationCopy *pCmd;
4262	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4263	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4264
4265	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4266	AssertFailed();
4267	break;
4268	}
4269
4270	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4271
4272	default:
4273	# ifdef VBOX_WITH_VMSVGA3D
4274	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4275	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4276	{
4277	RT_UNTRUSTED_VALIDATED_FENCE();
4278
4279	/* All 3d commands start with a common header, which defines the size of the command. */
4280	SVGA3dCmdHeader *pHdr;
4281	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4282	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4283	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4284	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4285
4286	if (RT_LIKELY(pThis->svga.f3DEnabled))
4287	{ /* likely */ }
4288	else
4289	{
4290	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4291	break;
4292	}
4293
4294	/**
4295	* Check that the 3D command has at least a_cbMin of payload bytes after the
4296	* header. Will break out of the switch if it doesn't.
4297	*/
4298	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4299	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4300	RT_UNTRUSTED_VALIDATED_FENCE(); \
4301	} while (0)
4302	switch ((int)enmCmdId)
4303	{
4304	case SVGA_3D_CMD_SURFACE_DEFINE:
4305	{
4306	uint32_t cMipLevels;
4307	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4308	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4309	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4310
4311	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4312	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4313	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4314	# ifdef DEBUG_GMR_ACCESS
4315	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4316	# endif
4317	break;
4318	}
4319
4320	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4321	{
4322	uint32_t cMipLevels;
4323	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4326
4327	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4328	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4329	pCmd->multisampleCount, pCmd->autogenFilter,
4330	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4331	break;
4332	}
4333
4334	case SVGA_3D_CMD_SURFACE_DESTROY:
4335	{
4336	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4337	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4338	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4339	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4340	break;
4341	}
4342
4343	case SVGA_3D_CMD_SURFACE_COPY:
4344	{
4345	uint32_t cCopyBoxes;
4346	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4347	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4348	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4349
4350	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4351	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4352	break;
4353	}
4354
4355	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4356	{
4357	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4358	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4359	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4360
4361	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4362	break;
4363	}
4364
4365	case SVGA_3D_CMD_SURFACE_DMA:
4366	{
4367	uint32_t cCopyBoxes;
4368	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4371
4372	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4373	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4374	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4375	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4376	break;
4377	}
4378
4379	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4380	{
4381	uint32_t cRects;
4382	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4383	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4384	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4385
4386	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4387	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4388	break;
4389	}
4390
4391	case SVGA_3D_CMD_CONTEXT_DEFINE:
4392	{
4393	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4394	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4396
4397	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4398	break;
4399	}
4400
4401	case SVGA_3D_CMD_CONTEXT_DESTROY:
4402	{
4403	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4404	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4405	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4406
4407	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4408	break;
4409	}
4410
4411	case SVGA_3D_CMD_SETTRANSFORM:
4412	{
4413	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4414	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4415	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4416
4417	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4418	break;
4419	}
4420
4421	case SVGA_3D_CMD_SETZRANGE:
4422	{
4423	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4424	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4425	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4426
4427	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4428	break;
4429	}
4430
4431	case SVGA_3D_CMD_SETRENDERSTATE:
4432	{
4433	uint32_t cRenderStates;
4434	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4435	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4436	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4437
4438	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4439	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_SETRENDERTARGET:
4444	{
4445	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4448
4449	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4450	break;
4451	}
4452
4453	case SVGA_3D_CMD_SETTEXTURESTATE:
4454	{
4455	uint32_t cTextureStates;
4456	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4457	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4459
4460	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4461	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4462	break;
4463	}
4464
4465	case SVGA_3D_CMD_SETMATERIAL:
4466	{
4467	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4468	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4469	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4470
4471	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4472	break;
4473	}
4474
4475	case SVGA_3D_CMD_SETLIGHTDATA:
4476	{
4477	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4478	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4479	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4480
4481	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4482	break;
4483	}
4484
4485	case SVGA_3D_CMD_SETLIGHTENABLED:
4486	{
4487	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4488	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4489	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4490
4491	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4492	break;
4493	}
4494
4495	case SVGA_3D_CMD_SETVIEWPORT:
4496	{
4497	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4500
4501	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4502	break;
4503	}
4504
4505	case SVGA_3D_CMD_SETCLIPPLANE:
4506	{
4507	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4508	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4509	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4510
4511	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4512	break;
4513	}
4514
4515	case SVGA_3D_CMD_CLEAR:
4516	{
4517	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4518	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4520
4521	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4522	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4523	break;
4524	}
4525
4526	case SVGA_3D_CMD_PRESENT:
4527	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4528	{
4529	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4532	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4533	else
4534	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4535
4536	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4537
4538	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4539	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4540	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4541	break;
4542	}
4543
4544	case SVGA_3D_CMD_SHADER_DEFINE:
4545	{
4546	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4547	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4548	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4549
4550	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4551	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_SHADER_DESTROY:
4556	{
4557	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4560
4561	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4562	break;
4563	}
4564
4565	case SVGA_3D_CMD_SET_SHADER:
4566	{
4567	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4568	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4569	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4570
4571	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4572	break;
4573	}
4574
4575	case SVGA_3D_CMD_SET_SHADER_CONST:
4576	{
4577	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4578	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4579	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4580
4581	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4582	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4583	break;
4584	}
4585
4586	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4587	{
4588	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4589	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4590	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4591
4592	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4593	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4594	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4595	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4596	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4597
4598	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4599	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4600
4601	RT_UNTRUSTED_VALIDATED_FENCE();
4602
4603	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4604	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4605	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4606
4607	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4608	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4609	pNumRange, cVertexDivisor, pVertexDivisor);
4610	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4611	break;
4612	}
4613
4614	case SVGA_3D_CMD_SETSCISSORRECT:
4615	{
4616	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4617	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4618	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4619
4620	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4621	break;
4622	}
4623
4624	case SVGA_3D_CMD_BEGIN_QUERY:
4625	{
4626	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4627	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4628	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4629
4630	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4631	break;
4632	}
4633
4634	case SVGA_3D_CMD_END_QUERY:
4635	{
4636	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4637	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4638	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4639
4640	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4641	break;
4642	}
4643
4644	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4645	{
4646	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4647	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4648	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4649
4650	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4651	break;
4652	}
4653
4654	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4655	{
4656	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4657	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4658	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4659
4660	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4661	break;
4662	}
4663
4664	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4665	/* context id + surface id? */
4666	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4667	break;
4668	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4669	/* context id + surface id? */
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4671	break;
4672
4673	default:
4674	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4675	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4676	break;
4677	}
4678	}
4679	else
4680	# endif // VBOX_WITH_VMSVGA3D
4681	{
4682	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4683	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4684	}
4685	}
4686
4687	/* Go to the next slot */
4688	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4689	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4690	if (offCurrentCmd >= offFifoMax)
4691	{
4692	offCurrentCmd -= offFifoMax - offFifoMin;
4693	Assert(offCurrentCmd >= offFifoMin);
4694	Assert(offCurrentCmd < offFifoMax);
4695	}
4696	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4697	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4698
4699	/*
4700	* Raise IRQ if required. Must enter the critical section here
4701	* before making final decisions here, otherwise cubebench and
4702	* others may end up waiting forever.
4703	*/
4704	if ( u32IrqStatus
4705	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4706	{
4707	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4708	AssertRC(rc2);
4709
4710	/* FIFO progress might trigger an interrupt. */
4711	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4712	{
4713	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4714	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4715	}
4716
4717	/* Unmasked IRQ pending? */
4718	if (pThis->svga.u32IrqMask & u32IrqStatus)
4719	{
4720	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4721	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4722	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4723	}
4724
4725	PDMCritSectLeave(&pThis->CritSect);
4726	}
4727	}
4728
4729	/* If really done, clear the busy flag. */
4730	if (fDone)
4731	{
4732	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4733	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4734	}
4735	}
4736
4737	/*
4738	* Free the bounce buffer. (There are no returns above!)
4739	*/
4740	RTMemFree(pbBounceBuf);
4741
4742	return VINF_SUCCESS;
4743	}
4744
4745	/**
4746	* Free the specified GMR
4747	*
4748	* @param pThis VGA device instance data.
4749	* @param idGMR GMR id
4750	*/
4751	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4752	{
4753	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4754
4755	/* Free the old descriptor if present. */
4756	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4757	if ( pGMR->numDescriptors
4758	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4759	{
4760	# ifdef DEBUG_GMR_ACCESS
4761	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4762	# endif
4763
4764	Assert(pGMR->paDesc);
4765	RTMemFree(pGMR->paDesc);
4766	pGMR->paDesc = NULL;
4767	pGMR->numDescriptors = 0;
4768	pGMR->cbTotal = 0;
4769	pGMR->cMaxPages = 0;
4770	}
4771	Assert(!pGMR->cMaxPages);
4772	Assert(!pGMR->cbTotal);
4773	}
4774
4775	/**
4776	* Copy between a GMR and a host memory buffer.
4777	*
4778	* @returns VBox status code.
4779	* @param pThis VGA device instance data.
4780	* @param enmTransferType Transfer type (read/write)
4781	* @param pbHstBuf Host buffer pointer (valid)
4782	* @param cbHstBuf Size of host buffer (valid)
4783	* @param offHst Host buffer offset of the first scanline
4784	* @param cbHstPitch Destination buffer pitch
4785	* @param gstPtr GMR description
4786	* @param offGst Guest buffer offset of the first scanline
4787	* @param cbGstPitch Guest buffer pitch
4788	* @param cbWidth Width in bytes to copy
4789	* @param cHeight Number of scanllines to copy
4790	*/
4791	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4792	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4793	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4794	uint32_t cbWidth, uint32_t cHeight)
4795	{
4796	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4797	int rc;
4798
4799	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4800	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4801	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4802	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4803	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4804
4805	PGMR pGMR;
4806	uint32_t cbGmr; /* The GMR size in bytes. */
4807	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4808	{
4809	pGMR = NULL;
4810	cbGmr = pThis->vram_size;
4811	}
4812	else
4813	{
4814	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4815	RT_UNTRUSTED_VALIDATED_FENCE();
4816	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4817	cbGmr = pGMR->cbTotal;
4818	}
4819
4820	/*
4821	* GMR
4822	*/
4823	/* Calculate GMR offset of the data to be copied. */
4824	AssertMsgReturn(gstPtr.offset < cbGmr,
4825	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4826	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4827	VERR_INVALID_PARAMETER);
4828	RT_UNTRUSTED_VALIDATED_FENCE();
4829	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4830	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4831	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4832	VERR_INVALID_PARAMETER);
4833	RT_UNTRUSTED_VALIDATED_FENCE();
4834	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4835
4836	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4837	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4838	AssertMsgReturn(cbGmrScanline != 0,
4839	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4840	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4841	VERR_INVALID_PARAMETER);
4842	RT_UNTRUSTED_VALIDATED_FENCE();
4843	AssertMsgReturn(cbWidth <= cbGmrScanline,
4844	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4845	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4846	VERR_INVALID_PARAMETER);
4847	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4848	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4849	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4850	VERR_INVALID_PARAMETER);
4851	RT_UNTRUSTED_VALIDATED_FENCE();
4852
4853	/* How many bytes are available for the data in the GMR. */
4854	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4855
4856	/* How many scanlines would fit into the available data. */
4857	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4858	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4859	if (cbWidth <= cbGmrLastScanline)
4860	++cGmrScanlines;
4861
4862	if (cHeight > cGmrScanlines)
4863	cHeight = cGmrScanlines;
4864
4865	AssertMsgReturn(cHeight > 0,
4866	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4867	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4868	VERR_INVALID_PARAMETER);
4869	RT_UNTRUSTED_VALIDATED_FENCE();
4870
4871	/*
4872	* Host buffer.
4873	*/
4874	AssertMsgReturn(offHst < cbHstBuf,
4875	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4876	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4877	VERR_INVALID_PARAMETER);
4878
4879	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4880	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4881	AssertMsgReturn(cbHstScanline != 0,
4882	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4883	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4884	VERR_INVALID_PARAMETER);
4885	AssertMsgReturn(cbWidth <= cbHstScanline,
4886	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4887	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4888	VERR_INVALID_PARAMETER);
4889	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4890	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4891	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4892	VERR_INVALID_PARAMETER);
4893
4894	/* How many bytes are available for the data in the buffer. */
4895	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4896
4897	/* How many scanlines would fit into the available data. */
4898	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4899	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4900	if (cbWidth <= cbHstLastScanline)
4901	++cHstScanlines;
4902
4903	if (cHeight > cHstScanlines)
4904	cHeight = cHstScanlines;
4905
4906	AssertMsgReturn(cHeight > 0,
4907	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4908	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4909	VERR_INVALID_PARAMETER);
4910
4911	uint8_t *pbHst = pbHstBuf + offHst;
4912
4913	/* Shortcut for the framebuffer. */
4914	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4915	{
4916	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4917
4918	uint8_t const *pbSrc;
4919	int32_t cbSrcPitch;
4920	uint8_t *pbDst;
4921	int32_t cbDstPitch;
4922
4923	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4924	{
4925	pbSrc = pbHst;
4926	cbSrcPitch = cbHstPitch;
4927	pbDst = pbGst;
4928	cbDstPitch = cbGstPitch;
4929	}
4930	else
4931	{
4932	pbSrc = pbGst;
4933	cbSrcPitch = cbGstPitch;
4934	pbDst = pbHst;
4935	cbDstPitch = cbHstPitch;
4936	}
4937
4938	if ( cbWidth == (uint32_t)cbGstPitch
4939	&& cbGstPitch == cbHstPitch)
4940	{
4941	/* Entire scanlines, positive pitch. */
4942	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4943	}
4944	else
4945	{
4946	for (uint32_t i = 0; i < cHeight; ++i)
4947	{
4948	memcpy(pbDst, pbSrc, cbWidth);
4949
4950	pbDst += cbDstPitch;
4951	pbSrc += cbSrcPitch;
4952	}
4953	}
4954	return VINF_SUCCESS;
4955	}
4956
4957	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4958	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4959
4960	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4961	uint32_t iDesc = 0; /* Index in the descriptor array. */
4962	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4963	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4964	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4965	for (uint32_t i = 0; i < cHeight; ++i)
4966	{
4967	uint32_t cbCurrentWidth = cbWidth;
4968	uint32_t offGmrCurrent = offGmrScanline;
4969	uint8_t *pbCurrentHost = pbHstScanline;
4970
4971	/* Find the right descriptor */
4972	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4973	{
4974	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4975	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4976	++iDesc;
4977	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4978	}
4979
4980	while (cbCurrentWidth)
4981	{
4982	uint32_t cbToCopy;
4983
4984	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4985	{
4986	cbToCopy = cbCurrentWidth;
4987	}
4988	else
4989	{
4990	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4991	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4992	}
4993
4994	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4995
4996	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4997
4998	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4999	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5000	else
5001	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5002	AssertRCBreak(rc);
5003
5004	cbCurrentWidth -= cbToCopy;
5005	offGmrCurrent += cbToCopy;
5006	pbCurrentHost += cbToCopy;
5007
5008	/* Go to the next descriptor if there's anything left. */
5009	if (cbCurrentWidth)
5010	{
5011	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5012	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5013	++iDesc;
5014	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5015	}
5016	}
5017
5018	offGmrScanline += cbGstPitch;
5019	pbHstScanline += cbHstPitch;
5020	}
5021
5022	return VINF_SUCCESS;
5023	}
5024
5025
5026	/**
5027	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5028	*
5029	* @param pSizeSrc Source surface dimensions.
5030	* @param pSizeDest Destination surface dimensions.
5031	* @param pBox Coordinates to be clipped.
5032	*/
5033	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5034	const SVGA3dSize *pSizeDest,
5035	SVGA3dCopyBox *pBox)
5036	{
5037	/* Src x, w */
5038	if (pBox->srcx > pSizeSrc->width)
5039	pBox->srcx = pSizeSrc->width;
5040	if (pBox->w > pSizeSrc->width - pBox->srcx)
5041	pBox->w = pSizeSrc->width - pBox->srcx;
5042
5043	/* Src y, h */
5044	if (pBox->srcy > pSizeSrc->height)
5045	pBox->srcy = pSizeSrc->height;
5046	if (pBox->h > pSizeSrc->height - pBox->srcy)
5047	pBox->h = pSizeSrc->height - pBox->srcy;
5048
5049	/* Src z, d */
5050	if (pBox->srcz > pSizeSrc->depth)
5051	pBox->srcz = pSizeSrc->depth;
5052	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5053	pBox->d = pSizeSrc->depth - pBox->srcz;
5054
5055	/* Dest x, w */
5056	if (pBox->x > pSizeDest->width)
5057	pBox->x = pSizeDest->width;
5058	if (pBox->w > pSizeDest->width - pBox->x)
5059	pBox->w = pSizeDest->width - pBox->x;
5060
5061	/* Dest y, h */
5062	if (pBox->y > pSizeDest->height)
5063	pBox->y = pSizeDest->height;
5064	if (pBox->h > pSizeDest->height - pBox->y)
5065	pBox->h = pSizeDest->height - pBox->y;
5066
5067	/* Dest z, d */
5068	if (pBox->z > pSizeDest->depth)
5069	pBox->z = pSizeDest->depth;
5070	if (pBox->d > pSizeDest->depth - pBox->z)
5071	pBox->d = pSizeDest->depth - pBox->z;
5072	}
5073
5074	/**
5075	* Unsigned coordinates in pBox. Clip to [0; pSize).
5076	*
5077	* @param pSize Source surface dimensions.
5078	* @param pBox Coordinates to be clipped.
5079	*/
5080	void vmsvgaClipBox(const SVGA3dSize *pSize,
5081	SVGA3dBox *pBox)
5082	{
5083	/* x, w */
5084	if (pBox->x > pSize->width)
5085	pBox->x = pSize->width;
5086	if (pBox->w > pSize->width - pBox->x)
5087	pBox->w = pSize->width - pBox->x;
5088
5089	/* y, h */
5090	if (pBox->y > pSize->height)
5091	pBox->y = pSize->height;
5092	if (pBox->h > pSize->height - pBox->y)
5093	pBox->h = pSize->height - pBox->y;
5094
5095	/* z, d */
5096	if (pBox->z > pSize->depth)
5097	pBox->z = pSize->depth;
5098	if (pBox->d > pSize->depth - pBox->z)
5099	pBox->d = pSize->depth - pBox->z;
5100	}
5101
5102	/**
5103	* Clip.
5104	*
5105	* @param pBound Bounding rectangle.
5106	* @param pRect Rectangle to be clipped.
5107	*/
5108	void vmsvgaClipRect(SVGASignedRect const *pBound,
5109	SVGASignedRect *pRect)
5110	{
5111	int32_t left;
5112	int32_t top;
5113	int32_t right;
5114	int32_t bottom;
5115
5116	/* Right order. */
5117	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5118	if (pRect->left < pRect->right)
5119	{
5120	left = pRect->left;
5121	right = pRect->right;
5122	}
5123	else
5124	{
5125	left = pRect->right;
5126	right = pRect->left;
5127	}
5128	if (pRect->top < pRect->bottom)
5129	{
5130	top = pRect->top;
5131	bottom = pRect->bottom;
5132	}
5133	else
5134	{
5135	top = pRect->bottom;
5136	bottom = pRect->top;
5137	}
5138
5139	if (left < pBound->left)
5140	left = pBound->left;
5141	if (right < pBound->left)
5142	right = pBound->left;
5143
5144	if (left > pBound->right)
5145	left = pBound->right;
5146	if (right > pBound->right)
5147	right = pBound->right;
5148
5149	if (top < pBound->top)
5150	top = pBound->top;
5151	if (bottom < pBound->top)
5152	bottom = pBound->top;
5153
5154	if (top > pBound->bottom)
5155	top = pBound->bottom;
5156	if (bottom > pBound->bottom)
5157	bottom = pBound->bottom;
5158
5159	pRect->left = left;
5160	pRect->right = right;
5161	pRect->top = top;
5162	pRect->bottom = bottom;
5163	}
5164
5165	/**
5166	* Unblock the FIFO I/O thread so it can respond to a state change.
5167	*
5168	* @returns VBox status code.
5169	* @param pDevIns The VGA device instance.
5170	* @param pThread The send thread.
5171	*/
5172	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5173	{
5174	RT_NOREF(pDevIns);
5175	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5176	Log(("vmsvgaFIFOLoopWakeUp\n"));
5177	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5178	}
5179
5180	/**
5181	* Enables or disables dirty page tracking for the framebuffer
5182	*
5183	* @param pThis VGA device instance data.
5184	* @param fTraces Enable/disable traces
5185	*/
5186	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5187	{
5188	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5189	&& !fTraces)
5190	{
5191	//Assert(pThis->svga.fTraces);
5192	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5193	return;
5194	}
5195
5196	pThis->svga.fTraces = fTraces;
5197	if (pThis->svga.fTraces)
5198	{
5199	unsigned cbFrameBuffer = pThis->vram_size;
5200
5201	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5202	/** @todo How does this work with screens? */
5203	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5204	{
5205	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5206	Assert(pThis->svga.cbScanline);
5207	#endif
5208	/* Hardware enabled; return real framebuffer size .*/
5209	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5210	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5211	}
5212
5213	if (!pThis->svga.fVRAMTracking)
5214	{
5215	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5216	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5217	pThis->svga.fVRAMTracking = true;
5218	}
5219	}
5220	else
5221	{
5222	if (pThis->svga.fVRAMTracking)
5223	{
5224	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5225	vgaR3UnregisterVRAMHandler(pThis);
5226	pThis->svga.fVRAMTracking = false;
5227	}
5228	}
5229	}
5230
5231	/**
5232	* @callback_method_impl{FNPCIIOREGIONMAP}
5233	*/
5234	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5235	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5236	{
5237	int rc;
5238	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5239
5240	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5241	if (enmType == PCI_ADDRESS_SPACE_IO)
5242	{
5243	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5244	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5245	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5246	if (RT_FAILURE(rc))
5247	return rc;
5248	if (pThis->fR0Enabled)
5249	{
5250	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5251	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5252	if (RT_FAILURE(rc))
5253	return rc;
5254	}
5255	if (pThis->fGCEnabled)
5256	{
5257	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5258	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5259	if (RT_FAILURE(rc))
5260	return rc;
5261	}
5262
5263	pThis->svga.BasePort = GCPhysAddress;
5264	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5265	}
5266	else
5267	{
5268	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5269	if (GCPhysAddress != NIL_RTGCPHYS)
5270	{
5271	/*
5272	* Mapping the FIFO RAM.
5273	*/
5274	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5275	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5276	AssertRC(rc);
5277
5278	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5279	if (RT_SUCCESS(rc))
5280	{
5281	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5282	# ifdef DEBUG_FIFO_ACCESS
5283	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5284	# else
5285	GCPhysAddress + PAGE_SIZE - 1,
5286	# endif
5287	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5288	"VMSVGA FIFO");
5289	AssertRC(rc);
5290	}
5291	# endif
5292	if (RT_SUCCESS(rc))
5293	{
5294	pThis->svga.GCPhysFIFO = GCPhysAddress;
5295	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5296	}
5297	}
5298	else
5299	{
5300	Assert(pThis->svga.GCPhysFIFO);
5301	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5302	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5303	AssertRC(rc);
5304	# endif
5305	pThis->svga.GCPhysFIFO = 0;
5306	}
5307	}
5308	return VINF_SUCCESS;
5309	}
5310
5311	# ifdef VBOX_WITH_VMSVGA3D
5312
5313	/**
5314	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5315	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5316	*
5317	* @param pThis The VGA device instance data.
5318	* @param sid Either UINT32_MAX or the ID of a specific
5319	* surface. If UINT32_MAX is used, all surfaces
5320	* are processed.
5321	*/
5322	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5323	{
5324	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5325	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5326	}
5327
5328
5329	/**
5330	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5331	*/
5332	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5333	{
5334	/* There might be a specific surface ID at the start of the
5335	arguments, if not show all surfaces. */
5336	uint32_t sid = UINT32_MAX;
5337	if (pszArgs)
5338	pszArgs = RTStrStripL(pszArgs);
5339	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5340	sid = RTStrToUInt32(pszArgs);
5341
5342	/* Verbose or terse display, we default to verbose. */
5343	bool fVerbose = true;
5344	if (RTStrIStr(pszArgs, "terse"))
5345	fVerbose = false;
5346
5347	/* The size of the ascii art (x direction, y is 3/4 of x). */
5348	uint32_t cxAscii = 80;
5349	if (RTStrIStr(pszArgs, "gigantic"))
5350	cxAscii = 300;
5351	else if (RTStrIStr(pszArgs, "huge"))
5352	cxAscii = 180;
5353	else if (RTStrIStr(pszArgs, "big"))
5354	cxAscii = 132;
5355	else if (RTStrIStr(pszArgs, "normal"))
5356	cxAscii = 80;
5357	else if (RTStrIStr(pszArgs, "medium"))
5358	cxAscii = 64;
5359	else if (RTStrIStr(pszArgs, "small"))
5360	cxAscii = 48;
5361	else if (RTStrIStr(pszArgs, "tiny"))
5362	cxAscii = 24;
5363
5364	/* Y invert the image when producing the ASCII art. */
5365	bool fInvY = false;
5366	if (RTStrIStr(pszArgs, "invy"))
5367	fInvY = true;
5368
5369	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5370	}
5371
5372
5373	/**
5374	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5375	*/
5376	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5377	{
5378	/* pszArg = "sid[>dir]"
5379	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5380	*/
5381	char *pszBitmapPath = NULL;
5382	uint32_t sid = UINT32_MAX;
5383	if (pszArgs)
5384	pszArgs = RTStrStripL(pszArgs);
5385	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5386	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5387	if ( pszBitmapPath
5388	&& *pszBitmapPath == '>')
5389	++pszBitmapPath;
5390
5391	const bool fVerbose = true;
5392	const uint32_t cxAscii = 0; /* No ASCII */
5393	const bool fInvY = false; /* Do not invert. */
5394	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5395	}
5396
5397
5398	/**
5399	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5400	*/
5401	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5402	{
5403	/* There might be a specific surface ID at the start of the
5404	arguments, if not show all contexts. */
5405	uint32_t sid = UINT32_MAX;
5406	if (pszArgs)
5407	pszArgs = RTStrStripL(pszArgs);
5408	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5409	sid = RTStrToUInt32(pszArgs);
5410
5411	/* Verbose or terse display, we default to verbose. */
5412	bool fVerbose = true;
5413	if (RTStrIStr(pszArgs, "terse"))
5414	fVerbose = false;
5415
5416	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5417	}
5418
5419	# endif /* VBOX_WITH_VMSVGA3D */
5420
5421	/**
5422	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5423	*/
5424	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5425	{
5426	RT_NOREF(pszArgs);
5427	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5428	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5429
5430	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5431	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5432	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5433	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5434	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5435	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5436	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5437	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5438	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5439	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5440	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5441	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5442	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5443	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5444	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5445	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5446	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5447	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5448	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5449	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5450	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5451	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5452
5453	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5454	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5455	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5456	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5457
5458	# ifdef VBOX_WITH_VMSVGA3D
5459	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5460	# endif
5461	if (pThis->pDrv)
5462	{
5463	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5464	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5465	}
5466	}
5467
5468	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5469	*/
5470	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5471	{
5472	RT_NOREF(uPass);
5473
5474	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5475	int rc;
5476
5477	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5478	{
5479	uint32_t cScreens = 0;
5480	rc = SSMR3GetU32(pSSM, &cScreens);
5481	AssertRCReturn(rc, rc);
5482	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5483	("cScreens=%#x\n", cScreens),
5484	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5485
5486	for (uint32_t i = 0; i < cScreens; ++i)
5487	{
5488	VMSVGASCREENOBJECT screen;
5489	RT_ZERO(screen);
5490
5491	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5492	AssertLogRelRCReturn(rc, rc);
5493
5494	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5495	{
5496	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5497	*pScreen = screen;
5498	pScreen->fModified = true;
5499	}
5500	else
5501	{
5502	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5503	}
5504	}
5505	}
5506	else
5507	{
5508	/* Try to setup at least the first screen. */
5509	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5510	pScreen->fDefined = true;
5511	pScreen->fModified = true;
5512	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5513	pScreen->idScreen = 0;
5514	pScreen->xOrigin = 0;
5515	pScreen->yOrigin = 0;
5516	pScreen->offVRAM = pThis->svga.uScreenOffset;
5517	pScreen->cbPitch = pThis->svga.cbScanline;
5518	pScreen->cWidth = pThis->svga.uWidth;
5519	pScreen->cHeight = pThis->svga.uHeight;
5520	pScreen->cBpp = pThis->svga.uBpp;
5521	}
5522
5523	return VINF_SUCCESS;
5524	}
5525
5526	/**
5527	* @copydoc FNSSMDEVLOADEXEC
5528	*/
5529	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5530	{
5531	RT_NOREF(uPass);
5532	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5533	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5534	int rc;
5535
5536	/* Load our part of the VGAState */
5537	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5538	AssertRCReturn(rc, rc);
5539
5540	/* Load the VGA framebuffer. */
5541	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5542	uint32_t cbVgaFramebuffer = _32K;
5543	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5544	{
5545	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5546	AssertRCReturn(rc, rc);
5547	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5548	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5549	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5550	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5551	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5552	}
5553	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5554	AssertRCReturn(rc, rc);
5555	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5556	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5557	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5558	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5559
5560	/* Load the VMSVGA state. */
5561	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5562	AssertRCReturn(rc, rc);
5563
5564	/* Load the active cursor bitmaps. */
5565	if (pSVGAState->Cursor.fActive)
5566	{
5567	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5568	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5569
5570	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5571	AssertRCReturn(rc, rc);
5572	}
5573
5574	/* Load the GMR state. */
5575	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5576	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5577	{
5578	rc = SSMR3GetU32(pSSM, &cGMR);
5579	AssertRCReturn(rc, rc);
5580	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5581	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5582	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5583	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5584	}
5585
5586	if (pThis->svga.cGMR != cGMR)
5587	{
5588	/* Reallocate GMR array. */
5589	Assert(pSVGAState->paGMR != NULL);
5590	RTMemFree(pSVGAState->paGMR);
5591	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5592	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5593	pThis->svga.cGMR = cGMR;
5594	}
5595
5596	for (uint32_t i = 0; i < cGMR; ++i)
5597	{
5598	PGMR pGMR = &pSVGAState->paGMR[i];
5599
5600	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5601	AssertRCReturn(rc, rc);
5602
5603	if (pGMR->numDescriptors)
5604	{
5605	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5606	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5607	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5608
5609	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5610	{
5611	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5612	AssertRCReturn(rc, rc);
5613	}
5614	}
5615	}
5616
5617	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5618	vmsvga3dPowerOn(pThis);
5619	# endif
5620
5621	VMSVGA_STATE_LOAD LoadState;
5622	LoadState.pSSM = pSSM;
5623	LoadState.uVersion = uVersion;
5624	LoadState.uPass = uPass;
5625	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5626	AssertLogRelRCReturn(rc, rc);
5627
5628	return VINF_SUCCESS;
5629	}
5630
5631	/**
5632	* Reinit the video mode after the state has been loaded.
5633	*/
5634	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5635	{
5636	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5637	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5638
5639	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5640
5641	/* Set the active cursor. */
5642	if (pSVGAState->Cursor.fActive)
5643	{
5644	int rc;
5645
5646	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5647	true,
5648	true,
5649	pSVGAState->Cursor.xHotspot,
5650	pSVGAState->Cursor.yHotspot,
5651	pSVGAState->Cursor.width,
5652	pSVGAState->Cursor.height,
5653	pSVGAState->Cursor.pData);
5654	AssertRC(rc);
5655	}
5656	return VINF_SUCCESS;
5657	}
5658
5659	/**
5660	* Portion of SVGA state which must be saved in the FIFO thread.
5661	*/
5662	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5663	{
5664	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5665	int rc;
5666
5667	/* Save the screen objects. */
5668	/* Count defined screen object. */
5669	uint32_t cScreens = 0;
5670	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5671	{
5672	if (pSVGAState->aScreens[i].fDefined)
5673	++cScreens;
5674	}
5675
5676	rc = SSMR3PutU32(pSSM, cScreens);
5677	AssertLogRelRCReturn(rc, rc);
5678
5679	for (uint32_t i = 0; i < cScreens; ++i)
5680	{
5681	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5682
5683	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5684	AssertLogRelRCReturn(rc, rc);
5685	}
5686	return VINF_SUCCESS;
5687	}
5688
5689	/**
5690	* @copydoc FNSSMDEVSAVEEXEC
5691	*/
5692	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5693	{
5694	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5695	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5696	int rc;
5697
5698	/* Save our part of the VGAState */
5699	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5700	AssertLogRelRCReturn(rc, rc);
5701
5702	/* Save the framebuffer backup. */
5703	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5704	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5705	AssertLogRelRCReturn(rc, rc);
5706
5707	/* Save the VMSVGA state. */
5708	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5709	AssertLogRelRCReturn(rc, rc);
5710
5711	/* Save the active cursor bitmaps. */
5712	if (pSVGAState->Cursor.fActive)
5713	{
5714	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5715	AssertLogRelRCReturn(rc, rc);
5716	}
5717
5718	/* Save the GMR state */
5719	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5720	AssertLogRelRCReturn(rc, rc);
5721	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5722	{
5723	PGMR pGMR = &pSVGAState->paGMR[i];
5724
5725	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5726	AssertLogRelRCReturn(rc, rc);
5727
5728	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5729	{
5730	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5731	AssertLogRelRCReturn(rc, rc);
5732	}
5733	}
5734
5735	/*
5736	* Must save some state (3D in particular) in the FIFO thread.
5737	*/
5738	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5739	AssertLogRelRCReturn(rc, rc);
5740
5741	return VINF_SUCCESS;
5742	}
5743
5744	/**
5745	* Destructor for PVMSVGAR3STATE structure.
5746	*
5747	* @param pThis The VGA instance.
5748	* @param pSVGAState Pointer to the structure. It is not deallocated.
5749	*/
5750	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5751	{
5752	#ifndef VMSVGA_USE_EMT_HALT_CODE
5753	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5754	{
5755	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5756	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5757	}
5758	#endif
5759
5760	if (pSVGAState->Cursor.fActive)
5761	{
5762	RTMemFree(pSVGAState->Cursor.pData);
5763	pSVGAState->Cursor.pData = NULL;
5764	pSVGAState->Cursor.fActive = false;
5765	}
5766
5767	if (pSVGAState->paGMR)
5768	{
5769	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5770	if (pSVGAState->paGMR[i].paDesc)
5771	RTMemFree(pSVGAState->paGMR[i].paDesc);
5772
5773	RTMemFree(pSVGAState->paGMR);
5774	pSVGAState->paGMR = NULL;
5775	}
5776	}
5777
5778	/**
5779	* Constructor for PVMSVGAR3STATE structure.
5780	*
5781	* @returns VBox status code.
5782	* @param pThis The VGA instance.
5783	* @param pSVGAState Pointer to the structure. It is already allocated.
5784	*/
5785	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5786	{
5787	int rc = VINF_SUCCESS;
5788	RT_ZERO(*pSVGAState);
5789
5790	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5791	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5792
5793	#ifndef VMSVGA_USE_EMT_HALT_CODE
5794	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5795	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5796	AssertRCReturn(rc, rc);
5797	#endif
5798
5799	return rc;
5800	}
5801
5802	/**
5803	* Resets the SVGA hardware state
5804	*
5805	* @returns VBox status code.
5806	* @param pDevIns The device instance.
5807	*/
5808	int vmsvgaReset(PPDMDEVINS pDevIns)
5809	{
5810	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5811	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5812
5813	/* Reset before init? */
5814	if (!pSVGAState)
5815	return VINF_SUCCESS;
5816
5817	Log(("vmsvgaReset\n"));
5818
5819	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5820	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5821	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5822
5823	/* Reset other stuff. */
5824	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5825	RT_ZERO(pThis->svga.au32ScratchRegion);
5826
5827	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5828	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5829
5830	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5831
5832	/* Register caps. */
5833	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5834	# ifdef VBOX_WITH_VMSVGA3D
5835	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5836	# endif
5837
5838	/* Setup FIFO capabilities. */
5839	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5840
5841	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5842	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5843
5844	/* VRAM tracking is enabled by default during bootup. */
5845	pThis->svga.fVRAMTracking = true;
5846	pThis->svga.fEnabled = false;
5847
5848	/* Invalidate current settings. */
5849	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5850	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5851	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5852	pThis->svga.cbScanline = 0;
5853
5854	return rc;
5855	}
5856
5857	/**
5858	* Cleans up the SVGA hardware state
5859	*
5860	* @returns VBox status code.
5861	* @param pDevIns The device instance.
5862	*/
5863	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5864	{
5865	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5866
5867	/*
5868	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5869	*/
5870	if (pThis->svga.pFIFOIOThread)
5871	{
5872	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5873	AssertLogRelRC(rc);
5874
5875	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5876	AssertLogRelRC(rc);
5877	pThis->svga.pFIFOIOThread = NULL;
5878	}
5879
5880	/*
5881	* Destroy the special SVGA state.
5882	*/
5883	if (pThis->svga.pSvgaR3State)
5884	{
5885	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5886
5887	RTMemFree(pThis->svga.pSvgaR3State);
5888	pThis->svga.pSvgaR3State = NULL;
5889	}
5890
5891	/*
5892	* Free our resources residing in the VGA state.
5893	*/
5894	if (pThis->svga.pbVgaFrameBufferR3)
5895	{
5896	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5897	pThis->svga.pbVgaFrameBufferR3 = NULL;
5898	}
5899	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5900	{
5901	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5902	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5903	}
5904	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5905	{
5906	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5907	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5908	}
5909
5910	return VINF_SUCCESS;
5911	}
5912
5913	/**
5914	* Initialize the SVGA hardware state
5915	*
5916	* @returns VBox status code.
5917	* @param pDevIns The device instance.
5918	*/
5919	int vmsvgaInit(PPDMDEVINS pDevIns)
5920	{
5921	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5922	PVMSVGAR3STATE pSVGAState;
5923	PVM pVM = PDMDevHlpGetVM(pDevIns);
5924	int rc;
5925
5926	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5927	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5928
5929	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5930
5931	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5932	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5933	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5934
5935	/* Create event semaphore. */
5936	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5937
5938	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5939	if (RT_FAILURE(rc))
5940	{
5941	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5942	return rc;
5943	}
5944
5945	/* Create event semaphore. */
5946	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5947	if (RT_FAILURE(rc))
5948	{
5949	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5950	return rc;
5951	}
5952
5953	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5954	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5955
5956	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5957	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5958
5959	pSVGAState = pThis->svga.pSvgaR3State;
5960
5961	/* Register caps. */
5962	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5963	# ifdef VBOX_WITH_VMSVGA3D
5964	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5965	# endif
5966
5967	/* Setup FIFO capabilities. */
5968	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5969
5970	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5971	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5972
5973	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5974	# ifdef VBOX_WITH_VMSVGA3D
5975	if (pThis->svga.f3DEnabled)
5976	{
5977	rc = vmsvga3dInit(pThis);
5978	if (RT_FAILURE(rc))
5979	{
5980	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5981	pThis->svga.f3DEnabled = false;
5982	}
5983	}
5984	# endif
5985	/* VRAM tracking is enabled by default during bootup. */
5986	pThis->svga.fVRAMTracking = true;
5987
5988	/* Invalidate current settings. */
5989	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5990	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5991	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5992	pThis->svga.cbScanline = 0;
5993
5994	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5995	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5996	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5997	{
5998	pThis->svga.u32MaxWidth -= 256;
5999	pThis->svga.u32MaxHeight -= 256;
6000	}
6001	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6002
6003	# ifdef DEBUG_GMR_ACCESS
6004	/* Register the GMR access handler type. */
6005	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6006	vmsvgaR3GMRAccessHandler,
6007	NULL, NULL, NULL,
6008	NULL, NULL, NULL,
6009	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6010	AssertRCReturn(rc, rc);
6011	# endif
6012
6013	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6014	/* Register the FIFO access handler type. In addition to
6015	debugging FIFO access, this is also used to facilitate
6016	extended fifo thread sleeps. */
6017	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6018	# ifdef DEBUG_FIFO_ACCESS
6019	PGMPHYSHANDLERKIND_ALL,
6020	# else
6021	PGMPHYSHANDLERKIND_WRITE,
6022	# endif
6023	vmsvgaR3FIFOAccessHandler,
6024	NULL, NULL, NULL,
6025	NULL, NULL, NULL,
6026	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6027	AssertRCReturn(rc, rc);
6028	# endif
6029
6030	/* Create the async IO thread. */
6031	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6032	RTTHREADTYPE_IO, "VMSVGA FIFO");
6033	if (RT_FAILURE(rc))
6034	{
6035	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6036	return rc;
6037	}
6038
6039	/*
6040	* Statistics.
6041	*/
6042	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6043	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6044	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6045	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6046	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6047	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6048	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6049	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6050	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6051	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6052	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6053	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6054	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6055	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6056	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6057	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6058	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6059	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6060	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6061	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6062	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6063	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6064	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6065	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6066	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6067	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6068	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6069	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6070	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6071	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6072	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6073	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6074	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6075	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6076	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6077	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6078	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6079	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6080	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6081	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6082	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6083	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6084	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6085	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6086	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6087	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6088	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6089	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6090	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6091	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6092	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6093	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6094	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6095	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6096	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6097	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6098
6099	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6100	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6101	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6102	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6103	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6104	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6105	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6106	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6107	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6108	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6109	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6110	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6111	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6112	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6113	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6114	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6115	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6116	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6117	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6118	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6119	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6120	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6121	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6122	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6123	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6124	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6125	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6126	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6127	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6128	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6129	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6130	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6131
6132	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6133	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6134	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6135	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6136	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6137	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6138	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6139	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6140	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6141	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6142	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6143	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6144	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6145	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6146	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6147	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6148	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6149	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6150	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6151	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6152	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6153	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6154	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6155	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6156	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6157	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6158	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6159	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6160	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6161	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6162	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6163	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6164	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6165	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6166	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6167	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6168	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6169	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6170	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6171	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6172	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6173	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6174	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6175	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6176	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6177	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6178	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6179	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6180	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6181
6182	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6183	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6184	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6185	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6186	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6187	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6188	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6189	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6190	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6191	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6192	# endif
6193	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6194	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6195	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6196	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6197	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6198
6199	/*
6200	* Info handlers.
6201	*/
6202	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6203	# ifdef VBOX_WITH_VMSVGA3D
6204	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6205	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6206	"VMSVGA 3d surface details. "
6207	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6208	vmsvgaR3Info3dSurface);
6209	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6210	"VMSVGA 3d surface details and bitmap: "
6211	"sid[>dir]",
6212	vmsvgaR3Info3dSurfaceBmp);
6213	# endif
6214
6215	return VINF_SUCCESS;
6216	}
6217
6218	# ifdef VBOX_WITH_VMSVGA3D
6219	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6220	static const char * const g_apszVmSvgaDevCapNames[] =
6221	{
6222	"x3D", /* = 0 */
6223	"xMAX_LIGHTS",
6224	"xMAX_TEXTURES",
6225	"xMAX_CLIP_PLANES",
6226	"xVERTEX_SHADER_VERSION",
6227	"xVERTEX_SHADER",
6228	"xFRAGMENT_SHADER_VERSION",
6229	"xFRAGMENT_SHADER",
6230	"xMAX_RENDER_TARGETS",
6231	"xS23E8_TEXTURES",
6232	"xS10E5_TEXTURES",
6233	"xMAX_FIXED_VERTEXBLEND",
6234	"xD16_BUFFER_FORMAT",
6235	"xD24S8_BUFFER_FORMAT",
6236	"xD24X8_BUFFER_FORMAT",
6237	"xQUERY_TYPES",
6238	"xTEXTURE_GRADIENT_SAMPLING",
6239	"rMAX_POINT_SIZE",
6240	"xMAX_SHADER_TEXTURES",
6241	"xMAX_TEXTURE_WIDTH",
6242	"xMAX_TEXTURE_HEIGHT",
6243	"xMAX_VOLUME_EXTENT",
6244	"xMAX_TEXTURE_REPEAT",
6245	"xMAX_TEXTURE_ASPECT_RATIO",
6246	"xMAX_TEXTURE_ANISOTROPY",
6247	"xMAX_PRIMITIVE_COUNT",
6248	"xMAX_VERTEX_INDEX",
6249	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6250	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6251	"xMAX_VERTEX_SHADER_TEMPS",
6252	"xMAX_FRAGMENT_SHADER_TEMPS",
6253	"xTEXTURE_OPS",
6254	"xSURFACEFMT_X8R8G8B8",
6255	"xSURFACEFMT_A8R8G8B8",
6256	"xSURFACEFMT_A2R10G10B10",
6257	"xSURFACEFMT_X1R5G5B5",
6258	"xSURFACEFMT_A1R5G5B5",
6259	"xSURFACEFMT_A4R4G4B4",
6260	"xSURFACEFMT_R5G6B5",
6261	"xSURFACEFMT_LUMINANCE16",
6262	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6263	"xSURFACEFMT_ALPHA8",
6264	"xSURFACEFMT_LUMINANCE8",
6265	"xSURFACEFMT_Z_D16",
6266	"xSURFACEFMT_Z_D24S8",
6267	"xSURFACEFMT_Z_D24X8",
6268	"xSURFACEFMT_DXT1",
6269	"xSURFACEFMT_DXT2",
6270	"xSURFACEFMT_DXT3",
6271	"xSURFACEFMT_DXT4",
6272	"xSURFACEFMT_DXT5",
6273	"xSURFACEFMT_BUMPX8L8V8U8",
6274	"xSURFACEFMT_A2W10V10U10",
6275	"xSURFACEFMT_BUMPU8V8",
6276	"xSURFACEFMT_Q8W8V8U8",
6277	"xSURFACEFMT_CxV8U8",
6278	"xSURFACEFMT_R_S10E5",
6279	"xSURFACEFMT_R_S23E8",
6280	"xSURFACEFMT_RG_S10E5",
6281	"xSURFACEFMT_RG_S23E8",
6282	"xSURFACEFMT_ARGB_S10E5",
6283	"xSURFACEFMT_ARGB_S23E8",
6284	"xMISSING62",
6285	"xMAX_VERTEX_SHADER_TEXTURES",
6286	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6287	"xSURFACEFMT_V16U16",
6288	"xSURFACEFMT_G16R16",
6289	"xSURFACEFMT_A16B16G16R16",
6290	"xSURFACEFMT_UYVY",
6291	"xSURFACEFMT_YUY2",
6292	"xMULTISAMPLE_NONMASKABLESAMPLES",
6293	"xMULTISAMPLE_MASKABLESAMPLES",
6294	"xALPHATOCOVERAGE",
6295	"xSUPERSAMPLE",
6296	"xAUTOGENMIPMAPS",
6297	"xSURFACEFMT_NV12",
6298	"xSURFACEFMT_AYUV",
6299	"xMAX_CONTEXT_IDS",
6300	"xMAX_SURFACE_IDS",
6301	"xSURFACEFMT_Z_DF16",
6302	"xSURFACEFMT_Z_DF24",
6303	"xSURFACEFMT_Z_D24S8_INT",
6304	"xSURFACEFMT_BC4_UNORM",
6305	"xSURFACEFMT_BC5_UNORM", /* 83 */
6306	};
6307	# endif
6308
6309
6310	/**
6311	* Power On notification.
6312	*
6313	* @returns VBox status code.
6314	* @param pDevIns The device instance data.
6315	*
6316	* @remarks Caller enters the device critical section.
6317	*/
6318	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6319	{
6320	# ifdef VBOX_WITH_VMSVGA3D
6321	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6322	if (pThis->svga.f3DEnabled)
6323	{
6324	int rc = vmsvga3dPowerOn(pThis);
6325
6326	if (RT_SUCCESS(rc))
6327	{
6328	bool fSavedBuffering = RTLogRelSetBuffering(true);
6329	SVGA3dCapsRecord *pCaps;
6330	SVGA3dCapPair *pData;
6331	uint32_t idxCap = 0;
6332
6333	/* 3d hardware version; latest and greatest */
6334	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6335	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6336
6337	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6338	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6339	pData = (SVGA3dCapPair *)&pCaps->data;
6340
6341	/* Fill out all 3d capabilities. */
6342	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6343	{
6344	uint32_t val = 0;
6345
6346	rc = vmsvga3dQueryCaps(pThis, i, &val);
6347	if (RT_SUCCESS(rc))
6348	{
6349	pData[idxCap][0] = i;
6350	pData[idxCap][1] = val;
6351	idxCap++;
6352	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6353	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6354	else
6355	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6356	&g_apszVmSvgaDevCapNames[i][1]));
6357	}
6358	else
6359	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6360	}
6361	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6362	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6363
6364	/* Mark end of record array. */
6365	pCaps->header.length = 0;
6366
6367	RTLogRelSetBuffering(fSavedBuffering);
6368	}
6369	}
6370	# else /* !VBOX_WITH_VMSVGA3D */
6371	RT_NOREF(pDevIns);
6372	# endif /* !VBOX_WITH_VMSVGA3D */
6373	}
6374
6375	#endif /* IN_RING3 */
6376

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 77918

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