DevVGA-SVGA.cpp@ 82254

Last change on this file since 82254 was 82242, checked in by vboxsync, 5 years ago
Devices/Graphics: release statistics for SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN
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1	/* $Id: DevVGA-SVGA.cpp 82242 2019-11-27 13:23:01Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
256	STAMCOUNTER StatR3CmdDefineGmr2;
257	STAMCOUNTER StatR3CmdDefineGmr2Free;
258	STAMCOUNTER StatR3CmdDefineGmr2Modify;
259	STAMCOUNTER StatR3CmdRemapGmr2;
260	STAMCOUNTER StatR3CmdRemapGmr2Modify;
261	STAMCOUNTER StatR3CmdInvalidCmd;
262	STAMCOUNTER StatR3CmdFence;
263	STAMCOUNTER StatR3CmdUpdate;
264	STAMCOUNTER StatR3CmdUpdateVerbose;
265	STAMCOUNTER StatR3CmdDefineCursor;
266	STAMCOUNTER StatR3CmdDefineAlphaCursor;
267	STAMCOUNTER StatR3CmdEscape;
268	STAMCOUNTER StatR3CmdDefineScreen;
269	STAMCOUNTER StatR3CmdDestroyScreen;
270	STAMCOUNTER StatR3CmdDefineGmrFb;
271	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
272	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
273	STAMCOUNTER StatR3CmdAnnotationFill;
274	STAMCOUNTER StatR3CmdAnnotationCopy;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
276	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
277	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
278	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
279	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
280	STAMCOUNTER StatR3Cmd3dSurfaceDma;
281	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
282	STAMCOUNTER StatR3Cmd3dContextDefine;
283	STAMCOUNTER StatR3Cmd3dContextDestroy;
284	STAMCOUNTER StatR3Cmd3dSetTransform;
285	STAMCOUNTER StatR3Cmd3dSetZRange;
286	STAMCOUNTER StatR3Cmd3dSetRenderState;
287	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
288	STAMCOUNTER StatR3Cmd3dSetTextureState;
289	STAMCOUNTER StatR3Cmd3dSetMaterial;
290	STAMCOUNTER StatR3Cmd3dSetLightData;
291	STAMCOUNTER StatR3Cmd3dSetLightEnable;
292	STAMCOUNTER StatR3Cmd3dSetViewPort;
293	STAMCOUNTER StatR3Cmd3dSetClipPlane;
294	STAMCOUNTER StatR3Cmd3dClear;
295	STAMCOUNTER StatR3Cmd3dPresent;
296	STAMCOUNTER StatR3Cmd3dPresentReadBack;
297	STAMCOUNTER StatR3Cmd3dShaderDefine;
298	STAMCOUNTER StatR3Cmd3dShaderDestroy;
299	STAMCOUNTER StatR3Cmd3dSetShader;
300	STAMCOUNTER StatR3Cmd3dSetShaderConst;
301	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
302	STAMCOUNTER StatR3Cmd3dSetScissorRect;
303	STAMCOUNTER StatR3Cmd3dBeginQuery;
304	STAMCOUNTER StatR3Cmd3dEndQuery;
305	STAMCOUNTER StatR3Cmd3dWaitForQuery;
306	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
307	STAMCOUNTER StatR3Cmd3dActivateSurface;
308	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
309
310	STAMCOUNTER StatR3RegConfigDoneWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWr;
312	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
313	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
314
315	STAMCOUNTER StatFifoCommands;
316	STAMCOUNTER StatFifoErrors;
317	STAMCOUNTER StatFifoUnkCmds;
318	STAMCOUNTER StatFifoTodoTimeout;
319	STAMCOUNTER StatFifoTodoWoken;
320	STAMPROFILE StatFifoStalls;
321	STAMPROFILE StatFifoExtendedSleep;
322	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
323	STAMCOUNTER StatFifoAccessHandler;
324	# endif
325	STAMCOUNTER StatFifoCursorFetchAgain;
326	STAMCOUNTER StatFifoCursorNoChange;
327	STAMCOUNTER StatFifoCursorPosition;
328	STAMCOUNTER StatFifoCursorVisiblity;
329	STAMCOUNTER StatFifoWatchdogWakeUps;
330	} VMSVGAR3STATE, *PVMSVGAR3STATE;
331	#endif /* IN_RING3 */
332
333
334	/*********************************************************************************************************************************
335	* Internal Functions *
336	*********************************************************************************************************************************/
337	#ifdef IN_RING3
338	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
339	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
340	# endif
341	# ifdef DEBUG_GMR_ACCESS
342	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
343	# endif
344	#endif
345
346
347	/*********************************************************************************************************************************
348	* Global Variables *
349	*********************************************************************************************************************************/
350	#ifdef IN_RING3
351
352	/**
353	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
354	*/
355	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
356	{
357	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
358	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
359	SSMFIELD_ENTRY_TERM()
360	};
361
362	/**
363	* SSM descriptor table for the GMR structure.
364	*/
365	static SSMFIELD const g_aGMRFields[] =
366	{
367	SSMFIELD_ENTRY( GMR, cMaxPages),
368	SSMFIELD_ENTRY( GMR, cbTotal),
369	SSMFIELD_ENTRY( GMR, numDescriptors),
370	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
371	SSMFIELD_ENTRY_TERM()
372	};
373
374	/**
375	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
376	*/
377	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
378	{
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
390	SSMFIELD_ENTRY_TERM()
391	};
392
393	/**
394	* SSM descriptor table for the VMSVGAR3STATE structure.
395	*/
396	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
397	{
398	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
406	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
409	#ifdef VMSVGA_USE_EMT_HALT_CODE
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
411	#else
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
413	#endif
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
472
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
477
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
485	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
487	# endif
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
492
493	SSMFIELD_ENTRY_TERM()
494	};
495
496	/**
497	* SSM descriptor table for the VGAState.svga structure.
498	*/
499	static SSMFIELD const g_aVGAStateSVGAFields[] =
500	{
501	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
504	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
505	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
506	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
507	SSMFIELD_ENTRY( VMSVGAState, fBusy),
508	SSMFIELD_ENTRY( VMSVGAState, fTraces),
509	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
510	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
511	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
512	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
513	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
514	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
515	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
516	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
517	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
519	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
521	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
522	SSMFIELD_ENTRY( VMSVGAState, uWidth),
523	SSMFIELD_ENTRY( VMSVGAState, uHeight),
524	SSMFIELD_ENTRY( VMSVGAState, uBpp),
525	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
526	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
527	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
528	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
529	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
530	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
531	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
532	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
533	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
534	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
535	SSMFIELD_ENTRY_TERM()
536	};
537	#endif /* IN_RING3 */
538
539
540	/*********************************************************************************************************************************
541	* Internal Functions *
542	*********************************************************************************************************************************/
543	#ifdef IN_RING3
544	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
545	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
546	uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
548	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
549	#endif /* IN_RING3 */
550
551
552
553	#ifdef IN_RING3
554	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
555	{
556	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
557	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
558	&& pSVGAState
559	&& pSVGAState->aScreens[idScreen].fDefined)
560	{
561	return &pSVGAState->aScreens[idScreen];
562	}
563	return NULL;
564	}
565	#endif /* IN_RING3 */
566
567	#ifdef LOG_ENABLED
568
569	/**
570	* Index register string name lookup
571	*
572	* @returns Index register string or "UNKNOWN"
573	* @param pThis The shared VGA/VMSVGA state.
574	* @param idxReg The index register.
575	*/
576	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
577	{
578	switch (idxReg)
579	{
580	case SVGA_REG_ID: return "SVGA_REG_ID";
581	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
582	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
583	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
584	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
585	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
586	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
587	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
588	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
589	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
590	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
591	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
592	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
593	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
594	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
595	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
596	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
597	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
598	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
599	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
600	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
601	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
602	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
603	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
604	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
605	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
606	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
607	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
608	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
609	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
610	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
611	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
612	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
613	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
614	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
615	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
616	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
617	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
618	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
619	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
620	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
621	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
622	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
623	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
624	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
625	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
626	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
627	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
628	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
629	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
630
631	default:
632	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
633	return "SVGA_SCRATCH_BASE reg";
634	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
635	return "SVGA_PALETTE_BASE reg";
636	return "UNKNOWN";
637	}
638	}
639
640	#ifdef IN_RING3
641	/**
642	* FIFO command name lookup
643	*
644	* @returns FIFO command string or "UNKNOWN"
645	* @param u32Cmd FIFO command
646	*/
647	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
648	{
649	switch (u32Cmd)
650	{
651	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
652	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
653	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
654	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
655	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
656	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
657	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
658	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
659	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
660	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
661	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
662	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
663	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
664	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
665	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
666	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
667	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
668	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
669	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
670	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
671	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
672	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
673	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
674	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
675	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
676	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
677	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
678	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
679	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
680	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
681	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
682	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
683	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
684	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
685	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
686	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
687	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
688	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
689	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
690	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
691	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
692	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
693	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
694	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
695	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
696	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
697	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
698	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
699	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
700	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
701	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
702	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
703	default: return "UNKNOWN";
704	}
705	}
706	# endif /* IN_RING3 */
707
708	#endif /* LOG_ENABLED */
709
710	#ifdef IN_RING3
711	/**
712	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
713	*/
714	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
715	{
716	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
717	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
718
719	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
720	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
721
722	/** @todo Test how it interacts with multiple screen objects. */
723	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
724	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
725	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
726
727	if (x < uWidth)
728	{
729	pThis->svga.viewport.x = x;
730	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
731	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
732	}
733	else
734	{
735	pThis->svga.viewport.x = uWidth;
736	pThis->svga.viewport.cx = 0;
737	pThis->svga.viewport.xRight = uWidth;
738	}
739	if (y < uHeight)
740	{
741	pThis->svga.viewport.y = y;
742	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
743	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
744	pThis->svga.viewport.yHighWC = uHeight - y;
745	}
746	else
747	{
748	pThis->svga.viewport.y = uHeight;
749	pThis->svga.viewport.cy = 0;
750	pThis->svga.viewport.yLowWC = 0;
751	pThis->svga.viewport.yHighWC = 0;
752	}
753
754	# ifdef VBOX_WITH_VMSVGA3D
755	/*
756	* Now inform the 3D backend.
757	*/
758	if (pThis->svga.f3DEnabled)
759	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
760	# else
761	RT_NOREF(OldViewport);
762	# endif
763	}
764	#endif /* IN_RING3 */
765
766	/**
767	* Read port register
768	*
769	* @returns VBox status code.
770	* @param pDevIns The device instance.
771	* @param pThis The shared VGA/VMSVGA state.
772	* @param pu32 Where to store the read value
773	*/
774	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
775	{
776	#ifdef IN_RING3
777	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
778	#endif
779	int rc = VINF_SUCCESS;
780	*pu32 = 0;
781
782	/* Rough index register validation. */
783	uint32_t idxReg = pThis->svga.u32IndexReg;
784	#if !defined(IN_RING3) && defined(VBOX_STRICT)
785	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
786	VINF_IOM_R3_IOPORT_READ);
787	#else
788	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
789	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
790	VINF_SUCCESS);
791	#endif
792	RT_UNTRUSTED_VALIDATED_FENCE();
793
794	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
795	if ( idxReg >= SVGA_REG_CAPABILITIES
796	&& pThis->svga.u32SVGAId == SVGA_ID_0)
797	{
798	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
799	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
800	}
801
802	switch (idxReg)
803	{
804	case SVGA_REG_ID:
805	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
806	*pu32 = pThis->svga.u32SVGAId;
807	break;
808
809	case SVGA_REG_ENABLE:
810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
811	*pu32 = pThis->svga.fEnabled;
812	break;
813
814	case SVGA_REG_WIDTH:
815	{
816	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
817	if ( pThis->svga.fEnabled
818	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
819	*pu32 = pThis->svga.uWidth;
820	else
821	{
822	#ifndef IN_RING3
823	rc = VINF_IOM_R3_IOPORT_READ;
824	#else
825	*pu32 = pThisCC->pDrv->cx;
826	#endif
827	}
828	break;
829	}
830
831	case SVGA_REG_HEIGHT:
832	{
833	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
834	if ( pThis->svga.fEnabled
835	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
836	*pu32 = pThis->svga.uHeight;
837	else
838	{
839	#ifndef IN_RING3
840	rc = VINF_IOM_R3_IOPORT_READ;
841	#else
842	*pu32 = pThisCC->pDrv->cy;
843	#endif
844	}
845	break;
846	}
847
848	case SVGA_REG_MAX_WIDTH:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
850	*pu32 = pThis->svga.u32MaxWidth;
851	break;
852
853	case SVGA_REG_MAX_HEIGHT:
854	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
855	*pu32 = pThis->svga.u32MaxHeight;
856	break;
857
858	case SVGA_REG_DEPTH:
859	/* This returns the color depth of the current mode. */
860	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
861	switch (pThis->svga.uBpp)
862	{
863	case 15:
864	case 16:
865	case 24:
866	*pu32 = pThis->svga.uBpp;
867	break;
868
869	default:
870	case 32:
871	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
872	break;
873	}
874	break;
875
876	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
877	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
878	if ( pThis->svga.fEnabled
879	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
880	*pu32 = pThis->svga.uBpp;
881	else
882	{
883	#ifndef IN_RING3
884	rc = VINF_IOM_R3_IOPORT_READ;
885	#else
886	*pu32 = pThisCC->pDrv->cBits;
887	#endif
888	}
889	break;
890
891	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
893	if ( pThis->svga.fEnabled
894	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
895	*pu32 = (pThis->svga.uBpp + 7) & ~7;
896	else
897	{
898	#ifndef IN_RING3
899	rc = VINF_IOM_R3_IOPORT_READ;
900	#else
901	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
902	#endif
903	}
904	break;
905
906	case SVGA_REG_PSEUDOCOLOR:
907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
908	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
909	break;
910
911	case SVGA_REG_RED_MASK:
912	case SVGA_REG_GREEN_MASK:
913	case SVGA_REG_BLUE_MASK:
914	{
915	uint32_t uBpp;
916
917	if ( pThis->svga.fEnabled
918	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
919	{
920	uBpp = pThis->svga.uBpp;
921	}
922	else
923	{
924	#ifndef IN_RING3
925	rc = VINF_IOM_R3_IOPORT_READ;
926	break;
927	#else
928	uBpp = pThisCC->pDrv->cBits;
929	#endif
930	}
931	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
932	switch (uBpp)
933	{
934	case 8:
935	u32RedMask = 0x07;
936	u32GreenMask = 0x38;
937	u32BlueMask = 0xc0;
938	break;
939
940	case 15:
941	u32RedMask = 0x0000001f;
942	u32GreenMask = 0x000003e0;
943	u32BlueMask = 0x00007c00;
944	break;
945
946	case 16:
947	u32RedMask = 0x0000001f;
948	u32GreenMask = 0x000007e0;
949	u32BlueMask = 0x0000f800;
950	break;
951
952	case 24:
953	case 32:
954	default:
955	u32RedMask = 0x00ff0000;
956	u32GreenMask = 0x0000ff00;
957	u32BlueMask = 0x000000ff;
958	break;
959	}
960	switch (idxReg)
961	{
962	case SVGA_REG_RED_MASK:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
964	*pu32 = u32RedMask;
965	break;
966
967	case SVGA_REG_GREEN_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
969	*pu32 = u32GreenMask;
970	break;
971
972	case SVGA_REG_BLUE_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
974	*pu32 = u32BlueMask;
975	break;
976	}
977	break;
978	}
979
980	case SVGA_REG_BYTES_PER_LINE:
981	{
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.cbScanline)
985	*pu32 = pThis->svga.cbScanline;
986	else
987	{
988	#ifndef IN_RING3
989	rc = VINF_IOM_R3_IOPORT_READ;
990	#else
991	*pu32 = pThisCC->pDrv->cbScanline;
992	#endif
993	}
994	break;
995	}
996
997	case SVGA_REG_VRAM_SIZE: /* VRAM size */
998	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
999	*pu32 = pThis->vram_size;
1000	break;
1001
1002	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1003	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1004	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1005	*pu32 = pThis->GCPhysVRAM;
1006	break;
1007
1008	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1010	/* Always zero in our case. */
1011	*pu32 = 0;
1012	break;
1013
1014	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1015	{
1016	#ifndef IN_RING3
1017	rc = VINF_IOM_R3_IOPORT_READ;
1018	#else
1019	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1020
1021	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1022	if ( pThis->svga.fEnabled
1023	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1024	{
1025	/* Hardware enabled; return real framebuffer size .*/
1026	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1027	}
1028	else
1029	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1030
1031	pu32 = RT_MIN(pThis->vram_size, pu32);
1032	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1033	#endif
1034	break;
1035	}
1036
1037	case SVGA_REG_CAPABILITIES:
1038	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1039	*pu32 = pThis->svga.u32RegCaps;
1040	break;
1041
1042	case SVGA_REG_MEM_START: /* FIFO start */
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1044	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1045	*pu32 = pThis->svga.GCPhysFIFO;
1046	break;
1047
1048	case SVGA_REG_MEM_SIZE: /* FIFO size */
1049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1050	*pu32 = pThis->svga.cbFIFO;
1051	break;
1052
1053	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1055	*pu32 = pThis->svga.fConfigured;
1056	break;
1057
1058	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1060	*pu32 = 0;
1061	break;
1062
1063	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1065	if (pThis->svga.fBusy)
1066	{
1067	#ifndef IN_RING3
1068	/* Go to ring-3 and halt the CPU. */
1069	rc = VINF_IOM_R3_IOPORT_READ;
1070	RT_NOREF(pDevIns);
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pDevIns);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis The shared VGA state.
1291	* @param pThisCC The ring-3 VGA state.
1292	*/
1293	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1294	{
1295	int rc;
1296
1297	/* Always do changemode on FIFO thread. */
1298	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1299
1300	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1301
1302	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1303
1304	if (pThis->svga.fGFBRegisters)
1305	{
1306	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1307	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1308	* deletes all screens other than screen #0, and redefines screen
1309	* #0 according to the specified mode. Drivers that use
1310	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1311	*/
1312
1313	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1314	pScreen->fDefined = true;
1315	pScreen->fModified = true;
1316	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1317	pScreen->idScreen = 0;
1318	pScreen->xOrigin = 0;
1319	pScreen->yOrigin = 0;
1320	pScreen->offVRAM = 0;
1321	pScreen->cbPitch = pThis->svga.cbScanline;
1322	pScreen->cWidth = pThis->svga.uWidth;
1323	pScreen->cHeight = pThis->svga.uHeight;
1324	pScreen->cBpp = pThis->svga.uBpp;
1325
1326	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1327	{
1328	/* Delete screen. */
1329	pScreen = &pSVGAState->aScreens[iScreen];
1330	if (pScreen->fDefined)
1331	{
1332	pScreen->fModified = true;
1333	pScreen->fDefined = false;
1334	}
1335	}
1336	}
1337	else
1338	{
1339	/* "If Screen Objects are supported, they can be used to fully
1340	* replace the functionality provided by the framebuffer registers
1341	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1342	*/
1343	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1345	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1346	}
1347
1348	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1349	{
1350	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1351	if (!pScreen->fModified)
1352	continue;
1353
1354	pScreen->fModified = false;
1355
1356	VBVAINFOVIEW view;
1357	RT_ZERO(view);
1358	view.u32ViewIndex = pScreen->idScreen;
1359	// view.u32ViewOffset = 0;
1360	view.u32ViewSize = pThis->vram_size;
1361	view.u32MaxScreenSize = pThis->vram_size;
1362
1363	VBVAINFOSCREEN screen;
1364	RT_ZERO(screen);
1365	screen.u32ViewIndex = pScreen->idScreen;
1366
1367	if (pScreen->fDefined)
1368	{
1369	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1371	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1372	{
1373	Assert(pThis->svga.fGFBRegisters);
1374	continue;
1375	}
1376
1377	screen.i32OriginX = pScreen->xOrigin;
1378	screen.i32OriginY = pScreen->yOrigin;
1379	screen.u32StartOffset = pScreen->offVRAM;
1380	screen.u32LineSize = pScreen->cbPitch;
1381	screen.u32Width = pScreen->cWidth;
1382	screen.u32Height = pScreen->cHeight;
1383	screen.u16BitsPerPixel = pScreen->cBpp;
1384	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1385	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1386	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1387	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1388	}
1389	else
1390	{
1391	/* Screen is destroyed. */
1392	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1393	}
1394
1395	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1396	AssertRC(rc);
1397	}
1398
1399	/* Last stuff. For the VGA device screenshot. */
1400	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1401	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1402	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1403	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1404	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1405
1406	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1407	if ( pThis->svga.viewport.cx == 0
1408	&& pThis->svga.viewport.cy == 0)
1409	{
1410	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1412	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1414	pThis->svga.viewport.yLowWC = 0;
1415	}
1416
1417	return VINF_SUCCESS;
1418	}
1419
1420	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1421	{
1422	VBVACMDHDR cmd;
1423	cmd.x = (int16_t)(pScreen->xOrigin + x);
1424	cmd.y = (int16_t)(pScreen->yOrigin + y);
1425	cmd.w = (uint16_t)w;
1426	cmd.h = (uint16_t)h;
1427
1428	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1429	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1430	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1431	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1432
1433	return VINF_SUCCESS;
1434	}
1435
1436	#endif /* IN_RING3 */
1437	#if defined(IN_RING0) \|\| defined(IN_RING3)
1438
1439	/**
1440	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1441	*
1442	* @param pThis The shared VGA/VMSVGA instance data.
1443	* @param pThisCC The VGA/VMSVGA state for the current context.
1444	* @param fState The busy state.
1445	*/
1446	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1447	{
1448	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1449
1450	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1451	{
1452	/* Race / unfortunately scheduling. Highly unlikly. */
1453	uint32_t cLoops = 64;
1454	do
1455	{
1456	ASMNopPause();
1457	fState = (pThis->svga.fBusy != 0);
1458	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1459	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1460	}
1461	}
1462
1463
1464	/**
1465	* Update the scanline pitch in response to the guest changing mode
1466	* width/bpp.
1467	*
1468	* @param pThis The shared VGA/VMSVGA state.
1469	* @param pThisCC The VGA/VMSVGA state for the current context.
1470	*/
1471	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1472	{
1473	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1474	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1475	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1476	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1477
1478	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1479	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1480	* location but it has a different meaning.
1481	*/
1482	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1483	uFifoPitchLock = 0;
1484
1485	/* Sanitize values. */
1486	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1487	uFifoPitchLock = 0;
1488	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1489	uRegPitchLock = 0;
1490
1491	/* Prefer the register value to the FIFO value.*/
1492	if (uRegPitchLock)
1493	pThis->svga.cbScanline = uRegPitchLock;
1494	else if (uFifoPitchLock)
1495	pThis->svga.cbScanline = uFifoPitchLock;
1496	else
1497	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1498
1499	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1500	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1501	}
1502
1503	#endif /* IN_RING0 \|\| IN_RING3 */
1504
1505
1506	/**
1507	* Write port register
1508	*
1509	* @returns Strict VBox status code.
1510	* @param pDevIns The device instance.
1511	* @param pThis The shared VGA/VMSVGA state.
1512	* @param pThisCC The VGA/VMSVGA state for the current context.
1513	* @param u32 Value to write
1514	*/
1515	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1516	{
1517	#ifdef IN_RING3
1518	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1519	#endif
1520	VBOXSTRICTRC rc = VINF_SUCCESS;
1521	RT_NOREF(pThisCC);
1522
1523	/* Rough index register validation. */
1524	uint32_t idxReg = pThis->svga.u32IndexReg;
1525	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1526	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1527	VINF_IOM_R3_IOPORT_WRITE);
1528	#else
1529	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1530	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1531	VINF_SUCCESS);
1532	#endif
1533	RT_UNTRUSTED_VALIDATED_FENCE();
1534
1535	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1536	if ( idxReg >= SVGA_REG_CAPABILITIES
1537	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1538	{
1539	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1540	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1541	}
1542	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1543	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1544	switch (idxReg)
1545	{
1546	case SVGA_REG_WIDTH:
1547	case SVGA_REG_HEIGHT:
1548	case SVGA_REG_PITCHLOCK:
1549	case SVGA_REG_BITS_PER_PIXEL:
1550	pThis->svga.fGFBRegisters = true;
1551	break;
1552	default:
1553	break;
1554	}
1555
1556	switch (idxReg)
1557	{
1558	case SVGA_REG_ID:
1559	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1560	if ( u32 == SVGA_ID_0
1561	\|\| u32 == SVGA_ID_1
1562	\|\| u32 == SVGA_ID_2)
1563	pThis->svga.u32SVGAId = u32;
1564	else
1565	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1566	break;
1567
1568	case SVGA_REG_ENABLE:
1569	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1570	#ifdef IN_RING3
1571	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1572	&& pThis->svga.fEnabled == false)
1573	{
1574	/* Make a backup copy of the first 512kb in order to save font data etc. */
1575	/** @todo should probably swap here, rather than copy + zero */
1576	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1577	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1578	}
1579
1580	pThis->svga.fEnabled = u32;
1581	if (pThis->svga.fEnabled)
1582	{
1583	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1584	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1585	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1586	{
1587	/* Keep the current mode. */
1588	pThis->svga.uWidth = pThisCC->pDrv->cx;
1589	pThis->svga.uHeight = pThisCC->pDrv->cy;
1590	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1591	}
1592
1593	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1594	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1595	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1596	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1597	# ifdef LOG_ENABLED
1598	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1599	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1600	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1601	# endif
1602
1603	/* Disable or enable dirty page tracking according to the current fTraces value. */
1604	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1605
1606	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1607	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1608	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1609	}
1610	else
1611	{
1612	/* Restore the text mode backup. */
1613	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1614
1615	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1616
1617	/* Enable dirty page tracking again when going into legacy mode. */
1618	vmsvgaR3SetTraces(pDevIns, pThis, true);
1619
1620	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1621	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1622	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1623
1624	/* Clear the pitch lock. */
1625	pThis->svga.u32PitchLock = 0;
1626	}
1627	#else /* !IN_RING3 */
1628	rc = VINF_IOM_R3_IOPORT_WRITE;
1629	#endif /* !IN_RING3 */
1630	break;
1631
1632	case SVGA_REG_WIDTH:
1633	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1634	if (pThis->svga.uWidth != u32)
1635	{
1636	#if defined(IN_RING3) \|\| defined(IN_RING0)
1637	pThis->svga.uWidth = u32;
1638	vmsvgaHCUpdatePitch(pThis, pThisCC);
1639	if (pThis->svga.fEnabled)
1640	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1641	#else
1642	rc = VINF_IOM_R3_IOPORT_WRITE;
1643	#endif
1644	}
1645	/* else: nop */
1646	break;
1647
1648	case SVGA_REG_HEIGHT:
1649	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1650	if (pThis->svga.uHeight != u32)
1651	{
1652	pThis->svga.uHeight = u32;
1653	if (pThis->svga.fEnabled)
1654	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1655	}
1656	/* else: nop */
1657	break;
1658
1659	case SVGA_REG_DEPTH:
1660	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1661	/** @todo read-only?? */
1662	break;
1663
1664	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1665	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1666	if (pThis->svga.uBpp != u32)
1667	{
1668	#if defined(IN_RING3) \|\| defined(IN_RING0)
1669	pThis->svga.uBpp = u32;
1670	vmsvgaHCUpdatePitch(pThis, pThisCC);
1671	if (pThis->svga.fEnabled)
1672	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1673	#else
1674	rc = VINF_IOM_R3_IOPORT_WRITE;
1675	#endif
1676	}
1677	/* else: nop */
1678	break;
1679
1680	case SVGA_REG_PSEUDOCOLOR:
1681	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1682	break;
1683
1684	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1685	#ifdef IN_RING3
1686	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1687	pThis->svga.fConfigured = u32;
1688	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1689	if (!pThis->svga.fConfigured)
1690	pThis->svga.fTraces = true;
1691	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1692	#else
1693	rc = VINF_IOM_R3_IOPORT_WRITE;
1694	#endif
1695	break;
1696
1697	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1698	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1699	if ( pThis->svga.fEnabled
1700	&& pThis->svga.fConfigured)
1701	{
1702	#if defined(IN_RING3) \|\| defined(IN_RING0)
1703	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1704	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1705	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1706	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1707
1708	/* Kick the FIFO thread to start processing commands again. */
1709	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1710	#else
1711	rc = VINF_IOM_R3_IOPORT_WRITE;
1712	#endif
1713	}
1714	/* else nothing to do. */
1715	else
1716	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1717
1718	break;
1719
1720	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1722	break;
1723
1724	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1726	pThis->svga.u32GuestId = u32;
1727	break;
1728
1729	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1730	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1731	pThis->svga.u32PitchLock = u32;
1732	/* Should this also update the FIFO pitch lock? Unclear. */
1733	break;
1734
1735	case SVGA_REG_IRQMASK: /* Interrupt mask */
1736	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1737	pThis->svga.u32IrqMask = u32;
1738
1739	/* Irq pending after the above change? */
1740	if (pThis->svga.u32IrqStatus & u32)
1741	{
1742	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1743	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1744	}
1745	else
1746	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1747	break;
1748
1749	/* Mouse cursor support */
1750	case SVGA_REG_CURSOR_ID:
1751	case SVGA_REG_CURSOR_X:
1752	case SVGA_REG_CURSOR_Y:
1753	case SVGA_REG_CURSOR_ON:
1754	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1755	break;
1756
1757	/* Legacy multi-monitor support */
1758	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1760	break;
1761	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1762	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1763	break;
1764	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1766	break;
1767	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1769	break;
1770	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1772	break;
1773	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1775	break;
1776	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1778	break;
1779	#ifdef VBOX_WITH_VMSVGA3D
1780	/* See "Guest memory regions" below. */
1781	case SVGA_REG_GMR_ID:
1782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1783	pThis->svga.u32CurrentGMRId = u32;
1784	break;
1785
1786	case SVGA_REG_GMR_DESCRIPTOR:
1787	# ifndef IN_RING3
1788	rc = VINF_IOM_R3_IOPORT_WRITE;
1789	break;
1790	# else /* IN_RING3 */
1791	{
1792	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1793
1794	/* Validate current GMR id. */
1795	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1796	AssertBreak(idGMR < pThis->svga.cGMR);
1797	RT_UNTRUSTED_VALIDATED_FENCE();
1798
1799	/* Free the old GMR if present. */
1800	vmsvgaR3GmrFree(pThisCC, idGMR);
1801
1802	/* Just undefine the GMR? */
1803	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1804	if (GCPhys == 0)
1805	{
1806	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1807	break;
1808	}
1809
1810
1811	/* Never cross a page boundary automatically. */
1812	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1813	uint32_t cPagesTotal = 0;
1814	uint32_t iDesc = 0;
1815	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1816	uint32_t cLoops = 0;
1817	RTGCPHYS GCPhysBase = GCPhys;
1818	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1819	{
1820	/* Read descriptor. */
1821	SVGAGuestMemDescriptor desc;
1822	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1823	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1824
1825	if (desc.numPages != 0)
1826	{
1827	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1828	cPagesTotal += desc.numPages;
1829	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1830
1831	if ((iDesc & 15) == 0)
1832	{
1833	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1834	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1835	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1836	}
1837
1838	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1839	paDescs[iDesc++].numPages = desc.numPages;
1840
1841	/* Continue with the next descriptor. */
1842	GCPhys += sizeof(desc);
1843	}
1844	else if (desc.ppn == 0)
1845	break; /* terminator */
1846	else /* Pointer to the next physical page of descriptors. */
1847	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1848
1849	cLoops++;
1850	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1851	}
1852
1853	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1854	if (RT_SUCCESS(rc))
1855	{
1856	/* Commit the GMR. */
1857	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1858	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1859	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1860	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1861	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1862	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1863	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1864	}
1865	else
1866	{
1867	RTMemFree(paDescs);
1868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1869	}
1870	break;
1871	}
1872	# endif /* IN_RING3 */
1873	#endif // VBOX_WITH_VMSVGA3D
1874
1875	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1876	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1877	if (pThis->svga.fTraces == u32)
1878	break; /* nothing to do */
1879
1880	#ifdef IN_RING3
1881	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1882	#else
1883	rc = VINF_IOM_R3_IOPORT_WRITE;
1884	#endif
1885	break;
1886
1887	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1888	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1889	break;
1890
1891	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1893	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1894	break;
1895
1896	case SVGA_REG_FB_START:
1897	case SVGA_REG_MEM_START:
1898	case SVGA_REG_HOST_BITS_PER_PIXEL:
1899	case SVGA_REG_MAX_WIDTH:
1900	case SVGA_REG_MAX_HEIGHT:
1901	case SVGA_REG_VRAM_SIZE:
1902	case SVGA_REG_FB_SIZE:
1903	case SVGA_REG_CAPABILITIES:
1904	case SVGA_REG_MEM_SIZE:
1905	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1906	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1907	case SVGA_REG_BYTES_PER_LINE:
1908	case SVGA_REG_FB_OFFSET:
1909	case SVGA_REG_RED_MASK:
1910	case SVGA_REG_GREEN_MASK:
1911	case SVGA_REG_BLUE_MASK:
1912	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1913	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1914	case SVGA_REG_GMR_MAX_IDS:
1915	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1916	/* Read only - ignore. */
1917	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1918	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1919	break;
1920
1921	default:
1922	{
1923	uint32_t offReg;
1924	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1925	{
1926	RT_UNTRUSTED_VALIDATED_FENCE();
1927	pThis->svga.au32ScratchRegion[offReg] = u32;
1928	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1929	}
1930	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1931	{
1932	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1933	Btw, see rgb_to_pixel32. */
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1935	u32 &= 0xff;
1936	RT_UNTRUSTED_VALIDATED_FENCE();
1937	uint32_t uRgb = pThis->last_palette[offReg / 3];
1938	switch (offReg % 3)
1939	{
1940	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1941	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1942	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1943	}
1944	pThis->last_palette[offReg / 3] = uRgb;
1945	}
1946	else
1947	{
1948	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1949	rc = VINF_IOM_R3_IOPORT_WRITE;
1950	#else
1951	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1952	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1953	#endif
1954	}
1955	break;
1956	}
1957	}
1958	return rc;
1959	}
1960
1961	/**
1962	* @callback_method_impl{FNIOMIOPORTNEWIN}
1963	*/
1964	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1965	{
1966	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1967	RT_NOREF_PV(pvUser);
1968
1969	/* Only dword accesses. */
1970	if (cb == 4)
1971	{
1972	switch (offPort)
1973	{
1974	case SVGA_INDEX_PORT:
1975	*pu32 = pThis->svga.u32IndexReg;
1976	break;
1977
1978	case SVGA_VALUE_PORT:
1979	return vmsvgaReadPort(pDevIns, pThis, pu32);
1980
1981	case SVGA_BIOS_PORT:
1982	Log(("Ignoring BIOS port read\n"));
1983	*pu32 = 0;
1984	break;
1985
1986	case SVGA_IRQSTATUS_PORT:
1987	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1988	*pu32 = pThis->svga.u32IrqStatus;
1989	break;
1990
1991	default:
1992	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1993	*pu32 = UINT32_MAX;
1994	break;
1995	}
1996	}
1997	else
1998	{
1999	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2000	*pu32 = UINT32_MAX;
2001	}
2002	return VINF_SUCCESS;
2003	}
2004
2005	/**
2006	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2007	*/
2008	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2009	{
2010	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2011	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2012	RT_NOREF_PV(pvUser);
2013
2014	/* Only dword accesses. */
2015	if (cb == 4)
2016	switch (offPort)
2017	{
2018	case SVGA_INDEX_PORT:
2019	pThis->svga.u32IndexReg = u32;
2020	break;
2021
2022	case SVGA_VALUE_PORT:
2023	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2024
2025	case SVGA_BIOS_PORT:
2026	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2027	break;
2028
2029	case SVGA_IRQSTATUS_PORT:
2030	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2031	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2032	/* Clear the irq in case all events have been cleared. */
2033	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2034	{
2035	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2036	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2037	}
2038	break;
2039
2040	default:
2041	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2042	break;
2043	}
2044	else
2045	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2046
2047	return VINF_SUCCESS;
2048	}
2049
2050	#ifdef IN_RING3
2051
2052	# ifdef DEBUG_FIFO_ACCESS
2053	/**
2054	* Handle FIFO memory access.
2055	* @returns VBox status code.
2056	* @param pVM VM handle.
2057	* @param pThis The shared VGA/VMSVGA instance data.
2058	* @param GCPhys The access physical address.
2059	* @param fWriteAccess Read or write access
2060	*/
2061	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2062	{
2063	RT_NOREF(pVM);
2064	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2065	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2066
2067	switch (GCPhysOffset >> 2)
2068	{
2069	case SVGA_FIFO_MIN:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_MAX:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_NEXT_CMD:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_STOP:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_CAPABILITIES:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_FLAGS:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_FENCE:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_3D_HWVERSION:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_PITCHLOCK:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_CURSOR_ON:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_CURSOR_X:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_CURSOR_Y:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_CURSOR_COUNT:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_RESERVED:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_CURSOR_SCREEN_ID:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_DEAD:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_HWVERSION_REVISED:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS_LAST:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_GUEST_3D_HWVERSION:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_FENCE_GOAL:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_BUSY:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	default:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	}
2388
2389	return VINF_EM_RAW_EMULATE_INSTR;
2390	}
2391	# endif /* DEBUG_FIFO_ACCESS */
2392
2393	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2394	/**
2395	* HC access handler for the FIFO.
2396	*
2397	* @returns VINF_SUCCESS if the handler have carried out the operation.
2398	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2399	* @param pVM VM Handle.
2400	* @param pVCpu The cross context CPU structure for the calling EMT.
2401	* @param GCPhys The physical address the guest is writing to.
2402	* @param pvPhys The HC mapping of that address.
2403	* @param pvBuf What the guest is reading/writing.
2404	* @param cbBuf How much it's reading/writing.
2405	* @param enmAccessType The access type.
2406	* @param enmOrigin Who is making the access.
2407	* @param pvUser User argument.
2408	*/
2409	static DECLCALLBACK(VBOXSTRICTRC)
2410	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2411	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2412	{
2413	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2414	PVGASTATE pThis = (PVGASTATE)pvUser;
2415	AssertPtr(pThis);
2416
2417	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2418	/*
2419	* Wake up the FIFO thread as it might have work to do now.
2420	*/
2421	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2422	AssertLogRelRC(rc);
2423	# endif
2424
2425	# ifdef DEBUG_FIFO_ACCESS
2426	/*
2427	* When in debug-fifo-access mode, we do not disable the access handler,
2428	* but leave it on as we wish to catch all access.
2429	*/
2430	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2431	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2432	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2433	/*
2434	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2435	*/
2436	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2437	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2438	# endif
2439	if (RT_SUCCESS(rc))
2440	return VINF_PGM_HANDLER_DO_DEFAULT;
2441	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2442	return rc;
2443	}
2444	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2445
2446	#endif /* IN_RING3 */
2447
2448	#ifdef DEBUG_GMR_ACCESS
2449	# ifdef IN_RING3
2450
2451	/**
2452	* HC access handler for the FIFO.
2453	*
2454	* @returns VINF_SUCCESS if the handler have carried out the operation.
2455	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2456	* @param pVM VM Handle.
2457	* @param pVCpu The cross context CPU structure for the calling EMT.
2458	* @param GCPhys The physical address the guest is writing to.
2459	* @param pvPhys The HC mapping of that address.
2460	* @param pvBuf What the guest is reading/writing.
2461	* @param cbBuf How much it's reading/writing.
2462	* @param enmAccessType The access type.
2463	* @param enmOrigin Who is making the access.
2464	* @param pvUser User argument.
2465	*/
2466	static DECLCALLBACK(VBOXSTRICTRC)
2467	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2468	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2469	{
2470	PVGASTATE pThis = (PVGASTATE)pvUser;
2471	Assert(pThis);
2472	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2473	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2474
2475	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2476
2477	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2478	{
2479	PGMR pGMR = &pSVGAState->paGMR[i];
2480
2481	if (pGMR->numDescriptors)
2482	{
2483	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2484	{
2485	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2486	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2487	{
2488	/*
2489	* Turn off the write handler for this particular page and make it R/W.
2490	* Then return telling the caller to restart the guest instruction.
2491	*/
2492	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2493	AssertRC(rc);
2494	return VINF_PGM_HANDLER_DO_DEFAULT;
2495	}
2496	}
2497	}
2498	}
2499
2500	return VINF_PGM_HANDLER_DO_DEFAULT;
2501	}
2502
2503	/** Callback handler for VMR3ReqCallWaitU */
2504	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2505	{
2506	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2507	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2508	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2509	int rc;
2510
2511	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2512	{
2513	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2514	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2515	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2516	AssertRC(rc);
2517	}
2518	return VINF_SUCCESS;
2519	}
2520
2521	/** Callback handler for VMR3ReqCallWaitU */
2522	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2523	{
2524	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2525	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2526	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2527
2528	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2529	{
2530	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2531	AssertRC(rc);
2532	}
2533	return VINF_SUCCESS;
2534	}
2535
2536	/** Callback handler for VMR3ReqCallWaitU */
2537	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2538	{
2539	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2540
2541	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2542	{
2543	PGMR pGMR = &pSVGAState->paGMR[i];
2544
2545	if (pGMR->numDescriptors)
2546	{
2547	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2548	{
2549	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2550	AssertRC(rc);
2551	}
2552	}
2553	}
2554	return VINF_SUCCESS;
2555	}
2556
2557	# endif /* IN_RING3 */
2558	#endif /* DEBUG_GMR_ACCESS */
2559
2560	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2561
2562	#ifdef IN_RING3
2563
2564
2565	/**
2566	* Common worker for changing the pointer shape.
2567	*
2568	* @param pThisCC The VGA/VMSVGA state for ring-3.
2569	* @param pSVGAState The VMSVGA ring-3 instance data.
2570	* @param fAlpha Whether there is alpha or not.
2571	* @param xHot Hotspot x coordinate.
2572	* @param yHot Hotspot y coordinate.
2573	* @param cx Width.
2574	* @param cy Height.
2575	* @param pbData Heap copy of the cursor data. Consumed.
2576	* @param cbData The size of the data.
2577	*/
2578	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2579	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2580	{
2581	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2582	# ifdef LOG_ENABLED
2583	if (LogIs2Enabled())
2584	{
2585	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2586	if (!fAlpha)
2587	{
2588	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2589	for (uint32_t y = 0; y < cy; y++)
2590	{
2591	Log2(("%3u:", y));
2592	uint8_t const pbLine = &pbData[y cbAndLine];
2593	for (uint32_t x = 0; x < cx; x += 8)
2594	{
2595	uint8_t b = pbLine[x / 8];
2596	char szByte[12];
2597	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2598	szByte[1] = b & 0x40 ? '*' : ' ';
2599	szByte[2] = b & 0x20 ? '*' : ' ';
2600	szByte[3] = b & 0x10 ? '*' : ' ';
2601	szByte[4] = b & 0x08 ? '*' : ' ';
2602	szByte[5] = b & 0x04 ? '*' : ' ';
2603	szByte[6] = b & 0x02 ? '*' : ' ';
2604	szByte[7] = b & 0x01 ? '*' : ' ';
2605	szByte[8] = '\0';
2606	Log2(("%s", szByte));
2607	}
2608	Log2(("\n"));
2609	}
2610	}
2611
2612	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2613	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2614	for (uint32_t y = 0; y < cy; y++)
2615	{
2616	Log2(("%3u:", y));
2617	uint32_t const pu32Line = &pu32Xor[y cx];
2618	for (uint32_t x = 0; x < cx; x++)
2619	Log2((" %08x", pu32Line[x]));
2620	Log2(("\n"));
2621	}
2622	}
2623	# endif
2624
2625	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2626	AssertRC(rc);
2627
2628	if (pSVGAState->Cursor.fActive)
2629	RTMemFree(pSVGAState->Cursor.pData);
2630
2631	pSVGAState->Cursor.fActive = true;
2632	pSVGAState->Cursor.xHotspot = xHot;
2633	pSVGAState->Cursor.yHotspot = yHot;
2634	pSVGAState->Cursor.width = cx;
2635	pSVGAState->Cursor.height = cy;
2636	pSVGAState->Cursor.cbData = cbData;
2637	pSVGAState->Cursor.pData = pbData;
2638	}
2639
2640
2641	/**
2642	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2643	*
2644	* @param pThis The shared VGA/VMSVGA state.
2645	* @param pThisCC The VGA/VMSVGA state for ring-3.
2646	* @param pSVGAState The VMSVGA ring-3 instance data.
2647	* @param pCursor The cursor.
2648	* @param pbSrcAndMask The AND mask.
2649	* @param cbSrcAndLine The scanline length of the AND mask.
2650	* @param pbSrcXorMask The XOR mask.
2651	* @param cbSrcXorLine The scanline length of the XOR mask.
2652	*/
2653	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2654	SVGAFifoCmdDefineCursor const *pCursor,
2655	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2656	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2657	{
2658	uint32_t const cx = pCursor->width;
2659	uint32_t const cy = pCursor->height;
2660
2661	/*
2662	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2663	* The AND data uses 8-bit aligned scanlines.
2664	* The XOR data must be starting on a 32-bit boundrary.
2665	*/
2666	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2667	uint32_t cbDstAndMask = cbDstAndLine * cy;
2668	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2669	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2670
2671	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2672	AssertReturnVoid(pbCopy);
2673
2674	/* Convert the AND mask. */
2675	uint8_t *pbDst = pbCopy;
2676	uint8_t const *pbSrc = pbSrcAndMask;
2677	switch (pCursor->andMaskDepth)
2678	{
2679	case 1:
2680	if (cbSrcAndLine == cbDstAndLine)
2681	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2682	else
2683	{
2684	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2685	for (uint32_t y = 0; y < cy; y++)
2686	{
2687	memcpy(pbDst, pbSrc, cbDstAndLine);
2688	pbDst += cbDstAndLine;
2689	pbSrc += cbSrcAndLine;
2690	}
2691	}
2692	break;
2693	/* Should take the XOR mask into account for the multi-bit AND mask. */
2694	case 8:
2695	for (uint32_t y = 0; y < cy; y++)
2696	{
2697	for (uint32_t x = 0; x < cx; )
2698	{
2699	uint8_t bDst = 0;
2700	uint8_t fBit = 1;
2701	do
2702	{
2703	uintptr_t const idxPal = pbSrc[x] * 3;
2704	if ((( pThis->last_palette[idxPal]
2705	\| (pThis->last_palette[idxPal] >> 8)
2706	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2707	bDst \|= fBit;
2708	fBit <<= 1;
2709	x++;
2710	} while (x < cx && (x & 7));
2711	pbDst[(x - 1) / 8] = bDst;
2712	}
2713	pbDst += cbDstAndLine;
2714	pbSrc += cbSrcAndLine;
2715	}
2716	break;
2717	case 15:
2718	for (uint32_t y = 0; y < cy; y++)
2719	{
2720	for (uint32_t x = 0; x < cx; )
2721	{
2722	uint8_t bDst = 0;
2723	uint8_t fBit = 1;
2724	do
2725	{
2726	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2727	bDst \|= fBit;
2728	fBit <<= 1;
2729	x++;
2730	} while (x < cx && (x & 7));
2731	pbDst[(x - 1) / 8] = bDst;
2732	}
2733	pbDst += cbDstAndLine;
2734	pbSrc += cbSrcAndLine;
2735	}
2736	break;
2737	case 16:
2738	for (uint32_t y = 0; y < cy; y++)
2739	{
2740	for (uint32_t x = 0; x < cx; )
2741	{
2742	uint8_t bDst = 0;
2743	uint8_t fBit = 1;
2744	do
2745	{
2746	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2747	bDst \|= fBit;
2748	fBit <<= 1;
2749	x++;
2750	} while (x < cx && (x & 7));
2751	pbDst[(x - 1) / 8] = bDst;
2752	}
2753	pbDst += cbDstAndLine;
2754	pbSrc += cbSrcAndLine;
2755	}
2756	break;
2757	case 24:
2758	for (uint32_t y = 0; y < cy; y++)
2759	{
2760	for (uint32_t x = 0; x < cx; )
2761	{
2762	uint8_t bDst = 0;
2763	uint8_t fBit = 1;
2764	do
2765	{
2766	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2767	bDst \|= fBit;
2768	fBit <<= 1;
2769	x++;
2770	} while (x < cx && (x & 7));
2771	pbDst[(x - 1) / 8] = bDst;
2772	}
2773	pbDst += cbDstAndLine;
2774	pbSrc += cbSrcAndLine;
2775	}
2776	break;
2777	case 32:
2778	for (uint32_t y = 0; y < cy; y++)
2779	{
2780	for (uint32_t x = 0; x < cx; )
2781	{
2782	uint8_t bDst = 0;
2783	uint8_t fBit = 1;
2784	do
2785	{
2786	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2787	bDst \|= fBit;
2788	fBit <<= 1;
2789	x++;
2790	} while (x < cx && (x & 7));
2791	pbDst[(x - 1) / 8] = bDst;
2792	}
2793	pbDst += cbDstAndLine;
2794	pbSrc += cbSrcAndLine;
2795	}
2796	break;
2797	default:
2798	RTMemFree(pbCopy);
2799	AssertFailedReturnVoid();
2800	}
2801
2802	/* Convert the XOR mask. */
2803	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2804	pbSrc = pbSrcXorMask;
2805	switch (pCursor->xorMaskDepth)
2806	{
2807	case 1:
2808	for (uint32_t y = 0; y < cy; y++)
2809	{
2810	for (uint32_t x = 0; x < cx; )
2811	{
2812	/* most significant bit is the left most one. */
2813	uint8_t bSrc = pbSrc[x / 8];
2814	do
2815	{
2816	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2817	bSrc <<= 1;
2818	x++;
2819	} while ((x & 7) && x < cx);
2820	}
2821	pbSrc += cbSrcXorLine;
2822	}
2823	break;
2824	case 8:
2825	for (uint32_t y = 0; y < cy; y++)
2826	{
2827	for (uint32_t x = 0; x < cx; x++)
2828	{
2829	uint32_t u = pThis->last_palette[pbSrc[x]];
2830	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2831	}
2832	pbSrc += cbSrcXorLine;
2833	}
2834	break;
2835	case 15: /* Src: RGB-5-5-5 */
2836	for (uint32_t y = 0; y < cy; y++)
2837	{
2838	for (uint32_t x = 0; x < cx; x++)
2839	{
2840	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2841	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2842	((uValue >> 5) & 0x1f) << 3,
2843	((uValue >> 10) & 0x1f) << 3, 0);
2844	}
2845	pbSrc += cbSrcXorLine;
2846	}
2847	break;
2848	case 16: /* Src: RGB-5-6-5 */
2849	for (uint32_t y = 0; y < cy; y++)
2850	{
2851	for (uint32_t x = 0; x < cx; x++)
2852	{
2853	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2854	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2855	((uValue >> 5) & 0x3f) << 2,
2856	((uValue >> 11) & 0x1f) << 3, 0);
2857	}
2858	pbSrc += cbSrcXorLine;
2859	}
2860	break;
2861	case 24:
2862	for (uint32_t y = 0; y < cy; y++)
2863	{
2864	for (uint32_t x = 0; x < cx; x++)
2865	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2866	pbSrc += cbSrcXorLine;
2867	}
2868	break;
2869	case 32:
2870	for (uint32_t y = 0; y < cy; y++)
2871	{
2872	for (uint32_t x = 0; x < cx; x++)
2873	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2874	pbSrc += cbSrcXorLine;
2875	}
2876	break;
2877	default:
2878	RTMemFree(pbCopy);
2879	AssertFailedReturnVoid();
2880	}
2881
2882	/*
2883	* Pass it to the frontend/whatever.
2884	*/
2885	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2886	}
2887
2888
2889	/**
2890	* Worker for vmsvgaR3FifoThread that handles an external command.
2891	*
2892	* @param pDevIns The device instance.
2893	* @param pThis The shared VGA/VMSVGA instance data.
2894	* @param pThisCC The VGA/VMSVGA state for ring-3.
2895	*/
2896	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2897	{
2898	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2899	switch (pThis->svga.u8FIFOExtCommand)
2900	{
2901	case VMSVGA_FIFO_EXTCMD_RESET:
2902	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2903	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2904	# ifdef VBOX_WITH_VMSVGA3D
2905	if (pThis->svga.f3DEnabled)
2906	{
2907	/* The 3d subsystem must be reset from the fifo thread. */
2908	vmsvga3dReset(pThisCC);
2909	}
2910	# endif
2911	break;
2912
2913	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2914	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2915	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2916	# ifdef VBOX_WITH_VMSVGA3D
2917	if (pThis->svga.f3DEnabled)
2918	{
2919	/* The 3d subsystem must be shut down from the fifo thread. */
2920	vmsvga3dTerminate(pThisCC);
2921	}
2922	# endif
2923	break;
2924
2925	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2926	{
2927	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2928	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2929	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2930	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2931	# ifdef VBOX_WITH_VMSVGA3D
2932	if (pThis->svga.f3DEnabled)
2933	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2934	# endif
2935	break;
2936	}
2937
2938	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2939	{
2940	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2941	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2942	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2943	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2944	# ifdef VBOX_WITH_VMSVGA3D
2945	if (pThis->svga.f3DEnabled)
2946	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2947	# endif
2948	break;
2949	}
2950
2951	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2952	{
2953	# ifdef VBOX_WITH_VMSVGA3D
2954	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
2955	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2956	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
2957	# endif
2958	break;
2959	}
2960
2961
2962	default:
2963	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
2964	break;
2965	}
2966
2967	/*
2968	* Signal the end of the external command.
2969	*/
2970	pThisCC->svga.pvFIFOExtCmdParam = NULL;
2971	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2972	ASMMemoryFence(); /* paranoia^2 */
2973	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
2974	AssertLogRelRC(rc);
2975	}
2976
2977	/**
2978	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2979	* doing a job on the FIFO thread (even when it's officially suspended).
2980	*
2981	* @returns VBox status code (fully asserted).
2982	* @param pDevIns The device instance.
2983	* @param pThis The shared VGA/VMSVGA instance data.
2984	* @param pThisCC The VGA/VMSVGA state for ring-3.
2985	* @param uExtCmd The command to execute on the FIFO thread.
2986	* @param pvParam Pointer to command parameters.
2987	* @param cMsWait The time to wait for the command, given in
2988	* milliseconds.
2989	*/
2990	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
2991	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2992	{
2993	Assert(cMsWait >= RT_MS_1SEC * 5);
2994	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2995	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2996
2997	int rc;
2998	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
2999	PDMTHREADSTATE enmState = pThread->enmState;
3000	if (enmState == PDMTHREADSTATE_SUSPENDED)
3001	{
3002	/*
3003	* The thread is suspended, we have to temporarily wake it up so it can
3004	* perform the task.
3005	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3006	*/
3007	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3008	/* Post the request. */
3009	pThis->svga.fFifoExtCommandWakeup = true;
3010	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3011	pThis->svga.u8FIFOExtCommand = uExtCmd;
3012	ASMMemoryFence(); /* paranoia^3 */
3013
3014	/* Resume the thread. */
3015	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3016	AssertLogRelRC(rc);
3017	if (RT_SUCCESS(rc))
3018	{
3019	/* Wait. Take care in case the semaphore was already posted (same as below). */
3020	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3021	if ( rc == VINF_SUCCESS
3022	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3023	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3024	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3025	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3026
3027	/* suspend the thread */
3028	pThis->svga.fFifoExtCommandWakeup = false;
3029	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3030	AssertLogRelRC(rc2);
3031	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3032	rc = rc2;
3033	}
3034	pThis->svga.fFifoExtCommandWakeup = false;
3035	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3036	}
3037	else if (enmState == PDMTHREADSTATE_RUNNING)
3038	{
3039	/*
3040	* The thread is running, should only happen during reset and vmsvga3dsfc.
3041	* We ASSUME not racing code here, both wrt thread state and ext commands.
3042	*/
3043	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3044	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3045
3046	/* Post the request. */
3047	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3048	pThis->svga.u8FIFOExtCommand = uExtCmd;
3049	ASMMemoryFence(); /* paranoia^2 */
3050	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3051	AssertLogRelRC(rc);
3052
3053	/* Wait. Take care in case the semaphore was already posted (same as above). */
3054	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3055	if ( rc == VINF_SUCCESS
3056	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3057	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3058	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3059	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3060
3061	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3062	}
3063	else
3064	{
3065	/*
3066	* Something is wrong with the thread!
3067	*/
3068	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3069	rc = VERR_INVALID_STATE;
3070	}
3071	return rc;
3072	}
3073
3074
3075	/**
3076	* Marks the FIFO non-busy, notifying any waiting EMTs.
3077	*
3078	* @param pDevIns The device instance.
3079	* @param pThis The shared VGA/VMSVGA instance data.
3080	* @param pThisCC The VGA/VMSVGA state for ring-3.
3081	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3082	* @param offFifoMin The start byte offset of the command FIFO.
3083	*/
3084	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3085	{
3086	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3087	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3088	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3089
3090	/* Wake up any waiting EMTs. */
3091	if (pSVGAState->cBusyDelayedEmts > 0)
3092	{
3093	# ifdef VMSVGA_USE_EMT_HALT_CODE
3094	PVM pVM = PDMDevHlpGetVM(pDevIns);
3095	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3096	if (idCpu != NIL_VMCPUID)
3097	{
3098	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3099	while (idCpu-- > 0)
3100	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3101	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3102	}
3103	# else
3104	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3105	AssertRC(rc2);
3106	# endif
3107	}
3108	}
3109
3110	/**
3111	* Reads (more) payload into the command buffer.
3112	*
3113	* @returns pbBounceBuf on success
3114	* @retval (void *)1 if the thread was requested to stop.
3115	* @retval NULL on FIFO error.
3116	*
3117	* @param cbPayloadReq The number of bytes of payload requested.
3118	* @param pFIFO The FIFO.
3119	* @param offCurrentCmd The FIFO byte offset of the current command.
3120	* @param offFifoMin The start byte offset of the command FIFO.
3121	* @param offFifoMax The end byte offset of the command FIFO.
3122	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3123	* always sufficient size.
3124	* @param pcbAlreadyRead How much payload we've already read into the bounce
3125	* buffer. (We will NEVER re-read anything.)
3126	* @param pThread The calling PDM thread handle.
3127	* @param pThis The shared VGA/VMSVGA instance data.
3128	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3129	* statistics collection.
3130	* @param pDevIns The device instance.
3131	*/
3132	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3133	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3134	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3135	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3136	{
3137	Assert(pbBounceBuf);
3138	Assert(pcbAlreadyRead);
3139	Assert(offFifoMin < offFifoMax);
3140	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3141	Assert(offFifoMax <= pThis->svga.cbFIFO);
3142
3143	/*
3144	* Check if the requested payload size has already been satisfied .
3145	* .
3146	* When called to read more, the caller is responsible for making sure the .
3147	* new command size (cbRequsted) never is smaller than what has already .
3148	* been read.
3149	*/
3150	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3151	if (cbPayloadReq <= cbAlreadyRead)
3152	{
3153	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3154	return pbBounceBuf;
3155	}
3156
3157	/*
3158	* Commands bigger than the fifo buffer are invalid.
3159	*/
3160	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3161	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3162	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3163	NULL);
3164
3165	/*
3166	* Move offCurrentCmd past the command dword.
3167	*/
3168	offCurrentCmd += sizeof(uint32_t);
3169	if (offCurrentCmd >= offFifoMax)
3170	offCurrentCmd = offFifoMin;
3171
3172	/*
3173	* Do we have sufficient payload data available already?
3174	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3175	*/
3176	uint32_t cbAfter, cbBefore;
3177	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3178	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3179	if (offNextCmd >= offCurrentCmd)
3180	{
3181	if (RT_LIKELY(offNextCmd < offFifoMax))
3182	cbAfter = offNextCmd - offCurrentCmd;
3183	else
3184	{
3185	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3186	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3187	offNextCmd, offFifoMin, offFifoMax));
3188	cbAfter = offFifoMax - offCurrentCmd;
3189	}
3190	cbBefore = 0;
3191	}
3192	else
3193	{
3194	cbAfter = offFifoMax - offCurrentCmd;
3195	if (offNextCmd >= offFifoMin)
3196	cbBefore = offNextCmd - offFifoMin;
3197	else
3198	{
3199	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3200	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3201	offNextCmd, offFifoMin, offFifoMax));
3202	cbBefore = 0;
3203	}
3204	}
3205	if (cbAfter + cbBefore < cbPayloadReq)
3206	{
3207	/*
3208	* Insufficient, must wait for it to arrive.
3209	*/
3210	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3211	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3212	for (uint32_t i = 0;; i++)
3213	{
3214	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3215	{
3216	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3217	return (void *)(uintptr_t)1;
3218	}
3219	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3220	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3221
3222	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3223
3224	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3225	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3226	if (offNextCmd >= offCurrentCmd)
3227	{
3228	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3229	cbBefore = 0;
3230	}
3231	else
3232	{
3233	cbAfter = offFifoMax - offCurrentCmd;
3234	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3235	}
3236
3237	if (cbAfter + cbBefore >= cbPayloadReq)
3238	break;
3239	}
3240	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3241	}
3242
3243	/*
3244	* Copy out the memory and update what pcbAlreadyRead points to.
3245	*/
3246	if (cbAfter >= cbPayloadReq)
3247	memcpy(pbBounceBuf + cbAlreadyRead,
3248	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3249	cbPayloadReq - cbAlreadyRead);
3250	else
3251	{
3252	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3253	if (cbAlreadyRead < cbAfter)
3254	{
3255	memcpy(pbBounceBuf + cbAlreadyRead,
3256	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3257	cbAfter - cbAlreadyRead);
3258	cbAlreadyRead = cbAfter;
3259	}
3260	memcpy(pbBounceBuf + cbAlreadyRead,
3261	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3262	cbPayloadReq - cbAlreadyRead);
3263	}
3264	*pcbAlreadyRead = cbPayloadReq;
3265	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3266	return pbBounceBuf;
3267	}
3268
3269
3270	/**
3271	* Sends cursor position and visibility information from the FIFO to the front-end.
3272	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3273	*/
3274	static uint32_t
3275	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3276	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3277	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3278	{
3279	/*
3280	* Check if the cursor update counter has changed and try get a stable
3281	* set of values if it has. This is race-prone, especially consindering
3282	* the screen ID, but little we can do about that.
3283	*/
3284	uint32_t x, y, fVisible, idScreen;
3285	for (uint32_t i = 0; ; i++)
3286	{
3287	x = pFIFO[SVGA_FIFO_CURSOR_X];
3288	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3289	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3290	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3291	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3292	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3293	\|\| i > 3)
3294	break;
3295	if (i == 0)
3296	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3297	ASMNopPause();
3298	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3299	}
3300
3301	/*
3302	* Check if anything has changed, as calling into pDrv is not light-weight.
3303	*/
3304	if ( *pxLast == x
3305	&& *pyLast == y
3306	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3307	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3308	else
3309	{
3310	/*
3311	* Detected changes.
3312	*
3313	* We handle global, not per-screen visibility information by sending
3314	* pfnVBVAMousePointerShape without shape data.
3315	*/
3316	*pxLast = x;
3317	*pyLast = y;
3318	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3319	if (idScreen != SVGA_ID_INVALID)
3320	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3321	else if (*pfLastVisible != fVisible)
3322	{
3323	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3324	*pfLastVisible = fVisible;
3325	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3326	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3327	}
3328	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3329	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3330	}
3331
3332	/*
3333	* Update done. Signal this to the guest.
3334	*/
3335	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3336
3337	return uCursorUpdateCount;
3338	}
3339
3340
3341	/**
3342	* Checks if there is work to be done, either cursor updating or FIFO commands.
3343	*
3344	* @returns true if pending work, false if not.
3345	* @param pFIFO The FIFO to examine.
3346	* @param uLastCursorCount The last cursor update counter value.
3347	*/
3348	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3349	{
3350	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3351	return true;
3352
3353	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3354	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3355	return true;
3356
3357	return false;
3358	}
3359
3360
3361	/**
3362	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3363	*
3364	* @param pDevIns The device instance.
3365	* @param pThis The shared VGA/VMSVGA instance data.
3366	* @param pThisCC The VGA/VMSVGA state for ring-3.
3367	*/
3368	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3369	{
3370	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3371	to recheck it before doing the signalling. */
3372	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3373	AssertReturnVoid(pFIFO);
3374	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3375	&& pThis->svga.fFIFOThreadSleeping)
3376	{
3377	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3378	AssertRC(rc);
3379	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3380	}
3381	}
3382
3383
3384	/*
3385	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3386	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3387	*/
3388	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3389	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3390	*
3391	* Will break out of the switch on failure.
3392	* Will restart and quit the loop if the thread was requested to stop.
3393	*
3394	* @param a_PtrVar Request variable pointer.
3395	* @param a_Type Request typedef (not pointer) for casting.
3396	* @param a_cbPayloadReq How much payload to fetch.
3397	* @remarks Accesses a bunch of variables in the current scope!
3398	*/
3399	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3400	if (1) { \
3401	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3402	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3403	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3404	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3405	} else do {} while (0)
3406	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3407	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3408	* buffer after figuring out the actual command size.
3409	*
3410	* Will break out of the switch on failure.
3411	*
3412	* @param a_PtrVar Request variable pointer.
3413	* @param a_Type Request typedef (not pointer) for casting.
3414	* @param a_cbPayloadReq How much payload to fetch.
3415	* @remarks Accesses a bunch of variables in the current scope!
3416	*/
3417	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3418	if (1) { \
3419	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3420	} else do {} while (0)
3421
3422	/**
3423	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3424	*/
3425	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3426	{
3427	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3428	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3429	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3430	int rc;
3431
3432	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3433	return VINF_SUCCESS;
3434
3435	/*
3436	* Special mode where we only execute an external command and the go back
3437	* to being suspended. Currently, all ext cmds ends up here, with the reset
3438	* one also being eligble for runtime execution further down as well.
3439	*/
3440	if (pThis->svga.fFifoExtCommandWakeup)
3441	{
3442	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3443	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3444	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3445	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3446	else
3447	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3448	return VINF_SUCCESS;
3449	}
3450
3451
3452	/*
3453	* Signal the semaphore to make sure we don't wait for 250ms after a
3454	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3455	*/
3456	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3457
3458	/*
3459	* Allocate a bounce buffer for command we get from the FIFO.
3460	* (All code must return via the end of the function to free this buffer.)
3461	*/
3462	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3463	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3464
3465	/*
3466	* Polling/sleep interval config.
3467	*
3468	* We wait for an a short interval if the guest has recently given us work
3469	* to do, but the interval increases the longer we're kept idle. Once we've
3470	* reached the refresh timer interval, we'll switch to extended waits,
3471	* depending on it or the guest to kick us into action when needed.
3472	*
3473	* Should the refresh time go fishing, we'll just continue increasing the
3474	* sleep length till we reaches the 250 ms max after about 16 seconds.
3475	*/
3476	RTMSINTERVAL const cMsMinSleep = 16;
3477	RTMSINTERVAL const cMsIncSleep = 2;
3478	RTMSINTERVAL const cMsMaxSleep = 250;
3479	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3480	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3481
3482	/*
3483	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3484	*
3485	* Initialize with values that will detect an update from the guest.
3486	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3487	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3488	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3489	*/
3490	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3491	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3492	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3493	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3494	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3495
3496	/*
3497	* The FIFO loop.
3498	*/
3499	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3500	bool fBadOrDisabledFifo = false;
3501	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3502	{
3503	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3504	/*
3505	* Should service the run loop every so often.
3506	*/
3507	if (pThis->svga.f3DEnabled)
3508	vmsvga3dCocoaServiceRunLoop();
3509	# endif
3510
3511	/*
3512	* Unless there's already work pending, go to sleep for a short while.
3513	* (See polling/sleep interval config above.)
3514	*/
3515	if ( fBadOrDisabledFifo
3516	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3517	{
3518	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3519	Assert(pThis->cMilliesRefreshInterval > 0);
3520	if (cMsSleep < pThis->cMilliesRefreshInterval)
3521	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3522	else
3523	{
3524	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3525	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3526	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3527	# endif
3528	if ( !fBadOrDisabledFifo
3529	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3530	rc = VINF_SUCCESS;
3531	else
3532	{
3533	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3534	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3535	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3536	}
3537	}
3538	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3539	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3540	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3541	{
3542	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3543	break;
3544	}
3545	}
3546	else
3547	rc = VINF_SUCCESS;
3548	fBadOrDisabledFifo = false;
3549	if (rc == VERR_TIMEOUT)
3550	{
3551	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3552	{
3553	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3554	continue;
3555	}
3556	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3557
3558	Log(("vmsvgaR3FifoLoop: timeout\n"));
3559	}
3560	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3561	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3562	cMsSleep = cMsMinSleep;
3563
3564	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3565	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3566	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3567
3568	/*
3569	* Handle external commands (currently only reset).
3570	*/
3571	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3572	{
3573	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3574	continue;
3575	}
3576
3577	/*
3578	* The device must be enabled and configured.
3579	*/
3580	if ( !pThis->svga.fEnabled
3581	\|\| !pThis->svga.fConfigured)
3582	{
3583	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3584	fBadOrDisabledFifo = true;
3585	cMsSleep = cMsMaxSleep; /* cheat */
3586	continue;
3587	}
3588
3589	/*
3590	* Get and check the min/max values. We ASSUME that they will remain
3591	* unchanged while we process requests. A further ASSUMPTION is that
3592	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3593	* we don't read it back while in the loop.
3594	*/
3595	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3596	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3597	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3598	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3599	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3600	\|\| offFifoMax <= offFifoMin
3601	\|\| offFifoMax > pThis->svga.cbFIFO
3602	\|\| (offFifoMax & 3) != 0
3603	\|\| (offFifoMin & 3) != 0
3604	\|\| offCurrentCmd < offFifoMin
3605	\|\| offCurrentCmd > offFifoMax))
3606	{
3607	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3608	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3609	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3610	fBadOrDisabledFifo = true;
3611	continue;
3612	}
3613	RT_UNTRUSTED_VALIDATED_FENCE();
3614	if (RT_UNLIKELY(offCurrentCmd & 3))
3615	{
3616	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3617	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3618	offCurrentCmd &= ~UINT32_C(3);
3619	}
3620
3621	/*
3622	* Update the cursor position before we start on the FIFO commands.
3623	*/
3624	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3625	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3626	{
3627	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3628	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3629	{ /* halfways likely */ }
3630	else
3631	{
3632	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3633	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3634	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3635	}
3636	}
3637
3638	/*
3639	* Mark the FIFO as busy.
3640	*/
3641	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3642	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3643	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3644
3645	/*
3646	* Execute all queued FIFO commands.
3647	* Quit if pending external command or changes in the thread state.
3648	*/
3649	bool fDone = false;
3650	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3651	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3652	{
3653	uint32_t cbPayload = 0;
3654	uint32_t u32IrqStatus = 0;
3655
3656	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3657
3658	/* First check any pending actions. */
3659	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3660	{
3661	vmsvgaR3ChangeMode(pThis, pThisCC);
3662	# ifdef VBOX_WITH_VMSVGA3D
3663	if (pThisCC->svga.p3dState != NULL)
3664	vmsvga3dChangeMode(pThisCC);
3665	# endif
3666	}
3667
3668	/* Check for pending external commands (reset). */
3669	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3670	break;
3671
3672	/*
3673	* Process the command.
3674	*/
3675	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3676	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3677	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3678	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3679	switch (enmCmdId)
3680	{
3681	case SVGA_CMD_INVALID_CMD:
3682	/* Nothing to do. */
3683	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3684	break;
3685
3686	case SVGA_CMD_FENCE:
3687	{
3688	SVGAFifoCmdFence *pCmdFence;
3689	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3691	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3692	{
3693	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3694	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3695
3696	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3697	{
3698	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3699	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3700	}
3701	else
3702	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3703	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3704	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3705	{
3706	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3707	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3708	}
3709	}
3710	else
3711	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3712	break;
3713	}
3714	case SVGA_CMD_UPDATE:
3715	case SVGA_CMD_UPDATE_VERBOSE:
3716	{
3717	SVGAFifoCmdUpdate *pUpdate;
3718	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3719	if (enmCmdId == SVGA_CMD_UPDATE)
3720	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3721	else
3722	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3723	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3724	/** @todo Multiple screens? */
3725	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3726	AssertBreak(pScreen);
3727	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3728	break;
3729	}
3730
3731	case SVGA_CMD_DEFINE_CURSOR:
3732	{
3733	/* Followed by bitmap data. */
3734	SVGAFifoCmdDefineCursor *pCursor;
3735	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3736	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3737
3738	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3739	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3740	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3741	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3742	AssertBreak(pCursor->andMaskDepth <= 32);
3743	AssertBreak(pCursor->xorMaskDepth <= 32);
3744	RT_UNTRUSTED_VALIDATED_FENCE();
3745
3746	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3747	uint32_t cbAndMask = cbAndLine * pCursor->height;
3748	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3749	uint32_t cbXorMask = cbXorLine * pCursor->height;
3750	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3751
3752	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3753	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3754	break;
3755	}
3756
3757	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3758	{
3759	/* Followed by bitmap data. */
3760	uint32_t cbCursorShape, cbAndMask;
3761	uint8_t *pCursorCopy;
3762	uint32_t cbCmd;
3763
3764	SVGAFifoCmdDefineAlphaCursor *pCursor;
3765	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3766	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3767
3768	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3769
3770	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3771	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3772	RT_UNTRUSTED_VALIDATED_FENCE();
3773
3774	/* Refetch the bitmap data as well. */
3775	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3776	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3777	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3778
3779	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3780	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3781	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3782	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3783
3784	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3785	AssertBreak(pCursorCopy);
3786
3787	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3788	memset(pCursorCopy, 0xff, cbAndMask);
3789	/* Colour data */
3790	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3791
3792	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3793	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3794	break;
3795	}
3796
3797	case SVGA_CMD_ESCAPE:
3798	{
3799	/* Followed by nsize bytes of data. */
3800	SVGAFifoCmdEscape *pEscape;
3801	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3802	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3803
3804	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3805	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3806	RT_UNTRUSTED_VALIDATED_FENCE();
3807	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3808	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3809
3810	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3811	{
3812	AssertBreak(pEscape->size >= sizeof(uint32_t));
3813	RT_UNTRUSTED_VALIDATED_FENCE();
3814	uint32_t cmd = (uint32_t )(pEscape + 1);
3815	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3816
3817	switch (cmd)
3818	{
3819	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3820	{
3821	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3822	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3823	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3824
3825	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3826	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3827	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3828
3829	RT_NOREF_PV(pVideoCmd);
3830	break;
3831
3832	}
3833
3834	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3835	{
3836	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3837	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3838	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3839	RT_NOREF_PV(pVideoCmd);
3840	break;
3841	}
3842
3843	default:
3844	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3845	break;
3846	}
3847	}
3848	else
3849	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3850
3851	break;
3852	}
3853	# ifdef VBOX_WITH_VMSVGA3D
3854	case SVGA_CMD_DEFINE_GMR2:
3855	{
3856	SVGAFifoCmdDefineGMR2 *pCmd;
3857	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3858	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3859	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3860
3861	/* Validate current GMR id. */
3862	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3863	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3864	RT_UNTRUSTED_VALIDATED_FENCE();
3865
3866	if (!pCmd->numPages)
3867	{
3868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3869	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3870	}
3871	else
3872	{
3873	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3874	if (pGMR->cMaxPages)
3875	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3876
3877	/* Not sure if we should always free the descriptor, but for simplicity
3878	we do so if the new size is smaller than the current. */
3879	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3880	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3881	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3882
3883	pGMR->cMaxPages = pCmd->numPages;
3884	/* The rest is done by the REMAP_GMR2 command. */
3885	}
3886	break;
3887	}
3888
3889	case SVGA_CMD_REMAP_GMR2:
3890	{
3891	/* Followed by page descriptors or guest ptr. */
3892	SVGAFifoCmdRemapGMR2 *pCmd;
3893	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3894	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3895
3896	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3897	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3898	RT_UNTRUSTED_VALIDATED_FENCE();
3899
3900	/* Calculate the size of what comes after next and fetch it. */
3901	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3902	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3903	cbCmd += sizeof(SVGAGuestPtr);
3904	else
3905	{
3906	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3907	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3908	{
3909	cbCmd += cbPageDesc;
3910	pCmd->numPages = 1;
3911	}
3912	else
3913	{
3914	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3915	cbCmd += cbPageDesc * pCmd->numPages;
3916	}
3917	}
3918	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3919
3920	/* Validate current GMR id and size. */
3921	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3922	RT_UNTRUSTED_VALIDATED_FENCE();
3923	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3924	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3925	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3926	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3927
3928	if (pCmd->numPages == 0)
3929	break;
3930
3931	/** @todo Move to a separate function vmsvgaGMRRemap() */
3932
3933	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3934	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3935
3936	/*
3937	* We flatten the existing descriptors into a page array, overwrite the
3938	* pages specified in this command and then recompress the descriptor.
3939	*/
3940	/** @todo Optimize the GMR remap algorithm! */
3941
3942	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3943	uint64_t *paNewPage64 = NULL;
3944	if (pGMR->paDesc)
3945	{
3946	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3947
3948	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3949	AssertBreak(paNewPage64);
3950
3951	uint32_t idxPage = 0;
3952	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3953	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3954	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3955	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3956	RT_UNTRUSTED_VALIDATED_FENCE();
3957	}
3958
3959	/* Free the old GMR if present. */
3960	if (pGMR->paDesc)
3961	RTMemFree(pGMR->paDesc);
3962
3963	/* Allocate the maximum amount possible (everything non-continuous) */
3964	PVMSVGAGMRDESCRIPTOR paDescs;
3965	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3966	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3967
3968	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3969	{
3970	/** @todo */
3971	AssertFailed();
3972	pGMR->numDescriptors = 0;
3973	}
3974	else
3975	{
3976	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3977	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3978	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3979
3980	if (paNewPage64)
3981	{
3982	/* Overwrite the old page array with the new page values. */
3983	if (fGCPhys64)
3984	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3985	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3986	else
3987	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3988	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3989
3990	/* Use the updated page array instead of the command data. */
3991	fGCPhys64 = true;
3992	paPages64 = paNewPage64;
3993	pCmd->numPages = cNewTotalPages;
3994	}
3995
3996	/* The first page. */
3997	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3998	* applied to paNewPage64. */
3999	RTGCPHYS GCPhys;
4000	if (fGCPhys64)
4001	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4002	else
4003	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4004	paDescs[0].GCPhys = GCPhys;
4005	paDescs[0].numPages = 1;
4006
4007	/* Subsequent pages. */
4008	uint32_t iDescriptor = 0;
4009	for (uint32_t i = 1; i < pCmd->numPages; i++)
4010	{
4011	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4012	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4013	else
4014	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4015
4016	/* Continuous physical memory? */
4017	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4018	{
4019	Assert(paDescs[iDescriptor].numPages);
4020	paDescs[iDescriptor].numPages++;
4021	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4022	}
4023	else
4024	{
4025	iDescriptor++;
4026	paDescs[iDescriptor].GCPhys = GCPhys;
4027	paDescs[iDescriptor].numPages = 1;
4028	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4029	}
4030	}
4031
4032	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4033	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4034	pGMR->numDescriptors = iDescriptor + 1;
4035	}
4036
4037	if (paNewPage64)
4038	RTMemFree(paNewPage64);
4039
4040	# ifdef DEBUG_GMR_ACCESS
4041	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4042	# endif
4043	break;
4044	}
4045	# endif // VBOX_WITH_VMSVGA3D
4046	case SVGA_CMD_DEFINE_SCREEN:
4047	{
4048	/* The size of this command is specified by the guest and depends on capabilities. */
4049	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4050
4051	SVGAFifoCmdDefineScreen *pCmd;
4052	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4053	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4054	RT_UNTRUSTED_VALIDATED_FENCE();
4055
4056	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4057	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4058	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4059
4060	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4061	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4062	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4063
4064	uint32_t const idScreen = pCmd->screen.id;
4065	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4066
4067	uint32_t const uWidth = pCmd->screen.size.width;
4068	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4069
4070	uint32_t const uHeight = pCmd->screen.size.height;
4071	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4072
4073	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4074	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4075	AssertBreak(cbWidth <= cbPitch);
4076
4077	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4078	AssertBreak(uScreenOffset < pThis->vram_size);
4079
4080	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4081	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4082	AssertBreak( (uHeight == 0 && cbPitch == 0)
4083	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4084	RT_UNTRUSTED_VALIDATED_FENCE();
4085
4086	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4087
4088	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4089
4090	pScreen->fDefined = true;
4091	pScreen->fModified = true;
4092	pScreen->fuScreen = pCmd->screen.flags;
4093	pScreen->idScreen = idScreen;
4094	if (!fBlank)
4095	{
4096	AssertBreak(uWidth > 0 && uHeight > 0);
4097
4098	pScreen->xOrigin = pCmd->screen.root.x;
4099	pScreen->yOrigin = pCmd->screen.root.y;
4100	pScreen->cWidth = uWidth;
4101	pScreen->cHeight = uHeight;
4102	pScreen->offVRAM = uScreenOffset;
4103	pScreen->cbPitch = cbPitch;
4104	pScreen->cBpp = 32;
4105	}
4106	else
4107	{
4108	/* Keep old values. */
4109	}
4110
4111	pThis->svga.fGFBRegisters = false;
4112	vmsvgaR3ChangeMode(pThis, pThisCC);
4113	break;
4114	}
4115
4116	case SVGA_CMD_DESTROY_SCREEN:
4117	{
4118	SVGAFifoCmdDestroyScreen *pCmd;
4119	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4120	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4121
4122	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4123
4124	uint32_t const idScreen = pCmd->screenId;
4125	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4126	RT_UNTRUSTED_VALIDATED_FENCE();
4127
4128	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4129	pScreen->fModified = true;
4130	pScreen->fDefined = false;
4131	pScreen->idScreen = idScreen;
4132
4133	vmsvgaR3ChangeMode(pThis, pThisCC);
4134	break;
4135	}
4136
4137	case SVGA_CMD_DEFINE_GMRFB:
4138	{
4139	SVGAFifoCmdDefineGMRFB *pCmd;
4140	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4141	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4142
4143	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4144	pSVGAState->GMRFB.ptr = pCmd->ptr;
4145	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4146	pSVGAState->GMRFB.format = pCmd->format;
4147	break;
4148	}
4149
4150	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4151	{
4152	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4153	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4154	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4155
4156	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4157	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4158
4159	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4160	RT_UNTRUSTED_VALIDATED_FENCE();
4161
4162	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4163	AssertBreak(pScreen);
4164
4165	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4166	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4167
4168	/* Clip destRect to the screen dimensions. */
4169	SVGASignedRect screenRect;
4170	screenRect.left = 0;
4171	screenRect.top = 0;
4172	screenRect.right = pScreen->cWidth;
4173	screenRect.bottom = pScreen->cHeight;
4174	SVGASignedRect clipRect = pCmd->destRect;
4175	vmsvgaR3ClipRect(&screenRect, &clipRect);
4176	RT_UNTRUSTED_VALIDATED_FENCE();
4177
4178	uint32_t const width = clipRect.right - clipRect.left;
4179	uint32_t const height = clipRect.bottom - clipRect.top;
4180
4181	if ( width == 0
4182	\|\| height == 0)
4183	break; /* Nothing to do. */
4184
4185	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4186	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4187
4188	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4189	* Prepare parameters for vmsvgaR3GmrTransfer.
4190	*/
4191	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4192
4193	/* Destination: host buffer which describes the screen 0 VRAM.
4194	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4195	*/
4196	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4197	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4198	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4199	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4200	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4201	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4202	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4203	+ cbScanline * clipRect.top;
4204	int32_t const cbHstPitch = cbScanline;
4205
4206	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4207	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4208	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4209	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4210	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4211
4212	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4213	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4214	gstPtr, offGst, cbGstPitch,
4215	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4216	AssertRC(rc);
4217	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4218	break;
4219	}
4220
4221	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4222	{
4223	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4224	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4225	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4226
4227	/* Note! This can fetch 3d render results as well!! */
4228	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4229	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4230
4231	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4232	RT_UNTRUSTED_VALIDATED_FENCE();
4233
4234	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4235	AssertBreak(pScreen);
4236
4237	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4238	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4239
4240	/* Clip destRect to the screen dimensions. */
4241	SVGASignedRect screenRect;
4242	screenRect.left = 0;
4243	screenRect.top = 0;
4244	screenRect.right = pScreen->cWidth;
4245	screenRect.bottom = pScreen->cHeight;
4246	SVGASignedRect clipRect = pCmd->srcRect;
4247	vmsvgaR3ClipRect(&screenRect, &clipRect);
4248	RT_UNTRUSTED_VALIDATED_FENCE();
4249
4250	uint32_t const width = clipRect.right - clipRect.left;
4251	uint32_t const height = clipRect.bottom - clipRect.top;
4252
4253	if ( width == 0
4254	\|\| height == 0)
4255	break; /* Nothing to do. */
4256
4257	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4258	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4259
4260	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4261	* Prepare parameters for vmsvgaR3GmrTransfer.
4262	*/
4263	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4264
4265	/* Source: host buffer which describes the screen 0 VRAM.
4266	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4267	*/
4268	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4269	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4270	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4271	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4272	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4273	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4274	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4275	+ cbScanline * clipRect.top;
4276	int32_t const cbHstPitch = cbScanline;
4277
4278	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4279	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4280	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4281	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4282	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4283
4284	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4285	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4286	gstPtr, offGst, cbGstPitch,
4287	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4288	AssertRC(rc);
4289	break;
4290	}
4291
4292	case SVGA_CMD_ANNOTATION_FILL:
4293	{
4294	SVGAFifoCmdAnnotationFill *pCmd;
4295	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4296	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4297
4298	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4299	pSVGAState->colorAnnotation = pCmd->color;
4300	break;
4301	}
4302
4303	case SVGA_CMD_ANNOTATION_COPY:
4304	{
4305	SVGAFifoCmdAnnotationCopy *pCmd;
4306	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4307	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4308
4309	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4310	AssertFailed();
4311	break;
4312	}
4313
4314	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4315
4316	default:
4317	# ifdef VBOX_WITH_VMSVGA3D
4318	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4319	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4320	{
4321	RT_UNTRUSTED_VALIDATED_FENCE();
4322
4323	/* All 3d commands start with a common header, which defines the size of the command. */
4324	SVGA3dCmdHeader *pHdr;
4325	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4326	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4327	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4328	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4329
4330	if (RT_LIKELY(pThis->svga.f3DEnabled))
4331	{ /* likely */ }
4332	else
4333	{
4334	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4335	break;
4336	}
4337
4338	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4339	* Check that the 3D command has at least a_cbMin of payload bytes after the
4340	* header. Will break out of the switch if it doesn't.
4341	*/
4342	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4343	if (1) { \
4344	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4345	RT_UNTRUSTED_VALIDATED_FENCE(); \
4346	} else do {} while (0)
4347	switch ((int)enmCmdId)
4348	{
4349	case SVGA_3D_CMD_SURFACE_DEFINE:
4350	{
4351	uint32_t cMipLevels;
4352	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4353	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4354	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4355
4356	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4357	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4358	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4359	# ifdef DEBUG_GMR_ACCESS
4360	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4361	# endif
4362	break;
4363	}
4364
4365	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4366	{
4367	uint32_t cMipLevels;
4368	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4371
4372	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4373	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4374	pCmd->multisampleCount, pCmd->autogenFilter,
4375	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4376	break;
4377	}
4378
4379	case SVGA_3D_CMD_SURFACE_DESTROY:
4380	{
4381	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4382	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4383	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4384	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4385	break;
4386	}
4387
4388	case SVGA_3D_CMD_SURFACE_COPY:
4389	{
4390	uint32_t cCopyBoxes;
4391	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4392	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4393	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4394
4395	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4396	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4397	break;
4398	}
4399
4400	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4401	{
4402	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4403	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4404	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4405
4406	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4407	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4408	break;
4409	}
4410
4411	case SVGA_3D_CMD_SURFACE_DMA:
4412	{
4413	uint32_t cCopyBoxes;
4414	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4415	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4416	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4417
4418	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4419	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4420	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4421	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4422	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4423	break;
4424	}
4425
4426	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4427	{
4428	uint32_t cRects;
4429	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4430	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4431	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4432
4433	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4434	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4435	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4436	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4437	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4438	break;
4439	}
4440
4441	case SVGA_3D_CMD_CONTEXT_DEFINE:
4442	{
4443	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4446
4447	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4448	break;
4449	}
4450
4451	case SVGA_3D_CMD_CONTEXT_DESTROY:
4452	{
4453	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4454	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4455	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4456
4457	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4458	break;
4459	}
4460
4461	case SVGA_3D_CMD_SETTRANSFORM:
4462	{
4463	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4464	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4465	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4466
4467	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4468	break;
4469	}
4470
4471	case SVGA_3D_CMD_SETZRANGE:
4472	{
4473	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4474	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4475	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4476
4477	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4478	break;
4479	}
4480
4481	case SVGA_3D_CMD_SETRENDERSTATE:
4482	{
4483	uint32_t cRenderStates;
4484	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4485	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4486	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4487
4488	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4489	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4490	break;
4491	}
4492
4493	case SVGA_3D_CMD_SETRENDERTARGET:
4494	{
4495	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4496	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4497	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4498
4499	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4500	break;
4501	}
4502
4503	case SVGA_3D_CMD_SETTEXTURESTATE:
4504	{
4505	uint32_t cTextureStates;
4506	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4507	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4508	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4509
4510	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4511	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4512	break;
4513	}
4514
4515	case SVGA_3D_CMD_SETMATERIAL:
4516	{
4517	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4518	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4520
4521	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4522	break;
4523	}
4524
4525	case SVGA_3D_CMD_SETLIGHTDATA:
4526	{
4527	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4528	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4530
4531	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4532	break;
4533	}
4534
4535	case SVGA_3D_CMD_SETLIGHTENABLED:
4536	{
4537	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4538	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4539	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4540
4541	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4542	break;
4543	}
4544
4545	case SVGA_3D_CMD_SETVIEWPORT:
4546	{
4547	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4548	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4549	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4550
4551	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_SETCLIPPLANE:
4556	{
4557	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4560
4561	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4562	break;
4563	}
4564
4565	case SVGA_3D_CMD_CLEAR:
4566	{
4567	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4568	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4569	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4570
4571	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4572	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4573	break;
4574	}
4575
4576	case SVGA_3D_CMD_PRESENT:
4577	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4578	{
4579	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4580	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4582	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4583	else
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4585
4586	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4587
4588	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4589	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4590	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4591	break;
4592	}
4593
4594	case SVGA_3D_CMD_SHADER_DEFINE:
4595	{
4596	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4597	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4598	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4599
4600	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4601	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4602	break;
4603	}
4604
4605	case SVGA_3D_CMD_SHADER_DESTROY:
4606	{
4607	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4608	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4609	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4610
4611	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4612	break;
4613	}
4614
4615	case SVGA_3D_CMD_SET_SHADER:
4616	{
4617	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4618	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4619	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4620
4621	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4622	break;
4623	}
4624
4625	case SVGA_3D_CMD_SET_SHADER_CONST:
4626	{
4627	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4628	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4629	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4630
4631	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4632	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4633	break;
4634	}
4635
4636	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4637	{
4638	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4639	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4641
4642	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4643	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4644	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4645	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4646	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4647
4648	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4649	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4650
4651	RT_UNTRUSTED_VALIDATED_FENCE();
4652
4653	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4654	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4655	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4656
4657	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4658	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4659	pNumRange, cVertexDivisor, pVertexDivisor);
4660	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4661	break;
4662	}
4663
4664	case SVGA_3D_CMD_SETSCISSORRECT:
4665	{
4666	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4667	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4669
4670	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4671	break;
4672	}
4673
4674	case SVGA_3D_CMD_BEGIN_QUERY:
4675	{
4676	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4677	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4679
4680	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4681	break;
4682	}
4683
4684	case SVGA_3D_CMD_END_QUERY:
4685	{
4686	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4687	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4689
4690	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4695	{
4696	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4699
4700	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4705	{
4706	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4709
4710	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4711	break;
4712	}
4713
4714	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4715	/* context id + surface id? */
4716	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4717	break;
4718	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4719	/* context id + surface id? */
4720	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4721	break;
4722
4723	default:
4724	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4725	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4726	break;
4727	}
4728	}
4729	else
4730	# endif // VBOX_WITH_VMSVGA3D
4731	{
4732	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4733	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4734	}
4735	}
4736
4737	/* Go to the next slot */
4738	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4739	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4740	if (offCurrentCmd >= offFifoMax)
4741	{
4742	offCurrentCmd -= offFifoMax - offFifoMin;
4743	Assert(offCurrentCmd >= offFifoMin);
4744	Assert(offCurrentCmd < offFifoMax);
4745	}
4746	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4748
4749	/*
4750	* Raise IRQ if required. Must enter the critical section here
4751	* before making final decisions here, otherwise cubebench and
4752	* others may end up waiting forever.
4753	*/
4754	if ( u32IrqStatus
4755	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4756	{
4757	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4758	AssertRC(rc2);
4759
4760	/* FIFO progress might trigger an interrupt. */
4761	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4762	{
4763	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4764	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4765	}
4766
4767	/* Unmasked IRQ pending? */
4768	if (pThis->svga.u32IrqMask & u32IrqStatus)
4769	{
4770	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4771	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4772	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4773	}
4774
4775	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4776	}
4777	}
4778
4779	/* If really done, clear the busy flag. */
4780	if (fDone)
4781	{
4782	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4783	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4784	}
4785	}
4786
4787	/*
4788	* Free the bounce buffer. (There are no returns above!)
4789	*/
4790	RTMemFree(pbBounceBuf);
4791
4792	return VINF_SUCCESS;
4793	}
4794
4795	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4796	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4797	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4798
4799	/**
4800	* Free the specified GMR
4801	*
4802	* @param pThisCC The VGA/VMSVGA state for ring-3.
4803	* @param idGMR GMR id
4804	*/
4805	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4806	{
4807	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4808
4809	/* Free the old descriptor if present. */
4810	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4811	if ( pGMR->numDescriptors
4812	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4813	{
4814	# ifdef DEBUG_GMR_ACCESS
4815	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4816	# endif
4817
4818	Assert(pGMR->paDesc);
4819	RTMemFree(pGMR->paDesc);
4820	pGMR->paDesc = NULL;
4821	pGMR->numDescriptors = 0;
4822	pGMR->cbTotal = 0;
4823	pGMR->cMaxPages = 0;
4824	}
4825	Assert(!pGMR->cMaxPages);
4826	Assert(!pGMR->cbTotal);
4827	}
4828
4829	/**
4830	* Copy between a GMR and a host memory buffer.
4831	*
4832	* @returns VBox status code.
4833	* @param pThis The shared VGA/VMSVGA instance data.
4834	* @param pThisCC The VGA/VMSVGA state for ring-3.
4835	* @param enmTransferType Transfer type (read/write)
4836	* @param pbHstBuf Host buffer pointer (valid)
4837	* @param cbHstBuf Size of host buffer (valid)
4838	* @param offHst Host buffer offset of the first scanline
4839	* @param cbHstPitch Destination buffer pitch
4840	* @param gstPtr GMR description
4841	* @param offGst Guest buffer offset of the first scanline
4842	* @param cbGstPitch Guest buffer pitch
4843	* @param cbWidth Width in bytes to copy
4844	* @param cHeight Number of scanllines to copy
4845	*/
4846	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4847	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4848	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4849	uint32_t cbWidth, uint32_t cHeight)
4850	{
4851	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4852	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4853	int rc;
4854
4855	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4856	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4857	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4858	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4859	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4860
4861	PGMR pGMR;
4862	uint32_t cbGmr; /* The GMR size in bytes. */
4863	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4864	{
4865	pGMR = NULL;
4866	cbGmr = pThis->vram_size;
4867	}
4868	else
4869	{
4870	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4871	RT_UNTRUSTED_VALIDATED_FENCE();
4872	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4873	cbGmr = pGMR->cbTotal;
4874	}
4875
4876	/*
4877	* GMR
4878	*/
4879	/* Calculate GMR offset of the data to be copied. */
4880	AssertMsgReturn(gstPtr.offset < cbGmr,
4881	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4882	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4883	VERR_INVALID_PARAMETER);
4884	RT_UNTRUSTED_VALIDATED_FENCE();
4885	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4886	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4887	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4888	VERR_INVALID_PARAMETER);
4889	RT_UNTRUSTED_VALIDATED_FENCE();
4890	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4891
4892	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4893	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4894	AssertMsgReturn(cbGmrScanline != 0,
4895	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4896	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4897	VERR_INVALID_PARAMETER);
4898	RT_UNTRUSTED_VALIDATED_FENCE();
4899	AssertMsgReturn(cbWidth <= cbGmrScanline,
4900	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4901	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4902	VERR_INVALID_PARAMETER);
4903	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4904	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4905	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4906	VERR_INVALID_PARAMETER);
4907	RT_UNTRUSTED_VALIDATED_FENCE();
4908
4909	/* How many bytes are available for the data in the GMR. */
4910	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4911
4912	/* How many scanlines would fit into the available data. */
4913	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4914	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4915	if (cbWidth <= cbGmrLastScanline)
4916	++cGmrScanlines;
4917
4918	if (cHeight > cGmrScanlines)
4919	cHeight = cGmrScanlines;
4920
4921	AssertMsgReturn(cHeight > 0,
4922	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4923	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4924	VERR_INVALID_PARAMETER);
4925	RT_UNTRUSTED_VALIDATED_FENCE();
4926
4927	/*
4928	* Host buffer.
4929	*/
4930	AssertMsgReturn(offHst < cbHstBuf,
4931	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4932	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4933	VERR_INVALID_PARAMETER);
4934
4935	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4936	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4937	AssertMsgReturn(cbHstScanline != 0,
4938	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4939	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4940	VERR_INVALID_PARAMETER);
4941	AssertMsgReturn(cbWidth <= cbHstScanline,
4942	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4943	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4944	VERR_INVALID_PARAMETER);
4945	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4946	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4947	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4948	VERR_INVALID_PARAMETER);
4949
4950	/* How many bytes are available for the data in the buffer. */
4951	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4952
4953	/* How many scanlines would fit into the available data. */
4954	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4955	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4956	if (cbWidth <= cbHstLastScanline)
4957	++cHstScanlines;
4958
4959	if (cHeight > cHstScanlines)
4960	cHeight = cHstScanlines;
4961
4962	AssertMsgReturn(cHeight > 0,
4963	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4964	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4965	VERR_INVALID_PARAMETER);
4966
4967	uint8_t *pbHst = pbHstBuf + offHst;
4968
4969	/* Shortcut for the framebuffer. */
4970	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4971	{
4972	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
4973
4974	uint8_t const *pbSrc;
4975	int32_t cbSrcPitch;
4976	uint8_t *pbDst;
4977	int32_t cbDstPitch;
4978
4979	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4980	{
4981	pbSrc = pbHst;
4982	cbSrcPitch = cbHstPitch;
4983	pbDst = pbGst;
4984	cbDstPitch = cbGstPitch;
4985	}
4986	else
4987	{
4988	pbSrc = pbGst;
4989	cbSrcPitch = cbGstPitch;
4990	pbDst = pbHst;
4991	cbDstPitch = cbHstPitch;
4992	}
4993
4994	if ( cbWidth == (uint32_t)cbGstPitch
4995	&& cbGstPitch == cbHstPitch)
4996	{
4997	/* Entire scanlines, positive pitch. */
4998	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4999	}
5000	else
5001	{
5002	for (uint32_t i = 0; i < cHeight; ++i)
5003	{
5004	memcpy(pbDst, pbSrc, cbWidth);
5005
5006	pbDst += cbDstPitch;
5007	pbSrc += cbSrcPitch;
5008	}
5009	}
5010	return VINF_SUCCESS;
5011	}
5012
5013	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5014	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5015
5016	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5017	uint32_t iDesc = 0; /* Index in the descriptor array. */
5018	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5019	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5020	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5021	for (uint32_t i = 0; i < cHeight; ++i)
5022	{
5023	uint32_t cbCurrentWidth = cbWidth;
5024	uint32_t offGmrCurrent = offGmrScanline;
5025	uint8_t *pbCurrentHost = pbHstScanline;
5026
5027	/* Find the right descriptor */
5028	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5029	{
5030	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5031	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5032	++iDesc;
5033	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5034	}
5035
5036	while (cbCurrentWidth)
5037	{
5038	uint32_t cbToCopy;
5039
5040	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5041	{
5042	cbToCopy = cbCurrentWidth;
5043	}
5044	else
5045	{
5046	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5047	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5048	}
5049
5050	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5051
5052	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5053
5054	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5055	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5056	else
5057	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5058	AssertRCBreak(rc);
5059
5060	cbCurrentWidth -= cbToCopy;
5061	offGmrCurrent += cbToCopy;
5062	pbCurrentHost += cbToCopy;
5063
5064	/* Go to the next descriptor if there's anything left. */
5065	if (cbCurrentWidth)
5066	{
5067	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5068	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5069	++iDesc;
5070	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5071	}
5072	}
5073
5074	offGmrScanline += cbGstPitch;
5075	pbHstScanline += cbHstPitch;
5076	}
5077
5078	return VINF_SUCCESS;
5079	}
5080
5081
5082	/**
5083	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5084	*
5085	* @param pSizeSrc Source surface dimensions.
5086	* @param pSizeDest Destination surface dimensions.
5087	* @param pBox Coordinates to be clipped.
5088	*/
5089	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5090	{
5091	/* Src x, w */
5092	if (pBox->srcx > pSizeSrc->width)
5093	pBox->srcx = pSizeSrc->width;
5094	if (pBox->w > pSizeSrc->width - pBox->srcx)
5095	pBox->w = pSizeSrc->width - pBox->srcx;
5096
5097	/* Src y, h */
5098	if (pBox->srcy > pSizeSrc->height)
5099	pBox->srcy = pSizeSrc->height;
5100	if (pBox->h > pSizeSrc->height - pBox->srcy)
5101	pBox->h = pSizeSrc->height - pBox->srcy;
5102
5103	/* Src z, d */
5104	if (pBox->srcz > pSizeSrc->depth)
5105	pBox->srcz = pSizeSrc->depth;
5106	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5107	pBox->d = pSizeSrc->depth - pBox->srcz;
5108
5109	/* Dest x, w */
5110	if (pBox->x > pSizeDest->width)
5111	pBox->x = pSizeDest->width;
5112	if (pBox->w > pSizeDest->width - pBox->x)
5113	pBox->w = pSizeDest->width - pBox->x;
5114
5115	/* Dest y, h */
5116	if (pBox->y > pSizeDest->height)
5117	pBox->y = pSizeDest->height;
5118	if (pBox->h > pSizeDest->height - pBox->y)
5119	pBox->h = pSizeDest->height - pBox->y;
5120
5121	/* Dest z, d */
5122	if (pBox->z > pSizeDest->depth)
5123	pBox->z = pSizeDest->depth;
5124	if (pBox->d > pSizeDest->depth - pBox->z)
5125	pBox->d = pSizeDest->depth - pBox->z;
5126	}
5127
5128	/**
5129	* Unsigned coordinates in pBox. Clip to [0; pSize).
5130	*
5131	* @param pSize Source surface dimensions.
5132	* @param pBox Coordinates to be clipped.
5133	*/
5134	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5135	{
5136	/* x, w */
5137	if (pBox->x > pSize->width)
5138	pBox->x = pSize->width;
5139	if (pBox->w > pSize->width - pBox->x)
5140	pBox->w = pSize->width - pBox->x;
5141
5142	/* y, h */
5143	if (pBox->y > pSize->height)
5144	pBox->y = pSize->height;
5145	if (pBox->h > pSize->height - pBox->y)
5146	pBox->h = pSize->height - pBox->y;
5147
5148	/* z, d */
5149	if (pBox->z > pSize->depth)
5150	pBox->z = pSize->depth;
5151	if (pBox->d > pSize->depth - pBox->z)
5152	pBox->d = pSize->depth - pBox->z;
5153	}
5154
5155	/**
5156	* Clip.
5157	*
5158	* @param pBound Bounding rectangle.
5159	* @param pRect Rectangle to be clipped.
5160	*/
5161	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5162	{
5163	int32_t left;
5164	int32_t top;
5165	int32_t right;
5166	int32_t bottom;
5167
5168	/* Right order. */
5169	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5170	if (pRect->left < pRect->right)
5171	{
5172	left = pRect->left;
5173	right = pRect->right;
5174	}
5175	else
5176	{
5177	left = pRect->right;
5178	right = pRect->left;
5179	}
5180	if (pRect->top < pRect->bottom)
5181	{
5182	top = pRect->top;
5183	bottom = pRect->bottom;
5184	}
5185	else
5186	{
5187	top = pRect->bottom;
5188	bottom = pRect->top;
5189	}
5190
5191	if (left < pBound->left)
5192	left = pBound->left;
5193	if (right < pBound->left)
5194	right = pBound->left;
5195
5196	if (left > pBound->right)
5197	left = pBound->right;
5198	if (right > pBound->right)
5199	right = pBound->right;
5200
5201	if (top < pBound->top)
5202	top = pBound->top;
5203	if (bottom < pBound->top)
5204	bottom = pBound->top;
5205
5206	if (top > pBound->bottom)
5207	top = pBound->bottom;
5208	if (bottom > pBound->bottom)
5209	bottom = pBound->bottom;
5210
5211	pRect->left = left;
5212	pRect->right = right;
5213	pRect->top = top;
5214	pRect->bottom = bottom;
5215	}
5216
5217	/**
5218	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5219	* Unblock the FIFO I/O thread so it can respond to a state change.}
5220	*/
5221	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5222	{
5223	RT_NOREF(pDevIns);
5224	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5225	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5226	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5227	}
5228
5229	/**
5230	* Enables or disables dirty page tracking for the framebuffer
5231	*
5232	* @param pDevIns The device instance.
5233	* @param pThis The shared VGA/VMSVGA instance data.
5234	* @param fTraces Enable/disable traces
5235	*/
5236	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5237	{
5238	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5239	&& !fTraces)
5240	{
5241	//Assert(pThis->svga.fTraces);
5242	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5243	return;
5244	}
5245
5246	pThis->svga.fTraces = fTraces;
5247	if (pThis->svga.fTraces)
5248	{
5249	unsigned cbFrameBuffer = pThis->vram_size;
5250
5251	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5252	/** @todo How does this work with screens? */
5253	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5254	{
5255	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5256	Assert(pThis->svga.cbScanline);
5257	# endif
5258	/* Hardware enabled; return real framebuffer size .*/
5259	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5260	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5261	}
5262
5263	if (!pThis->svga.fVRAMTracking)
5264	{
5265	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5266	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5267	pThis->svga.fVRAMTracking = true;
5268	}
5269	}
5270	else
5271	{
5272	if (pThis->svga.fVRAMTracking)
5273	{
5274	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5275	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5276	pThis->svga.fVRAMTracking = false;
5277	}
5278	}
5279	}
5280
5281	/**
5282	* @callback_method_impl{FNPCIIOREGIONMAP}
5283	*/
5284	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5285	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5286	{
5287	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5288	int rc;
5289	RT_NOREF(pPciDev);
5290	Assert(pPciDev == pDevIns->apPciDevs[0]);
5291
5292	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5293	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5294	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5295	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5296	, VERR_INTERNAL_ERROR);
5297	if (GCPhysAddress != NIL_RTGCPHYS)
5298	{
5299	/*
5300	* Mapping the FIFO RAM.
5301	*/
5302	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5303	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5304	AssertRC(rc);
5305
5306	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5307	if (RT_SUCCESS(rc))
5308	{
5309	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5310	# ifdef DEBUG_FIFO_ACCESS
5311	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5312	# else
5313	GCPhysAddress + PAGE_SIZE - 1,
5314	# endif
5315	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5316	"VMSVGA FIFO");
5317	AssertRC(rc);
5318	}
5319	# endif
5320	if (RT_SUCCESS(rc))
5321	{
5322	pThis->svga.GCPhysFIFO = GCPhysAddress;
5323	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5324	}
5325	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5326	}
5327	else
5328	{
5329	Assert(pThis->svga.GCPhysFIFO);
5330	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5331	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5332	AssertRC(rc);
5333	# else
5334	rc = VINF_SUCCESS;
5335	# endif
5336	pThis->svga.GCPhysFIFO = 0;
5337	}
5338	return rc;
5339	}
5340
5341	# ifdef VBOX_WITH_VMSVGA3D
5342
5343	/**
5344	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5345	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5346	*
5347	* @param pDevIns The device instance.
5348	* @param pThis The The shared VGA/VMSVGA instance data.
5349	* @param pThisCC The VGA/VMSVGA state for ring-3.
5350	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5351	* UINT32_MAX is used, all surfaces are processed.
5352	*/
5353	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5354	{
5355	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5356	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5357	}
5358
5359
5360	/**
5361	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5362	*/
5363	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5364	{
5365	/* There might be a specific surface ID at the start of the
5366	arguments, if not show all surfaces. */
5367	uint32_t sid = UINT32_MAX;
5368	if (pszArgs)
5369	pszArgs = RTStrStripL(pszArgs);
5370	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5371	sid = RTStrToUInt32(pszArgs);
5372
5373	/* Verbose or terse display, we default to verbose. */
5374	bool fVerbose = true;
5375	if (RTStrIStr(pszArgs, "terse"))
5376	fVerbose = false;
5377
5378	/* The size of the ascii art (x direction, y is 3/4 of x). */
5379	uint32_t cxAscii = 80;
5380	if (RTStrIStr(pszArgs, "gigantic"))
5381	cxAscii = 300;
5382	else if (RTStrIStr(pszArgs, "huge"))
5383	cxAscii = 180;
5384	else if (RTStrIStr(pszArgs, "big"))
5385	cxAscii = 132;
5386	else if (RTStrIStr(pszArgs, "normal"))
5387	cxAscii = 80;
5388	else if (RTStrIStr(pszArgs, "medium"))
5389	cxAscii = 64;
5390	else if (RTStrIStr(pszArgs, "small"))
5391	cxAscii = 48;
5392	else if (RTStrIStr(pszArgs, "tiny"))
5393	cxAscii = 24;
5394
5395	/* Y invert the image when producing the ASCII art. */
5396	bool fInvY = false;
5397	if (RTStrIStr(pszArgs, "invy"))
5398	fInvY = true;
5399
5400	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5401	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5402	}
5403
5404
5405	/**
5406	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5407	*/
5408	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5409	{
5410	/* pszArg = "sid[>dir]"
5411	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5412	*/
5413	char *pszBitmapPath = NULL;
5414	uint32_t sid = UINT32_MAX;
5415	if (pszArgs)
5416	pszArgs = RTStrStripL(pszArgs);
5417	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5418	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5419	if ( pszBitmapPath
5420	&& *pszBitmapPath == '>')
5421	++pszBitmapPath;
5422
5423	const bool fVerbose = true;
5424	const uint32_t cxAscii = 0; /* No ASCII */
5425	const bool fInvY = false; /* Do not invert. */
5426	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5427	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5428	}
5429
5430
5431	/**
5432	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5433	*/
5434	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5435	{
5436	/* There might be a specific surface ID at the start of the
5437	arguments, if not show all contexts. */
5438	uint32_t sid = UINT32_MAX;
5439	if (pszArgs)
5440	pszArgs = RTStrStripL(pszArgs);
5441	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5442	sid = RTStrToUInt32(pszArgs);
5443
5444	/* Verbose or terse display, we default to verbose. */
5445	bool fVerbose = true;
5446	if (RTStrIStr(pszArgs, "terse"))
5447	fVerbose = false;
5448
5449	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5450	}
5451
5452	# endif /* VBOX_WITH_VMSVGA3D */
5453
5454	/**
5455	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5456	*/
5457	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5458	{
5459	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5460	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5461	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5462	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5463	RT_NOREF(pszArgs);
5464
5465	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5466	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5467	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5468	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5469	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5470	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5471	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5472	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5473	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5474	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5475	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5476	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5477	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5478	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5479	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5480	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5481	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5482	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5483	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5484	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5485	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5486	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5487	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5488	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5489	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5490
5491	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5492	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5493	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5494	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5495
5496	# ifdef VBOX_WITH_VMSVGA3D
5497	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5498	# endif
5499	if (pThisCC->pDrv)
5500	{
5501	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5502	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5503	}
5504	}
5505
5506	/**
5507	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5508	*/
5509	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5510	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5511	{
5512	RT_NOREF(uPass);
5513
5514	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5515	int rc;
5516
5517	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5518	{
5519	uint32_t cScreens = 0;
5520	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5521	AssertRCReturn(rc, rc);
5522	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5523	("cScreens=%#x\n", cScreens),
5524	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5525
5526	for (uint32_t i = 0; i < cScreens; ++i)
5527	{
5528	VMSVGASCREENOBJECT screen;
5529	RT_ZERO(screen);
5530
5531	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5532	AssertLogRelRCReturn(rc, rc);
5533
5534	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5535	{
5536	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5537	*pScreen = screen;
5538	pScreen->fModified = true;
5539	}
5540	else
5541	{
5542	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5543	}
5544	}
5545	}
5546	else
5547	{
5548	/* Try to setup at least the first screen. */
5549	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5550	pScreen->fDefined = true;
5551	pScreen->fModified = true;
5552	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5553	pScreen->idScreen = 0;
5554	pScreen->xOrigin = 0;
5555	pScreen->yOrigin = 0;
5556	pScreen->offVRAM = pThis->svga.uScreenOffset;
5557	pScreen->cbPitch = pThis->svga.cbScanline;
5558	pScreen->cWidth = pThis->svga.uWidth;
5559	pScreen->cHeight = pThis->svga.uHeight;
5560	pScreen->cBpp = pThis->svga.uBpp;
5561	}
5562
5563	return VINF_SUCCESS;
5564	}
5565
5566	/**
5567	* @copydoc FNSSMDEVLOADEXEC
5568	*/
5569	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5570	{
5571	RT_NOREF(uPass);
5572	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5573	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5574	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5575	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5576	int rc;
5577
5578	/* Load our part of the VGAState */
5579	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5580	AssertRCReturn(rc, rc);
5581
5582	/* Load the VGA framebuffer. */
5583	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5584	uint32_t cbVgaFramebuffer = _32K;
5585	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5586	{
5587	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5588	AssertRCReturn(rc, rc);
5589	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5590	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5591	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5592	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5593	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5594	}
5595	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5596	AssertRCReturn(rc, rc);
5597	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5598	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5599	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5600	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5601
5602	/* Load the VMSVGA state. */
5603	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5604	AssertRCReturn(rc, rc);
5605
5606	/* Load the active cursor bitmaps. */
5607	if (pSVGAState->Cursor.fActive)
5608	{
5609	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5610	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5611
5612	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5613	AssertRCReturn(rc, rc);
5614	}
5615
5616	/* Load the GMR state. */
5617	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5618	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5619	{
5620	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5621	AssertRCReturn(rc, rc);
5622	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5623	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5624	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5625	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5626	}
5627
5628	if (pThis->svga.cGMR != cGMR)
5629	{
5630	/* Reallocate GMR array. */
5631	Assert(pSVGAState->paGMR != NULL);
5632	RTMemFree(pSVGAState->paGMR);
5633	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5634	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5635	pThis->svga.cGMR = cGMR;
5636	}
5637
5638	for (uint32_t i = 0; i < cGMR; ++i)
5639	{
5640	PGMR pGMR = &pSVGAState->paGMR[i];
5641
5642	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5643	AssertRCReturn(rc, rc);
5644
5645	if (pGMR->numDescriptors)
5646	{
5647	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5648	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5649	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5650
5651	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5652	{
5653	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5654	AssertRCReturn(rc, rc);
5655	}
5656	}
5657	}
5658
5659	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5660	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5661	# endif
5662
5663	VMSVGA_STATE_LOAD LoadState;
5664	LoadState.pSSM = pSSM;
5665	LoadState.uVersion = uVersion;
5666	LoadState.uPass = uPass;
5667	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5668	AssertLogRelRCReturn(rc, rc);
5669
5670	return VINF_SUCCESS;
5671	}
5672
5673	/**
5674	* Reinit the video mode after the state has been loaded.
5675	*/
5676	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5677	{
5678	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5679	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5680	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5681
5682	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5683
5684	/* Set the active cursor. */
5685	if (pSVGAState->Cursor.fActive)
5686	{
5687	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5688	true /fVisible/,
5689	true /fAlpha/,
5690	pSVGAState->Cursor.xHotspot,
5691	pSVGAState->Cursor.yHotspot,
5692	pSVGAState->Cursor.width,
5693	pSVGAState->Cursor.height,
5694	pSVGAState->Cursor.pData);
5695	AssertRC(rc);
5696	}
5697	return VINF_SUCCESS;
5698	}
5699
5700	/**
5701	* Portion of SVGA state which must be saved in the FIFO thread.
5702	*/
5703	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5704	{
5705	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5706	int rc;
5707
5708	/* Save the screen objects. */
5709	/* Count defined screen object. */
5710	uint32_t cScreens = 0;
5711	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5712	{
5713	if (pSVGAState->aScreens[i].fDefined)
5714	++cScreens;
5715	}
5716
5717	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5718	AssertLogRelRCReturn(rc, rc);
5719
5720	for (uint32_t i = 0; i < cScreens; ++i)
5721	{
5722	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5723
5724	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5725	AssertLogRelRCReturn(rc, rc);
5726	}
5727	return VINF_SUCCESS;
5728	}
5729
5730	/**
5731	* @copydoc FNSSMDEVSAVEEXEC
5732	*/
5733	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5734	{
5735	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5736	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5737	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5738	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5739	int rc;
5740
5741	/* Save our part of the VGAState */
5742	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5743	AssertLogRelRCReturn(rc, rc);
5744
5745	/* Save the framebuffer backup. */
5746	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5747	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5748	AssertLogRelRCReturn(rc, rc);
5749
5750	/* Save the VMSVGA state. */
5751	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5752	AssertLogRelRCReturn(rc, rc);
5753
5754	/* Save the active cursor bitmaps. */
5755	if (pSVGAState->Cursor.fActive)
5756	{
5757	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5758	AssertLogRelRCReturn(rc, rc);
5759	}
5760
5761	/* Save the GMR state */
5762	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5763	AssertLogRelRCReturn(rc, rc);
5764	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5765	{
5766	PGMR pGMR = &pSVGAState->paGMR[i];
5767
5768	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5769	AssertLogRelRCReturn(rc, rc);
5770
5771	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5772	{
5773	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5774	AssertLogRelRCReturn(rc, rc);
5775	}
5776	}
5777
5778	/*
5779	* Must save some state (3D in particular) in the FIFO thread.
5780	*/
5781	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5782	AssertLogRelRCReturn(rc, rc);
5783
5784	return VINF_SUCCESS;
5785	}
5786
5787	/**
5788	* Destructor for PVMSVGAR3STATE structure.
5789	*
5790	* @param pThis The shared VGA/VMSVGA instance data.
5791	* @param pSVGAState Pointer to the structure. It is not deallocated.
5792	*/
5793	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5794	{
5795	# ifndef VMSVGA_USE_EMT_HALT_CODE
5796	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5797	{
5798	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5799	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5800	}
5801	# endif
5802
5803	if (pSVGAState->Cursor.fActive)
5804	{
5805	RTMemFree(pSVGAState->Cursor.pData);
5806	pSVGAState->Cursor.pData = NULL;
5807	pSVGAState->Cursor.fActive = false;
5808	}
5809
5810	if (pSVGAState->paGMR)
5811	{
5812	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5813	if (pSVGAState->paGMR[i].paDesc)
5814	RTMemFree(pSVGAState->paGMR[i].paDesc);
5815
5816	RTMemFree(pSVGAState->paGMR);
5817	pSVGAState->paGMR = NULL;
5818	}
5819	}
5820
5821	/**
5822	* Constructor for PVMSVGAR3STATE structure.
5823	*
5824	* @returns VBox status code.
5825	* @param pThis The shared VGA/VMSVGA instance data.
5826	* @param pSVGAState Pointer to the structure. It is already allocated.
5827	*/
5828	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5829	{
5830	int rc = VINF_SUCCESS;
5831	RT_ZERO(*pSVGAState);
5832
5833	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5834	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5835
5836	# ifndef VMSVGA_USE_EMT_HALT_CODE
5837	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5838	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5839	AssertRCReturn(rc, rc);
5840	# endif
5841
5842	return rc;
5843	}
5844
5845	/**
5846	* Initializes the host capabilities: registers and FIFO.
5847	*
5848	* @returns VBox status code.
5849	* @param pThis The shared VGA/VMSVGA instance data.
5850	* @param pThisCC The VGA/VMSVGA state for ring-3.
5851	*/
5852	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5853	{
5854	/* Register caps. */
5855	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5856	\| SVGA_CAP_GMR2
5857	\| SVGA_CAP_CURSOR
5858	\| SVGA_CAP_CURSOR_BYPASS_2
5859	\| SVGA_CAP_EXTENDED_FIFO
5860	\| SVGA_CAP_IRQMASK
5861	\| SVGA_CAP_PITCHLOCK
5862	\| SVGA_CAP_TRACES
5863	\| SVGA_CAP_SCREEN_OBJECT_2
5864	\| SVGA_CAP_ALPHA_CURSOR;
5865	# ifdef VBOX_WITH_VMSVGA3D
5866	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5867	# endif
5868
5869	/* Clear the FIFO. */
5870	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5871
5872	/* Setup FIFO capabilities. */
5873	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5874	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5875	\| SVGA_FIFO_CAP_GMR2
5876	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5877	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5878	\| SVGA_FIFO_CAP_RESERVE
5879	\| SVGA_FIFO_CAP_PITCHLOCK;
5880
5881	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5882	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5883	}
5884
5885	# ifdef VBOX_WITH_VMSVGA3D
5886	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5887	static const char * const g_apszVmSvgaDevCapNames[] =
5888	{
5889	"x3D", /* = 0 */
5890	"xMAX_LIGHTS",
5891	"xMAX_TEXTURES",
5892	"xMAX_CLIP_PLANES",
5893	"xVERTEX_SHADER_VERSION",
5894	"xVERTEX_SHADER",
5895	"xFRAGMENT_SHADER_VERSION",
5896	"xFRAGMENT_SHADER",
5897	"xMAX_RENDER_TARGETS",
5898	"xS23E8_TEXTURES",
5899	"xS10E5_TEXTURES",
5900	"xMAX_FIXED_VERTEXBLEND",
5901	"xD16_BUFFER_FORMAT",
5902	"xD24S8_BUFFER_FORMAT",
5903	"xD24X8_BUFFER_FORMAT",
5904	"xQUERY_TYPES",
5905	"xTEXTURE_GRADIENT_SAMPLING",
5906	"rMAX_POINT_SIZE",
5907	"xMAX_SHADER_TEXTURES",
5908	"xMAX_TEXTURE_WIDTH",
5909	"xMAX_TEXTURE_HEIGHT",
5910	"xMAX_VOLUME_EXTENT",
5911	"xMAX_TEXTURE_REPEAT",
5912	"xMAX_TEXTURE_ASPECT_RATIO",
5913	"xMAX_TEXTURE_ANISOTROPY",
5914	"xMAX_PRIMITIVE_COUNT",
5915	"xMAX_VERTEX_INDEX",
5916	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5917	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5918	"xMAX_VERTEX_SHADER_TEMPS",
5919	"xMAX_FRAGMENT_SHADER_TEMPS",
5920	"xTEXTURE_OPS",
5921	"xSURFACEFMT_X8R8G8B8",
5922	"xSURFACEFMT_A8R8G8B8",
5923	"xSURFACEFMT_A2R10G10B10",
5924	"xSURFACEFMT_X1R5G5B5",
5925	"xSURFACEFMT_A1R5G5B5",
5926	"xSURFACEFMT_A4R4G4B4",
5927	"xSURFACEFMT_R5G6B5",
5928	"xSURFACEFMT_LUMINANCE16",
5929	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5930	"xSURFACEFMT_ALPHA8",
5931	"xSURFACEFMT_LUMINANCE8",
5932	"xSURFACEFMT_Z_D16",
5933	"xSURFACEFMT_Z_D24S8",
5934	"xSURFACEFMT_Z_D24X8",
5935	"xSURFACEFMT_DXT1",
5936	"xSURFACEFMT_DXT2",
5937	"xSURFACEFMT_DXT3",
5938	"xSURFACEFMT_DXT4",
5939	"xSURFACEFMT_DXT5",
5940	"xSURFACEFMT_BUMPX8L8V8U8",
5941	"xSURFACEFMT_A2W10V10U10",
5942	"xSURFACEFMT_BUMPU8V8",
5943	"xSURFACEFMT_Q8W8V8U8",
5944	"xSURFACEFMT_CxV8U8",
5945	"xSURFACEFMT_R_S10E5",
5946	"xSURFACEFMT_R_S23E8",
5947	"xSURFACEFMT_RG_S10E5",
5948	"xSURFACEFMT_RG_S23E8",
5949	"xSURFACEFMT_ARGB_S10E5",
5950	"xSURFACEFMT_ARGB_S23E8",
5951	"xMISSING62",
5952	"xMAX_VERTEX_SHADER_TEXTURES",
5953	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5954	"xSURFACEFMT_V16U16",
5955	"xSURFACEFMT_G16R16",
5956	"xSURFACEFMT_A16B16G16R16",
5957	"xSURFACEFMT_UYVY",
5958	"xSURFACEFMT_YUY2",
5959	"xMULTISAMPLE_NONMASKABLESAMPLES",
5960	"xMULTISAMPLE_MASKABLESAMPLES",
5961	"xALPHATOCOVERAGE",
5962	"xSUPERSAMPLE",
5963	"xAUTOGENMIPMAPS",
5964	"xSURFACEFMT_NV12",
5965	"xSURFACEFMT_AYUV",
5966	"xMAX_CONTEXT_IDS",
5967	"xMAX_SURFACE_IDS",
5968	"xSURFACEFMT_Z_DF16",
5969	"xSURFACEFMT_Z_DF24",
5970	"xSURFACEFMT_Z_D24S8_INT",
5971	"xSURFACEFMT_BC4_UNORM",
5972	"xSURFACEFMT_BC5_UNORM", /* 83 */
5973	};
5974
5975	/**
5976	* Initializes the host 3D capabilities in FIFO.
5977	*
5978	* @returns VBox status code.
5979	* @param pThis The shared VGA/VMSVGA instance data.
5980	* @param pThisCC The VGA/VMSVGA state for ring-3.
5981	*/
5982	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
5983	{
5984	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5985	bool fSavedBuffering = RTLogRelSetBuffering(true);
5986	SVGA3dCapsRecord *pCaps;
5987	SVGA3dCapPair *pData;
5988	uint32_t idxCap = 0;
5989
5990	/* 3d hardware version; latest and greatest */
5991	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5992	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5993
5994	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5995	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5996	pData = (SVGA3dCapPair *)&pCaps->data;
5997
5998	/* Fill out all 3d capabilities. */
5999	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6000	{
6001	uint32_t val = 0;
6002
6003	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6004	if (RT_SUCCESS(rc))
6005	{
6006	pData[idxCap][0] = i;
6007	pData[idxCap][1] = val;
6008	idxCap++;
6009	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6010	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6011	else
6012	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6013	&g_apszVmSvgaDevCapNames[i][1]));
6014	}
6015	else
6016	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6017	}
6018	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6019	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6020
6021	/* Mark end of record array. */
6022	pCaps->header.length = 0;
6023
6024	RTLogRelSetBuffering(fSavedBuffering);
6025	}
6026
6027	# endif
6028
6029	/**
6030	* Resets the SVGA hardware state
6031	*
6032	* @returns VBox status code.
6033	* @param pDevIns The device instance.
6034	*/
6035	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6036	{
6037	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6038	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6039	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6040
6041	/* Reset before init? */
6042	if (!pSVGAState)
6043	return VINF_SUCCESS;
6044
6045	Log(("vmsvgaR3Reset\n"));
6046
6047	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6048	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6049	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6050
6051	/* Reset other stuff. */
6052	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6053	RT_ZERO(pThis->svga.au32ScratchRegion);
6054
6055	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6056	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6057
6058	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6059
6060	/* Initialize FIFO and register capabilities. */
6061	vmsvgaR3InitCaps(pThis, pThisCC);
6062
6063	# ifdef VBOX_WITH_VMSVGA3D
6064	if (pThis->svga.f3DEnabled)
6065	vmsvgaR3InitFifo3DCaps(pThisCC);
6066	# endif
6067
6068	/* VRAM tracking is enabled by default during bootup. */
6069	pThis->svga.fVRAMTracking = true;
6070	pThis->svga.fEnabled = false;
6071
6072	/* Invalidate current settings. */
6073	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6074	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6075	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6076	pThis->svga.cbScanline = 0;
6077	pThis->svga.u32PitchLock = 0;
6078
6079	return rc;
6080	}
6081
6082	/**
6083	* Cleans up the SVGA hardware state
6084	*
6085	* @returns VBox status code.
6086	* @param pDevIns The device instance.
6087	*/
6088	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6089	{
6090	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6091	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6092
6093	/*
6094	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6095	*/
6096	if (pThisCC->svga.pFIFOIOThread)
6097	{
6098	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6099	NULL /pvParam/, 30000 /ms/);
6100	AssertLogRelRC(rc);
6101
6102	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6103	AssertLogRelRC(rc);
6104	pThisCC->svga.pFIFOIOThread = NULL;
6105	}
6106
6107	/*
6108	* Destroy the special SVGA state.
6109	*/
6110	if (pThisCC->svga.pSvgaR3State)
6111	{
6112	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6113
6114	RTMemFree(pThisCC->svga.pSvgaR3State);
6115	pThisCC->svga.pSvgaR3State = NULL;
6116	}
6117
6118	/*
6119	* Free our resources residing in the VGA state.
6120	*/
6121	if (pThisCC->svga.pbVgaFrameBufferR3)
6122	{
6123	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6124	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6125	}
6126	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6127	{
6128	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6129	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6130	}
6131	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6132	{
6133	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6134	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6135	}
6136
6137	return VINF_SUCCESS;
6138	}
6139
6140	/**
6141	* Initialize the SVGA hardware state
6142	*
6143	* @returns VBox status code.
6144	* @param pDevIns The device instance.
6145	*/
6146	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6147	{
6148	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6149	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6150	PVMSVGAR3STATE pSVGAState;
6151	int rc;
6152
6153	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6154	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6155
6156	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6157
6158	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6159	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6160	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6161
6162	/* Create event semaphore. */
6163	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6164	AssertRCReturn(rc, rc);
6165
6166	/* Create event semaphore. */
6167	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6168	AssertRCReturn(rc, rc);
6169
6170	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6171	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6172
6173	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6174	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6175
6176	pSVGAState = pThisCC->svga.pSvgaR3State;
6177
6178	/* Initialize FIFO and register capabilities. */
6179	vmsvgaR3InitCaps(pThis, pThisCC);
6180
6181	# ifdef VBOX_WITH_VMSVGA3D
6182	if (pThis->svga.f3DEnabled)
6183	{
6184	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6185	if (RT_FAILURE(rc))
6186	{
6187	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6188	pThis->svga.f3DEnabled = false;
6189	}
6190	}
6191	# endif
6192	/* VRAM tracking is enabled by default during bootup. */
6193	pThis->svga.fVRAMTracking = true;
6194
6195	/* Invalidate current settings. */
6196	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6197	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6198	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6199	pThis->svga.cbScanline = 0;
6200
6201	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6202	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6203	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6204	{
6205	pThis->svga.u32MaxWidth -= 256;
6206	pThis->svga.u32MaxHeight -= 256;
6207	}
6208	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6209
6210	# ifdef DEBUG_GMR_ACCESS
6211	/* Register the GMR access handler type. */
6212	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6213	vmsvgaR3GmrAccessHandler,
6214	NULL, NULL, NULL,
6215	NULL, NULL, NULL,
6216	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6217	AssertRCReturn(rc, rc);
6218	# endif
6219
6220	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6221	/* Register the FIFO access handler type. In addition to
6222	debugging FIFO access, this is also used to facilitate
6223	extended fifo thread sleeps. */
6224	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6225	# ifdef DEBUG_FIFO_ACCESS
6226	PGMPHYSHANDLERKIND_ALL,
6227	# else
6228	PGMPHYSHANDLERKIND_WRITE,
6229	# endif
6230	vmsvgaR3FifoAccessHandler,
6231	NULL, NULL, NULL,
6232	NULL, NULL, NULL,
6233	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6234	AssertRCReturn(rc, rc);
6235	# endif
6236
6237	/* Create the async IO thread. */
6238	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6239	RTTHREADTYPE_IO, "VMSVGA FIFO");
6240	if (RT_FAILURE(rc))
6241	{
6242	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6243	return rc;
6244	}
6245
6246	/*
6247	* Statistics.
6248	*/
6249	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6250	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6251	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6252	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6253	# ifdef VBOX_WITH_STATISTICS
6254	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6255	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6256	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6257	# endif
6258	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6259	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6260	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6261	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6262	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6263	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6264	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6265	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6266	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6267	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6268	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6269	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6270	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6271	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6272	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6273	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6274	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6275	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6276	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6277	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6278	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6279	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6280	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6281	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6282	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6283	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6284	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6285	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6286	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6287	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6288	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6289	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6290	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6291	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6292	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6293	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6294	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6295	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6296	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6297	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6298	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6299	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6300	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6301	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6302	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6303	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6304	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6305	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6306	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6307	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6308	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6309	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6310	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6311	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6312
6313	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6314	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6315	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6316	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6317	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6318	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6319	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6320	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6321	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6322	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6323	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6324	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6325	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6326	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6327	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6328	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6329	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6330	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6331	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6332	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6333	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6334	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6335	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6336	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6337	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6338	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6339	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6340	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6341	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6342	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6343	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6344	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6345
6346	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6347	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6348	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6349	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6350	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6351	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6352	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6353	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6354	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6355	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6356	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6357	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6358	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6359	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6360	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6361	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6362	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6363	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6364	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6365	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6366	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6367	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6368	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6369	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6370	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6371	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6372	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6373	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6374	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6375	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6376	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6377	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6378	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6379	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6380	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6381	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6382	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6383	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6384	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6385	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6386	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6387	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6388	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6389	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6390	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6391	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6392	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6393	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6394	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6395
6396	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6397	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6398	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6399	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6400	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6401	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6402	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6403	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6404	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6405	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6406	# endif
6407	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6408	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6409	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6410	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6411	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6412
6413	# undef REG_CNT
6414	# undef REG_PRF
6415
6416	/*
6417	* Info handlers.
6418	*/
6419	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6420	# ifdef VBOX_WITH_VMSVGA3D
6421	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6422	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6423	"VMSVGA 3d surface details. "
6424	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6425	vmsvgaR3Info3dSurface);
6426	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6427	"VMSVGA 3d surface details and bitmap: "
6428	"sid[>dir]",
6429	vmsvgaR3Info3dSurfaceBmp);
6430	# endif
6431
6432	return VINF_SUCCESS;
6433	}
6434
6435	/**
6436	* Power On notification.
6437	*
6438	* @returns VBox status code.
6439	* @param pDevIns The device instance data.
6440	*
6441	* @remarks Caller enters the device critical section.
6442	*/
6443	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6444	{
6445	# ifdef VBOX_WITH_VMSVGA3D
6446	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6447	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6448	if (pThis->svga.f3DEnabled)
6449	{
6450	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6451
6452	if (RT_SUCCESS(rc))
6453	{
6454	/* Initialize FIFO 3D capabilities. */
6455	vmsvgaR3InitFifo3DCaps(pThisCC);
6456	}
6457	}
6458	# else /* !VBOX_WITH_VMSVGA3D */
6459	RT_NOREF(pDevIns);
6460	# endif /* !VBOX_WITH_VMSVGA3D */
6461	}
6462
6463	#endif /* IN_RING3 */
6464

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82254

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