DevVGA-SVGA.cpp@ 90894

Last change on this file since 90894 was 90852, checked in by vboxsync, 3 years ago
Devices/Graphics: Update cbScanline after changing uWidth and uBpp
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1	/* $Id: DevVGA-SVGA.cpp 90852 2021-08-24 16:53:54Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - LogRel for the usual important stuff.
15	* - LogRel2 for cursor.
16	* - LogRel3 for 3D performance data.
17	* - LogRel4 for HW accelerated graphics output.
18	*/
19
20	/*
21	* Copyright (C) 2013-2020 Oracle Corporation
22	*
23	* This file is part of VirtualBox Open Source Edition (OSE), as
24	* available from http://www.virtualbox.org. This file is free software;
25	* you can redistribute it and/or modify it under the terms of the GNU
26	* General Public License (GPL) as published by the Free Software
27	* Foundation, in version 2 as it comes in the "COPYING" file of the
28	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30	*/
31
32
33	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
34	*
35	* This device emulation was contributed by trivirt AG. It offers an
36	* alternative to our Bochs based VGA graphics and 3d emulations. This is
37	* valuable for Xorg based guests, as there is driver support shipping with Xorg
38	* since it forked from XFree86.
39	*
40	*
41	* @section sec_dev_vmsvga_sdk The VMware SDK
42	*
43	* This is officially deprecated now, however it's still quite useful,
44	* especially for getting the old features working:
45	* http://vmware-svga.sourceforge.net/
46	*
47	* They currently point developers at the following resources.
48	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
49	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
50	* - http://cgit.freedesktop.org/mesa/vmwgfx/
51	*
52	* @subsection subsec_dev_vmsvga_sdk_results Test results
53	*
54	* Test results:
55	* - 2dmark.img:
56	* + todo
57	* - backdoor-tclo.img:
58	* + todo
59	* - blit-cube.img:
60	* + todo
61	* - bunnies.img:
62	* + todo
63	* - cube.img:
64	* + todo
65	* - cubemark.img:
66	* + todo
67	* - dynamic-vertex-stress.img:
68	* + todo
69	* - dynamic-vertex.img:
70	* + todo
71	* - fence-stress.img:
72	* + todo
73	* - gmr-test.img:
74	* + todo
75	* - half-float-test.img:
76	* + todo
77	* - noscreen-cursor.img:
78	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
79	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
80	* visible though.)
81	* - Cursor animation via the palette doesn't work.
82	* - During debugging, it turns out that the framebuffer content seems to
83	* be halfways ignore or something (memset(fb, 0xcc, lots)).
84	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
85	* grow it 0x10 fold (128KB -> 2MB like in WS10).
86	* - null.img:
87	* + todo
88	* - pong.img:
89	* + todo
90	* - presentReadback.img:
91	* + todo
92	* - resolution-set.img:
93	* + todo
94	* - rt-gamma-test.img:
95	* + todo
96	* - screen-annotation.img:
97	* + todo
98	* - screen-cursor.img:
99	* + todo
100	* - screen-dma-coalesce.img:
101	* + todo
102	* - screen-gmr-discontig.img:
103	* + todo
104	* - screen-gmr-remap.img:
105	* + todo
106	* - screen-multimon.img:
107	* + todo
108	* - screen-present-clip.img:
109	* + todo
110	* - screen-render-test.img:
111	* + todo
112	* - screen-simple.img:
113	* + todo
114	* - screen-text.img:
115	* + todo
116	* - simple-shaders.img:
117	* + todo
118	* - simple_blit.img:
119	* + todo
120	* - tiny-2d-updates.img:
121	* + todo
122	* - video-formats.img:
123	* + todo
124	* - video-sync.img:
125	* + todo
126	*
127	*/
128
129
130	/*********************************************************************************************************************************
131	* Header Files *
132	*********************************************************************************************************************************/
133	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
134	#include <VBox/vmm/pdmdev.h>
135	#include <VBox/version.h>
136	#include <VBox/err.h>
137	#include <VBox/log.h>
138	#include <VBox/vmm/pgm.h>
139	#include <VBox/sup.h>
140
141	#include <iprt/assert.h>
142	#include <iprt/semaphore.h>
143	#include <iprt/uuid.h>
144	#ifdef IN_RING3
145	# include <iprt/ctype.h>
146	# include <iprt/mem.h>
147	# ifdef VBOX_STRICT
148	# include <iprt/time.h>
149	# endif
150	#endif
151
152	#include <VBox/AssertGuest.h>
153	#include <VBox/VMMDev.h>
154	#include <VBoxVideo.h>
155	#include <VBox/bioslogo.h>
156
157	#ifdef LOG_ENABLED
158	#include "svgadump/svga_dump.h"
159	#endif
160
161	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
162	#include "DevVGA.h"
163
164	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
165	#ifdef VBOX_WITH_VMSVGA3D
166	# include "DevVGA-SVGA3d.h"
167	# ifdef RT_OS_DARWIN
168	# include "DevVGA-SVGA3d-cocoa.h"
169	# endif
170	# ifdef RT_OS_LINUX
171	# ifdef IN_RING3
172	# include "DevVGA-SVGA3d-glLdr.h"
173	# endif
174	# endif
175	#endif
176	#ifdef IN_RING3
177	#include "DevVGA-SVGA-internal.h"
178	#endif
179
180
181	/*********************************************************************************************************************************
182	* Defined Constants And Macros *
183	*********************************************************************************************************************************/
184	/**
185	* Macro for checking if a fixed FIFO register is valid according to the
186	* current FIFO configuration.
187	*
188	* @returns true / false.
189	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
190	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
191	*/
192	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
193
194
195	/*********************************************************************************************************************************
196	* Structures and Typedefs *
197	*********************************************************************************************************************************/
198
199
200	/*********************************************************************************************************************************
201	* Internal Functions *
202	*********************************************************************************************************************************/
203	#ifdef IN_RING3
204	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
205	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
206	# endif
207	# ifdef DEBUG_GMR_ACCESS
208	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
209	# endif
210	#endif
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216	#ifdef IN_RING3
217
218	/**
219	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
220	*/
221	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
222	{
223	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
224	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
225	SSMFIELD_ENTRY_TERM()
226	};
227
228	/**
229	* SSM descriptor table for the GMR structure.
230	*/
231	static SSMFIELD const g_aGMRFields[] =
232	{
233	SSMFIELD_ENTRY( GMR, cMaxPages),
234	SSMFIELD_ENTRY( GMR, cbTotal),
235	SSMFIELD_ENTRY( GMR, numDescriptors),
236	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
237	SSMFIELD_ENTRY_TERM()
238	};
239
240	/**
241	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
242	*/
243	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
244	{
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
250	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
251	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
252	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
253	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
254	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
255	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
256	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
257	SSMFIELD_ENTRY_TERM()
258	};
259
260	/**
261	* SSM descriptor table for the VMSVGAR3STATE structure.
262	*/
263	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
264	{
265	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
267	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
269	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
270	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
271	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
272	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
273	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
274	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
276	#ifdef VMSVGA_USE_EMT_HALT_CODE
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
278	#else
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
280	#endif
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
344
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
349
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
357	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
359	# endif
360	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
364
365	SSMFIELD_ENTRY_TERM()
366	};
367
368	/**
369	* SSM descriptor table for the VGAState.svga structure.
370	*/
371	static SSMFIELD const g_aVGAStateSVGAFields[] =
372	{
373	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
375	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
376	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
377	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
378	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
379	SSMFIELD_ENTRY( VMSVGAState, fBusy),
380	SSMFIELD_ENTRY( VMSVGAState, fTraces),
381	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
382	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
383	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
384	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
385	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
386	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
387	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
388	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
389	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
393	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
394	SSMFIELD_ENTRY( VMSVGAState, uWidth),
395	SSMFIELD_ENTRY( VMSVGAState, uHeight),
396	SSMFIELD_ENTRY( VMSVGAState, uBpp),
397	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
398	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
399	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
400	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
401	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
402	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
403	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
404	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
405	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
406	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
407	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
411	SSMFIELD_ENTRY_TERM()
412	};
413	#endif /* IN_RING3 */
414
415
416	/*********************************************************************************************************************************
417	* Internal Functions *
418	*********************************************************************************************************************************/
419	#ifdef IN_RING3
420	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
421	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
422	uint32_t uVersion, uint32_t uPass);
423	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
424	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
425	#endif /* IN_RING3 */
426
427
428	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
429	#if defined(LOG_ENABLED)
430	/**
431	* Index register string name lookup
432	*
433	* @returns Index register string or "UNKNOWN"
434	* @param pThis The shared VGA/VMSVGA state.
435	* @param idxReg The index register.
436	*/
437	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
438	{
439	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
440	switch (idxReg)
441	{
442	SVGA_CASE_ID2STR(SVGA_REG_ID);
443	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
444	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
445	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
446	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
447	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
448	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
449	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
450	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
451	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
452	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
453	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
454	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
455	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
456	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
457	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
458	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
459
460	/* ID 0 implementation only had the above registers, then the palette */
461	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
462	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
463	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
464	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
465	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
466	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
467	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
468	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
469	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
470	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
471	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
472	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
473	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
474	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
475	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
476	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
477	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
478
479	/* Legacy multi-monitor support */
480	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
481	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
482	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
483	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
484	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
485	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
486	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
487
488	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
489	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
490	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
491	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
492
493	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
494	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
495	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
496	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
497	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
498	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
499	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
500	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
501	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
502	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
503	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
504	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
505	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
506	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
507	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
508	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
509	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
510	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
511	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
512	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
513	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
514	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
515	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
516	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
517	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
518	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
519	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
520	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
521	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
522	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
523	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
524	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
525	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
526
527	default:
528	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
529	return "SVGA_SCRATCH_BASE reg";
530	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
531	return "SVGA_PALETTE_BASE reg";
532	return "UNKNOWN";
533	}
534	}
535	#endif /* LOG_ENABLED */
536
537	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
538	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
539	{
540	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
541	switch (idxDevCap)
542	{
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
804
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
806
807	default:
808	break;
809	}
810	return "UNKNOWN";
811	}
812	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
813	#undef SVGA_CASE_ID2STR
814
815
816	#ifdef IN_RING3
817
818	/**
819	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
820	*/
821	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
822	{
823	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
824	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
825
826	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
827	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
828
829	/** @todo Test how it interacts with multiple screen objects. */
830	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
831	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
832	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
833
834	if (x < uWidth)
835	{
836	pThis->svga.viewport.x = x;
837	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
838	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
839	}
840	else
841	{
842	pThis->svga.viewport.x = uWidth;
843	pThis->svga.viewport.cx = 0;
844	pThis->svga.viewport.xRight = uWidth;
845	}
846	if (y < uHeight)
847	{
848	pThis->svga.viewport.y = y;
849	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
850	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
851	pThis->svga.viewport.yHighWC = uHeight - y;
852	}
853	else
854	{
855	pThis->svga.viewport.y = uHeight;
856	pThis->svga.viewport.cy = 0;
857	pThis->svga.viewport.yLowWC = 0;
858	pThis->svga.viewport.yHighWC = 0;
859	}
860
861	# ifdef VBOX_WITH_VMSVGA3D
862	/*
863	* Now inform the 3D backend.
864	*/
865	if (pThis->svga.f3DEnabled)
866	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
867	# else
868	RT_NOREF(OldViewport);
869	# endif
870	}
871
872
873	/**
874	* Updating screen information in API
875	*
876	* @param pThis The The shared VGA/VMSVGA instance data.
877	* @param pThisCC The VGA/VMSVGA state for ring-3.
878	*/
879	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
880	{
881	int rc;
882
883	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
884
885	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
886	{
887	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
888	if (!pScreen->fModified)
889	continue;
890
891	pScreen->fModified = false;
892
893	VBVAINFOVIEW view;
894	RT_ZERO(view);
895	view.u32ViewIndex = pScreen->idScreen;
896	// view.u32ViewOffset = 0;
897	view.u32ViewSize = pThis->vram_size;
898	view.u32MaxScreenSize = pThis->vram_size;
899
900	VBVAINFOSCREEN screen;
901	RT_ZERO(screen);
902	screen.u32ViewIndex = pScreen->idScreen;
903
904	if (pScreen->fDefined)
905	{
906	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
907	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
908	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
909	{
910	Assert(pThis->svga.fGFBRegisters);
911	continue;
912	}
913
914	screen.i32OriginX = pScreen->xOrigin;
915	screen.i32OriginY = pScreen->yOrigin;
916	screen.u32StartOffset = pScreen->offVRAM;
917	screen.u32LineSize = pScreen->cbPitch;
918	screen.u32Width = pScreen->cWidth;
919	screen.u32Height = pScreen->cHeight;
920	screen.u16BitsPerPixel = pScreen->cBpp;
921	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
922	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
923	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
924	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
925	}
926	else
927	{
928	/* Screen is destroyed. */
929	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
930	}
931
932	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
933	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
934	AssertRC(rc);
935	}
936	}
937
938
939	/**
940	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
941	*
942	* Used to update screen offsets (positions) since appearently vmwgfx fails to
943	* pass correct offsets thru FIFO.
944	*/
945	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
946	{
947	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
948	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
949	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
950
951	AssertReturnVoid(pSVGAState);
952
953	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
954	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
955	for (uint32_t i = 0; i < cPositions; ++i)
956	{
957	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
958	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
959	continue;
960
961	if (paPositions[i].x == -1)
962	continue;
963	if (paPositions[i].y == -1)
964	continue;
965
966	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
967	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
968	pSVGAState->aScreens[i].fModified = true;
969	}
970
971	vmsvgaR3VBVAResize(pThis, pThisCC);
972	}
973
974	#endif /* IN_RING3 */
975
976	/**
977	* Read port register
978	*
979	* @returns VBox status code.
980	* @param pDevIns The device instance.
981	* @param pThis The shared VGA/VMSVGA state.
982	* @param pu32 Where to store the read value
983	*/
984	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
985	{
986	#ifdef IN_RING3
987	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
988	#endif
989	int rc = VINF_SUCCESS;
990	*pu32 = 0;
991
992	/* Rough index register validation. */
993	uint32_t idxReg = pThis->svga.u32IndexReg;
994	#if !defined(IN_RING3) && defined(VBOX_STRICT)
995	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
996	VINF_IOM_R3_IOPORT_READ);
997	#else
998	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1000	VINF_SUCCESS);
1001	#endif
1002	RT_UNTRUSTED_VALIDATED_FENCE();
1003
1004	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1005	if ( idxReg >= SVGA_REG_ID_0_TOP
1006	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1007	{
1008	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1009	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1010	}
1011
1012	switch (idxReg)
1013	{
1014	case SVGA_REG_ID:
1015	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1016	*pu32 = pThis->svga.u32SVGAId;
1017	break;
1018
1019	case SVGA_REG_ENABLE:
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1021	*pu32 = pThis->svga.fEnabled;
1022	break;
1023
1024	case SVGA_REG_WIDTH:
1025	{
1026	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1027	if ( pThis->svga.fEnabled
1028	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1029	*pu32 = pThis->svga.uWidth;
1030	else
1031	{
1032	#ifndef IN_RING3
1033	rc = VINF_IOM_R3_IOPORT_READ;
1034	#else
1035	*pu32 = pThisCC->pDrv->cx;
1036	#endif
1037	}
1038	break;
1039	}
1040
1041	case SVGA_REG_HEIGHT:
1042	{
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1044	if ( pThis->svga.fEnabled
1045	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1046	*pu32 = pThis->svga.uHeight;
1047	else
1048	{
1049	#ifndef IN_RING3
1050	rc = VINF_IOM_R3_IOPORT_READ;
1051	#else
1052	*pu32 = pThisCC->pDrv->cy;
1053	#endif
1054	}
1055	break;
1056	}
1057
1058	case SVGA_REG_MAX_WIDTH:
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1060	*pu32 = pThis->svga.u32MaxWidth;
1061	break;
1062
1063	case SVGA_REG_MAX_HEIGHT:
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1065	*pu32 = pThis->svga.u32MaxHeight;
1066	break;
1067
1068	case SVGA_REG_DEPTH:
1069	/* This returns the color depth of the current mode. */
1070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1071	switch (pThis->svga.uBpp)
1072	{
1073	case 15:
1074	case 16:
1075	case 24:
1076	*pu32 = pThis->svga.uBpp;
1077	break;
1078
1079	default:
1080	case 32:
1081	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1082	break;
1083	}
1084	break;
1085
1086	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1087	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1088	*pu32 = pThis->svga.uHostBpp;
1089	break;
1090
1091	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1092	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1093	*pu32 = pThis->svga.uBpp;
1094	break;
1095
1096	case SVGA_REG_PSEUDOCOLOR:
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1098	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1099	break;
1100
1101	case SVGA_REG_RED_MASK:
1102	case SVGA_REG_GREEN_MASK:
1103	case SVGA_REG_BLUE_MASK:
1104	{
1105	uint32_t uBpp;
1106
1107	if (pThis->svga.fEnabled)
1108	uBpp = pThis->svga.uBpp;
1109	else
1110	uBpp = pThis->svga.uHostBpp;
1111
1112	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1113	switch (uBpp)
1114	{
1115	case 8:
1116	u32RedMask = 0x07;
1117	u32GreenMask = 0x38;
1118	u32BlueMask = 0xc0;
1119	break;
1120
1121	case 15:
1122	u32RedMask = 0x0000001f;
1123	u32GreenMask = 0x000003e0;
1124	u32BlueMask = 0x00007c00;
1125	break;
1126
1127	case 16:
1128	u32RedMask = 0x0000001f;
1129	u32GreenMask = 0x000007e0;
1130	u32BlueMask = 0x0000f800;
1131	break;
1132
1133	case 24:
1134	case 32:
1135	default:
1136	u32RedMask = 0x00ff0000;
1137	u32GreenMask = 0x0000ff00;
1138	u32BlueMask = 0x000000ff;
1139	break;
1140	}
1141	switch (idxReg)
1142	{
1143	case SVGA_REG_RED_MASK:
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1145	*pu32 = u32RedMask;
1146	break;
1147
1148	case SVGA_REG_GREEN_MASK:
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1150	*pu32 = u32GreenMask;
1151	break;
1152
1153	case SVGA_REG_BLUE_MASK:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1155	*pu32 = u32BlueMask;
1156	break;
1157	}
1158	break;
1159	}
1160
1161	case SVGA_REG_BYTES_PER_LINE:
1162	{
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1164	if ( pThis->svga.fEnabled
1165	&& pThis->svga.cbScanline)
1166	*pu32 = pThis->svga.cbScanline;
1167	else
1168	{
1169	#ifndef IN_RING3
1170	rc = VINF_IOM_R3_IOPORT_READ;
1171	#else
1172	*pu32 = pThisCC->pDrv->cbScanline;
1173	#endif
1174	}
1175	break;
1176	}
1177
1178	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1180	*pu32 = pThis->vram_size;
1181	break;
1182
1183	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1185	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1186	*pu32 = pThis->GCPhysVRAM;
1187	break;
1188
1189	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1191	/* Always zero in our case. */
1192	*pu32 = 0;
1193	break;
1194
1195	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1196	{
1197	#ifndef IN_RING3
1198	rc = VINF_IOM_R3_IOPORT_READ;
1199	#else
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1201
1202	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1203	if ( pThis->svga.fEnabled
1204	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1205	{
1206	/* Hardware enabled; return real framebuffer size .*/
1207	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1208	}
1209	else
1210	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1211
1212	pu32 = RT_MIN(pThis->vram_size, pu32);
1213	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1214	#endif
1215	break;
1216	}
1217
1218	case SVGA_REG_CAPABILITIES:
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1220	*pu32 = pThis->svga.u32DeviceCaps;
1221	break;
1222
1223	case SVGA_REG_MEM_START: /* FIFO start */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1225	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1226	*pu32 = pThis->svga.GCPhysFIFO;
1227	break;
1228
1229	case SVGA_REG_MEM_SIZE: /* FIFO size */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1231	*pu32 = pThis->svga.cbFIFO;
1232	break;
1233
1234	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1236	*pu32 = pThis->svga.fConfigured;
1237	break;
1238
1239	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1241	*pu32 = 0;
1242	break;
1243
1244	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1245	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1246	if (pThis->svga.fBusy)
1247	{
1248	#ifndef IN_RING3
1249	/* Go to ring-3 and halt the CPU. */
1250	rc = VINF_IOM_R3_IOPORT_READ;
1251	RT_NOREF(pDevIns);
1252	break;
1253	#else /* IN_RING3 */
1254	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1255	/* The guest is basically doing a HLT via the device here, but with
1256	a special wake up condition on FIFO completion. */
1257	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1258	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1259	PVM pVM = PDMDevHlpGetVM(pDevIns);
1260	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1261	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1262	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1263	if (pThis->svga.fBusy)
1264	{
1265	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1266	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1267	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1268	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1269	}
1270	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1271	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1272	# else
1273
1274	/* Delay the EMT a bit so the FIFO and others can get some work done.
1275	This used to be a crude 50 ms sleep. The current code tries to be
1276	more efficient, but the consept is still very crude. */
1277	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1278	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1279	RTThreadYield();
1280	if (pThis->svga.fBusy)
1281	{
1282	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1283
1284	if (pThis->svga.fBusy && cRefs == 1)
1285	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1286	if (pThis->svga.fBusy)
1287	{
1288	/** @todo If this code is going to stay, we need to call into the halt/wait
1289	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1290	* suffer when the guest is polling on a busy FIFO. */
1291	uint64_t uIgnored1, uIgnored2;
1292	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1293	if (cNsMaxWait >= RT_NS_100US)
1294	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1295	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1296	RT_MIN(cNsMaxWait, RT_NS_10MS));
1297	}
1298
1299	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1300	}
1301	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1302	# endif
1303	*pu32 = pThis->svga.fBusy != 0;
1304	#endif /* IN_RING3 */
1305	}
1306	else
1307	*pu32 = false;
1308	break;
1309
1310	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1311	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1312	*pu32 = pThis->svga.u32GuestId;
1313	break;
1314
1315	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1316	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1317	*pu32 = pThis->svga.cScratchRegion;
1318	break;
1319
1320	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1321	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1322	*pu32 = SVGA_FIFO_NUM_REGS;
1323	break;
1324
1325	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1326	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1327	*pu32 = pThis->svga.u32PitchLock;
1328	break;
1329
1330	case SVGA_REG_IRQMASK: /* Interrupt mask */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1332	*pu32 = pThis->svga.u32IrqMask;
1333	break;
1334
1335	/* See "Guest memory regions" below. */
1336	case SVGA_REG_GMR_ID:
1337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1338	*pu32 = pThis->svga.u32CurrentGMRId;
1339	break;
1340
1341	case SVGA_REG_GMR_DESCRIPTOR:
1342	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1343	/* Write only */
1344	*pu32 = 0;
1345	break;
1346
1347	case SVGA_REG_GMR_MAX_IDS:
1348	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1349	*pu32 = pThis->svga.cGMR;
1350	break;
1351
1352	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1353	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1354	*pu32 = VMSVGA_MAX_GMR_PAGES;
1355	break;
1356
1357	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1358	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1359	*pu32 = pThis->svga.fTraces;
1360	break;
1361
1362	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1363	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1364	*pu32 = VMSVGA_MAX_GMR_PAGES;
1365	break;
1366
1367	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1368	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1369	*pu32 = VMSVGA_SURFACE_SIZE;
1370	break;
1371
1372	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1373	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1374	break;
1375
1376	/* Mouse cursor support. */
1377	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1378	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1379	*pu32 = pThis->svga.uCursorID;
1380	break;
1381
1382	case SVGA_REG_CURSOR_X:
1383	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1384	*pu32 = pThis->svga.uCursorX;
1385	break;
1386
1387	case SVGA_REG_CURSOR_Y:
1388	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1389	*pu32 = pThis->svga.uCursorY;
1390	break;
1391
1392	case SVGA_REG_CURSOR_ON:
1393	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1394	*pu32 = pThis->svga.uCursorOn;
1395	break;
1396
1397	/* Legacy multi-monitor support */
1398	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1399	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1400	*pu32 = 1;
1401	break;
1402
1403	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1404	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1405	*pu32 = 0;
1406	break;
1407
1408	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1409	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1410	*pu32 = 0;
1411	break;
1412
1413	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1414	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1415	*pu32 = 0;
1416	break;
1417
1418	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1419	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1420	*pu32 = 0;
1421	break;
1422
1423	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1424	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1425	*pu32 = pThis->svga.uWidth;
1426	break;
1427
1428	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1429	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1430	*pu32 = pThis->svga.uHeight;
1431	break;
1432
1433	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1434	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1435	/* We must return something sensible here otherwise the Linux driver
1436	will take a legacy code path without 3d support. This number also
1437	limits how many screens Linux guests will allow. */
1438	*pu32 = pThis->cMonitors;
1439	break;
1440
1441	/*
1442	* SVGA_CAP_GBOBJECTS+ registers.
1443	*/
1444	case SVGA_REG_COMMAND_LOW:
1445	/* Lower 32 bits of command buffer physical address. */
1446	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1447	*pu32 = pThis->svga.u32RegCommandLow;
1448	break;
1449
1450	case SVGA_REG_COMMAND_HIGH:
1451	/* Upper 32 bits of command buffer PA. */
1452	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1453	*pu32 = pThis->svga.u32RegCommandHigh;
1454	break;
1455
1456	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1457	/* Max primary (screen) memory. */
1458	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1459	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1460	break;
1461
1462	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1463	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1464	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1465	*pu32 = pThis->vram_size / 1024;
1466	break;
1467
1468	case SVGA_REG_DEV_CAP:
1469	/* Write dev cap index, read value */
1470	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1471	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1472	{
1473	RT_UNTRUSTED_VALIDATED_FENCE();
1474	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1475	}
1476	else
1477	*pu32 = 0;
1478	break;
1479
1480	case SVGA_REG_CMD_PREPEND_LOW:
1481	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1482	pu32 = 0; / Not supported. */
1483	break;
1484
1485	case SVGA_REG_CMD_PREPEND_HIGH:
1486	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1487	pu32 = 0; / Not supported. */
1488	break;
1489
1490	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1491	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1492	*pu32 = pThis->svga.u32MaxWidth;
1493	break;
1494
1495	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1496	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1497	*pu32 = pThis->svga.u32MaxHeight;
1498	break;
1499
1500	case SVGA_REG_MOB_MAX_SIZE:
1501	/* Essentially the max texture size */
1502	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1503	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1504	break;
1505
1506	default:
1507	{
1508	uint32_t offReg;
1509	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1510	{
1511	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1512	RT_UNTRUSTED_VALIDATED_FENCE();
1513	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1514	}
1515	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1516	{
1517	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1518	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1519	RT_UNTRUSTED_VALIDATED_FENCE();
1520	uint32_t u32 = pThis->last_palette[offReg / 3];
1521	switch (offReg % 3)
1522	{
1523	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1524	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1525	case 2: pu32 = u32 & 0xff; break; / blue */
1526	}
1527	}
1528	else
1529	{
1530	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1531	rc = VINF_IOM_R3_IOPORT_READ;
1532	#else
1533	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1534
1535	/* Do not assert. The guest might be reading all registers. */
1536	LogFunc(("Unknown reg=%#x\n", idxReg));
1537	#endif
1538	}
1539	break;
1540	}
1541	}
1542	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1543	return rc;
1544	}
1545
1546	#ifdef IN_RING3
1547	/**
1548	* Apply the current resolution settings to change the video mode.
1549	*
1550	* @returns VBox status code.
1551	* @param pThis The shared VGA state.
1552	* @param pThisCC The ring-3 VGA state.
1553	*/
1554	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1555	{
1556	/* Always do changemode on FIFO thread. */
1557	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1558
1559	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1560
1561	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1562
1563	if (pThis->svga.fGFBRegisters)
1564	{
1565	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1566	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1567	* deletes all screens other than screen #0, and redefines screen
1568	* #0 according to the specified mode. Drivers that use
1569	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1570	*/
1571
1572	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1573	pScreen->fDefined = true;
1574	pScreen->fModified = true;
1575	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1576	pScreen->idScreen = 0;
1577	pScreen->xOrigin = 0;
1578	pScreen->yOrigin = 0;
1579	pScreen->offVRAM = 0;
1580	pScreen->cbPitch = pThis->svga.cbScanline;
1581	pScreen->cWidth = pThis->svga.uWidth;
1582	pScreen->cHeight = pThis->svga.uHeight;
1583	pScreen->cBpp = pThis->svga.uBpp;
1584
1585	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1586	{
1587	/* Delete screen. */
1588	pScreen = &pSVGAState->aScreens[iScreen];
1589	if (pScreen->fDefined)
1590	{
1591	pScreen->fModified = true;
1592	pScreen->fDefined = false;
1593	}
1594	}
1595	}
1596	else
1597	{
1598	/* "If Screen Objects are supported, they can be used to fully
1599	* replace the functionality provided by the framebuffer registers
1600	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1601	*/
1602	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1603	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1604	pThis->svga.uBpp = pThis->svga.uHostBpp;
1605	}
1606
1607	vmsvgaR3VBVAResize(pThis, pThisCC);
1608
1609	/* Last stuff. For the VGA device screenshot. */
1610	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1611	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1612	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1613	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1614	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1615
1616	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1617	if ( pThis->svga.viewport.cx == 0
1618	&& pThis->svga.viewport.cy == 0)
1619	{
1620	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1621	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1622	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1623	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1624	pThis->svga.viewport.yLowWC = 0;
1625	}
1626
1627	return VINF_SUCCESS;
1628	}
1629
1630	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1631	{
1632	VBVACMDHDR cmd;
1633	cmd.x = (int16_t)(pScreen->xOrigin + x);
1634	cmd.y = (int16_t)(pScreen->yOrigin + y);
1635	cmd.w = (uint16_t)w;
1636	cmd.h = (uint16_t)h;
1637
1638	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1639	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1640	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1641	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1642
1643	return VINF_SUCCESS;
1644	}
1645
1646	#endif /* IN_RING3 */
1647	#if defined(IN_RING0) \|\| defined(IN_RING3)
1648
1649	/**
1650	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1651	*
1652	* @param pThis The shared VGA/VMSVGA instance data.
1653	* @param pThisCC The VGA/VMSVGA state for the current context.
1654	* @param fState The busy state.
1655	*/
1656	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1657	{
1658	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1659
1660	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1661	{
1662	/* Race / unfortunately scheduling. Highly unlikly. */
1663	uint32_t cLoops = 64;
1664	do
1665	{
1666	ASMNopPause();
1667	fState = (pThis->svga.fBusy != 0);
1668	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1669	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1670	}
1671	}
1672
1673
1674	/**
1675	* Update the scanline pitch in response to the guest changing mode
1676	* width/bpp.
1677	*
1678	* @param pThis The shared VGA/VMSVGA state.
1679	* @param pThisCC The VGA/VMSVGA state for the current context.
1680	*/
1681	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1682	{
1683	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1684	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1685	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1686	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1687
1688	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1689	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1690	* location but it has a different meaning.
1691	*/
1692	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1693	uFifoPitchLock = 0;
1694
1695	/* Sanitize values. */
1696	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1697	uFifoPitchLock = 0;
1698	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1699	uRegPitchLock = 0;
1700
1701	/* Prefer the register value to the FIFO value.*/
1702	if (uRegPitchLock)
1703	pThis->svga.cbScanline = uRegPitchLock;
1704	else if (uFifoPitchLock)
1705	pThis->svga.cbScanline = uFifoPitchLock;
1706	else
1707	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1708
1709	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1710	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1711	}
1712
1713	#endif /* IN_RING0 \|\| IN_RING3 */
1714
1715	#ifdef IN_RING3
1716
1717	/**
1718	* Sends cursor position and visibility information from legacy
1719	* SVGA registers to the front-end.
1720	*/
1721	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1722	{
1723	/*
1724	* Writing the X/Y/ID registers does not trigger changes; only writing the
1725	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1726	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1727	* register if they don't have to.
1728	*/
1729	uint32_t x, y, idScreen;
1730	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1731
1732	x = pThis->svga.uCursorX;
1733	y = pThis->svga.uCursorY;
1734	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1735
1736	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1737	* were extended as follows:
1738	*
1739	* SVGA_CURSOR_ON_HIDE 0
1740	* SVGA_CURSOR_ON_SHOW 1
1741	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1742	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1743	*
1744	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1745	* distinguish between the non-zero values but still remember them.
1746	*/
1747	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1748	{
1749	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1750	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1751	}
1752	pThis->svga.uCursorOn = uCursorOn;
1753	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1754	}
1755
1756	#endif /* IN_RING3 */
1757
1758
1759	/**
1760	* Write port register
1761	*
1762	* @returns Strict VBox status code.
1763	* @param pDevIns The device instance.
1764	* @param pThis The shared VGA/VMSVGA state.
1765	* @param pThisCC The VGA/VMSVGA state for the current context.
1766	* @param u32 Value to write
1767	*/
1768	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1769	{
1770	#ifdef IN_RING3
1771	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1772	#endif
1773	VBOXSTRICTRC rc = VINF_SUCCESS;
1774	RT_NOREF(pThisCC);
1775
1776	/* Rough index register validation. */
1777	uint32_t idxReg = pThis->svga.u32IndexReg;
1778	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1779	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1780	VINF_IOM_R3_IOPORT_WRITE);
1781	#else
1782	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1783	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1784	VINF_SUCCESS);
1785	#endif
1786	RT_UNTRUSTED_VALIDATED_FENCE();
1787
1788	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1789	if ( idxReg >= SVGA_REG_ID_0_TOP
1790	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1791	{
1792	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1793	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1794	}
1795	#ifdef LOG_ENABLED
1796	if (idxReg != SVGA_REG_DEV_CAP)
1797	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1798	else
1799	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1800	#endif
1801	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1802	switch (idxReg)
1803	{
1804	case SVGA_REG_WIDTH:
1805	case SVGA_REG_HEIGHT:
1806	case SVGA_REG_PITCHLOCK:
1807	case SVGA_REG_BITS_PER_PIXEL:
1808	pThis->svga.fGFBRegisters = true;
1809	break;
1810	default:
1811	break;
1812	}
1813
1814	switch (idxReg)
1815	{
1816	case SVGA_REG_ID:
1817	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1818	if ( u32 == SVGA_ID_0
1819	\|\| u32 == SVGA_ID_1
1820	\|\| u32 == SVGA_ID_2)
1821	pThis->svga.u32SVGAId = u32;
1822	else
1823	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1824	break;
1825
1826	case SVGA_REG_ENABLE:
1827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1828	#ifdef IN_RING3
1829	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1830	&& pThis->svga.fEnabled == false)
1831	{
1832	/* Make a backup copy of the first 512kb in order to save font data etc. */
1833	/** @todo should probably swap here, rather than copy + zero */
1834	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1835	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1836	}
1837
1838	pThis->svga.fEnabled = u32;
1839	if (pThis->svga.fEnabled)
1840	{
1841	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1842	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1843	{
1844	/* Keep the current mode. */
1845	pThis->svga.uWidth = pThisCC->pDrv->cx;
1846	pThis->svga.uHeight = pThisCC->pDrv->cy;
1847	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1848	vmsvgaHCUpdatePitch(pThis, pThisCC);
1849	}
1850
1851	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1852	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1853	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1854	# ifdef LOG_ENABLED
1855	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1856	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1857	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1858	# endif
1859
1860	/* Disable or enable dirty page tracking according to the current fTraces value. */
1861	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1862
1863	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1864	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1865	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1866
1867	/* Make the cursor visible again as needed. */
1868	if (pSVGAState->Cursor.fActive)
1869	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1870	}
1871	else
1872	{
1873	/* Make sure the cursor is off. */
1874	if (pSVGAState->Cursor.fActive)
1875	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1876
1877	/* Restore the text mode backup. */
1878	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1879
1880	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1881
1882	/* Enable dirty page tracking again when going into legacy mode. */
1883	vmsvgaR3SetTraces(pDevIns, pThis, true);
1884
1885	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1886	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1887	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1888
1889	/* Clear the pitch lock. */
1890	pThis->svga.u32PitchLock = 0;
1891	}
1892	#else /* !IN_RING3 */
1893	rc = VINF_IOM_R3_IOPORT_WRITE;
1894	#endif /* !IN_RING3 */
1895	break;
1896
1897	case SVGA_REG_WIDTH:
1898	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1899	if (u32 != pThis->svga.uWidth)
1900	{
1901	if (u32 <= pThis->svga.u32MaxWidth)
1902	{
1903	#if defined(IN_RING3) \|\| defined(IN_RING0)
1904	pThis->svga.uWidth = u32;
1905	vmsvgaHCUpdatePitch(pThis, pThisCC);
1906	if (pThis->svga.fEnabled)
1907	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1908	#else
1909	rc = VINF_IOM_R3_IOPORT_WRITE;
1910	#endif
1911	}
1912	else
1913	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
1914	}
1915	/* else: nop */
1916	break;
1917
1918	case SVGA_REG_HEIGHT:
1919	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1920	if (u32 != pThis->svga.uHeight)
1921	{
1922	if (u32 <= pThis->svga.u32MaxHeight)
1923	{
1924	pThis->svga.uHeight = u32;
1925	if (pThis->svga.fEnabled)
1926	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1927	}
1928	else
1929	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
1930	}
1931	/* else: nop */
1932	break;
1933
1934	case SVGA_REG_DEPTH:
1935	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1936	/** @todo read-only?? */
1937	break;
1938
1939	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1941	if (pThis->svga.uBpp != u32)
1942	{
1943	if (u32 <= 32)
1944	{
1945	#if defined(IN_RING3) \|\| defined(IN_RING0)
1946	pThis->svga.uBpp = u32;
1947	vmsvgaHCUpdatePitch(pThis, pThisCC);
1948	if (pThis->svga.fEnabled)
1949	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1950	#else
1951	rc = VINF_IOM_R3_IOPORT_WRITE;
1952	#endif
1953	}
1954	else
1955	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
1956	}
1957	/* else: nop */
1958	break;
1959
1960	case SVGA_REG_PSEUDOCOLOR:
1961	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1962	break;
1963
1964	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1965	#ifdef IN_RING3
1966	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1967	pThis->svga.fConfigured = u32;
1968	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1969	if (!pThis->svga.fConfigured)
1970	pThis->svga.fTraces = true;
1971	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1972	#else
1973	rc = VINF_IOM_R3_IOPORT_WRITE;
1974	#endif
1975	break;
1976
1977	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1979	if ( pThis->svga.fEnabled
1980	&& pThis->svga.fConfigured)
1981	{
1982	#if defined(IN_RING3) \|\| defined(IN_RING0)
1983	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1984	/*
1985	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1986	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1987	*/
1988	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1989	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1990	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1991
1992	/* Kick the FIFO thread to start processing commands again. */
1993	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1994	#else
1995	rc = VINF_IOM_R3_IOPORT_WRITE;
1996	#endif
1997	}
1998	/* else nothing to do. */
1999	else
2000	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2001
2002	break;
2003
2004	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2005	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2006	break;
2007
2008	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2010	pThis->svga.u32GuestId = u32;
2011	break;
2012
2013	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2015	pThis->svga.u32PitchLock = u32;
2016	/* Should this also update the FIFO pitch lock? Unclear. */
2017	break;
2018
2019	case SVGA_REG_IRQMASK: /* Interrupt mask */
2020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2021	pThis->svga.u32IrqMask = u32;
2022
2023	/* Irq pending after the above change? */
2024	if (pThis->svga.u32IrqStatus & u32)
2025	{
2026	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2027	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2028	}
2029	else
2030	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2031	break;
2032
2033	/* Mouse cursor support */
2034	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2035	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2036	pThis->svga.uCursorID = u32;
2037	break;
2038
2039	case SVGA_REG_CURSOR_X:
2040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2041	pThis->svga.uCursorX = u32;
2042	break;
2043
2044	case SVGA_REG_CURSOR_Y:
2045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2046	pThis->svga.uCursorY = u32;
2047	break;
2048
2049	case SVGA_REG_CURSOR_ON:
2050	#ifdef IN_RING3
2051	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2053	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2054	#else
2055	rc = VINF_IOM_R3_IOPORT_WRITE;
2056	#endif
2057	break;
2058
2059	/* Legacy multi-monitor support */
2060	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2062	break;
2063	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2065	break;
2066	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2068	break;
2069	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2071	break;
2072	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2073	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2074	break;
2075	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2076	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2077	break;
2078	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2079	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2080	break;
2081	#ifdef VBOX_WITH_VMSVGA3D
2082	/* See "Guest memory regions" below. */
2083	case SVGA_REG_GMR_ID:
2084	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2085	pThis->svga.u32CurrentGMRId = u32;
2086	break;
2087
2088	case SVGA_REG_GMR_DESCRIPTOR:
2089	# ifndef IN_RING3
2090	rc = VINF_IOM_R3_IOPORT_WRITE;
2091	break;
2092	# else /* IN_RING3 */
2093	{
2094	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2095
2096	/* Validate current GMR id. */
2097	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2098	AssertBreak(idGMR < pThis->svga.cGMR);
2099	RT_UNTRUSTED_VALIDATED_FENCE();
2100
2101	/* Free the old GMR if present. */
2102	vmsvgaR3GmrFree(pThisCC, idGMR);
2103
2104	/* Just undefine the GMR? */
2105	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2106	if (GCPhys == 0)
2107	{
2108	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2109	break;
2110	}
2111
2112
2113	/* Never cross a page boundary automatically. */
2114	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2115	uint32_t cPagesTotal = 0;
2116	uint32_t iDesc = 0;
2117	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2118	uint32_t cLoops = 0;
2119	RTGCPHYS GCPhysBase = GCPhys;
2120	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2121	{
2122	/* Read descriptor. */
2123	SVGAGuestMemDescriptor desc;
2124	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2125	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2126
2127	if (desc.numPages != 0)
2128	{
2129	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2130	cPagesTotal += desc.numPages;
2131	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2132
2133	if ((iDesc & 15) == 0)
2134	{
2135	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2136	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2137	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2138	}
2139
2140	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2141	paDescs[iDesc++].numPages = desc.numPages;
2142
2143	/* Continue with the next descriptor. */
2144	GCPhys += sizeof(desc);
2145	}
2146	else if (desc.ppn == 0)
2147	break; /* terminator */
2148	else /* Pointer to the next physical page of descriptors. */
2149	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2150
2151	cLoops++;
2152	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2153	}
2154
2155	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2156	if (RT_SUCCESS(rc))
2157	{
2158	/* Commit the GMR. */
2159	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2160	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2161	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2162	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2163	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2164	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2165	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2166	}
2167	else
2168	{
2169	RTMemFree(paDescs);
2170	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2171	}
2172	break;
2173	}
2174	# endif /* IN_RING3 */
2175	#endif // VBOX_WITH_VMSVGA3D
2176
2177	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2179	if (pThis->svga.fTraces == u32)
2180	break; /* nothing to do */
2181
2182	#ifdef IN_RING3
2183	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2184	#else
2185	rc = VINF_IOM_R3_IOPORT_WRITE;
2186	#endif
2187	break;
2188
2189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2191	break;
2192
2193	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2195	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2196	break;
2197
2198	/*
2199	* SVGA_CAP_GBOBJECTS+ registers.
2200	*/
2201	case SVGA_REG_COMMAND_LOW:
2202	{
2203	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2204	#ifdef IN_RING3
2205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2206	pThis->svga.u32RegCommandLow = u32;
2207
2208	/* "lower 6 bits are used for the SVGACBContext" */
2209	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2210	GCPhysCB <<= 32;
2211	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2212	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2213	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2214	#else
2215	rc = VINF_IOM_R3_IOPORT_WRITE;
2216	#endif
2217	break;
2218	}
2219
2220	case SVGA_REG_COMMAND_HIGH:
2221	/* Upper 32 bits of command buffer PA. */
2222	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2223	pThis->svga.u32RegCommandHigh = u32;
2224	break;
2225
2226	case SVGA_REG_DEV_CAP:
2227	/* Write dev cap index, read value */
2228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2229	pThis->svga.u32DevCapIndex = u32;
2230	break;
2231
2232	case SVGA_REG_CMD_PREPEND_LOW:
2233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2234	/* Not supported. */
2235	break;
2236
2237	case SVGA_REG_CMD_PREPEND_HIGH:
2238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2239	/* Not supported. */
2240	break;
2241
2242	case SVGA_REG_FB_START:
2243	case SVGA_REG_MEM_START:
2244	case SVGA_REG_HOST_BITS_PER_PIXEL:
2245	case SVGA_REG_MAX_WIDTH:
2246	case SVGA_REG_MAX_HEIGHT:
2247	case SVGA_REG_VRAM_SIZE:
2248	case SVGA_REG_FB_SIZE:
2249	case SVGA_REG_CAPABILITIES:
2250	case SVGA_REG_MEM_SIZE:
2251	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2252	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2253	case SVGA_REG_BYTES_PER_LINE:
2254	case SVGA_REG_FB_OFFSET:
2255	case SVGA_REG_RED_MASK:
2256	case SVGA_REG_GREEN_MASK:
2257	case SVGA_REG_BLUE_MASK:
2258	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2259	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2260	case SVGA_REG_GMR_MAX_IDS:
2261	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2262	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2263	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2264	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2265	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2266	case SVGA_REG_MOB_MAX_SIZE:
2267	/* Read only - ignore. */
2268	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2269	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2270	break;
2271
2272	default:
2273	{
2274	uint32_t offReg;
2275	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2276	{
2277	RT_UNTRUSTED_VALIDATED_FENCE();
2278	pThis->svga.au32ScratchRegion[offReg] = u32;
2279	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2280	}
2281	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2282	{
2283	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2284	Btw, see rgb_to_pixel32. */
2285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2286	u32 &= 0xff;
2287	RT_UNTRUSTED_VALIDATED_FENCE();
2288	uint32_t uRgb = pThis->last_palette[offReg / 3];
2289	switch (offReg % 3)
2290	{
2291	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2292	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2293	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2294	}
2295	pThis->last_palette[offReg / 3] = uRgb;
2296	}
2297	else
2298	{
2299	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2300	rc = VINF_IOM_R3_IOPORT_WRITE;
2301	#else
2302	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2303	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2304	#endif
2305	}
2306	break;
2307	}
2308	}
2309	return rc;
2310	}
2311
2312	/**
2313	* @callback_method_impl{FNIOMIOPORTNEWIN}
2314	*/
2315	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2316	{
2317	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2318	RT_NOREF_PV(pvUser);
2319
2320	/* Only dword accesses. */
2321	if (cb == 4)
2322	{
2323	switch (offPort)
2324	{
2325	case SVGA_INDEX_PORT:
2326	*pu32 = pThis->svga.u32IndexReg;
2327	break;
2328
2329	case SVGA_VALUE_PORT:
2330	return vmsvgaReadPort(pDevIns, pThis, pu32);
2331
2332	case SVGA_BIOS_PORT:
2333	Log(("Ignoring BIOS port read\n"));
2334	*pu32 = 0;
2335	break;
2336
2337	case SVGA_IRQSTATUS_PORT:
2338	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2339	*pu32 = pThis->svga.u32IrqStatus;
2340	break;
2341
2342	default:
2343	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2344	*pu32 = UINT32_MAX;
2345	break;
2346	}
2347	}
2348	else
2349	{
2350	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2351	*pu32 = UINT32_MAX;
2352	}
2353	return VINF_SUCCESS;
2354	}
2355
2356	/**
2357	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2358	*/
2359	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2360	{
2361	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2362	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2363	RT_NOREF_PV(pvUser);
2364
2365	/* Only dword accesses. */
2366	if (cb == 4)
2367	switch (offPort)
2368	{
2369	case SVGA_INDEX_PORT:
2370	pThis->svga.u32IndexReg = u32;
2371	break;
2372
2373	case SVGA_VALUE_PORT:
2374	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2375
2376	case SVGA_BIOS_PORT:
2377	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2378	break;
2379
2380	case SVGA_IRQSTATUS_PORT:
2381	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2382	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2383	/* Clear the irq in case all events have been cleared. */
2384	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2385	{
2386	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2387	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2388	}
2389	break;
2390
2391	default:
2392	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2393	break;
2394	}
2395	else
2396	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2397
2398	return VINF_SUCCESS;
2399	}
2400
2401	#ifdef IN_RING3
2402
2403	# ifdef DEBUG_FIFO_ACCESS
2404	/**
2405	* Handle FIFO memory access.
2406	* @returns VBox status code.
2407	* @param pVM VM handle.
2408	* @param pThis The shared VGA/VMSVGA instance data.
2409	* @param GCPhys The access physical address.
2410	* @param fWriteAccess Read or write access
2411	*/
2412	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2413	{
2414	RT_NOREF(pVM);
2415	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2416	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2417
2418	switch (GCPhysOffset >> 2)
2419	{
2420	case SVGA_FIFO_MIN:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_MAX:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_NEXT_CMD:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_STOP:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_CAPABILITIES:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_FLAGS:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_FENCE:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_3D_HWVERSION:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_PITCHLOCK:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_CURSOR_ON:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_CURSOR_X:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_CURSOR_Y:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_CURSOR_COUNT:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_RESERVED:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_CURSOR_SCREEN_ID:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_DEAD:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_HWVERSION_REVISED:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2592	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2593	break;
2594	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2595	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2596	break;
2597	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2598	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2599	break;
2600	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2601	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2602	break;
2603	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2604	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2605	break;
2606	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2607	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2608	break;
2609	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2610	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2611	break;
2612	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2613	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2614	break;
2615	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2616	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2617	break;
2618	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2619	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2620	break;
2621	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2622	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2623	break;
2624	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2625	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2626	break;
2627	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2628	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2629	break;
2630	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2631	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2632	break;
2633	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2634	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2635	break;
2636	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2637	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2638	break;
2639	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2640	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2641	break;
2642	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2643	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2644	break;
2645	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2646	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2647	break;
2648	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2649	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2650	break;
2651	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2652	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2653	break;
2654	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2655	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2656	break;
2657	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2658	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2659	break;
2660	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2661	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2662	break;
2663	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2664	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2665	break;
2666	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2667	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2668	break;
2669	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2670	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2671	break;
2672	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2673	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2674	break;
2675	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2676	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2677	break;
2678	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2679	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2680	break;
2681	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2682	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2683	break;
2684	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2685	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2686	break;
2687	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2688	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2689	break;
2690	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2691	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2692	break;
2693	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2694	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2695	break;
2696	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2697	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2698	break;
2699	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2700	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2701	break;
2702	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2703	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2704	break;
2705	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2706	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2707	break;
2708	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2709	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2710	break;
2711	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2712	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2713	break;
2714	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2715	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2716	break;
2717	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2718	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2719	break;
2720	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2721	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2722	break;
2723	case SVGA_FIFO_3D_CAPS_LAST:
2724	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2725	break;
2726	case SVGA_FIFO_GUEST_3D_HWVERSION:
2727	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2728	break;
2729	case SVGA_FIFO_FENCE_GOAL:
2730	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2731	break;
2732	case SVGA_FIFO_BUSY:
2733	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2734	break;
2735	default:
2736	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2737	break;
2738	}
2739
2740	return VINF_EM_RAW_EMULATE_INSTR;
2741	}
2742	# endif /* DEBUG_FIFO_ACCESS */
2743
2744	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2745	/**
2746	* HC access handler for the FIFO.
2747	*
2748	* @returns VINF_SUCCESS if the handler have carried out the operation.
2749	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2750	* @param pVM VM Handle.
2751	* @param pVCpu The cross context CPU structure for the calling EMT.
2752	* @param GCPhys The physical address the guest is writing to.
2753	* @param pvPhys The HC mapping of that address.
2754	* @param pvBuf What the guest is reading/writing.
2755	* @param cbBuf How much it's reading/writing.
2756	* @param enmAccessType The access type.
2757	* @param enmOrigin Who is making the access.
2758	* @param pvUser User argument.
2759	*/
2760	static DECLCALLBACK(VBOXSTRICTRC)
2761	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2762	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2763	{
2764	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2765	PVGASTATE pThis = (PVGASTATE)pvUser;
2766	AssertPtr(pThis);
2767
2768	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2769	/*
2770	* Wake up the FIFO thread as it might have work to do now.
2771	*/
2772	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2773	AssertLogRelRC(rc);
2774	# endif
2775
2776	# ifdef DEBUG_FIFO_ACCESS
2777	/*
2778	* When in debug-fifo-access mode, we do not disable the access handler,
2779	* but leave it on as we wish to catch all access.
2780	*/
2781	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2782	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2783	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2784	/*
2785	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2786	*/
2787	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2788	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2789	# endif
2790	if (RT_SUCCESS(rc))
2791	return VINF_PGM_HANDLER_DO_DEFAULT;
2792	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2793	return rc;
2794	}
2795	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2796
2797	#endif /* IN_RING3 */
2798
2799	#ifdef DEBUG_GMR_ACCESS
2800	# ifdef IN_RING3
2801
2802	/**
2803	* HC access handler for GMRs.
2804	*
2805	* @returns VINF_SUCCESS if the handler have carried out the operation.
2806	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2807	* @param pVM VM Handle.
2808	* @param pVCpu The cross context CPU structure for the calling EMT.
2809	* @param GCPhys The physical address the guest is writing to.
2810	* @param pvPhys The HC mapping of that address.
2811	* @param pvBuf What the guest is reading/writing.
2812	* @param cbBuf How much it's reading/writing.
2813	* @param enmAccessType The access type.
2814	* @param enmOrigin Who is making the access.
2815	* @param pvUser User argument.
2816	*/
2817	static DECLCALLBACK(VBOXSTRICTRC)
2818	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2819	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2820	{
2821	PVGASTATE pThis = (PVGASTATE)pvUser;
2822	Assert(pThis);
2823	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2824	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2825
2826	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2827
2828	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2829	{
2830	PGMR pGMR = &pSVGAState->paGMR[i];
2831
2832	if (pGMR->numDescriptors)
2833	{
2834	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2835	{
2836	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2837	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2838	{
2839	/*
2840	* Turn off the write handler for this particular page and make it R/W.
2841	* Then return telling the caller to restart the guest instruction.
2842	*/
2843	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2844	AssertRC(rc);
2845	return VINF_PGM_HANDLER_DO_DEFAULT;
2846	}
2847	}
2848	}
2849	}
2850
2851	return VINF_PGM_HANDLER_DO_DEFAULT;
2852	}
2853
2854	/** Callback handler for VMR3ReqCallWaitU */
2855	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2856	{
2857	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2858	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2859	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2860	int rc;
2861
2862	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2863	{
2864	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2865	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2866	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2867	AssertRC(rc);
2868	}
2869	return VINF_SUCCESS;
2870	}
2871
2872	/** Callback handler for VMR3ReqCallWaitU */
2873	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2874	{
2875	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2876	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2877	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2878
2879	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2880	{
2881	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2882	AssertRC(rc);
2883	}
2884	return VINF_SUCCESS;
2885	}
2886
2887	/** Callback handler for VMR3ReqCallWaitU */
2888	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2889	{
2890	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2891
2892	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2893	{
2894	PGMR pGMR = &pSVGAState->paGMR[i];
2895
2896	if (pGMR->numDescriptors)
2897	{
2898	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2899	{
2900	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2901	AssertRC(rc);
2902	}
2903	}
2904	}
2905	return VINF_SUCCESS;
2906	}
2907
2908	# endif /* IN_RING3 */
2909	#endif /* DEBUG_GMR_ACCESS */
2910
2911	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2912
2913	#ifdef IN_RING3
2914
2915
2916	/*
2917	*
2918	* Command buffer submission.
2919	*
2920	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2921	*
2922	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2923	* and wakes up the FIFO thread.
2924	*
2925	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2926	* the buffer header back to the guest memory.
2927	*
2928	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2929	*
2930	*/
2931
2932
2933	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2934	*
2935	* @param pDevIns The device instance.
2936	* @param GCPhysCB Guest physical address of the command buffer header.
2937	* @param status Command buffer status (SVGA_CB_STATUS_*).
2938	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2939	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2940	* @thread FIFO or EMT.
2941	*/
2942	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2943	{
2944	SVGACBHeader hdr;
2945	hdr.status = status;
2946	hdr.errorOffset = errorOffset;
2947	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2948	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2949	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2950	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2951	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2952	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2953	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2954	}
2955
2956
2957	/** Raise an IRQ.
2958	*
2959	* @param pDevIns The device instance.
2960	* @param pThis The shared VGA/VMSVGA state.
2961	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2962	* @thread FIFO or EMT.
2963	*/
2964	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2965	{
2966	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2967	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
2968
2969	if (pThis->svga.u32IrqMask & u32IrqStatus)
2970	{
2971	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2972	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2973	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2974	}
2975
2976	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2977	}
2978
2979
2980	/** Allocate a command buffer structure.
2981	*
2982	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2983	* @return Pointer to the allocated command buffer structure.
2984	*/
2985	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2986	{
2987	if (!pCmdBufCtx)
2988	return NULL;
2989
2990	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2991	if (pCmdBuf)
2992	{
2993	// RT_ZERO(pCmdBuf->nodeBuffer);
2994	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2995	// pCmdBuf->GCPhysCB = 0;
2996	// RT_ZERO(pCmdBuf->hdr);
2997	// pCmdBuf->pvCommands = NULL;
2998	}
2999
3000	return pCmdBuf;
3001	}
3002
3003
3004	/** Free a command buffer structure.
3005	*
3006	* @param pCmdBuf The command buffer pointer.
3007	*/
3008	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3009	{
3010	if (pCmdBuf)
3011	RTMemFree(pCmdBuf->pvCommands);
3012	RTMemFree(pCmdBuf);
3013	}
3014
3015
3016	/** Initialize a command buffer context.
3017	*
3018	* @param pCmdBufCtx The command buffer context.
3019	*/
3020	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3021	{
3022	RTListInit(&pCmdBufCtx->listSubmitted);
3023	pCmdBufCtx->cSubmitted = 0;
3024	}
3025
3026
3027	/** Destroy a command buffer context.
3028	*
3029	* @param pCmdBufCtx The command buffer context pointer.
3030	*/
3031	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3032	{
3033	if (!pCmdBufCtx)
3034	return;
3035
3036	if (pCmdBufCtx->listSubmitted.pNext)
3037	{
3038	/* If the list has been initialized. */
3039	PVMSVGACMDBUF pIter, pNext;
3040	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3041	{
3042	RTListNodeRemove(&pIter->nodeBuffer);
3043	--pCmdBufCtx->cSubmitted;
3044	vmsvgaR3CmdBufFree(pIter);
3045	}
3046	}
3047	Assert(pCmdBufCtx->cSubmitted == 0);
3048	pCmdBufCtx->cSubmitted = 0;
3049	}
3050
3051
3052	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3053	*
3054	* @param pSvgaR3State VMSVGA R3 state.
3055	* @param pCmd The command data.
3056	* @return SVGACBStatus code.
3057	* @thread EMT
3058	*/
3059	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3060	{
3061	/* Create or destroy a regular command buffer context. */
3062	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3063	return SVGA_CB_STATUS_COMMAND_ERROR;
3064	RT_UNTRUSTED_VALIDATED_FENCE();
3065
3066	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3067
3068	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3069	AssertRC(rc);
3070	if (pCmd->enable)
3071	{
3072	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3073	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3074	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3075	else
3076	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3077	}
3078	else
3079	{
3080	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3081	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3082	}
3083	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3084
3085	return CBStatus;
3086	}
3087
3088
3089	/** Handles SVGA_DC_CMD_PREEMPT command.
3090	*
3091	* @param pDevIns The device instance.
3092	* @param pSvgaR3State VMSVGA R3 state.
3093	* @param pCmd The command data.
3094	* @return SVGACBStatus code.
3095	* @thread EMT
3096	*/
3097	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3098	{
3099	/* Remove buffers from the processing queue of the specified context. */
3100	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3101	return SVGA_CB_STATUS_COMMAND_ERROR;
3102	RT_UNTRUSTED_VALIDATED_FENCE();
3103
3104	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3105	RTLISTANCHOR listPreempted;
3106
3107	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3108	AssertRC(rc);
3109	if (pCmd->ignoreIDZero)
3110	{
3111	RTListInit(&listPreempted);
3112
3113	PVMSVGACMDBUF pIter, pNext;
3114	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3115	{
3116	if (pIter->hdr.id == 0)
3117	continue;
3118
3119	RTListNodeRemove(&pIter->nodeBuffer);
3120	--pCmdBufCtx->cSubmitted;
3121	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3122	}
3123	}
3124	else
3125	{
3126	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3127	}
3128	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3129
3130	PVMSVGACMDBUF pIter, pNext;
3131	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3132	{
3133	RTListNodeRemove(&pIter->nodeBuffer);
3134	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3135	vmsvgaR3CmdBufFree(pIter);
3136	}
3137
3138	return SVGA_CB_STATUS_COMPLETED;
3139	}
3140
3141
3142	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3143	* Increments the size of the command cbCmd by a_cbMore.
3144	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3145	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3146	*/
3147	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3148	if (1) { \
3149	cbCmd += (a_cbMore); \
3150	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3151	RT_UNTRUSTED_VALIDATED_FENCE(); \
3152	} else do {} while (0)
3153
3154
3155	/** Processes Device Context command buffer.
3156	*
3157	* @param pDevIns The device instance.
3158	* @param pSvgaR3State VMSVGA R3 state.
3159	* @param pvCommands Pointer to the command buffer.
3160	* @param cbCommands Size of the command buffer.
3161	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3162	* @return SVGACBStatus code.
3163	* @thread EMT
3164	*/
3165	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3166	{
3167	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3168
3169	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3170	uint32_t cbRemain = cbCommands;
3171	while (cbRemain)
3172	{
3173	/* Command identifier is a 32 bit value. */
3174	if (cbRemain < sizeof(uint32_t))
3175	{
3176	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3177	break;
3178	}
3179
3180	/* Fetch the command id. */
3181	uint32_t const cmdId = (uint32_t )pu8Cmd;
3182	uint32_t cbCmd = sizeof(uint32_t);
3183	switch (cmdId)
3184	{
3185	case SVGA_DC_CMD_NOP:
3186	{
3187	/* NOP */
3188	break;
3189	}
3190
3191	case SVGA_DC_CMD_START_STOP_CONTEXT:
3192	{
3193	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3194	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3195	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3196	break;
3197	}
3198
3199	case SVGA_DC_CMD_PREEMPT:
3200	{
3201	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3202	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3203	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3204	break;
3205	}
3206
3207	default:
3208	{
3209	/* Unsupported command. */
3210	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3211	break;
3212	}
3213	}
3214
3215	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3216	break;
3217
3218	pu8Cmd += cbCmd;
3219	cbRemain -= cbCmd;
3220	}
3221
3222	Assert(cbRemain <= cbCommands);
3223	*poffNextCmd = cbCommands - cbRemain;
3224	return CBstatus;
3225	}
3226
3227
3228	/** Submits a device context command buffer for synchronous processing.
3229	*
3230	* @param pDevIns The device instance.
3231	* @param pThisCC The VGA/VMSVGA state for the current context.
3232	* @param ppCmdBuf Pointer to the command buffer pointer.
3233	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3234	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3235	* @return SVGACBStatus code.
3236	* @thread EMT
3237	*/
3238	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3239	{
3240	/* Synchronously process the device context commands. */
3241	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3242	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3243	}
3244
3245	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3246	*
3247	* @param pDevIns The device instance.
3248	* @param pThis The shared VGA/VMSVGA state.
3249	* @param pThisCC The VGA/VMSVGA state for the current context.
3250	* @param ppCmdBuf Pointer to the command buffer pointer.
3251	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3252	* @return SVGACBStatus code.
3253	* @thread EMT
3254	*/
3255	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3256	{
3257	/* Command buffer submission. */
3258	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3259
3260	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3261
3262	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3263	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3264
3265	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3266	AssertRC(rc);
3267
3268	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3269	{
3270	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3271	++pCmdBufCtx->cSubmitted;
3272	ppCmdBuf = NULL; / Consume the buffer. */
3273	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3274	}
3275	else
3276	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3277
3278	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3279
3280	/* Inform the FIFO thread. */
3281	if (*ppCmdBuf == NULL)
3282	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3283
3284	return CBstatus;
3285	}
3286
3287
3288	/** SVGA_REG_COMMAND_LOW write handler.
3289	* Submits a command buffer to the FIFO thread or processes a device context command.
3290	*
3291	* @param pDevIns The device instance.
3292	* @param pThis The shared VGA/VMSVGA state.
3293	* @param pThisCC The VGA/VMSVGA state for the current context.
3294	* @param GCPhysCB Guest physical address of the command buffer header.
3295	* @param CBCtx Context the command buffer is submitted to.
3296	* @thread EMT
3297	*/
3298	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3299	{
3300	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3301
3302	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3303	uint32_t offNextCmd = 0;
3304	uint32_t fIRQ = 0;
3305
3306	/* Get the context if the device has the capability. */
3307	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3308	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3309	{
3310	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3311	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3312	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3313	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3314	RT_UNTRUSTED_VALIDATED_FENCE();
3315	}
3316
3317	/* Allocate a new command buffer. */
3318	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3319	if (RT_LIKELY(pCmdBuf))
3320	{
3321	pCmdBuf->GCPhysCB = GCPhysCB;
3322
3323	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3324	if (RT_SUCCESS(rc))
3325	{
3326	/* Verify the command buffer header. */
3327	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3328	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3329	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3330	{
3331	RT_UNTRUSTED_VALIDATED_FENCE();
3332
3333	/* Read the command buffer content. */
3334	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3335	if (pCmdBuf->pvCommands)
3336	{
3337	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3338	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3339	if (RT_SUCCESS(rc))
3340	{
3341	/* Submit the buffer. Device context buffers will be processed synchronously. */
3342	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3343	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3344	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3345	else
3346	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3347	}
3348	else
3349	{
3350	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3351	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3352	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3353	}
3354	}
3355	else
3356	{
3357	/* No memory for commands. */
3358	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3359	}
3360	}
3361	else
3362	{
3363	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3364	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3365	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3366	}
3367	}
3368	else
3369	{
3370	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3371	ASSERT_GUEST_FAILED();
3372	/* Do not attempt to write the status. */
3373	}
3374
3375	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3376	vmsvgaR3CmdBufFree(pCmdBuf);
3377	}
3378	else
3379	{
3380	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3381	ASSERT_GUEST_FAILED();
3382	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3383	}
3384
3385	if (CBstatus != SVGA_CB_STATUS_NONE)
3386	{
3387	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf ? pCmdBuf->hdr.length : 0, fIRQ));
3388	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3389	if (fIRQ)
3390	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3391	}
3392	}
3393
3394
3395	/** Checks if there are some buffers to be processed.
3396	*
3397	* @param pThisCC The VGA/VMSVGA state for the current context.
3398	* @return true if buffers must be processed.
3399	* @thread FIFO
3400	*/
3401	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3402	{
3403	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3404	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3405	}
3406
3407
3408	/** Processes a command buffer.
3409	*
3410	* @param pDevIns The device instance.
3411	* @param pThis The shared VGA/VMSVGA state.
3412	* @param pThisCC The VGA/VMSVGA state for the current context.
3413	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3414	* @param pvCommands Pointer to the command buffer.
3415	* @param cbCommands Size of the command buffer.
3416	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3417	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3418	* @return SVGACBStatus code.
3419	* @thread FIFO
3420	*/
3421	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3422	{
3423	# ifndef VBOX_WITH_VMSVGA3D
3424	RT_NOREF(idDXContext);
3425	# endif
3426	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3427	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3428
3429	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3430
3431	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3432	uint32_t cbRemain = cbCommands;
3433	while (cbRemain)
3434	{
3435	/* Command identifier is a 32 bit value. */
3436	if (cbRemain < sizeof(uint32_t))
3437	{
3438	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3439	break;
3440	}
3441
3442	/* Fetch the command id.
3443	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3444	* warning. Because we support some obsolete and deprecated commands, which are not included in
3445	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3446	*/
3447	uint32_t const cmdId = (uint32_t )pu8Cmd;
3448	uint32_t cbCmd = sizeof(uint32_t);
3449
3450	LogFlowFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3451	# ifdef LOG_ENABLED
3452	# ifdef VBOX_WITH_VMSVGA3D
3453	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3454	{
3455	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3456	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3457	}
3458	else if (cmdId == SVGA_CMD_FENCE)
3459	{
3460	Log7(("\tSVGA_CMD_FENCE\n"));
3461	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3462	}
3463	# endif
3464	# endif
3465
3466	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3467	* I.e. pu8Cmd + cbCmd must point to the next command.
3468	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3469	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3470	*/
3471	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3472	switch (cmdId)
3473	{
3474	case SVGA_CMD_INVALID_CMD:
3475	{
3476	/* Nothing to do. */
3477	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3478	break;
3479	}
3480
3481	case SVGA_CMD_FENCE:
3482	{
3483	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3484	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3485	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3486	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3487
3488	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3489	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3490	{
3491	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3492
3493	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3494	{
3495	Log(("any fence irq\n"));
3496	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3497	}
3498	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3499	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3500	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3501	{
3502	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3503	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3504	}
3505	}
3506	else
3507	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3508	break;
3509	}
3510
3511	case SVGA_CMD_UPDATE:
3512	{
3513	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3514	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3515	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3516	break;
3517	}
3518
3519	case SVGA_CMD_UPDATE_VERBOSE:
3520	{
3521	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3522	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3523	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3524	break;
3525	}
3526
3527	case SVGA_CMD_DEFINE_CURSOR:
3528	{
3529	/* Followed by bitmap data. */
3530	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3531	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3532
3533	/* Figure out the size of the bitmap data. */
3534	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3535	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3536	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3537	RT_UNTRUSTED_VALIDATED_FENCE();
3538
3539	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3540	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3541	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3542	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3543
3544	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3545	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3546	break;
3547	}
3548
3549	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3550	{
3551	/* Followed by bitmap data. */
3552	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3553	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3554
3555	/* Figure out the size of the bitmap data. */
3556	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3557
3558	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3559	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3560	break;
3561	}
3562
3563	case SVGA_CMD_MOVE_CURSOR:
3564	{
3565	/* Deprecated; there should be no driver which requires this command. However, if
3566	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3567	* alignment.
3568	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3569	*/
3570	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3571	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3572	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3573	break;
3574	}
3575
3576	case SVGA_CMD_DISPLAY_CURSOR:
3577	{
3578	/* Deprecated; there should be no driver which requires this command. However, if
3579	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3580	* alignment.
3581	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3582	*/
3583	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3584	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3585	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3586	break;
3587	}
3588
3589	case SVGA_CMD_RECT_FILL:
3590	{
3591	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3592	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3593	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3594	break;
3595	}
3596
3597	case SVGA_CMD_RECT_COPY:
3598	{
3599	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3600	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3601	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3602	break;
3603	}
3604
3605	case SVGA_CMD_RECT_ROP_COPY:
3606	{
3607	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3608	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3609	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3610	break;
3611	}
3612
3613	case SVGA_CMD_ESCAPE:
3614	{
3615	/* Followed by 'size' bytes of data. */
3616	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3617	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3618
3619	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3620	RT_UNTRUSTED_VALIDATED_FENCE();
3621
3622	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3623	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3624	break;
3625	}
3626	# ifdef VBOX_WITH_VMSVGA3D
3627	case SVGA_CMD_DEFINE_GMR2:
3628	{
3629	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3630	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3631	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3632	break;
3633	}
3634
3635	case SVGA_CMD_REMAP_GMR2:
3636	{
3637	/* Followed by page descriptors or guest ptr. */
3638	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3639	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3640
3641	/* Calculate the size of what comes after next and fetch it. */
3642	uint32_t cbMore = 0;
3643	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3644	cbMore = sizeof(SVGAGuestPtr);
3645	else
3646	{
3647	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3648	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3649	{
3650	cbMore = cbPageDesc;
3651	pCmd->numPages = 1;
3652	}
3653	else
3654	{
3655	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3656	cbMore = cbPageDesc * pCmd->numPages;
3657	}
3658	}
3659	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3660	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3661	# ifdef DEBUG_GMR_ACCESS
3662	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3663	# endif
3664	break;
3665	}
3666	# endif /* VBOX_WITH_VMSVGA3D */
3667	case SVGA_CMD_DEFINE_SCREEN:
3668	{
3669	/* The size of this command is specified by the guest and depends on capabilities. */
3670	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3671	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3672	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3673	RT_UNTRUSTED_VALIDATED_FENCE();
3674
3675	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3676	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3677	break;
3678	}
3679
3680	case SVGA_CMD_DESTROY_SCREEN:
3681	{
3682	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3683	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3684	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3685	break;
3686	}
3687
3688	case SVGA_CMD_DEFINE_GMRFB:
3689	{
3690	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3691	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3692	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3693	break;
3694	}
3695
3696	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3697	{
3698	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3699	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3700	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3701	break;
3702	}
3703
3704	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3705	{
3706	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3707	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3708	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3709	break;
3710	}
3711
3712	case SVGA_CMD_ANNOTATION_FILL:
3713	{
3714	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3715	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3716	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3717	break;
3718	}
3719
3720	case SVGA_CMD_ANNOTATION_COPY:
3721	{
3722	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3723	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3724	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3725	break;
3726	}
3727
3728	default:
3729	{
3730	# ifdef VBOX_WITH_VMSVGA3D
3731	if ( cmdId >= SVGA_3D_CMD_BASE
3732	&& cmdId < SVGA_3D_CMD_MAX)
3733	{
3734	RT_UNTRUSTED_VALIDATED_FENCE();
3735
3736	/* All 3d commands start with a common header, which defines the identifier and the size
3737	* of the command. The identifier has been already read. Fetch the size.
3738	*/
3739	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3740	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3741	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3742	if (RT_LIKELY(pThis->svga.f3DEnabled))
3743	{ /* likely */ }
3744	else
3745	{
3746	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3747	break;
3748	}
3749
3750	/* Command data begins after the 32 bit command length. */
3751	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3752	if (RT_SUCCESS(rc))
3753	{ /* likely */ }
3754	else
3755	{
3756	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3757	break;
3758	}
3759	}
3760	else
3761	# endif /* VBOX_WITH_VMSVGA3D */
3762	{
3763	/* Unsupported command. */
3764	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3765	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3766	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3767	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3768	break;
3769	}
3770	}
3771	}
3772
3773	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3774	break;
3775
3776	pu8Cmd += cbCmd;
3777	cbRemain -= cbCmd;
3778
3779	/* If this is not the last command in the buffer, then generate IRQ, if required.
3780	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3781	* in the buffer (usually the case).
3782	*/
3783	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3784	{ /* likely */ }
3785	else
3786	{
3787	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3788	*pu32IrqStatus = 0;
3789	}
3790	}
3791
3792	Assert(cbRemain <= cbCommands);
3793	*poffNextCmd = cbCommands - cbRemain;
3794	return CBstatus;
3795	}
3796
3797
3798	/** Process command buffers.
3799	*
3800	* @param pDevIns The device instance.
3801	* @param pThis The shared VGA/VMSVGA state.
3802	* @param pThisCC The VGA/VMSVGA state for the current context.
3803	* @param pThread Handle of the FIFO thread.
3804	* @thread FIFO
3805	*/
3806	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3807	{
3808	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3809
3810	for (;;)
3811	{
3812	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3813	break;
3814
3815	/* See if there is a submitted buffer. */
3816	PVMSVGACMDBUF pCmdBuf = NULL;
3817
3818	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3819	AssertRC(rc);
3820
3821	/* It seems that a higher queue index has a higher priority.
3822	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3823	*/
3824	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3825	{
3826	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3827	if (pCmdBufCtx)
3828	{
3829	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3830	if (pCmdBuf)
3831	{
3832	Assert(pCmdBufCtx->cSubmitted > 0);
3833	--pCmdBufCtx->cSubmitted;
3834	break;
3835	}
3836	}
3837	}
3838
3839	if (!pCmdBuf)
3840	{
3841	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3842	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3843	break;
3844	}
3845
3846	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3847
3848	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3849	uint32_t offNextCmd = 0;
3850	uint32_t u32IrqStatus = 0;
3851	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
3852	? pCmdBuf->hdr.dxContext
3853	: SVGA3D_INVALID_ID;
3854	/* Process one buffer. */
3855	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3856
3857	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3858	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3859	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3860	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3861
3862	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3863	if (u32IrqStatus)
3864	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3865
3866	vmsvgaR3CmdBufFree(pCmdBuf);
3867	}
3868	}
3869
3870
3871	/**
3872	* Worker for vmsvgaR3FifoThread that handles an external command.
3873	*
3874	* @param pDevIns The device instance.
3875	* @param pThis The shared VGA/VMSVGA instance data.
3876	* @param pThisCC The VGA/VMSVGA state for ring-3.
3877	*/
3878	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3879	{
3880	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3881	switch (pThis->svga.u8FIFOExtCommand)
3882	{
3883	case VMSVGA_FIFO_EXTCMD_RESET:
3884	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3885	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3886
3887	vmsvgaR3ResetScreens(pThis, pThisCC);
3888	# ifdef VBOX_WITH_VMSVGA3D
3889	if (pThis->svga.f3DEnabled)
3890	{
3891	/* The 3d subsystem must be reset from the fifo thread. */
3892	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3893	pSVGAState->pFuncs3D->pfnReset(pThisCC);
3894	}
3895	# endif
3896	break;
3897
3898	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3899	Log(("vmsvgaR3FifoLoop: power off.\n"));
3900	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3901
3902	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3903	vmsvgaR3ResetScreens(pThis, pThisCC);
3904	break;
3905
3906	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3907	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3908	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3909	# ifdef VBOX_WITH_VMSVGA3D
3910	if (pThis->svga.f3DEnabled)
3911	{
3912	/* The 3d subsystem must be shut down from the fifo thread. */
3913	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3914	pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
3915	}
3916	# endif
3917	break;
3918
3919	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3920	{
3921	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3922	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3923	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3924	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3925	# ifdef VBOX_WITH_VMSVGA3D
3926	if (pThis->svga.f3DEnabled)
3927	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3928	# endif
3929	break;
3930	}
3931
3932	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3933	{
3934	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3935	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3936	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3937	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3938	# ifdef VBOX_WITH_VMSVGA3D
3939	if (pThis->svga.f3DEnabled)
3940	{
3941	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
3942	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
3943	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
3944	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3945	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
3946	# endif
3947
3948	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3949	}
3950	# endif
3951	break;
3952	}
3953
3954	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3955	{
3956	# ifdef VBOX_WITH_VMSVGA3D
3957	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3958	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3959	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3960	# endif
3961	break;
3962	}
3963
3964
3965	default:
3966	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3967	break;
3968	}
3969
3970	/*
3971	* Signal the end of the external command.
3972	*/
3973	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3974	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3975	ASMMemoryFence(); /* paranoia^2 */
3976	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3977	AssertLogRelRC(rc);
3978	}
3979
3980	/**
3981	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3982	* doing a job on the FIFO thread (even when it's officially suspended).
3983	*
3984	* @returns VBox status code (fully asserted).
3985	* @param pDevIns The device instance.
3986	* @param pThis The shared VGA/VMSVGA instance data.
3987	* @param pThisCC The VGA/VMSVGA state for ring-3.
3988	* @param uExtCmd The command to execute on the FIFO thread.
3989	* @param pvParam Pointer to command parameters.
3990	* @param cMsWait The time to wait for the command, given in
3991	* milliseconds.
3992	*/
3993	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3994	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3995	{
3996	Assert(cMsWait >= RT_MS_1SEC * 5);
3997	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3998	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3999
4000	int rc;
4001	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4002	PDMTHREADSTATE enmState = pThread->enmState;
4003	if (enmState == PDMTHREADSTATE_SUSPENDED)
4004	{
4005	/*
4006	* The thread is suspended, we have to temporarily wake it up so it can
4007	* perform the task.
4008	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4009	*/
4010	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4011	/* Post the request. */
4012	pThis->svga.fFifoExtCommandWakeup = true;
4013	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4014	pThis->svga.u8FIFOExtCommand = uExtCmd;
4015	ASMMemoryFence(); /* paranoia^3 */
4016
4017	/* Resume the thread. */
4018	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4019	AssertLogRelRC(rc);
4020	if (RT_SUCCESS(rc))
4021	{
4022	/* Wait. Take care in case the semaphore was already posted (same as below). */
4023	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4024	if ( rc == VINF_SUCCESS
4025	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4026	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4027	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4028	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4029
4030	/* suspend the thread */
4031	pThis->svga.fFifoExtCommandWakeup = false;
4032	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4033	AssertLogRelRC(rc2);
4034	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4035	rc = rc2;
4036	}
4037	pThis->svga.fFifoExtCommandWakeup = false;
4038	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4039	}
4040	else if (enmState == PDMTHREADSTATE_RUNNING)
4041	{
4042	/*
4043	* The thread is running, should only happen during reset and vmsvga3dsfc.
4044	* We ASSUME not racing code here, both wrt thread state and ext commands.
4045	*/
4046	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4047	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4048
4049	/* Post the request. */
4050	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4051	pThis->svga.u8FIFOExtCommand = uExtCmd;
4052	ASMMemoryFence(); /* paranoia^2 */
4053	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4054	AssertLogRelRC(rc);
4055
4056	/* Wait. Take care in case the semaphore was already posted (same as above). */
4057	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4058	if ( rc == VINF_SUCCESS
4059	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4060	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4061	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4062	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4063
4064	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4065	}
4066	else
4067	{
4068	/*
4069	* Something is wrong with the thread!
4070	*/
4071	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4072	rc = VERR_INVALID_STATE;
4073	}
4074	return rc;
4075	}
4076
4077
4078	/**
4079	* Marks the FIFO non-busy, notifying any waiting EMTs.
4080	*
4081	* @param pDevIns The device instance.
4082	* @param pThis The shared VGA/VMSVGA instance data.
4083	* @param pThisCC The VGA/VMSVGA state for ring-3.
4084	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4085	* @param offFifoMin The start byte offset of the command FIFO.
4086	*/
4087	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4088	{
4089	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4090	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4091	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4092
4093	/* Wake up any waiting EMTs. */
4094	if (pSVGAState->cBusyDelayedEmts > 0)
4095	{
4096	# ifdef VMSVGA_USE_EMT_HALT_CODE
4097	PVM pVM = PDMDevHlpGetVM(pDevIns);
4098	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4099	if (idCpu != NIL_VMCPUID)
4100	{
4101	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4102	while (idCpu-- > 0)
4103	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4104	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4105	}
4106	# else
4107	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4108	AssertRC(rc2);
4109	# endif
4110	}
4111	}
4112
4113	/**
4114	* Reads (more) payload into the command buffer.
4115	*
4116	* @returns pbBounceBuf on success
4117	* @retval (void *)1 if the thread was requested to stop.
4118	* @retval NULL on FIFO error.
4119	*
4120	* @param cbPayloadReq The number of bytes of payload requested.
4121	* @param pFIFO The FIFO.
4122	* @param offCurrentCmd The FIFO byte offset of the current command.
4123	* @param offFifoMin The start byte offset of the command FIFO.
4124	* @param offFifoMax The end byte offset of the command FIFO.
4125	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4126	* always sufficient size.
4127	* @param pcbAlreadyRead How much payload we've already read into the bounce
4128	* buffer. (We will NEVER re-read anything.)
4129	* @param pThread The calling PDM thread handle.
4130	* @param pThis The shared VGA/VMSVGA instance data.
4131	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4132	* statistics collection.
4133	* @param pDevIns The device instance.
4134	*/
4135	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4136	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4137	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4138	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4139	{
4140	Assert(pbBounceBuf);
4141	Assert(pcbAlreadyRead);
4142	Assert(offFifoMin < offFifoMax);
4143	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4144	Assert(offFifoMax <= pThis->svga.cbFIFO);
4145
4146	/*
4147	* Check if the requested payload size has already been satisfied .
4148	* .
4149	* When called to read more, the caller is responsible for making sure the .
4150	* new command size (cbRequsted) never is smaller than what has already .
4151	* been read.
4152	*/
4153	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4154	if (cbPayloadReq <= cbAlreadyRead)
4155	{
4156	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4157	return pbBounceBuf;
4158	}
4159
4160	/*
4161	* Commands bigger than the fifo buffer are invalid.
4162	*/
4163	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4164	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4165	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4166	NULL);
4167
4168	/*
4169	* Move offCurrentCmd past the command dword.
4170	*/
4171	offCurrentCmd += sizeof(uint32_t);
4172	if (offCurrentCmd >= offFifoMax)
4173	offCurrentCmd = offFifoMin;
4174
4175	/*
4176	* Do we have sufficient payload data available already?
4177	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4178	*/
4179	uint32_t cbAfter, cbBefore;
4180	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4181	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4182	if (offNextCmd >= offCurrentCmd)
4183	{
4184	if (RT_LIKELY(offNextCmd < offFifoMax))
4185	cbAfter = offNextCmd - offCurrentCmd;
4186	else
4187	{
4188	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4189	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4190	offNextCmd, offFifoMin, offFifoMax));
4191	cbAfter = offFifoMax - offCurrentCmd;
4192	}
4193	cbBefore = 0;
4194	}
4195	else
4196	{
4197	cbAfter = offFifoMax - offCurrentCmd;
4198	if (offNextCmd >= offFifoMin)
4199	cbBefore = offNextCmd - offFifoMin;
4200	else
4201	{
4202	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4203	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4204	offNextCmd, offFifoMin, offFifoMax));
4205	cbBefore = 0;
4206	}
4207	}
4208	if (cbAfter + cbBefore < cbPayloadReq)
4209	{
4210	/*
4211	* Insufficient, must wait for it to arrive.
4212	*/
4213	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4214	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4215	for (uint32_t i = 0;; i++)
4216	{
4217	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4218	{
4219	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4220	return (void *)(uintptr_t)1;
4221	}
4222	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4223	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4224
4225	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4226
4227	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4228	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4229	if (offNextCmd >= offCurrentCmd)
4230	{
4231	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4232	cbBefore = 0;
4233	}
4234	else
4235	{
4236	cbAfter = offFifoMax - offCurrentCmd;
4237	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4238	}
4239
4240	if (cbAfter + cbBefore >= cbPayloadReq)
4241	break;
4242	}
4243	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4244	}
4245
4246	/*
4247	* Copy out the memory and update what pcbAlreadyRead points to.
4248	*/
4249	if (cbAfter >= cbPayloadReq)
4250	memcpy(pbBounceBuf + cbAlreadyRead,
4251	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4252	cbPayloadReq - cbAlreadyRead);
4253	else
4254	{
4255	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4256	if (cbAlreadyRead < cbAfter)
4257	{
4258	memcpy(pbBounceBuf + cbAlreadyRead,
4259	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4260	cbAfter - cbAlreadyRead);
4261	cbAlreadyRead = cbAfter;
4262	}
4263	memcpy(pbBounceBuf + cbAlreadyRead,
4264	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4265	cbPayloadReq - cbAlreadyRead);
4266	}
4267	*pcbAlreadyRead = cbPayloadReq;
4268	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4269	return pbBounceBuf;
4270	}
4271
4272
4273	/**
4274	* Sends cursor position and visibility information from the FIFO to the front-end.
4275	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4276	*/
4277	static uint32_t
4278	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4279	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4280	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4281	{
4282	/*
4283	* Check if the cursor update counter has changed and try get a stable
4284	* set of values if it has. This is race-prone, especially consindering
4285	* the screen ID, but little we can do about that.
4286	*/
4287	uint32_t x, y, fVisible, idScreen;
4288	for (uint32_t i = 0; ; i++)
4289	{
4290	x = pFIFO[SVGA_FIFO_CURSOR_X];
4291	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4292	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4293	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4294	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4295	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4296	\|\| i > 3)
4297	break;
4298	if (i == 0)
4299	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4300	ASMNopPause();
4301	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4302	}
4303
4304	/*
4305	* Check if anything has changed, as calling into pDrv is not light-weight.
4306	*/
4307	if ( *pxLast == x
4308	&& *pyLast == y
4309	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4310	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4311	else
4312	{
4313	/*
4314	* Detected changes.
4315	*
4316	* We handle global, not per-screen visibility information by sending
4317	* pfnVBVAMousePointerShape without shape data.
4318	*/
4319	*pxLast = x;
4320	*pyLast = y;
4321	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4322	if (idScreen != SVGA_ID_INVALID)
4323	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4324	else if (*pfLastVisible != fVisible)
4325	{
4326	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4327	*pfLastVisible = fVisible;
4328	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4329	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4330	}
4331	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4332	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4333	}
4334
4335	/*
4336	* Update done. Signal this to the guest.
4337	*/
4338	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4339
4340	return uCursorUpdateCount;
4341	}
4342
4343
4344	/**
4345	* Checks if there is work to be done, either cursor updating or FIFO commands.
4346	*
4347	* @returns true if pending work, false if not.
4348	* @param pThisCC The VGA/VMSVGA state for ring-3.
4349	* @param uLastCursorCount The last cursor update counter value.
4350	*/
4351	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4352	{
4353	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4354	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4355	AssertReturn(pFIFO, false);
4356
4357	if (vmsvgaR3CmdBufHasWork(pThisCC))
4358	return true;
4359
4360	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4361	return true;
4362
4363	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4364	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4365	return true;
4366
4367	return false;
4368	}
4369
4370
4371	/**
4372	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4373	*
4374	* @param pDevIns The device instance.
4375	* @param pThis The shared VGA/VMSVGA instance data.
4376	* @param pThisCC The VGA/VMSVGA state for ring-3.
4377	*/
4378	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4379	{
4380	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4381	to recheck it before doing the signalling. */
4382	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4383	&& pThis->svga.fFIFOThreadSleeping
4384	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4385	{
4386	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4387	AssertRC(rc);
4388	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4389	}
4390	}
4391
4392
4393	/**
4394	* Called by the FIFO thread to process pending actions.
4395	*
4396	* @param pDevIns The device instance.
4397	* @param pThis The shared VGA/VMSVGA instance data.
4398	* @param pThisCC The VGA/VMSVGA state for ring-3.
4399	*/
4400	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4401	{
4402	RT_NOREF(pDevIns);
4403
4404	/* Currently just mode changes. */
4405	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4406	{
4407	vmsvgaR3ChangeMode(pThis, pThisCC);
4408	# ifdef VBOX_WITH_VMSVGA3D
4409	if (pThisCC->svga.p3dState != NULL)
4410	vmsvga3dChangeMode(pThisCC);
4411	# endif
4412	}
4413	}
4414
4415
4416	/*
4417	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4418	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4419	*/
4420	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4421	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4422	*
4423	* Will break out of the switch on failure.
4424	* Will restart and quit the loop if the thread was requested to stop.
4425	*
4426	* @param a_PtrVar Request variable pointer.
4427	* @param a_Type Request typedef (not pointer) for casting.
4428	* @param a_cbPayloadReq How much payload to fetch.
4429	* @remarks Accesses a bunch of variables in the current scope!
4430	*/
4431	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4432	if (1) { \
4433	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4434	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4435	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4436	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4437	} else do {} while (0)
4438	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4439	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4440	* buffer after figuring out the actual command size.
4441	*
4442	* Will break out of the switch on failure.
4443	*
4444	* @param a_PtrVar Request variable pointer.
4445	* @param a_Type Request typedef (not pointer) for casting.
4446	* @param a_cbPayloadReq How much payload to fetch.
4447	* @remarks Accesses a bunch of variables in the current scope!
4448	*/
4449	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4450	if (1) { \
4451	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4452	} else do {} while (0)
4453
4454	/**
4455	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4456	*/
4457	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4458	{
4459	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4460	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4461	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4462	int rc;
4463
4464	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4465	if (pThis->svga.f3DEnabled)
4466	{
4467	/* The FIFO thread may use X API for accelerated screen output. */
4468	XInitThreads();
4469	}
4470	# endif
4471
4472	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4473	return VINF_SUCCESS;
4474
4475	/*
4476	* Special mode where we only execute an external command and the go back
4477	* to being suspended. Currently, all ext cmds ends up here, with the reset
4478	* one also being eligble for runtime execution further down as well.
4479	*/
4480	if (pThis->svga.fFifoExtCommandWakeup)
4481	{
4482	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4483	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4484	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4485	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4486	else
4487	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4488	return VINF_SUCCESS;
4489	}
4490
4491
4492	/*
4493	* Signal the semaphore to make sure we don't wait for 250ms after a
4494	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4495	*/
4496	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4497
4498	/*
4499	* Allocate a bounce buffer for command we get from the FIFO.
4500	* (All code must return via the end of the function to free this buffer.)
4501	*/
4502	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4503	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4504
4505	/*
4506	* Polling/sleep interval config.
4507	*
4508	* We wait for an a short interval if the guest has recently given us work
4509	* to do, but the interval increases the longer we're kept idle. Once we've
4510	* reached the refresh timer interval, we'll switch to extended waits,
4511	* depending on it or the guest to kick us into action when needed.
4512	*
4513	* Should the refresh time go fishing, we'll just continue increasing the
4514	* sleep length till we reaches the 250 ms max after about 16 seconds.
4515	*/
4516	RTMSINTERVAL const cMsMinSleep = 16;
4517	RTMSINTERVAL const cMsIncSleep = 2;
4518	RTMSINTERVAL const cMsMaxSleep = 250;
4519	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4520	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4521
4522	/*
4523	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4524	*
4525	* Initialize with values that will detect an update from the guest.
4526	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4527	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4528	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4529	*/
4530	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4531	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4532	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4533	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4534	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4535
4536	/*
4537	* The FIFO loop.
4538	*/
4539	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4540	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4541	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4542	{
4543	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4544	/*
4545	* Should service the run loop every so often.
4546	*/
4547	if (pThis->svga.f3DEnabled)
4548	vmsvga3dCocoaServiceRunLoop();
4549	# endif
4550
4551	/* First check any pending actions. */
4552	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4553
4554	/*
4555	* Unless there's already work pending, go to sleep for a short while.
4556	* (See polling/sleep interval config above.)
4557	*/
4558	if ( fBadOrDisabledFifo
4559	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4560	{
4561	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4562	Assert(pThis->cMilliesRefreshInterval > 0);
4563	if (cMsSleep < pThis->cMilliesRefreshInterval)
4564	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4565	else
4566	{
4567	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4568	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4569	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4570	# endif
4571	if ( !fBadOrDisabledFifo
4572	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4573	rc = VINF_SUCCESS;
4574	else
4575	{
4576	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4577	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4578	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4579	}
4580	}
4581	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4582	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4583	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4584	{
4585	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4586	break;
4587	}
4588	}
4589	else
4590	rc = VINF_SUCCESS;
4591	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4592	if (rc == VERR_TIMEOUT)
4593	{
4594	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4595	{
4596	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4597	continue;
4598	}
4599	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4600
4601	Log(("vmsvgaR3FifoLoop: timeout\n"));
4602	}
4603	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4604	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4605	cMsSleep = cMsMinSleep;
4606
4607	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4608	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4609	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4610
4611	/*
4612	* Handle external commands (currently only reset).
4613	*/
4614	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4615	{
4616	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4617	continue;
4618	}
4619
4620	/*
4621	* If guest misbehaves, then do nothing.
4622	*/
4623	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4624	{
4625	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4626	cMsSleep = cMsExtendedSleep;
4627	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4628	continue;
4629	}
4630
4631	/*
4632	* The device must be enabled and configured.
4633	*/
4634	if ( !pThis->svga.fEnabled
4635	\|\| !pThis->svga.fConfigured)
4636	{
4637	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4638	fBadOrDisabledFifo = true;
4639	cMsSleep = cMsMaxSleep; /* cheat */
4640	continue;
4641	}
4642
4643	/*
4644	* Get and check the min/max values. We ASSUME that they will remain
4645	* unchanged while we process requests. A further ASSUMPTION is that
4646	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4647	* we don't read it back while in the loop.
4648	*/
4649	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4650	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4651	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4652	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4653	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4654	\|\| offFifoMax <= offFifoMin
4655	\|\| offFifoMax > pThis->svga.cbFIFO
4656	\|\| (offFifoMax & 3) != 0
4657	\|\| (offFifoMin & 3) != 0
4658	\|\| offCurrentCmd < offFifoMin
4659	\|\| offCurrentCmd > offFifoMax))
4660	{
4661	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4662	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4663	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4664	fBadOrDisabledFifo = true;
4665	continue;
4666	}
4667	RT_UNTRUSTED_VALIDATED_FENCE();
4668	if (RT_UNLIKELY(offCurrentCmd & 3))
4669	{
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4671	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4672	offCurrentCmd &= ~UINT32_C(3);
4673	}
4674
4675	/*
4676	* Update the cursor position before we start on the FIFO commands.
4677	*/
4678	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4679	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4680	{
4681	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4682	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4683	{ /* halfways likely */ }
4684	else
4685	{
4686	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4687	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4688	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4689	}
4690	}
4691
4692	/*
4693	* Mark the FIFO as busy.
4694	*/
4695	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4696	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4697	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4698
4699	/*
4700	* Process all submitted command buffers.
4701	*/
4702	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4703
4704	/*
4705	* Execute all queued FIFO commands.
4706	* Quit if pending external command or changes in the thread state.
4707	*/
4708	bool fDone = false;
4709	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4710	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4711	{
4712	uint32_t cbPayload = 0;
4713	uint32_t u32IrqStatus = 0;
4714
4715	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4716
4717	/* First check any pending actions. */
4718	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4719
4720	/* Check for pending external commands (reset). */
4721	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4722	break;
4723
4724	/*
4725	* Process the command.
4726	*/
4727	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4728	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4729	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4730	*/
4731	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4732	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4733	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4734	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4735	switch (enmCmdId)
4736	{
4737	case SVGA_CMD_INVALID_CMD:
4738	/* Nothing to do. */
4739	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4740	break;
4741
4742	case SVGA_CMD_FENCE:
4743	{
4744	SVGAFifoCmdFence *pCmdFence;
4745	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4746	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4747	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4748	{
4749	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4750	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4751
4752	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4753	{
4754	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4755	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4756	}
4757	else
4758	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4759	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4760	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4761	{
4762	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4763	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4764	}
4765	}
4766	else
4767	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4768	break;
4769	}
4770
4771	case SVGA_CMD_UPDATE:
4772	{
4773	SVGAFifoCmdUpdate *pCmd;
4774	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4775	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4776	break;
4777	}
4778
4779	case SVGA_CMD_UPDATE_VERBOSE:
4780	{
4781	SVGAFifoCmdUpdateVerbose *pCmd;
4782	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4783	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4784	break;
4785	}
4786
4787	case SVGA_CMD_DEFINE_CURSOR:
4788	{
4789	/* Followed by bitmap data. */
4790	SVGAFifoCmdDefineCursor *pCmd;
4791	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4792
4793	/* Figure out the size of the bitmap data. */
4794	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4795	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4796	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4797	RT_UNTRUSTED_VALIDATED_FENCE();
4798
4799	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4800	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4801	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4802	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4803
4804	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4805	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4806	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4807	break;
4808	}
4809
4810	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4811	{
4812	/* Followed by bitmap data. */
4813	SVGAFifoCmdDefineAlphaCursor *pCmd;
4814	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4815
4816	/* Figure out the size of the bitmap data. */
4817	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4818
4819	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4820	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4821	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4822	break;
4823	}
4824
4825	case SVGA_CMD_MOVE_CURSOR:
4826	{
4827	/* Deprecated; there should be no driver which requires this command. However, if
4828	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4829	* alignment.
4830	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4831	*/
4832	SVGAFifoCmdMoveCursor *pCmd;
4833	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4834	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4835	break;
4836	}
4837
4838	case SVGA_CMD_DISPLAY_CURSOR:
4839	{
4840	/* Deprecated; there should be no driver which requires this command. However, if
4841	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4842	* alignment.
4843	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4844	*/
4845	SVGAFifoCmdDisplayCursor *pCmd;
4846	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4847	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4848	break;
4849	}
4850
4851	case SVGA_CMD_RECT_FILL:
4852	{
4853	SVGAFifoCmdRectFill *pCmd;
4854	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4855	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4856	break;
4857	}
4858
4859	case SVGA_CMD_RECT_COPY:
4860	{
4861	SVGAFifoCmdRectCopy *pCmd;
4862	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4863	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4864	break;
4865	}
4866
4867	case SVGA_CMD_RECT_ROP_COPY:
4868	{
4869	SVGAFifoCmdRectRopCopy *pCmd;
4870	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4871	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4872	break;
4873	}
4874
4875	case SVGA_CMD_ESCAPE:
4876	{
4877	/* Followed by 'size' bytes of data. */
4878	SVGAFifoCmdEscape *pCmd;
4879	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4880
4881	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4882	RT_UNTRUSTED_VALIDATED_FENCE();
4883
4884	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4885	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4886	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4887	break;
4888	}
4889	# ifdef VBOX_WITH_VMSVGA3D
4890	case SVGA_CMD_DEFINE_GMR2:
4891	{
4892	SVGAFifoCmdDefineGMR2 *pCmd;
4893	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4894	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4895	break;
4896	}
4897
4898	case SVGA_CMD_REMAP_GMR2:
4899	{
4900	/* Followed by page descriptors or guest ptr. */
4901	SVGAFifoCmdRemapGMR2 *pCmd;
4902	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4903
4904	/* Calculate the size of what comes after next and fetch it. */
4905	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4906	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4907	cbCmd += sizeof(SVGAGuestPtr);
4908	else
4909	{
4910	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4911	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4912	{
4913	cbCmd += cbPageDesc;
4914	pCmd->numPages = 1;
4915	}
4916	else
4917	{
4918	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4919	cbCmd += cbPageDesc * pCmd->numPages;
4920	}
4921	}
4922	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4923	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4924	# ifdef DEBUG_GMR_ACCESS
4925	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4926	# endif
4927	break;
4928	}
4929	# endif // VBOX_WITH_VMSVGA3D
4930	case SVGA_CMD_DEFINE_SCREEN:
4931	{
4932	/* The size of this command is specified by the guest and depends on capabilities. */
4933	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4934
4935	SVGAFifoCmdDefineScreen *pCmd;
4936	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4937	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4938	RT_UNTRUSTED_VALIDATED_FENCE();
4939
4940	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4941	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4942	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4943	break;
4944	}
4945
4946	case SVGA_CMD_DESTROY_SCREEN:
4947	{
4948	SVGAFifoCmdDestroyScreen *pCmd;
4949	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4950	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4951	break;
4952	}
4953
4954	case SVGA_CMD_DEFINE_GMRFB:
4955	{
4956	SVGAFifoCmdDefineGMRFB *pCmd;
4957	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4958	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4959	break;
4960	}
4961
4962	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4963	{
4964	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4965	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4966	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4967	break;
4968	}
4969
4970	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4971	{
4972	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4973	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4974	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4975	break;
4976	}
4977
4978	case SVGA_CMD_ANNOTATION_FILL:
4979	{
4980	SVGAFifoCmdAnnotationFill *pCmd;
4981	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4982	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4983	break;
4984	}
4985
4986	case SVGA_CMD_ANNOTATION_COPY:
4987	{
4988	SVGAFifoCmdAnnotationCopy *pCmd;
4989	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4990	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4991	break;
4992	}
4993
4994	default:
4995	# ifdef VBOX_WITH_VMSVGA3D
4996	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4997	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4998	{
4999	RT_UNTRUSTED_VALIDATED_FENCE();
5000
5001	/* All 3d commands start with a common header, which defines the identifier and the size
5002	* of the command. The identifier has been already read from FIFO. Fetch the size.
5003	*/
5004	uint32_t *pcbCmd;
5005	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5006	uint32_t const cbCmd = *pcbCmd;
5007	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5008	uint32_t *pu32Cmd;
5009	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5010	pu32Cmd++; /* Skip the command size. */
5011
5012	if (RT_LIKELY(pThis->svga.f3DEnabled))
5013	{ /* likely */ }
5014	else
5015	{
5016	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5017	break;
5018	}
5019
5020	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5021	}
5022	else
5023	# endif // VBOX_WITH_VMSVGA3D
5024	{
5025	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5026	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5027	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5028	}
5029	}
5030
5031	/* Go to the next slot */
5032	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5033	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5034	if (offCurrentCmd >= offFifoMax)
5035	{
5036	offCurrentCmd -= offFifoMax - offFifoMin;
5037	Assert(offCurrentCmd >= offFifoMin);
5038	Assert(offCurrentCmd < offFifoMax);
5039	}
5040	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5041	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5042
5043	/*
5044	* Raise IRQ if required. Must enter the critical section here
5045	* before making final decisions here, otherwise cubebench and
5046	* others may end up waiting forever.
5047	*/
5048	if ( u32IrqStatus
5049	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5050	{
5051	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5052	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5053
5054	/* FIFO progress might trigger an interrupt. */
5055	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5056	{
5057	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5058	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5059	}
5060
5061	/* Unmasked IRQ pending? */
5062	if (pThis->svga.u32IrqMask & u32IrqStatus)
5063	{
5064	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5065	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5066	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5067	}
5068
5069	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5070	}
5071	}
5072
5073	/* If really done, clear the busy flag. */
5074	if (fDone)
5075	{
5076	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5077	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5078	}
5079	}
5080
5081	/*
5082	* Free the bounce buffer. (There are no returns above!)
5083	*/
5084	RTMemFree(pbBounceBuf);
5085
5086	return VINF_SUCCESS;
5087	}
5088
5089	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5090	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5091
5092	/**
5093	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5094	* Unblock the FIFO I/O thread so it can respond to a state change.}
5095	*/
5096	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5097	{
5098	RT_NOREF(pDevIns);
5099	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5100	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5101	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5102	}
5103
5104	/**
5105	* Enables or disables dirty page tracking for the framebuffer
5106	*
5107	* @param pDevIns The device instance.
5108	* @param pThis The shared VGA/VMSVGA instance data.
5109	* @param fTraces Enable/disable traces
5110	*/
5111	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5112	{
5113	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5114	&& !fTraces)
5115	{
5116	//Assert(pThis->svga.fTraces);
5117	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5118	return;
5119	}
5120
5121	pThis->svga.fTraces = fTraces;
5122	if (pThis->svga.fTraces)
5123	{
5124	unsigned cbFrameBuffer = pThis->vram_size;
5125
5126	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5127	/** @todo How does this work with screens? */
5128	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5129	{
5130	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5131	Assert(pThis->svga.cbScanline);
5132	# endif
5133	/* Hardware enabled; return real framebuffer size .*/
5134	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5135	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5136	}
5137
5138	if (!pThis->svga.fVRAMTracking)
5139	{
5140	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5141	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5142	pThis->svga.fVRAMTracking = true;
5143	}
5144	}
5145	else
5146	{
5147	if (pThis->svga.fVRAMTracking)
5148	{
5149	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5150	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5151	pThis->svga.fVRAMTracking = false;
5152	}
5153	}
5154	}
5155
5156	/**
5157	* @callback_method_impl{FNPCIIOREGIONMAP}
5158	*/
5159	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5160	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5161	{
5162	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5163	int rc;
5164	RT_NOREF(pPciDev);
5165	Assert(pPciDev == pDevIns->apPciDevs[0]);
5166
5167	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5168	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5169	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5170	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5171	, VERR_INTERNAL_ERROR);
5172	if (GCPhysAddress != NIL_RTGCPHYS)
5173	{
5174	/*
5175	* Mapping the FIFO RAM.
5176	*/
5177	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5178	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5179	AssertRC(rc);
5180
5181	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5182	if (RT_SUCCESS(rc))
5183	{
5184	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5185	# ifdef DEBUG_FIFO_ACCESS
5186	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5187	# else
5188	GCPhysAddress + PAGE_SIZE - 1,
5189	# endif
5190	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5191	"VMSVGA FIFO");
5192	AssertRC(rc);
5193	}
5194	# endif
5195	if (RT_SUCCESS(rc))
5196	{
5197	pThis->svga.GCPhysFIFO = GCPhysAddress;
5198	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5199	}
5200	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5201	}
5202	else
5203	{
5204	Assert(pThis->svga.GCPhysFIFO);
5205	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5206	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5207	AssertRC(rc);
5208	# else
5209	rc = VINF_SUCCESS;
5210	# endif
5211	pThis->svga.GCPhysFIFO = 0;
5212	}
5213	return rc;
5214	}
5215
5216	# ifdef VBOX_WITH_VMSVGA3D
5217
5218	/**
5219	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5220	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5221	*
5222	* @param pDevIns The device instance.
5223	* @param pThis The The shared VGA/VMSVGA instance data.
5224	* @param pThisCC The VGA/VMSVGA state for ring-3.
5225	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5226	* UINT32_MAX is used, all surfaces are processed.
5227	*/
5228	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5229	{
5230	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5231	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5232	}
5233
5234
5235	/**
5236	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5237	*/
5238	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5239	{
5240	/* There might be a specific surface ID at the start of the
5241	arguments, if not show all surfaces. */
5242	uint32_t sid = UINT32_MAX;
5243	if (pszArgs)
5244	pszArgs = RTStrStripL(pszArgs);
5245	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5246	sid = RTStrToUInt32(pszArgs);
5247
5248	/* Verbose or terse display, we default to verbose. */
5249	bool fVerbose = true;
5250	if (RTStrIStr(pszArgs, "terse"))
5251	fVerbose = false;
5252
5253	/* The size of the ascii art (x direction, y is 3/4 of x). */
5254	uint32_t cxAscii = 80;
5255	if (RTStrIStr(pszArgs, "gigantic"))
5256	cxAscii = 300;
5257	else if (RTStrIStr(pszArgs, "huge"))
5258	cxAscii = 180;
5259	else if (RTStrIStr(pszArgs, "big"))
5260	cxAscii = 132;
5261	else if (RTStrIStr(pszArgs, "normal"))
5262	cxAscii = 80;
5263	else if (RTStrIStr(pszArgs, "medium"))
5264	cxAscii = 64;
5265	else if (RTStrIStr(pszArgs, "small"))
5266	cxAscii = 48;
5267	else if (RTStrIStr(pszArgs, "tiny"))
5268	cxAscii = 24;
5269
5270	/* Y invert the image when producing the ASCII art. */
5271	bool fInvY = false;
5272	if (RTStrIStr(pszArgs, "invy"))
5273	fInvY = true;
5274
5275	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5276	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5277	}
5278
5279
5280	/**
5281	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5282	*/
5283	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5284	{
5285	/* pszArg = "sid[>dir]"
5286	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5287	*/
5288	char *pszBitmapPath = NULL;
5289	uint32_t sid = UINT32_MAX;
5290	if (pszArgs)
5291	pszArgs = RTStrStripL(pszArgs);
5292	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5293	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5294	if ( pszBitmapPath
5295	&& *pszBitmapPath == '>')
5296	++pszBitmapPath;
5297
5298	const bool fVerbose = true;
5299	const uint32_t cxAscii = 0; /* No ASCII */
5300	const bool fInvY = false; /* Do not invert. */
5301	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5302	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5303	}
5304
5305	/**
5306	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5307	*/
5308	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5309	{
5310	/* There might be a specific surface ID at the start of the
5311	arguments, if not show all contexts. */
5312	uint32_t sid = UINT32_MAX;
5313	if (pszArgs)
5314	pszArgs = RTStrStripL(pszArgs);
5315	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5316	sid = RTStrToUInt32(pszArgs);
5317
5318	/* Verbose or terse display, we default to verbose. */
5319	bool fVerbose = true;
5320	if (RTStrIStr(pszArgs, "terse"))
5321	fVerbose = false;
5322
5323	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5324	}
5325	# endif /* VBOX_WITH_VMSVGA3D */
5326
5327	/**
5328	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5329	*/
5330	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5331	{
5332	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5333	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5334	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5335	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5336	RT_NOREF(pszArgs);
5337
5338	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5339	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5340	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5341	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5342	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5343	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5344	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5345	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5346	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5347	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5348	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5349	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5350	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5351	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5352	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5353	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5354	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5355	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5356	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5357	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5358	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5359	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5360	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5361	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5362	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5363
5364	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5365	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5366	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5367	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5368
5369	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5370	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5371
5372	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5373	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5374
5375	# ifdef VBOX_WITH_VMSVGA3D
5376	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5377	# endif
5378	if (pThisCC->pDrv)
5379	{
5380	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5381	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5382	}
5383
5384	/* Dump screen information. */
5385	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5386	{
5387	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5388	if (pScreen)
5389	{
5390	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5391	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5392	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5393	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5394	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5395	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5396	{
5397	pHlp->pfnPrintf(pHlp, " (");
5398	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5399	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5400	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5401	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5402	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5403	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5404	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5405	pHlp->pfnPrintf(pHlp, " BLANKING");
5406	pHlp->pfnPrintf(pHlp, " )");
5407	}
5408	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5409	}
5410	}
5411
5412	}
5413
5414	/**
5415	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5416	*/
5417	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5418	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5419	{
5420	RT_NOREF(uPass);
5421
5422	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5423	int rc;
5424
5425	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5426	{
5427	uint32_t cScreens = 0;
5428	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5429	AssertRCReturn(rc, rc);
5430	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5431	("cScreens=%#x\n", cScreens),
5432	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5433
5434	for (uint32_t i = 0; i < cScreens; ++i)
5435	{
5436	VMSVGASCREENOBJECT screen;
5437	RT_ZERO(screen);
5438
5439	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5440	AssertLogRelRCReturn(rc, rc);
5441
5442	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5443	{
5444	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5445	*pScreen = screen;
5446	pScreen->fModified = true;
5447	}
5448	else
5449	{
5450	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5451	}
5452	}
5453	}
5454	else
5455	{
5456	/* Try to setup at least the first screen. */
5457	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5458	pScreen->fDefined = true;
5459	pScreen->fModified = true;
5460	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5461	pScreen->idScreen = 0;
5462	pScreen->xOrigin = 0;
5463	pScreen->yOrigin = 0;
5464	pScreen->offVRAM = pThis->svga.uScreenOffset;
5465	pScreen->cbPitch = pThis->svga.cbScanline;
5466	pScreen->cWidth = pThis->svga.uWidth;
5467	pScreen->cHeight = pThis->svga.uHeight;
5468	pScreen->cBpp = pThis->svga.uBpp;
5469	}
5470
5471	return VINF_SUCCESS;
5472	}
5473
5474	/**
5475	* @copydoc FNSSMDEVLOADEXEC
5476	*/
5477	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5478	{
5479	RT_NOREF(uPass);
5480	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5481	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5482	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5483	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5484	int rc;
5485
5486	/* Load our part of the VGAState */
5487	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5488	AssertRCReturn(rc, rc);
5489
5490	/* Load the VGA framebuffer. */
5491	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5492	uint32_t cbVgaFramebuffer = _32K;
5493	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5494	{
5495	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5496	AssertRCReturn(rc, rc);
5497	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5498	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5499	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5500	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5501	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5502	}
5503	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5504	AssertRCReturn(rc, rc);
5505	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5506	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5507	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5508	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5509
5510	/* Load the VMSVGA state. */
5511	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5512	AssertRCReturn(rc, rc);
5513
5514	/* Load the active cursor bitmaps. */
5515	if (pSVGAState->Cursor.fActive)
5516	{
5517	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5518	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5519
5520	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5521	AssertRCReturn(rc, rc);
5522	}
5523
5524	/* Load the GMR state. */
5525	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5526	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5527	{
5528	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5529	AssertRCReturn(rc, rc);
5530	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5531	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5532	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5533	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5534	}
5535
5536	if (pThis->svga.cGMR != cGMR)
5537	{
5538	/* Reallocate GMR array. */
5539	Assert(pSVGAState->paGMR != NULL);
5540	RTMemFree(pSVGAState->paGMR);
5541	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5542	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5543	pThis->svga.cGMR = cGMR;
5544	}
5545
5546	for (uint32_t i = 0; i < cGMR; ++i)
5547	{
5548	PGMR pGMR = &pSVGAState->paGMR[i];
5549
5550	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5551	AssertRCReturn(rc, rc);
5552
5553	if (pGMR->numDescriptors)
5554	{
5555	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5556	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5557	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5558
5559	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5560	{
5561	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5562	AssertRCReturn(rc, rc);
5563	}
5564	}
5565	}
5566
5567	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5568	if (pThis->svga.f3DEnabled)
5569	pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
5570	# endif
5571
5572	VMSVGA_STATE_LOAD LoadState;
5573	LoadState.pSSM = pSSM;
5574	LoadState.uVersion = uVersion;
5575	LoadState.uPass = uPass;
5576	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5577	AssertLogRelRCReturn(rc, rc);
5578
5579	return VINF_SUCCESS;
5580	}
5581
5582	/**
5583	* Reinit the video mode after the state has been loaded.
5584	*/
5585	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5586	{
5587	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5588	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5589	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5590
5591	/* VMSVGA is working via VBVA interface, therefore it needs to be
5592	* enabled on saved state restore. See @bugref{10071#c7}. */
5593	if (pThis->svga.fEnabled)
5594	{
5595	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
5596	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
5597	}
5598
5599	/* Set the active cursor. */
5600	if (pSVGAState->Cursor.fActive)
5601	{
5602	/* We don't store the alpha flag, but we can take a guess that if
5603	* the old register interface was used, the cursor was B&W.
5604	*/
5605	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5606
5607	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5608	true /fVisible/,
5609	fAlpha,
5610	pSVGAState->Cursor.xHotspot,
5611	pSVGAState->Cursor.yHotspot,
5612	pSVGAState->Cursor.width,
5613	pSVGAState->Cursor.height,
5614	pSVGAState->Cursor.pData);
5615	AssertRC(rc);
5616
5617	if (pThis->svga.uCursorOn)
5618	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5619	}
5620
5621	/* If the VRAM handler should not be registered, we have to explicitly
5622	* unregister it here!
5623	*/
5624	if (!pThis->svga.fVRAMTracking)
5625	{
5626	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5627	}
5628
5629	/* Let the FIFO thread deal with changing the mode. */
5630	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5631
5632	return VINF_SUCCESS;
5633	}
5634
5635	/**
5636	* Portion of SVGA state which must be saved in the FIFO thread.
5637	*/
5638	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5639	{
5640	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5641	int rc;
5642
5643	/* Save the screen objects. */
5644	/* Count defined screen object. */
5645	uint32_t cScreens = 0;
5646	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5647	{
5648	if (pSVGAState->aScreens[i].fDefined)
5649	++cScreens;
5650	}
5651
5652	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5653	AssertLogRelRCReturn(rc, rc);
5654
5655	for (uint32_t i = 0; i < cScreens; ++i)
5656	{
5657	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5658
5659	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5660	AssertLogRelRCReturn(rc, rc);
5661	}
5662	return VINF_SUCCESS;
5663	}
5664
5665	/**
5666	* @copydoc FNSSMDEVSAVEEXEC
5667	*/
5668	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5669	{
5670	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5671	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5672	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5673	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5674	int rc;
5675
5676	/* Save our part of the VGAState */
5677	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5678	AssertLogRelRCReturn(rc, rc);
5679
5680	/* Save the framebuffer backup. */
5681	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5682	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5683	AssertLogRelRCReturn(rc, rc);
5684
5685	/* Save the VMSVGA state. */
5686	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5687	AssertLogRelRCReturn(rc, rc);
5688
5689	/* Save the active cursor bitmaps. */
5690	if (pSVGAState->Cursor.fActive)
5691	{
5692	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5693	AssertLogRelRCReturn(rc, rc);
5694	}
5695
5696	/* Save the GMR state */
5697	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5698	AssertLogRelRCReturn(rc, rc);
5699	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5700	{
5701	PGMR pGMR = &pSVGAState->paGMR[i];
5702
5703	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5704	AssertLogRelRCReturn(rc, rc);
5705
5706	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5707	{
5708	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5709	AssertLogRelRCReturn(rc, rc);
5710	}
5711	}
5712
5713	/*
5714	* Must save some state (3D in particular) in the FIFO thread.
5715	*/
5716	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5717	AssertLogRelRCReturn(rc, rc);
5718
5719	return VINF_SUCCESS;
5720	}
5721
5722	/**
5723	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
5724	*
5725	* @param pThis The shared VGA/VMSVGA instance data.
5726	* @param pThisCC The device context.
5727	*/
5728	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
5729	{
5730	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5731
5732	# ifndef VMSVGA_USE_EMT_HALT_CODE
5733	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5734	{
5735	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5736	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5737	}
5738	# endif
5739
5740	if (pSVGAState->Cursor.fActive)
5741	{
5742	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5743	pSVGAState->Cursor.pData = NULL;
5744	pSVGAState->Cursor.fActive = false;
5745	}
5746
5747	if (pSVGAState->paGMR)
5748	{
5749	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5750	if (pSVGAState->paGMR[i].paDesc)
5751	RTMemFree(pSVGAState->paGMR[i].paDesc);
5752
5753	RTMemFree(pSVGAState->paGMR);
5754	pSVGAState->paGMR = NULL;
5755	}
5756
5757	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5758	{
5759	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5760	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5761	{
5762	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5763	pSVGAState->apCmdBufCtxs[i] = NULL;
5764	}
5765	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5766	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5767	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5768	}
5769	}
5770
5771	/**
5772	* Constructor for PVMSVGAR3STATE structure.
5773	*
5774	* @returns VBox status code.
5775	* @param pDevIns The PDM device instance.
5776	* @param pThis The shared VGA/VMSVGA instance data.
5777	* @param pSVGAState Pointer to the structure. It is already allocated.
5778	*/
5779	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5780	{
5781	int rc = VINF_SUCCESS;
5782
5783	pSVGAState->pDevIns = pDevIns;
5784
5785	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5786	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5787
5788	# ifndef VMSVGA_USE_EMT_HALT_CODE
5789	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5790	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5791	AssertRCReturn(rc, rc);
5792	# endif
5793
5794	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5795	AssertRCReturn(rc, rc);
5796
5797	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5798
5799	RTListInit(&pSVGAState->MOBLRUList);
5800	return rc;
5801	}
5802
5803	# ifdef VBOX_WITH_VMSVGA3D
5804	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
5805	{
5806	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5807
5808	RTMemFree(pSVGAState->pFuncsMap);
5809	pSVGAState->pFuncsMap = NULL;
5810	RTMemFree(pSVGAState->pFuncsGBO);
5811	pSVGAState->pFuncsGBO = NULL;
5812	RTMemFree(pSVGAState->pFuncsDX);
5813	pSVGAState->pFuncsDX = NULL;
5814	RTMemFree(pSVGAState->pFuncsVGPU9);
5815	pSVGAState->pFuncsVGPU9 = NULL;
5816	RTMemFree(pSVGAState->pFuncs3D);
5817	pSVGAState->pFuncs3D = NULL;
5818	}
5819
5820	/* This structure is used only by vmsvgaR3Init3dInterfaces */
5821	typedef struct VMSVGA3DINTERFACE
5822	{
5823	char const *pcszName;
5824	uint32_t cbFuncs;
5825	void **ppvFuncs;
5826	} VMSVGA3DINTERFACE;
5827
5828	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
5829	#ifdef VMSVGA3D_DX
5830	extern VMSVGA3DBACKENDDESC const g_BackendDX;
5831	#endif
5832
5833	/**
5834	* Initializes the optional host 3D backend interfaces.
5835	*
5836	* @returns VBox status code.
5837	* @param pThisCC The VGA/VMSVGA state for ring-3.
5838	*/
5839	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
5840	{
5841	#ifndef VMSVGA3D_DX
5842	RT_NOREF(pThis);
5843	#endif
5844
5845	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5846
5847	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
5848	VMSVGA3DINTERFACE a3dInterface[] =
5849	{
5850	ENTRY_3D_INTERFACE(3D, pFuncs3D),
5851	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
5852	ENTRY_3D_INTERFACE(DX, pFuncsDX),
5853	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
5854	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
5855	};
5856	#undef ENTRY_3D_INTERFACE
5857
5858	VMSVGA3DBACKENDDESC const *pBackend = NULL;
5859	#ifdef VMSVGA3D_DX
5860	if (pThis->fVMSVGA10)
5861	pBackend = &g_BackendDX;
5862	else
5863	#endif
5864	pBackend = &g_BackendLegacy;
5865
5866	int rc = VINF_SUCCESS;
5867	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
5868	{
5869	VMSVGA3DINTERFACE *p = &a3dInterface[i];
5870
5871	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
5872	if (RT_SUCCESS(rc2))
5873	{
5874	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
5875	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
5876
5877	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
5878	}
5879	}
5880
5881	if (RT_SUCCESS(rc))
5882	{
5883	/* 3D interface is required. */
5884	if (pSVGAState->pFuncs3D)
5885	{
5886	rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
5887	if (RT_SUCCESS(rc))
5888	return VINF_SUCCESS;
5889	}
5890	else
5891	rc = VERR_NOT_SUPPORTED;
5892	}
5893
5894	vmsvga3dR3Free3dInterfaces(pThisCC);
5895	return rc;
5896	}
5897	# endif /* VBOX_WITH_VMSVGA3D */
5898
5899	/**
5900	* Initializes the host capabilities: device and FIFO.
5901	*
5902	* @returns VBox status code.
5903	* @param pThis The shared VGA/VMSVGA instance data.
5904	* @param pThisCC The VGA/VMSVGA state for ring-3.
5905	*/
5906	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5907	{
5908	# ifdef VBOX_WITH_VMSVGA3D
5909	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5910	# endif
5911
5912	/* Device caps. */
5913	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5914	\| SVGA_CAP_GMR2
5915	\| SVGA_CAP_CURSOR
5916	\| SVGA_CAP_CURSOR_BYPASS
5917	\| SVGA_CAP_CURSOR_BYPASS_2
5918	\| SVGA_CAP_EXTENDED_FIFO
5919	\| SVGA_CAP_IRQMASK
5920	\| SVGA_CAP_PITCHLOCK
5921	\| SVGA_CAP_RECT_COPY
5922	\| SVGA_CAP_TRACES
5923	\| SVGA_CAP_SCREEN_OBJECT_2
5924	\| SVGA_CAP_ALPHA_CURSOR;
5925
5926	/* VGPU10 capabilities. */
5927	if (pThis->fVMSVGA10)
5928	{
5929	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5930	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5931	;
5932
5933	# ifdef VBOX_WITH_VMSVGA3D
5934	if (pSVGAState->pFuncsGBO)
5935	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5936	if (pSVGAState->pFuncsDX)
5937	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5938	# endif
5939	}
5940
5941	# ifdef VBOX_WITH_VMSVGA3D
5942	if (pSVGAState->pFuncs3D)
5943	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5944	# endif
5945
5946	/* Clear the FIFO. */
5947	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5948
5949	/* Setup FIFO capabilities. */
5950	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5951	\| SVGA_FIFO_CAP_PITCHLOCK
5952	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5953	\| SVGA_FIFO_CAP_RESERVE
5954	\| SVGA_FIFO_CAP_GMR2
5955	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5956	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5957
5958	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5959	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5960	}
5961
5962	# ifdef VBOX_WITH_VMSVGA3D
5963	/**
5964	* Initializes the host 3D capabilities and writes them to FIFO memory.
5965	*
5966	* @returns VBox status code.
5967	* @param pThis The shared VGA/VMSVGA instance data.
5968	* @param pThisCC The VGA/VMSVGA state for ring-3.
5969	*/
5970	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5971	{
5972	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5973	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5974
5975	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5976	{
5977	uint32_t val = 0;
5978	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5979	if (RT_SUCCESS(rc))
5980	pThis->svga.au32DevCaps[i] = val;
5981	else
5982	pThis->svga.au32DevCaps[i] = 0;
5983
5984	/* LogRel the capability value. */
5985	if (i < SVGA3D_DEVCAP_MAX)
5986	{
5987	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5988	if (RT_SUCCESS(rc))
5989	{
5990	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5991	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5992	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5993	{
5994	float const fval = (float )&val;
5995	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5996	}
5997	else
5998	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5999	}
6000	else
6001	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
6002	}
6003	else
6004	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
6005	}
6006
6007	RTLogRelSetBuffering(fSavedBuffering);
6008
6009	/* 3d hardware version; latest and greatest */
6010	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6011	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6012
6013	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
6014	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
6015	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
6016	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
6017	*/
6018	SVGA3dCapsRecord *pCaps;
6019	SVGA3dCapPair *pData;
6020
6021	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6022	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6023	pData = (SVGA3dCapPair *)&pCaps->data;
6024
6025	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6026	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6027	{
6028	pData[i][0] = i;
6029	pData[i][1] = pThis->svga.au32DevCaps[i];
6030	}
6031	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6032	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6033
6034	/* Mark end of record array (a zero word). */
6035	pCaps->header.length = 0;
6036	}
6037
6038	# endif
6039
6040	/**
6041	* Resets the SVGA hardware state
6042	*
6043	* @returns VBox status code.
6044	* @param pDevIns The device instance.
6045	*/
6046	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6047	{
6048	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6049	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6050	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6051
6052	/* Reset before init? */
6053	if (!pSVGAState)
6054	return VINF_SUCCESS;
6055
6056	Log(("vmsvgaR3Reset\n"));
6057
6058	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6059	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6060	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6061
6062	/* Reset other stuff. */
6063	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6064	RT_ZERO(pThis->svga.au32ScratchRegion);
6065
6066	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6067
6068	vmsvgaR3StateTerm(pThis, pThisCC);
6069	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6070
6071	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6072
6073	/* Initialize FIFO and register capabilities. */
6074	vmsvgaR3InitCaps(pThis, pThisCC);
6075
6076	# ifdef VBOX_WITH_VMSVGA3D
6077	if (pThis->svga.f3DEnabled)
6078	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6079	# endif
6080
6081	/* VRAM tracking is enabled by default during bootup. */
6082	pThis->svga.fVRAMTracking = true;
6083	pThis->svga.fEnabled = false;
6084
6085	/* Invalidate current settings. */
6086	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6087	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6088	pThis->svga.uBpp = pThis->svga.uHostBpp;
6089	pThis->svga.cbScanline = 0;
6090	pThis->svga.u32PitchLock = 0;
6091
6092	return rc;
6093	}
6094
6095	/**
6096	* Cleans up the SVGA hardware state
6097	*
6098	* @returns VBox status code.
6099	* @param pDevIns The device instance.
6100	*/
6101	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6102	{
6103	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6104	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6105
6106	/*
6107	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6108	*/
6109	if (pThisCC->svga.pFIFOIOThread)
6110	{
6111	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6112	NULL /pvParam/, 30000 /ms/);
6113	AssertLogRelRC(rc);
6114
6115	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6116	AssertLogRelRC(rc);
6117	pThisCC->svga.pFIFOIOThread = NULL;
6118	}
6119
6120	/*
6121	* Destroy the special SVGA state.
6122	*/
6123	if (pThisCC->svga.pSvgaR3State)
6124	{
6125	vmsvgaR3StateTerm(pThis, pThisCC);
6126
6127	# ifdef VBOX_WITH_VMSVGA3D
6128	vmsvga3dR3Free3dInterfaces(pThisCC);
6129	# endif
6130
6131	RTMemFree(pThisCC->svga.pSvgaR3State);
6132	pThisCC->svga.pSvgaR3State = NULL;
6133	}
6134
6135	/*
6136	* Free our resources residing in the VGA state.
6137	*/
6138	if (pThisCC->svga.pbVgaFrameBufferR3)
6139	{
6140	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6141	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6142	}
6143	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6144	{
6145	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6146	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6147	}
6148	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6149	{
6150	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6151	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6152	}
6153
6154	return VINF_SUCCESS;
6155	}
6156
6157	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6158	const char pszType, void const pvValue,
6159	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6160	{
6161	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6162	double const v = (double )&pvValue;
6163	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6164	}
6165
6166	/**
6167	* Initialize the SVGA hardware state
6168	*
6169	* @returns VBox status code.
6170	* @param pDevIns The device instance.
6171	*/
6172	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6173	{
6174	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6175	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6176	PVMSVGAR3STATE pSVGAState;
6177	int rc;
6178
6179	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6180	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6181
6182	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6183	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6184
6185	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6186
6187	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6188	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6189	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6190
6191	/* Create event semaphore. */
6192	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6193	AssertRCReturn(rc, rc);
6194
6195	/* Create event semaphore. */
6196	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6197	AssertRCReturn(rc, rc);
6198
6199	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6200	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6201
6202	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6203	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6204
6205	pSVGAState = pThisCC->svga.pSvgaR3State;
6206
6207	/* Register the write-protected GBO access handler type. */
6208	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6209	vmsvgaR3GboAccessHandler,
6210	NULL, NULL, NULL,
6211	NULL, NULL, NULL,
6212	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6213	AssertRCReturn(rc, rc);
6214
6215	# ifdef VBOX_WITH_VMSVGA3D
6216	if (pThis->svga.f3DEnabled)
6217	{
6218	/* Load a 3D backend. */
6219	rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
6220	if (RT_FAILURE(rc))
6221	{
6222	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6223	pThis->svga.f3DEnabled = false;
6224	}
6225	}
6226	# endif
6227
6228	/* Initialize FIFO and register capabilities. */
6229	vmsvgaR3InitCaps(pThis, pThisCC);
6230
6231	/* VRAM tracking is enabled by default during bootup. */
6232	pThis->svga.fVRAMTracking = true;
6233
6234	/* Set up the host bpp. This value is as a default for the programmable
6235	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6236	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6237	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6238	*
6239	* NB: The driver cBits value is currently constant for the lifetime of the
6240	* VM. If that changes, the host bpp logic might need revisiting.
6241	*/
6242	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6243
6244	/* Invalidate current settings. */
6245	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6246	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6247	pThis->svga.uBpp = pThis->svga.uHostBpp;
6248	pThis->svga.cbScanline = 0;
6249
6250	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
6251	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
6252	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6253	{
6254	pThis->svga.u32MaxWidth -= 256;
6255	pThis->svga.u32MaxHeight -= 256;
6256	}
6257	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6258
6259	# ifdef DEBUG_GMR_ACCESS
6260	/* Register the GMR access handler type. */
6261	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6262	vmsvgaR3GmrAccessHandler,
6263	NULL, NULL, NULL,
6264	NULL, NULL, NULL,
6265	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6266	AssertRCReturn(rc, rc);
6267	# endif
6268
6269	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6270	/* Register the FIFO access handler type. In addition to
6271	debugging FIFO access, this is also used to facilitate
6272	extended fifo thread sleeps. */
6273	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6274	# ifdef DEBUG_FIFO_ACCESS
6275	PGMPHYSHANDLERKIND_ALL,
6276	# else
6277	PGMPHYSHANDLERKIND_WRITE,
6278	# endif
6279	vmsvgaR3FifoAccessHandler,
6280	NULL, NULL, NULL,
6281	NULL, NULL, NULL,
6282	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6283	AssertRCReturn(rc, rc);
6284	# endif
6285
6286	/* Create the async IO thread. */
6287	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6288	RTTHREADTYPE_IO, "VMSVGA FIFO");
6289	if (RT_FAILURE(rc))
6290	{
6291	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6292	return rc;
6293	}
6294
6295	/*
6296	* Statistics.
6297	*/
6298	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6299	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6300	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6301	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6302	# ifdef VBOX_WITH_STATISTICS
6303	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6304	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6305	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6306	# endif
6307	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6308	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6309	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6310	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6311	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6312	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6313	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6314	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6315	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6316	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6317	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6318	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6319	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6320	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6321	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6322	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6323	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6324	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6325	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6326	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6327	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6328	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6329	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6330	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6331	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6332	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6333	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6334	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6335	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6336	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6337	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6338	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6339	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6340	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6341	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6342	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6343	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6344	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6345	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6346	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6347	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6348	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6349	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6350	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6351	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6352	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6353	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6354	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6355	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6356	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6357	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6358	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6359	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6360	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6361	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6362	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6363	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6364	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6365	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6366
6367	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6368	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6369	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6370	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6371	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6372	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6373	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6374	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6375	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6376	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6377	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6378	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6379	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6380	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6381	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6382	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6383	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6384	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6385	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6386	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6387	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6388	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6389	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6390	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6391	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6392	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6393	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6394	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6395	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6396	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6397	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6398	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6399	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6400	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6401	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6402	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6403	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6404	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6405	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6406	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6407
6408	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6409	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6410	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6411	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6412	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6413	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6414	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6415	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6416	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6417	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6418	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6419	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6420	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6421	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6422	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6423	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6424	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6425	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6426	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6427	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6428	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6429	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6430	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6431	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6432	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6433	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6434	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6435	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6436	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6437	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6438	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6439	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6440	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6441	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6442	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6443	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6444	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6445	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6446	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6447	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6448	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6449	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6450	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6451	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6452	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6453	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6454	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6455	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6456	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6457	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6458	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6459	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6460	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6461	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6462	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6463	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6464	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6465	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6466	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6467	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6468	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6469	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6470
6471	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6472	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6473	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6474	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6475	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6476	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6477	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6478	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6479	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6480	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6481	# endif
6482	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6483	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6484	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6485	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6486	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6487
6488	# undef REG_CNT
6489	# undef REG_PRF
6490
6491	/*
6492	* Info handlers.
6493	*/
6494	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6495	# ifdef VBOX_WITH_VMSVGA3D
6496	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6497	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6498	"VMSVGA 3d surface details. "
6499	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6500	vmsvgaR3Info3dSurface);
6501	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6502	"VMSVGA 3d surface details and bitmap: "
6503	"sid[>dir]",
6504	vmsvgaR3Info3dSurfaceBmp);
6505	# endif
6506
6507	return VINF_SUCCESS;
6508	}
6509
6510	/**
6511	* Power On notification.
6512	*
6513	* @returns VBox status code.
6514	* @param pDevIns The device instance data.
6515	*
6516	* @remarks Caller enters the device critical section.
6517	*/
6518	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6519	{
6520	# ifdef VBOX_WITH_VMSVGA3D
6521	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6522	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6523	if (pThis->svga.f3DEnabled)
6524	{
6525	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6526	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
6527	if (RT_SUCCESS(rc))
6528	{
6529	/* Initialize FIFO 3D capabilities. */
6530	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6531	}
6532	else
6533	{
6534	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
6535	pThis->svga.f3DEnabled = false;
6536	}
6537	}
6538	# else /* !VBOX_WITH_VMSVGA3D */
6539	RT_NOREF(pDevIns);
6540	# endif /* !VBOX_WITH_VMSVGA3D */
6541	}
6542
6543	/**
6544	* Power Off notification.
6545	*
6546	* @param pDevIns The device instance data.
6547	*
6548	* @remarks Caller enters the device critical section.
6549	*/
6550	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6551	{
6552	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6553	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6554
6555	/*
6556	* Notify the FIFO thread.
6557	*/
6558	if (pThisCC->svga.pFIFOIOThread)
6559	{
6560	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6561	NULL /pvParam/, 30000 /ms/);
6562	AssertLogRelRC(rc);
6563	}
6564	}
6565
6566	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 90894

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