DevVGA-SVGA.cpp@ 69304

Last change on this file since 69304 was 69242, checked in by vboxsync, 7 years ago
Devices/Graphics: VMSVGA: support vertex divisors in vmsvga3dDrawPrimitives.
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1	/* $Id: DevVGA-SVGA.cpp 69242 2017-10-24 16:22:20Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2017 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/VMMDev.h>
148	#include <VBoxVideo.h>
149	#include <VBox/bioslogo.h>
150
151	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
152	#include "DevVGA.h"
153
154	#include "DevVGA-SVGA.h"
155	#include "vmsvga/svga_reg.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_reg.h"
159	#include "vmsvga/svga3d_caps.h"
160	#ifdef VBOX_WITH_VMSVGA3D
161	# include "DevVGA-SVGA3d.h"
162	# ifdef RT_OS_DARWIN
163	# include "DevVGA-SVGA3d-cocoa.h"
164	# endif
165	#endif
166
167
168	/*********************************************************************************************************************************
169	* Defined Constants And Macros *
170	*********************************************************************************************************************************/
171	/**
172	* Macro for checking if a fixed FIFO register is valid according to the
173	* current FIFO configuration.
174	*
175	* @returns true / false.
176	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
177	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
178	*/
179	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* 64-bit GMR descriptor.
187	*/
188	typedef struct
189	{
190	RTGCPHYS GCPhys;
191	uint64_t numPages;
192	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
193
194	/**
195	* GMR slot
196	*/
197	typedef struct
198	{
199	uint32_t cMaxPages;
200	uint32_t cbTotal;
201	uint32_t numDescriptors;
202	PVMSVGAGMRDESCRIPTOR paDesc;
203	} GMR, *PGMR;
204
205	#ifdef IN_RING3
206	/**
207	* Internal SVGA ring-3 only state.
208	*/
209	typedef struct VMSVGAR3STATE
210	{
211	GMR *paGMR; // [VMSVGAState::cGMR]
212	struct
213	{
214	SVGAGuestPtr ptr;
215	uint32_t bytesPerLine;
216	SVGAGMRImageFormat format;
217	} GMRFB;
218	struct
219	{
220	bool fActive;
221	uint32_t xHotspot;
222	uint32_t yHotspot;
223	uint32_t width;
224	uint32_t height;
225	uint32_t cbData;
226	void *pData;
227	} Cursor;
228	SVGAColorBGRX colorAnnotation;
229
230	# ifdef VMSVGA_USE_EMT_HALT_CODE
231	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
232	uint32_t volatile cBusyDelayedEmts;
233	/** Set of EMTs that are */
234	VMCPUSET BusyDelayedEmts;
235	# else
236	/** Number of EMTs waiting on hBusyDelayedEmts. */
237	uint32_t volatile cBusyDelayedEmts;
238	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
239	* busy (ugly). */
240	RTSEMEVENTMULTI hBusyDelayedEmts;
241	# endif
242	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
243	STAMPROFILE StatBusyDelayEmts;
244
245	STAMPROFILE StatR3Cmd3dPresentProf;
246	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
247	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
248	STAMCOUNTER StatR3CmdDefineGmr2;
249	STAMCOUNTER StatR3CmdDefineGmr2Free;
250	STAMCOUNTER StatR3CmdDefineGmr2Modify;
251	STAMCOUNTER StatR3CmdRemapGmr2;
252	STAMCOUNTER StatR3CmdRemapGmr2Modify;
253	STAMCOUNTER StatR3CmdInvalidCmd;
254	STAMCOUNTER StatR3CmdFence;
255	STAMCOUNTER StatR3CmdUpdate;
256	STAMCOUNTER StatR3CmdUpdateVerbose;
257	STAMCOUNTER StatR3CmdDefineCursor;
258	STAMCOUNTER StatR3CmdDefineAlphaCursor;
259	STAMCOUNTER StatR3CmdEscape;
260	STAMCOUNTER StatR3CmdDefineScreen;
261	STAMCOUNTER StatR3CmdDestroyScreen;
262	STAMCOUNTER StatR3CmdDefineGmrFb;
263	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
264	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
265	STAMCOUNTER StatR3CmdAnnotationFill;
266	STAMCOUNTER StatR3CmdAnnotationCopy;
267	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
268	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
269	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
270	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
271	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
272	STAMCOUNTER StatR3Cmd3dSurfaceDma;
273	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
274	STAMCOUNTER StatR3Cmd3dContextDefine;
275	STAMCOUNTER StatR3Cmd3dContextDestroy;
276	STAMCOUNTER StatR3Cmd3dSetTransform;
277	STAMCOUNTER StatR3Cmd3dSetZRange;
278	STAMCOUNTER StatR3Cmd3dSetRenderState;
279	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
280	STAMCOUNTER StatR3Cmd3dSetTextureState;
281	STAMCOUNTER StatR3Cmd3dSetMaterial;
282	STAMCOUNTER StatR3Cmd3dSetLightData;
283	STAMCOUNTER StatR3Cmd3dSetLightEnable;
284	STAMCOUNTER StatR3Cmd3dSetViewPort;
285	STAMCOUNTER StatR3Cmd3dSetClipPlane;
286	STAMCOUNTER StatR3Cmd3dClear;
287	STAMCOUNTER StatR3Cmd3dPresent;
288	STAMCOUNTER StatR3Cmd3dPresentReadBack;
289	STAMCOUNTER StatR3Cmd3dShaderDefine;
290	STAMCOUNTER StatR3Cmd3dShaderDestroy;
291	STAMCOUNTER StatR3Cmd3dSetShader;
292	STAMCOUNTER StatR3Cmd3dSetShaderConst;
293	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
294	STAMCOUNTER StatR3Cmd3dSetScissorRect;
295	STAMCOUNTER StatR3Cmd3dBeginQuery;
296	STAMCOUNTER StatR3Cmd3dEndQuery;
297	STAMCOUNTER StatR3Cmd3dWaitForQuery;
298	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
299	STAMCOUNTER StatR3Cmd3dActivateSurface;
300	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
301
302	STAMCOUNTER StatR3RegConfigDoneWr;
303	STAMCOUNTER StatR3RegGmrDescriptorWr;
304	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
305	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
306
307	STAMCOUNTER StatFifoCommands;
308	STAMCOUNTER StatFifoErrors;
309	STAMCOUNTER StatFifoUnkCmds;
310	STAMCOUNTER StatFifoTodoTimeout;
311	STAMCOUNTER StatFifoTodoWoken;
312	STAMPROFILE StatFifoStalls;
313
314	} VMSVGAR3STATE, *PVMSVGAR3STATE;
315	#endif /* IN_RING3 */
316
317
318	/*********************************************************************************************************************************
319	* Internal Functions *
320	*********************************************************************************************************************************/
321	#ifdef IN_RING3
322	# ifdef DEBUG_FIFO_ACCESS
323	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
324	# endif
325	# ifdef DEBUG_GMR_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
327	# endif
328	#endif
329
330
331	/*********************************************************************************************************************************
332	* Global Variables *
333	*********************************************************************************************************************************/
334	#ifdef IN_RING3
335
336	/**
337	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
338	*/
339	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
340	{
341	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
342	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
343	SSMFIELD_ENTRY_TERM()
344	};
345
346	/**
347	* SSM descriptor table for the GMR structure.
348	*/
349	static SSMFIELD const g_aGMRFields[] =
350	{
351	SSMFIELD_ENTRY( GMR, cMaxPages),
352	SSMFIELD_ENTRY( GMR, cbTotal),
353	SSMFIELD_ENTRY( GMR, numDescriptors),
354	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
355	SSMFIELD_ENTRY_TERM()
356	};
357
358	/**
359	* SSM descriptor table for the VMSVGAR3STATE structure.
360	*/
361	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
362	{
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
364	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
365	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
366	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
367	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
368	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
369	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
370	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
371	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
372	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
374	#ifdef VMSVGA_USE_EMT_HALT_CODE
375	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
376	#else
377	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
378	#endif
379	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
380	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
381	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
382	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
383	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
387	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
388	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
389	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
393	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
394	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
398	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
400	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
436
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
441
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
448	SSMFIELD_ENTRY_TERM()
449	};
450
451	/**
452	* SSM descriptor table for the VGAState.svga structure.
453	*/
454	static SSMFIELD const g_aVGAStateSVGAFields[] =
455	{
456	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
457	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
458	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
459	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
460	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
461	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
462	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
463	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
466	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
467	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
468	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
469	SSMFIELD_ENTRY( VMSVGAState, fBusy),
470	SSMFIELD_ENTRY( VMSVGAState, fTraces),
471	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
472	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
473	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
474	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
475	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
476	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
477	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
478	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
480	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
485	SSMFIELD_ENTRY( VMSVGAState, uWidth),
486	SSMFIELD_ENTRY( VMSVGAState, uHeight),
487	SSMFIELD_ENTRY( VMSVGAState, uBpp),
488	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
489	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
490	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
491	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
492	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
493	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
497	SSMFIELD_ENTRY_TERM()
498	};
499
500	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
501
502	#endif /* IN_RING3 */
503
504	#ifdef LOG_ENABLED
505
506	/**
507	* Index register string name lookup
508	*
509	* @returns Index register string or "UNKNOWN"
510	* @param pThis VMSVGA State
511	* @param idxReg The index register.
512	*/
513	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
514	{
515	switch (idxReg)
516	{
517	case SVGA_REG_ID: return "SVGA_REG_ID";
518	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
519	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
520	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
521	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
522	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
523	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
524	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
525	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
526	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
527	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
528	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
529	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
530	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
531	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
532	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
533	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
534	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
535	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
536	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
537	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
538	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
539	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
540	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
541	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
542	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
543	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
544	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
545	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
546	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
547	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
548	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
549	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
550	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
551	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
552	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
553	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
554	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
555	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
556	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
557	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
558	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
559	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
560	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
561	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
562	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
563	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
564	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
565	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
566	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
567
568	default:
569	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
570	return "SVGA_SCRATCH_BASE reg";
571	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
572	return "SVGA_PALETTE_BASE reg";
573	return "UNKNOWN";
574	}
575	}
576
577	#ifdef IN_RING3
578	/**
579	* FIFO command name lookup
580	*
581	* @returns FIFO command string or "UNKNOWN"
582	* @param u32Cmd FIFO command
583	*/
584	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
585	{
586	switch (u32Cmd)
587	{
588	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
589	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
590	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
591	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
592	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
593	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
594	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
595	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
596	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
597	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
598	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
599	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
600	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
601	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
602	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
603	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
604	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
605	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
606	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
607	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
608	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
609	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
610	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
611	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
612	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
613	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
614	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
615	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
616	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
617	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
618	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
619	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
620	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
621	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
622	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
623	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
624	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
625	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
626	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
627	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
628	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
629	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
630	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
631	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
632	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
633	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
634	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
635	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
636	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
637	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
638	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
639	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
640	default: return "UNKNOWN";
641	}
642	}
643	# endif /* IN_RING3 */
644
645	#endif /* LOG_ENABLED */
646
647	#ifdef IN_RING3
648	/**
649	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
650	*/
651	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
652	{
653	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
654
655	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
656	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
657
658	if (x < pThis->svga.uWidth)
659	{
660	pThis->svga.viewport.x = x;
661	pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
662	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
663	}
664	else
665	{
666	pThis->svga.viewport.x = pThis->svga.uWidth;
667	pThis->svga.viewport.cx = 0;
668	pThis->svga.viewport.xRight = pThis->svga.uWidth;
669	}
670	if (y < pThis->svga.uHeight)
671	{
672	pThis->svga.viewport.y = y;
673	pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
674	pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
675	pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
676	}
677	else
678	{
679	pThis->svga.viewport.y = pThis->svga.uHeight;
680	pThis->svga.viewport.cy = 0;
681	pThis->svga.viewport.yLowWC = 0;
682	pThis->svga.viewport.yHighWC = 0;
683	}
684
685	# ifdef VBOX_WITH_VMSVGA3D
686	/*
687	* Now inform the 3D backend.
688	*/
689	if (pThis->svga.f3DEnabled)
690	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
691	# else
692	RT_NOREF(idScreen, OldViewport);
693	# endif
694	}
695	#endif /* IN_RING3 */
696
697	/**
698	* Read port register
699	*
700	* @returns VBox status code.
701	* @param pThis VMSVGA State
702	* @param pu32 Where to store the read value
703	*/
704	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
705	{
706	int rc = VINF_SUCCESS;
707	*pu32 = 0;
708
709	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
710	uint32_t idxReg = pThis->svga.u32IndexReg;
711	if ( idxReg >= SVGA_REG_CAPABILITIES
712	&& pThis->svga.u32SVGAId == SVGA_ID_0)
713	{
714	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
715	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
716	}
717
718	switch (idxReg)
719	{
720	case SVGA_REG_ID:
721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
722	*pu32 = pThis->svga.u32SVGAId;
723	break;
724
725	case SVGA_REG_ENABLE:
726	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
727	*pu32 = pThis->svga.fEnabled;
728	break;
729
730	case SVGA_REG_WIDTH:
731	{
732	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
733	if ( pThis->svga.fEnabled
734	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
735	{
736	*pu32 = pThis->svga.uWidth;
737	}
738	else
739	{
740	#ifndef IN_RING3
741	rc = VINF_IOM_R3_IOPORT_READ;
742	#else
743	*pu32 = pThis->pDrv->cx;
744	#endif
745	}
746	break;
747	}
748
749	case SVGA_REG_HEIGHT:
750	{
751	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
752	if ( pThis->svga.fEnabled
753	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
754	{
755	*pu32 = pThis->svga.uHeight;
756	}
757	else
758	{
759	#ifndef IN_RING3
760	rc = VINF_IOM_R3_IOPORT_READ;
761	#else
762	*pu32 = pThis->pDrv->cy;
763	#endif
764	}
765	break;
766	}
767
768	case SVGA_REG_MAX_WIDTH:
769	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
770	*pu32 = pThis->svga.u32MaxWidth;
771	break;
772
773	case SVGA_REG_MAX_HEIGHT:
774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
775	*pu32 = pThis->svga.u32MaxHeight;
776	break;
777
778	case SVGA_REG_DEPTH:
779	/* This returns the color depth of the current mode. */
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
781	switch (pThis->svga.uBpp)
782	{
783	case 15:
784	case 16:
785	case 24:
786	*pu32 = pThis->svga.uBpp;
787	break;
788
789	default:
790	case 32:
791	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
792	break;
793	}
794	break;
795
796	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
797	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
798	if ( pThis->svga.fEnabled
799	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
800	{
801	*pu32 = pThis->svga.uBpp;
802	}
803	else
804	{
805	#ifndef IN_RING3
806	rc = VINF_IOM_R3_IOPORT_READ;
807	#else
808	*pu32 = pThis->pDrv->cBits;
809	#endif
810	}
811	break;
812
813	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
814	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
815	if ( pThis->svga.fEnabled
816	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
817	{
818	*pu32 = (pThis->svga.uBpp + 7) & ~7;
819	}
820	else
821	{
822	#ifndef IN_RING3
823	rc = VINF_IOM_R3_IOPORT_READ;
824	#else
825	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
826	#endif
827	}
828	break;
829
830	case SVGA_REG_PSEUDOCOLOR:
831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
832	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
833	break;
834
835	case SVGA_REG_RED_MASK:
836	case SVGA_REG_GREEN_MASK:
837	case SVGA_REG_BLUE_MASK:
838	{
839	uint32_t uBpp;
840
841	if ( pThis->svga.fEnabled
842	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
843	{
844	uBpp = pThis->svga.uBpp;
845	}
846	else
847	{
848	#ifndef IN_RING3
849	rc = VINF_IOM_R3_IOPORT_READ;
850	break;
851	#else
852	uBpp = pThis->pDrv->cBits;
853	#endif
854	}
855	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
856	switch (uBpp)
857	{
858	case 8:
859	u32RedMask = 0x07;
860	u32GreenMask = 0x38;
861	u32BlueMask = 0xc0;
862	break;
863
864	case 15:
865	u32RedMask = 0x0000001f;
866	u32GreenMask = 0x000003e0;
867	u32BlueMask = 0x00007c00;
868	break;
869
870	case 16:
871	u32RedMask = 0x0000001f;
872	u32GreenMask = 0x000007e0;
873	u32BlueMask = 0x0000f800;
874	break;
875
876	case 24:
877	case 32:
878	default:
879	u32RedMask = 0x00ff0000;
880	u32GreenMask = 0x0000ff00;
881	u32BlueMask = 0x000000ff;
882	break;
883	}
884	switch (idxReg)
885	{
886	case SVGA_REG_RED_MASK:
887	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
888	*pu32 = u32RedMask;
889	break;
890
891	case SVGA_REG_GREEN_MASK:
892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
893	*pu32 = u32GreenMask;
894	break;
895
896	case SVGA_REG_BLUE_MASK:
897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
898	*pu32 = u32BlueMask;
899	break;
900	}
901	break;
902	}
903
904	case SVGA_REG_BYTES_PER_LINE:
905	{
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
907	if ( pThis->svga.fEnabled
908	&& pThis->svga.cbScanline)
909	{
910	*pu32 = pThis->svga.cbScanline;
911	}
912	else
913	{
914	#ifndef IN_RING3
915	rc = VINF_IOM_R3_IOPORT_READ;
916	#else
917	*pu32 = pThis->pDrv->cbScanline;
918	#endif
919	}
920	break;
921	}
922
923	case SVGA_REG_VRAM_SIZE: /* VRAM size */
924	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
925	*pu32 = pThis->vram_size;
926	break;
927
928	case SVGA_REG_FB_START: /* Frame buffer physical address. */
929	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
930	Assert(pThis->GCPhysVRAM <= 0xffffffff);
931	*pu32 = pThis->GCPhysVRAM;
932	break;
933
934	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
935	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
936	/* Always zero in our case. */
937	*pu32 = 0;
938	break;
939
940	case SVGA_REG_FB_SIZE: /* Frame buffer size */
941	{
942	#ifndef IN_RING3
943	rc = VINF_IOM_R3_IOPORT_READ;
944	#else
945	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
946
947	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
948	if ( pThis->svga.fEnabled
949	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
950	{
951	/* Hardware enabled; return real framebuffer size .*/
952	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
953	}
954	else
955	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
956
957	pu32 = RT_MIN(pThis->vram_size, pu32);
958	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
959	#endif
960	break;
961	}
962
963	case SVGA_REG_CAPABILITIES:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
965	*pu32 = pThis->svga.u32RegCaps;
966	break;
967
968	case SVGA_REG_MEM_START: /* FIFO start */
969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
970	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
971	*pu32 = pThis->svga.GCPhysFIFO;
972	break;
973
974	case SVGA_REG_MEM_SIZE: /* FIFO size */
975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
976	*pu32 = pThis->svga.cbFIFO;
977	break;
978
979	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
980	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
981	*pu32 = pThis->svga.fConfigured;
982	break;
983
984	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
985	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
986	*pu32 = 0;
987	break;
988
989	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
990	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
991	if (pThis->svga.fBusy)
992	{
993	#ifndef IN_RING3
994	/* Go to ring-3 and halt the CPU. */
995	rc = VINF_IOM_R3_IOPORT_READ;
996	break;
997	#else
998	# if defined(VMSVGA_USE_EMT_HALT_CODE)
999	/* The guest is basically doing a HLT via the device here, but with
1000	a special wake up condition on FIFO completion. */
1001	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1002	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1003	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1004	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1005	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1006	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1007	if (pThis->svga.fBusy)
1008	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1009	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1010	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1011	# else
1012
1013	/* Delay the EMT a bit so the FIFO and others can get some work done.
1014	This used to be a crude 50 ms sleep. The current code tries to be
1015	more efficient, but the consept is still very crude. */
1016	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1017	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1018	RTThreadYield();
1019	if (pThis->svga.fBusy)
1020	{
1021	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1022
1023	if (pThis->svga.fBusy && cRefs == 1)
1024	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1025	if (pThis->svga.fBusy)
1026	{
1027	/** @todo If this code is going to stay, we need to call into the halt/wait
1028	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1029	* suffer when the guest is polling on a busy FIFO. */
1030	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1031	if (cNsMaxWait >= RT_NS_100US)
1032	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1033	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1034	RT_MIN(cNsMaxWait, RT_NS_10MS));
1035	}
1036
1037	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1038	}
1039	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1040	# endif
1041	*pu32 = pThis->svga.fBusy != 0;
1042	#endif
1043	}
1044	else
1045	*pu32 = false;
1046	break;
1047
1048	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1050	*pu32 = pThis->svga.u32GuestId;
1051	break;
1052
1053	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1055	*pu32 = pThis->svga.cScratchRegion;
1056	break;
1057
1058	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1060	*pu32 = SVGA_FIFO_NUM_REGS;
1061	break;
1062
1063	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1065	*pu32 = pThis->svga.u32PitchLock;
1066	break;
1067
1068	case SVGA_REG_IRQMASK: /* Interrupt mask */
1069	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1070	*pu32 = pThis->svga.u32IrqMask;
1071	break;
1072
1073	/* See "Guest memory regions" below. */
1074	case SVGA_REG_GMR_ID:
1075	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1076	*pu32 = pThis->svga.u32CurrentGMRId;
1077	break;
1078
1079	case SVGA_REG_GMR_DESCRIPTOR:
1080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1081	/* Write only */
1082	*pu32 = 0;
1083	break;
1084
1085	case SVGA_REG_GMR_MAX_IDS:
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1087	*pu32 = pThis->svga.cGMR;
1088	break;
1089
1090	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1092	*pu32 = VMSVGA_MAX_GMR_PAGES;
1093	break;
1094
1095	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1096	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1097	*pu32 = pThis->svga.fTraces;
1098	break;
1099
1100	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1101	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1102	*pu32 = VMSVGA_MAX_GMR_PAGES;
1103	break;
1104
1105	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1107	*pu32 = VMSVGA_SURFACE_SIZE;
1108	break;
1109
1110	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1112	break;
1113
1114	/* Mouse cursor support. */
1115	case SVGA_REG_CURSOR_ID:
1116	case SVGA_REG_CURSOR_X:
1117	case SVGA_REG_CURSOR_Y:
1118	case SVGA_REG_CURSOR_ON:
1119	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1120	break;
1121
1122	/* Legacy multi-monitor support */
1123	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1125	*pu32 = 1;
1126	break;
1127
1128	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1130	*pu32 = 0;
1131	break;
1132
1133	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1135	*pu32 = 0;
1136	break;
1137
1138	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1139	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1140	*pu32 = 0;
1141	break;
1142
1143	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1145	*pu32 = 0;
1146	break;
1147
1148	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1150	*pu32 = pThis->svga.uWidth;
1151	break;
1152
1153	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1155	*pu32 = pThis->svga.uHeight;
1156	break;
1157
1158	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1160	pu32 = 1; / Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
1161	break;
1162
1163	default:
1164	{
1165	uint32_t offReg;
1166	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1167	{
1168	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1170	}
1171	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1172	{
1173	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1174	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1175	uint32_t u32 = pThis->last_palette[offReg / 3];
1176	switch (offReg % 3)
1177	{
1178	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1179	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1180	case 2: pu32 = u32 & 0xff; break; / blue */
1181	}
1182	}
1183	else
1184	{
1185	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1186	rc = VINF_IOM_R3_IOPORT_READ;
1187	#else
1188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1189	# ifndef DEBUG_sunlover
1190	AssertMsgFailed(("reg=%#x\n", idxReg));
1191	# endif
1192	#endif
1193	}
1194	break;
1195	}
1196	}
1197	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1198	return rc;
1199	}
1200
1201	#ifdef IN_RING3
1202	/**
1203	* Apply the current resolution settings to change the video mode.
1204	*
1205	* @returns VBox status code.
1206	* @param pThis VMSVGA State
1207	*/
1208	int vmsvgaChangeMode(PVGASTATE pThis)
1209	{
1210	int rc;
1211
1212	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1213	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1214	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1215	{
1216	/* Mode change in progress; wait for all values to be set. */
1217	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1218	return VINF_SUCCESS;
1219	}
1220
1221	if ( pThis->svga.uWidth == 0
1222	\|\| pThis->svga.uHeight == 0
1223	\|\| pThis->svga.uBpp == 0)
1224	{
1225	/* Invalid mode change - BB does this early in the boot up. */
1226	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1227	return VINF_SUCCESS;
1228	}
1229
1230	if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1231	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1232	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1233	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1234	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1235	)
1236	{
1237	/* Nothing to do. */
1238	Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1239	return VINF_SUCCESS;
1240	}
1241
1242	Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1243	pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1244
1245	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1246	rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1247	AssertRC(rc);
1248	AssertReturn(rc == VINF_SUCCESS \|\| rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1249
1250	/* last stuff */
1251	pThis->last_bpp = pThis->svga.uBpp;
1252	pThis->last_scr_width = pThis->svga.uWidth;
1253	pThis->last_scr_height = pThis->svga.uHeight;
1254	pThis->last_width = pThis->svga.uWidth;
1255	pThis->last_height = pThis->svga.uHeight;
1256
1257	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1258
1259	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1260	if ( pThis->svga.viewport.cx == 0
1261	&& pThis->svga.viewport.cy == 0)
1262	{
1263	pThis->svga.viewport.cx = pThis->svga.uWidth;
1264	pThis->svga.viewport.xRight = pThis->svga.uWidth;
1265	pThis->svga.viewport.cy = pThis->svga.uHeight;
1266	pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1267	pThis->svga.viewport.yLowWC = 0;
1268	}
1269	return VINF_SUCCESS;
1270	}
1271	#endif /* IN_RING3 */
1272
1273	#if defined(IN_RING0) \|\| defined(IN_RING3)
1274	/**
1275	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1276	*
1277	* @param pThis The VMSVGA state.
1278	* @param fState The busy state.
1279	*/
1280	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1281	{
1282	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1283
1284	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1285	{
1286	/* Race / unfortunately scheduling. Highly unlikly. */
1287	uint32_t cLoops = 64;
1288	do
1289	{
1290	ASMNopPause();
1291	fState = (pThis->svga.fBusy != 0);
1292	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1293	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1294	}
1295	}
1296	#endif
1297
1298	/**
1299	* Write port register
1300	*
1301	* @returns VBox status code.
1302	* @param pThis VMSVGA State
1303	* @param u32 Value to write
1304	*/
1305	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1306	{
1307	#ifdef IN_RING3
1308	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1309	#endif
1310	int rc = VINF_SUCCESS;
1311
1312	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1313	uint32_t idxReg = pThis->svga.u32IndexReg;
1314	if ( idxReg >= SVGA_REG_CAPABILITIES
1315	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1316	{
1317	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1318	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1319	}
1320	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1321	switch (idxReg)
1322	{
1323	case SVGA_REG_ID:
1324	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1325	if ( u32 == SVGA_ID_0
1326	\|\| u32 == SVGA_ID_1
1327	\|\| u32 == SVGA_ID_2)
1328	pThis->svga.u32SVGAId = u32;
1329	else
1330	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1331	break;
1332
1333	case SVGA_REG_ENABLE:
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1335	if ( pThis->svga.fEnabled == u32
1336	&& pThis->last_bpp == (unsigned)pThis->svga.uBpp
1337	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1338	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1339	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1340	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1341	)
1342	/* Nothing to do. */
1343	break;
1344
1345	#ifdef IN_RING3
1346	if ( u32 == 1
1347	&& pThis->svga.fEnabled == false)
1348	{
1349	/* Make a backup copy of the first 512kb in order to save font data etc. */
1350	/** @todo should probably swap here, rather than copy + zero */
1351	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1352	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1353	}
1354
1355	pThis->svga.fEnabled = u32;
1356	if (pThis->svga.fEnabled)
1357	{
1358	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1359	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1360	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1361	{
1362	/* Keep the current mode. */
1363	pThis->svga.uWidth = pThis->pDrv->cx;
1364	pThis->svga.uHeight = pThis->pDrv->cy;
1365	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1366	}
1367
1368	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1369	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1370	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	rc = vmsvgaChangeMode(pThis);
1373	AssertRCReturn(rc, rc);
1374	}
1375	# ifdef LOG_ENABLED
1376	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1377	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1378	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1379	# endif
1380
1381	/* Disable or enable dirty page tracking according to the current fTraces value. */
1382	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1383	}
1384	else
1385	{
1386	/* Restore the text mode backup. */
1387	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1388
1389	/* pThis->svga.uHeight = -1;
1390	pThis->svga.uWidth = -1;
1391	pThis->svga.uBpp = -1;
1392	pThis->svga.cbScanline = 0; */
1393	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1394
1395	/* Enable dirty page tracking again when going into legacy mode. */
1396	vmsvgaSetTraces(pThis, true);
1397	}
1398	#else /* !IN_RING3 */
1399	rc = VINF_IOM_R3_IOPORT_WRITE;
1400	#endif /* !IN_RING3 */
1401	break;
1402
1403	case SVGA_REG_WIDTH:
1404	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1405	if (pThis->svga.uWidth != u32)
1406	{
1407	if (pThis->svga.fEnabled)
1408	{
1409	#ifdef IN_RING3
1410	pThis->svga.uWidth = u32;
1411	rc = vmsvgaChangeMode(pThis);
1412	AssertRCReturn(rc, rc);
1413	#else
1414	rc = VINF_IOM_R3_IOPORT_WRITE;
1415	#endif
1416	}
1417	else
1418	pThis->svga.uWidth = u32;
1419	}
1420	/* else: nop */
1421	break;
1422
1423	case SVGA_REG_HEIGHT:
1424	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1425	if (pThis->svga.uHeight != u32)
1426	{
1427	if (pThis->svga.fEnabled)
1428	{
1429	#ifdef IN_RING3
1430	pThis->svga.uHeight = u32;
1431	rc = vmsvgaChangeMode(pThis);
1432	AssertRCReturn(rc, rc);
1433	#else
1434	rc = VINF_IOM_R3_IOPORT_WRITE;
1435	#endif
1436	}
1437	else
1438	pThis->svga.uHeight = u32;
1439	}
1440	/* else: nop */
1441	break;
1442
1443	case SVGA_REG_DEPTH:
1444	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1445	/** @todo read-only?? */
1446	break;
1447
1448	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1449	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1450	if (pThis->svga.uBpp != u32)
1451	{
1452	if (pThis->svga.fEnabled)
1453	{
1454	#ifdef IN_RING3
1455	pThis->svga.uBpp = u32;
1456	rc = vmsvgaChangeMode(pThis);
1457	AssertRCReturn(rc, rc);
1458	#else
1459	rc = VINF_IOM_R3_IOPORT_WRITE;
1460	#endif
1461	}
1462	else
1463	pThis->svga.uBpp = u32;
1464	}
1465	/* else: nop */
1466	break;
1467
1468	case SVGA_REG_PSEUDOCOLOR:
1469	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1470	break;
1471
1472	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1473	#ifdef IN_RING3
1474	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1475	pThis->svga.fConfigured = u32;
1476	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1477	if (!pThis->svga.fConfigured)
1478	{
1479	pThis->svga.fTraces = true;
1480	}
1481	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1482	#else
1483	rc = VINF_IOM_R3_IOPORT_WRITE;
1484	#endif
1485	break;
1486
1487	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1489	if ( pThis->svga.fEnabled
1490	&& pThis->svga.fConfigured)
1491	{
1492	#if defined(IN_RING3) \|\| defined(IN_RING0)
1493	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1494	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1495	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1496	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1497
1498	/* Kick the FIFO thread to start processing commands again. */
1499	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1500	#else
1501	rc = VINF_IOM_R3_IOPORT_WRITE;
1502	#endif
1503	}
1504	/* else nothing to do. */
1505	else
1506	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1507
1508	break;
1509
1510	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1511	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1512	break;
1513
1514	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1515	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1516	pThis->svga.u32GuestId = u32;
1517	break;
1518
1519	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1520	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1521	pThis->svga.u32PitchLock = u32;
1522	break;
1523
1524	case SVGA_REG_IRQMASK: /* Interrupt mask */
1525	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1526	pThis->svga.u32IrqMask = u32;
1527
1528	/* Irq pending after the above change? */
1529	if (pThis->svga.u32IrqStatus & u32)
1530	{
1531	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1532	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1533	}
1534	else
1535	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1536	break;
1537
1538	/* Mouse cursor support */
1539	case SVGA_REG_CURSOR_ID:
1540	case SVGA_REG_CURSOR_X:
1541	case SVGA_REG_CURSOR_Y:
1542	case SVGA_REG_CURSOR_ON:
1543	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1544	break;
1545
1546	/* Legacy multi-monitor support */
1547	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1548	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1549	break;
1550	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1551	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1552	break;
1553	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1554	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1555	break;
1556	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1557	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1558	break;
1559	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1560	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1561	break;
1562	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1563	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1564	break;
1565	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1566	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1567	break;
1568	#ifdef VBOX_WITH_VMSVGA3D
1569	/* See "Guest memory regions" below. */
1570	case SVGA_REG_GMR_ID:
1571	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1572	pThis->svga.u32CurrentGMRId = u32;
1573	break;
1574
1575	case SVGA_REG_GMR_DESCRIPTOR:
1576	# ifndef IN_RING3
1577	rc = VINF_IOM_R3_IOPORT_WRITE;
1578	break;
1579	# else /* IN_RING3 */
1580	{
1581	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1582
1583	/* Validate current GMR id. */
1584	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1585	AssertBreak(idGMR < pThis->svga.cGMR);
1586
1587	/* Free the old GMR if present. */
1588	vmsvgaGMRFree(pThis, idGMR);
1589
1590	/* Just undefine the GMR? */
1591	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1592	if (GCPhys == 0)
1593	{
1594	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1595	break;
1596	}
1597
1598
1599	/* Never cross a page boundary automatically. */
1600	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1601	uint32_t cPagesTotal = 0;
1602	uint32_t iDesc = 0;
1603	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1604	uint32_t cLoops = 0;
1605	RTGCPHYS GCPhysBase = GCPhys;
1606	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1607	{
1608	/* Read descriptor. */
1609	SVGAGuestMemDescriptor desc;
1610	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1611	AssertRCBreak(rc);
1612
1613	if (desc.numPages != 0)
1614	{
1615	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1616	cPagesTotal += desc.numPages;
1617	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1618
1619	if ((iDesc & 15) == 0)
1620	{
1621	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1622	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1623	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1624	}
1625
1626	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1627	paDescs[iDesc++].numPages = desc.numPages;
1628
1629	/* Continue with the next descriptor. */
1630	GCPhys += sizeof(desc);
1631	}
1632	else if (desc.ppn == 0)
1633	break; /* terminator */
1634	else /* Pointer to the next physical page of descriptors. */
1635	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1636
1637	cLoops++;
1638	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1639	}
1640
1641	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1642	if (RT_SUCCESS(rc))
1643	{
1644	/* Commit the GMR. */
1645	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1646	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1647	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1648	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1649	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1650	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1651	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1652	}
1653	else
1654	{
1655	RTMemFree(paDescs);
1656	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1657	}
1658	break;
1659	}
1660	# endif /* IN_RING3 */
1661	#endif // VBOX_WITH_VMSVGA3D
1662
1663	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1664	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1665	if (pThis->svga.fTraces == u32)
1666	break; /* nothing to do */
1667
1668	#ifdef IN_RING3
1669	vmsvgaSetTraces(pThis, !!u32);
1670	#else
1671	rc = VINF_IOM_R3_IOPORT_WRITE;
1672	#endif
1673	break;
1674
1675	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1676	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1677	break;
1678
1679	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1680	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1681	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1682	break;
1683
1684	case SVGA_REG_FB_START:
1685	case SVGA_REG_MEM_START:
1686	case SVGA_REG_HOST_BITS_PER_PIXEL:
1687	case SVGA_REG_MAX_WIDTH:
1688	case SVGA_REG_MAX_HEIGHT:
1689	case SVGA_REG_VRAM_SIZE:
1690	case SVGA_REG_FB_SIZE:
1691	case SVGA_REG_CAPABILITIES:
1692	case SVGA_REG_MEM_SIZE:
1693	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1694	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1695	case SVGA_REG_BYTES_PER_LINE:
1696	case SVGA_REG_FB_OFFSET:
1697	case SVGA_REG_RED_MASK:
1698	case SVGA_REG_GREEN_MASK:
1699	case SVGA_REG_BLUE_MASK:
1700	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1701	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1702	case SVGA_REG_GMR_MAX_IDS:
1703	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1704	/* Read only - ignore. */
1705	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1706	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1707	break;
1708
1709	default:
1710	{
1711	uint32_t offReg;
1712	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1713	{
1714	pThis->svga.au32ScratchRegion[offReg] = u32;
1715	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1716	}
1717	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1718	{
1719	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1720	Btw, see rgb_to_pixel32. */
1721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1722	u32 &= 0xff;
1723	uint32_t uRgb = pThis->last_palette[offReg / 3];
1724	switch (offReg % 3)
1725	{
1726	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1727	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1728	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1729	}
1730	pThis->last_palette[offReg / 3] = uRgb;
1731	}
1732	else
1733	{
1734	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1735	rc = VINF_IOM_R3_IOPORT_WRITE;
1736	#else
1737	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1738	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1739	#endif
1740	}
1741	break;
1742	}
1743	}
1744	return rc;
1745	}
1746
1747	/**
1748	* Port I/O Handler for IN operations.
1749	*
1750	* @returns VINF_SUCCESS or VINF_EM_*.
1751	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1752	*
1753	* @param pDevIns The device instance.
1754	* @param pvUser User argument.
1755	* @param uPort Port number used for the IN operation.
1756	* @param pu32 Where to store the result. This is always a 32-bit
1757	* variable regardless of what @a cb might say.
1758	* @param cb Number of bytes read.
1759	*/
1760	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1761	{
1762	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1763	RT_NOREF_PV(pvUser);
1764
1765	/* Ignore non-dword accesses. */
1766	if (cb != 4)
1767	{
1768	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1769	*pu32 = UINT32_MAX;
1770	return VINF_SUCCESS;
1771	}
1772
1773	switch (uPort - pThis->svga.BasePort)
1774	{
1775	case SVGA_INDEX_PORT:
1776	*pu32 = pThis->svga.u32IndexReg;
1777	break;
1778
1779	case SVGA_VALUE_PORT:
1780	return vmsvgaReadPort(pThis, pu32);
1781
1782	case SVGA_BIOS_PORT:
1783	Log(("Ignoring BIOS port read\n"));
1784	*pu32 = 0;
1785	break;
1786
1787	case SVGA_IRQSTATUS_PORT:
1788	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1789	*pu32 = pThis->svga.u32IrqStatus;
1790	break;
1791	}
1792
1793	return VINF_SUCCESS;
1794	}
1795
1796	/**
1797	* Port I/O Handler for OUT operations.
1798	*
1799	* @returns VINF_SUCCESS or VINF_EM_*.
1800	*
1801	* @param pDevIns The device instance.
1802	* @param pvUser User argument.
1803	* @param uPort Port number used for the OUT operation.
1804	* @param u32 The value to output.
1805	* @param cb The value size in bytes.
1806	*/
1807	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1808	{
1809	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1810	RT_NOREF_PV(pvUser);
1811
1812	/* Ignore non-dword accesses. */
1813	if (cb != 4)
1814	{
1815	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1816	return VINF_SUCCESS;
1817	}
1818
1819	switch (uPort - pThis->svga.BasePort)
1820	{
1821	case SVGA_INDEX_PORT:
1822	pThis->svga.u32IndexReg = u32;
1823	break;
1824
1825	case SVGA_VALUE_PORT:
1826	return vmsvgaWritePort(pThis, u32);
1827
1828	case SVGA_BIOS_PORT:
1829	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1830	break;
1831
1832	case SVGA_IRQSTATUS_PORT:
1833	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1834	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1835	/* Clear the irq in case all events have been cleared. */
1836	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1837	{
1838	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1839	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1840	}
1841	break;
1842	}
1843	return VINF_SUCCESS;
1844	}
1845
1846	#ifdef DEBUG_FIFO_ACCESS
1847
1848	# ifdef IN_RING3
1849	/**
1850	* Handle LFB access.
1851	* @returns VBox status code.
1852	* @param pVM VM handle.
1853	* @param pThis VGA device instance data.
1854	* @param GCPhys The access physical address.
1855	* @param fWriteAccess Read or write access
1856	*/
1857	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1858	{
1859	RT_NOREF(pVM);
1860	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1861	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1862
1863	switch (GCPhysOffset >> 2)
1864	{
1865	case SVGA_FIFO_MIN:
1866	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1867	break;
1868	case SVGA_FIFO_MAX:
1869	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1870	break;
1871	case SVGA_FIFO_NEXT_CMD:
1872	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1873	break;
1874	case SVGA_FIFO_STOP:
1875	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1876	break;
1877	case SVGA_FIFO_CAPABILITIES:
1878	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1879	break;
1880	case SVGA_FIFO_FLAGS:
1881	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1882	break;
1883	case SVGA_FIFO_FENCE:
1884	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1885	break;
1886	case SVGA_FIFO_3D_HWVERSION:
1887	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1888	break;
1889	case SVGA_FIFO_PITCHLOCK:
1890	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1891	break;
1892	case SVGA_FIFO_CURSOR_ON:
1893	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1894	break;
1895	case SVGA_FIFO_CURSOR_X:
1896	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1897	break;
1898	case SVGA_FIFO_CURSOR_Y:
1899	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1900	break;
1901	case SVGA_FIFO_CURSOR_COUNT:
1902	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1903	break;
1904	case SVGA_FIFO_CURSOR_LAST_UPDATED:
1905	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1906	break;
1907	case SVGA_FIFO_RESERVED:
1908	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1909	break;
1910	case SVGA_FIFO_CURSOR_SCREEN_ID:
1911	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1912	break;
1913	case SVGA_FIFO_DEAD:
1914	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1915	break;
1916	case SVGA_FIFO_3D_HWVERSION_REVISED:
1917	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1918	break;
1919	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1920	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1921	break;
1922	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1923	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1924	break;
1925	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1926	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1927	break;
1928	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1929	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1930	break;
1931	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1932	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1933	break;
1934	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1935	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1936	break;
1937	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1938	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1939	break;
1940	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1941	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1942	break;
1943	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1944	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1945	break;
1946	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1947	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1948	break;
1949	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1950	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1951	break;
1952	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1953	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1954	break;
1955	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1956	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1957	break;
1958	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1959	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1960	break;
1961	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1962	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1963	break;
1964	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1965	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1966	break;
1967	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1968	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1969	break;
1970	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1971	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1972	break;
1973	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1974	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1975	break;
1976	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1977	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1978	break;
1979	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1980	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1981	break;
1982	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1983	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1984	break;
1985	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1986	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1987	break;
1988	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1989	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1990	break;
1991	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1992	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1993	break;
1994	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1995	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1996	break;
1997	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1998	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1999	break;
2000	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2001	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2002	break;
2003	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2004	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2005	break;
2006	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2007	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2008	break;
2009	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2010	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2011	break;
2012	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2013	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2014	break;
2015	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2016	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2017	break;
2018	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2019	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2020	break;
2021	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2022	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2023	break;
2024	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2025	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2026	break;
2027	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2028	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2029	break;
2030	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2031	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2032	break;
2033	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2034	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2035	break;
2036	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2037	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2038	break;
2039	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2040	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2041	break;
2042	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2043	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2044	break;
2045	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2046	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2047	break;
2048	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2049	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2050	break;
2051	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2052	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2053	break;
2054	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS_LAST:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_GUEST_3D_HWVERSION:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_FENCE_GOAL:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_BUSY:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	default:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	}
2184
2185	return VINF_EM_RAW_EMULATE_INSTR;
2186	}
2187
2188	/**
2189	* HC access handler for the FIFO.
2190	*
2191	* @returns VINF_SUCCESS if the handler have carried out the operation.
2192	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2193	* @param pVM VM Handle.
2194	* @param pVCpu The cross context CPU structure for the calling EMT.
2195	* @param GCPhys The physical address the guest is writing to.
2196	* @param pvPhys The HC mapping of that address.
2197	* @param pvBuf What the guest is reading/writing.
2198	* @param cbBuf How much it's reading/writing.
2199	* @param enmAccessType The access type.
2200	* @param enmOrigin Who is making the access.
2201	* @param pvUser User argument.
2202	*/
2203	static DECLCALLBACK(VBOXSTRICTRC)
2204	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2205	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2206	{
2207	PVGASTATE pThis = (PVGASTATE)pvUser;
2208	int rc;
2209	Assert(pThis);
2210	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2211	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2212
2213	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2214	if (RT_SUCCESS(rc))
2215	return VINF_PGM_HANDLER_DO_DEFAULT;
2216	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2217	return rc;
2218	}
2219
2220	# endif /* IN_RING3 */
2221	#endif /* DEBUG_FIFO_ACCESS */
2222
2223	#ifdef DEBUG_GMR_ACCESS
2224	# ifdef IN_RING3
2225
2226	/**
2227	* HC access handler for the FIFO.
2228	*
2229	* @returns VINF_SUCCESS if the handler have carried out the operation.
2230	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2231	* @param pVM VM Handle.
2232	* @param pVCpu The cross context CPU structure for the calling EMT.
2233	* @param GCPhys The physical address the guest is writing to.
2234	* @param pvPhys The HC mapping of that address.
2235	* @param pvBuf What the guest is reading/writing.
2236	* @param cbBuf How much it's reading/writing.
2237	* @param enmAccessType The access type.
2238	* @param enmOrigin Who is making the access.
2239	* @param pvUser User argument.
2240	*/
2241	static DECLCALLBACK(VBOXSTRICTRC)
2242	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2243	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2244	{
2245	PVGASTATE pThis = (PVGASTATE)pvUser;
2246	Assert(pThis);
2247	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2248	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2249
2250	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2251
2252	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2253	{
2254	PGMR pGMR = &pSVGAState->paGMR[i];
2255
2256	if (pGMR->numDescriptors)
2257	{
2258	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2259	{
2260	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2261	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2262	{
2263	/*
2264	* Turn off the write handler for this particular page and make it R/W.
2265	* Then return telling the caller to restart the guest instruction.
2266	*/
2267	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2268	AssertRC(rc);
2269	goto end;
2270	}
2271	}
2272	}
2273	}
2274	end:
2275	return VINF_PGM_HANDLER_DO_DEFAULT;
2276	}
2277
2278	/* Callback handler for VMR3ReqCallWaitU */
2279	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2280	{
2281	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2282	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2283	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2284	int rc;
2285
2286	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2287	{
2288	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2289	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2290	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2291	AssertRC(rc);
2292	}
2293	return VINF_SUCCESS;
2294	}
2295
2296	/* Callback handler for VMR3ReqCallWaitU */
2297	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2298	{
2299	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2300	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2301	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2302
2303	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2304	{
2305	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2306	AssertRC(rc);
2307	}
2308	return VINF_SUCCESS;
2309	}
2310
2311	/* Callback handler for VMR3ReqCallWaitU */
2312	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2313	{
2314	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2315
2316	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2317	{
2318	PGMR pGMR = &pSVGAState->paGMR[i];
2319
2320	if (pGMR->numDescriptors)
2321	{
2322	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2323	{
2324	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2325	AssertRC(rc);
2326	}
2327	}
2328	}
2329	return VINF_SUCCESS;
2330	}
2331
2332	# endif /* IN_RING3 */
2333	#endif /* DEBUG_GMR_ACCESS */
2334
2335	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2336
2337	#ifdef IN_RING3
2338
2339
2340	/**
2341	* Common worker for changing the pointer shape.
2342	*
2343	* @param pThis The VGA instance data.
2344	* @param pSVGAState The VMSVGA ring-3 instance data.
2345	* @param fAlpha Whether there is alpha or not.
2346	* @param xHot Hotspot x coordinate.
2347	* @param yHot Hotspot y coordinate.
2348	* @param cx Width.
2349	* @param cy Height.
2350	* @param pbData Heap copy of the cursor data. Consumed.
2351	* @param cbData The size of the data.
2352	*/
2353	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2354	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2355	{
2356	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2357	#ifdef LOG_ENABLED
2358	if (LogIs2Enabled())
2359	{
2360	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2361	if (!fAlpha)
2362	{
2363	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2364	for (uint32_t y = 0; y < cy; y++)
2365	{
2366	Log2(("%3u:", y));
2367	uint8_t const pbLine = &pbData[y cbAndLine];
2368	for (uint32_t x = 0; x < cx; x += 8)
2369	{
2370	uint8_t b = pbLine[x / 8];
2371	char szByte[12];
2372	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2373	szByte[1] = b & 0x40 ? '*' : ' ';
2374	szByte[2] = b & 0x20 ? '*' : ' ';
2375	szByte[3] = b & 0x10 ? '*' : ' ';
2376	szByte[4] = b & 0x08 ? '*' : ' ';
2377	szByte[5] = b & 0x04 ? '*' : ' ';
2378	szByte[6] = b & 0x02 ? '*' : ' ';
2379	szByte[7] = b & 0x01 ? '*' : ' ';
2380	szByte[8] = '\0';
2381	Log2(("%s", szByte));
2382	}
2383	Log2(("\n"));
2384	}
2385	}
2386
2387	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2388	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2389	for (uint32_t y = 0; y < cy; y++)
2390	{
2391	Log2(("%3u:", y));
2392	uint32_t const pu32Line = &pu32Xor[y cx];
2393	for (uint32_t x = 0; x < cx; x++)
2394	Log2((" %08x", pu32Line[x]));
2395	Log2(("\n"));
2396	}
2397	}
2398	#endif
2399
2400	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2401	AssertRC(rc);
2402
2403	if (pSVGAState->Cursor.fActive)
2404	RTMemFree(pSVGAState->Cursor.pData);
2405
2406	pSVGAState->Cursor.fActive = true;
2407	pSVGAState->Cursor.xHotspot = xHot;
2408	pSVGAState->Cursor.yHotspot = yHot;
2409	pSVGAState->Cursor.width = cx;
2410	pSVGAState->Cursor.height = cy;
2411	pSVGAState->Cursor.cbData = cbData;
2412	pSVGAState->Cursor.pData = pbData;
2413	}
2414
2415
2416	/**
2417	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2418	*
2419	* @param pThis The VGA instance data.
2420	* @param pSVGAState The VMSVGA ring-3 instance data.
2421	* @param pCursor The cursor.
2422	* @param pbSrcAndMask The AND mask.
2423	* @param cbSrcAndLine The scanline length of the AND mask.
2424	* @param pbSrcXorMask The XOR mask.
2425	* @param cbSrcXorLine The scanline length of the XOR mask.
2426	*/
2427	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2428	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2429	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2430	{
2431	uint32_t const cx = pCursor->width;
2432	uint32_t const cy = pCursor->height;
2433
2434	/*
2435	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2436	* The AND data uses 8-bit aligned scanlines.
2437	* The XOR data must be starting on a 32-bit boundrary.
2438	*/
2439	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2440	uint32_t cbDstAndMask = cbDstAndLine * cy;
2441	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2442	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2443
2444	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2445	AssertReturnVoid(pbCopy);
2446
2447	/* Convert the AND mask. */
2448	uint8_t *pbDst = pbCopy;
2449	uint8_t const *pbSrc = pbSrcAndMask;
2450	switch (pCursor->andMaskDepth)
2451	{
2452	case 1:
2453	if (cbSrcAndLine == cbDstAndLine)
2454	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2455	else
2456	{
2457	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2458	for (uint32_t y = 0; y < cy; y++)
2459	{
2460	memcpy(pbDst, pbSrc, cbDstAndLine);
2461	pbDst += cbDstAndLine;
2462	pbSrc += cbSrcAndLine;
2463	}
2464	}
2465	break;
2466	/* Should take the XOR mask into account for the multi-bit AND mask. */
2467	case 8:
2468	for (uint32_t y = 0; y < cy; y++)
2469	{
2470	for (uint32_t x = 0; x < cx; )
2471	{
2472	uint8_t bDst = 0;
2473	uint8_t fBit = 1;
2474	do
2475	{
2476	uintptr_t const idxPal = pbSrc[x] * 3;
2477	if ((( pThis->last_palette[idxPal]
2478	\| (pThis->last_palette[idxPal] >> 8)
2479	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2480	bDst \|= fBit;
2481	fBit <<= 1;
2482	x++;
2483	} while (x < cx && (x & 7));
2484	pbDst[(x - 1) / 8] = bDst;
2485	}
2486	pbDst += cbDstAndLine;
2487	pbSrc += cbSrcAndLine;
2488	}
2489	break;
2490	case 15:
2491	for (uint32_t y = 0; y < cy; y++)
2492	{
2493	for (uint32_t x = 0; x < cx; )
2494	{
2495	uint8_t bDst = 0;
2496	uint8_t fBit = 1;
2497	do
2498	{
2499	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2500	bDst \|= fBit;
2501	fBit <<= 1;
2502	x++;
2503	} while (x < cx && (x & 7));
2504	pbDst[(x - 1) / 8] = bDst;
2505	}
2506	pbDst += cbDstAndLine;
2507	pbSrc += cbSrcAndLine;
2508	}
2509	break;
2510	case 16:
2511	for (uint32_t y = 0; y < cy; y++)
2512	{
2513	for (uint32_t x = 0; x < cx; )
2514	{
2515	uint8_t bDst = 0;
2516	uint8_t fBit = 1;
2517	do
2518	{
2519	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2520	bDst \|= fBit;
2521	fBit <<= 1;
2522	x++;
2523	} while (x < cx && (x & 7));
2524	pbDst[(x - 1) / 8] = bDst;
2525	}
2526	pbDst += cbDstAndLine;
2527	pbSrc += cbSrcAndLine;
2528	}
2529	break;
2530	case 24:
2531	for (uint32_t y = 0; y < cy; y++)
2532	{
2533	for (uint32_t x = 0; x < cx; )
2534	{
2535	uint8_t bDst = 0;
2536	uint8_t fBit = 1;
2537	do
2538	{
2539	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2540	bDst \|= fBit;
2541	fBit <<= 1;
2542	x++;
2543	} while (x < cx && (x & 7));
2544	pbDst[(x - 1) / 8] = bDst;
2545	}
2546	pbDst += cbDstAndLine;
2547	pbSrc += cbSrcAndLine;
2548	}
2549	break;
2550	case 32:
2551	for (uint32_t y = 0; y < cy; y++)
2552	{
2553	for (uint32_t x = 0; x < cx; )
2554	{
2555	uint8_t bDst = 0;
2556	uint8_t fBit = 1;
2557	do
2558	{
2559	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2560	bDst \|= fBit;
2561	fBit <<= 1;
2562	x++;
2563	} while (x < cx && (x & 7));
2564	pbDst[(x - 1) / 8] = bDst;
2565	}
2566	pbDst += cbDstAndLine;
2567	pbSrc += cbSrcAndLine;
2568	}
2569	break;
2570	default:
2571	RTMemFree(pbCopy);
2572	AssertFailedReturnVoid();
2573	}
2574
2575	/* Convert the XOR mask. */
2576	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2577	pbSrc = pbSrcXorMask;
2578	switch (pCursor->xorMaskDepth)
2579	{
2580	case 1:
2581	for (uint32_t y = 0; y < cy; y++)
2582	{
2583	for (uint32_t x = 0; x < cx; )
2584	{
2585	/* most significant bit is the left most one. */
2586	uint8_t bSrc = pbSrc[x / 8];
2587	do
2588	{
2589	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2590	bSrc <<= 1;
2591	x++;
2592	} while ((x & 7) && x < cx);
2593	}
2594	pbSrc += cbSrcXorLine;
2595	}
2596	break;
2597	case 8:
2598	for (uint32_t y = 0; y < cy; y++)
2599	{
2600	for (uint32_t x = 0; x < cx; x++)
2601	{
2602	uint32_t u = pThis->last_palette[pbSrc[x]];
2603	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2604	}
2605	pbSrc += cbSrcXorLine;
2606	}
2607	break;
2608	case 15: /* Src: RGB-5-5-5 */
2609	for (uint32_t y = 0; y < cy; y++)
2610	{
2611	for (uint32_t x = 0; x < cx; x++)
2612	{
2613	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2614	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2615	((uValue >> 5) & 0x1f) << 3,
2616	((uValue >> 10) & 0x1f) << 3, 0);
2617	}
2618	pbSrc += cbSrcXorLine;
2619	}
2620	break;
2621	case 16: /* Src: RGB-5-6-5 */
2622	for (uint32_t y = 0; y < cy; y++)
2623	{
2624	for (uint32_t x = 0; x < cx; x++)
2625	{
2626	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2627	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2628	((uValue >> 5) & 0x3f) << 2,
2629	((uValue >> 11) & 0x1f) << 3, 0);
2630	}
2631	pbSrc += cbSrcXorLine;
2632	}
2633	break;
2634	case 24:
2635	for (uint32_t y = 0; y < cy; y++)
2636	{
2637	for (uint32_t x = 0; x < cx; x++)
2638	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2639	pbSrc += cbSrcXorLine;
2640	}
2641	break;
2642	case 32:
2643	for (uint32_t y = 0; y < cy; y++)
2644	{
2645	for (uint32_t x = 0; x < cx; x++)
2646	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2647	pbSrc += cbSrcXorLine;
2648	}
2649	break;
2650	default:
2651	RTMemFree(pbCopy);
2652	AssertFailedReturnVoid();
2653	}
2654
2655	/*
2656	* Pass it to the frontend/whatever.
2657	*/
2658	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2659	}
2660
2661
2662	/**
2663	* Worker for vmsvgaR3FifoThread that handles an external command.
2664	*
2665	* @param pThis VGA device instance data.
2666	*/
2667	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2668	{
2669	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2670	switch (pThis->svga.u8FIFOExtCommand)
2671	{
2672	case VMSVGA_FIFO_EXTCMD_RESET:
2673	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2674	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2675	# ifdef VBOX_WITH_VMSVGA3D
2676	if (pThis->svga.f3DEnabled)
2677	{
2678	/* The 3d subsystem must be reset from the fifo thread. */
2679	vmsvga3dReset(pThis);
2680	}
2681	# endif
2682	break;
2683
2684	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2685	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2686	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2687	# ifdef VBOX_WITH_VMSVGA3D
2688	if (pThis->svga.f3DEnabled)
2689	{
2690	/* The 3d subsystem must be shut down from the fifo thread. */
2691	vmsvga3dTerminate(pThis);
2692	}
2693	# endif
2694	break;
2695
2696	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2697	{
2698	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2699	# ifdef VBOX_WITH_VMSVGA3D
2700	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2701	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2702	vmsvga3dSaveExec(pThis, pSSM);
2703	# endif
2704	break;
2705	}
2706
2707	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2708	{
2709	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2710	# ifdef VBOX_WITH_VMSVGA3D
2711	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2712	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2713	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2714	# endif
2715	break;
2716	}
2717
2718	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2719	{
2720	# ifdef VBOX_WITH_VMSVGA3D
2721	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2722	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2723	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2724	# endif
2725	break;
2726	}
2727
2728
2729	default:
2730	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2731	break;
2732	}
2733
2734	/*
2735	* Signal the end of the external command.
2736	*/
2737	pThis->svga.pvFIFOExtCmdParam = NULL;
2738	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2739	ASMMemoryFence(); /* paranoia^2 */
2740	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2741	AssertLogRelRC(rc);
2742	}
2743
2744	/**
2745	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2746	* doing a job on the FIFO thread (even when it's officially suspended).
2747	*
2748	* @returns VBox status code (fully asserted).
2749	* @param pThis VGA device instance data.
2750	* @param uExtCmd The command to execute on the FIFO thread.
2751	* @param pvParam Pointer to command parameters.
2752	* @param cMsWait The time to wait for the command, given in
2753	* milliseconds.
2754	*/
2755	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2756	{
2757	Assert(cMsWait >= RT_MS_1SEC * 5);
2758	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2759	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2760
2761	int rc;
2762	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2763	PDMTHREADSTATE enmState = pThread->enmState;
2764	if (enmState == PDMTHREADSTATE_SUSPENDED)
2765	{
2766	/*
2767	* The thread is suspended, we have to temporarily wake it up so it can
2768	* perform the task.
2769	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2770	*/
2771	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2772	/* Post the request. */
2773	pThis->svga.fFifoExtCommandWakeup = true;
2774	pThis->svga.pvFIFOExtCmdParam = pvParam;
2775	pThis->svga.u8FIFOExtCommand = uExtCmd;
2776	ASMMemoryFence(); /* paranoia^3 */
2777
2778	/* Resume the thread. */
2779	rc = PDMR3ThreadResume(pThread);
2780	AssertLogRelRC(rc);
2781	if (RT_SUCCESS(rc))
2782	{
2783	/* Wait. Take care in case the semaphore was already posted (same as below). */
2784	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2785	if ( rc == VINF_SUCCESS
2786	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2787	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2788	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2789	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2790
2791	/* suspend the thread */
2792	pThis->svga.fFifoExtCommandWakeup = false;
2793	int rc2 = PDMR3ThreadSuspend(pThread);
2794	AssertLogRelRC(rc2);
2795	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2796	rc = rc2;
2797	}
2798	pThis->svga.fFifoExtCommandWakeup = false;
2799	pThis->svga.pvFIFOExtCmdParam = NULL;
2800	}
2801	else if (enmState == PDMTHREADSTATE_RUNNING)
2802	{
2803	/*
2804	* The thread is running, should only happen during reset and vmsvga3dsfc.
2805	* We ASSUME not racing code here, both wrt thread state and ext commands.
2806	*/
2807	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2808	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2809
2810	/* Post the request. */
2811	pThis->svga.pvFIFOExtCmdParam = pvParam;
2812	pThis->svga.u8FIFOExtCommand = uExtCmd;
2813	ASMMemoryFence(); /* paranoia^2 */
2814	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2815	AssertLogRelRC(rc);
2816
2817	/* Wait. Take care in case the semaphore was already posted (same as above). */
2818	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2819	if ( rc == VINF_SUCCESS
2820	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2821	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2822	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2823	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2824
2825	pThis->svga.pvFIFOExtCmdParam = NULL;
2826	}
2827	else
2828	{
2829	/*
2830	* Something is wrong with the thread!
2831	*/
2832	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2833	rc = VERR_INVALID_STATE;
2834	}
2835	return rc;
2836	}
2837
2838
2839	/**
2840	* Marks the FIFO non-busy, notifying any waiting EMTs.
2841	*
2842	* @param pThis The VGA state.
2843	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2844	* @param offFifoMin The start byte offset of the command FIFO.
2845	*/
2846	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2847	{
2848	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2849	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2850	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2851
2852	/* Wake up any waiting EMTs. */
2853	if (pSVGAState->cBusyDelayedEmts > 0)
2854	{
2855	#ifdef VMSVGA_USE_EMT_HALT_CODE
2856	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2857	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2858	if (idCpu != NIL_VMCPUID)
2859	{
2860	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2861	while (idCpu-- > 0)
2862	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2863	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2864	}
2865	#else
2866	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2867	AssertRC(rc2);
2868	#endif
2869	}
2870	}
2871
2872	/**
2873	* Reads (more) payload into the command buffer.
2874	*
2875	* @returns pbBounceBuf on success
2876	* @retval (void *)1 if the thread was requested to stop.
2877	* @retval NULL on FIFO error.
2878	*
2879	* @param cbPayloadReq The number of bytes of payload requested.
2880	* @param pFIFO The FIFO.
2881	* @param offCurrentCmd The FIFO byte offset of the current command.
2882	* @param offFifoMin The start byte offset of the command FIFO.
2883	* @param offFifoMax The end byte offset of the command FIFO.
2884	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2885	* always sufficient size.
2886	* @param pcbAlreadyRead How much payload we've already read into the bounce
2887	* buffer. (We will NEVER re-read anything.)
2888	* @param pThread The calling PDM thread handle.
2889	* @param pThis The VGA state.
2890	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2891	* statistics collection.
2892	*/
2893	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile pFIFO,
2894	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2895	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
2896	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2897	{
2898	Assert(pbBounceBuf);
2899	Assert(pcbAlreadyRead);
2900	Assert(offFifoMin < offFifoMax);
2901	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2902	Assert(offFifoMax <= pThis->svga.cbFIFO);
2903
2904	/*
2905	* Check if the requested payload size has already been satisfied .
2906	* .
2907	* When called to read more, the caller is responsible for making sure the .
2908	* new command size (cbRequsted) never is smaller than what has already .
2909	* been read.
2910	*/
2911	uint32_t cbAlreadyRead = *pcbAlreadyRead;
2912	if (cbPayloadReq <= cbAlreadyRead)
2913	{
2914	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2915	return pbBounceBuf;
2916	}
2917
2918	/*
2919	* Commands bigger than the fifo buffer are invalid.
2920	*/
2921	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2922	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2923	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2924	NULL);
2925
2926	/*
2927	* Move offCurrentCmd past the command dword.
2928	*/
2929	offCurrentCmd += sizeof(uint32_t);
2930	if (offCurrentCmd >= offFifoMax)
2931	offCurrentCmd = offFifoMin;
2932
2933	/*
2934	* Do we have sufficient payload data available already?
2935	*/
2936	uint32_t cbAfter, cbBefore;
2937	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2938	if (offNextCmd > offCurrentCmd)
2939	{
2940	if (RT_LIKELY(offNextCmd < offFifoMax))
2941	cbAfter = offNextCmd - offCurrentCmd;
2942	else
2943	{
2944	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2945	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2946	offNextCmd, offFifoMin, offFifoMax));
2947	cbAfter = offFifoMax - offCurrentCmd;
2948	}
2949	cbBefore = 0;
2950	}
2951	else
2952	{
2953	cbAfter = offFifoMax - offCurrentCmd;
2954	if (offNextCmd >= offFifoMin)
2955	cbBefore = offNextCmd - offFifoMin;
2956	else
2957	{
2958	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2959	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2960	offNextCmd, offFifoMin, offFifoMax));
2961	cbBefore = 0;
2962	}
2963	}
2964	if (cbAfter + cbBefore < cbPayloadReq)
2965	{
2966	/*
2967	* Insufficient, must wait for it to arrive.
2968	*/
2969	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2970	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2971	for (uint32_t i = 0;; i++)
2972	{
2973	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2974	{
2975	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2976	return (void *)(uintptr_t)1;
2977	}
2978	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2979	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2980
2981	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2982
2983	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2984	if (offNextCmd > offCurrentCmd)
2985	{
2986	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2987	cbBefore = 0;
2988	}
2989	else
2990	{
2991	cbAfter = offFifoMax - offCurrentCmd;
2992	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2993	}
2994
2995	if (cbAfter + cbBefore >= cbPayloadReq)
2996	break;
2997	}
2998	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2999	}
3000
3001	/*
3002	* Copy out the memory and update what pcbAlreadyRead points to.
3003	*/
3004	if (cbAfter >= cbPayloadReq)
3005	memcpy(pbBounceBuf + cbAlreadyRead,
3006	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3007	cbPayloadReq - cbAlreadyRead);
3008	else
3009	{
3010	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3011	if (cbAlreadyRead < cbAfter)
3012	{
3013	memcpy(pbBounceBuf + cbAlreadyRead,
3014	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3015	cbAfter - cbAlreadyRead);
3016	cbAlreadyRead = cbAfter;
3017	}
3018	memcpy(pbBounceBuf + cbAlreadyRead,
3019	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3020	cbPayloadReq - cbAlreadyRead);
3021	}
3022	*pcbAlreadyRead = cbPayloadReq;
3023	return pbBounceBuf;
3024	}
3025
3026	/* The async FIFO handling thread. */
3027	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3028	{
3029	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3030	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3031	int rc;
3032
3033	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3034	return VINF_SUCCESS;
3035
3036	/*
3037	* Special mode where we only execute an external command and the go back
3038	* to being suspended. Currently, all ext cmds ends up here, with the reset
3039	* one also being eligble for runtime execution further down as well.
3040	*/
3041	if (pThis->svga.fFifoExtCommandWakeup)
3042	{
3043	vmsvgaR3FifoHandleExtCmd(pThis);
3044	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3045	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3046	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3047	else
3048	vmsvgaR3FifoHandleExtCmd(pThis);
3049	return VINF_SUCCESS;
3050	}
3051
3052
3053	/*
3054	* Signal the semaphore to make sure we don't wait for 250ms after a
3055	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3056	*/
3057	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3058
3059	/*
3060	* Allocate a bounce buffer for command we get from the FIFO.
3061	* (All code must return via the end of the function to free this buffer.)
3062	*/
3063	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3064	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3065
3066	/*
3067	* Polling/sleep interval config.
3068	*
3069	* We wait for an a short interval if the guest has recently given us work
3070	* to do, but the interval increases the longer we're kept idle. With the
3071	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3072	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3073	* 16 seconds.
3074	*/
3075	RTMSINTERVAL const cMsMinSleep = 16;
3076	RTMSINTERVAL const cMsIncSleep = 2;
3077	RTMSINTERVAL const cMsMaxSleep = 250;
3078	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3079
3080	/*
3081	* The FIFO loop.
3082	*/
3083	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3084	bool fBadOrDisabledFifo = false;
3085	uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
3086	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3087	{
3088	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3089	/*
3090	* Should service the run loop every so often.
3091	*/
3092	if (pThis->svga.f3DEnabled)
3093	vmsvga3dCocoaServiceRunLoop();
3094	# endif
3095
3096	/*
3097	* Unless there's already work pending, go to sleep for a short while.
3098	* (See polling/sleep interval config above.)
3099	*/
3100	if ( fBadOrDisabledFifo
3101	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3102	{
3103	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3104	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3105	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3106	{
3107	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3108	break;
3109	}
3110	}
3111	else
3112	rc = VINF_SUCCESS;
3113	fBadOrDisabledFifo = false;
3114	if (rc == VERR_TIMEOUT)
3115	{
3116	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3117	{
3118	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3119	continue;
3120	}
3121	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3122
3123	Log(("vmsvgaFIFOLoop: timeout\n"));
3124	}
3125	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3126	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3127	cMsSleep = cMsMinSleep;
3128
3129	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3130	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3131	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3132
3133	/*
3134	* Handle external commands (currently only reset).
3135	*/
3136	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3137	{
3138	vmsvgaR3FifoHandleExtCmd(pThis);
3139	continue;
3140	}
3141
3142	/*
3143	* The device must be enabled and configured.
3144	*/
3145	if ( !pThis->svga.fEnabled
3146	\|\| !pThis->svga.fConfigured)
3147	{
3148	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3149	fBadOrDisabledFifo = true;
3150	continue;
3151	}
3152
3153	/*
3154	* Get and check the min/max values. We ASSUME that they will remain
3155	* unchanged while we process requests. A further ASSUMPTION is that
3156	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3157	* we don't read it back while in the loop.
3158	*/
3159	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3160	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3161	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3162	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3163	\|\| offFifoMax <= offFifoMin
3164	\|\| offFifoMax > pThis->svga.cbFIFO
3165	\|\| (offFifoMax & 3) != 0
3166	\|\| (offFifoMin & 3) != 0
3167	\|\| offCurrentCmd < offFifoMin
3168	\|\| offCurrentCmd > offFifoMax))
3169	{
3170	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3171	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3172	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3173	fBadOrDisabledFifo = true;
3174	continue;
3175	}
3176	if (RT_UNLIKELY(offCurrentCmd & 3))
3177	{
3178	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3179	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3180	offCurrentCmd = ~UINT32_C(3);
3181	}
3182
3183	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3184	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3185	*
3186	* Will break out of the switch on failure.
3187	* Will restart and quit the loop if the thread was requested to stop.
3188	*
3189	* @param a_PtrVar Request variable pointer.
3190	* @param a_Type Request typedef (not pointer) for casting.
3191	* @param a_cbPayloadReq How much payload to fetch.
3192	* @remarks Accesses a bunch of variables in the current scope!
3193	*/
3194	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3195	if (1) { \
3196	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3197	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3198	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3199	} else do {} while (0)
3200	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3201	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3202	* buffer after figuring out the actual command size.
3203	*
3204	* Will break out of the switch on failure.
3205	*
3206	* @param a_PtrVar Request variable pointer.
3207	* @param a_Type Request typedef (not pointer) for casting.
3208	* @param a_cbPayloadReq How much payload to fetch.
3209	* @remarks Accesses a bunch of variables in the current scope!
3210	*/
3211	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3212	if (1) { \
3213	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3214	} else do {} while (0)
3215
3216	/*
3217	* Mark the FIFO as busy.
3218	*/
3219	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3220	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3221	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3222
3223	/*
3224	* Execute all queued FIFO commands.
3225	* Quit if pending external command or changes in the thread state.
3226	*/
3227	bool fDone = false;
3228	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3229	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3230	{
3231	uint32_t cbPayload = 0;
3232	uint32_t u32IrqStatus = 0;
3233
3234	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3235
3236	/* First check any pending actions. */
3237	if ( ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT)
3238	&& pThis->svga.p3dState != NULL)
3239	# ifdef VBOX_WITH_VMSVGA3D
3240	vmsvga3dChangeMode(pThis);
3241	# else
3242	{/nothing/}
3243	# endif
3244	/* Check for pending external commands (reset). */
3245	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3246	break;
3247
3248	/*
3249	* Process the command.
3250	*/
3251	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3252	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3253	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3254	switch (enmCmdId)
3255	{
3256	case SVGA_CMD_INVALID_CMD:
3257	/* Nothing to do. */
3258	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3259	break;
3260
3261	case SVGA_CMD_FENCE:
3262	{
3263	SVGAFifoCmdFence *pCmdFence;
3264	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3265	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3266	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3267	{
3268	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3269	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3270
3271	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3272	{
3273	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3274	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3275	}
3276	else
3277	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3278	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3279	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3280	{
3281	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3282	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3283	}
3284	}
3285	else
3286	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3287	break;
3288	}
3289	case SVGA_CMD_UPDATE:
3290	case SVGA_CMD_UPDATE_VERBOSE:
3291	{
3292	SVGAFifoCmdUpdate *pUpdate;
3293	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3294	if (enmCmdId == SVGA_CMD_UPDATE)
3295	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3296	else
3297	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3298	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3299	vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3300	break;
3301	}
3302
3303	case SVGA_CMD_DEFINE_CURSOR:
3304	{
3305	/* Followed by bitmap data. */
3306	SVGAFifoCmdDefineCursor *pCursor;
3307	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3308	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3309
3310	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3311	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3312	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3313	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3314	AssertBreak(pCursor->andMaskDepth <= 32);
3315	AssertBreak(pCursor->xorMaskDepth <= 32);
3316
3317	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3318	uint32_t cbAndMask = cbAndLine * pCursor->height;
3319	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3320	uint32_t cbXorMask = cbXorLine * pCursor->height;
3321	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3322
3323	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3324	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3325	break;
3326	}
3327
3328	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3329	{
3330	/* Followed by bitmap data. */
3331	uint32_t cbCursorShape, cbAndMask;
3332	uint8_t *pCursorCopy;
3333	uint32_t cbCmd;
3334
3335	SVGAFifoCmdDefineAlphaCursor *pCursor;
3336	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3337	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3338
3339	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3340
3341	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3342	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3343
3344	/* Refetch the bitmap data as well. */
3345	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3346	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3347	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3348
3349	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3350	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3351	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3352	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3353
3354	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3355	AssertBreak(pCursorCopy);
3356
3357	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3358	memset(pCursorCopy, 0xff, cbAndMask);
3359	/* Colour data */
3360	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3361
3362	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3363	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3364	break;
3365	}
3366
3367	case SVGA_CMD_ESCAPE:
3368	{
3369	/* Followed by nsize bytes of data. */
3370	SVGAFifoCmdEscape *pEscape;
3371	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3372	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3373
3374	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3375	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3376	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3377	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3378
3379	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3380	{
3381	AssertBreak(pEscape->size >= sizeof(uint32_t));
3382	uint32_t cmd = (uint32_t )(pEscape + 1);
3383	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3384
3385	switch (cmd)
3386	{
3387	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3388	{
3389	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3390	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3391	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3392
3393	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3394	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3395	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3396
3397	RT_NOREF_PV(pVideoCmd);
3398	break;
3399
3400	}
3401
3402	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3403	{
3404	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3405	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3406	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3407	RT_NOREF_PV(pVideoCmd);
3408	break;
3409	}
3410	}
3411	}
3412	else
3413	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3414
3415	break;
3416	}
3417	# ifdef VBOX_WITH_VMSVGA3D
3418	case SVGA_CMD_DEFINE_GMR2:
3419	{
3420	SVGAFifoCmdDefineGMR2 *pCmd;
3421	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3422	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3423	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3424
3425	/* Validate current GMR id. */
3426	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3427	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3428
3429	if (!pCmd->numPages)
3430	{
3431	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3432	vmsvgaGMRFree(pThis, pCmd->gmrId);
3433	}
3434	else
3435	{
3436	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3437	if (pGMR->cMaxPages)
3438	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3439
3440	/* Not sure if we should always free the descriptor, but for simplicity
3441	we do so if the new size is smaller than the current. */
3442	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3443	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3444	vmsvgaGMRFree(pThis, pCmd->gmrId);
3445
3446	pGMR->cMaxPages = pCmd->numPages;
3447	/* The rest is done by the REMAP_GMR2 command. */
3448	}
3449	break;
3450	}
3451
3452	case SVGA_CMD_REMAP_GMR2:
3453	{
3454	/* Followed by page descriptors or guest ptr. */
3455	SVGAFifoCmdRemapGMR2 *pCmd;
3456	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3457	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3458
3459	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3460	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3461
3462	/* Calculate the size of what comes after next and fetch it. */
3463	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3464	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3465	cbCmd += sizeof(SVGAGuestPtr);
3466	else
3467	{
3468	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3469	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3470	{
3471	cbCmd += cbPageDesc;
3472	pCmd->numPages = 1;
3473	}
3474	else
3475	{
3476	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3477	cbCmd += cbPageDesc * pCmd->numPages;
3478	}
3479	}
3480	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3481
3482	/* Validate current GMR id and size. */
3483	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3484	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3485	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3486	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3487	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3488
3489	if (pCmd->numPages == 0)
3490	break;
3491
3492	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3493	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3494
3495	/*
3496	* We flatten the existing descriptors into a page array, overwrite the
3497	* pages specified in this command and then recompress the descriptor.
3498	*/
3499	/** @todo Optimize the GMR remap algorithm! */
3500
3501	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3502	uint64_t *paNewPage64 = NULL;
3503	if (pGMR->paDesc)
3504	{
3505	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3506
3507	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3508	AssertBreak(paNewPage64);
3509
3510	uint32_t idxPage = 0;
3511	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3512	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3513	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3514	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3515	}
3516
3517	/* Free the old GMR if present. */
3518	if (pGMR->paDesc)
3519	RTMemFree(pGMR->paDesc);
3520
3521	/* Allocate the maximum amount possible (everything non-continuous) */
3522	PVMSVGAGMRDESCRIPTOR paDescs;
3523	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3524	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3525
3526	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3527	{
3528	/** @todo */
3529	AssertFailed();
3530	pGMR->numDescriptors = 0;
3531	}
3532	else
3533	{
3534	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3535	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3536	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3537
3538	if (paNewPage64)
3539	{
3540	/* Overwrite the old page array with the new page values. */
3541	if (fGCPhys64)
3542	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3543	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3544	else
3545	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3546	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3547
3548	/* Use the updated page array instead of the command data. */
3549	fGCPhys64 = true;
3550	paPages64 = paNewPage64;
3551	pCmd->numPages = cNewTotalPages;
3552	}
3553
3554	/* The first page. */
3555	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3556	* applied to paNewPage64. */
3557	RTGCPHYS GCPhys;
3558	if (fGCPhys64)
3559	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3560	else
3561	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3562	paDescs[0].GCPhys = GCPhys;
3563	paDescs[0].numPages = 1;
3564
3565	/* Subsequent pages. */
3566	uint32_t iDescriptor = 0;
3567	for (uint32_t i = 1; i < pCmd->numPages; i++)
3568	{
3569	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3570	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3571	else
3572	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3573
3574	/* Continuous physical memory? */
3575	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3576	{
3577	Assert(paDescs[iDescriptor].numPages);
3578	paDescs[iDescriptor].numPages++;
3579	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3580	}
3581	else
3582	{
3583	iDescriptor++;
3584	paDescs[iDescriptor].GCPhys = GCPhys;
3585	paDescs[iDescriptor].numPages = 1;
3586	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3587	}
3588	}
3589
3590	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3591	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3592	pGMR->numDescriptors = iDescriptor + 1;
3593	}
3594
3595	if (paNewPage64)
3596	RTMemFree(paNewPage64);
3597
3598	# ifdef DEBUG_GMR_ACCESS
3599	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3600	# endif
3601	break;
3602	}
3603	# endif // VBOX_WITH_VMSVGA3D
3604	case SVGA_CMD_DEFINE_SCREEN:
3605	{
3606	/* Note! The size of this command is specified by the guest and depends on capabilities. */
3607	Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
3608	SVGAFifoCmdDefineScreen *pCmd;
3609	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3610	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
3611	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3612	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3613
3614	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
3615	if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
3616	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
3617	if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
3618	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
3619	if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
3620	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
3621	if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
3622	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
3623	if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
3624	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
3625
3626	/** @todo multi monitor support and screen object capabilities. */
3627	pThis->svga.uWidth = pCmd->screen.size.width;
3628	pThis->svga.uHeight = pCmd->screen.size.height;
3629	vmsvgaChangeMode(pThis);
3630	break;
3631	}
3632
3633	case SVGA_CMD_DESTROY_SCREEN:
3634	{
3635	SVGAFifoCmdDestroyScreen *pCmd;
3636	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3637	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3638
3639	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3640	break;
3641	}
3642	# ifdef VBOX_WITH_VMSVGA3D
3643	case SVGA_CMD_DEFINE_GMRFB:
3644	{
3645	SVGAFifoCmdDefineGMRFB *pCmd;
3646	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3647	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3648
3649	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3650	pSVGAState->GMRFB.ptr = pCmd->ptr;
3651	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3652	pSVGAState->GMRFB.format = pCmd->format;
3653	break;
3654	}
3655
3656	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3657	{
3658	uint32_t width, height;
3659	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3660	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3661	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3662
3663	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3664
3665	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3666	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3667	AssertBreak(pCmd->destScreenId == 0);
3668
3669	if (pCmd->destRect.left < 0)
3670	pCmd->destRect.left = 0;
3671	if (pCmd->destRect.top < 0)
3672	pCmd->destRect.top = 0;
3673	if (pCmd->destRect.right < 0)
3674	pCmd->destRect.right = 0;
3675	if (pCmd->destRect.bottom < 0)
3676	pCmd->destRect.bottom = 0;
3677
3678	width = pCmd->destRect.right - pCmd->destRect.left;
3679	height = pCmd->destRect.bottom - pCmd->destRect.top;
3680
3681	if ( width == 0
3682	\|\| height == 0)
3683	break; /* Nothing to do. */
3684
3685	/* Clip to screen dimensions. */
3686	if (width > pThis->svga.uWidth)
3687	width = pThis->svga.uWidth;
3688	if (height > pThis->svga.uHeight)
3689	height = pThis->svga.uHeight;
3690
3691	/* srcOrigin */
3692	AssertBreak(pSVGAState->GMRFB.bytesPerLine != 0);
3693	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel != 0);
3694
3695	const uint32_t cScanlines = pThis->vram_size / pSVGAState->GMRFB.bytesPerLine;
3696	AssertBreak(pCmd->srcOrigin.y < (int32_t)cScanlines);
3697
3698	AssertBreak(pCmd->srcOrigin.x < (int32_t)(pSVGAState->GMRFB.bytesPerLine / ((pSVGAState->GMRFB.format.s.bitsPerPixel + 7) / 8)));
3699
3700	unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3701	unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3702	unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3703
3704	AssertBreak(offsetDest < pThis->vram_size);
3705
3706	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3707	AssertRC(rc);
3708	vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3709	break;
3710	}
3711
3712	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3713	{
3714	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3715	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3716	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3717
3718	/* Note! This can fetch 3d render results as well!! */
3719	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3720	AssertFailed();
3721	break;
3722	}
3723	# endif // VBOX_WITH_VMSVGA3D
3724	case SVGA_CMD_ANNOTATION_FILL:
3725	{
3726	SVGAFifoCmdAnnotationFill *pCmd;
3727	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3728	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
3729
3730	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3731	pSVGAState->colorAnnotation = pCmd->color;
3732	break;
3733	}
3734
3735	case SVGA_CMD_ANNOTATION_COPY:
3736	{
3737	SVGAFifoCmdAnnotationCopy *pCmd;
3738	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3739	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
3740
3741	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3742	AssertFailed();
3743	break;
3744	}
3745
3746	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3747
3748	default:
3749	# ifdef VBOX_WITH_VMSVGA3D
3750	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
3751	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
3752	{
3753	/* All 3d commands start with a common header, which defines the size of the command. */
3754	SVGA3dCmdHeader *pHdr;
3755	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3756	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
3757	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3758	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3759
3760	/**
3761	* Check that the 3D command has at least a_cbMin of payload bytes after the
3762	* header. Will break out of the switch if it doesn't.
3763	*/
3764	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3765	AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3766	switch ((int)enmCmdId)
3767	{
3768	case SVGA_3D_CMD_SURFACE_DEFINE:
3769	{
3770	uint32_t cMipLevels;
3771	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
3772	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3773	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
3774
3775	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3776	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3777	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3778	# ifdef DEBUG_GMR_ACCESS
3779	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3780	# endif
3781	break;
3782	}
3783
3784	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3785	{
3786	uint32_t cMipLevels;
3787	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
3788	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3789	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
3790
3791	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3792	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3793	pCmd->multisampleCount, pCmd->autogenFilter,
3794	cMipLevels, (SVGA3dSize *)(pCmd + 1));
3795	break;
3796	}
3797
3798	case SVGA_3D_CMD_SURFACE_DESTROY:
3799	{
3800	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
3801	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3802	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
3803	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3804	break;
3805	}
3806
3807	case SVGA_3D_CMD_SURFACE_COPY:
3808	{
3809	uint32_t cCopyBoxes;
3810	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
3811	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3812	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
3813
3814	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3815	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3816	break;
3817	}
3818
3819	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3820	{
3821	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
3822	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3823	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
3824
3825	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3826	break;
3827	}
3828
3829	case SVGA_3D_CMD_SURFACE_DMA:
3830	{
3831	uint32_t cCopyBoxes;
3832	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
3833	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3834	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
3835
3836	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3837	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3838	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3839	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3840	break;
3841	}
3842
3843	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3844	{
3845	uint32_t cRects;
3846	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
3847	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3848	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
3849
3850	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3851	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3852	break;
3853	}
3854
3855	case SVGA_3D_CMD_CONTEXT_DEFINE:
3856	{
3857	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
3858	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3859	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
3860
3861	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3862	break;
3863	}
3864
3865	case SVGA_3D_CMD_CONTEXT_DESTROY:
3866	{
3867	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
3868	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3869	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
3870
3871	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3872	break;
3873	}
3874
3875	case SVGA_3D_CMD_SETTRANSFORM:
3876	{
3877	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
3878	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3879	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
3880
3881	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3882	break;
3883	}
3884
3885	case SVGA_3D_CMD_SETZRANGE:
3886	{
3887	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
3888	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3889	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
3890
3891	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3892	break;
3893	}
3894
3895	case SVGA_3D_CMD_SETRENDERSTATE:
3896	{
3897	uint32_t cRenderStates;
3898	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
3899	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3900	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
3901
3902	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3903	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3904	break;
3905	}
3906
3907	case SVGA_3D_CMD_SETRENDERTARGET:
3908	{
3909	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
3910	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3911	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
3912
3913	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3914	break;
3915	}
3916
3917	case SVGA_3D_CMD_SETTEXTURESTATE:
3918	{
3919	uint32_t cTextureStates;
3920	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
3921	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3922	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
3923
3924	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3925	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3926	break;
3927	}
3928
3929	case SVGA_3D_CMD_SETMATERIAL:
3930	{
3931	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
3932	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3933	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
3934
3935	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3936	break;
3937	}
3938
3939	case SVGA_3D_CMD_SETLIGHTDATA:
3940	{
3941	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
3942	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3943	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
3944
3945	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3946	break;
3947	}
3948
3949	case SVGA_3D_CMD_SETLIGHTENABLED:
3950	{
3951	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
3952	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3953	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
3954
3955	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3956	break;
3957	}
3958
3959	case SVGA_3D_CMD_SETVIEWPORT:
3960	{
3961	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
3962	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3963	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
3964
3965	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3966	break;
3967	}
3968
3969	case SVGA_3D_CMD_SETCLIPPLANE:
3970	{
3971	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
3972	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3973	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
3974
3975	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3976	break;
3977	}
3978
3979	case SVGA_3D_CMD_CLEAR:
3980	{
3981	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
3982	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3983	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
3984
3985	uint32_t cRects;
3986	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3987	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3988	break;
3989	}
3990
3991	case SVGA_3D_CMD_PRESENT:
3992	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3993	{
3994	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
3995	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3996	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
3997	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
3998	else
3999	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4000
4001	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4002
4003	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4004	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4005	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4006	break;
4007	}
4008
4009	case SVGA_3D_CMD_SHADER_DEFINE:
4010	{
4011	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4012	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4013	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4014
4015	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4016	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4017	break;
4018	}
4019
4020	case SVGA_3D_CMD_SHADER_DESTROY:
4021	{
4022	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4023	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4024	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4025
4026	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4027	break;
4028	}
4029
4030	case SVGA_3D_CMD_SET_SHADER:
4031	{
4032	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4033	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4034	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4035
4036	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4037	break;
4038	}
4039
4040	case SVGA_3D_CMD_SET_SHADER_CONST:
4041	{
4042	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4043	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4044	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4045
4046	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4047	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4048	break;
4049	}
4050
4051	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4052	{
4053	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4054	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4055	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4056
4057	uint32_t cVertexDivisor = (pHdr->size - sizeof(pCmd) - sizeof(SVGA3dVertexDecl) pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges) / sizeof(uint32_t);
4058	Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4059	Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4060	Assert(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4061
4062	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4063	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange ) (&pVertexDecl[pCmd->numVertexDecls]);
4064	SVGA3dVertexDivisor pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor )(&pNumRange[pCmd->numRanges]) : NULL;
4065
4066	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4067	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
4068	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4069	break;
4070	}
4071
4072	case SVGA_3D_CMD_SETSCISSORRECT:
4073	{
4074	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4075	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4076	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4077
4078	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4079	break;
4080	}
4081
4082	case SVGA_3D_CMD_BEGIN_QUERY:
4083	{
4084	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4085	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4086	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4087
4088	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4089	break;
4090	}
4091
4092	case SVGA_3D_CMD_END_QUERY:
4093	{
4094	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4095	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4096	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4097
4098	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4099	break;
4100	}
4101
4102	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4103	{
4104	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4105	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4106	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4107
4108	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4109	break;
4110	}
4111
4112	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4113	{
4114	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4115	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4116	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4117
4118	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4119	break;
4120	}
4121
4122	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4123	/* context id + surface id? */
4124	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4125	break;
4126	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4127	/* context id + surface id? */
4128	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4129	break;
4130
4131	default:
4132	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4133	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4134	break;
4135	}
4136	}
4137	else
4138	# endif // VBOX_WITH_VMSVGA3D
4139	{
4140	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4141	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4142	}
4143	}
4144
4145	/* Go to the next slot */
4146	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4147	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4148	if (offCurrentCmd >= offFifoMax)
4149	{
4150	offCurrentCmd -= offFifoMax - offFifoMin;
4151	Assert(offCurrentCmd >= offFifoMin);
4152	Assert(offCurrentCmd < offFifoMax);
4153	}
4154	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4155	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4156
4157	/*
4158	* Raise IRQ if required. Must enter the critical section here
4159	* before making final decisions here, otherwise cubebench and
4160	* others may end up waiting forever.
4161	*/
4162	if ( u32IrqStatus
4163	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4164	{
4165	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4166	AssertRC(rc2);
4167
4168	/* FIFO progress might trigger an interrupt. */
4169	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4170	{
4171	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4172	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4173	}
4174
4175	/* Unmasked IRQ pending? */
4176	if (pThis->svga.u32IrqMask & u32IrqStatus)
4177	{
4178	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4179	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4180	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4181	}
4182
4183	PDMCritSectLeave(&pThis->CritSect);
4184	}
4185	}
4186
4187	/* If really done, clear the busy flag. */
4188	if (fDone)
4189	{
4190	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4191	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4192	}
4193	}
4194
4195	/*
4196	* Free the bounce buffer. (There are no returns above!)
4197	*/
4198	RTMemFree(pbBounceBuf);
4199
4200	return VINF_SUCCESS;
4201	}
4202
4203	/**
4204	* Free the specified GMR
4205	*
4206	* @param pThis VGA device instance data.
4207	* @param idGMR GMR id
4208	*/
4209	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4210	{
4211	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4212
4213	/* Free the old descriptor if present. */
4214	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4215	if ( pGMR->numDescriptors
4216	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4217	{
4218	# ifdef DEBUG_GMR_ACCESS
4219	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4220	# endif
4221
4222	Assert(pGMR->paDesc);
4223	RTMemFree(pGMR->paDesc);
4224	pGMR->paDesc = NULL;
4225	pGMR->numDescriptors = 0;
4226	pGMR->cbTotal = 0;
4227	pGMR->cMaxPages = 0;
4228	}
4229	Assert(!pGMR->cMaxPages);
4230	Assert(!pGMR->cbTotal);
4231	}
4232
4233	/**
4234	* Copy from a GMR to host memory or vice versa
4235	*
4236	* @returns VBox status code.
4237	* @param pThis VGA device instance data.
4238	* @param enmTransferType Transfer type (read/write)
4239	* @param pbDst Host destination pointer
4240	* @param cbDestPitch Destination buffer pitch
4241	* @param src GMR description
4242	* @param offSrc Source buffer offset
4243	* @param cbSrcPitch Source buffer pitch
4244	* @param cbWidth Source width in bytes
4245	* @param cHeight Source height
4246	*/
4247	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
4248	SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
4249	{
4250	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4251	PGMR pGMR;
4252	int rc;
4253	PVMSVGAGMRDESCRIPTOR pDesc;
4254	unsigned offDesc = 0;
4255
4256	Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
4257	src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
4258	Assert(cbWidth && cHeight);
4259
4260	const uint32_t cbGmrScanline = cbSrcPitch > 0 ? cbSrcPitch : -cbSrcPitch;
4261
4262	uint32_t cbGmrTotal; /* The GMR size in bytes. */
4263	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4264	{
4265	pGMR = NULL;
4266	cbGmrTotal = pThis->vram_size;
4267	}
4268	else
4269	{
4270	AssertReturn(src.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4271	pGMR = &pSVGAState->paGMR[src.gmrId];
4272	cbGmrTotal = pGMR->cbTotal;
4273	}
4274
4275	/* Check GMR parameters */
4276	AssertMsgReturn(src.offset < cbGmrTotal,
4277	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4278	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4279	VERR_INVALID_PARAMETER);
4280	AssertMsgReturn(offSrc < cbGmrTotal - src.offset,
4281	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4282	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4283	VERR_INVALID_PARAMETER);
4284	AssertMsgReturn(cbGmrScanline != 0,
4285	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4286	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4287	VERR_INVALID_PARAMETER);
4288	AssertMsgReturn(cbWidth <= cbGmrScanline,
4289	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4290	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4291	VERR_INVALID_PARAMETER);
4292
4293	offSrc += src.offset; /* Actual offset in the GMR, where the first scanline will be copied. */
4294
4295	AssertMsgReturn(cbWidth <= cbGmrTotal - offSrc,
4296	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4297	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4298	VERR_INVALID_PARAMETER);
4299
4300	uint32_t cbGmrLeft = cbSrcPitch > 0 ? cbGmrTotal - offSrc : offSrc + cbWidth;
4301
4302	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4303	uint32_t cbLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4304	if (cbWidth <= cbLastScanline)
4305	++cGmrScanlines;
4306
4307	if (cHeight > cGmrScanlines)
4308	cHeight = cGmrScanlines;
4309
4310	AssertMsgReturn(cHeight > 0,
4311	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbGmrTotal=%#x\n",
4312	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, cbGmrTotal),
4313	VERR_INVALID_PARAMETER);
4314
4315	/* Shortcut for the framebuffer. */
4316	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4317	{
4318	uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
4319
4320	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4321	{
4322	/* switch src & dest */
4323	uint8_t *pTemp = pbDst;
4324	int32_t cbTempPitch = cbDestPitch;
4325
4326	pbDst = pSrc;
4327	pSrc = pTemp;
4328
4329	cbDestPitch = cbSrcPitch;
4330	cbSrcPitch = cbTempPitch;
4331	}
4332
4333	if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
4334	&& cbWidth == (uint32_t)cbDestPitch
4335	&& cbSrcPitch == cbDestPitch)
4336	{
4337	memcpy(pbDst, pSrc, cbWidth * cHeight);
4338	}
4339	else
4340	{
4341	for(uint32_t i = 0; i < cHeight; i++)
4342	{
4343	memcpy(pbDst, pSrc, cbWidth);
4344
4345	pbDst += cbDestPitch;
4346	pSrc += cbSrcPitch;
4347	}
4348	}
4349	return VINF_SUCCESS;
4350	}
4351
4352	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4353	pDesc = pGMR->paDesc;
4354
4355	for (uint32_t i = 0; i < cHeight; i++)
4356	{
4357	uint32_t cbCurrentWidth = cbWidth;
4358	uint32_t offCurrent = offSrc;
4359	uint8_t *pCurrentDest = pbDst;
4360
4361	/* Find the right descriptor */
4362	while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
4363	{
4364	offDesc += pDesc->numPages * PAGE_SIZE;
4365	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4366	pDesc++;
4367	}
4368
4369	while (cbCurrentWidth)
4370	{
4371	uint32_t cbToCopy;
4372
4373	if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
4374	{
4375	cbToCopy = cbCurrentWidth;
4376	}
4377	else
4378	{
4379	cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
4380	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4381	}
4382
4383	LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
4384
4385	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4386	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4387	else
4388	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4389	AssertRCBreak(rc);
4390
4391	cbCurrentWidth -= cbToCopy;
4392	offCurrent += cbToCopy;
4393	pCurrentDest += cbToCopy;
4394
4395	/* Go to the next descriptor if there's anything left. */
4396	if (cbCurrentWidth)
4397	{
4398	offDesc += pDesc->numPages * PAGE_SIZE;
4399	pDesc++;
4400	}
4401	}
4402
4403	offSrc += cbSrcPitch;
4404	pbDst += cbDestPitch;
4405	}
4406
4407	return VINF_SUCCESS;
4408	}
4409
4410	/**
4411	* Unblock the FIFO I/O thread so it can respond to a state change.
4412	*
4413	* @returns VBox status code.
4414	* @param pDevIns The VGA device instance.
4415	* @param pThread The send thread.
4416	*/
4417	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4418	{
4419	RT_NOREF(pDevIns);
4420	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4421	Log(("vmsvgaFIFOLoopWakeUp\n"));
4422	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4423	}
4424
4425	/**
4426	* Enables or disables dirty page tracking for the framebuffer
4427	*
4428	* @param pThis VGA device instance data.
4429	* @param fTraces Enable/disable traces
4430	*/
4431	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4432	{
4433	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4434	&& !fTraces)
4435	{
4436	//Assert(pThis->svga.fTraces);
4437	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4438	return;
4439	}
4440
4441	pThis->svga.fTraces = fTraces;
4442	if (pThis->svga.fTraces)
4443	{
4444	unsigned cbFrameBuffer = pThis->vram_size;
4445
4446	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4447	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4448	{
4449	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4450	Assert(pThis->svga.cbScanline);
4451	#endif
4452	/* Hardware enabled; return real framebuffer size .*/
4453	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4454	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4455	}
4456
4457	if (!pThis->svga.fVRAMTracking)
4458	{
4459	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4460	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4461	pThis->svga.fVRAMTracking = true;
4462	}
4463	}
4464	else
4465	{
4466	if (pThis->svga.fVRAMTracking)
4467	{
4468	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4469	vgaR3UnregisterVRAMHandler(pThis);
4470	pThis->svga.fVRAMTracking = false;
4471	}
4472	}
4473	}
4474
4475	/**
4476	* @callback_method_impl{FNPCIIOREGIONMAP}
4477	*/
4478	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4479	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4480	{
4481	int rc;
4482	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4483
4484	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4485	if (enmType == PCI_ADDRESS_SPACE_IO)
4486	{
4487	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4488	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4489	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4490	if (RT_FAILURE(rc))
4491	return rc;
4492	if (pThis->fR0Enabled)
4493	{
4494	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4495	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4496	if (RT_FAILURE(rc))
4497	return rc;
4498	}
4499	if (pThis->fGCEnabled)
4500	{
4501	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4502	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4503	if (RT_FAILURE(rc))
4504	return rc;
4505	}
4506
4507	pThis->svga.BasePort = GCPhysAddress;
4508	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
4509	}
4510	else
4511	{
4512	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
4513	if (GCPhysAddress != NIL_RTGCPHYS)
4514	{
4515	/*
4516	* Mapping the FIFO RAM.
4517	*/
4518	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
4519	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
4520	AssertRC(rc);
4521
4522	# ifdef DEBUG_FIFO_ACCESS
4523	if (RT_SUCCESS(rc))
4524	{
4525	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
4526	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
4527	"VMSVGA FIFO");
4528	AssertRC(rc);
4529	}
4530	# endif
4531	if (RT_SUCCESS(rc))
4532	{
4533	pThis->svga.GCPhysFIFO = GCPhysAddress;
4534	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
4535	}
4536	}
4537	else
4538	{
4539	Assert(pThis->svga.GCPhysFIFO);
4540	# ifdef DEBUG_FIFO_ACCESS
4541	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4542	AssertRC(rc);
4543	# endif
4544	pThis->svga.GCPhysFIFO = 0;
4545	}
4546
4547	}
4548	return VINF_SUCCESS;
4549	}
4550
4551	# ifdef VBOX_WITH_VMSVGA3D
4552
4553	/**
4554	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
4555	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
4556	*
4557	* @param pThis The VGA device instance data.
4558	* @param sid Either UINT32_MAX or the ID of a specific
4559	* surface. If UINT32_MAX is used, all surfaces
4560	* are processed.
4561	*/
4562	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
4563	{
4564	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
4565	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
4566	}
4567
4568
4569	/**
4570	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
4571	*/
4572	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4573	{
4574	/* There might be a specific context ID at the start of the
4575	arguments, if not show all contexts. */
4576	uint32_t cid = UINT32_MAX;
4577	if (pszArgs)
4578	pszArgs = RTStrStripL(pszArgs);
4579	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4580	cid = RTStrToUInt32(pszArgs);
4581
4582	/* Verbose or terse display, we default to verbose. */
4583	bool fVerbose = true;
4584	if (RTStrIStr(pszArgs, "terse"))
4585	fVerbose = false;
4586
4587	/* The size of the ascii art (x direction, y is 3/4 of x). */
4588	uint32_t cxAscii = 80;
4589	if (RTStrIStr(pszArgs, "gigantic"))
4590	cxAscii = 300;
4591	else if (RTStrIStr(pszArgs, "huge"))
4592	cxAscii = 180;
4593	else if (RTStrIStr(pszArgs, "big"))
4594	cxAscii = 132;
4595	else if (RTStrIStr(pszArgs, "normal"))
4596	cxAscii = 80;
4597	else if (RTStrIStr(pszArgs, "medium"))
4598	cxAscii = 64;
4599	else if (RTStrIStr(pszArgs, "small"))
4600	cxAscii = 48;
4601	else if (RTStrIStr(pszArgs, "tiny"))
4602	cxAscii = 24;
4603
4604	/* Y invert the image when producing the ASCII art. */
4605	bool fInvY = false;
4606	if (RTStrIStr(pszArgs, "invy"))
4607	fInvY = true;
4608
4609	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
4610	}
4611
4612
4613	/**
4614	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
4615	*/
4616	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4617	{
4618	/* There might be a specific surface ID at the start of the
4619	arguments, if not show all contexts. */
4620	uint32_t sid = UINT32_MAX;
4621	if (pszArgs)
4622	pszArgs = RTStrStripL(pszArgs);
4623	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4624	sid = RTStrToUInt32(pszArgs);
4625
4626	/* Verbose or terse display, we default to verbose. */
4627	bool fVerbose = true;
4628	if (RTStrIStr(pszArgs, "terse"))
4629	fVerbose = false;
4630
4631	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
4632	}
4633
4634	# endif /* VBOX_WITH_VMSVGA3D */
4635
4636	/**
4637	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
4638	*/
4639	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4640	{
4641	RT_NOREF(pszArgs);
4642	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4643	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4644
4645	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
4646	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
4647	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
4648	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
4649	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
4650	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
4651	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
4652	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
4653	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
4654	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
4655	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
4656	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
4657	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
4658	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
4659	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
4660	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
4661	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
4662	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
4663	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4664	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
4665	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
4666	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
4667
4668	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
4669	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
4670	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
4671	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
4672
4673	# ifdef VBOX_WITH_VMSVGA3D
4674	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
4675	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
4676	if (pThis->svga.u64HostWindowId != 0)
4677	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
4678	# endif
4679	}
4680
4681
4682	/**
4683	* @copydoc FNSSMDEVLOADEXEC
4684	*/
4685	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4686	{
4687	RT_NOREF(uPass);
4688	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4689	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4690	int rc;
4691
4692	/* Load our part of the VGAState */
4693	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4694	AssertRCReturn(rc, rc);
4695
4696	/* Load the VGA framebuffer. */
4697	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
4698	uint32_t cbVgaFramebuffer = _32K;
4699	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
4700	{
4701	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
4702	AssertRCReturn(rc, rc);
4703	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
4704	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
4705	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4706	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
4707	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
4708	}
4709	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
4710	AssertRCReturn(rc, rc);
4711	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
4712	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
4713	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
4714	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
4715
4716	/* Load the VMSVGA state. */
4717	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4718	AssertRCReturn(rc, rc);
4719
4720	/* Load the active cursor bitmaps. */
4721	if (pSVGAState->Cursor.fActive)
4722	{
4723	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
4724	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
4725
4726	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4727	AssertRCReturn(rc, rc);
4728	}
4729
4730	/* Load the GMR state. */
4731	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
4732	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
4733	{
4734	rc = SSMR3GetU32(pSSM, &cGMR);
4735	AssertRCReturn(rc, rc);
4736	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
4737	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
4738	("cGMR=%#x - expected 256B..1MB\n", cGMR),
4739	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4740	}
4741
4742	if (pThis->svga.cGMR != cGMR)
4743	{
4744	/* Reallocate GMR array. */
4745	Assert(pSVGAState->paGMR != NULL);
4746	RTMemFree(pSVGAState->paGMR);
4747	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
4748	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
4749	pThis->svga.cGMR = cGMR;
4750	}
4751
4752	for (uint32_t i = 0; i < cGMR; ++i)
4753	{
4754	PGMR pGMR = &pSVGAState->paGMR[i];
4755
4756	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4757	AssertRCReturn(rc, rc);
4758
4759	if (pGMR->numDescriptors)
4760	{
4761	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
4762	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
4763	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4764
4765	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
4766	{
4767	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4768	AssertRCReturn(rc, rc);
4769	}
4770	}
4771	}
4772
4773	# ifdef VBOX_WITH_VMSVGA3D
4774	if (pThis->svga.f3DEnabled)
4775	{
4776	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4777	vmsvga3dPowerOn(pThis);
4778	# endif
4779
4780	VMSVGA_STATE_LOAD LoadState;
4781	LoadState.pSSM = pSSM;
4782	LoadState.uVersion = uVersion;
4783	LoadState.uPass = uPass;
4784	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4785	AssertLogRelRCReturn(rc, rc);
4786	}
4787	# endif
4788
4789	return VINF_SUCCESS;
4790	}
4791
4792	/**
4793	* Reinit the video mode after the state has been loaded.
4794	*/
4795	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4796	{
4797	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4798	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4799
4800	pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4801	vmsvgaChangeMode(pThis);
4802
4803	/* Set the active cursor. */
4804	if (pSVGAState->Cursor.fActive)
4805	{
4806	int rc;
4807
4808	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4809	true,
4810	true,
4811	pSVGAState->Cursor.xHotspot,
4812	pSVGAState->Cursor.yHotspot,
4813	pSVGAState->Cursor.width,
4814	pSVGAState->Cursor.height,
4815	pSVGAState->Cursor.pData);
4816	AssertRC(rc);
4817	}
4818	return VINF_SUCCESS;
4819	}
4820
4821	/**
4822	* @copydoc FNSSMDEVSAVEEXEC
4823	*/
4824	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4825	{
4826	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4827	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4828	int rc;
4829
4830	/* Save our part of the VGAState */
4831	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4832	AssertLogRelRCReturn(rc, rc);
4833
4834	/* Save the framebuffer backup. */
4835	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
4836	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4837	AssertLogRelRCReturn(rc, rc);
4838
4839	/* Save the VMSVGA state. */
4840	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4841	AssertLogRelRCReturn(rc, rc);
4842
4843	/* Save the active cursor bitmaps. */
4844	if (pSVGAState->Cursor.fActive)
4845	{
4846	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4847	AssertLogRelRCReturn(rc, rc);
4848	}
4849
4850	/* Save the GMR state */
4851	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
4852	AssertLogRelRCReturn(rc, rc);
4853	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
4854	{
4855	PGMR pGMR = &pSVGAState->paGMR[i];
4856
4857	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4858	AssertLogRelRCReturn(rc, rc);
4859
4860	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
4861	{
4862	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4863	AssertLogRelRCReturn(rc, rc);
4864	}
4865	}
4866
4867	# ifdef VBOX_WITH_VMSVGA3D
4868	/*
4869	* Must save the 3d state in the FIFO thread.
4870	*/
4871	if (pThis->svga.f3DEnabled)
4872	{
4873	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4874	AssertLogRelRCReturn(rc, rc);
4875	}
4876	# endif
4877	return VINF_SUCCESS;
4878	}
4879
4880	/**
4881	* Resets the SVGA hardware state
4882	*
4883	* @returns VBox status code.
4884	* @param pDevIns The device instance.
4885	*/
4886	int vmsvgaReset(PPDMDEVINS pDevIns)
4887	{
4888	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4889	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4890
4891	/* Reset before init? */
4892	if (!pSVGAState)
4893	return VINF_SUCCESS;
4894
4895	Log(("vmsvgaReset\n"));
4896
4897
4898	/* Reset the FIFO processing as well as the 3d state (if we have one). */
4899	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4900	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
4901
4902	/* Reset other stuff. */
4903	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4904	RT_ZERO(pThis->svga.au32ScratchRegion);
4905	RT_ZERO(*pThis->svga.pSvgaR3State);
4906	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4907
4908	/* Register caps. */
4909	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
4910	# ifdef VBOX_WITH_VMSVGA3D
4911	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
4912	# endif
4913
4914	/* Setup FIFO capabilities. */
4915	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4916
4917	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4918	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4919
4920	/* VRAM tracking is enabled by default during bootup. */
4921	pThis->svga.fVRAMTracking = true;
4922	pThis->svga.fEnabled = false;
4923
4924	/* Invalidate current settings. */
4925	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4926	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4927	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4928	pThis->svga.cbScanline = 0;
4929
4930	return rc;
4931	}
4932
4933	/**
4934	* Cleans up the SVGA hardware state
4935	*
4936	* @returns VBox status code.
4937	* @param pDevIns The device instance.
4938	*/
4939	int vmsvgaDestruct(PPDMDEVINS pDevIns)
4940	{
4941	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4942
4943	/*
4944	* Ask the FIFO thread to terminate the 3d state and then terminate it.
4945	*/
4946	if (pThis->svga.pFIFOIOThread)
4947	{
4948	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
4949	AssertLogRelRC(rc);
4950
4951	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4952	AssertLogRelRC(rc);
4953	pThis->svga.pFIFOIOThread = NULL;
4954	}
4955
4956	/*
4957	* Destroy the special SVGA state.
4958	*/
4959	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4960	if (pSVGAState)
4961	{
4962	# ifndef VMSVGA_USE_EMT_HALT_CODE
4963	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4964	{
4965	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4966	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4967	}
4968	# endif
4969	if (pSVGAState->Cursor.fActive)
4970	RTMemFree(pSVGAState->Cursor.pData);
4971
4972	if (pSVGAState->paGMR)
4973	{
4974	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
4975	if (pSVGAState->paGMR[i].paDesc)
4976	RTMemFree(pSVGAState->paGMR[i].paDesc);
4977
4978	RTMemFree(pSVGAState->paGMR);
4979	pSVGAState->paGMR = NULL;
4980	}
4981
4982	RTMemFree(pSVGAState);
4983	pThis->svga.pSvgaR3State = NULL;
4984	}
4985
4986	/*
4987	* Free our resources residing in the VGA state.
4988	*/
4989	if (pThis->svga.pbVgaFrameBufferR3)
4990	{
4991	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
4992	pThis->svga.pbVgaFrameBufferR3 = NULL;
4993	}
4994	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4995	{
4996	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4997	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4998	}
4999	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5000	{
5001	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5002	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5003	}
5004
5005	return VINF_SUCCESS;
5006	}
5007
5008	/**
5009	* Initialize the SVGA hardware state
5010	*
5011	* @returns VBox status code.
5012	* @param pDevIns The device instance.
5013	*/
5014	int vmsvgaInit(PPDMDEVINS pDevIns)
5015	{
5016	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5017	PVMSVGAR3STATE pSVGAState;
5018	PVM pVM = PDMDevHlpGetVM(pDevIns);
5019	int rc;
5020
5021	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5022	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5023
5024	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
5025	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5026	pSVGAState = pThis->svga.pSvgaR3State;
5027
5028	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5029	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5030	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5031
5032	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5033	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5034	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5035
5036	/* Create event semaphore. */
5037	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5038
5039	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5040	if (RT_FAILURE(rc))
5041	{
5042	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5043	return rc;
5044	}
5045
5046	/* Create event semaphore. */
5047	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5048	if (RT_FAILURE(rc))
5049	{
5050	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5051	return rc;
5052	}
5053
5054	# ifndef VMSVGA_USE_EMT_HALT_CODE
5055	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5056	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5057	AssertRCReturn(rc, rc);
5058	# endif
5059
5060	/* Register caps. */
5061	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5062	# ifdef VBOX_WITH_VMSVGA3D
5063	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5064	# endif
5065
5066	/* Setup FIFO capabilities. */
5067	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5068
5069	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5070	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5071
5072	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5073	# ifdef VBOX_WITH_VMSVGA3D
5074	if (pThis->svga.f3DEnabled)
5075	{
5076	rc = vmsvga3dInit(pThis);
5077	if (RT_FAILURE(rc))
5078	{
5079	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5080	pThis->svga.f3DEnabled = false;
5081	}
5082	}
5083	# endif
5084	/* VRAM tracking is enabled by default during bootup. */
5085	pThis->svga.fVRAMTracking = true;
5086
5087	/* Invalidate current settings. */
5088	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5089	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5090	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5091	pThis->svga.cbScanline = 0;
5092
5093	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5094	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5095	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5096	{
5097	pThis->svga.u32MaxWidth -= 256;
5098	pThis->svga.u32MaxHeight -= 256;
5099	}
5100	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5101
5102	# ifdef DEBUG_GMR_ACCESS
5103	/* Register the GMR access handler type. */
5104	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5105	vmsvgaR3GMRAccessHandler,
5106	NULL, NULL, NULL,
5107	NULL, NULL, NULL,
5108	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5109	AssertRCReturn(rc, rc);
5110	# endif
5111	# ifdef DEBUG_FIFO_ACCESS
5112	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5113	vmsvgaR3FIFOAccessHandler,
5114	NULL, NULL, NULL,
5115	NULL, NULL, NULL,
5116	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5117	AssertRCReturn(rc, rc);
5118	#endif
5119
5120	/* Create the async IO thread. */
5121	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5122	RTTHREADTYPE_IO, "VMSVGA FIFO");
5123	if (RT_FAILURE(rc))
5124	{
5125	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5126	return rc;
5127	}
5128
5129	/*
5130	* Statistics.
5131	*/
5132	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5133	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5134	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5135	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5136	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5137	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5138	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5139	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5140	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5141	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5142	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5143	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5144	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5145	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5146	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5147	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5148	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5149	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5150	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5151	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5152	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5153	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5154	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5155	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5156	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5157	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5158	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5159	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5160	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5161	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5162	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5163	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5164	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5165	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5166	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5167	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5168	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5169	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5170	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5171	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5172	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5173	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5174	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5175	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5176	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5177	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5178	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5179	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5180	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5181	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5182	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5183	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5184	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5185	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5186	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5187	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5188
5189	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5190	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5191	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5192	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5193	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5194	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5195	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5196	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5197	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5198	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5199	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5200	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5201	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5202	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5203	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5204	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5205	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5206	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5207	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5208	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5209	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5210	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5211	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5212	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5213	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5214	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5215	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5216	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5217	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5218	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5219	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5220	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5221
5222	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5223	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5224	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5225	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5226	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5227	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5228	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5229	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5230	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5231	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5232	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5233	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5234	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5235	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5236	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5237	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5238	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5239	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5240	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5241	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5242	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5243	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5244	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5245	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5246	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5247	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5248	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5249	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5250	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5251	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5252	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5253	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5254	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5255	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5256	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5257	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5258	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5259	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5260	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5261	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5262	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5263	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5264	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5265	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5266	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5267	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5268	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5269	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5270	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5271
5272	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5273	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5274	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5275	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5276	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5277	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5278	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5279
5280	/*
5281	* Info handlers.
5282	*/
5283	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5284	# ifdef VBOX_WITH_VMSVGA3D
5285	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5286	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5287	"VMSVGA 3d surface details. "
5288	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5289	vmsvgaR3Info3dSurface);
5290	# endif
5291
5292	return VINF_SUCCESS;
5293	}
5294
5295	# ifdef VBOX_WITH_VMSVGA3D
5296	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5297	static const char * const g_apszVmSvgaDevCapNames[] =
5298	{
5299	"x3D", /* = 0 */
5300	"xMAX_LIGHTS",
5301	"xMAX_TEXTURES",
5302	"xMAX_CLIP_PLANES",
5303	"xVERTEX_SHADER_VERSION",
5304	"xVERTEX_SHADER",
5305	"xFRAGMENT_SHADER_VERSION",
5306	"xFRAGMENT_SHADER",
5307	"xMAX_RENDER_TARGETS",
5308	"xS23E8_TEXTURES",
5309	"xS10E5_TEXTURES",
5310	"xMAX_FIXED_VERTEXBLEND",
5311	"xD16_BUFFER_FORMAT",
5312	"xD24S8_BUFFER_FORMAT",
5313	"xD24X8_BUFFER_FORMAT",
5314	"xQUERY_TYPES",
5315	"xTEXTURE_GRADIENT_SAMPLING",
5316	"rMAX_POINT_SIZE",
5317	"xMAX_SHADER_TEXTURES",
5318	"xMAX_TEXTURE_WIDTH",
5319	"xMAX_TEXTURE_HEIGHT",
5320	"xMAX_VOLUME_EXTENT",
5321	"xMAX_TEXTURE_REPEAT",
5322	"xMAX_TEXTURE_ASPECT_RATIO",
5323	"xMAX_TEXTURE_ANISOTROPY",
5324	"xMAX_PRIMITIVE_COUNT",
5325	"xMAX_VERTEX_INDEX",
5326	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5327	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5328	"xMAX_VERTEX_SHADER_TEMPS",
5329	"xMAX_FRAGMENT_SHADER_TEMPS",
5330	"xTEXTURE_OPS",
5331	"xSURFACEFMT_X8R8G8B8",
5332	"xSURFACEFMT_A8R8G8B8",
5333	"xSURFACEFMT_A2R10G10B10",
5334	"xSURFACEFMT_X1R5G5B5",
5335	"xSURFACEFMT_A1R5G5B5",
5336	"xSURFACEFMT_A4R4G4B4",
5337	"xSURFACEFMT_R5G6B5",
5338	"xSURFACEFMT_LUMINANCE16",
5339	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5340	"xSURFACEFMT_ALPHA8",
5341	"xSURFACEFMT_LUMINANCE8",
5342	"xSURFACEFMT_Z_D16",
5343	"xSURFACEFMT_Z_D24S8",
5344	"xSURFACEFMT_Z_D24X8",
5345	"xSURFACEFMT_DXT1",
5346	"xSURFACEFMT_DXT2",
5347	"xSURFACEFMT_DXT3",
5348	"xSURFACEFMT_DXT4",
5349	"xSURFACEFMT_DXT5",
5350	"xSURFACEFMT_BUMPX8L8V8U8",
5351	"xSURFACEFMT_A2W10V10U10",
5352	"xSURFACEFMT_BUMPU8V8",
5353	"xSURFACEFMT_Q8W8V8U8",
5354	"xSURFACEFMT_CxV8U8",
5355	"xSURFACEFMT_R_S10E5",
5356	"xSURFACEFMT_R_S23E8",
5357	"xSURFACEFMT_RG_S10E5",
5358	"xSURFACEFMT_RG_S23E8",
5359	"xSURFACEFMT_ARGB_S10E5",
5360	"xSURFACEFMT_ARGB_S23E8",
5361	"xMISSING62",
5362	"xMAX_VERTEX_SHADER_TEXTURES",
5363	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5364	"xSURFACEFMT_V16U16",
5365	"xSURFACEFMT_G16R16",
5366	"xSURFACEFMT_A16B16G16R16",
5367	"xSURFACEFMT_UYVY",
5368	"xSURFACEFMT_YUY2",
5369	"xMULTISAMPLE_NONMASKABLESAMPLES",
5370	"xMULTISAMPLE_MASKABLESAMPLES",
5371	"xALPHATOCOVERAGE",
5372	"xSUPERSAMPLE",
5373	"xAUTOGENMIPMAPS",
5374	"xSURFACEFMT_NV12",
5375	"xSURFACEFMT_AYUV",
5376	"xMAX_CONTEXT_IDS",
5377	"xMAX_SURFACE_IDS",
5378	"xSURFACEFMT_Z_DF16",
5379	"xSURFACEFMT_Z_DF24",
5380	"xSURFACEFMT_Z_D24S8_INT",
5381	"xSURFACEFMT_BC4_UNORM",
5382	"xSURFACEFMT_BC5_UNORM", /* 83 */
5383	};
5384	# endif
5385
5386
5387	/**
5388	* Power On notification.
5389	*
5390	* @returns VBox status code.
5391	* @param pDevIns The device instance data.
5392	*
5393	* @remarks Caller enters the device critical section.
5394	*/
5395	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
5396	{
5397	# ifdef VBOX_WITH_VMSVGA3D
5398	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5399	if (pThis->svga.f3DEnabled)
5400	{
5401	int rc = vmsvga3dPowerOn(pThis);
5402
5403	if (RT_SUCCESS(rc))
5404	{
5405	bool fSavedBuffering = RTLogRelSetBuffering(true);
5406	SVGA3dCapsRecord *pCaps;
5407	SVGA3dCapPair *pData;
5408	uint32_t idxCap = 0;
5409
5410	/* 3d hardware version; latest and greatest */
5411	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5412	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5413
5414	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5415	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5416	pData = (SVGA3dCapPair *)&pCaps->data;
5417
5418	/* Fill out all 3d capabilities. */
5419	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5420	{
5421	uint32_t val = 0;
5422
5423	rc = vmsvga3dQueryCaps(pThis, i, &val);
5424	if (RT_SUCCESS(rc))
5425	{
5426	pData[idxCap][0] = i;
5427	pData[idxCap][1] = val;
5428	idxCap++;
5429	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5430	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5431	else
5432	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5433	&g_apszVmSvgaDevCapNames[i][1]));
5434	}
5435	else
5436	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5437	}
5438	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5439	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5440
5441	/* Mark end of record array. */
5442	pCaps->header.length = 0;
5443
5444	RTLogRelSetBuffering(fSavedBuffering);
5445	}
5446	}
5447	# else /* !VBOX_WITH_VMSVGA3D */
5448	RT_NOREF(pDevIns);
5449	# endif /* !VBOX_WITH_VMSVGA3D */
5450	}
5451
5452	#endif /* IN_RING3 */
5453

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 69304

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