DevVGA-SVGA.cpp@ 106221

Last change on this file since 106221 was 106188, checked in by vboxsync, 2 months ago
3D: Conditionally enable 3D backend in 2D mode if VMSVGA2dGBO extradata is set (experimental change for testing purposes). bugref:10580
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1	/* $Id: DevVGA-SVGA.cpp 106188 2024-10-01 09:52:02Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - Log8 for content of constant and vertex buffers.
15	* - LogRel for the usual important stuff.
16	* - LogRel2 for cursor.
17	* - LogRel3 for 3D performance data.
18	* - LogRel4 for HW accelerated graphics output.
19	*/
20
21	/*
22	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
23	*
24	* This file is part of VirtualBox base platform packages, as
25	* available from https://www.virtualbox.org.
26	*
27	* This program is free software; you can redistribute it and/or
28	* modify it under the terms of the GNU General Public License
29	* as published by the Free Software Foundation, in version 3 of the
30	* License.
31	*
32	* This program is distributed in the hope that it will be useful, but
33	* WITHOUT ANY WARRANTY; without even the implied warranty of
34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35	* General Public License for more details.
36	*
37	* You should have received a copy of the GNU General Public License
38	* along with this program; if not, see <https://www.gnu.org/licenses>.
39	*
40	* SPDX-License-Identifier: GPL-3.0-only
41	*/
42
43
44	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
45	*
46	* This device emulation was contributed by trivirt AG. It offers an
47	* alternative to our Bochs based VGA graphics and 3d emulations. This is
48	* valuable for Xorg based guests, as there is driver support shipping with Xorg
49	* since it forked from XFree86.
50	*
51	*
52	* @section sec_dev_vmsvga_sdk The VMware SDK
53	*
54	* This is officially deprecated now, however it's still quite useful,
55	* especially for getting the old features working:
56	* http://vmware-svga.sourceforge.net/
57	*
58	* They currently point developers at the following resources.
59	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
60	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
61	* - http://cgit.freedesktop.org/mesa/vmwgfx/
62	*
63	* @subsection subsec_dev_vmsvga_sdk_results Test results
64	*
65	* Test results:
66	* - 2dmark.img:
67	* + todo
68	* - backdoor-tclo.img:
69	* + todo
70	* - blit-cube.img:
71	* + todo
72	* - bunnies.img:
73	* + todo
74	* - cube.img:
75	* + todo
76	* - cubemark.img:
77	* + todo
78	* - dynamic-vertex-stress.img:
79	* + todo
80	* - dynamic-vertex.img:
81	* + todo
82	* - fence-stress.img:
83	* + todo
84	* - gmr-test.img:
85	* + todo
86	* - half-float-test.img:
87	* + todo
88	* - noscreen-cursor.img:
89	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
90	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
91	* visible though.)
92	* - Cursor animation via the palette doesn't work.
93	* - During debugging, it turns out that the framebuffer content seems to
94	* be halfways ignore or something (memset(fb, 0xcc, lots)).
95	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
96	* grow it 0x10 fold (128KB -> 2MB like in WS10).
97	* - null.img:
98	* + todo
99	* - pong.img:
100	* + todo
101	* - presentReadback.img:
102	* + todo
103	* - resolution-set.img:
104	* + todo
105	* - rt-gamma-test.img:
106	* + todo
107	* - screen-annotation.img:
108	* + todo
109	* - screen-cursor.img:
110	* + todo
111	* - screen-dma-coalesce.img:
112	* + todo
113	* - screen-gmr-discontig.img:
114	* + todo
115	* - screen-gmr-remap.img:
116	* + todo
117	* - screen-multimon.img:
118	* + todo
119	* - screen-present-clip.img:
120	* + todo
121	* - screen-render-test.img:
122	* + todo
123	* - screen-simple.img:
124	* + todo
125	* - screen-text.img:
126	* + todo
127	* - simple-shaders.img:
128	* + todo
129	* - simple_blit.img:
130	* + todo
131	* - tiny-2d-updates.img:
132	* + todo
133	* - video-formats.img:
134	* + todo
135	* - video-sync.img:
136	* + todo
137	*
138	*/
139
140
141	/*********************************************************************************************************************************
142	* Header Files *
143	*********************************************************************************************************************************/
144	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
145	#include <VBox/vmm/pdmdev.h>
146	#include <VBox/version.h>
147	#include <VBox/err.h>
148	#include <VBox/log.h>
149	#include <VBox/vmm/pgm.h>
150	#include <VBox/sup.h>
151
152	#include <iprt/assert.h>
153	#include <iprt/semaphore.h>
154	#include <iprt/uuid.h>
155	#ifdef IN_RING3
156	# include <iprt/ctype.h>
157	# include <iprt/mem.h>
158	# ifdef VBOX_STRICT
159	# include <iprt/time.h>
160	# endif
161	#endif
162
163	#include <VBox/AssertGuest.h>
164	#include <VBox/VMMDev.h>
165	#include <VBoxVideo.h>
166	#include <VBox/bioslogo.h>
167
168	#ifdef LOG_ENABLED
169	#include "svgadump/svga_dump.h"
170	#endif
171
172	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
173	#include "DevVGA.h"
174
175	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
176	#ifdef VBOX_WITH_VMSVGA3D
177	# include "DevVGA-SVGA3d.h"
178	# ifdef RT_OS_DARWIN
179	# include "DevVGA-SVGA3d-cocoa.h"
180	# endif
181	# ifdef RT_OS_LINUX
182	# ifdef IN_RING3
183	# include "DevVGA-SVGA3d-glLdr.h"
184	# endif
185	# endif
186	#endif
187	#ifdef IN_RING3
188	#include "DevVGA-SVGA-internal.h"
189	#endif
190
191
192	/*********************************************************************************************************************************
193	* Defined Constants And Macros *
194	*********************************************************************************************************************************/
195	/**
196	* Macro for checking if a fixed FIFO register is valid according to the
197	* current FIFO configuration.
198	*
199	* @returns true / false.
200	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
201	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
202	*/
203	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
204
205
206	/*********************************************************************************************************************************
207	* Structures and Typedefs *
208	*********************************************************************************************************************************/
209
210
211	/*********************************************************************************************************************************
212	* Internal Functions *
213	*********************************************************************************************************************************/
214	#ifdef IN_RING3
215	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
216	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
217	# endif
218	# ifdef DEBUG_GMR_ACCESS
219	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
220	# endif
221	#endif
222
223
224	/*********************************************************************************************************************************
225	* Global Variables *
226	*********************************************************************************************************************************/
227	#ifdef IN_RING3
228
229	/**
230	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
231	*/
232	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
233	{
234	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
235	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
236	SSMFIELD_ENTRY_TERM()
237	};
238
239	/**
240	* SSM descriptor table for the GMR structure.
241	*/
242	static SSMFIELD const g_aGMRFields[] =
243	{
244	SSMFIELD_ENTRY( GMR, cMaxPages),
245	SSMFIELD_ENTRY( GMR, cbTotal),
246	SSMFIELD_ENTRY( GMR, numDescriptors),
247	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
248	SSMFIELD_ENTRY_TERM()
249	};
250
251	/**
252	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
253	*/
254	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
255	{
256	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
257	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
258	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
259	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
260	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
261	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
262	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
263	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
264	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
265	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
266	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
267	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
268	SSMFIELD_ENTRY_TERM()
269	};
270
271	/**
272	* SSM descriptor table for the VMSVGAR3STATE structure.
273	*/
274	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
275	{
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
277	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
278	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
279	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
280	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
281	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
282	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
283	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
284	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
285	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
287	#ifdef VMSVGA_USE_EMT_HALT_CODE
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
289	#else
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
291	#endif
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
355
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
359	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
360
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
364	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
365	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
366	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
367	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
368	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
369	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
370	# endif
371	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
372	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
375
376	SSMFIELD_ENTRY_TERM()
377	};
378
379	/**
380	* SSM descriptor table for the VGAState.svga structure.
381	*/
382	static SSMFIELD const g_aVGAStateSVGAFields[] =
383	{
384	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
387	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
388	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
389	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
390	SSMFIELD_ENTRY( VMSVGAState, fBusy),
391	SSMFIELD_ENTRY( VMSVGAState, fTraces),
392	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
393	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
394	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
395	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
396	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
397	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
398	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
399	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
400	SSMFIELD_ENTRY_VER( VMSVGAState, u32DeviceCaps2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
401	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverId, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
402	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer1, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
403	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
404	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer3, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
405	SSMFIELD_ENTRY_VER( VMSVGAState, u32FenceLast, VGA_SAVEDSTATE_VERSION_VMSVGA_SVGA3),
406	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
410	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
411	SSMFIELD_ENTRY( VMSVGAState, uWidth),
412	SSMFIELD_ENTRY( VMSVGAState, uHeight),
413	SSMFIELD_ENTRY( VMSVGAState, uBpp),
414	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
415	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
416	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
417	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
418	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
419	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
420	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
421	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
422	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
423	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
424	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
428	SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
429	SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
430	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
431	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
432
433	SSMFIELD_ENTRY_TERM()
434	};
435	#endif /* IN_RING3 */
436
437
438	/*********************************************************************************************************************************
439	* Internal Functions *
440	*********************************************************************************************************************************/
441	#ifdef IN_RING3
442	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
443	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
444	uint32_t uVersion, uint32_t uPass);
445	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
446	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
447	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState);
448	#endif /* IN_RING3 */
449
450
451	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
452	#if defined(LOG_ENABLED)
453	/**
454	* Index register string name lookup
455	*
456	* @returns Index register string or "UNKNOWN"
457	* @param pThis The shared VGA/VMSVGA state.
458	* @param idxReg The index register.
459	*/
460	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
461	{
462	AssertCompile(SVGA_REG_TOP == 84); /* Ensure that the correct headers are used. */
463	switch (idxReg)
464	{
465	SVGA_CASE_ID2STR(SVGA_REG_ID);
466	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
467	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
468	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
469	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
470	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
471	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
472	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
473	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
474	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
475	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
476	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
477	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
478	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
479	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
480	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
481	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
482
483	/* ID 0 implementation only had the above registers, then the palette */
484	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
485	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
486	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
487	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
488	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
489	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
490	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
491	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
492	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
493	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
494	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
495	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
496	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
497	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
498	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
499	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
500	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
501
502	/* Legacy multi-monitor support */
503	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
504	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
505	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
506	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
507	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
508	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
509	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
510
511	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
512	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
513	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
514	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
515
516	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
517	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
518	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
519	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
520	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
521	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
522	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
523	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
524	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
525	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
526	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
527	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
528	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
529	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
530	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
531	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
532	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
533	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
534	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
535	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
536	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
537	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
538	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
539	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
540	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
541	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
542	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
543	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
544	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
545	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
546	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
547	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
548	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_HIGH32);
549	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_LOW32);
550	SVGA_CASE_ID2STR(SVGA_REG_FB_START_HIGH32);
551	SVGA_CASE_ID2STR(SVGA_REG_FB_START_LOW32);
552	SVGA_CASE_ID2STR(SVGA_REG_MSHINT);
553	SVGA_CASE_ID2STR(SVGA_REG_IRQ_STATUS);
554	SVGA_CASE_ID2STR(SVGA_REG_DIRTY_TRACKING);
555	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
556
557	default:
558	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
559	return "SVGA_SCRATCH_BASE reg";
560	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
561	return "SVGA_PALETTE_BASE reg";
562	return "UNKNOWN";
563	}
564	}
565	#endif /* LOG_ENABLED */
566
567	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
568	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
569	{
570	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
571	switch (idxDevCap)
572	{
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
807	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
809	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
810	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
811	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
812	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
813	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
814	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
815	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
816	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
817	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
818	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
819	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
820	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
821	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
822	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
823	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
824	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
825	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
826	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
827	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
828	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
829	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
830	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
831	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
832	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
833	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
834
835	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
836
837	default:
838	break;
839	}
840	return "UNKNOWN";
841	}
842	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
843	#undef SVGA_CASE_ID2STR
844
845
846	#ifdef IN_RING3
847
848	/**
849	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
850	*/
851	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
852	{
853	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
854	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
855
856	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
857	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
858
859	/** @todo Test how it interacts with multiple screen objects. */
860	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
861	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
862	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
863
864	if (x < uWidth)
865	{
866	pThis->svga.viewport.x = x;
867	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
868	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
869	}
870	else
871	{
872	pThis->svga.viewport.x = uWidth;
873	pThis->svga.viewport.cx = 0;
874	pThis->svga.viewport.xRight = uWidth;
875	}
876	if (y < uHeight)
877	{
878	pThis->svga.viewport.y = y;
879	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
880	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
881	pThis->svga.viewport.yHighWC = uHeight - y;
882	}
883	else
884	{
885	pThis->svga.viewport.y = uHeight;
886	pThis->svga.viewport.cy = 0;
887	pThis->svga.viewport.yLowWC = 0;
888	pThis->svga.viewport.yHighWC = 0;
889	}
890
891	# ifdef VBOX_WITH_VMSVGA3D
892	/*
893	* Now inform the 3D backend.
894	*/
895	if (pThis->svga.f3DEnabled)
896	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
897	# else
898	RT_NOREF(OldViewport);
899	# endif
900	}
901
902
903	/**
904	* Updating screen information in API
905	*
906	* @param pThis The The shared VGA/VMSVGA instance data.
907	* @param pThisCC The VGA/VMSVGA state for ring-3.
908	*/
909	static void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
910	{
911	int rc;
912
913	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
914
915	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
916	{
917	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
918	if (!pScreen->fModified)
919	continue;
920
921	pScreen->fModified = false;
922
923	VBVAINFOVIEW view;
924	RT_ZERO(view);
925	view.u32ViewIndex = pScreen->idScreen;
926	// view.u32ViewOffset = 0;
927	view.u32ViewSize = pThis->vram_size;
928	view.u32MaxScreenSize = pThis->vram_size;
929
930	VBVAINFOSCREEN screen;
931	RT_ZERO(screen);
932	screen.u32ViewIndex = pScreen->idScreen;
933
934	if (pScreen->fDefined)
935	{
936	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
937	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
938	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
939	{
940	Assert(pThis->svga.fGFBRegisters);
941	continue;
942	}
943
944	screen.i32OriginX = pScreen->xOrigin;
945	screen.i32OriginY = pScreen->yOrigin;
946	screen.u32StartOffset = pScreen->offVRAM;
947	screen.u32LineSize = pScreen->cbPitch;
948	screen.u32Width = pScreen->cWidth;
949	screen.u32Height = pScreen->cHeight;
950	screen.u16BitsPerPixel = pScreen->cBpp;
951	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
952	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
953	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
954	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
955	}
956	else
957	{
958	/* Screen is destroyed. */
959	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
960	}
961
962	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
963	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
964	AssertRC(rc);
965	}
966	}
967
968
969	/**
970	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
971	*
972	* Used to update screen offsets (positions) since appearently vmwgfx fails to
973	* pass correct offsets thru FIFO.
974	*/
975	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
976	{
977	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
978	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
979	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
980
981	AssertReturnVoid(pSVGAState);
982
983	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
984	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
985	for (uint32_t i = 0; i < cPositions; ++i)
986	{
987	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
988	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
989	continue;
990
991	if (paPositions[i].x == -1)
992	continue;
993	if (paPositions[i].y == -1)
994	continue;
995
996	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
997	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
998	pSVGAState->aScreens[i].fModified = true;
999	}
1000
1001	vmsvgaR3VBVAResize(pThis, pThisCC);
1002	}
1003
1004	#endif /* IN_RING3 */
1005
1006	/**
1007	* Read port register
1008	*
1009	* @returns VBox status code.
1010	* @param pDevIns The device instance.
1011	* @param pThis The shared VGA/VMSVGA state.
1012	* @param idxReg The register index being read.
1013	* @param pu32 Where to store the read value
1014	*/
1015	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t idxReg, uint32_t *pu32)
1016	{
1017	#ifdef IN_RING3
1018	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1019	#endif
1020	int rc = VINF_SUCCESS;
1021	*pu32 = 0;
1022
1023	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1024	if ( idxReg >= SVGA_REG_ID_0_TOP
1025	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1026	{
1027	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1028	Log(("vmsvgaReadPort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1029	}
1030
1031	switch (idxReg)
1032	{
1033	case SVGA_REG_ID:
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1035	*pu32 = pThis->svga.u32SVGAId;
1036	break;
1037
1038	case SVGA_REG_ENABLE:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1040	*pu32 = pThis->svga.fEnabled;
1041	break;
1042
1043	case SVGA_REG_WIDTH:
1044	{
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1046	if ( pThis->svga.fEnabled
1047	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1048	*pu32 = pThis->svga.uWidth;
1049	else
1050	{
1051	#ifndef IN_RING3
1052	rc = VINF_IOM_R3_IOPORT_READ;
1053	#else
1054	*pu32 = pThisCC->pDrv->cx;
1055	#endif
1056	}
1057	break;
1058	}
1059
1060	case SVGA_REG_HEIGHT:
1061	{
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1063	if ( pThis->svga.fEnabled
1064	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1065	*pu32 = pThis->svga.uHeight;
1066	else
1067	{
1068	#ifndef IN_RING3
1069	rc = VINF_IOM_R3_IOPORT_READ;
1070	#else
1071	*pu32 = pThisCC->pDrv->cy;
1072	#endif
1073	}
1074	break;
1075	}
1076
1077	case SVGA_REG_MAX_WIDTH:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1079	*pu32 = pThis->svga.u32MaxWidth;
1080	break;
1081
1082	case SVGA_REG_MAX_HEIGHT:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1084	*pu32 = pThis->svga.u32MaxHeight;
1085	break;
1086
1087	case SVGA_REG_DEPTH:
1088	/* This returns the color depth of the current mode. */
1089	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1090	switch (pThis->svga.uBpp)
1091	{
1092	case 15:
1093	case 16:
1094	case 24:
1095	*pu32 = pThis->svga.uBpp;
1096	break;
1097
1098	default:
1099	case 32:
1100	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1101	break;
1102	}
1103	break;
1104
1105	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1107	*pu32 = pThis->svga.uHostBpp;
1108	break;
1109
1110	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1112	*pu32 = pThis->svga.uBpp;
1113	break;
1114
1115	case SVGA_REG_PSEUDOCOLOR:
1116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1117	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1118	break;
1119
1120	case SVGA_REG_RED_MASK:
1121	case SVGA_REG_GREEN_MASK:
1122	case SVGA_REG_BLUE_MASK:
1123	{
1124	uint32_t uBpp;
1125
1126	if (pThis->svga.fEnabled)
1127	uBpp = pThis->svga.uBpp;
1128	else
1129	uBpp = pThis->svga.uHostBpp;
1130
1131	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1132	switch (uBpp)
1133	{
1134	case 8:
1135	u32RedMask = 0x07;
1136	u32GreenMask = 0x38;
1137	u32BlueMask = 0xc0;
1138	break;
1139
1140	case 15:
1141	u32RedMask = 0x0000001f;
1142	u32GreenMask = 0x000003e0;
1143	u32BlueMask = 0x00007c00;
1144	break;
1145
1146	case 16:
1147	u32RedMask = 0x0000001f;
1148	u32GreenMask = 0x000007e0;
1149	u32BlueMask = 0x0000f800;
1150	break;
1151
1152	case 24:
1153	case 32:
1154	default:
1155	u32RedMask = 0x00ff0000;
1156	u32GreenMask = 0x0000ff00;
1157	u32BlueMask = 0x000000ff;
1158	break;
1159	}
1160	switch (idxReg)
1161	{
1162	case SVGA_REG_RED_MASK:
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1164	*pu32 = u32RedMask;
1165	break;
1166
1167	case SVGA_REG_GREEN_MASK:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1169	*pu32 = u32GreenMask;
1170	break;
1171
1172	case SVGA_REG_BLUE_MASK:
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1174	*pu32 = u32BlueMask;
1175	break;
1176	}
1177	break;
1178	}
1179
1180	case SVGA_REG_BYTES_PER_LINE:
1181	{
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1183	if ( pThis->svga.fEnabled
1184	&& pThis->svga.cbScanline)
1185	*pu32 = pThis->svga.cbScanline;
1186	else
1187	{
1188	#ifndef IN_RING3
1189	rc = VINF_IOM_R3_IOPORT_READ;
1190	#else
1191	*pu32 = pThisCC->pDrv->cbScanline;
1192	#endif
1193	}
1194	break;
1195	}
1196
1197	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1199	*pu32 = pThis->vram_size;
1200	break;
1201
1202	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1204	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1205	*pu32 = pThis->GCPhysVRAM;
1206	break;
1207
1208	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1210	/* Always zero in our case. */
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1215	{
1216	#ifndef IN_RING3
1217	rc = VINF_IOM_R3_IOPORT_READ;
1218	#else
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1220
1221	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1222	if ( pThis->svga.fEnabled
1223	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1224	{
1225	/* Hardware enabled; return real framebuffer size .*/
1226	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1227	}
1228	else
1229	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1230
1231	pu32 = RT_MIN(pThis->vram_size, pu32);
1232	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1233	#endif
1234	break;
1235	}
1236
1237	case SVGA_REG_CAPABILITIES:
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1239	*pu32 = pThis->svga.u32DeviceCaps;
1240	break;
1241
1242	case SVGA_REG_MEM_START: /* FIFO start */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1244	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1245	*pu32 = pThis->svga.GCPhysFIFO;
1246	break;
1247
1248	case SVGA_REG_MEM_SIZE: /* FIFO size */
1249	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1250	*pu32 = pThis->svga.cbFIFO;
1251	break;
1252
1253	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1255	*pu32 = pThis->svga.fConfigured;
1256	break;
1257
1258	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1260	*pu32 = 0;
1261	break;
1262
1263	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1265	if (pThis->svga.fBusy)
1266	{
1267	#ifndef IN_RING3
1268	/* Go to ring-3 and halt the CPU. */
1269	rc = VINF_IOM_R3_IOPORT_READ;
1270	RT_NOREF(pDevIns);
1271	break;
1272	#else /* IN_RING3 */
1273	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1274	/* The guest is basically doing a HLT via the device here, but with
1275	a special wake up condition on FIFO completion. */
1276	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1277	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1278	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1279	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1280	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1281	if (pThis->svga.fBusy)
1282	{
1283	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1284	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1285	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1286	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1287	}
1288	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1289	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1290	# else
1291
1292	/* Delay the EMT a bit so the FIFO and others can get some work done.
1293	This used to be a crude 50 ms sleep. The current code tries to be
1294	more efficient, but the consept is still very crude. */
1295	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1296	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1297	RTThreadYield();
1298	if (pThis->svga.fBusy)
1299	{
1300	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1301
1302	if (pThis->svga.fBusy && cRefs == 1)
1303	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1304	if (pThis->svga.fBusy)
1305	{
1306	/** @todo If this code is going to stay, we need to call into the halt/wait
1307	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1308	* suffer when the guest is polling on a busy FIFO. */
1309	uint64_t uIgnored1, uIgnored2;
1310	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1311	if (cNsMaxWait >= RT_NS_100US)
1312	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1313	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1314	RT_MIN(cNsMaxWait, RT_NS_10MS));
1315	}
1316
1317	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1318	}
1319	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1320	# endif
1321	*pu32 = pThis->svga.fBusy != 0;
1322	#endif /* IN_RING3 */
1323	}
1324	else
1325	*pu32 = false;
1326	break;
1327
1328	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1329	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1330	*pu32 = pThis->svga.u32GuestId;
1331	break;
1332
1333	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1335	*pu32 = pThis->svga.cScratchRegion;
1336	break;
1337
1338	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1340	*pu32 = SVGA_FIFO_NUM_REGS;
1341	break;
1342
1343	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1345	*pu32 = pThis->svga.u32PitchLock;
1346	break;
1347
1348	case SVGA_REG_IRQMASK: /* Interrupt mask */
1349	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1350	*pu32 = pThis->svga.u32IrqMask;
1351	break;
1352
1353	/* See "Guest memory regions" below. */
1354	case SVGA_REG_GMR_ID:
1355	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1356	*pu32 = pThis->svga.u32CurrentGMRId;
1357	break;
1358
1359	case SVGA_REG_GMR_DESCRIPTOR:
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1361	/* Write only */
1362	*pu32 = 0;
1363	break;
1364
1365	case SVGA_REG_GMR_MAX_IDS:
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1367	*pu32 = pThis->svga.cGMR;
1368	break;
1369
1370	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1372	*pu32 = VMSVGA_MAX_GMR_PAGES;
1373	break;
1374
1375	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1377	*pu32 = pThis->svga.fTraces;
1378	break;
1379
1380	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1382	*pu32 = VMSVGA_MAX_GMR_PAGES;
1383	break;
1384
1385	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1386	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1387	*pu32 = VMSVGA_SURFACE_SIZE;
1388	break;
1389
1390	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1391	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1392	break;
1393
1394	/* Mouse cursor support. */
1395	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1396	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1397	*pu32 = pThis->svga.uCursorID;
1398	break;
1399
1400	case SVGA_REG_CURSOR_X:
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1402	*pu32 = pThis->svga.uCursorX;
1403	break;
1404
1405	case SVGA_REG_CURSOR_Y:
1406	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1407	*pu32 = pThis->svga.uCursorY;
1408	break;
1409
1410	case SVGA_REG_CURSOR_ON:
1411	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1412	*pu32 = pThis->svga.uCursorOn;
1413	break;
1414
1415	/* Legacy multi-monitor support */
1416	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1417	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1418	*pu32 = 1;
1419	break;
1420
1421	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1422	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1423	*pu32 = 0;
1424	break;
1425
1426	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1427	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1428	*pu32 = 0;
1429	break;
1430
1431	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1432	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1433	*pu32 = 0;
1434	break;
1435
1436	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1437	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1438	*pu32 = 0;
1439	break;
1440
1441	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1442	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1443	*pu32 = pThis->svga.uWidth;
1444	break;
1445
1446	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1447	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1448	*pu32 = pThis->svga.uHeight;
1449	break;
1450
1451	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1452	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1453	/* We must return something sensible here otherwise the Linux driver
1454	will take a legacy code path without 3d support. This number also
1455	limits how many screens Linux guests will allow. */
1456	*pu32 = pThis->cMonitors;
1457	break;
1458
1459	/*
1460	* SVGA_CAP_GBOBJECTS+ registers.
1461	*/
1462	case SVGA_REG_COMMAND_LOW:
1463	/* Lower 32 bits of command buffer physical address. */
1464	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1465	*pu32 = pThis->svga.u32RegCommandLow;
1466	break;
1467
1468	case SVGA_REG_COMMAND_HIGH:
1469	/* Upper 32 bits of command buffer PA. */
1470	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1471	*pu32 = pThis->svga.u32RegCommandHigh;
1472	break;
1473
1474	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1475	/* Max primary (screen) memory. */
1476	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1477	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1478	break;
1479
1480	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1481	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1482	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1483	*pu32 = pThis->vram_size / 1024;
1484	break;
1485
1486	case SVGA_REG_DEV_CAP:
1487	/* Write dev cap index, read value */
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1489	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1490	{
1491	RT_UNTRUSTED_VALIDATED_FENCE();
1492	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1493	}
1494	else
1495	*pu32 = 0;
1496	break;
1497
1498	case SVGA_REG_CMD_PREPEND_LOW:
1499	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1500	pu32 = 0; / Not supported. */
1501	break;
1502
1503	case SVGA_REG_CMD_PREPEND_HIGH:
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1505	pu32 = 0; / Not supported. */
1506	break;
1507
1508	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1509	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1510	*pu32 = pThis->svga.u32MaxWidth;
1511	break;
1512
1513	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1514	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1515	*pu32 = pThis->svga.u32MaxHeight;
1516	break;
1517
1518	case SVGA_REG_MOB_MAX_SIZE:
1519	/* Essentially the max texture size */
1520	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1521	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1522	break;
1523
1524	case SVGA_REG_BLANK_SCREEN_TARGETS:
1525	/// @todo STAM_REL_COUNTER_INC(&pThis->svga.aStatRegRd[idxReg]);
1526	pu32 = 0; / Not supported. */
1527	break;
1528
1529	case SVGA_REG_CAP2:
1530	*pu32 = pThis->svga.u32DeviceCaps2;
1531	break;
1532
1533	case SVGA_REG_DEVEL_CAP:
1534	pu32 = 0; / Not supported. */
1535	break;
1536
1537	/*
1538	* SVGA_REG_GUEST_DRIVER_* registers require SVGA_CAP2_DX2.
1539	*/
1540	case SVGA_REG_GUEST_DRIVER_ID:
1541	*pu32 = pThis->svga.u32GuestDriverId;
1542	break;
1543
1544	case SVGA_REG_GUEST_DRIVER_VERSION1:
1545	*pu32 = pThis->svga.u32GuestDriverVer1;
1546	break;
1547
1548	case SVGA_REG_GUEST_DRIVER_VERSION2:
1549	*pu32 = pThis->svga.u32GuestDriverVer2;
1550	break;
1551
1552	case SVGA_REG_GUEST_DRIVER_VERSION3:
1553	*pu32 = pThis->svga.u32GuestDriverVer3;
1554	break;
1555
1556	/*
1557	* SVGA_REG_CURSOR_ registers require SVGA_CAP2_CURSOR_MOB which the device does not support currently.
1558	*/
1559	case SVGA_REG_CURSOR_MOBID:
1560	*pu32 = SVGA_ID_INVALID;
1561	break;
1562
1563	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
1564	*pu32 = 0;
1565	break;
1566
1567	case SVGA_REG_CURSOR_MAX_DIMENSION:
1568	*pu32 = 0;
1569	break;
1570
1571	case SVGA_REG_FIFO_CAPS:
1572	{
1573	if (pThis->fVmSvga3)
1574	*pu32 = SVGA_FIFO_CAP_FENCE
1575	\| SVGA_FIFO_CAP_PITCHLOCK
1576	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
1577	\| SVGA_FIFO_CAP_RESERVE
1578	\| SVGA_FIFO_CAP_GMR2
1579	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
1580	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
1581	else
1582	*pu32 = 0;
1583	break;
1584	}
1585	case SVGA_REG_FENCE:
1586	{
1587	if (pThis->fVmSvga3)
1588	*pu32 = pThis->svga.u32FenceLast;
1589	else
1590	*pu32 = 0;
1591	break;
1592	}
1593
1594	case SVGA_REG_RESERVED1: /* SVGA_REG_RESERVED* correspond to SVGA_REG_CURSOR4_. Require SVGA_CAP2_EXTRA_REGS. /
1595	case SVGA_REG_RESERVED2:
1596	case SVGA_REG_RESERVED3:
1597	case SVGA_REG_RESERVED4:
1598	case SVGA_REG_RESERVED5:
1599	case SVGA_REG_SCREENDMA:
1600	pu32 = 0; / Not supported. */
1601	break;
1602
1603	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
1604	/** @todo "The maximum amount of guest-backed objects that the device can have resident at a time" */
1605	*pu32 = _1G / _1K;
1606	break;
1607
1608	case SVGA_REG_IRQ_STATUS:
1609	{
1610	if (pThis->fVmSvga3)
1611	*pu32 = pThis->svga.u32IrqStatus;
1612	else
1613	*pu32 = 0;
1614	break;
1615	}
1616
1617	default:
1618	{
1619	uint32_t offReg;
1620	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1621	{
1622	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1623	RT_UNTRUSTED_VALIDATED_FENCE();
1624	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1625	}
1626	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1627	{
1628	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1630	RT_UNTRUSTED_VALIDATED_FENCE();
1631	uint32_t u32 = pThis->last_palette[offReg / 3];
1632	switch (offReg % 3)
1633	{
1634	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1635	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1636	case 2: pu32 = u32 & 0xff; break; / blue */
1637	}
1638	}
1639	else
1640	{
1641	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1642	rc = VINF_IOM_R3_IOPORT_READ;
1643	#else
1644	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1645
1646	/* Do not assert. The guest might be reading all registers. */
1647	LogFunc(("Unknown reg=%#x\n", idxReg));
1648	#endif
1649	}
1650	break;
1651	}
1652	}
1653	LogFlow(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1654	return rc;
1655	}
1656
1657	#ifdef IN_RING3
1658	/**
1659	* Apply the current resolution settings to change the video mode.
1660	*
1661	* @returns VBox status code.
1662	* @param pThis The shared VGA state.
1663	* @param pThisCC The ring-3 VGA state.
1664	*/
1665	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1666	{
1667	/* Always do changemode on FIFO thread. */
1668	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1669
1670	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1671
1672	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1673
1674	if (pThis->svga.fGFBRegisters)
1675	{
1676	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1677	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1678	* deletes all screens other than screen #0, and redefines screen
1679	* #0 according to the specified mode. Drivers that use
1680	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1681	*/
1682
1683	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1684	Assert(pScreen->idScreen == 0);
1685
1686	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1687	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1688	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1689	{
1690	/* Do not apply the change if the guest has not finished updating registers.
1691	* This is necessary in order to make a full mode change, including freeing
1692	* pvScreenBitmap buffers for screen 0 if necessary.
1693	*/
1694	return VINF_SUCCESS;
1695	}
1696
1697	/* Remember screen bitmap buffers to be freed. */
1698	void * apvOldScreenBitmap[RT_ELEMENTS(pSVGAState->aScreens)];
1699	RT_ZERO(apvOldScreenBitmap);
1700
1701	pScreen->fDefined = true;
1702	pScreen->fModified = true;
1703	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1704	pScreen->xOrigin = 0;
1705	pScreen->yOrigin = 0;
1706	pScreen->offVRAM = 0;
1707	pScreen->cbPitch = pThis->svga.cbScanline;
1708	pScreen->cWidth = pThis->svga.uWidth;
1709	pScreen->cHeight = pThis->svga.uHeight;
1710	pScreen->cBpp = pThis->svga.uBpp;
1711	pScreen->cDpi = 0; /* GFB mode does not support dpi. */
1712	/* GFB mode uses the guest VRAM. The screen bitmap must be deallocated after 'vmsvgaR3VBVAResize'. */
1713	apvOldScreenBitmap[0] = pScreen->pvScreenBitmap;
1714	/* Set pvScreenBitmap to zero because if it is not, then vmsvgaR3VBVAResize uses it as VRAM address. */
1715	pScreen->pvScreenBitmap = 0;
1716
1717	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1718	{
1719	/* Delete screen. */
1720	pScreen = &pSVGAState->aScreens[iScreen];
1721	if (pScreen->fDefined)
1722	{
1723	pScreen->fModified = true;
1724	pScreen->fDefined = false;
1725
1726	#ifdef VBOX_WITH_VMSVGA3D
1727	if (RT_LIKELY(pThis->svga.f3DEnabled))
1728	vmsvga3dDestroyScreen(pThisCC, pScreen);
1729	#endif
1730	apvOldScreenBitmap[iScreen] = pScreen->pvScreenBitmap;
1731	pScreen->pvScreenBitmap = 0;
1732	}
1733	}
1734
1735	vmsvgaR3VBVAResize(pThis, pThisCC);
1736
1737	/* Deallocate screen bitmaps for all screens because GFB mode uses the guest VRAM. */
1738	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(apvOldScreenBitmap); ++iScreen)
1739	RTMemFree(apvOldScreenBitmap[iScreen]);
1740	}
1741	else
1742	{
1743	/* "If Screen Objects are supported, they can be used to fully
1744	* replace the functionality provided by the framebuffer registers
1745	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1746	*/
1747	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1748	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1749	pThis->svga.uBpp = pThis->svga.uHostBpp;
1750
1751	vmsvgaR3VBVAResize(pThis, pThisCC);
1752	}
1753
1754	/* Last stuff. For the VGA device screenshot. */
1755	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1756	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1757	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1758	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1759	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1760
1761	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1762	if ( pThis->svga.viewport.cx == 0
1763	&& pThis->svga.viewport.cy == 0)
1764	{
1765	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1766	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1767	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1768	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1769	pThis->svga.viewport.yLowWC = 0;
1770	}
1771
1772	return VINF_SUCCESS;
1773	}
1774
1775	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1776	{
1777	ASSERT_GUEST_LOGREL_MSG_RETURN(w > 0 && h > 0,
1778	("vmsvgaR3UpdateScreen: screen %d (%d,%d) %dx%d: Invalid height and/or width supplied.\n",
1779	pScreen->idScreen, x, y, w, h),
1780	VERR_INVALID_PARAMETER);
1781
1782	VBVACMDHDR cmd;
1783	cmd.x = (int16_t)(pScreen->xOrigin + x);
1784	cmd.y = (int16_t)(pScreen->yOrigin + y);
1785	cmd.w = (uint16_t)w;
1786	cmd.h = (uint16_t)h;
1787
1788	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1789	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1790	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1791	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1792
1793	return VINF_SUCCESS;
1794	}
1795
1796	#endif /* IN_RING3 */
1797	#if defined(IN_RING0) \|\| defined(IN_RING3)
1798
1799	/**
1800	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1801	*
1802	* @param pThis The shared VGA/VMSVGA instance data.
1803	* @param pThisCC The VGA/VMSVGA state for the current context.
1804	* @param fState The busy state.
1805	*/
1806	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1807	{
1808	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1809
1810	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1811	{
1812	/* Race / unfortunately scheduling. Highly unlikly. */
1813	uint32_t cLoops = 64;
1814	do
1815	{
1816	ASMNopPause();
1817	fState = (pThis->svga.fBusy != 0);
1818	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1819	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1820	}
1821	}
1822
1823
1824	/**
1825	* Update the scanline pitch in response to the guest changing mode
1826	* width/bpp.
1827	*
1828	* @param pThis The shared VGA/VMSVGA state.
1829	* @param pThisCC The VGA/VMSVGA state for the current context.
1830	*/
1831	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1832	{
1833	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1834	uint32_t uFifoPitchLock = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_PITCHLOCK];
1835	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1836	uint32_t uFifoMin = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_MIN];
1837
1838	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1839	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1840	* location but it has a different meaning.
1841	*/
1842	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1843	uFifoPitchLock = 0;
1844
1845	/* Sanitize values. */
1846	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1847	uFifoPitchLock = 0;
1848	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1849	uRegPitchLock = 0;
1850
1851	/* Prefer the register value to the FIFO value.*/
1852	if (uRegPitchLock)
1853	pThis->svga.cbScanline = uRegPitchLock;
1854	else if (uFifoPitchLock)
1855	pThis->svga.cbScanline = uFifoPitchLock;
1856	else
1857	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1858
1859	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1860	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1861	}
1862
1863	#endif /* IN_RING0 \|\| IN_RING3 */
1864
1865	#ifdef IN_RING3
1866
1867	/**
1868	* Sends cursor position and visibility information from legacy
1869	* SVGA registers to the front-end.
1870	*/
1871	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1872	{
1873	/*
1874	* Writing the X/Y/ID registers does not trigger changes; only writing the
1875	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1876	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1877	* register if they don't have to.
1878	*/
1879	uint32_t x, y, idScreen;
1880	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1881
1882	x = pThis->svga.uCursorX;
1883	y = pThis->svga.uCursorY;
1884	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1885
1886	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1887	* were extended as follows:
1888	*
1889	* SVGA_CURSOR_ON_HIDE 0
1890	* SVGA_CURSOR_ON_SHOW 1
1891	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1892	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1893	*
1894	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1895	* distinguish between the non-zero values but still remember them.
1896	*/
1897	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1898	{
1899	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1900	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1901	}
1902	pThis->svga.uCursorOn = uCursorOn;
1903	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1904	}
1905
1906	#endif /* IN_RING3 */
1907
1908
1909	/**
1910	* Write port register
1911	*
1912	* @returns Strict VBox status code.
1913	* @param pDevIns The device instance.
1914	* @param pThis The shared VGA/VMSVGA state.
1915	* @param pThisCC The VGA/VMSVGA state for the current context.
1916	* @param idxReg Rge register index being written.
1917	* @param u32 Value to write
1918	*/
1919	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idxReg, uint32_t u32)
1920	{
1921	#ifdef IN_RING3
1922	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1923	#endif
1924	VBOXSTRICTRC rc = VINF_SUCCESS;
1925	RT_NOREF(pThisCC);
1926
1927	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1928	if ( idxReg >= SVGA_REG_ID_0_TOP
1929	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1930	{
1931	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1932	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1933	}
1934	#ifdef LOG_ENABLED
1935	if (idxReg != SVGA_REG_DEV_CAP)
1936	LogFlow(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1937	else
1938	LogFlow(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1939	#endif
1940	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1941	switch (idxReg)
1942	{
1943	case SVGA_REG_WIDTH:
1944	case SVGA_REG_HEIGHT:
1945	case SVGA_REG_PITCHLOCK:
1946	case SVGA_REG_BITS_PER_PIXEL:
1947	pThis->svga.fGFBRegisters = true;
1948	break;
1949	default:
1950	break;
1951	}
1952
1953	switch (idxReg)
1954	{
1955	case SVGA_REG_ID:
1956	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1957	if ( u32 == SVGA_ID_0
1958	\|\| u32 == SVGA_ID_1
1959	\|\| u32 == SVGA_ID_2
1960	\|\| u32 == SVGA_ID_3)
1961	pThis->svga.u32SVGAId = u32;
1962	else
1963	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1964	break;
1965
1966	case SVGA_REG_ENABLE:
1967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1968	#ifdef IN_RING3
1969	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1970	&& pThis->svga.fEnabled == false)
1971	{
1972	/* Make a backup copy of the first 512kb in order to save font data etc. */
1973	/** @todo should probably swap here, rather than copy + zero */
1974	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1975	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1976	}
1977
1978	pThis->svga.fEnabled = u32;
1979	if (pThis->svga.fEnabled)
1980	{
1981	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1982	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1983	{
1984	/* Keep the current mode. */
1985	pThis->svga.uWidth = pThisCC->pDrv->cx;
1986	pThis->svga.uHeight = pThisCC->pDrv->cy;
1987	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1988	vmsvgaHCUpdatePitch(pThis, pThisCC);
1989	}
1990
1991	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1992	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1993	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1994	# ifdef LOG_ENABLED
1995	if (!pThis->fVmSvga3)
1996	{
1997	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1998	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1999	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2000	}
2001	# endif
2002
2003	/* Disable or enable dirty page tracking according to the current fTraces value. */
2004	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2005
2006	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2007	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2008	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
2009
2010	/* Make the cursor visible again as needed. */
2011	if (pSVGAState->Cursor.fActive)
2012	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
2013	}
2014	else
2015	{
2016	/* Make sure the cursor is off. */
2017	if (pSVGAState->Cursor.fActive)
2018	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
2019
2020	/* Restore the text mode backup. */
2021	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
2022
2023	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
2024
2025	/* Enable dirty page tracking again when going into legacy mode. */
2026	vmsvgaR3SetTraces(pDevIns, pThis, true);
2027
2028	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
2029	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
2030	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
2031
2032	/* Clear the pitch lock. */
2033	pThis->svga.u32PitchLock = 0;
2034	}
2035	#else /* !IN_RING3 */
2036	rc = VINF_IOM_R3_IOPORT_WRITE;
2037	#endif /* !IN_RING3 */
2038	break;
2039
2040	case SVGA_REG_WIDTH:
2041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
2042	if (u32 != pThis->svga.uWidth)
2043	{
2044	if (u32 <= pThis->svga.u32MaxWidth)
2045	{
2046	#if defined(IN_RING3) \|\| defined(IN_RING0)
2047	pThis->svga.uWidth = u32;
2048	vmsvgaHCUpdatePitch(pThis, pThisCC);
2049	if (pThis->svga.fEnabled)
2050	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2051	#else
2052	rc = VINF_IOM_R3_IOPORT_WRITE;
2053	#endif
2054	}
2055	else
2056	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
2057	}
2058	/* else: nop */
2059	break;
2060
2061	case SVGA_REG_HEIGHT:
2062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2063	if (u32 != pThis->svga.uHeight)
2064	{
2065	if (u32 <= pThis->svga.u32MaxHeight)
2066	{
2067	pThis->svga.uHeight = u32;
2068	if (pThis->svga.fEnabled)
2069	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2070	}
2071	else
2072	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
2073	}
2074	/* else: nop */
2075	break;
2076
2077	case SVGA_REG_DEPTH:
2078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2079	/** @todo read-only?? */
2080	break;
2081
2082	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2084	if (pThis->svga.uBpp != u32)
2085	{
2086	if (u32 <= 32)
2087	{
2088	#if defined(IN_RING3) \|\| defined(IN_RING0)
2089	pThis->svga.uBpp = u32;
2090	vmsvgaHCUpdatePitch(pThis, pThisCC);
2091	if (pThis->svga.fEnabled)
2092	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2093	#else
2094	rc = VINF_IOM_R3_IOPORT_WRITE;
2095	#endif
2096	}
2097	else
2098	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
2099	}
2100	/* else: nop */
2101	break;
2102
2103	case SVGA_REG_PSEUDOCOLOR:
2104	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2105	break;
2106
2107	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2108	#ifdef IN_RING3
2109	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2110	pThis->svga.fConfigured = u32;
2111	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
2112	if (!pThis->svga.fConfigured)
2113	pThis->svga.fTraces = true;
2114	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2115	#else
2116	rc = VINF_IOM_R3_IOPORT_WRITE;
2117	#endif
2118	break;
2119
2120	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2121	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2122	if ( pThis->svga.fEnabled
2123	&& pThis->svga.fConfigured)
2124	{
2125	#if defined(IN_RING3) \|\| defined(IN_RING0)
2126	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2127	/*
2128	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2129	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2130	*/
2131	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
2132	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2133	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2134
2135	/* Kick the FIFO thread to start processing commands again. */
2136	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2137	#else
2138	rc = VINF_IOM_R3_IOPORT_WRITE;
2139	#endif
2140	}
2141	/* else nothing to do. */
2142	else
2143	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2144
2145	break;
2146
2147	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2149	break;
2150
2151	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2152	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2153	pThis->svga.u32GuestId = u32;
2154	break;
2155
2156	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2158	pThis->svga.u32PitchLock = u32;
2159	/* Should this also update the FIFO pitch lock? Unclear. */
2160	break;
2161
2162	case SVGA_REG_IRQMASK: /* Interrupt mask */
2163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2164	pThis->svga.u32IrqMask = u32;
2165
2166	/* Irq pending after the above change? */
2167	if (pThis->svga.u32IrqStatus & u32)
2168	{
2169	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2170	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2171	}
2172	else
2173	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2174	break;
2175
2176	/* Mouse cursor support */
2177	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2179	pThis->svga.uCursorID = u32;
2180	break;
2181
2182	case SVGA_REG_CURSOR_X:
2183	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2184	pThis->svga.uCursorX = u32;
2185	break;
2186
2187	case SVGA_REG_CURSOR_Y:
2188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2189	pThis->svga.uCursorY = u32;
2190	break;
2191
2192	case SVGA_REG_CURSOR_ON:
2193	#ifdef IN_RING3
2194	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2196	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2197	#else
2198	rc = VINF_IOM_R3_IOPORT_WRITE;
2199	#endif
2200	break;
2201
2202	/* Legacy multi-monitor support */
2203	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2204	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2205	break;
2206	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2207	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2208	break;
2209	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2211	break;
2212	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2214	break;
2215	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2217	break;
2218	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2220	break;
2221	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2222	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2223	break;
2224	#ifdef VBOX_WITH_VMSVGA3D
2225	/* See "Guest memory regions" below. */
2226	case SVGA_REG_GMR_ID:
2227	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2228	pThis->svga.u32CurrentGMRId = u32;
2229	break;
2230
2231	case SVGA_REG_GMR_DESCRIPTOR:
2232	# ifndef IN_RING3
2233	rc = VINF_IOM_R3_IOPORT_WRITE;
2234	break;
2235	# else /* IN_RING3 */
2236	{
2237	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2238
2239	/* Validate current GMR id. */
2240	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2241	AssertBreak(idGMR < pThis->svga.cGMR);
2242	RT_UNTRUSTED_VALIDATED_FENCE();
2243
2244	/* Free the old GMR if present. */
2245	vmsvgaR3GmrFree(pThisCC, idGMR);
2246
2247	/* Just undefine the GMR? */
2248	RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2249	if (GCPhys == 0)
2250	{
2251	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2252	break;
2253	}
2254
2255
2256	/* Never cross a page boundary automatically. */
2257	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2258	uint32_t cPagesTotal = 0;
2259	uint32_t iDesc = 0;
2260	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2261	uint32_t cLoops = 0;
2262	RTGCPHYS GCPhysBase = GCPhys;
2263	while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2264	{
2265	/* Read descriptor. */
2266	SVGAGuestMemDescriptor desc;
2267	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2268	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2269
2270	if (desc.numPages != 0)
2271	{
2272	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2273	cPagesTotal += desc.numPages;
2274	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2275
2276	if ((iDesc & 15) == 0)
2277	{
2278	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2279	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2280	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2281	}
2282
2283	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2284	paDescs[iDesc++].numPages = desc.numPages;
2285
2286	/* Continue with the next descriptor. */
2287	GCPhys += sizeof(desc);
2288	}
2289	else if (desc.ppn == 0)
2290	break; /* terminator */
2291	else /* Pointer to the next physical page of descriptors. */
2292	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2293
2294	cLoops++;
2295	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2296	}
2297
2298	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2299	if (RT_SUCCESS(rc))
2300	{
2301	/* Commit the GMR. */
2302	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2303	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2304	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2305	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2306	Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2307	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2308	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2309	}
2310	else
2311	{
2312	RTMemFree(paDescs);
2313	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2314	}
2315	break;
2316	}
2317	# endif /* IN_RING3 */
2318	#endif // VBOX_WITH_VMSVGA3D
2319
2320	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2321	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2322	if (pThis->svga.fTraces == u32)
2323	break; /* nothing to do */
2324
2325	#ifdef IN_RING3
2326	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2327	#else
2328	rc = VINF_IOM_R3_IOPORT_WRITE;
2329	#endif
2330	break;
2331
2332	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2333	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2334	break;
2335
2336	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2338	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2339	break;
2340
2341	/*
2342	* SVGA_CAP_GBOBJECTS+ registers.
2343	*/
2344	case SVGA_REG_COMMAND_LOW:
2345	{
2346	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2347	#ifdef IN_RING3
2348	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2349	pThis->svga.u32RegCommandLow = u32;
2350
2351	/* "lower 6 bits are used for the SVGACBContext" */
2352	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2353	GCPhysCB <<= 32;
2354	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2355	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2356	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2357	#else
2358	rc = VINF_IOM_R3_IOPORT_WRITE;
2359	#endif
2360	break;
2361	}
2362
2363	case SVGA_REG_COMMAND_HIGH:
2364	/* Upper 32 bits of command buffer PA. */
2365	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2366	pThis->svga.u32RegCommandHigh = u32;
2367	break;
2368
2369	case SVGA_REG_DEV_CAP:
2370	/* Write dev cap index, read value */
2371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2372	pThis->svga.u32DevCapIndex = u32;
2373	break;
2374
2375	case SVGA_REG_CMD_PREPEND_LOW:
2376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2377	/* Not supported. */
2378	break;
2379
2380	case SVGA_REG_CMD_PREPEND_HIGH:
2381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2382	/* Not supported. */
2383	break;
2384
2385	case SVGA_REG_GUEST_DRIVER_ID:
2386	if (u32 != SVGA_REG_GUEST_DRIVER_ID_SUBMIT)
2387	pThis->svga.u32GuestDriverId = u32;
2388	break;
2389
2390	case SVGA_REG_GUEST_DRIVER_VERSION1:
2391	pThis->svga.u32GuestDriverVer1 = u32;
2392	break;
2393
2394	case SVGA_REG_GUEST_DRIVER_VERSION2:
2395	pThis->svga.u32GuestDriverVer2 = u32;
2396	break;
2397
2398	case SVGA_REG_GUEST_DRIVER_VERSION3:
2399	pThis->svga.u32GuestDriverVer3 = u32;
2400	break;
2401
2402	case SVGA_REG_CURSOR_MOBID:
2403	/* Not supported, ignore. See correspondent comments in vmsvgaReadPort. */
2404	break;
2405
2406	case SVGA_REG_FB_START:
2407	case SVGA_REG_MEM_START:
2408	case SVGA_REG_HOST_BITS_PER_PIXEL:
2409	case SVGA_REG_MAX_WIDTH:
2410	case SVGA_REG_MAX_HEIGHT:
2411	case SVGA_REG_VRAM_SIZE:
2412	case SVGA_REG_FB_SIZE:
2413	case SVGA_REG_CAPABILITIES:
2414	case SVGA_REG_MEM_SIZE:
2415	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2416	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2417	case SVGA_REG_BYTES_PER_LINE:
2418	case SVGA_REG_FB_OFFSET:
2419	case SVGA_REG_RED_MASK:
2420	case SVGA_REG_GREEN_MASK:
2421	case SVGA_REG_BLUE_MASK:
2422	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2423	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2424	case SVGA_REG_GMR_MAX_IDS:
2425	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2426	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2427	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2428	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2429	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2430	case SVGA_REG_MOB_MAX_SIZE:
2431	case SVGA_REG_BLANK_SCREEN_TARGETS:
2432	case SVGA_REG_CAP2:
2433	case SVGA_REG_DEVEL_CAP:
2434	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
2435	case SVGA_REG_CURSOR_MAX_DIMENSION:
2436	case SVGA_REG_FIFO_CAPS:
2437	case SVGA_REG_FENCE:
2438	case SVGA_REG_RESERVED1:
2439	case SVGA_REG_RESERVED2:
2440	case SVGA_REG_RESERVED3:
2441	case SVGA_REG_RESERVED4:
2442	case SVGA_REG_RESERVED5:
2443	case SVGA_REG_SCREENDMA:
2444	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
2445	/* Read only - ignore. */
2446	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2447	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2448	break;
2449
2450	case SVGA_REG_IRQ_STATUS:
2451	{
2452	if (pThis->fVmSvga3)
2453	{
2454	LogFlow(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2455	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2456	/* Clear the irq in case all events have been cleared. */
2457	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2458	{
2459	Log(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2460	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2461	}
2462	}
2463	break;
2464	}
2465
2466	default:
2467	{
2468	uint32_t offReg;
2469	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2470	{
2471	RT_UNTRUSTED_VALIDATED_FENCE();
2472	pThis->svga.au32ScratchRegion[offReg] = u32;
2473	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2474	}
2475	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2476	{
2477	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2478	Btw, see rgb_to_pixel32. */
2479	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2480	u32 &= 0xff;
2481	RT_UNTRUSTED_VALIDATED_FENCE();
2482	uint32_t uRgb = pThis->last_palette[offReg / 3];
2483	switch (offReg % 3)
2484	{
2485	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2486	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2487	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2488	}
2489	pThis->last_palette[offReg / 3] = uRgb;
2490	}
2491	else
2492	{
2493	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2494	rc = VINF_IOM_R3_IOPORT_WRITE;
2495	#else
2496	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2497	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2498	#endif
2499	}
2500	break;
2501	}
2502	}
2503	return rc;
2504	}
2505
2506	/**
2507	* @callback_method_impl{FNIOMIOPORTNEWIN}
2508	*/
2509	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2510	{
2511	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2512	RT_NOREF_PV(pvUser);
2513
2514	/* Only dword accesses. */
2515	if (cb == 4)
2516	{
2517	switch (offPort)
2518	{
2519	case SVGA_INDEX_PORT:
2520	*pu32 = pThis->svga.u32IndexReg;
2521	break;
2522
2523	case SVGA_VALUE_PORT:
2524	{
2525	/* Rough index register validation. */
2526	uint32_t idxReg = pThis->svga.u32IndexReg;
2527	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2528	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2529	VINF_IOM_R3_IOPORT_READ);
2530	#else
2531	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2532	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
2533	VINF_SUCCESS);
2534	#endif
2535	RT_UNTRUSTED_VALIDATED_FENCE();
2536
2537	return vmsvgaReadPort(pDevIns, pThis, idxReg, pu32);
2538	}
2539
2540	case SVGA_BIOS_PORT:
2541	Log(("Ignoring BIOS port read\n"));
2542	*pu32 = 0;
2543	break;
2544
2545	case SVGA_IRQSTATUS_PORT:
2546	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2547	*pu32 = pThis->svga.u32IrqStatus;
2548	break;
2549
2550	default:
2551	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2552	*pu32 = UINT32_MAX;
2553	break;
2554	}
2555	}
2556	else
2557	{
2558	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2559	*pu32 = UINT32_MAX;
2560	}
2561	return VINF_SUCCESS;
2562	}
2563
2564	/**
2565	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2566	*/
2567	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2568	{
2569	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2570	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2571	RT_NOREF_PV(pvUser);
2572
2573	/* Only dword accesses. */
2574	if (cb == 4)
2575	switch (offPort)
2576	{
2577	case SVGA_INDEX_PORT:
2578	pThis->svga.u32IndexReg = u32;
2579	break;
2580
2581	case SVGA_VALUE_PORT:
2582	{
2583	/* Rough index register validation. */
2584	uint32_t idxReg = pThis->svga.u32IndexReg;
2585	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2586	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2587	VINF_IOM_R3_IOPORT_WRITE);
2588	#else
2589	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2590	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
2591	VINF_SUCCESS);
2592	#endif
2593	RT_UNTRUSTED_VALIDATED_FENCE();
2594
2595	return vmsvgaWritePort(pDevIns, pThis, pThisCC, idxReg, u32);
2596	}
2597
2598	case SVGA_BIOS_PORT:
2599	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2600	break;
2601
2602	case SVGA_IRQSTATUS_PORT:
2603	LogFlow(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2604	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2605	/* Clear the irq in case all events have been cleared. */
2606	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2607	{
2608	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2609	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2610	}
2611	break;
2612
2613	default:
2614	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2615	break;
2616	}
2617	else
2618	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2619
2620	return VINF_SUCCESS;
2621	}
2622
2623	/**
2624	* @callback_method_impl{FNIOMMMIONEWREAD}
2625	*/
2626	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
2627	{
2628	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2629	RT_NOREF_PV(pvUser);
2630
2631	/* Only dword accesses. */
2632	VBOXSTRICTRC rcStrict;
2633	if (cb == sizeof(uint32_t))
2634	{
2635	rcStrict = vmsvgaReadPort(pDevIns, pThis, (uint32_t)(off / sizeof(uint32_t)), (uint32_t *)pv);
2636	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
2637	rcStrict = VINF_IOM_R3_MMIO_READ;
2638	}
2639	else
2640	{
2641	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", off, cb));
2642	rcStrict = VINF_IOM_MMIO_UNUSED_00;
2643	}
2644	return rcStrict;
2645	}
2646
2647	/**
2648	* @callback_method_impl{FNIOMMMIONEWWRITE}
2649	*/
2650	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2651	{
2652	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2653	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2654	RT_NOREF_PV(pvUser);
2655
2656	/* Only dword accesses. */
2657	VBOXSTRICTRC rcStrict;
2658	if (cb == sizeof(uint32_t))
2659	{
2660	rcStrict = vmsvgaWritePort(pDevIns, pThis, pThisCC, (uint32_t)(off / sizeof(uint32_t)), (uint32_t )pv);
2661	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
2662	rcStrict = VINF_IOM_R3_MMIO_WRITE;
2663	}
2664	else
2665	{
2666	Log(("Ignoring non-dword write at %x cb=%d\n", off, cb));
2667	rcStrict = VINF_SUCCESS;
2668	}
2669
2670	return rcStrict;
2671	}
2672
2673	#ifdef IN_RING3
2674
2675	# ifdef DEBUG_FIFO_ACCESS
2676	/**
2677	* Handle FIFO memory access.
2678	* @returns VBox status code.
2679	* @param pVM VM handle.
2680	* @param pThis The shared VGA/VMSVGA instance data.
2681	* @param GCPhys The access physical address.
2682	* @param fWriteAccess Read or write access
2683	*/
2684	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2685	{
2686	RT_NOREF(pVM);
2687	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2688	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2689
2690	switch (GCPhysOffset >> 2)
2691	{
2692	case SVGA_FIFO_MIN:
2693	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2694	break;
2695	case SVGA_FIFO_MAX:
2696	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2697	break;
2698	case SVGA_FIFO_NEXT_CMD:
2699	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2700	break;
2701	case SVGA_FIFO_STOP:
2702	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2703	break;
2704	case SVGA_FIFO_CAPABILITIES:
2705	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2706	break;
2707	case SVGA_FIFO_FLAGS:
2708	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2709	break;
2710	case SVGA_FIFO_FENCE:
2711	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2712	break;
2713	case SVGA_FIFO_3D_HWVERSION:
2714	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2715	break;
2716	case SVGA_FIFO_PITCHLOCK:
2717	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2718	break;
2719	case SVGA_FIFO_CURSOR_ON:
2720	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2721	break;
2722	case SVGA_FIFO_CURSOR_X:
2723	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2724	break;
2725	case SVGA_FIFO_CURSOR_Y:
2726	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2727	break;
2728	case SVGA_FIFO_CURSOR_COUNT:
2729	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2730	break;
2731	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2732	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2733	break;
2734	case SVGA_FIFO_RESERVED:
2735	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2736	break;
2737	case SVGA_FIFO_CURSOR_SCREEN_ID:
2738	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2739	break;
2740	case SVGA_FIFO_DEAD:
2741	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2742	break;
2743	case SVGA_FIFO_3D_HWVERSION_REVISED:
2744	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2745	break;
2746	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2747	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2748	break;
2749	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2750	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2751	break;
2752	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2753	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2754	break;
2755	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2756	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2757	break;
2758	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2759	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2760	break;
2761	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2762	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2763	break;
2764	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2765	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2766	break;
2767	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2768	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2769	break;
2770	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2771	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2772	break;
2773	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2774	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2775	break;
2776	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2777	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2778	break;
2779	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2780	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2781	break;
2782	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2783	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2784	break;
2785	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2786	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2787	break;
2788	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2789	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2790	break;
2791	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2792	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2793	break;
2794	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2795	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2796	break;
2797	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2798	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2799	break;
2800	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2801	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2802	break;
2803	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2804	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2805	break;
2806	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2807	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2808	break;
2809	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2810	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2811	break;
2812	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2813	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2814	break;
2815	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2816	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2817	break;
2818	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2819	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2820	break;
2821	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2822	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2823	break;
2824	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2825	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2826	break;
2827	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2828	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2829	break;
2830	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2831	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2832	break;
2833	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2834	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2835	break;
2836	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2837	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2838	break;
2839	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2840	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2841	break;
2842	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2843	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2844	break;
2845	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2846	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2847	break;
2848	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2849	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2850	break;
2851	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2852	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2853	break;
2854	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2855	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2856	break;
2857	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2858	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2859	break;
2860	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2861	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2862	break;
2863	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2864	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2865	break;
2866	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2867	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2868	break;
2869	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2870	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2871	break;
2872	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2873	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2874	break;
2875	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2876	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2877	break;
2878	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2879	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2880	break;
2881	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2882	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2883	break;
2884	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2885	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2886	break;
2887	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2888	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2889	break;
2890	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2891	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2892	break;
2893	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2894	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2895	break;
2896	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2897	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2898	break;
2899	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2900	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2901	break;
2902	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2903	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2904	break;
2905	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2906	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2907	break;
2908	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2909	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2910	break;
2911	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2912	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2913	break;
2914	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2915	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2916	break;
2917	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2918	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2919	break;
2920	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2921	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2922	break;
2923	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2924	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2925	break;
2926	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2927	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2928	break;
2929	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2930	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2931	break;
2932	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2933	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2934	break;
2935	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2936	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2937	break;
2938	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2939	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2940	break;
2941	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2942	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2943	break;
2944	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2945	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2946	break;
2947	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2948	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2949	break;
2950	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2951	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2952	break;
2953	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2954	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2955	break;
2956	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2957	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2958	break;
2959	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2960	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2961	break;
2962	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2963	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2964	break;
2965	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2966	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2967	break;
2968	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2969	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2970	break;
2971	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2972	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2973	break;
2974	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2975	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2976	break;
2977	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2978	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2979	break;
2980	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2981	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2982	break;
2983	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2984	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2985	break;
2986	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2987	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2988	break;
2989	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2990	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2991	break;
2992	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2993	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2994	break;
2995	case SVGA_FIFO_3D_CAPS_LAST:
2996	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2997	break;
2998	case SVGA_FIFO_GUEST_3D_HWVERSION:
2999	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
3000	break;
3001	case SVGA_FIFO_FENCE_GOAL:
3002	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
3003	break;
3004	case SVGA_FIFO_BUSY:
3005	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
3006	break;
3007	default:
3008	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
3009	break;
3010	}
3011
3012	return VINF_EM_RAW_EMULATE_INSTR;
3013	}
3014	# endif /* DEBUG_FIFO_ACCESS */
3015
3016	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
3017	/**
3018	* HC access handler for the FIFO.
3019	*
3020	* @returns VINF_SUCCESS if the handler have carried out the operation.
3021	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3022	* @param pVM VM Handle.
3023	* @param pVCpu The cross context CPU structure for the calling EMT.
3024	* @param GCPhys The physical address the guest is writing to.
3025	* @param pvPhys The HC mapping of that address.
3026	* @param pvBuf What the guest is reading/writing.
3027	* @param cbBuf How much it's reading/writing.
3028	* @param enmAccessType The access type.
3029	* @param enmOrigin Who is making the access.
3030	* @param pvUser User argument.
3031	*/
3032	static DECLCALLBACK(VBOXSTRICTRC)
3033	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3034	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3035	{
3036	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
3037	PVGASTATE pThis = (PVGASTATE)pvUser;
3038	AssertPtr(pThis);
3039
3040	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3041	/*
3042	* Wake up the FIFO thread as it might have work to do now.
3043	*/
3044	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3045	AssertLogRelRC(rc);
3046	# endif
3047
3048	# ifdef DEBUG_FIFO_ACCESS
3049	/*
3050	* When in debug-fifo-access mode, we do not disable the access handler,
3051	* but leave it on as we wish to catch all access.
3052	*/
3053	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
3054	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
3055	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
3056	/*
3057	* Temporarily disable the access handler now that we've kicked the FIFO thread.
3058	*/
3059	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
3060	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
3061	# endif
3062	if (RT_SUCCESS(rc))
3063	return VINF_PGM_HANDLER_DO_DEFAULT;
3064	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
3065	return rc;
3066	}
3067	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
3068
3069	#endif /* IN_RING3 */
3070
3071	#ifdef DEBUG_GMR_ACCESS
3072	# ifdef IN_RING3
3073
3074	/**
3075	* HC access handler for GMRs.
3076	*
3077	* @returns VINF_SUCCESS if the handler have carried out the operation.
3078	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3079	* @param pVM VM Handle.
3080	* @param pVCpu The cross context CPU structure for the calling EMT.
3081	* @param GCPhys The physical address the guest is writing to.
3082	* @param pvPhys The HC mapping of that address.
3083	* @param pvBuf What the guest is reading/writing.
3084	* @param cbBuf How much it's reading/writing.
3085	* @param enmAccessType The access type.
3086	* @param enmOrigin Who is making the access.
3087	* @param pvUser User argument.
3088	*/
3089	static DECLCALLBACK(VBOXSTRICTRC)
3090	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3091	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3092	{
3093	PVGASTATE pThis = (PVGASTATE)pvUser;
3094	Assert(pThis);
3095	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3096	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
3097
3098	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
3099
3100	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3101	{
3102	PGMR pGMR = &pSVGAState->paGMR[i];
3103
3104	if (pGMR->numDescriptors)
3105	{
3106	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3107	{
3108	if ( GCPhys >= pGMR->paDesc[j].GCPhys
3109	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
3110	{
3111	/*
3112	* Turn off the write handler for this particular page and make it R/W.
3113	* Then return telling the caller to restart the guest instruction.
3114	*/
3115	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
3116	AssertRC(rc);
3117	return VINF_PGM_HANDLER_DO_DEFAULT;
3118	}
3119	}
3120	}
3121	}
3122
3123	return VINF_PGM_HANDLER_DO_DEFAULT;
3124	}
3125
3126	/** Callback handler for VMR3ReqCallWaitU */
3127	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3128	{
3129	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3130	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3131	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3132	int rc;
3133
3134	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3135	{
3136	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
3137	pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
3138	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
3139	AssertRC(rc);
3140	}
3141	return VINF_SUCCESS;
3142	}
3143
3144	/** Callback handler for VMR3ReqCallWaitU */
3145	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3146	{
3147	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3148	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3149	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3150
3151	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3152	{
3153	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
3154	AssertRC(rc);
3155	}
3156	return VINF_SUCCESS;
3157	}
3158
3159	/** Callback handler for VMR3ReqCallWaitU */
3160	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3161	{
3162	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3163
3164	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3165	{
3166	PGMR pGMR = &pSVGAState->paGMR[i];
3167
3168	if (pGMR->numDescriptors)
3169	{
3170	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3171	{
3172	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
3173	AssertRC(rc);
3174	}
3175	}
3176	}
3177	return VINF_SUCCESS;
3178	}
3179
3180	# endif /* IN_RING3 */
3181	#endif /* DEBUG_GMR_ACCESS */
3182
3183	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3184
3185	#ifdef IN_RING3
3186
3187
3188	/*
3189	*
3190	* Command buffer submission.
3191	*
3192	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
3193	*
3194	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
3195	* and wakes up the FIFO thread.
3196	*
3197	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
3198	* the buffer header back to the guest memory.
3199	*
3200	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
3201	*
3202	*/
3203
3204
3205	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
3206	*
3207	* @param pDevIns The device instance.
3208	* @param GCPhysCB Guest physical address of the command buffer header.
3209	* @param status Command buffer status (SVGA_CB_STATUS_*).
3210	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
3211	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
3212	* @thread FIFO or EMT.
3213	*/
3214	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
3215	{
3216	SVGACBHeader hdr;
3217	hdr.status = status;
3218	hdr.errorOffset = errorOffset;
3219	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
3220	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
3221	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
3222	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
3223	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
3224	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
3225	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
3226	}
3227
3228
3229	/** Raise an IRQ.
3230	*
3231	* @param pDevIns The device instance.
3232	* @param pThis The shared VGA/VMSVGA state.
3233	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
3234	* @thread FIFO or EMT.
3235	*/
3236	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
3237	{
3238	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
3239	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
3240
3241	if (pThis->svga.u32IrqMask & u32IrqStatus)
3242	{
3243	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
3244	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3245	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3246	}
3247
3248	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3249	}
3250
3251
3252	/** Allocate a command buffer structure.
3253	*
3254	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
3255	* @return Pointer to the allocated command buffer structure.
3256	*/
3257	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
3258	{
3259	if (!pCmdBufCtx)
3260	return NULL;
3261
3262	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
3263	if (pCmdBuf)
3264	{
3265	// RT_ZERO(pCmdBuf->nodeBuffer);
3266	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
3267	// pCmdBuf->GCPhysCB = 0;
3268	// RT_ZERO(pCmdBuf->hdr);
3269	// pCmdBuf->pvCommands = NULL;
3270	}
3271
3272	return pCmdBuf;
3273	}
3274
3275
3276	/** Free a command buffer structure.
3277	*
3278	* @param pCmdBuf The command buffer pointer.
3279	*/
3280	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3281	{
3282	if (pCmdBuf)
3283	RTMemFree(pCmdBuf->pvCommands);
3284	RTMemFree(pCmdBuf);
3285	}
3286
3287
3288	/** Initialize a command buffer context.
3289	*
3290	* @param pCmdBufCtx The command buffer context.
3291	*/
3292	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3293	{
3294	RTListInit(&pCmdBufCtx->listSubmitted);
3295	pCmdBufCtx->cSubmitted = 0;
3296	}
3297
3298
3299	/** Destroy a command buffer context.
3300	*
3301	* @param pCmdBufCtx The command buffer context pointer.
3302	*/
3303	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3304	{
3305	if (!pCmdBufCtx)
3306	return;
3307
3308	if (pCmdBufCtx->listSubmitted.pNext)
3309	{
3310	/* If the list has been initialized. */
3311	PVMSVGACMDBUF pIter, pNext;
3312	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3313	{
3314	RTListNodeRemove(&pIter->nodeBuffer);
3315	--pCmdBufCtx->cSubmitted;
3316	vmsvgaR3CmdBufFree(pIter);
3317	}
3318	}
3319	Assert(pCmdBufCtx->cSubmitted == 0);
3320	pCmdBufCtx->cSubmitted = 0;
3321	}
3322
3323
3324	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3325	*
3326	* @param pSvgaR3State VMSVGA R3 state.
3327	* @param pCmd The command data.
3328	* @return SVGACBStatus code.
3329	* @thread EMT
3330	*/
3331	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3332	{
3333	/* Create or destroy a regular command buffer context. */
3334	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3335	return SVGA_CB_STATUS_COMMAND_ERROR;
3336	RT_UNTRUSTED_VALIDATED_FENCE();
3337
3338	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3339
3340	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3341	AssertRC(rc);
3342	if (pCmd->enable)
3343	{
3344	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3345	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3346	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3347	else
3348	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3349	}
3350	else
3351	{
3352	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3353	RTMemFree(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3354	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3355	}
3356	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3357
3358	return CBStatus;
3359	}
3360
3361
3362	/** Handles SVGA_DC_CMD_PREEMPT command.
3363	*
3364	* @param pDevIns The device instance.
3365	* @param pSvgaR3State VMSVGA R3 state.
3366	* @param pCmd The command data.
3367	* @return SVGACBStatus code.
3368	* @thread EMT
3369	*/
3370	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3371	{
3372	/* Remove buffers from the processing queue of the specified context. */
3373	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3374	return SVGA_CB_STATUS_COMMAND_ERROR;
3375	RT_UNTRUSTED_VALIDATED_FENCE();
3376
3377	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3378	RTLISTANCHOR listPreempted;
3379
3380	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3381	AssertRC(rc);
3382	if (pCmd->ignoreIDZero)
3383	{
3384	RTListInit(&listPreempted);
3385
3386	PVMSVGACMDBUF pIter, pNext;
3387	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3388	{
3389	if (pIter->hdr.id == 0)
3390	continue;
3391
3392	RTListNodeRemove(&pIter->nodeBuffer);
3393	--pCmdBufCtx->cSubmitted;
3394	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3395	}
3396	}
3397	else
3398	{
3399	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3400	pCmdBufCtx->cSubmitted = 0;
3401	}
3402	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3403
3404	PVMSVGACMDBUF pIter, pNext;
3405	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3406	{
3407	RTListNodeRemove(&pIter->nodeBuffer);
3408	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3409	LogFunc(("Preempted %RX64\n", pIter->GCPhysCB));
3410	vmsvgaR3CmdBufFree(pIter);
3411	}
3412
3413	return SVGA_CB_STATUS_COMPLETED;
3414	}
3415
3416
3417	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3418	* Increments the size of the command cbCmd by a_cbMore.
3419	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3420	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3421	*/
3422	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3423	if (1) { \
3424	cbCmd += (a_cbMore); \
3425	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3426	RT_UNTRUSTED_VALIDATED_FENCE(); \
3427	} else do {} while (0)
3428
3429
3430	/** Processes Device Context command buffer.
3431	*
3432	* @param pDevIns The device instance.
3433	* @param pSvgaR3State VMSVGA R3 state.
3434	* @param pvCommands Pointer to the command buffer.
3435	* @param cbCommands Size of the command buffer.
3436	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3437	* @return SVGACBStatus code.
3438	* @thread EMT
3439	*/
3440	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3441	{
3442	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3443
3444	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3445	uint32_t cbRemain = cbCommands;
3446	while (cbRemain)
3447	{
3448	/* Command identifier is a 32 bit value. */
3449	if (cbRemain < sizeof(uint32_t))
3450	{
3451	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3452	break;
3453	}
3454
3455	/* Fetch the command id. */
3456	uint32_t const cmdId = (uint32_t )pu8Cmd;
3457	uint32_t cbCmd = sizeof(uint32_t);
3458	switch (cmdId)
3459	{
3460	case SVGA_DC_CMD_NOP:
3461	{
3462	/* NOP */
3463	break;
3464	}
3465
3466	case SVGA_DC_CMD_START_STOP_CONTEXT:
3467	{
3468	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3469	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3470	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3471	break;
3472	}
3473
3474	case SVGA_DC_CMD_PREEMPT:
3475	{
3476	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3477	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3478	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3479	break;
3480	}
3481
3482	default:
3483	{
3484	/* Unsupported command. */
3485	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3486	break;
3487	}
3488	}
3489
3490	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3491	break;
3492
3493	pu8Cmd += cbCmd;
3494	cbRemain -= cbCmd;
3495	}
3496
3497	Assert(cbRemain <= cbCommands);
3498	*poffNextCmd = cbCommands - cbRemain;
3499	return CBstatus;
3500	}
3501
3502
3503	/** Submits a device context command buffer for synchronous processing.
3504	*
3505	* @param pDevIns The device instance.
3506	* @param pThisCC The VGA/VMSVGA state for the current context.
3507	* @param ppCmdBuf Pointer to the command buffer pointer.
3508	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3509	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3510	* @return SVGACBStatus code.
3511	* @thread EMT
3512	*/
3513	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3514	{
3515	/* Synchronously process the device context commands. */
3516	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3517	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3518	}
3519
3520	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3521	*
3522	* @param pDevIns The device instance.
3523	* @param pThis The shared VGA/VMSVGA state.
3524	* @param pThisCC The VGA/VMSVGA state for the current context.
3525	* @param ppCmdBuf Pointer to the command buffer pointer.
3526	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3527	* @return SVGACBStatus code.
3528	* @thread EMT
3529	*/
3530	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3531	{
3532	/* Command buffer submission. */
3533	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3534
3535	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3536
3537	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3538	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3539
3540	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3541	AssertRC(rc);
3542
3543	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3544	{
3545	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3546	++pCmdBufCtx->cSubmitted;
3547	ppCmdBuf = NULL; / Consume the buffer. */
3548	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3549	}
3550	else
3551	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3552
3553	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3554
3555	/* Inform the FIFO thread. */
3556	if (*ppCmdBuf == NULL)
3557	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3558
3559	return CBstatus;
3560	}
3561
3562
3563	/** SVGA_REG_COMMAND_LOW write handler.
3564	* Submits a command buffer to the FIFO thread or processes a device context command.
3565	*
3566	* @param pDevIns The device instance.
3567	* @param pThis The shared VGA/VMSVGA state.
3568	* @param pThisCC The VGA/VMSVGA state for the current context.
3569	* @param GCPhysCB Guest physical address of the command buffer header.
3570	* @param CBCtx Context the command buffer is submitted to.
3571	* @thread EMT
3572	*/
3573	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3574	{
3575	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3576
3577	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3578	uint32_t offNextCmd = 0;
3579	uint32_t fIRQ = 0;
3580
3581	/* Get the context if the device has the capability. */
3582	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3583	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3584	{
3585	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3586	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3587	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3588	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3589	RT_UNTRUSTED_VALIDATED_FENCE();
3590	}
3591
3592	/* Allocate a new command buffer. */
3593	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3594	if (RT_LIKELY(pCmdBuf))
3595	{
3596	pCmdBuf->GCPhysCB = GCPhysCB;
3597
3598	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3599	if (RT_SUCCESS(rc))
3600	{
3601	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3602	pCmdBuf->hdr.status,
3603	pCmdBuf->hdr.errorOffset,
3604	pCmdBuf->hdr.id,
3605	pCmdBuf->hdr.flags,
3606	pCmdBuf->hdr.length,
3607	pCmdBuf->hdr.ptr.pa,
3608	pCmdBuf->hdr.offset,
3609	pCmdBuf->hdr.dxContext,
3610	pCmdBuf->hdr.mustBeZero[0],
3611	pCmdBuf->hdr.mustBeZero[1],
3612	pCmdBuf->hdr.mustBeZero[2],
3613	pCmdBuf->hdr.mustBeZero[3],
3614	pCmdBuf->hdr.mustBeZero[4],
3615	pCmdBuf->hdr.mustBeZero[5]));
3616
3617	/* Verify the command buffer header. */
3618	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3619	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3620	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3621	{
3622	RT_UNTRUSTED_VALIDATED_FENCE();
3623
3624	/* Read the command buffer content. */
3625	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3626	if (pCmdBuf->pvCommands)
3627	{
3628	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3629	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3630	if (RT_SUCCESS(rc))
3631	{
3632	/* Submit the buffer. Device context buffers will be processed synchronously. */
3633	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3634	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3635	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3636	else
3637	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3638	}
3639	else
3640	{
3641	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3642	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3643	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3644	}
3645	}
3646	else
3647	{
3648	/* No memory for commands. */
3649	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3650	}
3651	}
3652	else
3653	{
3654	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3655	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3656	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3657	}
3658	}
3659	else
3660	{
3661	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3662	ASSERT_GUEST_FAILED();
3663	/* Do not attempt to write the status. */
3664	}
3665
3666	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3667	vmsvgaR3CmdBufFree(pCmdBuf);
3668	}
3669	else
3670	{
3671	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3672	AssertFailed();
3673	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3674	}
3675
3676	if (CBstatus != SVGA_CB_STATUS_NONE)
3677	{
3678	LogFunc(("Write status %#x, offNextCmd %#x, fIRQ %#x\n", CBstatus, offNextCmd, fIRQ));
3679	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3680	if (fIRQ)
3681	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3682	}
3683	}
3684
3685
3686	/** Checks if there are some buffers to be processed.
3687	*
3688	* @param pThisCC The VGA/VMSVGA state for the current context.
3689	* @return true if buffers must be processed.
3690	* @thread FIFO
3691	*/
3692	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3693	{
3694	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3695	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3696	}
3697
3698
3699	/** Processes a command buffer.
3700	*
3701	* @param pDevIns The device instance.
3702	* @param pThis The shared VGA/VMSVGA state.
3703	* @param pThisCC The VGA/VMSVGA state for the current context.
3704	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3705	* @param pvCommands Pointer to the command buffer.
3706	* @param cbCommands Size of the command buffer.
3707	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3708	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3709	* @return SVGACBStatus code.
3710	* @thread FIFO
3711	*/
3712	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3713	{
3714	# ifndef VBOX_WITH_VMSVGA3D
3715	RT_NOREF(idDXContext);
3716	# endif
3717	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3718	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3719
3720	# ifdef VBOX_WITH_VMSVGA3D
3721	# ifdef VMSVGA3D_DX
3722	/* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3723	if (idDXContext != SVGA3D_INVALID_ID)
3724	{
3725	if (pSvgaR3State->idDXContextCurrent != idDXContext)
3726	{
3727	LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3728	vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3729	pSvgaR3State->idDXContextCurrent = idDXContext;
3730	}
3731	}
3732	# endif
3733	# endif
3734
3735	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3736
3737	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3738	uint32_t cbRemain = cbCommands;
3739	while (cbRemain)
3740	{
3741	/* Command identifier is a 32 bit value. */
3742	if (cbRemain < sizeof(uint32_t))
3743	{
3744	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3745	break;
3746	}
3747
3748	/* Fetch the command id.
3749	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3750	* warning. Because we support some obsolete and deprecated commands, which are not included in
3751	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3752	*/
3753	uint32_t const cmdId = (uint32_t )pu8Cmd;
3754	uint32_t cbCmd = sizeof(uint32_t);
3755
3756	LogFlowFunc(("[cid=%d] %s %u\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3757	# ifdef LOG_ENABLED
3758	# ifdef VBOX_WITH_VMSVGA3D
3759	if ( (cmdId >= SVGA_3D_CMD_BASE && cmdId < SVGA_3D_CMD_MAX)
3760	\|\| (cmdId >= VBSVGA_3D_CMD_BASE && cmdId < VBSVGA_3D_CMD_MAX))
3761	{
3762	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3763	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3764	}
3765	else if (cmdId == SVGA_CMD_FENCE)
3766	{
3767	Log7(("\tSVGA_CMD_FENCE\n"));
3768	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3769	}
3770	# endif
3771	# endif
3772
3773	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3774	* I.e. pu8Cmd + cbCmd must point to the next command.
3775	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3776	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3777	*/
3778	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3779	switch (cmdId)
3780	{
3781	case SVGA_CMD_INVALID_CMD:
3782	{
3783	/* Nothing to do. */
3784	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3785	break;
3786	}
3787
3788	case SVGA_CMD_FENCE:
3789	{
3790	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3791	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3792	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3793	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3794
3795	if (pThis->fVmSvga3)
3796	{
3797	pThis->svga.u32FenceLast = pCmd->fence;
3798
3799	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3800	{
3801	Log(("any fence irq\n"));
3802	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3803	}
3804	else if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3805	{
3806	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3807	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3808	}
3809	}
3810	else
3811	{
3812	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3813	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3814	{
3815	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3816
3817	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3818	{
3819	Log(("any fence irq\n"));
3820	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3821	}
3822	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3823	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3824	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3825	{
3826	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3827	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3828	}
3829	}
3830	else
3831	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3832	}
3833	break;
3834	}
3835
3836	case SVGA_CMD_UPDATE:
3837	{
3838	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3839	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3840	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3841	break;
3842	}
3843
3844	case SVGA_CMD_UPDATE_VERBOSE:
3845	{
3846	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3847	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3848	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3849	break;
3850	}
3851
3852	case SVGA_CMD_DEFINE_CURSOR:
3853	{
3854	/* Followed by bitmap data. */
3855	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3856	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3857
3858	/* Figure out the size of the bitmap data. */
3859	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3860	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3861	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3862	RT_UNTRUSTED_VALIDATED_FENCE();
3863
3864	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3865	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3866	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3867	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3868
3869	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3870	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3871	break;
3872	}
3873
3874	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3875	{
3876	/* Followed by bitmap data. */
3877	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3878	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3879
3880	/* Figure out the size of the bitmap data. */
3881	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3882
3883	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3884	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3885	break;
3886	}
3887
3888	case SVGA_CMD_MOVE_CURSOR:
3889	{
3890	/* Deprecated; there should be no driver which requires this command. However, if
3891	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3892	* alignment.
3893	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3894	*/
3895	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3896	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3897	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3898	break;
3899	}
3900
3901	case SVGA_CMD_DISPLAY_CURSOR:
3902	{
3903	/* Deprecated; there should be no driver which requires this command. However, if
3904	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3905	* alignment.
3906	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3907	*/
3908	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3909	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3910	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3911	break;
3912	}
3913
3914	case SVGA_CMD_RECT_FILL:
3915	{
3916	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3917	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3918	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3919	break;
3920	}
3921
3922	case SVGA_CMD_RECT_COPY:
3923	{
3924	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3925	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3926	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3927	break;
3928	}
3929
3930	case SVGA_CMD_RECT_ROP_COPY:
3931	{
3932	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3933	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3934	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3935	break;
3936	}
3937
3938	case SVGA_CMD_ESCAPE:
3939	{
3940	/* Followed by 'size' bytes of data. */
3941	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3942	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3943
3944	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3945	RT_UNTRUSTED_VALIDATED_FENCE();
3946
3947	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3948	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3949	break;
3950	}
3951	# ifdef VBOX_WITH_VMSVGA3D
3952	case SVGA_CMD_DEFINE_GMR2:
3953	{
3954	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3955	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3956	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3957	break;
3958	}
3959
3960	case SVGA_CMD_REMAP_GMR2:
3961	{
3962	/* Followed by page descriptors or guest ptr. */
3963	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3964	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3965
3966	/* Calculate the size of what comes after next and fetch it. */
3967	uint32_t cbMore = 0;
3968	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3969	cbMore = sizeof(SVGAGuestPtr);
3970	else
3971	{
3972	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3973	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3974	{
3975	cbMore = cbPageDesc;
3976	pCmd->numPages = 1;
3977	}
3978	else
3979	{
3980	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3981	cbMore = cbPageDesc * pCmd->numPages;
3982	}
3983	}
3984	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3985	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3986	# ifdef DEBUG_GMR_ACCESS
3987	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3988	# endif
3989	break;
3990	}
3991	# endif /* VBOX_WITH_VMSVGA3D */
3992	case SVGA_CMD_DEFINE_SCREEN:
3993	{
3994	/* The size of this command is specified by the guest and depends on capabilities. */
3995	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3996	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3997	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3998	RT_UNTRUSTED_VALIDATED_FENCE();
3999
4000	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
4001	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4002	break;
4003	}
4004
4005	case SVGA_CMD_DESTROY_SCREEN:
4006	{
4007	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
4008	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4009	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4010	break;
4011	}
4012
4013	case SVGA_CMD_DEFINE_GMRFB:
4014	{
4015	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
4016	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4017	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4018	break;
4019	}
4020
4021	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4022	{
4023	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
4024	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4025	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4026	break;
4027	}
4028
4029	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4030	{
4031	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
4032	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4033	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4034	break;
4035	}
4036
4037	case SVGA_CMD_ANNOTATION_FILL:
4038	{
4039	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
4040	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4041	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4042	break;
4043	}
4044
4045	case SVGA_CMD_ANNOTATION_COPY:
4046	{
4047	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
4048	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4049	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4050	break;
4051	}
4052
4053	default:
4054	{
4055	# ifdef VBOX_WITH_VMSVGA3D
4056	if ( (cmdId >= SVGA_3D_CMD_BASE && cmdId < SVGA_3D_CMD_MAX)
4057	\|\| ( pThis->svga.fVBoxExtensions
4058	&& (cmdId >= VBSVGA_3D_CMD_BASE && cmdId < VBSVGA_3D_CMD_MAX)))
4059	{
4060	RT_UNTRUSTED_VALIDATED_FENCE();
4061
4062	/* All 3d commands start with a common header, which defines the identifier and the size
4063	* of the command. The identifier has been already read. Fetch the size.
4064	*/
4065	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
4066	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
4067	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
4068	if (RT_LIKELY(pThis->svga.f3DEnabled))
4069	{ /* likely */ }
4070	else
4071	{
4072	if (pThis->svga.fVMSVGA2dGBO &&
4073	(cmdId == SVGA_3D_CMD_SET_OTABLE_BASE64 \|\|
4074	cmdId == SVGA_3D_CMD_DEFINE_GB_MOB64 \|\|
4075	cmdId == SVGA_3D_CMD_DESTROY_GB_MOB \|\|
4076	cmdId == SVGA_3D_CMD_DEFINE_GB_SURFACE \|\|
4077	cmdId == SVGA_3D_CMD_DESTROY_GB_SURFACE \|\|
4078	cmdId == SVGA_3D_CMD_BIND_GB_SURFACE \|\|
4079	cmdId == SVGA_3D_CMD_INVALIDATE_GB_SURFACE \|\|
4080	cmdId == SVGA_3D_CMD_DEFINE_GB_SCREENTARGET \|\|
4081	cmdId == SVGA_3D_CMD_DESTROY_GB_SCREENTARGET \|\|
4082	cmdId == SVGA_3D_CMD_BIND_GB_SCREENTARGET \|\|
4083	cmdId == SVGA_3D_CMD_UPDATE_GB_IMAGE \|\|
4084	cmdId == SVGA_3D_CMD_UPDATE_GB_SCREENTARGET \|\|
4085	cmdId == SVGA_3D_CMD_SURFACE_COPY)
4086	)
4087	{
4088	LogRelMax(8, ("VMSVGA: 3D disabled, but command %d will be processed\n", cmdId));
4089	}
4090	else
4091	{
4092	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
4093	break;
4094	}
4095	}
4096
4097	/* Command data begins after the 32 bit command length. */
4098	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
4099	if (RT_SUCCESS(rc))
4100	{ /* likely */ }
4101	else
4102	{
4103	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4104	break;
4105	}
4106	}
4107	else
4108	# endif /* VBOX_WITH_VMSVGA3D */
4109	{
4110	/* Unsupported command. */
4111	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
4112	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
4113	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
4114	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4115	break;
4116	}
4117	}
4118	}
4119
4120	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
4121	break;
4122
4123	pu8Cmd += cbCmd;
4124	cbRemain -= cbCmd;
4125
4126	/* If this is not the last command in the buffer, then generate IRQ, if required.
4127	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
4128	* in the buffer (usually the case).
4129	*/
4130	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
4131	{ /* likely */ }
4132	else
4133	{
4134	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
4135	*pu32IrqStatus = 0;
4136	}
4137	}
4138
4139	Assert(cbRemain <= cbCommands);
4140	*poffNextCmd = cbCommands - cbRemain;
4141	return CBstatus;
4142	}
4143
4144
4145	/** Process command buffers.
4146	*
4147	* @param pDevIns The device instance.
4148	* @param pThis The shared VGA/VMSVGA state.
4149	* @param pThisCC The VGA/VMSVGA state for the current context.
4150	* @param pThread Handle of the FIFO thread.
4151	* @thread FIFO
4152	*/
4153	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
4154	{
4155	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4156
4157	for (;;)
4158	{
4159	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4160	break;
4161
4162	/* See if there is a submitted buffer. */
4163	PVMSVGACMDBUF pCmdBuf = NULL;
4164
4165	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4166	AssertRC(rc);
4167
4168	/* It seems that a higher queue index has a higher priority.
4169	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
4170	*/
4171	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
4172	{
4173	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
4174	if (pCmdBufCtx)
4175	{
4176	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
4177	if (pCmdBuf)
4178	{
4179	Assert(pCmdBufCtx->cSubmitted > 0);
4180	--pCmdBufCtx->cSubmitted;
4181	break;
4182	}
4183	}
4184	}
4185
4186	if (!pCmdBuf)
4187	{
4188	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
4189	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4190	break;
4191	}
4192
4193	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4194
4195	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4196	uint32_t offNextCmd = 0;
4197	uint32_t u32IrqStatus = 0;
4198	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
4199	? pCmdBuf->hdr.dxContext
4200	: SVGA3D_INVALID_ID;
4201	/* Process one buffer. */
4202	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
4203
4204	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
4205	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
4206	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
4207	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
4208
4209	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
4210	if (u32IrqStatus)
4211	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
4212
4213	vmsvgaR3CmdBufFree(pCmdBuf);
4214	}
4215	}
4216
4217
4218	/**
4219	* Worker for vmsvgaR3FifoThread that handles an external command.
4220	*
4221	* @param pDevIns The device instance.
4222	* @param pThis The shared VGA/VMSVGA instance data.
4223	* @param pThisCC The VGA/VMSVGA state for ring-3.
4224	*/
4225	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4226	{
4227	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
4228	switch (pThis->svga.u8FIFOExtCommand)
4229	{
4230	case VMSVGA_FIFO_EXTCMD_RESET:
4231	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
4232	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4233
4234	vmsvgaR3ResetScreens(pThis, pThisCC);
4235	# ifdef VBOX_WITH_VMSVGA3D
4236	/* The 3d subsystem must be reset from the fifo thread. */
4237	if (pThis->svga.f3DEnabled)
4238	vmsvga3dReset(pThisCC);
4239	# endif
4240	vmsvgaR3ResetSvgaState(pThis, pThisCC);
4241	break;
4242
4243	case VMSVGA_FIFO_EXTCMD_POWEROFF:
4244	Log(("vmsvgaR3FifoLoop: power off.\n"));
4245	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4246
4247	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
4248	vmsvgaR3ResetScreens(pThis, pThisCC);
4249	break;
4250
4251	case VMSVGA_FIFO_EXTCMD_TERMINATE:
4252	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
4253	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4254
4255	# ifdef VBOX_WITH_VMSVGA3D
4256	/* The 3d subsystem must be shut down from the fifo thread. */
4257	if (pThis->svga.f3DEnabled)
4258	vmsvga3dTerminate(pThisCC);
4259	# endif
4260	vmsvgaR3TerminateSvgaState(pThis, pThisCC);
4261	break;
4262
4263	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
4264	{
4265	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
4266	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
4267	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
4268	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
4269	# ifdef VBOX_WITH_VMSVGA3D
4270	if (pThis->svga.f3DEnabled)
4271	{
4272	if (vmsvga3dIsLegacyBackend(pThisCC))
4273	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
4274	# ifdef VMSVGA3D_DX
4275	else
4276	vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
4277	# endif
4278	}
4279	# endif
4280	break;
4281	}
4282
4283	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
4284	{
4285	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
4286	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
4287	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
4288	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4289	# ifdef VBOX_WITH_VMSVGA3D
4290	if (pThis->svga.f3DEnabled)
4291	{
4292	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
4293	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
4294	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
4295	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
4296	# endif
4297
4298	if (vmsvga3dIsLegacyBackend(pThisCC))
4299	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4300	# ifdef VMSVGA3D_DX
4301	else
4302	vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4303	# endif
4304	}
4305	# endif
4306	break;
4307	}
4308
4309	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4310	{
4311	# ifdef VBOX_WITH_VMSVGA3D
4312	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4313	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4314	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4315	# endif
4316	break;
4317	}
4318
4319
4320	default:
4321	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4322	break;
4323	}
4324
4325	/*
4326	* Signal the end of the external command.
4327	*/
4328	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4329	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4330	ASMMemoryFence(); /* paranoia^2 */
4331	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4332	AssertLogRelRC(rc);
4333	}
4334
4335	/**
4336	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4337	* doing a job on the FIFO thread (even when it's officially suspended).
4338	*
4339	* @returns VBox status code (fully asserted).
4340	* @param pDevIns The device instance.
4341	* @param pThis The shared VGA/VMSVGA instance data.
4342	* @param pThisCC The VGA/VMSVGA state for ring-3.
4343	* @param uExtCmd The command to execute on the FIFO thread.
4344	* @param pvParam Pointer to command parameters.
4345	* @param cMsWait The time to wait for the command, given in
4346	* milliseconds.
4347	*/
4348	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4349	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4350	{
4351	Assert(cMsWait >= RT_MS_1SEC * 5);
4352	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4353	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4354
4355	int rc;
4356	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4357	PDMTHREADSTATE enmState = pThread->enmState;
4358	if (enmState == PDMTHREADSTATE_SUSPENDED)
4359	{
4360	/*
4361	* The thread is suspended, we have to temporarily wake it up so it can
4362	* perform the task.
4363	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4364	*/
4365	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4366	/* Post the request. */
4367	pThis->svga.fFifoExtCommandWakeup = true;
4368	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4369	pThis->svga.u8FIFOExtCommand = uExtCmd;
4370	ASMMemoryFence(); /* paranoia^3 */
4371
4372	/* Resume the thread. */
4373	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4374	AssertLogRelRC(rc);
4375	if (RT_SUCCESS(rc))
4376	{
4377	/* Wait. Take care in case the semaphore was already posted (same as below). */
4378	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4379	if ( rc == VINF_SUCCESS
4380	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4381	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4382	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4383	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4384
4385	/* suspend the thread */
4386	pThis->svga.fFifoExtCommandWakeup = false;
4387	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4388	AssertLogRelRC(rc2);
4389	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4390	rc = rc2;
4391	}
4392	pThis->svga.fFifoExtCommandWakeup = false;
4393	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4394	}
4395	else if (enmState == PDMTHREADSTATE_RUNNING)
4396	{
4397	/*
4398	* The thread is running, should only happen during reset and vmsvga3dsfc.
4399	* We ASSUME not racing code here, both wrt thread state and ext commands.
4400	*/
4401	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4402	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4403
4404	/* Post the request. */
4405	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4406	pThis->svga.u8FIFOExtCommand = uExtCmd;
4407	ASMMemoryFence(); /* paranoia^2 */
4408	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4409	AssertLogRelRC(rc);
4410
4411	/* Wait. Take care in case the semaphore was already posted (same as above). */
4412	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4413	if ( rc == VINF_SUCCESS
4414	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4415	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4416	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4417	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4418
4419	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4420	}
4421	else
4422	{
4423	/*
4424	* Something is wrong with the thread!
4425	*/
4426	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4427	rc = VERR_INVALID_STATE;
4428	}
4429	return rc;
4430	}
4431
4432
4433	/**
4434	* Marks the FIFO non-busy, notifying any waiting EMTs.
4435	*
4436	* @param pDevIns The device instance.
4437	* @param pThis The shared VGA/VMSVGA instance data.
4438	* @param pThisCC The VGA/VMSVGA state for ring-3.
4439	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4440	* @param offFifoMin The start byte offset of the command FIFO.
4441	*/
4442	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4443	{
4444	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4445	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4446	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4447
4448	/* Wake up any waiting EMTs. */
4449	if (pSVGAState->cBusyDelayedEmts > 0)
4450	{
4451	# ifdef VMSVGA_USE_EMT_HALT_CODE
4452	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4453	if (idCpu != NIL_VMCPUID)
4454	{
4455	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4456	while (idCpu-- > 0)
4457	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4458	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4459	}
4460	# else
4461	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4462	AssertRC(rc2);
4463	# endif
4464	}
4465	}
4466
4467	/**
4468	* Reads (more) payload into the command buffer.
4469	*
4470	* @returns pbBounceBuf on success
4471	* @retval (void *)1 if the thread was requested to stop.
4472	* @retval NULL on FIFO error.
4473	*
4474	* @param cbPayloadReq The number of bytes of payload requested.
4475	* @param pFIFO The FIFO.
4476	* @param offCurrentCmd The FIFO byte offset of the current command.
4477	* @param offFifoMin The start byte offset of the command FIFO.
4478	* @param offFifoMax The end byte offset of the command FIFO.
4479	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4480	* always sufficient size.
4481	* @param pcbAlreadyRead How much payload we've already read into the bounce
4482	* buffer. (We will NEVER re-read anything.)
4483	* @param pThread The calling PDM thread handle.
4484	* @param pThis The shared VGA/VMSVGA instance data.
4485	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4486	* statistics collection.
4487	* @param pDevIns The device instance.
4488	*/
4489	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4490	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4491	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4492	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4493	{
4494	Assert(pbBounceBuf);
4495	Assert(pcbAlreadyRead);
4496	Assert(offFifoMin < offFifoMax);
4497	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4498	Assert(offFifoMax <= pThis->svga.cbFIFO);
4499
4500	/*
4501	* Check if the requested payload size has already been satisfied .
4502	* .
4503	* When called to read more, the caller is responsible for making sure the .
4504	* new command size (cbRequsted) never is smaller than what has already .
4505	* been read.
4506	*/
4507	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4508	if (cbPayloadReq <= cbAlreadyRead)
4509	{
4510	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4511	return pbBounceBuf;
4512	}
4513
4514	/*
4515	* Commands bigger than the fifo buffer are invalid.
4516	*/
4517	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4518	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4520	NULL);
4521
4522	/*
4523	* Move offCurrentCmd past the command dword.
4524	*/
4525	offCurrentCmd += sizeof(uint32_t);
4526	if (offCurrentCmd >= offFifoMax)
4527	offCurrentCmd = offFifoMin;
4528
4529	/*
4530	* Do we have sufficient payload data available already?
4531	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4532	*/
4533	uint32_t cbAfter, cbBefore;
4534	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4535	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4536	if (offNextCmd >= offCurrentCmd)
4537	{
4538	if (RT_LIKELY(offNextCmd < offFifoMax))
4539	cbAfter = offNextCmd - offCurrentCmd;
4540	else
4541	{
4542	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4543	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4544	offNextCmd, offFifoMin, offFifoMax));
4545	cbAfter = offFifoMax - offCurrentCmd;
4546	}
4547	cbBefore = 0;
4548	}
4549	else
4550	{
4551	cbAfter = offFifoMax - offCurrentCmd;
4552	if (offNextCmd >= offFifoMin)
4553	cbBefore = offNextCmd - offFifoMin;
4554	else
4555	{
4556	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4557	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4558	offNextCmd, offFifoMin, offFifoMax));
4559	cbBefore = 0;
4560	}
4561	}
4562	if (cbAfter + cbBefore < cbPayloadReq)
4563	{
4564	/*
4565	* Insufficient, must wait for it to arrive.
4566	*/
4567	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4568	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4569	for (uint32_t i = 0;; i++)
4570	{
4571	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4572	{
4573	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4574	return (void *)(uintptr_t)1;
4575	}
4576	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4577	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4578
4579	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4580
4581	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4582	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4583	if (offNextCmd >= offCurrentCmd)
4584	{
4585	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4586	cbBefore = 0;
4587	}
4588	else
4589	{
4590	cbAfter = offFifoMax - offCurrentCmd;
4591	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4592	}
4593
4594	if (cbAfter + cbBefore >= cbPayloadReq)
4595	break;
4596	}
4597	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4598	}
4599
4600	/*
4601	* Copy out the memory and update what pcbAlreadyRead points to.
4602	*/
4603	if (cbAfter >= cbPayloadReq)
4604	memcpy(pbBounceBuf + cbAlreadyRead,
4605	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4606	cbPayloadReq - cbAlreadyRead);
4607	else
4608	{
4609	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4610	if (cbAlreadyRead < cbAfter)
4611	{
4612	memcpy(pbBounceBuf + cbAlreadyRead,
4613	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4614	cbAfter - cbAlreadyRead);
4615	cbAlreadyRead = cbAfter;
4616	}
4617	memcpy(pbBounceBuf + cbAlreadyRead,
4618	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4619	cbPayloadReq - cbAlreadyRead);
4620	}
4621	*pcbAlreadyRead = cbPayloadReq;
4622	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4623	return pbBounceBuf;
4624	}
4625
4626
4627	/**
4628	* Sends cursor position and visibility information from the FIFO to the front-end.
4629	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4630	*/
4631	static uint32_t
4632	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4633	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4634	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4635	{
4636	/*
4637	* Check if the cursor update counter has changed and try get a stable
4638	* set of values if it has. This is race-prone, especially consindering
4639	* the screen ID, but little we can do about that.
4640	*/
4641	uint32_t x, y, fVisible, idScreen;
4642	for (uint32_t i = 0; ; i++)
4643	{
4644	x = pFIFO[SVGA_FIFO_CURSOR_X];
4645	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4646	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4647	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4648	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4649	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4650	\|\| i > 3)
4651	break;
4652	if (i == 0)
4653	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4654	ASMNopPause();
4655	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4656	}
4657
4658	/*
4659	* Check if anything has changed, as calling into pDrv is not light-weight.
4660	*/
4661	if ( *pxLast == x
4662	&& *pyLast == y
4663	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4664	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4665	else
4666	{
4667	/*
4668	* Detected changes.
4669	*
4670	* We handle global, not per-screen visibility information by sending
4671	* pfnVBVAMousePointerShape without shape data.
4672	*/
4673	*pxLast = x;
4674	*pyLast = y;
4675	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4676	if (idScreen != SVGA_ID_INVALID)
4677	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4678	else if (*pfLastVisible != fVisible)
4679	{
4680	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4681	*pfLastVisible = fVisible;
4682	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4683	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4684	}
4685	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4686	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4687	}
4688
4689	/*
4690	* Update done. Signal this to the guest.
4691	*/
4692	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4693
4694	return uCursorUpdateCount;
4695	}
4696
4697
4698	/**
4699	* Checks if there is work to be done, either cursor updating or FIFO commands.
4700	*
4701	* @returns true if pending work, false if not.
4702	* @param pThisCC The VGA/VMSVGA state for ring-3.
4703	* @param uLastCursorCount The last cursor update counter value.
4704	*/
4705	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4706	{
4707	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4708	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4709	AssertReturn(pFIFO, false);
4710
4711	if (vmsvgaR3CmdBufHasWork(pThisCC))
4712	return true;
4713
4714	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4715	return true;
4716
4717	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4718	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4719	return true;
4720
4721	return false;
4722	}
4723
4724
4725	/**
4726	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4727	*
4728	* @param pDevIns The device instance.
4729	* @param pThis The shared VGA/VMSVGA instance data.
4730	* @param pThisCC The VGA/VMSVGA state for ring-3.
4731	*/
4732	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4733	{
4734	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4735	to recheck it before doing the signalling. */
4736	if ( (pThis->fVmSvga3 \|\| vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount)))
4737	&& pThis->svga.fFIFOThreadSleeping
4738	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4739	{
4740	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4741	AssertRC(rc);
4742	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4743	}
4744	}
4745
4746
4747	/**
4748	* Called by the FIFO thread to process pending actions.
4749	*
4750	* @param pDevIns The device instance.
4751	* @param pThis The shared VGA/VMSVGA instance data.
4752	* @param pThisCC The VGA/VMSVGA state for ring-3.
4753	*/
4754	static void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4755	{
4756	RT_NOREF(pDevIns);
4757
4758	/* Currently just mode changes. */
4759	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4760	{
4761	vmsvgaR3ChangeMode(pThis, pThisCC);
4762	# ifdef VBOX_WITH_VMSVGA3D
4763	if (pThisCC->svga.p3dState != NULL)
4764	vmsvga3dChangeMode(pThisCC);
4765	# endif
4766	}
4767	}
4768
4769
4770	/*
4771	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4772	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4773	*/
4774	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4775	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4776	*
4777	* Will break out of the switch on failure.
4778	* Will restart and quit the loop if the thread was requested to stop.
4779	*
4780	* @param a_PtrVar Request variable pointer.
4781	* @param a_Type Request typedef (not pointer) for casting.
4782	* @param a_cbPayloadReq How much payload to fetch.
4783	* @remarks Accesses a bunch of variables in the current scope!
4784	*/
4785	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4786	if (1) { \
4787	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4788	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4789	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4790	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4791	} else do {} while (0)
4792	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4793	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4794	* buffer after figuring out the actual command size.
4795	*
4796	* Will break out of the switch on failure.
4797	*
4798	* @param a_PtrVar Request variable pointer.
4799	* @param a_Type Request typedef (not pointer) for casting.
4800	* @param a_cbPayloadReq How much payload to fetch.
4801	* @remarks Accesses a bunch of variables in the current scope!
4802	*/
4803	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4804	if (1) { \
4805	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4806	} else do {} while (0)
4807
4808	/**
4809	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4810	*/
4811	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4812	{
4813	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4814	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4815	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4816	int rc;
4817
4818	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4819	return VINF_SUCCESS;
4820
4821	/*
4822	* Special mode where we only execute an external command and the go back
4823	* to being suspended. Currently, all ext cmds ends up here, with the reset
4824	* one also being eligble for runtime execution further down as well.
4825	*/
4826	if (pThis->svga.fFifoExtCommandWakeup)
4827	{
4828	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4829	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4830	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4831	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4832	else
4833	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4834	return VINF_SUCCESS;
4835	}
4836
4837
4838	/*
4839	* Signal the semaphore to make sure we don't wait for 250ms after a
4840	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4841	*/
4842	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4843
4844	/*
4845	* Allocate a bounce buffer for command we get from the FIFO.
4846	* (All code must return via the end of the function to free this buffer.)
4847	*/
4848	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4849	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4850
4851	/*
4852	* Polling/sleep interval config.
4853	*
4854	* We wait for an a short interval if the guest has recently given us work
4855	* to do, but the interval increases the longer we're kept idle. Once we've
4856	* reached the refresh timer interval, we'll switch to extended waits,
4857	* depending on it or the guest to kick us into action when needed.
4858	*
4859	* Should the refresh time go fishing, we'll just continue increasing the
4860	* sleep length till we reaches the 250 ms max after about 16 seconds.
4861	*/
4862	RTMSINTERVAL const cMsMinSleep = 16;
4863	RTMSINTERVAL const cMsIncSleep = 2;
4864	RTMSINTERVAL const cMsMaxSleep = 250;
4865	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4866	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4867
4868	/*
4869	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4870	*
4871	* Initialize with values that will detect an update from the guest.
4872	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4873	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4874	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4875	*/
4876	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4877	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4878	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4879	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4880	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4881
4882	/*
4883	* The FIFO loop.
4884	*/
4885	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4886	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4887	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4888	{
4889	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4890	/*
4891	* Should service the run loop every so often.
4892	*/
4893	if (pThis->svga.f3DEnabled)
4894	vmsvga3dCocoaServiceRunLoop();
4895	# endif
4896
4897	/* First check any pending actions. */
4898	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4899
4900	/*
4901	* Unless there's already work pending, go to sleep for a short while.
4902	* (See polling/sleep interval config above.)
4903	*/
4904	if ( fBadOrDisabledFifo
4905	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4906	{
4907	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4908	Assert(pThis->cMilliesRefreshInterval > 0);
4909	if (cMsSleep < pThis->cMilliesRefreshInterval)
4910	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4911	else
4912	{
4913	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4914	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4915	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4916	# endif
4917	if ( !fBadOrDisabledFifo
4918	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4919	rc = VINF_SUCCESS;
4920	else
4921	{
4922	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4923	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4924	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4925	}
4926	}
4927	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4928	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4929	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4930	{
4931	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4932	break;
4933	}
4934	}
4935	else
4936	rc = VINF_SUCCESS;
4937	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4938	if (rc == VERR_TIMEOUT)
4939	{
4940	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4941	{
4942	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4943	continue;
4944	}
4945	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4946
4947	Log(("vmsvgaR3FifoLoop: timeout\n"));
4948	}
4949	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4950	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4951	cMsSleep = cMsMinSleep;
4952
4953	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4954	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4955	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4956
4957	/*
4958	* Handle external commands (currently only reset).
4959	*/
4960	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4961	{
4962	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4963	continue;
4964	}
4965
4966	/*
4967	* If guest misbehaves, then do nothing.
4968	*/
4969	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4970	{
4971	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4972	cMsSleep = cMsExtendedSleep;
4973	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4974	continue;
4975	}
4976
4977	/*
4978	* The device must be enabled and configured.
4979	*/
4980	if ( !pThis->svga.fEnabled
4981	\|\| !pThis->svga.fConfigured)
4982	{
4983	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4984	fBadOrDisabledFifo = true;
4985	cMsSleep = cMsMaxSleep; /* cheat */
4986	continue;
4987	}
4988
4989	/*
4990	* Get and check the min/max values. We ASSUME that they will remain
4991	* unchanged while we process requests. A further ASSUMPTION is that
4992	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4993	* we don't read it back while in the loop.
4994	*/
4995	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4996	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4997	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4998	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4999	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
5000	\|\| offFifoMax <= offFifoMin
5001	\|\| offFifoMax > pThis->svga.cbFIFO
5002	\|\| (offFifoMax & 3) != 0
5003	\|\| (offFifoMin & 3) != 0
5004	\|\| offCurrentCmd < offFifoMin
5005	\|\| offCurrentCmd > offFifoMax))
5006	{
5007	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
5008	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
5009	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5010	fBadOrDisabledFifo = true;
5011	continue;
5012	}
5013	RT_UNTRUSTED_VALIDATED_FENCE();
5014	if (RT_UNLIKELY(offCurrentCmd & 3))
5015	{
5016	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
5017	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
5018	offCurrentCmd &= ~UINT32_C(3);
5019	}
5020
5021	/*
5022	* Update the cursor position before we start on the FIFO commands.
5023	*/
5024	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
5025	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
5026	{
5027	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
5028	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
5029	{ /* halfways likely */ }
5030	else
5031	{
5032	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
5033	&xLastCursor, &yLastCursor, &fLastCursorVisible);
5034	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
5035	}
5036	}
5037
5038	/*
5039	* Mark the FIFO as busy.
5040	*/
5041	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
5042	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
5043	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
5044
5045	/*
5046	* Process all submitted command buffers.
5047	*/
5048	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
5049
5050	/*
5051	* Execute all queued FIFO commands.
5052	* Quit if pending external command or changes in the thread state.
5053	*/
5054	bool fDone = false;
5055	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
5056	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
5057	{
5058	uint32_t cbPayload = 0;
5059	uint32_t u32IrqStatus = 0;
5060
5061	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
5062
5063	/* First check any pending actions. */
5064	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
5065
5066	/* Check for pending external commands (reset). */
5067	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
5068	break;
5069
5070	/*
5071	* Process the command.
5072	*/
5073	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
5074	* warning. Because we implement some obsolete and deprecated commands, which are not included in
5075	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
5076	*/
5077	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
5078	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
5079	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
5080	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
5081	switch (enmCmdId)
5082	{
5083	case SVGA_CMD_INVALID_CMD:
5084	/* Nothing to do. */
5085	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
5086	break;
5087
5088	case SVGA_CMD_FENCE:
5089	{
5090	SVGAFifoCmdFence *pCmdFence;
5091	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
5092	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
5093	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
5094	{
5095	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
5096	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
5097
5098	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
5099	{
5100	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
5101	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
5102	}
5103	else
5104	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
5105	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
5106	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
5107	{
5108	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
5109	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
5110	}
5111	}
5112	else
5113	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
5114	break;
5115	}
5116
5117	case SVGA_CMD_UPDATE:
5118	{
5119	SVGAFifoCmdUpdate *pCmd;
5120	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
5121	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
5122	break;
5123	}
5124
5125	case SVGA_CMD_UPDATE_VERBOSE:
5126	{
5127	SVGAFifoCmdUpdateVerbose *pCmd;
5128	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
5129	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
5130	break;
5131	}
5132
5133	case SVGA_CMD_DEFINE_CURSOR:
5134	{
5135	/* Followed by bitmap data. */
5136	SVGAFifoCmdDefineCursor *pCmd;
5137	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
5138
5139	/* Figure out the size of the bitmap data. */
5140	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
5141	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
5142	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
5143	RT_UNTRUSTED_VALIDATED_FENCE();
5144
5145	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5146	uint32_t const cbAndMask = cbAndLine * pCmd->height;
5147	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5148	uint32_t const cbXorMask = cbXorLine * pCmd->height;
5149
5150	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
5151	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
5152	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
5153	break;
5154	}
5155
5156	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
5157	{
5158	/* Followed by bitmap data. */
5159	SVGAFifoCmdDefineAlphaCursor *pCmd;
5160	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
5161
5162	/* Figure out the size of the bitmap data. */
5163	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
5164
5165	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
5166	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
5167	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
5168	break;
5169	}
5170
5171	case SVGA_CMD_MOVE_CURSOR:
5172	{
5173	/* Deprecated; there should be no driver which requires this command. However, if
5174	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5175	* alignment.
5176	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5177	*/
5178	SVGAFifoCmdMoveCursor *pCmd;
5179	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
5180	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
5181	break;
5182	}
5183
5184	case SVGA_CMD_DISPLAY_CURSOR:
5185	{
5186	/* Deprecated; there should be no driver which requires this command. However, if
5187	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5188	* alignment.
5189	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5190	*/
5191	SVGAFifoCmdDisplayCursor *pCmd;
5192	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
5193	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
5194	break;
5195	}
5196
5197	case SVGA_CMD_RECT_FILL:
5198	{
5199	SVGAFifoCmdRectFill *pCmd;
5200	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
5201	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
5202	break;
5203	}
5204
5205	case SVGA_CMD_RECT_COPY:
5206	{
5207	SVGAFifoCmdRectCopy *pCmd;
5208	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
5209	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
5210	break;
5211	}
5212
5213	case SVGA_CMD_RECT_ROP_COPY:
5214	{
5215	SVGAFifoCmdRectRopCopy *pCmd;
5216	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
5217	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
5218	break;
5219	}
5220
5221	case SVGA_CMD_ESCAPE:
5222	{
5223	/* Followed by 'size' bytes of data. */
5224	SVGAFifoCmdEscape *pCmd;
5225	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
5226
5227	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
5228	RT_UNTRUSTED_VALIDATED_FENCE();
5229
5230	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
5231	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
5232	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
5233	break;
5234	}
5235	# ifdef VBOX_WITH_VMSVGA3D
5236	case SVGA_CMD_DEFINE_GMR2:
5237	{
5238	SVGAFifoCmdDefineGMR2 *pCmd;
5239	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
5240	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
5241	break;
5242	}
5243
5244	case SVGA_CMD_REMAP_GMR2:
5245	{
5246	/* Followed by page descriptors or guest ptr. */
5247	SVGAFifoCmdRemapGMR2 *pCmd;
5248	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
5249
5250	/* Calculate the size of what comes after next and fetch it. */
5251	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
5252	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
5253	cbCmd += sizeof(SVGAGuestPtr);
5254	else
5255	{
5256	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
5257	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
5258	{
5259	cbCmd += cbPageDesc;
5260	pCmd->numPages = 1;
5261	}
5262	else
5263	{
5264	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
5265	cbCmd += cbPageDesc * pCmd->numPages;
5266	}
5267	}
5268	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
5269	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
5270	# ifdef DEBUG_GMR_ACCESS
5271	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
5272	# endif
5273	break;
5274	}
5275	# endif // VBOX_WITH_VMSVGA3D
5276	case SVGA_CMD_DEFINE_SCREEN:
5277	{
5278	/* The size of this command is specified by the guest and depends on capabilities. */
5279	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
5280
5281	SVGAFifoCmdDefineScreen *pCmd;
5282	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
5283	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
5284	RT_UNTRUSTED_VALIDATED_FENCE();
5285
5286	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
5287	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
5288	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
5289	break;
5290	}
5291
5292	case SVGA_CMD_DESTROY_SCREEN:
5293	{
5294	SVGAFifoCmdDestroyScreen *pCmd;
5295	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
5296	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
5297	break;
5298	}
5299
5300	case SVGA_CMD_DEFINE_GMRFB:
5301	{
5302	SVGAFifoCmdDefineGMRFB *pCmd;
5303	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
5304	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5305	break;
5306	}
5307
5308	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5309	{
5310	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
5311	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
5312	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5313	break;
5314	}
5315
5316	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5317	{
5318	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
5319	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
5320	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5321	break;
5322	}
5323
5324	case SVGA_CMD_ANNOTATION_FILL:
5325	{
5326	SVGAFifoCmdAnnotationFill *pCmd;
5327	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
5328	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5329	break;
5330	}
5331
5332	case SVGA_CMD_ANNOTATION_COPY:
5333	{
5334	SVGAFifoCmdAnnotationCopy *pCmd;
5335	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
5336	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5337	break;
5338	}
5339
5340	default:
5341	# ifdef VBOX_WITH_VMSVGA3D
5342	if ( ((int)enmCmdId >= SVGA_3D_CMD_BASE && (int)enmCmdId < SVGA_3D_CMD_MAX)
5343	\|\| ( pThis->svga.fVBoxExtensions
5344	&& ((int)enmCmdId >= VBSVGA_3D_CMD_BASE && (int)enmCmdId < VBSVGA_3D_CMD_MAX)))
5345	{
5346	RT_UNTRUSTED_VALIDATED_FENCE();
5347
5348	/* All 3d commands start with a common header, which defines the identifier and the size
5349	* of the command. The identifier has been already read from FIFO. Fetch the size.
5350	*/
5351	uint32_t *pcbCmd;
5352	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5353	uint32_t const cbCmd = *pcbCmd;
5354	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5355	uint32_t *pu32Cmd;
5356	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5357	pu32Cmd++; /* Skip the command size. */
5358
5359	if (RT_LIKELY(pThis->svga.f3DEnabled))
5360	{ /* likely */ }
5361	else
5362	{
5363	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5364	break;
5365	}
5366
5367	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5368	}
5369	else
5370	# endif // VBOX_WITH_VMSVGA3D
5371	{
5372	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5373	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5374	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5375	}
5376	}
5377
5378	/* Go to the next slot */
5379	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5380	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5381	if (offCurrentCmd >= offFifoMax)
5382	{
5383	offCurrentCmd -= offFifoMax - offFifoMin;
5384	Assert(offCurrentCmd >= offFifoMin);
5385	Assert(offCurrentCmd < offFifoMax);
5386	}
5387	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5388	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5389
5390	/*
5391	* Raise IRQ if required. Must enter the critical section here
5392	* before making final decisions here, otherwise cubebench and
5393	* others may end up waiting forever.
5394	*/
5395	if ( u32IrqStatus
5396	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5397	{
5398	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5399	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5400
5401	/* FIFO progress might trigger an interrupt. */
5402	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5403	{
5404	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5405	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5406	}
5407
5408	/* Unmasked IRQ pending? */
5409	if (pThis->svga.u32IrqMask & u32IrqStatus)
5410	{
5411	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5412	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5413	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5414	}
5415
5416	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5417	}
5418	}
5419
5420	/* If really done, clear the busy flag. */
5421	if (fDone)
5422	{
5423	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5424	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5425	}
5426	}
5427
5428	/*
5429	* Free the bounce buffer. (There are no returns above!)
5430	*/
5431	RTMemFree(pbBounceBuf);
5432
5433	return VINF_SUCCESS;
5434	}
5435
5436	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5437	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5438
5439	/**
5440	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
5441	*/
5442	static DECLCALLBACK(int) vmsvgaR3CmdBufLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5443	{
5444	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5445	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5446	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5447	int rc;
5448
5449	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5450	return VINF_SUCCESS;
5451
5452	/*
5453	* Special mode where we only execute an external command and the go back
5454	* to being suspended. Currently, all ext cmds ends up here, with the reset
5455	* one also being eligble for runtime execution further down as well.
5456	*/
5457	if (pThis->svga.fFifoExtCommandWakeup)
5458	{
5459	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5460	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5461	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
5462	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
5463	else
5464	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5465	return VINF_SUCCESS;
5466	}
5467
5468
5469	/*
5470	* Signal the semaphore to make sure we don't wait for 250ms after a
5471	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
5472	*/
5473	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5474
5475	/*
5476	* Polling/sleep interval config.
5477	*
5478	* We wait for an a short interval if the guest has recently given us work
5479	* to do, but the interval increases the longer we're kept idle. Once we've
5480	* reached the refresh timer interval, we'll switch to extended waits,
5481	* depending on it or the guest to kick us into action when needed.
5482	*
5483	* Should the refresh time go fishing, we'll just continue increasing the
5484	* sleep length till we reaches the 250 ms max after about 16 seconds.
5485	*/
5486	RTMSINTERVAL const cMsMinSleep = 16;
5487	RTMSINTERVAL const cMsMaxSleep = 250;
5488	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
5489	RTMSINTERVAL cMsSleep = cMsMaxSleep;
5490
5491	/*
5492	* The FIFO loop.
5493	*/
5494	LogFlow(("vmsvgaR3CmdBufLoop: started loop\n"));
5495	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
5496	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5497	{
5498	/* First check any pending actions. */
5499	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
5500
5501	/*
5502	* Unless there's already work pending, go to sleep for a short while.
5503	* (See polling/sleep interval config above.)
5504	*/
5505	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
5506	Assert(pThis->cMilliesRefreshInterval > 0);
5507	if (cMsSleep < pThis->cMilliesRefreshInterval)
5508	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
5509	else
5510	{
5511	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
5512	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
5513	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
5514	}
5515	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
5516	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
5517	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
5518	{
5519	LogFlow(("vmsvgaR3CmdBufLoop: thread state %x\n", pThread->enmState));
5520	break;
5521	}
5522
5523	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
5524	cMsSleep = cMsMinSleep;
5525
5526	Log(("vmsvgaR3CmdBufLoop: enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
5527
5528	/*
5529	* Handle external commands (currently only reset).
5530	*/
5531	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
5532	{
5533	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5534	continue;
5535	}
5536
5537	/*
5538	* If guest misbehaves, then do nothing.
5539	*/
5540	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
5541	{
5542	cMsSleep = cMsExtendedSleep;
5543	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
5544	continue;
5545	}
5546
5547	/*
5548	* The device must be enabled and configured.
5549	*/
5550	if ( !pThis->svga.fEnabled
5551	\|\| !pThis->svga.fConfigured)
5552	{
5553	fBadOrDisabledFifo = true;
5554	cMsSleep = cMsMaxSleep; /* cheat */
5555	continue;
5556	}
5557
5558	/*
5559	* Process all submitted command buffers.
5560	*/
5561	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
5562	}
5563
5564	return VINF_SUCCESS;
5565	}
5566
5567
5568	/**
5569	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5570	* Unblock the FIFO I/O thread so it can respond to a state change.}
5571	*/
5572	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5573	{
5574	RT_NOREF(pDevIns);
5575	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5576	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5577	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5578	}
5579
5580	/**
5581	* Enables or disables dirty page tracking for the framebuffer
5582	*
5583	* @param pDevIns The device instance.
5584	* @param pThis The shared VGA/VMSVGA instance data.
5585	* @param fTraces Enable/disable traces
5586	*/
5587	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5588	{
5589	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5590	&& !fTraces)
5591	{
5592	//Assert(pThis->svga.fTraces);
5593	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5594	return;
5595	}
5596
5597	pThis->svga.fTraces = fTraces;
5598	if (pThis->svga.fTraces)
5599	{
5600	unsigned cbFrameBuffer = pThis->vram_size;
5601
5602	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5603	/** @todo How does this work with screens? */
5604	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5605	{
5606	# if 0 //ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5607	Assert(pThis->svga.cbScanline);
5608	# endif
5609	/* Hardware enabled; return real framebuffer size .*/
5610	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5611	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, GUEST_PAGE_SIZE);
5612	}
5613
5614	if (!pThis->svga.fVRAMTracking)
5615	{
5616	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5617	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5618	pThis->svga.fVRAMTracking = true;
5619	}
5620	}
5621	else
5622	{
5623	if (pThis->svga.fVRAMTracking)
5624	{
5625	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5626	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5627	pThis->svga.fVRAMTracking = false;
5628	}
5629	}
5630	}
5631
5632	/**
5633	* @callback_method_impl{FNPCIIOREGIONMAP}
5634	*/
5635	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5636	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5637	{
5638	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5639	int rc;
5640	RT_NOREF(pPciDev);
5641	Assert(pPciDev == pDevIns->apPciDevs[0]);
5642
5643	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5644	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5645	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5646	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5647	, VERR_INTERNAL_ERROR);
5648	if (GCPhysAddress != NIL_RTGCPHYS)
5649	{
5650	/*
5651	* Mapping the FIFO RAM.
5652	*/
5653	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5654	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5655	AssertRC(rc);
5656
5657	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5658	if (RT_SUCCESS(rc))
5659	{
5660	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, GCPhysAddress,
5661	# ifdef DEBUG_FIFO_ACCESS
5662	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5663	# else
5664	GCPhysAddress + GUEST_PAGE_SIZE - 1,
5665	# endif
5666	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5667	"VMSVGA FIFO");
5668	AssertRC(rc);
5669	}
5670	# endif
5671	if (RT_SUCCESS(rc))
5672	{
5673	pThis->svga.GCPhysFIFO = GCPhysAddress;
5674	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5675	}
5676	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5677	}
5678	else
5679	{
5680	Assert(pThis->svga.GCPhysFIFO);
5681	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5682	rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pThis->svga.GCPhysFIFO);
5683	AssertRC(rc);
5684	# else
5685	rc = VINF_SUCCESS;
5686	# endif
5687	pThis->svga.GCPhysFIFO = 0;
5688	}
5689	return rc;
5690	}
5691
5692	# ifdef VBOX_WITH_VMSVGA3D
5693
5694	/**
5695	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5696	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5697	*
5698	* @param pDevIns The device instance.
5699	* @param pThis The The shared VGA/VMSVGA instance data.
5700	* @param pThisCC The VGA/VMSVGA state for ring-3.
5701	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5702	* UINT32_MAX is used, all surfaces are processed.
5703	*/
5704	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5705	{
5706	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5707	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5708	}
5709
5710
5711	/**
5712	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5713	*/
5714	static DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5715	{
5716	/* There might be a specific surface ID at the start of the
5717	arguments, if not show all surfaces. */
5718	uint32_t sid = UINT32_MAX;
5719	if (pszArgs)
5720	pszArgs = RTStrStripL(pszArgs);
5721	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5722	sid = RTStrToUInt32(pszArgs);
5723
5724	/* Verbose or terse display, we default to verbose. */
5725	bool fVerbose = true;
5726	if (RTStrIStr(pszArgs, "terse"))
5727	fVerbose = false;
5728
5729	/* The size of the ascii art (x direction, y is 3/4 of x). */
5730	uint32_t cxAscii = 80;
5731	if (RTStrIStr(pszArgs, "gigantic"))
5732	cxAscii = 300;
5733	else if (RTStrIStr(pszArgs, "huge"))
5734	cxAscii = 180;
5735	else if (RTStrIStr(pszArgs, "big"))
5736	cxAscii = 132;
5737	else if (RTStrIStr(pszArgs, "normal"))
5738	cxAscii = 80;
5739	else if (RTStrIStr(pszArgs, "medium"))
5740	cxAscii = 64;
5741	else if (RTStrIStr(pszArgs, "small"))
5742	cxAscii = 48;
5743	else if (RTStrIStr(pszArgs, "tiny"))
5744	cxAscii = 24;
5745
5746	/* Y invert the image when producing the ASCII art. */
5747	bool fInvY = false;
5748	if (RTStrIStr(pszArgs, "invy"))
5749	fInvY = true;
5750
5751	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5752	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5753	}
5754
5755
5756	/**
5757	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5758	*/
5759	static DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5760	{
5761	/* pszArg = "sid[>dir]"
5762	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5763	*/
5764	char *pszBitmapPath = NULL;
5765	uint32_t sid = UINT32_MAX;
5766	if (pszArgs)
5767	pszArgs = RTStrStripL(pszArgs);
5768	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5769	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5770	if ( pszBitmapPath
5771	&& *pszBitmapPath == '>')
5772	++pszBitmapPath;
5773
5774	const bool fVerbose = true;
5775	const uint32_t cxAscii = 0; /* No ASCII */
5776	const bool fInvY = false; /* Do not invert. */
5777	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5778	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5779	}
5780
5781	/**
5782	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5783	*/
5784	static DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5785	{
5786	/* There might be a specific surface ID at the start of the
5787	arguments, if not show all contexts. */
5788	uint32_t sid = UINT32_MAX;
5789	if (pszArgs)
5790	pszArgs = RTStrStripL(pszArgs);
5791	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5792	sid = RTStrToUInt32(pszArgs);
5793
5794	/* Verbose or terse display, we default to verbose. */
5795	bool fVerbose = true;
5796	if (RTStrIStr(pszArgs, "terse"))
5797	fVerbose = false;
5798
5799	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5800	}
5801	# endif /* VBOX_WITH_VMSVGA3D */
5802
5803	/**
5804	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5805	*/
5806	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5807	{
5808	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5809	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5810	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5811	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5812	RT_NOREF(pszArgs);
5813
5814	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5815	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5816	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5817	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5818	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5819	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5820	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5821	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5822	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5823	if (pFIFO)
5824	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5825	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5826	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5827	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5828	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5829	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5830	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO ? pFIFO[SVGA_FIFO_PITCHLOCK] : 0);
5831	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5832	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5833	pHlp->pfnPrintf(pHlp, "Device Cap2: %#x\n", pThis->svga.u32DeviceCaps2);
5834	pHlp->pfnPrintf(pHlp, "Guest driver id: %#x\n", pThis->svga.u32GuestDriverId);
5835	pHlp->pfnPrintf(pHlp, "Guest driver ver1: %#x\n", pThis->svga.u32GuestDriverVer1);
5836	pHlp->pfnPrintf(pHlp, "Guest driver ver2: %#x\n", pThis->svga.u32GuestDriverVer2);
5837	pHlp->pfnPrintf(pHlp, "Guest driver ver3: %#x\n", pThis->svga.u32GuestDriverVer3);
5838	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5839	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5840	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5841	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5842	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5843	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5844	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5845
5846	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5847	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5848	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5849	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5850	if (pFIFO)
5851	{
5852	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5853	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5854	}
5855	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5856	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5857
5858	# ifdef VBOX_WITH_VMSVGA3D
5859	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5860	# endif
5861	if (pThisCC->pDrv)
5862	{
5863	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5864	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5865	}
5866
5867	/* Dump screen information. */
5868	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5869	{
5870	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5871	if (pScreen)
5872	{
5873	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5874	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5875	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5876	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5877	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5878	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5879	{
5880	pHlp->pfnPrintf(pHlp, " (");
5881	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5882	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5883	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5884	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5885	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5886	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5887	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5888	pHlp->pfnPrintf(pHlp, " BLANKING");
5889	pHlp->pfnPrintf(pHlp, " )");
5890	}
5891	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5892	}
5893	}
5894
5895	}
5896
5897	static int vmsvgaR3LoadBufCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx, SVGACBContext CBCtx)
5898	{
5899	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5900	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5901
5902	uint32_t cSubmitted;
5903	int rc = pHlp->pfnSSMGetU32(pSSM, &cSubmitted);
5904	AssertLogRelRCReturn(rc, rc);
5905
5906	for (uint32_t i = 0; i < cSubmitted; ++i)
5907	{
5908	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pBufCtx);
5909	AssertPtrReturn(pCmdBuf, VERR_NO_MEMORY);
5910
5911	pHlp->pfnSSMGetGCPhys(pSSM, &pCmdBuf->GCPhysCB);
5912
5913	uint32_t u32;
5914	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5915	AssertRCReturn(rc, rc);
5916	AssertReturn(u32 == sizeof(SVGACBHeader), VERR_INVALID_STATE);
5917	pHlp->pfnSSMGetMem(pSSM, &pCmdBuf->hdr, sizeof(SVGACBHeader));
5918
5919	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5920	AssertRCReturn(rc, rc);
5921	AssertReturn(u32 == pCmdBuf->hdr.length, VERR_INVALID_STATE);
5922
5923	if (pCmdBuf->hdr.length)
5924	{
5925	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
5926	AssertPtrReturn(pCmdBuf->pvCommands, VERR_NO_MEMORY);
5927
5928	rc = pHlp->pfnSSMGetMem(pSSM, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
5929	AssertRCReturn(rc, rc);
5930	}
5931
5932	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5933	{
5934	vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
5935	}
5936	else
5937	{
5938	uint32_t offNextCmd = 0;
5939	vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
5940	}
5941
5942	/* Free the buffer if CmdBufSubmit* did not consume it. */
5943	vmsvgaR3CmdBufFree(pCmdBuf);
5944	}
5945	return rc;
5946	}
5947
5948	static int vmsvgaR3LoadCommandBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5949	{
5950	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5951	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5952
5953	bool f;
5954	uint32_t u32;
5955
5956	/* Device context command buffers. */
5957	int rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, &pSvgaR3State->CmdBufCtxDC, SVGA_CB_CONTEXT_MAX);
5958	AssertLogRelRCReturn(rc, rc);
5959
5960	/* DX contexts command buffers. */
5961	uint32_t cBufCtx;
5962	rc = pHlp->pfnSSMGetU32(pSSM, &cBufCtx);
5963	AssertLogRelRCReturn(rc, rc);
5964	AssertReturn(cBufCtx == RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs), VERR_INVALID_STATE);
5965	for (uint32_t j = 0; j < cBufCtx; ++j)
5966	{
5967	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5968	AssertLogRelRCReturn(rc, rc);
5969	if (f)
5970	{
5971	pSvgaR3State->apCmdBufCtxs[j] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
5972	AssertPtrReturn(pSvgaR3State->apCmdBufCtxs[j], VERR_NO_MEMORY);
5973	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[j]);
5974
5975	rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, pSvgaR3State->apCmdBufCtxs[j], (SVGACBContext)j);
5976	AssertLogRelRCReturn(rc, rc);
5977	}
5978	}
5979
5980	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5981	pSvgaR3State->fCmdBuf = u32;
5982	return rc;
5983	}
5984
5985	static int vmsvgaR3LoadGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5986	{
5987	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5988
5989	int rc;
5990	pHlp->pfnSSMGetU32(pSSM, &pGbo->fGboFlags);
5991	pHlp->pfnSSMGetU32(pSSM, &pGbo->cTotalPages);
5992	pHlp->pfnSSMGetU32(pSSM, &pGbo->cbTotal);
5993	rc = pHlp->pfnSSMGetU32(pSSM, &pGbo->cDescriptors);
5994	AssertRCReturn(rc, rc);
5995
5996	if (pGbo->cDescriptors)
5997	{
5998	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAllocZ(pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
5999	AssertPtrReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
6000	}
6001
6002	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
6003	{
6004	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
6005	pHlp->pfnSSMGetGCPhys(pSSM, &pDesc->GCPhys);
6006	rc = pHlp->pfnSSMGetU64(pSSM, &pDesc->cPages);
6007	}
6008
6009	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
6010	{
6011	pGbo->pvHost = RTMemAlloc(pGbo->cbTotal);
6012	AssertPtrReturn(pGbo->pvHost, VERR_NO_MEMORY);
6013	rc = pHlp->pfnSSMGetMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
6014	}
6015
6016	return rc;
6017	}
6018
6019	/**
6020	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
6021	*/
6022	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
6023	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6024	{
6025	RT_NOREF(uPass);
6026
6027	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6028	int rc;
6029
6030	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
6031	{
6032	uint32_t cScreens = 0;
6033	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
6034	AssertRCReturn(rc, rc);
6035	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
6036	("cScreens=%#x\n", cScreens),
6037	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6038
6039	for (uint32_t i = 0; i < cScreens; ++i)
6040	{
6041	VMSVGASCREENOBJECT screen;
6042	RT_ZERO(screen);
6043
6044	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6045	AssertLogRelRCReturn(rc, rc);
6046
6047	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
6048	{
6049	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
6050	*pScreen = screen;
6051	pScreen->fModified = true;
6052
6053	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
6054	{
6055	uint32_t u32;
6056	pHlp->pfnSSMGetU32(pSSM, &u32); /* Size of screen bitmap. */
6057	AssertLogRelRCReturn(rc, rc);
6058	if (u32)
6059	{
6060	pScreen->pvScreenBitmap = RTMemAlloc(u32);
6061	AssertPtrReturn(pScreen->pvScreenBitmap, VERR_NO_MEMORY);
6062
6063	pHlp->pfnSSMGetMem(pSSM, pScreen->pvScreenBitmap, u32);
6064	}
6065	}
6066	}
6067	else
6068	{
6069	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
6070	}
6071	}
6072	}
6073	else
6074	{
6075	/* Try to setup at least the first screen. */
6076	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
6077	Assert(pScreen->idScreen == 0);
6078	pScreen->fDefined = true;
6079	pScreen->fModified = true;
6080	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
6081	pScreen->xOrigin = 0;
6082	pScreen->yOrigin = 0;
6083	pScreen->offVRAM = pThis->svga.uScreenOffset;
6084	pScreen->cbPitch = pThis->svga.cbScanline;
6085	pScreen->cWidth = pThis->svga.uWidth;
6086	pScreen->cHeight = pThis->svga.uHeight;
6087	pScreen->cBpp = pThis->svga.uBpp;
6088	}
6089
6090	return VINF_SUCCESS;
6091	}
6092
6093	/**
6094	* @copydoc FNSSMDEVLOADEXEC
6095	*/
6096	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6097	{
6098	RT_NOREF(uPass);
6099	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6100	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6101	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6102	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6103	int rc;
6104
6105	/* Load our part of the VGAState */
6106	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6107	AssertRCReturn(rc, rc);
6108
6109	/* Load the VGA framebuffer. */
6110	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
6111	uint32_t cbVgaFramebuffer = _32K;
6112	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
6113	{
6114	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
6115	AssertRCReturn(rc, rc);
6116	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
6117	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
6118	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6119	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
6120	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
6121	}
6122	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
6123	AssertRCReturn(rc, rc);
6124	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
6125	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
6126	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
6127	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
6128
6129	/* Load the VMSVGA state. */
6130	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6131	AssertRCReturn(rc, rc);
6132
6133	/* Load the active cursor bitmaps. */
6134	if (pSVGAState->Cursor.fActive)
6135	{
6136	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
6137	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
6138
6139	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6140	AssertRCReturn(rc, rc);
6141	}
6142
6143	/* Load the GMR state. */
6144	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
6145	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
6146	{
6147	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
6148	AssertRCReturn(rc, rc);
6149	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
6150	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
6151	("cGMR=%#x - expected 256B..1MB\n", cGMR),
6152	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6153	}
6154
6155	if (pThis->svga.cGMR != cGMR)
6156	{
6157	/* Reallocate GMR array. */
6158	Assert(pSVGAState->paGMR != NULL);
6159	RTMemFree(pSVGAState->paGMR);
6160	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
6161	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6162	pThis->svga.cGMR = cGMR;
6163	}
6164
6165	for (uint32_t i = 0; i < cGMR; ++i)
6166	{
6167	PGMR pGMR = &pSVGAState->paGMR[i];
6168
6169	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6170	AssertRCReturn(rc, rc);
6171
6172	if (pGMR->numDescriptors)
6173	{
6174	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6175	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6176	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6177
6178	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6179	{
6180	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6181	AssertRCReturn(rc, rc);
6182	}
6183	}
6184	}
6185
6186	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
6187	{
6188	bool f;
6189	uint32_t u32;
6190
6191	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
6192	{
6193	/* Command buffers are saved independently from VGPU10. */
6194	rc = pHlp->pfnSSMGetBool(pSSM, &f);
6195	AssertLogRelRCReturn(rc, rc);
6196	if (f)
6197	{
6198	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
6199	AssertLogRelRCReturn(rc, rc);
6200	}
6201	}
6202
6203	rc = pHlp->pfnSSMGetBool(pSSM, &f);
6204	AssertLogRelRCReturn(rc, rc);
6205	pThis->fVMSVGA10 = f;
6206
6207	if (pThis->fVMSVGA10)
6208	{
6209	if (uVersion < VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
6210	{
6211	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
6212	AssertLogRelRCReturn(rc, rc);
6213	}
6214
6215	/*
6216	* OTables GBOs.
6217	*/
6218	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
6219	AssertLogRelRCReturn(rc, rc);
6220	AssertReturn(u32 == SVGA_OTABLE_MAX, VERR_INVALID_STATE);
6221	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6222	{
6223	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6224	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, pGbo);
6225	AssertRCReturn(rc, rc);
6226	}
6227
6228	/*
6229	* MOBs.
6230	*/
6231	for (;;)
6232	{
6233	rc = pHlp->pfnSSMGetU32(pSSM, &u32); /* MOB id. */
6234	AssertRCReturn(rc, rc);
6235	if (u32 == SVGA_ID_INVALID)
6236	break;
6237
6238	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
6239	AssertPtrReturn(pMob, VERR_NO_MEMORY);
6240
6241	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, &pMob->Gbo);
6242	AssertRCReturn(rc, rc);
6243
6244	pMob->Core.Key = u32;
6245	if (RTAvlU32Insert(&pSVGAState->MOBTree, &pMob->Core))
6246	RTListPrepend(&pSVGAState->MOBLRUList, &pMob->nodeLRU);
6247	else
6248	AssertFailedReturn(VERR_NO_MEMORY);
6249	}
6250
6251	# ifdef VMSVGA3D_DX
6252	if (pThis->svga.f3DEnabled)
6253	{
6254	pHlp->pfnSSMGetU32(pSSM, &pSVGAState->idDXContextCurrent);
6255	}
6256	# endif
6257	}
6258	}
6259
6260	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6261	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
6262	# endif
6263
6264	VMSVGA_STATE_LOAD LoadState;
6265	LoadState.pSSM = pSSM;
6266	LoadState.uVersion = uVersion;
6267	LoadState.uPass = uPass;
6268	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6269	AssertLogRelRCReturn(rc, rc);
6270
6271	return VINF_SUCCESS;
6272	}
6273
6274	/**
6275	* Reinit the video mode after the state has been loaded.
6276	*/
6277	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6278	{
6279	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6280	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6281	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6282
6283	/* VMSVGA is working via VBVA interface, therefore it needs to be
6284	* enabled on saved state restore. See @bugref{10071#c7}. */
6285	if (pThis->svga.fEnabled)
6286	{
6287	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
6288	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
6289	}
6290
6291	/* Set the active cursor. */
6292	if (pSVGAState->Cursor.fActive)
6293	{
6294	/* We don't store the alpha flag, but we can take a guess that if
6295	* the old register interface was used, the cursor was B&W.
6296	*/
6297	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6298
6299	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6300	true /fVisible/,
6301	fAlpha,
6302	pSVGAState->Cursor.xHotspot,
6303	pSVGAState->Cursor.yHotspot,
6304	pSVGAState->Cursor.width,
6305	pSVGAState->Cursor.height,
6306	pSVGAState->Cursor.pData);
6307	AssertRC(rc);
6308
6309	if (pThis->svga.uCursorOn)
6310	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6311	}
6312
6313	/* If the VRAM handler should not be registered, we have to explicitly
6314	* unregister it here!
6315	*/
6316	if (!pThis->svga.fVRAMTracking)
6317	{
6318	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6319	}
6320
6321	/* Let the FIFO thread deal with changing the mode. */
6322	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6323
6324	return VINF_SUCCESS;
6325	}
6326
6327	static int vmsvgaR3SaveBufCtx(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx)
6328	{
6329	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6330
6331	int rc = pHlp->pfnSSMPutU32(pSSM, pBufCtx->cSubmitted);
6332	AssertLogRelRCReturn(rc, rc);
6333	if (pBufCtx->cSubmitted)
6334	{
6335	PVMSVGACMDBUF pIter;
6336	RTListForEach(&pBufCtx->listSubmitted, pIter, VMSVGACMDBUF, nodeBuffer)
6337	{
6338	pHlp->pfnSSMPutGCPhys(pSSM, pIter->GCPhysCB);
6339	pHlp->pfnSSMPutU32(pSSM, sizeof(SVGACBHeader));
6340	pHlp->pfnSSMPutMem(pSSM, &pIter->hdr, sizeof(SVGACBHeader));
6341	pHlp->pfnSSMPutU32(pSSM, pIter->hdr.length);
6342	if (pIter->hdr.length)
6343	rc = pHlp->pfnSSMPutMem(pSSM, pIter->pvCommands, pIter->hdr.length);
6344	AssertLogRelRCReturn(rc, rc);
6345	}
6346	}
6347	return rc;
6348	}
6349
6350	static int vmsvgaR3SaveGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
6351	{
6352	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6353
6354	int rc;
6355	pHlp->pfnSSMPutU32(pSSM, pGbo->fGboFlags);
6356	pHlp->pfnSSMPutU32(pSSM, pGbo->cTotalPages);
6357	pHlp->pfnSSMPutU32(pSSM, pGbo->cbTotal);
6358	rc = pHlp->pfnSSMPutU32(pSSM, pGbo->cDescriptors);
6359	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
6360	{
6361	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
6362	pHlp->pfnSSMPutGCPhys(pSSM, pDesc->GCPhys);
6363	rc = pHlp->pfnSSMPutU64(pSSM, pDesc->cPages);
6364	}
6365	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
6366	rc = pHlp->pfnSSMPutMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
6367	return rc;
6368	}
6369
6370	/**
6371	* Portion of SVGA state which must be saved in the FIFO thread.
6372	*/
6373	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6374	{
6375	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6376	int rc;
6377
6378	/* Save the screen objects. */
6379	/* Count defined screen object. */
6380	uint32_t cScreens = 0;
6381	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6382	{
6383	if (pSVGAState->aScreens[i].fDefined)
6384	++cScreens;
6385	}
6386
6387	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6388	AssertLogRelRCReturn(rc, rc);
6389
6390	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6391	{
6392	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6393	if (!pScreen->fDefined)
6394	continue;
6395
6396	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6397	AssertLogRelRCReturn(rc, rc);
6398
6399	/*
6400	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX
6401	*/
6402	if (pScreen->pvScreenBitmap)
6403	{
6404	uint32_t const cbScreenBitmap = pScreen->cHeight * pScreen->cbPitch;
6405	pHlp->pfnSSMPutU32(pSSM, cbScreenBitmap);
6406	pHlp->pfnSSMPutMem(pSSM, pScreen->pvScreenBitmap, cbScreenBitmap);
6407	}
6408	else
6409	pHlp->pfnSSMPutU32(pSSM, 0);
6410	}
6411	return VINF_SUCCESS;
6412	}
6413
6414	/**
6415	* @copydoc FNSSMDEVSAVEEXEC
6416	*/
6417	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6418	{
6419	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6420	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6421	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6422	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6423	int rc;
6424
6425	/* Save our part of the VGAState */
6426	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6427	AssertLogRelRCReturn(rc, rc);
6428
6429	/* Save the framebuffer backup. */
6430	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6431	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6432	AssertLogRelRCReturn(rc, rc);
6433
6434	/* Save the VMSVGA state. */
6435	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6436	AssertLogRelRCReturn(rc, rc);
6437
6438	/* Save the active cursor bitmaps. */
6439	if (pSVGAState->Cursor.fActive)
6440	{
6441	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6442	AssertLogRelRCReturn(rc, rc);
6443	}
6444
6445	/* Save the GMR state */
6446	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6447	AssertLogRelRCReturn(rc, rc);
6448	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6449	{
6450	PGMR pGMR = &pSVGAState->paGMR[i];
6451
6452	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6453	AssertLogRelRCReturn(rc, rc);
6454
6455	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6456	{
6457	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6458	AssertLogRelRCReturn(rc, rc);
6459	}
6460	}
6461
6462	/*
6463	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX+
6464	*/
6465	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
6466	{
6467	rc = pHlp->pfnSSMPutBool(pSSM, true);
6468	AssertLogRelRCReturn(rc, rc);
6469
6470	/* Device context command buffers. */
6471	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, &pSVGAState->CmdBufCtxDC);
6472	AssertRCReturn(rc, rc);
6473
6474	/* DX contexts command buffers. */
6475	rc = pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pSVGAState->apCmdBufCtxs));
6476	AssertLogRelRCReturn(rc, rc);
6477	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6478	{
6479	if (pSVGAState->apCmdBufCtxs[i])
6480	{
6481	pHlp->pfnSSMPutBool(pSSM, true);
6482	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, pSVGAState->apCmdBufCtxs[i]);
6483	AssertRCReturn(rc, rc);
6484	}
6485	else
6486	pHlp->pfnSSMPutBool(pSSM, false);
6487	}
6488
6489	rc = pHlp->pfnSSMPutU32(pSSM, pSVGAState->fCmdBuf);
6490	AssertRCReturn(rc, rc);
6491	}
6492	else
6493	{
6494	rc = pHlp->pfnSSMPutBool(pSSM, false);
6495	AssertLogRelRCReturn(rc, rc);
6496	}
6497
6498	rc = pHlp->pfnSSMPutBool(pSSM, pThis->fVMSVGA10);
6499	AssertLogRelRCReturn(rc, rc);
6500
6501	if (pThis->fVMSVGA10)
6502	{
6503	/*
6504	* OTables GBOs.
6505	*/
6506	pHlp->pfnSSMPutU32(pSSM, SVGA_OTABLE_MAX);
6507	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6508	{
6509	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6510	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, pGbo);
6511	AssertRCReturn(rc, rc);
6512	}
6513
6514	/*
6515	* MOBs.
6516	*/
6517	PVMSVGAMOB pIter;
6518	RTListForEach(&pSVGAState->MOBLRUList, pIter, VMSVGAMOB, nodeLRU)
6519	{
6520	pHlp->pfnSSMPutU32(pSSM, pIter->Core.Key); /* MOB id. */
6521	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, &pIter->Gbo);
6522	AssertRCReturn(rc, rc);
6523	}
6524
6525	pHlp->pfnSSMPutU32(pSSM, SVGA_ID_INVALID); /* End marker. */
6526
6527	# ifdef VMSVGA3D_DX
6528	if (pThis->svga.f3DEnabled)
6529	{
6530	pHlp->pfnSSMPutU32(pSSM, pSVGAState->idDXContextCurrent);
6531	}
6532	# endif
6533	}
6534
6535	/*
6536	* Must save some state (3D in particular) in the FIFO thread.
6537	*/
6538	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6539	AssertLogRelRCReturn(rc, rc);
6540
6541	return VINF_SUCCESS;
6542	}
6543
6544	/**
6545	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
6546	*
6547	* @param pThis The shared VGA/VMSVGA instance data.
6548	* @param pThisCC The device context.
6549	*/
6550	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
6551	{
6552	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6553
6554	# ifndef VMSVGA_USE_EMT_HALT_CODE
6555	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6556	{
6557	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6558	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6559	}
6560	# endif
6561
6562	if (pSVGAState->Cursor.fActive)
6563	{
6564	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6565	pSVGAState->Cursor.pData = NULL;
6566	pSVGAState->Cursor.fActive = false;
6567	}
6568
6569	if (pSVGAState->paGMR)
6570	{
6571	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6572	if (pSVGAState->paGMR[i].paDesc)
6573	RTMemFree(pSVGAState->paGMR[i].paDesc);
6574
6575	RTMemFree(pSVGAState->paGMR);
6576	pSVGAState->paGMR = NULL;
6577	}
6578
6579	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
6580	{
6581	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
6582	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6583	{
6584	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
6585	RTMemFree(pSVGAState->apCmdBufCtxs[i]);
6586	pSVGAState->apCmdBufCtxs[i] = NULL;
6587	}
6588	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
6589	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
6590	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
6591	}
6592	}
6593
6594	/**
6595	* Constructor for PVMSVGAR3STATE structure.
6596	*
6597	* @returns VBox status code.
6598	* @param pDevIns The PDM device instance.
6599	* @param pThis The shared VGA/VMSVGA instance data.
6600	* @param pSVGAState Pointer to the structure. It is already allocated.
6601	*/
6602	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6603	{
6604	int rc = VINF_SUCCESS;
6605
6606	pSVGAState->pDevIns = pDevIns;
6607
6608	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6609	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6610
6611	# ifndef VMSVGA_USE_EMT_HALT_CODE
6612	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6613	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6614	AssertRCReturn(rc, rc);
6615	# endif
6616
6617	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
6618	AssertRCReturn(rc, rc);
6619
6620	/* Init screen ids which are constant and allow to use a pointer to aScreens element and know its index. */
6621	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6622	pSVGAState->aScreens[i].idScreen = i;
6623
6624	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
6625
6626	RTListInit(&pSVGAState->MOBLRUList);
6627	# ifdef VBOX_WITH_VMSVGA3D
6628	# ifdef VMSVGA3D_DX
6629	pSVGAState->idDXContextCurrent = SVGA3D_INVALID_ID;
6630	# endif
6631	# endif
6632	return rc;
6633	}
6634
6635	# ifdef VBOX_WITH_VMSVGA3D
6636	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
6637	{
6638	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6639
6640	RTMemFree(pSVGAState->pFuncsMap);
6641	pSVGAState->pFuncsMap = NULL;
6642	RTMemFree(pSVGAState->pFuncsGBO);
6643	pSVGAState->pFuncsGBO = NULL;
6644	RTMemFree(pSVGAState->pFuncsDX);
6645	pSVGAState->pFuncsDX = NULL;
6646	RTMemFree(pSVGAState->pFuncsDXVideo);
6647	pSVGAState->pFuncsDXVideo = NULL;
6648	RTMemFree(pSVGAState->pFuncsVGPU9);
6649	pSVGAState->pFuncsVGPU9 = NULL;
6650	RTMemFree(pSVGAState->pFuncs3D);
6651	pSVGAState->pFuncs3D = NULL;
6652	}
6653
6654	/* This structure is used only by vmsvgaR3Init3dInterfaces */
6655	typedef struct VMSVGA3DINTERFACE
6656	{
6657	char const *pcszName;
6658	uint32_t cbFuncs;
6659	void **ppvFuncs;
6660	} VMSVGA3DINTERFACE;
6661
6662	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
6663	#if defined(VMSVGA3D_DX_BACKEND)
6664	extern VMSVGA3DBACKENDDESC const g_BackendDX;
6665	#endif
6666
6667	/**
6668	* Initializes the optional host 3D backend interfaces.
6669	*
6670	* @returns VBox status code.
6671	* @param pThisCC The VGA/VMSVGA state for ring-3.
6672	*/
6673	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6674	{
6675	#ifndef VMSVGA3D_DX
6676	RT_NOREF(pThis);
6677	#endif
6678
6679	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6680
6681	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
6682	VMSVGA3DINTERFACE a3dInterface[] =
6683	{
6684	ENTRY_3D_INTERFACE(3D, pFuncs3D),
6685	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
6686	ENTRY_3D_INTERFACE(DX, pFuncsDX),
6687	ENTRY_3D_INTERFACE(DXVIDEO, pFuncsDXVideo),
6688	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
6689	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
6690	};
6691	#undef ENTRY_3D_INTERFACE
6692
6693	VMSVGA3DBACKENDDESC const *pBackend = NULL;
6694	#if defined(VMSVGA3D_DX_BACKEND)
6695	if (pThis->fVMSVGA10)
6696	pBackend = &g_BackendDX;
6697	else
6698	#endif
6699	pBackend = &g_BackendLegacy;
6700
6701	int rc = VINF_SUCCESS;
6702	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
6703	{
6704	VMSVGA3DINTERFACE *p = &a3dInterface[i];
6705
6706	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
6707	if (RT_SUCCESS(rc2))
6708	{
6709	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
6710	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
6711
6712	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
6713	}
6714	}
6715
6716	if (RT_SUCCESS(rc))
6717	{
6718	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6719	if (RT_SUCCESS(rc))
6720	return VINF_SUCCESS;
6721	}
6722
6723	vmsvga3dR3Free3dInterfaces(pThisCC);
6724	return rc;
6725	}
6726	# endif /* VBOX_WITH_VMSVGA3D */
6727
6728	/**
6729	* Compute the host capabilities: device and FIFO.
6730	*
6731	* Depends on 3D backend initialization.
6732	*
6733	* @param pThis The shared VGA/VMSVGA instance data.
6734	* @param pThisCC The VGA/VMSVGA state for ring-3.
6735	* @param pu32DeviceCaps Device capabilities (SVGA_CAP_*).
6736	* @param pu32DeviceCaps2 Device capabilities (SVGA_CAP2_*).
6737	* @param pu32FIFOCaps FIFO capabilities (SVGA_FIFO_CAPS_*).
6738	*/
6739	static void vmsvgaR3GetCaps(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t pu32DeviceCaps, uint32_t pu32DeviceCaps2, uint32_t *pu32FIFOCaps)
6740	{
6741	#ifndef VBOX_WITH_VMSVGA3D
6742	RT_NOREF(pThisCC);
6743	#endif
6744
6745	/* Device caps. */
6746	*pu32DeviceCaps = SVGA_CAP_GMR
6747	\| SVGA_CAP_GMR2
6748	\| SVGA_CAP_CURSOR
6749	\| SVGA_CAP_CURSOR_BYPASS
6750	\| SVGA_CAP_CURSOR_BYPASS_2
6751	\| SVGA_CAP_EXTENDED_FIFO
6752	\| SVGA_CAP_IRQMASK
6753	\| SVGA_CAP_PITCHLOCK
6754	\| SVGA_CAP_RECT_COPY
6755	\| SVGA_CAP_TRACES
6756	\| SVGA_CAP_SCREEN_OBJECT_2
6757	\| SVGA_CAP_ALPHA_CURSOR;
6758
6759	pu32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS / Enable register based command buffer submission. */
6760	;
6761
6762	*pu32DeviceCaps2 = SVGA_CAP2_NONE;
6763
6764	/* VGPU10 capabilities. */
6765	if (pThis->fVMSVGA10)
6766	{
6767	# ifdef VBOX_WITH_VMSVGA3D
6768	if (pThisCC->svga.pSvgaR3State->pFuncsGBO)
6769	pu32DeviceCaps \|= SVGA_CAP_GBOBJECTS; / Enable guest-backed objects and surfaces. */
6770	if (pThisCC->svga.pSvgaR3State->pFuncsDX)
6771	{
6772	pu32DeviceCaps \|= SVGA_CAP_DX / DX commands, and command buffers in a mob. */
6773	\| SVGA_CAP_CAP2_REGISTER /* Extended capabilities. */
6774	;
6775
6776	if (*pu32DeviceCaps & SVGA_CAP_CAP2_REGISTER)
6777	pu32DeviceCaps2 \|= SVGA_CAP2_GROW_OTABLE / "Allow the GrowOTable/DXGrowCOTable commands" */
6778	\| SVGA_CAP2_INTRA_SURFACE_COPY /* "IntraSurfaceCopy command" */
6779	\| SVGA_CAP2_DX2 /* Shader Model 4.1.
6780	* "Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
6781	* HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register."
6782	*/
6783	\| SVGA_CAP2_GB_MEMSIZE_2 /* "Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register" */
6784	\| SVGA_CAP2_OTABLE_PTDEPTH_2
6785	\| SVGA_CAP2_DX3 /* Shader Model 5.
6786	* DefineGBSurface_v4, etc
6787	*/
6788	;
6789	}
6790	# endif
6791	}
6792
6793	# ifdef VBOX_WITH_VMSVGA3D
6794	// if (pThisCC->svga.pSvgaR3State->pFuncs3D)
6795	if (pThis->svga.f3DEnabled)
6796	*pu32DeviceCaps \|= SVGA_CAP_3D;
6797	# endif
6798
6799	/* FIFO capabilities. */
6800	if (!pThis->fVmSvga3)
6801	*pu32FIFOCaps = SVGA_FIFO_CAP_FENCE
6802	\| SVGA_FIFO_CAP_PITCHLOCK
6803	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6804	\| SVGA_FIFO_CAP_RESERVE
6805	\| SVGA_FIFO_CAP_GMR2
6806	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6807	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
6808	}
6809
6810	/** Initialize the FIFO on power on and reset.
6811	*
6812	* @param pThis The shared VGA/VMSVGA instance data.
6813	* @param pThisCC The VGA/VMSVGA state for ring-3.
6814	*/
6815	static void vmsvgaR3InitFIFO(PVGASTATE pThis, PVGASTATECC pThisCC)
6816	{
6817	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6818
6819	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6820	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6821	}
6822
6823	# ifdef VBOX_WITH_VMSVGA3D
6824	/**
6825	* Tweak the host 3D capabilities (pThis->svga.au32DevCaps).
6826	*
6827	* @returns VBox status code.
6828	* @param pThis The shared VGA/VMSVGA instance data.
6829	* @param pThisCC The VGA/VMSVGA state for ring-3.
6830	*/
6831	static void vmsvgaR3Censor3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6832	{
6833	RT_NOREF(pThisCC);
6834
6835	/*
6836	* Hide extended VBoxSVGA capabilities if they are not enabled.
6837	*/
6838	if (!pThis->svga.fVBoxExtensions)
6839	pThis->svga.au32DevCaps[SVGA3D_DEVCAP_3D] &= VBSVGA3D_CAP_3D;
6840
6841	/*
6842	* D3D11 does not support multisampling for a number of formats:
6843	* https://learn.microsoft.com/en-us/windows/win32/direct3ddxgi/format-support-for-direct3d-11-1-feature-level-hardware
6844	* "Format support for Direct3D Feature Level 11.1 hardware"
6845	* Implementations on non-Windows hosts may report such support.
6846	* Windows 11 guest actually checks this.
6847	*/
6848	static const uint32_t aDevCapNoMsaa[] =
6849	{
6850	SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24,
6851	SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT,
6852	SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM,
6853	SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8,
6854	SVGA3D_DEVCAP_DXFMT_X24_G8_UINT,
6855	SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
6856	SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM,
6857	SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM,
6858	SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
6859	SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
6860	SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
6861	SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
6862	SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
6863	SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
6864	SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
6865	SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
6866	SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
6867	SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
6868	SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
6869	SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
6870	SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
6871	SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
6872	SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
6873	SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
6874	SVGA3D_DEVCAP_DXFMT_BC6H_UF16,
6875	SVGA3D_DEVCAP_DXFMT_BC6H_SF16,
6876	SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS,
6877	SVGA3D_DEVCAP_DXFMT_BC7_UNORM,
6878	SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB,
6879	SVGA3D_DEVCAP_DXFMT_NV12,
6880	SVGA3D_DEVCAP_DXFMT_YUY2,
6881	SVGA3D_DEVCAP_DXFMT_P8
6882	};
6883
6884	for (unsigned i = 0; i < RT_ELEMENTS(aDevCapNoMsaa); ++i)
6885	pThis->svga.au32DevCaps[aDevCapNoMsaa[i]] &= ~SVGA3D_DXFMT_MULTISAMPLE;
6886
6887	/*
6888	* Formats belonging to the same group must have the same multisample capability.
6889	*/
6890	static const uint32_t aDevCapR32G32B32A32[] =
6891	{
6892	SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
6893	SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
6894	SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
6895	SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT
6896	};
6897
6898	static const uint32_t aDevCapR32G32B32[] =
6899	{
6900	SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
6901	SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
6902	SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
6903	SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT
6904	};
6905
6906	static const uint32_t aDevCapR16G16B16A16[] =
6907	{
6908	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
6909	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
6910	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
6911	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
6912	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
6913	SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM
6914	};
6915
6916	static const uint32_t aDevCapR32G32[] =
6917	{
6918	SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
6919	SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
6920	SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
6921	SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT
6922	};
6923
6924	static const uint32_t aDevCapR32G8X24[] =
6925	{
6926	SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
6927	SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT
6928	};
6929
6930	static const uint32_t aDevCapR10G10B10A2[] =
6931	{
6932	SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
6933	SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
6934	SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM
6935	};
6936
6937	static const uint32_t aDevCapR8G8B8A8[] =
6938	{
6939	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
6940	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
6941	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
6942	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
6943	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
6944	SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM
6945	};
6946
6947	static const uint32_t aDevCapR16G16[] =
6948	{
6949	SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
6950	SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
6951	SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
6952	SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
6953	SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
6954	SVGA3D_DEVCAP_DXFMT_R16G16_SNORM
6955	};
6956
6957	static const uint32_t aDevCapR32[] =
6958	{
6959	SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
6960	SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
6961	SVGA3D_DEVCAP_DXFMT_R32_UINT,
6962	SVGA3D_DEVCAP_DXFMT_R32_SINT,
6963	SVGA3D_DEVCAP_DXFMT_R32_FLOAT
6964	};
6965
6966	static const uint32_t aDevCapR24G8[] =
6967	{
6968	SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
6969	SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT
6970	};
6971
6972	static const uint32_t aDevCapR8G8[] =
6973	{
6974	SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
6975	SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
6976	SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
6977	SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
6978	SVGA3D_DEVCAP_DXFMT_R8G8_SNORM
6979	};
6980
6981	static const uint32_t aDevCapR16[] =
6982	{
6983	SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
6984	SVGA3D_DEVCAP_DXFMT_R16_UNORM,
6985	SVGA3D_DEVCAP_DXFMT_R16_UINT,
6986	SVGA3D_DEVCAP_DXFMT_R16_SNORM,
6987	SVGA3D_DEVCAP_DXFMT_R16_SINT,
6988	SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
6989	SVGA3D_DEVCAP_DXFMT_D16_UNORM
6990	};
6991
6992	static const uint32_t aDevCapR8[] =
6993	{
6994	SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
6995	SVGA3D_DEVCAP_DXFMT_R8_UNORM,
6996	SVGA3D_DEVCAP_DXFMT_R8_UINT,
6997	SVGA3D_DEVCAP_DXFMT_R8_SNORM,
6998	SVGA3D_DEVCAP_DXFMT_R8_SINT
6999	};
7000
7001	static const uint32_t aDevCapB8G8R8A8[] =
7002	{
7003	SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
7004	SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
7005	SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM
7006	};
7007
7008	static const uint32_t aDevCapB8G8R8X8[] =
7009	{
7010	SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
7011	SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
7012	SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM
7013	};
7014
7015	typedef struct _FormatGroup
7016	{
7017	uint32_t cFormats;
7018	uint32_t const *pau32DevCaps;
7019	char const *szGroupName;
7020	} FormatGroup;
7021
7022	#define FORMAT_GROUP_ENTRY(aFormat) { RT_ELEMENTS(aDevCap##aFormat), aDevCap##aFormat, #aFormat }
7023	static const FormatGroup aFormatGroup[] =
7024	{
7025	FORMAT_GROUP_ENTRY(R32G32B32A32),
7026	FORMAT_GROUP_ENTRY(R32G32B32),
7027	FORMAT_GROUP_ENTRY(R16G16B16A16),
7028	FORMAT_GROUP_ENTRY(R32G32),
7029	FORMAT_GROUP_ENTRY(R32G8X24),
7030	FORMAT_GROUP_ENTRY(R10G10B10A2),
7031	FORMAT_GROUP_ENTRY(R8G8B8A8),
7032	FORMAT_GROUP_ENTRY(R16G16),
7033	FORMAT_GROUP_ENTRY(R32),
7034	FORMAT_GROUP_ENTRY(R24G8),
7035	FORMAT_GROUP_ENTRY(R8G8),
7036	FORMAT_GROUP_ENTRY(R16),
7037	FORMAT_GROUP_ENTRY(R8),
7038	FORMAT_GROUP_ENTRY(B8G8R8A8),
7039	FORMAT_GROUP_ENTRY(B8G8R8X8)
7040	};
7041	#undef FORMAT_GROUP_ENTRY
7042
7043	for (unsigned iGroup = 0; iGroup < RT_ELEMENTS(aFormatGroup); ++iGroup)
7044	{
7045	FormatGroup const *pGroup = &aFormatGroup[iGroup];
7046
7047	/* Verify that all formats have the same MSAA capability. */
7048	uint32_t const fMSAA = pThis->svga.au32DevCaps[pGroup->pau32DevCaps[0]] & SVGA3D_DXFMT_MULTISAMPLE;
7049	for (unsigned i = 1; i < pGroup->cFormats; ++i)
7050	{
7051	if (fMSAA != (pThis->svga.au32DevCaps[pGroup->pau32DevCaps[i]] & SVGA3D_DXFMT_MULTISAMPLE))
7052	{
7053	/* If different MSAA capabilities have been detected. then disable MSAA for the group. */
7054	LogRel(("VMSVGA3d: disabling MSAA for %s\n", pGroup->szGroupName));
7055	for (unsigned j = 0; j < pGroup->cFormats; ++j)
7056	pThis->svga.au32DevCaps[pGroup->pau32DevCaps[j]] &= ~SVGA3D_DXFMT_MULTISAMPLE;
7057	break;
7058	}
7059	}
7060	}
7061	}
7062
7063	/**
7064	* Initializes the host 3D capabilities (pThis->svga.au32DevCaps).
7065	*
7066	* @returns VBox status code.
7067	* @param pThis The shared VGA/VMSVGA instance data.
7068	* @param pThisCC The VGA/VMSVGA state for ring-3.
7069	*/
7070	static void vmsvgaR3Init3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
7071	{
7072	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
7073
7074	uint32_t au32FailedCapsBitmap[(RT_ELEMENTS(pThis->svga.au32DevCaps) + 31) / 32];
7075	RT_ZERO(au32FailedCapsBitmap);
7076
7077	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
7078	{
7079	uint32_t val = 0;
7080	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
7081	if (RT_SUCCESS(rc))
7082	pThis->svga.au32DevCaps[i] = val;
7083	else
7084	{
7085	ASMBitSet(au32FailedCapsBitmap, i);
7086	pThis->svga.au32DevCaps[i] = 0;
7087	}
7088	}
7089
7090	vmsvgaR3Censor3DCaps(pThis, pThisCC);
7091
7092	bool const fSavedBuffering = RTLogRelSetBuffering(true);
7093
7094	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
7095	{
7096	/* LogRel the capability value. */
7097	uint32_t const val = pThis->svga.au32DevCaps[i];
7098	if (i < SVGA3D_DEVCAP_MAX)
7099	{
7100	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
7101	if (!ASMBitTest(au32FailedCapsBitmap, i))
7102	{
7103	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
7104	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
7105	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
7106	{
7107	float const fval = (float )&val;
7108	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
7109	}
7110	else
7111	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
7112	}
7113	else
7114	LogRel(("VMSVGA3d: cap[%u]=%#010x -{%s}\n", i, val, pszDevCapName));
7115	}
7116	else
7117	LogRel(("VMSVGA3d: new cap[%u]=%#010x%s\n", i, val, ASMBitTest(au32FailedCapsBitmap, i) ? " -" : ""));
7118	}
7119
7120	RTLogRelSetBuffering(fSavedBuffering);
7121	}
7122
7123
7124	/**
7125	* Write the host 3D capabilities to FIFO memory.
7126	* Must be called after vmsvgaR3Init3DCaps.
7127	*
7128	* @returns VBox status code.
7129	* @param pThis The shared VGA/VMSVGA instance data.
7130	* @param pThisCC The VGA/VMSVGA state for ring-3.
7131	*/
7132	static void vmsvgaR3InitFIFO3D(PVGASTATE pThis, PVGASTATECC pThisCC)
7133	{
7134	/* 3d hardware version; latest and greatest */
7135	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
7136	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
7137
7138	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
7139	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
7140	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
7141	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
7142	*/
7143	SVGA3dCapsRecord *pCaps;
7144	SVGA3dCapPair *pData;
7145
7146	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
7147	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
7148	pData = (SVGA3dCapPair *)&pCaps->data;
7149
7150	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
7151	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
7152	{
7153	pData[i][0] = i;
7154	pData[i][1] = pThis->svga.au32DevCaps[i];
7155	}
7156	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
7157	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
7158
7159	/* Mark end of record array (a zero word). */
7160	pCaps->header.length = 0;
7161	}
7162	# endif /* VBOX_WITH_VMSVGA3D */
7163
7164	/**
7165	* Resets the SVGA hardware state
7166	*
7167	* @returns VBox status code.
7168	* @param pDevIns The device instance.
7169	*/
7170	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
7171	{
7172	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7173	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7174	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7175
7176	/* Reset before init? */
7177	if (!pSVGAState)
7178	return VINF_SUCCESS;
7179
7180	Log(("vmsvgaR3Reset\n"));
7181
7182	if (!pThis->fVmSvga3)
7183	{
7184	/* Reset the FIFO processing as well as the 3d state (if we have one). */
7185	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
7186	}
7187
7188	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* Hack around lock order issue. FIFO thread might take the lock. */
7189
7190	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 60000 /ms/);
7191	AssertLogRelRC(rc);
7192
7193	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
7194	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
7195
7196	/* Reset other stuff. */
7197	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
7198	RT_ZERO(pThis->svga.au32ScratchRegion);
7199
7200	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
7201
7202	vmsvgaR3StateTerm(pThis, pThisCC);
7203	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
7204
7205	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
7206
7207	if (!pThis->fVmSvga3)
7208	vmsvgaR3InitFIFO(pThis, pThisCC);
7209
7210	/* Initialize FIFO and register capabilities. */
7211	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThis->svga.u32DeviceCaps2, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
7212
7213	# ifdef VBOX_WITH_VMSVGA3D
7214	if (pThis->svga.f3DEnabled)
7215	{
7216	vmsvgaR3Init3DCaps(pThis, pThisCC);
7217	if (!pThis->fVmSvga3)
7218	vmsvgaR3InitFIFO3D(pThis, pThisCC);
7219	}
7220	# endif
7221
7222	/* VRAM tracking is enabled by default during bootup. */
7223	pThis->svga.fVRAMTracking = true;
7224	pThis->svga.fEnabled = false;
7225
7226	/* Invalidate current settings. */
7227	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
7228	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
7229	pThis->svga.uBpp = pThis->svga.uHostBpp;
7230	pThis->svga.cbScanline = 0;
7231	pThis->svga.u32PitchLock = 0;
7232
7233	return rc;
7234	}
7235
7236	/**
7237	* Cleans up the SVGA hardware state
7238	*
7239	* @returns VBox status code.
7240	* @param pDevIns The device instance.
7241	*/
7242	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
7243	{
7244	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7245	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7246
7247	/*
7248	* Ask the FIFO thread to terminate the 3d state and then terminate it.
7249	*/
7250	if (pThisCC->svga.pFIFOIOThread)
7251	{
7252	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
7253	NULL /pvParam/, 30000 /ms/);
7254	AssertLogRelRC(rc);
7255
7256	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
7257	AssertLogRelRC(rc);
7258	pThisCC->svga.pFIFOIOThread = NULL;
7259	}
7260
7261	/*
7262	* Destroy the special SVGA state.
7263	*/
7264	if (pThisCC->svga.pSvgaR3State)
7265	{
7266	vmsvgaR3StateTerm(pThis, pThisCC);
7267
7268	# ifdef VBOX_WITH_VMSVGA3D
7269	vmsvga3dR3Free3dInterfaces(pThisCC);
7270	# endif
7271
7272	RTMemFree(pThisCC->svga.pSvgaR3State);
7273	pThisCC->svga.pSvgaR3State = NULL;
7274	}
7275
7276	/*
7277	* Free our resources residing in the VGA state.
7278	*/
7279	if (pThisCC->svga.pbVgaFrameBufferR3)
7280	{
7281	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
7282	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
7283	}
7284	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
7285	{
7286	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
7287	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
7288	}
7289	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
7290	{
7291	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
7292	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
7293	}
7294
7295	return VINF_SUCCESS;
7296	}
7297
7298	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
7299	const char pszType, void const pvValue,
7300	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
7301	{
7302	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
7303	double const v = (double )&pvValue;
7304	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
7305	}
7306
7307	/**
7308	* Initialize the SVGA hardware state
7309	*
7310	* @returns VBox status code.
7311	* @param pDevIns The device instance.
7312	*/
7313	int vmsvgaR3Init(PPDMDEVINS pDevIns)
7314	{
7315	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7316	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7317	PVMSVGAR3STATE pSVGAState;
7318	int rc;
7319
7320	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
7321	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
7322
7323	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
7324	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
7325
7326	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
7327
7328	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
7329	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
7330	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
7331
7332	/* Create event semaphore. */
7333	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
7334	AssertRCReturn(rc, rc);
7335
7336	/* Create event semaphore. */
7337	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
7338	AssertRCReturn(rc, rc);
7339
7340	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
7341	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
7342
7343	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
7344	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
7345
7346	pSVGAState = pThisCC->svga.pSvgaR3State;
7347
7348	/* VRAM tracking is enabled by default during bootup. */
7349	pThis->svga.fVRAMTracking = true;
7350
7351	/* Set up the host bpp. This value is as a default for the programmable
7352	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
7353	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
7354	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
7355	*
7356	* NB: The driver cBits value is currently constant for the lifetime of the
7357	* VM. If that changes, the host bpp logic might need revisiting.
7358	*/
7359	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
7360
7361	/* Invalidate current settings. */
7362	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
7363	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
7364	pThis->svga.uBpp = pThis->svga.uHostBpp;
7365	pThis->svga.cbScanline = 0;
7366
7367	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
7368	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
7369	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
7370	{
7371	pThis->svga.u32MaxWidth -= 256;
7372	pThis->svga.u32MaxHeight -= 256;
7373	}
7374	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
7375
7376	/* VBox commands and capabilities are always enabled for VirtualBox PCI device. */
7377	pThis->svga.fVBoxExtensions = !pThis->fVMSVGAPciId;
7378
7379	# ifdef DEBUG_GMR_ACCESS
7380	/* Register the GMR access handler type. */
7381	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GmrAccessHandler,
7382	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
7383	AssertRCReturn(rc, rc);
7384	# endif
7385
7386	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7387	/* Register the FIFO access handler type. In addition to debugging FIFO
7388	access, this is also used to facilitate extended fifo thread sleeps. */
7389	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns,
7390	# ifdef DEBUG_FIFO_ACCESS
7391	PGMPHYSHANDLERKIND_ALL,
7392	# else
7393	PGMPHYSHANDLERKIND_WRITE,
7394	# endif
7395	vmsvgaR3FifoAccessHandler,
7396	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
7397	AssertRCReturn(rc, rc);
7398	# endif
7399
7400	/* Create the async IO thread. */
7401	if (pThis->fVmSvga3)
7402	{
7403	/*
7404	* For SVGA 3 we use a different command processing loop because the standard FIFO loop would get riddled with
7405	* if (pThis->fVmsvga3) otherwise
7406	*/
7407	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3CmdBufLoop, vmsvgaR3FifoLoopWakeUp, 0,
7408	RTTHREADTYPE_IO, "VMSVGA CMD");
7409	}
7410	else
7411	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
7412	RTTHREADTYPE_IO, "VMSVGA FIFO");
7413	if (RT_FAILURE(rc))
7414	{
7415	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
7416	return rc;
7417	}
7418
7419	/*
7420	* Statistics.
7421	*/
7422	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
7423	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
7424	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
7425	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
7426	# ifdef VBOX_WITH_STATISTICS
7427	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
7428	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
7429	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
7430	# endif
7431	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
7432	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
7433	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
7434	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
7435	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
7436	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
7437	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
7438	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
7439	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
7440	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
7441	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
7442	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
7443	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
7444	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
7445	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
7446	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
7447	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
7448	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
7449	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
7450	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
7451	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
7452	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
7453	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
7454	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
7455	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
7456	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
7457	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
7458	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
7459	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
7460	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
7461	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
7462	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
7463	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
7464	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
7465	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
7466	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
7467	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
7468	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
7469	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
7470	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
7471	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
7472	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
7473	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
7474	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
7475	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
7476	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
7477	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
7478	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
7479	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
7480	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
7481	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
7482	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
7483	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
7484	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
7485	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
7486	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
7487	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
7488	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
7489	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
7490
7491	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
7492	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
7493	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
7494	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
7495	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
7496	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
7497	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
7498	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
7499	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
7500	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
7501	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
7502	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
7503	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
7504	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
7505	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
7506	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
7507	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
7508	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
7509	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
7510	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
7511	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
7512	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
7513	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
7514	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
7515	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
7516	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
7517	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
7518	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
7519	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
7520	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
7521	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
7522	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
7523	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
7524	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
7525	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
7526	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
7527	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
7528	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
7529	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
7530	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
7531
7532	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
7533	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
7534	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
7535	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
7536	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
7537	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
7538	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
7539	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
7540	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
7541	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
7542	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
7543	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
7544	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
7545	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
7546	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
7547	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
7548	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
7549	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
7550	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
7551	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
7552	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
7553	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
7554	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
7555	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
7556	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
7557	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
7558	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
7559	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
7560	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
7561	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
7562	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
7563	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
7564	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
7565	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
7566	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
7567	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
7568	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
7569	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
7570	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
7571	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
7572	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
7573	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
7574	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
7575	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
7576	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
7577	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
7578	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
7579	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
7580	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
7581	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
7582	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
7583	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
7584	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
7585	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
7586	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
7587	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
7588	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
7589	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
7590	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
7591	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
7592	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
7593	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
7594
7595	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
7596	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
7597	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
7598	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
7599	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
7600	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
7601	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
7602	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
7603	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7604	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
7605	# endif
7606	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
7607	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
7608	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
7609	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
7610	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
7611
7612	# undef REG_CNT
7613	# undef REG_PRF
7614
7615	/*
7616	* Info handlers.
7617	*/
7618	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
7619	# ifdef VBOX_WITH_VMSVGA3D
7620	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
7621	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
7622	"VMSVGA 3d surface details. "
7623	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
7624	vmsvgaR3Info3dSurface);
7625	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
7626	"VMSVGA 3d surface details and bitmap: "
7627	"sid[>dir]",
7628	vmsvgaR3Info3dSurfaceBmp);
7629	# endif
7630
7631	return VINF_SUCCESS;
7632	}
7633
7634	/* Initialize 3D backend, set device capabilities and call pfnPowerOn callback of 3D backend.
7635	*
7636	* @param pDevIns The device instance.
7637	* @param pThis The shared VGA/VMSVGA instance data.
7638	* @param pThisCC The VGA/VMSVGA state for ring-3.
7639	* @param fLoadState Whether saved state is being loaded.
7640	*/
7641	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState)
7642	{
7643	# ifdef VBOX_WITH_VMSVGA3D
7644	if (pThis->svga.f3DEnabled \|\| pThis->svga.fVMSVGA2dGBO)
7645	{
7646	/* Load a 3D backend. */
7647	int rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
7648	if (RT_FAILURE(rc))
7649	{
7650	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
7651	pThis->svga.f3DEnabled = false;
7652	}
7653	}
7654	# endif
7655
7656	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
7657	if (pThis->svga.f3DEnabled)
7658	{
7659	/* The FIFO thread may use X API for accelerated screen output. */
7660	/* This must be done after backend initialization by vmsvgaR3Init3dInterfaces,
7661	* because it dynamically resolves XInitThreads.
7662	*/
7663	XInitThreads();
7664	}
7665	# endif
7666
7667	if (!fLoadState)
7668	{
7669	if (!pThis->fVmSvga3)
7670	vmsvgaR3InitFIFO(pThis, pThisCC);
7671	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThis->svga.u32DeviceCaps2, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
7672	}
7673	# ifdef DEBUG
7674	else
7675	{
7676	/* If saved state is being loaded then FIFO and caps are already restored. */
7677	uint32_t u32DeviceCaps = 0;
7678	uint32_t u32DeviceCaps2 = 0;
7679	uint32_t u32FIFOCaps = 0;
7680	vmsvgaR3GetCaps(pThis, pThisCC, &u32DeviceCaps, &u32DeviceCaps2, &u32FIFOCaps);
7681
7682	/* Capabilities should not change normally.
7683	* However the saved state might have a subset of currently implemented caps.
7684	*/
7685	Assert( (pThis->svga.u32DeviceCaps & u32DeviceCaps) == pThis->svga.u32DeviceCaps
7686	&& (pThis->svga.u32DeviceCaps2 & u32DeviceCaps2) == pThis->svga.u32DeviceCaps2
7687	&& ( pThis->fVmSvga3
7688	\|\| (pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] & u32FIFOCaps) == pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]));
7689	}
7690	#endif
7691
7692	# ifdef VBOX_WITH_VMSVGA3D
7693	if (pThis->svga.f3DEnabled \|\| pThis->svga.fVMSVGA2dGBO)
7694	{
7695	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7696	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
7697	if (RT_SUCCESS(rc))
7698	{
7699	/* Initialize 3D capabilities. */
7700	vmsvgaR3Init3DCaps(pThis, pThisCC);
7701	if (!pThis->fVmSvga3)
7702	vmsvgaR3InitFIFO3D(pThis, pThisCC);
7703	}
7704	else
7705	{
7706	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
7707	pThis->svga.f3DEnabled = false;
7708	}
7709	}
7710	# else /* !VBOX_WITH_VMSVGA3D */
7711	RT_NOREF(pDevIns);
7712	# endif /* !VBOX_WITH_VMSVGA3D */
7713	}
7714
7715
7716	/**
7717	* Power On notification.
7718	*
7719	* @param pDevIns The device instance data.
7720	*
7721	* @remarks Caller enters the device critical section.
7722	*/
7723	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
7724	{
7725	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7726	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7727
7728	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ false);
7729	}
7730
7731	/**
7732	* Power Off notification.
7733	*
7734	* @param pDevIns The device instance data.
7735	*
7736	* @remarks Caller enters the device critical section.
7737	*/
7738	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
7739	{
7740	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7741	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7742
7743	/*
7744	* Notify the FIFO thread.
7745	*/
7746	if (pThisCC->svga.pFIFOIOThread)
7747	{
7748	/* Hack around a deadlock:
7749	* - the caller holds the device critsect;
7750	* - FIFO thread may attempt to enter the critsect too (when raising an IRQ).
7751	*/
7752	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
7753
7754	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
7755	NULL /pvParam/, 30000 /ms/);
7756	AssertLogRelRC(rc);
7757
7758	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
7759	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
7760	}
7761	}
7762
7763	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 106221

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