VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 57518

Last change on this file since 57518 was 57517, checked in by vboxsync, 9 years ago

SVGA3d/ogl: Finally figured out the scrolling issue with the SVGA_3D_CMD_PRESENT implementation.
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1/* $Id: DevVGA-SVGA.cpp 57517 2015-08-24 22:53:20Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2015 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295
296#ifdef LOG_ENABLED
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417/**
418 * FIFO command name lookup
419 *
420 * @returns FIFO command string or "UNKNOWN"
421 * @param u32Cmd FIFO command
422 */
423static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
424{
425 switch (u32Cmd)
426 {
427 case SVGA_CMD_INVALID_CMD:
428 return "SVGA_CMD_INVALID_CMD";
429 case SVGA_CMD_UPDATE:
430 return "SVGA_CMD_UPDATE";
431 case SVGA_CMD_RECT_COPY:
432 return "SVGA_CMD_RECT_COPY";
433 case SVGA_CMD_DEFINE_CURSOR:
434 return "SVGA_CMD_DEFINE_CURSOR";
435 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
436 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
437 case SVGA_CMD_UPDATE_VERBOSE:
438 return "SVGA_CMD_UPDATE_VERBOSE";
439 case SVGA_CMD_FRONT_ROP_FILL:
440 return "SVGA_CMD_FRONT_ROP_FILL";
441 case SVGA_CMD_FENCE:
442 return "SVGA_CMD_FENCE";
443 case SVGA_CMD_ESCAPE:
444 return "SVGA_CMD_ESCAPE";
445 case SVGA_CMD_DEFINE_SCREEN:
446 return "SVGA_CMD_DEFINE_SCREEN";
447 case SVGA_CMD_DESTROY_SCREEN:
448 return "SVGA_CMD_DESTROY_SCREEN";
449 case SVGA_CMD_DEFINE_GMRFB:
450 return "SVGA_CMD_DEFINE_GMRFB";
451 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
452 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
453 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
454 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
455 case SVGA_CMD_ANNOTATION_FILL:
456 return "SVGA_CMD_ANNOTATION_FILL";
457 case SVGA_CMD_ANNOTATION_COPY:
458 return "SVGA_CMD_ANNOTATION_COPY";
459 case SVGA_CMD_DEFINE_GMR2:
460 return "SVGA_CMD_DEFINE_GMR2";
461 case SVGA_CMD_REMAP_GMR2:
462 return "SVGA_CMD_REMAP_GMR2";
463 case SVGA_3D_CMD_SURFACE_DEFINE:
464 return "SVGA_3D_CMD_SURFACE_DEFINE";
465 case SVGA_3D_CMD_SURFACE_DESTROY:
466 return "SVGA_3D_CMD_SURFACE_DESTROY";
467 case SVGA_3D_CMD_SURFACE_COPY:
468 return "SVGA_3D_CMD_SURFACE_COPY";
469 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
470 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
471 case SVGA_3D_CMD_SURFACE_DMA:
472 return "SVGA_3D_CMD_SURFACE_DMA";
473 case SVGA_3D_CMD_CONTEXT_DEFINE:
474 return "SVGA_3D_CMD_CONTEXT_DEFINE";
475 case SVGA_3D_CMD_CONTEXT_DESTROY:
476 return "SVGA_3D_CMD_CONTEXT_DESTROY";
477 case SVGA_3D_CMD_SETTRANSFORM:
478 return "SVGA_3D_CMD_SETTRANSFORM";
479 case SVGA_3D_CMD_SETZRANGE:
480 return "SVGA_3D_CMD_SETZRANGE";
481 case SVGA_3D_CMD_SETRENDERSTATE:
482 return "SVGA_3D_CMD_SETRENDERSTATE";
483 case SVGA_3D_CMD_SETRENDERTARGET:
484 return "SVGA_3D_CMD_SETRENDERTARGET";
485 case SVGA_3D_CMD_SETTEXTURESTATE:
486 return "SVGA_3D_CMD_SETTEXTURESTATE";
487 case SVGA_3D_CMD_SETMATERIAL:
488 return "SVGA_3D_CMD_SETMATERIAL";
489 case SVGA_3D_CMD_SETLIGHTDATA:
490 return "SVGA_3D_CMD_SETLIGHTDATA";
491 case SVGA_3D_CMD_SETLIGHTENABLED:
492 return "SVGA_3D_CMD_SETLIGHTENABLED";
493 case SVGA_3D_CMD_SETVIEWPORT:
494 return "SVGA_3D_CMD_SETVIEWPORT";
495 case SVGA_3D_CMD_SETCLIPPLANE:
496 return "SVGA_3D_CMD_SETCLIPPLANE";
497 case SVGA_3D_CMD_CLEAR:
498 return "SVGA_3D_CMD_CLEAR";
499 case SVGA_3D_CMD_PRESENT:
500 return "SVGA_3D_CMD_PRESENT";
501 case SVGA_3D_CMD_SHADER_DEFINE:
502 return "SVGA_3D_CMD_SHADER_DEFINE";
503 case SVGA_3D_CMD_SHADER_DESTROY:
504 return "SVGA_3D_CMD_SHADER_DESTROY";
505 case SVGA_3D_CMD_SET_SHADER:
506 return "SVGA_3D_CMD_SET_SHADER";
507 case SVGA_3D_CMD_SET_SHADER_CONST:
508 return "SVGA_3D_CMD_SET_SHADER_CONST";
509 case SVGA_3D_CMD_DRAW_PRIMITIVES:
510 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
511 case SVGA_3D_CMD_SETSCISSORRECT:
512 return "SVGA_3D_CMD_SETSCISSORRECT";
513 case SVGA_3D_CMD_BEGIN_QUERY:
514 return "SVGA_3D_CMD_BEGIN_QUERY";
515 case SVGA_3D_CMD_END_QUERY:
516 return "SVGA_3D_CMD_END_QUERY";
517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
518 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
519 case SVGA_3D_CMD_PRESENT_READBACK:
520 return "SVGA_3D_CMD_PRESENT_READBACK";
521 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
522 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
523 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
524 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
525 case SVGA_3D_CMD_GENERATE_MIPMAPS:
526 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
527 case SVGA_3D_CMD_ACTIVATE_SURFACE:
528 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
529 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
530 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
531 default:
532 return "UNKNOWN";
533 }
534}
535#endif
536
537/**
538 * @interface_method_impl{PDMIDISPLAYPORT::pfnSetViewport}
539 */
540DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
541{
542 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
543
544 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
545
546 if (x < pThis->svga.uWidth)
547 {
548 pThis->svga.viewport.x = x;
549 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
550 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
551 }
552 else
553 {
554 pThis->svga.viewport.x = pThis->svga.uWidth;
555 pThis->svga.viewport.cx = 0;
556 pThis->svga.viewport.xRight = pThis->svga.uWidth;
557 }
558 if (y < pThis->svga.uHeight)
559 {
560 pThis->svga.viewport.y = y;
561 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
562 pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
563 pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
564 }
565 else
566 {
567 pThis->svga.viewport.y = pThis->svga.uHeight;
568 pThis->svga.viewport.cy = 0;
569 pThis->svga.viewport.yLowWC = 0;
570 pThis->svga.viewport.yHighWC = 0;
571 }
572}
573
574/**
575 * Read port register
576 *
577 * @returns VBox status code.
578 * @param pThis VMSVGA State
579 * @param pu32 Where to store the read value
580 */
581PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
582{
583 int rc = VINF_SUCCESS;
584
585 *pu32 = 0;
586 switch (pThis->svga.u32IndexReg)
587 {
588 case SVGA_REG_ID:
589 *pu32 = pThis->svga.u32SVGAId;
590 break;
591
592 case SVGA_REG_ENABLE:
593 *pu32 = pThis->svga.fEnabled;
594 break;
595
596 case SVGA_REG_WIDTH:
597 {
598 if ( pThis->svga.fEnabled
599 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
600 {
601 *pu32 = pThis->svga.uWidth;
602 }
603 else
604 {
605#ifndef IN_RING3
606 rc = VINF_IOM_R3_IOPORT_READ;
607#else
608 *pu32 = pThis->pDrv->cx;
609#endif
610 }
611 break;
612 }
613
614 case SVGA_REG_HEIGHT:
615 {
616 if ( pThis->svga.fEnabled
617 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
618 {
619 *pu32 = pThis->svga.uHeight;
620 }
621 else
622 {
623#ifndef IN_RING3
624 rc = VINF_IOM_R3_IOPORT_READ;
625#else
626 *pu32 = pThis->pDrv->cy;
627#endif
628 }
629 break;
630 }
631
632 case SVGA_REG_MAX_WIDTH:
633 *pu32 = pThis->svga.u32MaxWidth;
634 break;
635
636 case SVGA_REG_MAX_HEIGHT:
637 *pu32 = pThis->svga.u32MaxHeight;
638 break;
639
640 case SVGA_REG_DEPTH:
641 /* This returns the color depth of the current mode. */
642 switch (pThis->svga.uBpp)
643 {
644 case 15:
645 case 16:
646 case 24:
647 *pu32 = pThis->svga.uBpp;
648 break;
649
650 default:
651 case 32:
652 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
653 break;
654 }
655 break;
656
657 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
658 if ( pThis->svga.fEnabled
659 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
660 {
661 *pu32 = pThis->svga.uBpp;
662 }
663 else
664 {
665#ifndef IN_RING3
666 rc = VINF_IOM_R3_IOPORT_READ;
667#else
668 *pu32 = pThis->pDrv->cBits;
669#endif
670 }
671 break;
672
673 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
674 if ( pThis->svga.fEnabled
675 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
676 {
677 *pu32 = (pThis->svga.uBpp + 7) & ~7;
678 }
679 else
680 {
681#ifndef IN_RING3
682 rc = VINF_IOM_R3_IOPORT_READ;
683#else
684 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
685#endif
686 }
687 break;
688
689 case SVGA_REG_PSEUDOCOLOR:
690 *pu32 = 0;
691 break;
692
693 case SVGA_REG_RED_MASK:
694 case SVGA_REG_GREEN_MASK:
695 case SVGA_REG_BLUE_MASK:
696 {
697 uint32_t uBpp;
698
699 if ( pThis->svga.fEnabled
700 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
701 {
702 uBpp = pThis->svga.uBpp;
703 }
704 else
705 {
706#ifndef IN_RING3
707 rc = VINF_IOM_R3_IOPORT_READ;
708 break;
709#else
710 uBpp = pThis->pDrv->cBits;
711#endif
712 }
713 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
714 switch (uBpp)
715 {
716 case 8:
717 u32RedMask = 0x07;
718 u32GreenMask = 0x38;
719 u32BlueMask = 0xc0;
720 break;
721
722 case 15:
723 u32RedMask = 0x0000001f;
724 u32GreenMask = 0x000003e0;
725 u32BlueMask = 0x00007c00;
726 break;
727
728 case 16:
729 u32RedMask = 0x0000001f;
730 u32GreenMask = 0x000007e0;
731 u32BlueMask = 0x0000f800;
732 break;
733
734 case 24:
735 case 32:
736 default:
737 u32RedMask = 0x00ff0000;
738 u32GreenMask = 0x0000ff00;
739 u32BlueMask = 0x000000ff;
740 break;
741 }
742 switch (pThis->svga.u32IndexReg)
743 {
744 case SVGA_REG_RED_MASK:
745 *pu32 = u32RedMask;
746 break;
747
748 case SVGA_REG_GREEN_MASK:
749 *pu32 = u32GreenMask;
750 break;
751
752 case SVGA_REG_BLUE_MASK:
753 *pu32 = u32BlueMask;
754 break;
755 }
756 break;
757 }
758
759 case SVGA_REG_BYTES_PER_LINE:
760 {
761 if ( pThis->svga.fEnabled
762 && pThis->svga.cbScanline)
763 {
764 *pu32 = pThis->svga.cbScanline;
765 }
766 else
767 {
768#ifndef IN_RING3
769 rc = VINF_IOM_R3_IOPORT_READ;
770#else
771 *pu32 = pThis->pDrv->cbScanline;
772#endif
773 }
774 break;
775 }
776
777 case SVGA_REG_VRAM_SIZE: /* VRAM size */
778 *pu32 = pThis->vram_size;
779 break;
780
781 case SVGA_REG_FB_START: /* Frame buffer physical address. */
782 Assert(pThis->GCPhysVRAM <= 0xffffffff);
783 *pu32 = pThis->GCPhysVRAM;
784 break;
785
786 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
787 /* Always zero in our case. */
788 *pu32 = 0;
789 break;
790
791 case SVGA_REG_FB_SIZE: /* Frame buffer size */
792 {
793#ifndef IN_RING3
794 rc = VINF_IOM_R3_IOPORT_READ;
795#else
796 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
797 if ( pThis->svga.fEnabled
798 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
799 {
800 /* Hardware enabled; return real framebuffer size .*/
801 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
802 }
803 else
804 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
805
806 *pu32 = RT_MIN(pThis->vram_size, *pu32);
807 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
808#endif
809 break;
810 }
811
812 case SVGA_REG_CAPABILITIES:
813 *pu32 = pThis->svga.u32RegCaps;
814 break;
815
816 case SVGA_REG_MEM_START: /* FIFO start */
817 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
818 *pu32 = pThis->svga.GCPhysFIFO;
819 break;
820
821 case SVGA_REG_MEM_SIZE: /* FIFO size */
822 *pu32 = pThis->svga.cbFIFO;
823 break;
824
825 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
826 *pu32 = pThis->svga.fConfigured;
827 break;
828
829 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
830 *pu32 = 0;
831 break;
832
833 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
834 if (pThis->svga.fBusy)
835 {
836#ifndef IN_RING3
837 /* Go to ring-3 and halt the CPU. */
838 rc = VINF_IOM_R3_IOPORT_READ;
839 break;
840#elif defined(VMSVGA_USE_EMT_HALT_CODE)
841 /* The guest is basically doing a HLT via the device here, but with
842 a special wake up condition on FIFO completion. */
843 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
844 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
845 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
846 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
847 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
848 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
849 if (pThis->svga.fBusy)
850 rc = VMR3WaitForDeviceReady(pVM, idCpu);
851 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
852 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
853#else
854
855 /* Delay the EMT a bit so the FIFO and others can get some work done.
856 This used to be a crude 50 ms sleep. The current code tries to be
857 more efficient, but the consept is still very crude. */
858 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
859 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
860 RTThreadYield();
861 if (pThis->svga.fBusy)
862 {
863 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
864
865 if (pThis->svga.fBusy && cRefs == 1)
866 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
867 if (pThis->svga.fBusy)
868 {
869 /** @todo If this code is going to stay, we need to call into the halt/wait
870 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
871 * suffer when the guest is polling on a busy FIFO. */
872 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
873 if (cNsMaxWait >= RT_NS_100US)
874 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
875 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
876 RT_MIN(cNsMaxWait, RT_NS_10MS));
877 }
878
879 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
880 }
881 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
882#endif
883 *pu32 = pThis->svga.fBusy != 0;
884 }
885 else
886 *pu32 = false;
887 break;
888
889 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
890 *pu32 = pThis->svga.u32GuestId;
891 break;
892
893 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
894 *pu32 = pThis->svga.cScratchRegion;
895 break;
896
897 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
898 *pu32 = SVGA_FIFO_NUM_REGS;
899 break;
900
901 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
902 *pu32 = pThis->svga.u32PitchLock;
903 break;
904
905 case SVGA_REG_IRQMASK: /* Interrupt mask */
906 *pu32 = pThis->svga.u32IrqMask;
907 break;
908
909 /* See "Guest memory regions" below. */
910 case SVGA_REG_GMR_ID:
911 *pu32 = pThis->svga.u32CurrentGMRId;
912 break;
913
914 case SVGA_REG_GMR_DESCRIPTOR:
915 /* Write only */
916 *pu32 = 0;
917 break;
918
919 case SVGA_REG_GMR_MAX_IDS:
920 *pu32 = VMSVGA_MAX_GMR_IDS;
921 break;
922
923 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
924 *pu32 = VMSVGA_MAX_GMR_PAGES;
925 break;
926
927 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
928 *pu32 = pThis->svga.fTraces;
929 break;
930
931 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
932 *pu32 = VMSVGA_MAX_GMR_PAGES;
933 break;
934
935 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
936 *pu32 = VMSVGA_SURFACE_SIZE;
937 break;
938
939 case SVGA_REG_TOP: /* Must be 1 more than the last register */
940 break;
941
942 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
943 break;
944 /* Next 768 (== 256*3) registers exist for colormap */
945
946 /* Mouse cursor support. */
947 case SVGA_REG_CURSOR_ID:
948 case SVGA_REG_CURSOR_X:
949 case SVGA_REG_CURSOR_Y:
950 case SVGA_REG_CURSOR_ON:
951 break;
952
953 /* Legacy multi-monitor support */
954 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
955 *pu32 = 1;
956 break;
957
958 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
959 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
960 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
961 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
962 *pu32 = 0;
963 break;
964
965 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
966 *pu32 = pThis->svga.uWidth;
967 break;
968
969 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
970 *pu32 = pThis->svga.uHeight;
971 break;
972
973 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
974 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
975 break;
976
977 default:
978 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
979 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
980 {
981 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
982 }
983 break;
984 }
985 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
986 return rc;
987}
988
989#ifdef IN_RING3
990/**
991 * Apply the current resolution settings to change the video mode.
992 *
993 * @returns VBox status code.
994 * @param pThis VMSVGA State
995 */
996int vmsvgaChangeMode(PVGASTATE pThis)
997{
998 int rc;
999
1000 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1001 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1002 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1003 {
1004 /* Mode change in progress; wait for all values to be set. */
1005 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1006 return VINF_SUCCESS;
1007 }
1008
1009 if ( pThis->svga.uWidth == 0
1010 || pThis->svga.uHeight == 0
1011 || pThis->svga.uBpp == 0)
1012 {
1013 /* Invalid mode change - BB does this early in the boot up. */
1014 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1015 return VINF_SUCCESS;
1016 }
1017
1018 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1019 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1020 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1021 && pThis->last_width == (unsigned)pThis->svga.uWidth
1022 && pThis->last_height == (unsigned)pThis->svga.uHeight
1023 )
1024 {
1025 /* Nothing to do. */
1026 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1027 return VINF_SUCCESS;
1028 }
1029
1030 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1031 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1032
1033 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1034 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1035 AssertRC(rc);
1036 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1037
1038 /* last stuff */
1039 pThis->last_bpp = pThis->svga.uBpp;
1040 pThis->last_scr_width = pThis->svga.uWidth;
1041 pThis->last_scr_height = pThis->svga.uHeight;
1042 pThis->last_width = pThis->svga.uWidth;
1043 pThis->last_height = pThis->svga.uHeight;
1044
1045 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1046
1047 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1048 if ( pThis->svga.viewport.cx == 0
1049 && pThis->svga.viewport.cy == 0)
1050 {
1051 pThis->svga.viewport.cx = pThis->svga.uWidth;
1052 pThis->svga.viewport.xRight = pThis->svga.uWidth;
1053 pThis->svga.viewport.cy = pThis->svga.uHeight;
1054 pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1055 pThis->svga.viewport.yLowWC = 0;
1056 }
1057 return VINF_SUCCESS;
1058}
1059#endif /* IN_RING3 */
1060
1061#if defined(IN_RING0) || defined(IN_RING3)
1062/**
1063 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1064 *
1065 * @param pThis The VMSVGA state.
1066 * @param fState The busy state.
1067 */
1068DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1069{
1070 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1071
1072 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1073 {
1074 /* Race / unfortunately scheduling. Highly unlikly. */
1075 uint32_t cLoops = 64;
1076 do
1077 {
1078 ASMNopPause();
1079 fState = (pThis->svga.fBusy != 0);
1080 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1081 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1082 }
1083}
1084#endif
1085
1086/**
1087 * Write port register
1088 *
1089 * @returns VBox status code.
1090 * @param pThis VMSVGA State
1091 * @param u32 Value to write
1092 */
1093PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1094{
1095#ifdef IN_RING3
1096 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1097#endif
1098 int rc = VINF_SUCCESS;
1099
1100 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1101 switch (pThis->svga.u32IndexReg)
1102 {
1103 case SVGA_REG_ID:
1104 if ( u32 == SVGA_ID_0
1105 || u32 == SVGA_ID_1
1106 || u32 == SVGA_ID_2)
1107 pThis->svga.u32SVGAId = u32;
1108 break;
1109
1110 case SVGA_REG_ENABLE:
1111 if ( pThis->svga.fEnabled == u32
1112 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1113 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1114 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1115 && pThis->last_width == (unsigned)pThis->svga.uWidth
1116 && pThis->last_height == (unsigned)pThis->svga.uHeight
1117 )
1118 /* Nothing to do. */
1119 break;
1120
1121#ifdef IN_RING3
1122 if ( u32 == 1
1123 && pThis->svga.fEnabled == false)
1124 {
1125 /* Make a backup copy of the first 32k in order to save font data etc. */
1126 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1127 }
1128
1129 pThis->svga.fEnabled = u32;
1130 if (pThis->svga.fEnabled)
1131 {
1132 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1133 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1134 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1135 {
1136 /* Keep the current mode. */
1137 pThis->svga.uWidth = pThis->pDrv->cx;
1138 pThis->svga.uHeight = pThis->pDrv->cy;
1139 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1140 }
1141
1142 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1143 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1144 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1145 {
1146 rc = vmsvgaChangeMode(pThis);
1147 AssertRCReturn(rc, rc);
1148 }
1149 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1150 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1151 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1152
1153 /* Disable or enable dirty page tracking according to the current fTraces value. */
1154 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1155 }
1156 else
1157 {
1158 /* Restore the text mode backup. */
1159 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1160
1161/* pThis->svga.uHeight = -1;
1162 pThis->svga.uWidth = -1;
1163 pThis->svga.uBpp = -1;
1164 pThis->svga.cbScanline = 0; */
1165 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1166
1167 /* Enable dirty page tracking again when going into legacy mode. */
1168 vmsvgaSetTraces(pThis, true);
1169 }
1170#else
1171 rc = VINF_IOM_R3_IOPORT_WRITE;
1172#endif
1173 break;
1174
1175 case SVGA_REG_WIDTH:
1176 if (pThis->svga.uWidth != u32)
1177 {
1178 if (pThis->svga.fEnabled)
1179 {
1180#ifdef IN_RING3
1181 pThis->svga.uWidth = u32;
1182 rc = vmsvgaChangeMode(pThis);
1183 AssertRCReturn(rc, rc);
1184#else
1185 rc = VINF_IOM_R3_IOPORT_WRITE;
1186#endif
1187 }
1188 else
1189 pThis->svga.uWidth = u32;
1190 }
1191 /* else: nop */
1192 break;
1193
1194 case SVGA_REG_HEIGHT:
1195 if (pThis->svga.uHeight != u32)
1196 {
1197 if (pThis->svga.fEnabled)
1198 {
1199#ifdef IN_RING3
1200 pThis->svga.uHeight = u32;
1201 rc = vmsvgaChangeMode(pThis);
1202 AssertRCReturn(rc, rc);
1203#else
1204 rc = VINF_IOM_R3_IOPORT_WRITE;
1205#endif
1206 }
1207 else
1208 pThis->svga.uHeight = u32;
1209 }
1210 /* else: nop */
1211 break;
1212
1213 case SVGA_REG_DEPTH:
1214 /** @todo read-only?? */
1215 break;
1216
1217 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1218 if (pThis->svga.uBpp != u32)
1219 {
1220 if (pThis->svga.fEnabled)
1221 {
1222#ifdef IN_RING3
1223 pThis->svga.uBpp = u32;
1224 rc = vmsvgaChangeMode(pThis);
1225 AssertRCReturn(rc, rc);
1226#else
1227 rc = VINF_IOM_R3_IOPORT_WRITE;
1228#endif
1229 }
1230 else
1231 pThis->svga.uBpp = u32;
1232 }
1233 /* else: nop */
1234 break;
1235
1236 case SVGA_REG_PSEUDOCOLOR:
1237 break;
1238
1239 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1240#ifdef IN_RING3
1241 pThis->svga.fConfigured = u32;
1242 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1243 if (!pThis->svga.fConfigured)
1244 {
1245 pThis->svga.fTraces = true;
1246 }
1247 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1248#else
1249 rc = VINF_IOM_R3_IOPORT_WRITE;
1250#endif
1251 break;
1252
1253 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1254 if ( pThis->svga.fEnabled
1255 && pThis->svga.fConfigured)
1256 {
1257#if defined(IN_RING3) || defined(IN_RING0)
1258 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1259 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1260 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1261 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1262
1263 /* Kick the FIFO thread to start processing commands again. */
1264 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1265#else
1266 rc = VINF_IOM_R3_IOPORT_WRITE;
1267#endif
1268 }
1269 /* else nothing to do. */
1270 else
1271 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1272
1273 break;
1274
1275 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1276 break;
1277
1278 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1279 pThis->svga.u32GuestId = u32;
1280 break;
1281
1282 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1283 pThis->svga.u32PitchLock = u32;
1284 break;
1285
1286 case SVGA_REG_IRQMASK: /* Interrupt mask */
1287 pThis->svga.u32IrqMask = u32;
1288
1289 /* Irq pending after the above change? */
1290 if (pThis->svga.u32IrqStatus & u32)
1291 {
1292 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1293 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1294 }
1295 else
1296 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1297 break;
1298
1299 /* Mouse cursor support */
1300 case SVGA_REG_CURSOR_ID:
1301 case SVGA_REG_CURSOR_X:
1302 case SVGA_REG_CURSOR_Y:
1303 case SVGA_REG_CURSOR_ON:
1304 break;
1305
1306 /* Legacy multi-monitor support */
1307 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1308 break;
1309 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1310 break;
1311 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1312 break;
1313 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1314 break;
1315 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1316 break;
1317 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1318 break;
1319 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1320 break;
1321#ifdef VBOX_WITH_VMSVGA3D
1322 /* See "Guest memory regions" below. */
1323 case SVGA_REG_GMR_ID:
1324 pThis->svga.u32CurrentGMRId = u32;
1325 break;
1326
1327 case SVGA_REG_GMR_DESCRIPTOR:
1328# ifndef IN_RING3
1329 rc = VINF_IOM_R3_IOPORT_WRITE;
1330 break;
1331# else /* IN_RING3 */
1332 {
1333 SVGAGuestMemDescriptor desc;
1334 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1335 RTGCPHYS GCPhysBase = GCPhys;
1336 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1337 uint32_t cDescriptorsAllocated = 16;
1338 uint32_t iDescriptor = 0;
1339
1340 /* Validate current GMR id. */
1341 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1342
1343 /* Free the old GMR if present. */
1344 vmsvgaGMRFree(pThis, idGMR);
1345
1346 /* Just undefine the GMR? */
1347 if (GCPhys == 0)
1348 break;
1349
1350 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1351 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1352
1353 /* Never cross a page boundary automatically. */
1354 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1355 {
1356 /* Read descriptor. */
1357 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1358 AssertRCBreak(rc);
1359
1360 if ( desc.ppn == 0
1361 && desc.numPages == 0)
1362 break; /* terminator */
1363
1364 if ( desc.ppn != 0
1365 && desc.numPages == 0)
1366 {
1367 /* Pointer to the next physical page of descriptors. */
1368 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1369 }
1370 else
1371 {
1372 if (iDescriptor == cDescriptorsAllocated)
1373 {
1374 cDescriptorsAllocated += 16;
1375 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1376 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1377 }
1378
1379 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1380 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1381 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1382
1383 /* Continue with the next descriptor. */
1384 GCPhys += sizeof(desc);
1385 }
1386 }
1387 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1388 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1389
1390 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1391 {
1392 AssertFailed();
1393 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1394 pSVGAState->aGMR[idGMR].paDesc = NULL;
1395 }
1396 AssertRC(rc);
1397 break;
1398 }
1399# endif /* IN_RING3 */
1400#endif // VBOX_WITH_VMSVGA3D
1401
1402 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1403 if (pThis->svga.fTraces == u32)
1404 break; /* nothing to do */
1405
1406#ifdef IN_RING3
1407 vmsvgaSetTraces(pThis, !!u32);
1408#else
1409 rc = VINF_IOM_R3_IOPORT_WRITE;
1410#endif
1411 break;
1412
1413 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1414 break;
1415
1416 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1417 break;
1418 /* Next 768 (== 256*3) registers exist for colormap */
1419
1420 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1421 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1422 break;
1423
1424 case SVGA_REG_FB_START:
1425 case SVGA_REG_MEM_START:
1426 case SVGA_REG_HOST_BITS_PER_PIXEL:
1427 case SVGA_REG_MAX_WIDTH:
1428 case SVGA_REG_MAX_HEIGHT:
1429 case SVGA_REG_VRAM_SIZE:
1430 case SVGA_REG_FB_SIZE:
1431 case SVGA_REG_CAPABILITIES:
1432 case SVGA_REG_MEM_SIZE:
1433 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1434 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1435 case SVGA_REG_BYTES_PER_LINE:
1436 case SVGA_REG_FB_OFFSET:
1437 case SVGA_REG_RED_MASK:
1438 case SVGA_REG_GREEN_MASK:
1439 case SVGA_REG_BLUE_MASK:
1440 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1441 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1442 case SVGA_REG_GMR_MAX_IDS:
1443 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1444 /* Read only - ignore. */
1445 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1446 break;
1447
1448 default:
1449 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1450 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1451 {
1452 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1453 }
1454 break;
1455 }
1456 return rc;
1457}
1458
1459/**
1460 * Port I/O Handler for IN operations.
1461 *
1462 * @returns VINF_SUCCESS or VINF_EM_*.
1463 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1464 *
1465 * @param pDevIns The device instance.
1466 * @param pvUser User argument.
1467 * @param uPort Port number used for the IN operation.
1468 * @param pu32 Where to store the result. This is always a 32-bit
1469 * variable regardless of what @a cb might say.
1470 * @param cb Number of bytes read.
1471 */
1472PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1473{
1474 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1475 int rc = VINF_SUCCESS;
1476
1477 /* Ignore non-dword accesses. */
1478 if (cb != 4)
1479 {
1480 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1481 *pu32 = ~0;
1482 return VINF_SUCCESS;
1483 }
1484
1485 switch (Port - pThis->svga.BasePort)
1486 {
1487 case SVGA_INDEX_PORT:
1488 *pu32 = pThis->svga.u32IndexReg;
1489 break;
1490
1491 case SVGA_VALUE_PORT:
1492 return vmsvgaReadPort(pThis, pu32);
1493
1494 case SVGA_BIOS_PORT:
1495 Log(("Ignoring BIOS port read\n"));
1496 *pu32 = 0;
1497 break;
1498
1499 case SVGA_IRQSTATUS_PORT:
1500 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1501 *pu32 = pThis->svga.u32IrqStatus;
1502 break;
1503 }
1504 return rc;
1505}
1506
1507/**
1508 * Port I/O Handler for OUT operations.
1509 *
1510 * @returns VINF_SUCCESS or VINF_EM_*.
1511 *
1512 * @param pDevIns The device instance.
1513 * @param pvUser User argument.
1514 * @param uPort Port number used for the OUT operation.
1515 * @param u32 The value to output.
1516 * @param cb The value size in bytes.
1517 */
1518PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1519{
1520 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1521 int rc = VINF_SUCCESS;
1522
1523 /* Ignore non-dword accesses. */
1524 if (cb != 4)
1525 {
1526 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1527 return VINF_SUCCESS;
1528 }
1529
1530 switch (Port - pThis->svga.BasePort)
1531 {
1532 case SVGA_INDEX_PORT:
1533 pThis->svga.u32IndexReg = u32;
1534 break;
1535
1536 case SVGA_VALUE_PORT:
1537 return vmsvgaWritePort(pThis, u32);
1538
1539 case SVGA_BIOS_PORT:
1540 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1541 break;
1542
1543 case SVGA_IRQSTATUS_PORT:
1544 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1545 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1546 /* Clear the irq in case all events have been cleared. */
1547 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1548 {
1549 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1550 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1551 }
1552 break;
1553 }
1554 return rc;
1555}
1556
1557#ifdef DEBUG_FIFO_ACCESS
1558
1559# ifdef IN_RING3
1560/**
1561 * Handle LFB access.
1562 * @returns VBox status code.
1563 * @param pVM VM handle.
1564 * @param pThis VGA device instance data.
1565 * @param GCPhys The access physical address.
1566 * @param fWriteAccess Read or write access
1567 */
1568static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1569{
1570 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1571 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1572
1573 switch (GCPhysOffset >> 2)
1574 {
1575 case SVGA_FIFO_MIN:
1576 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1577 break;
1578 case SVGA_FIFO_MAX:
1579 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1580 break;
1581 case SVGA_FIFO_NEXT_CMD:
1582 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1583 break;
1584 case SVGA_FIFO_STOP:
1585 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1586 break;
1587 case SVGA_FIFO_CAPABILITIES:
1588 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1589 break;
1590 case SVGA_FIFO_FLAGS:
1591 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1592 break;
1593 case SVGA_FIFO_FENCE:
1594 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1595 break;
1596 case SVGA_FIFO_3D_HWVERSION:
1597 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1598 break;
1599 case SVGA_FIFO_PITCHLOCK:
1600 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1601 break;
1602 case SVGA_FIFO_CURSOR_ON:
1603 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1604 break;
1605 case SVGA_FIFO_CURSOR_X:
1606 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1607 break;
1608 case SVGA_FIFO_CURSOR_Y:
1609 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1610 break;
1611 case SVGA_FIFO_CURSOR_COUNT:
1612 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1613 break;
1614 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1615 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1616 break;
1617 case SVGA_FIFO_RESERVED:
1618 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1619 break;
1620 case SVGA_FIFO_CURSOR_SCREEN_ID:
1621 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1622 break;
1623 case SVGA_FIFO_DEAD:
1624 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1625 break;
1626 case SVGA_FIFO_3D_HWVERSION_REVISED:
1627 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1628 break;
1629 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1630 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1631 break;
1632 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1633 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1634 break;
1635 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1636 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1637 break;
1638 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1639 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1640 break;
1641 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1642 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1643 break;
1644 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1645 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1646 break;
1647 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1648 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1649 break;
1650 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1651 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1652 break;
1653 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1654 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1655 break;
1656 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1657 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1658 break;
1659 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1660 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1661 break;
1662 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1663 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1664 break;
1665 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1666 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1667 break;
1668 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1669 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1670 break;
1671 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1672 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1673 break;
1674 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1675 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1676 break;
1677 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1678 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1679 break;
1680 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1681 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1682 break;
1683 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1684 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1685 break;
1686 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1687 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1688 break;
1689 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1690 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1691 break;
1692 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1693 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1694 break;
1695 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1696 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1697 break;
1698 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1699 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1700 break;
1701 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1702 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1703 break;
1704 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1705 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1706 break;
1707 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1708 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1709 break;
1710 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1711 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1712 break;
1713 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1714 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1715 break;
1716 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1717 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1718 break;
1719 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1720 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1721 break;
1722 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1723 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1724 break;
1725 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1726 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1727 break;
1728 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1729 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1730 break;
1731 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1732 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1733 break;
1734 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1735 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1736 break;
1737 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1738 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1739 break;
1740 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1741 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1742 break;
1743 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1744 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1745 break;
1746 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1747 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1748 break;
1749 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1750 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1751 break;
1752 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1753 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1754 break;
1755 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1756 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1757 break;
1758 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1759 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1760 break;
1761 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1762 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1763 break;
1764 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1765 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1766 break;
1767 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1768 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1769 break;
1770 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1771 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1772 break;
1773 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1774 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1775 break;
1776 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1777 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1778 break;
1779 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1780 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1781 break;
1782 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1783 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1784 break;
1785 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1786 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1787 break;
1788 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1789 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1790 break;
1791 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1792 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1793 break;
1794 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1795 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1796 break;
1797 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1798 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1799 break;
1800 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1801 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1802 break;
1803 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1804 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1805 break;
1806 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1807 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1808 break;
1809 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1810 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1811 break;
1812 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1813 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1814 break;
1815 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1816 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1817 break;
1818 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1819 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1820 break;
1821 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1822 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1823 break;
1824 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1825 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1826 break;
1827 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1828 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1829 break;
1830 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1831 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1832 break;
1833 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1834 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1835 break;
1836 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1837 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1838 break;
1839 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1840 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1841 break;
1842 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1843 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1844 break;
1845 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1846 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1847 break;
1848 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1849 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1850 break;
1851 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1852 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1853 break;
1854 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1855 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1856 break;
1857 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1858 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1859 break;
1860 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1861 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1862 break;
1863 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1864 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1865 break;
1866 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1867 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1868 break;
1869 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1870 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1871 break;
1872 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1873 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1874 break;
1875 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1876 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1877 break;
1878 case SVGA_FIFO_3D_CAPS_LAST:
1879 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1880 break;
1881 case SVGA_FIFO_GUEST_3D_HWVERSION:
1882 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1883 break;
1884 case SVGA_FIFO_FENCE_GOAL:
1885 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1886 break;
1887 case SVGA_FIFO_BUSY:
1888 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1889 break;
1890 default:
1891 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1892 break;
1893 }
1894
1895 return VINF_EM_RAW_EMULATE_INSTR;
1896}
1897
1898/**
1899 * HC access handler for the FIFO.
1900 *
1901 * @returns VINF_SUCCESS if the handler have carried out the operation.
1902 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1903 * @param pVM VM Handle.
1904 * @param pVCpu The cross context CPU structure for the calling EMT.
1905 * @param GCPhys The physical address the guest is writing to.
1906 * @param pvPhys The HC mapping of that address.
1907 * @param pvBuf What the guest is reading/writing.
1908 * @param cbBuf How much it's reading/writing.
1909 * @param enmAccessType The access type.
1910 * @param enmOrigin Who is making the access.
1911 * @param pvUser User argument.
1912 */
1913static DECLCALLBACK(VBOXSTRICTRC)
1914vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1915 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1916{
1917 PVGASTATE pThis = (PVGASTATE)pvUser;
1918 int rc;
1919 Assert(pThis);
1920 Assert(GCPhys >= pThis->GCPhysVRAM);
1921 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1922
1923 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1924 if (RT_SUCCESS(rc))
1925 return VINF_PGM_HANDLER_DO_DEFAULT;
1926 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1927 return rc;
1928}
1929
1930# endif /* IN_RING3 */
1931#endif /* DEBUG_FIFO_ACCESS */
1932
1933#ifdef DEBUG_GMR_ACCESS
1934/**
1935 * HC access handler for the FIFO.
1936 *
1937 * @returns VINF_SUCCESS if the handler have carried out the operation.
1938 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1939 * @param pVM VM Handle.
1940 * @param pVCpu The cross context CPU structure for the calling EMT.
1941 * @param GCPhys The physical address the guest is writing to.
1942 * @param pvPhys The HC mapping of that address.
1943 * @param pvBuf What the guest is reading/writing.
1944 * @param cbBuf How much it's reading/writing.
1945 * @param enmAccessType The access type.
1946 * @param enmOrigin Who is making the access.
1947 * @param pvUser User argument.
1948 */
1949static DECLCALLBACK(VBOXSTRICTRC)
1950vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1951 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1952{
1953 PVGASTATE pThis = (PVGASTATE)pvUser;
1954 Assert(pThis);
1955 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1956 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1957
1958 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1959
1960 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1961 {
1962 PGMR pGMR = &pSVGAState->aGMR[i];
1963
1964 if (pGMR->numDescriptors)
1965 {
1966 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1967 {
1968 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1969 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1970 {
1971 /*
1972 * Turn off the write handler for this particular page and make it R/W.
1973 * Then return telling the caller to restart the guest instruction.
1974 */
1975 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1976 goto end;
1977 }
1978 }
1979 }
1980 }
1981end:
1982 return VINF_PGM_HANDLER_DO_DEFAULT;
1983}
1984
1985# ifdef IN_RING3
1986
1987/* Callback handler for VMR3ReqCallWait */
1988static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1989{
1990 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1991 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1992 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1993 int rc;
1994
1995 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1996 {
1997 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
1998 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
1999 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2000 AssertRC(rc);
2001 }
2002 return VINF_SUCCESS;
2003}
2004
2005/* Callback handler for VMR3ReqCallWait */
2006static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2007{
2008 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2009 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2010 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2011
2012 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2013 {
2014 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2015 AssertRC(rc);
2016 }
2017 return VINF_SUCCESS;
2018}
2019
2020/* Callback handler for VMR3ReqCallWait */
2021static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2022{
2023 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2024
2025 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2026 {
2027 PGMR pGMR = &pSVGAState->aGMR[i];
2028
2029 if (pGMR->numDescriptors)
2030 {
2031 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2032 {
2033 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2034 AssertRC(rc);
2035 }
2036 }
2037 }
2038 return VINF_SUCCESS;
2039}
2040
2041# endif /* IN_RING3 */
2042#endif /* DEBUG_GMR_ACCESS */
2043
2044/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2045
2046#ifdef IN_RING3
2047
2048/**
2049 * Worker for vmsvgaR3FifoThread that handles an external command.
2050 *
2051 * @param pThis VGA device instance data.
2052 */
2053static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2054{
2055 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2056 switch (pThis->svga.u8FIFOExtCommand)
2057 {
2058 case VMSVGA_FIFO_EXTCMD_RESET:
2059 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2060 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2061# ifdef VBOX_WITH_VMSVGA3D
2062 if (pThis->svga.f3DEnabled)
2063 {
2064 /* The 3d subsystem must be reset from the fifo thread. */
2065 vmsvga3dReset(pThis);
2066 }
2067# endif
2068 break;
2069
2070 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2071 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2072 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2073# ifdef VBOX_WITH_VMSVGA3D
2074 if (pThis->svga.f3DEnabled)
2075 {
2076 /* The 3d subsystem must be shut down from the fifo thread. */
2077 vmsvga3dTerminate(pThis);
2078 }
2079# endif
2080 break;
2081
2082 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2083 {
2084 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2085# ifdef VBOX_WITH_VMSVGA3D
2086 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2087 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2088 vmsvga3dSaveExec(pThis, pSSM);
2089# endif
2090 break;
2091 }
2092
2093 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2094 {
2095 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2096# ifdef VBOX_WITH_VMSVGA3D
2097 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2098 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2099 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2100# endif
2101 break;
2102 }
2103
2104 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2105 {
2106# ifdef VBOX_WITH_VMSVGA3D
2107 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2108 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2109 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2110# endif
2111 break;
2112 }
2113
2114
2115 default:
2116 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2117 break;
2118 }
2119
2120 /*
2121 * Signal the end of the external command.
2122 */
2123 pThis->svga.pvFIFOExtCmdParam = NULL;
2124 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2125 ASMMemoryFence(); /* paranoia^2 */
2126 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2127 AssertLogRelRC(rc);
2128}
2129
2130/**
2131 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2132 * doing a job on the FIFO thread (even when it's officially suspended).
2133 *
2134 * @returns VBox status code (fully asserted).
2135 * @param pThis VGA device instance data.
2136 * @param uExtCmd The command to execute on the FIFO thread.
2137 * @param pvParam Pointer to command parameters.
2138 * @param cMsWait The time to wait for the command, given in
2139 * milliseconds.
2140 */
2141static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2142{
2143 Assert(cMsWait >= RT_MS_1SEC * 5);
2144 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2145 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2146
2147 int rc;
2148 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2149 PDMTHREADSTATE enmState = pThread->enmState;
2150 if (enmState == PDMTHREADSTATE_SUSPENDED)
2151 {
2152 /*
2153 * The thread is suspended, we have to temporarily wake it up so it can
2154 * perform the task.
2155 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2156 */
2157 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2158 /* Post the request. */
2159 pThis->svga.fFifoExtCommandWakeup = true;
2160 pThis->svga.pvFIFOExtCmdParam = pvParam;
2161 pThis->svga.u8FIFOExtCommand = uExtCmd;
2162 ASMMemoryFence(); /* paranoia^3 */
2163
2164 /* Resume the thread. */
2165 rc = PDMR3ThreadResume(pThread);
2166 AssertLogRelRC(rc);
2167 if (RT_SUCCESS(rc))
2168 {
2169 /* Wait. Take care in case the semaphore was already posted (same as below). */
2170 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2171 if ( rc == VINF_SUCCESS
2172 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2173 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2174 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2175 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2176
2177 /* suspend the thread */
2178 pThis->svga.fFifoExtCommandWakeup = false;
2179 int rc2 = PDMR3ThreadSuspend(pThread);
2180 AssertLogRelRC(rc2);
2181 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2182 rc = rc2;
2183 }
2184 pThis->svga.fFifoExtCommandWakeup = false;
2185 pThis->svga.pvFIFOExtCmdParam = NULL;
2186 }
2187 else if (enmState == PDMTHREADSTATE_RUNNING)
2188 {
2189 /*
2190 * The thread is running, should only happen during reset and vmsvga3dsfc.
2191 * We ASSUME not racing code here, both wrt thread state and ext commands.
2192 */
2193 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2194 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2195
2196 /* Post the request. */
2197 pThis->svga.pvFIFOExtCmdParam = pvParam;
2198 pThis->svga.u8FIFOExtCommand = uExtCmd;
2199 ASMMemoryFence(); /* paranoia^2 */
2200 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2201 AssertLogRelRC(rc);
2202
2203 /* Wait. Take care in case the semaphore was already posted (same as above). */
2204 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2205 if ( rc == VINF_SUCCESS
2206 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2207 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2208 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2209 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2210
2211 pThis->svga.pvFIFOExtCmdParam = NULL;
2212 }
2213 else
2214 {
2215 /*
2216 * Something is wrong with the thread!
2217 */
2218 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2219 rc = VERR_INVALID_STATE;
2220 }
2221 return rc;
2222}
2223
2224
2225/**
2226 * Marks the FIFO non-busy, notifying any waiting EMTs.
2227 *
2228 * @param pThis The VGA state.
2229 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2230 * @param offFifoMin The start byte offset of the command FIFO.
2231 */
2232static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2233{
2234 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2235 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2236 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2237
2238 /* Wake up any waiting EMTs. */
2239 if (pSVGAState->cBusyDelayedEmts > 0)
2240 {
2241#ifdef VMSVGA_USE_EMT_HALT_CODE
2242 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2243 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2244 if (idCpu != NIL_VMCPUID)
2245 {
2246 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2247 while (idCpu-- > 0)
2248 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2249 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2250 }
2251#else
2252 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2253 AssertRC(rc2);
2254#endif
2255 }
2256}
2257
2258/**
2259 * Reads (more) payload into the command buffer.
2260 *
2261 * @returns pbBounceBuf on success
2262 * @retval (void *)1 if the thread was requested to stop.
2263 * @retval NULL on FIFO error.
2264 *
2265 * @param cbPayloadReq The number of bytes of payload requested.
2266 * @param pFIFO The FIFO.
2267 * @param offCurrentCmd The FIFO byte offset of the current command.
2268 * @param offFifoMin The start byte offset of the command FIFO.
2269 * @param offFifoMax The end byte offset of the command FIFO.
2270 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2271 * always sufficient size.
2272 * @param pcbAlreadyRead How much payload we've already read into the bounce
2273 * buffer. (We will NEVER re-read anything.)
2274 * @param pThread The calling PDM thread handle.
2275 * @param pThis The VGA state.
2276 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2277 * statistics collection.
2278 */
2279static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2280 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2281 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2282 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2283{
2284 Assert(pbBounceBuf);
2285 Assert(pcbAlreadyRead);
2286 Assert(offFifoMin < offFifoMax);
2287 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2288 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2289
2290 /*
2291 * Check if the requested payload size has already been satisfied .
2292 * .
2293 * When called to read more, the caller is responsible for making sure the .
2294 * new command size (cbRequsted) never is smaller than what has already .
2295 * been read.
2296 */
2297 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2298 if (cbPayloadReq <= cbAlreadyRead)
2299 {
2300 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2301 return pbBounceBuf;
2302 }
2303
2304 /*
2305 * Commands bigger than the fifo buffer are invalid.
2306 */
2307 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2308 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2309 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2310 NULL);
2311
2312 /*
2313 * Move offCurrentCmd past the command dword.
2314 */
2315 offCurrentCmd += sizeof(uint32_t);
2316 if (offCurrentCmd >= offFifoMax)
2317 offCurrentCmd = offFifoMin;
2318
2319 /*
2320 * Do we have sufficient payload data available already?
2321 */
2322 uint32_t cbAfter, cbBefore;
2323 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2324 if (offNextCmd > offCurrentCmd)
2325 {
2326 if (RT_LIKELY(offNextCmd < offFifoMax))
2327 cbAfter = offNextCmd - offCurrentCmd;
2328 else
2329 {
2330 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2331 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2332 offNextCmd, offFifoMin, offFifoMax));
2333 cbAfter = offFifoMax - offCurrentCmd;
2334 }
2335 cbBefore = 0;
2336 }
2337 else
2338 {
2339 cbAfter = offFifoMax - offCurrentCmd;
2340 if (offNextCmd >= offFifoMin)
2341 cbBefore = offNextCmd - offFifoMin;
2342 else
2343 {
2344 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2345 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2346 offNextCmd, offFifoMin, offFifoMax));
2347 cbBefore = 0;
2348 }
2349 }
2350 if (cbAfter + cbBefore < cbPayloadReq)
2351 {
2352 /*
2353 * Insufficient, must wait for it to arrive.
2354 */
2355 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2356 for (uint32_t i = 0;; i++)
2357 {
2358 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2359 {
2360 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2361 return (void *)(uintptr_t)1;
2362 }
2363 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2364 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2365
2366 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2367
2368 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2369 if (offNextCmd > offCurrentCmd)
2370 {
2371 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2372 cbBefore = 0;
2373 }
2374 else
2375 {
2376 cbAfter = offFifoMax - offCurrentCmd;
2377 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2378 }
2379
2380 if (cbAfter + cbBefore >= cbPayloadReq)
2381 break;
2382 }
2383 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2384 }
2385
2386 /*
2387 * Copy out the memory and update what pcbAlreadyRead points to.
2388 */
2389 if (cbAfter >= cbPayloadReq)
2390 memcpy(pbBounceBuf + cbAlreadyRead,
2391 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2392 cbPayloadReq - cbAlreadyRead);
2393 else
2394 {
2395 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2396 if (cbAlreadyRead < cbAfter)
2397 {
2398 memcpy(pbBounceBuf + cbAlreadyRead,
2399 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2400 cbAfter - cbAlreadyRead);
2401 cbAlreadyRead = cbAfter;
2402 }
2403 memcpy(pbBounceBuf + cbAlreadyRead,
2404 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2405 cbPayloadReq - cbAlreadyRead);
2406 }
2407 *pcbAlreadyRead = cbPayloadReq;
2408 return pbBounceBuf;
2409}
2410
2411/* The async FIFO handling thread. */
2412static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2413{
2414 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2415 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2416 int rc;
2417
2418 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2419 return VINF_SUCCESS;
2420
2421 /*
2422 * Special mode where we only execute an external command and the go back
2423 * to being suspended. Currently, all ext cmds ends up here, with the reset
2424 * one also being eligble for runtime execution further down as well.
2425 */
2426 if (pThis->svga.fFifoExtCommandWakeup)
2427 {
2428 vmsvgaR3FifoHandleExtCmd(pThis);
2429 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2430 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2431 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2432 else
2433 vmsvgaR3FifoHandleExtCmd(pThis);
2434 return VINF_SUCCESS;
2435 }
2436
2437
2438 /*
2439 * Signal the semaphore to make sure we don't wait for 250 after a
2440 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2441 */
2442 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2443
2444 /*
2445 * Allocate a bounce buffer for command we get from the FIFO.
2446 * (All code must return via the end of the function to free this buffer.)
2447 */
2448 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2449 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2450
2451 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2452 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2453 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2454 {
2455# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2456 /*
2457 * Should service the run loop every so often.
2458 */
2459 if (pThis->svga.f3DEnabled)
2460 vmsvga3dCocoaServiceRunLoop();
2461# endif
2462
2463 /*
2464 * Wait for at most 250 ms to start polling.
2465 */
2466 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2467 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2468 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2469 {
2470 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2471 break;
2472 }
2473 if (rc == VERR_TIMEOUT)
2474 {
2475 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2476 continue;
2477 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2478
2479 Log(("vmsvgaFIFOLoop: timeout\n"));
2480 }
2481 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2482 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2483
2484 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2485 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2486 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2487
2488 /*
2489 * Handle external commands (currently only reset).
2490 */
2491 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2492 {
2493 vmsvgaR3FifoHandleExtCmd(pThis);
2494 continue;
2495 }
2496
2497 /*
2498 * The device must be enabled and configured.
2499 */
2500 if ( !pThis->svga.fEnabled
2501 || !pThis->svga.fConfigured)
2502 {
2503 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2504 continue;
2505 }
2506
2507 /*
2508 * Get and check the min/max values. We ASSUME that they will remain
2509 * unchanged while we process requests. A further ASSUMPTION is that
2510 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2511 * we don't read it back while in the loop.
2512 */
2513 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2514 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2515 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2516 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2517 || offFifoMax <= offFifoMin
2518 || offFifoMax > VMSVGA_FIFO_SIZE
2519 || (offFifoMax & 3) != 0
2520 || (offFifoMin & 3) != 0
2521 || offCurrentCmd < offFifoMin
2522 || offCurrentCmd > offFifoMax))
2523 {
2524 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2525 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2526 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2527 continue;
2528 }
2529 if (RT_UNLIKELY(offCurrentCmd & 3))
2530 {
2531 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2532 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2533 offCurrentCmd = ~UINT32_C(3);
2534 }
2535
2536/**
2537 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2538 *
2539 * Will break out of the switch on failure.
2540 * Will restart and quit the loop if the thread was requested to stop.
2541 *
2542 * @param a_cbPayloadReq How much payload to fetch.
2543 * @remarks Access a bunch of variables in the current scope!
2544 */
2545# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2546 if (1) { \
2547 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2548 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2549 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2550 } else do {} while (0)
2551/**
2552 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2553 * buffer after figuring out the actual command size.
2554 * Will break out of the switch on failure.
2555 * @param a_cbPayloadReq How much payload to fetch.
2556 * @remarks Access a bunch of variables in the current scope!
2557 */
2558# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2559 if (1) { \
2560 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2561 } else do {} while (0)
2562
2563 /*
2564 * Mark the FIFO as busy.
2565 */
2566 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2567 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2568 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2569
2570 /*
2571 * Execute all queued FIFO commands.
2572 * Quit if pending external command or changes in the thread state.
2573 */
2574 bool fDone = false;
2575 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2576 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2577 {
2578 uint32_t cbPayload = 0;
2579 uint32_t u32IrqStatus = 0;
2580 bool fTriggerIrq = false;
2581
2582 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2583
2584 /* First check any pending actions. */
2585 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2586# ifdef VBOX_WITH_VMSVGA3D
2587 vmsvga3dChangeMode(pThis);
2588# else
2589 {/*nothing*/}
2590# endif
2591 /* Check for pending external commands (reset). */
2592 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2593 break;
2594
2595 /*
2596 * Process the command.
2597 */
2598 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2599 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2600 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2601 switch (enmCmdId)
2602 {
2603 case SVGA_CMD_INVALID_CMD:
2604 /* Nothing to do. */
2605 break;
2606
2607 case SVGA_CMD_FENCE:
2608 {
2609 SVGAFifoCmdFence *pCmdFence;
2610 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2611 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2612 {
2613 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2614 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2615
2616 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2617 {
2618 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2619 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2620 }
2621 else
2622 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2623 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2624 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2625 {
2626 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2627 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2628 }
2629 }
2630 else
2631 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2632 break;
2633 }
2634 case SVGA_CMD_UPDATE:
2635 case SVGA_CMD_UPDATE_VERBOSE:
2636 {
2637 SVGAFifoCmdUpdate *pUpdate;
2638 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2639 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2640 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2641 break;
2642 }
2643
2644 case SVGA_CMD_DEFINE_CURSOR:
2645 {
2646 /* Followed by bitmap data. */
2647 SVGAFifoCmdDefineCursor *pCursor;
2648 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2649 AssertFailed(); /** @todo implement when necessary. */
2650 break;
2651 }
2652
2653 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2654 {
2655 /* Followed by bitmap data. */
2656 uint32_t cbCursorShape, cbAndMask;
2657 uint8_t *pCursorCopy;
2658 uint32_t cbCmd;
2659
2660 SVGAFifoCmdDefineAlphaCursor *pCursor;
2661 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2662
2663 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2664
2665 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2666 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2667
2668 /* Refetch the bitmap data as well. */
2669 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2670 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2671 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2672
2673 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2674 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2675 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2676 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2677
2678 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2679 AssertBreak(pCursorCopy);
2680
2681 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2682
2683 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2684 memset(pCursorCopy, 0xff, cbAndMask);
2685 /* Colour data */
2686 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2687
2688 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2689 true,
2690 true,
2691 pCursor->hotspotX,
2692 pCursor->hotspotY,
2693 pCursor->width,
2694 pCursor->height,
2695 pCursorCopy);
2696 AssertRC(rc);
2697
2698 if (pSVGAState->Cursor.fActive)
2699 RTMemFree(pSVGAState->Cursor.pData);
2700
2701 pSVGAState->Cursor.fActive = true;
2702 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2703 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2704 pSVGAState->Cursor.width = pCursor->width;
2705 pSVGAState->Cursor.height = pCursor->height;
2706 pSVGAState->Cursor.cbData = cbCursorShape;
2707 pSVGAState->Cursor.pData = pCursorCopy;
2708 break;
2709 }
2710
2711 case SVGA_CMD_ESCAPE:
2712 {
2713 /* Followed by nsize bytes of data. */
2714 SVGAFifoCmdEscape *pEscape;
2715 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2716
2717 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2718 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2719 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2720 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2721
2722 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2723 {
2724 AssertBreak(pEscape->size >= sizeof(uint32_t));
2725 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2726 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2727
2728 switch (cmd)
2729 {
2730 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2731 {
2732 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2733 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2734 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2735
2736 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2737 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2738 {
2739 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2740 }
2741 break;
2742 }
2743
2744 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2745 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2746 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2747 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2748 break;
2749 }
2750 }
2751 else
2752 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2753
2754 break;
2755 }
2756# ifdef VBOX_WITH_VMSVGA3D
2757 case SVGA_CMD_DEFINE_GMR2:
2758 {
2759 SVGAFifoCmdDefineGMR2 *pCmd;
2760 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2761 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2762
2763 /* Validate current GMR id. */
2764 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2765 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2766
2767 if (!pCmd->numPages)
2768 {
2769 vmsvgaGMRFree(pThis, pCmd->gmrId);
2770 }
2771 else
2772 {
2773 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2774 pGMR->cMaxPages = pCmd->numPages;
2775 }
2776 /* everything done in remap */
2777 break;
2778 }
2779
2780 case SVGA_CMD_REMAP_GMR2:
2781 {
2782 /* Followed by page descriptors or guest ptr. */
2783 SVGAFifoCmdRemapGMR2 *pCmd;
2784 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2785 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2786 uint32_t cbCmd;
2787 uint64_t *paNewPage64 = NULL;
2788
2789 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2790 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2791
2792 /* Calculate the size of what comes after next and fetch it. */
2793 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2794 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2795 cbCmd += sizeof(SVGAGuestPtr);
2796 else
2797 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2798 {
2799 cbCmd += cbPageDesc;
2800 pCmd->numPages = 1;
2801 }
2802 else
2803 {
2804 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2805 cbCmd += cbPageDesc * pCmd->numPages;
2806 }
2807 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2808
2809 /* Validate current GMR id. */
2810 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2811 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2812 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2813 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2814
2815 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2816 if (pGMR->paDesc)
2817 {
2818 uint32_t idxPage = 0;
2819 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2820 AssertBreak(paNewPage64);
2821
2822 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2823 {
2824 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2825 {
2826 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2827 }
2828 }
2829 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2830 }
2831
2832 /* Free the old GMR if present. */
2833 if (pGMR->paDesc)
2834 RTMemFree(pGMR->paDesc);
2835
2836 /* Allocate the maximum amount possible (everything non-continuous) */
2837 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2838 AssertBreak(pGMR->paDesc);
2839
2840 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2841 {
2842 /** @todo */
2843 AssertFailed();
2844 }
2845 else
2846 {
2847 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2848 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2849 uint32_t iDescriptor = 0;
2850 RTGCPHYS GCPhys;
2851 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2852 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2853
2854 if (paNewPage64)
2855 {
2856 /* Overwrite the old page array with the new page values. */
2857 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2858 {
2859 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2860 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2861 else
2862 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2863 }
2864 /* Use the updated page array instead of the command data. */
2865 fGCPhys64 = true;
2866 pPage64 = paNewPage64;
2867 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2868 }
2869
2870 if (fGCPhys64)
2871 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2872 else
2873 GCPhys = pPage32[0] << PAGE_SHIFT;
2874
2875 pGMR->paDesc[0].GCPhys = GCPhys;
2876 pGMR->paDesc[0].numPages = 1;
2877 pGMR->cbTotal = PAGE_SIZE;
2878
2879 for (uint32_t i = 1; i < pCmd->numPages; i++)
2880 {
2881 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2882 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2883 else
2884 GCPhys = pPage32[i] << PAGE_SHIFT;
2885
2886 /* Continuous physical memory? */
2887 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2888 {
2889 Assert(pGMR->paDesc[iDescriptor].numPages);
2890 pGMR->paDesc[iDescriptor].numPages++;
2891 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2892 }
2893 else
2894 {
2895 iDescriptor++;
2896 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2897 pGMR->paDesc[iDescriptor].numPages = 1;
2898 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2899 }
2900
2901 pGMR->cbTotal += PAGE_SIZE;
2902 }
2903 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2904 pGMR->numDescriptors = iDescriptor + 1;
2905 }
2906
2907 if (paNewPage64)
2908 RTMemFree(paNewPage64);
2909
2910# ifdef DEBUG_GMR_ACCESS
2911 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2912# endif
2913 break;
2914 }
2915# endif // VBOX_WITH_VMSVGA3D
2916 case SVGA_CMD_DEFINE_SCREEN:
2917 {
2918 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2919 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2920 SVGAFifoCmdDefineScreen *pCmd;
2921 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2922 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2923 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2924
2925 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2926 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2927 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2928 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2929 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2930 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2931 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2932 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2933 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2934 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2935 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2936
2937 /** @todo multi monitor support and screen object capabilities. */
2938 pThis->svga.uWidth = pCmd->screen.size.width;
2939 pThis->svga.uHeight = pCmd->screen.size.height;
2940 vmsvgaChangeMode(pThis);
2941 break;
2942 }
2943
2944 case SVGA_CMD_DESTROY_SCREEN:
2945 {
2946 SVGAFifoCmdDestroyScreen *pCmd;
2947 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2948
2949 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2950 break;
2951 }
2952# ifdef VBOX_WITH_VMSVGA3D
2953 case SVGA_CMD_DEFINE_GMRFB:
2954 {
2955 SVGAFifoCmdDefineGMRFB *pCmd;
2956 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2957
2958 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2959 pSVGAState->GMRFB.ptr = pCmd->ptr;
2960 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2961 pSVGAState->GMRFB.format = pCmd->format;
2962 break;
2963 }
2964
2965 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2966 {
2967 uint32_t width, height;
2968 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2969 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2970
2971 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2972
2973 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2974 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2975 AssertBreak(pCmd->destScreenId == 0);
2976
2977 if (pCmd->destRect.left < 0)
2978 pCmd->destRect.left = 0;
2979 if (pCmd->destRect.top < 0)
2980 pCmd->destRect.top = 0;
2981 if (pCmd->destRect.right < 0)
2982 pCmd->destRect.right = 0;
2983 if (pCmd->destRect.bottom < 0)
2984 pCmd->destRect.bottom = 0;
2985
2986 width = pCmd->destRect.right - pCmd->destRect.left;
2987 height = pCmd->destRect.bottom - pCmd->destRect.top;
2988
2989 if ( width == 0
2990 || height == 0)
2991 break; /* Nothing to do. */
2992
2993 /* Clip to screen dimensions. */
2994 if (width > pThis->svga.uWidth)
2995 width = pThis->svga.uWidth;
2996 if (height > pThis->svga.uHeight)
2997 height = pThis->svga.uHeight;
2998
2999 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3000 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3001 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3002
3003 AssertBreak(offsetDest < pThis->vram_size);
3004
3005 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3006 AssertRC(rc);
3007 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3008 break;
3009 }
3010
3011 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3012 {
3013 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3014 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3015
3016 /* Note! This can fetch 3d render results as well!! */
3017 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3018 AssertFailed();
3019 break;
3020 }
3021# endif // VBOX_WITH_VMSVGA3D
3022 case SVGA_CMD_ANNOTATION_FILL:
3023 {
3024 SVGAFifoCmdAnnotationFill *pCmd;
3025 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3026
3027 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3028 pSVGAState->colorAnnotation = pCmd->color;
3029 break;
3030 }
3031
3032 case SVGA_CMD_ANNOTATION_COPY:
3033 {
3034 SVGAFifoCmdAnnotationCopy *pCmd;
3035 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3036
3037 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3038 AssertFailed();
3039 break;
3040 }
3041
3042 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3043
3044 default:
3045# ifdef VBOX_WITH_VMSVGA3D
3046 if ( enmCmdId >= SVGA_3D_CMD_BASE
3047 && enmCmdId < SVGA_3D_CMD_MAX)
3048 {
3049 /* All 3d commands start with a common header, which defines the size of the command. */
3050 SVGA3dCmdHeader *pHdr;
3051 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3052 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3053 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3054 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3055
3056/**
3057 * Check that the 3D command has at least a_cbMin of payload bytes after the
3058 * header. Will break out of the switch if it doesn't.
3059 */
3060# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3061 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3062 switch ((int)enmCmdId)
3063 {
3064 case SVGA_3D_CMD_SURFACE_DEFINE:
3065 {
3066 uint32_t cMipLevels;
3067 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3068 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3069
3070 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3071 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3072 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3073# ifdef DEBUG_GMR_ACCESS
3074 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3075# endif
3076 break;
3077 }
3078
3079 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3080 {
3081 uint32_t cMipLevels;
3082 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3083 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3084
3085 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3086 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3087 pCmd->multisampleCount, pCmd->autogenFilter,
3088 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3089 break;
3090 }
3091
3092 case SVGA_3D_CMD_SURFACE_DESTROY:
3093 {
3094 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3095 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3096 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3097 break;
3098 }
3099
3100 case SVGA_3D_CMD_SURFACE_COPY:
3101 {
3102 uint32_t cCopyBoxes;
3103 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3104 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3105
3106 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3107 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3108 break;
3109 }
3110
3111 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3112 {
3113 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3114 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3115
3116 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3117 break;
3118 }
3119
3120 case SVGA_3D_CMD_SURFACE_DMA:
3121 {
3122 uint32_t cCopyBoxes;
3123 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3124 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3125
3126 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3127 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3128 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3129 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3130 break;
3131 }
3132
3133 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3134 {
3135 uint32_t cRects;
3136 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3137 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3138
3139 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3140 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3141 break;
3142 }
3143
3144 case SVGA_3D_CMD_CONTEXT_DEFINE:
3145 {
3146 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3147 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3148
3149 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3150 break;
3151 }
3152
3153 case SVGA_3D_CMD_CONTEXT_DESTROY:
3154 {
3155 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3156 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3157
3158 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3159 break;
3160 }
3161
3162 case SVGA_3D_CMD_SETTRANSFORM:
3163 {
3164 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3165 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3166
3167 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3168 break;
3169 }
3170
3171 case SVGA_3D_CMD_SETZRANGE:
3172 {
3173 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3174 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3175
3176 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3177 break;
3178 }
3179
3180 case SVGA_3D_CMD_SETRENDERSTATE:
3181 {
3182 uint32_t cRenderStates;
3183 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3184 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3185
3186 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3187 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3188 break;
3189 }
3190
3191 case SVGA_3D_CMD_SETRENDERTARGET:
3192 {
3193 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3195
3196 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3197 break;
3198 }
3199
3200 case SVGA_3D_CMD_SETTEXTURESTATE:
3201 {
3202 uint32_t cTextureStates;
3203 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3204 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3205
3206 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3207 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3208 break;
3209 }
3210
3211 case SVGA_3D_CMD_SETMATERIAL:
3212 {
3213 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3214 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3215
3216 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3217 break;
3218 }
3219
3220 case SVGA_3D_CMD_SETLIGHTDATA:
3221 {
3222 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3223 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3224
3225 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3226 break;
3227 }
3228
3229 case SVGA_3D_CMD_SETLIGHTENABLED:
3230 {
3231 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3232 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3233
3234 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3235 break;
3236 }
3237
3238 case SVGA_3D_CMD_SETVIEWPORT:
3239 {
3240 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3242
3243 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3244 break;
3245 }
3246
3247 case SVGA_3D_CMD_SETCLIPPLANE:
3248 {
3249 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3250 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3251
3252 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3253 break;
3254 }
3255
3256 case SVGA_3D_CMD_CLEAR:
3257 {
3258 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3259 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3260 uint32_t cRects;
3261
3262 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3263 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3264 break;
3265 }
3266
3267 case SVGA_3D_CMD_PRESENT:
3268 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3269 {
3270 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3271 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3272 uint32_t cRects;
3273
3274 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3275
3276 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3277 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3278 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3279 break;
3280 }
3281
3282 case SVGA_3D_CMD_SHADER_DEFINE:
3283 {
3284 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3285 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3286 uint32_t cbData;
3287
3288 cbData = (pHdr->size - sizeof(*pCmd));
3289 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3290 break;
3291 }
3292
3293 case SVGA_3D_CMD_SHADER_DESTROY:
3294 {
3295 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3296 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3297
3298 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3299 break;
3300 }
3301
3302 case SVGA_3D_CMD_SET_SHADER:
3303 {
3304 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3305 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3306
3307 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3308 break;
3309 }
3310
3311 case SVGA_3D_CMD_SET_SHADER_CONST:
3312 {
3313 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3314 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3315
3316 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3317 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3318 break;
3319 }
3320
3321 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3322 {
3323 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3324 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3325 uint32_t cVertexDivisor;
3326
3327 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3328 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3329 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3330 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3331
3332 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3333 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3334 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3335
3336 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3337 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3338 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3339 break;
3340 }
3341
3342 case SVGA_3D_CMD_SETSCISSORRECT:
3343 {
3344 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3346
3347 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3348 break;
3349 }
3350
3351 case SVGA_3D_CMD_BEGIN_QUERY:
3352 {
3353 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3355
3356 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3357 break;
3358 }
3359
3360 case SVGA_3D_CMD_END_QUERY:
3361 {
3362 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3363 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3364
3365 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3366 break;
3367 }
3368
3369 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3370 {
3371 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3372 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3373
3374 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3375 break;
3376 }
3377
3378 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3379 {
3380 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3381 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3382
3383 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3384 break;
3385 }
3386
3387 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3388 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3389 /* context id + surface id? */
3390 break;
3391
3392 default:
3393 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3394 AssertFailed();
3395 break;
3396 }
3397 }
3398 else
3399# endif // VBOX_WITH_VMSVGA3D
3400 {
3401 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3402 AssertFailed();
3403 }
3404 }
3405
3406 /* Go to the next slot */
3407 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3408 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3409 if (offCurrentCmd >= offFifoMax)
3410 {
3411 offCurrentCmd -= offFifoMax - offFifoMin;
3412 Assert(offCurrentCmd >= offFifoMin);
3413 Assert(offCurrentCmd < offFifoMax);
3414 }
3415 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3416 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3417
3418 /*
3419 * Raise IRQ if required. Must enter the critical section here
3420 * before making final decisions here, otherwise cubebench and
3421 * others may end up waiting forever.
3422 */
3423 if ( u32IrqStatus
3424 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3425 {
3426 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3427
3428 /* FIFO progress might trigger an interrupt. */
3429 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3430 {
3431 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3432 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3433 }
3434
3435 /* Unmasked IRQ pending? */
3436 if (pThis->svga.u32IrqMask & u32IrqStatus)
3437 {
3438 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3439 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3440 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3441 }
3442
3443 PDMCritSectLeave(&pThis->CritSect);
3444 }
3445 }
3446
3447 /* If really done, clear the busy flag. */
3448 if (fDone)
3449 {
3450 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3451 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3452 }
3453 }
3454
3455 /*
3456 * Free the bounce buffer. (There are no returns above!)
3457 */
3458 RTMemFree(pbBounceBuf);
3459
3460 return VINF_SUCCESS;
3461}
3462
3463/**
3464 * Free the specified GMR
3465 *
3466 * @param pThis VGA device instance data.
3467 * @param idGMR GMR id
3468 */
3469void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3470{
3471 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3472
3473 /* Free the old descriptor if present. */
3474 if (pSVGAState->aGMR[idGMR].numDescriptors)
3475 {
3476 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3477# ifdef DEBUG_GMR_ACCESS
3478 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3479# endif
3480
3481 Assert(pGMR->paDesc);
3482 RTMemFree(pGMR->paDesc);
3483 pGMR->paDesc = NULL;
3484 pGMR->numDescriptors = 0;
3485 pGMR->cbTotal = 0;
3486 pGMR->cMaxPages = 0;
3487 }
3488 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3489}
3490
3491/**
3492 * Copy from a GMR to host memory or vice versa
3493 *
3494 * @returns VBox status code.
3495 * @param pThis VGA device instance data.
3496 * @param enmTransferType Transfer type (read/write)
3497 * @param pbDst Host destination pointer
3498 * @param cbDestPitch Destination buffer pitch
3499 * @param src GMR description
3500 * @param offSrc Source buffer offset
3501 * @param cbSrcPitch Source buffer pitch
3502 * @param cbWidth Source width in bytes
3503 * @param cHeight Source height
3504 */
3505int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3506 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3507{
3508 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3509 PGMR pGMR;
3510 int rc;
3511 PVMSVGAGMRDESCRIPTOR pDesc;
3512 unsigned offDesc = 0;
3513
3514 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3515 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3516 Assert(cbWidth && cHeight);
3517
3518 /* Shortcut for the framebuffer. */
3519 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3520 {
3521 offSrc += src.offset;
3522 AssertMsgReturn(src.offset < pThis->vram_size,
3523 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3524 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3525 VERR_INVALID_PARAMETER);
3526 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3527 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3528 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3529 VERR_INVALID_PARAMETER);
3530
3531 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3532
3533 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3534 {
3535 /* switch src & dest */
3536 uint8_t *pTemp = pbDst;
3537 int32_t cbTempPitch = cbDestPitch;
3538
3539 pbDst = pSrc;
3540 pSrc = pTemp;
3541
3542 cbDestPitch = cbSrcPitch;
3543 cbSrcPitch = cbTempPitch;
3544 }
3545
3546 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3547 && cbWidth == (uint32_t)cbDestPitch
3548 && cbSrcPitch == cbDestPitch)
3549 {
3550 memcpy(pbDst, pSrc, cbWidth * cHeight);
3551 }
3552 else
3553 {
3554 for(uint32_t i = 0; i < cHeight; i++)
3555 {
3556 memcpy(pbDst, pSrc, cbWidth);
3557
3558 pbDst += cbDestPitch;
3559 pSrc += cbSrcPitch;
3560 }
3561 }
3562 return VINF_SUCCESS;
3563 }
3564
3565 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3566 pGMR = &pSVGAState->aGMR[src.gmrId];
3567 pDesc = pGMR->paDesc;
3568
3569 offSrc += src.offset;
3570 AssertMsgReturn(src.offset < pGMR->cbTotal,
3571 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3572 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3573 VERR_INVALID_PARAMETER);
3574 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3575 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3576 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3577 VERR_INVALID_PARAMETER);
3578
3579 for (uint32_t i = 0; i < cHeight; i++)
3580 {
3581 uint32_t cbCurrentWidth = cbWidth;
3582 uint32_t offCurrent = offSrc;
3583 uint8_t *pCurrentDest = pbDst;
3584
3585 /* Find the right descriptor */
3586 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3587 {
3588 offDesc += pDesc->numPages * PAGE_SIZE;
3589 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3590 pDesc++;
3591 }
3592
3593 while (cbCurrentWidth)
3594 {
3595 uint32_t cbToCopy;
3596
3597 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3598 {
3599 cbToCopy = cbCurrentWidth;
3600 }
3601 else
3602 {
3603 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3604 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3605 }
3606
3607 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3608
3609 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3610 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3611 else
3612 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3613 AssertRCBreak(rc);
3614
3615 cbCurrentWidth -= cbToCopy;
3616 offCurrent += cbToCopy;
3617 pCurrentDest += cbToCopy;
3618
3619 /* Go to the next descriptor if there's anything left. */
3620 if (cbCurrentWidth)
3621 {
3622 offDesc += pDesc->numPages * PAGE_SIZE;
3623 pDesc++;
3624 }
3625 }
3626
3627 offSrc += cbSrcPitch;
3628 pbDst += cbDestPitch;
3629 }
3630
3631 return VINF_SUCCESS;
3632}
3633
3634/**
3635 * Unblock the FIFO I/O thread so it can respond to a state change.
3636 *
3637 * @returns VBox status code.
3638 * @param pDevIns The VGA device instance.
3639 * @param pThread The send thread.
3640 */
3641static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3642{
3643 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3644 Log(("vmsvgaFIFOLoopWakeUp\n"));
3645 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3646}
3647
3648/**
3649 * Enables or disables dirty page tracking for the framebuffer
3650 *
3651 * @param pThis VGA device instance data.
3652 * @param fTraces Enable/disable traces
3653 */
3654static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3655{
3656 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3657 && !fTraces)
3658 {
3659 //Assert(pThis->svga.fTraces);
3660 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3661 return;
3662 }
3663
3664 pThis->svga.fTraces = fTraces;
3665 if (pThis->svga.fTraces)
3666 {
3667 unsigned cbFrameBuffer = pThis->vram_size;
3668
3669 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3670 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3671 {
3672#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3673 Assert(pThis->svga.cbScanline);
3674#endif
3675 /* Hardware enabled; return real framebuffer size .*/
3676 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3677 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3678 }
3679
3680 if (!pThis->svga.fVRAMTracking)
3681 {
3682 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3683 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3684 pThis->svga.fVRAMTracking = true;
3685 }
3686 }
3687 else
3688 {
3689 if (pThis->svga.fVRAMTracking)
3690 {
3691 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3692 vgaR3UnregisterVRAMHandler(pThis);
3693 pThis->svga.fVRAMTracking = false;
3694 }
3695 }
3696}
3697
3698/**
3699 * Callback function for mapping a PCI I/O region.
3700 *
3701 * @return VBox status code.
3702 * @param pPciDev Pointer to PCI device.
3703 * Use pPciDev->pDevIns to get the device instance.
3704 * @param iRegion The region number.
3705 * @param GCPhysAddress Physical address of the region.
3706 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3707 * I/O port, else it's a physical address.
3708 * This address is *NOT* relative
3709 * to pci_mem_base like earlier!
3710 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3711 */
3712DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3713{
3714 int rc;
3715 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3716 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3717
3718 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3719 if (enmType == PCI_ADDRESS_SPACE_IO)
3720 {
3721 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3722 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3723 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3724 if (RT_FAILURE(rc))
3725 return rc;
3726 if (pThis->fR0Enabled)
3727 {
3728 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3729 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3730 if (RT_FAILURE(rc))
3731 return rc;
3732 }
3733 if (pThis->fGCEnabled)
3734 {
3735 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3736 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3737 if (RT_FAILURE(rc))
3738 return rc;
3739 }
3740
3741 pThis->svga.BasePort = GCPhysAddress;
3742 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3743 }
3744 else
3745 {
3746 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3747 if (GCPhysAddress != NIL_RTGCPHYS)
3748 {
3749 /*
3750 * Mapping the FIFO RAM.
3751 */
3752 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3753 AssertRC(rc);
3754
3755# ifdef DEBUG_FIFO_ACCESS
3756 if (RT_SUCCESS(rc))
3757 {
3758 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3759 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3760 "VMSVGA FIFO");
3761 AssertRC(rc);
3762 }
3763# endif
3764 if (RT_SUCCESS(rc))
3765 {
3766 pThis->svga.GCPhysFIFO = GCPhysAddress;
3767 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3768 }
3769 }
3770 else
3771 {
3772 Assert(pThis->svga.GCPhysFIFO);
3773# ifdef DEBUG_FIFO_ACCESS
3774 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3775 AssertRC(rc);
3776# endif
3777 pThis->svga.GCPhysFIFO = 0;
3778 }
3779
3780 }
3781 return VINF_SUCCESS;
3782}
3783
3784# ifdef VBOX_WITH_VMSVGA3D
3785
3786/**
3787 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3788 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3789 *
3790 * @param pThis The VGA device instance data.
3791 * @param sid Either UINT32_MAX or the ID of a specific
3792 * surface. If UINT32_MAX is used, all surfaces
3793 * are processed.
3794 */
3795void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3796{
3797 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3798 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3799}
3800
3801
3802/**
3803 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3804 */
3805DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3806{
3807 /* There might be a specific context ID at the start of the
3808 arguments, if not show all contexts. */
3809 uint32_t cid = UINT32_MAX;
3810 if (pszArgs)
3811 pszArgs = RTStrStripL(pszArgs);
3812 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3813 cid = RTStrToUInt32(pszArgs);
3814
3815 /* Verbose or terse display, we default to verbose. */
3816 bool fVerbose = true;
3817 if (RTStrIStr(pszArgs, "terse"))
3818 fVerbose = false;
3819
3820 /* The size of the ascii art (x direction, y is 3/4 of x). */
3821 uint32_t cxAscii = 80;
3822 if (RTStrIStr(pszArgs, "gigantic"))
3823 cxAscii = 300;
3824 else if (RTStrIStr(pszArgs, "huge"))
3825 cxAscii = 180;
3826 else if (RTStrIStr(pszArgs, "big"))
3827 cxAscii = 132;
3828 else if (RTStrIStr(pszArgs, "normal"))
3829 cxAscii = 80;
3830 else if (RTStrIStr(pszArgs, "medium"))
3831 cxAscii = 64;
3832 else if (RTStrIStr(pszArgs, "small"))
3833 cxAscii = 48;
3834 else if (RTStrIStr(pszArgs, "tiny"))
3835 cxAscii = 24;
3836
3837 /* Y invert the image when producing the ASCII art. */
3838 bool fInvY = false;
3839 if (RTStrIStr(pszArgs, "invy"))
3840 fInvY = true;
3841
3842 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3843}
3844
3845
3846/**
3847 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3848 */
3849DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3850{
3851 /* There might be a specific surface ID at the start of the
3852 arguments, if not show all contexts. */
3853 uint32_t sid = UINT32_MAX;
3854 if (pszArgs)
3855 pszArgs = RTStrStripL(pszArgs);
3856 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3857 sid = RTStrToUInt32(pszArgs);
3858
3859 /* Verbose or terse display, we default to verbose. */
3860 bool fVerbose = true;
3861 if (RTStrIStr(pszArgs, "terse"))
3862 fVerbose = false;
3863
3864 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3865}
3866
3867# endif /* VBOX_WITH_VMSVGA3D */
3868
3869/**
3870 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3871 */
3872static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3873{
3874 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3875 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3876
3877 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3878 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3879 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3880 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3881 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3882 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3883 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3884 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3885 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3886 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3887 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3888 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3889 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3890 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3891 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3892 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3893 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3894 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3895 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3896 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3897 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3898 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3899
3900 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3901 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3902 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3903 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3904
3905# ifdef VBOX_WITH_VMSVGA3D
3906 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3907 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3908 if (pThis->svga.u64HostWindowId != 0)
3909 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3910# endif
3911}
3912
3913
3914/**
3915 * @copydoc FNSSMDEVLOADEXEC
3916 */
3917int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3918{
3919 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3920 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3921 int rc;
3922
3923 /* Load our part of the VGAState */
3924 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3925 AssertRCReturn(rc, rc);
3926
3927 /* Load the framebuffer backup. */
3928 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3929 AssertRCReturn(rc, rc);
3930
3931 /* Load the VMSVGA state. */
3932 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3933 AssertRCReturn(rc, rc);
3934
3935 /* Load the active cursor bitmaps. */
3936 if (pSVGAState->Cursor.fActive)
3937 {
3938 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3939 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3940
3941 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3942 AssertRCReturn(rc, rc);
3943 }
3944
3945 /* Load the GMR state */
3946 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3947 {
3948 PGMR pGMR = &pSVGAState->aGMR[i];
3949
3950 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3951 AssertRCReturn(rc, rc);
3952
3953 if (pGMR->numDescriptors)
3954 {
3955 /* Allocate the maximum amount possible (everything non-continuous) */
3956 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3957 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3958 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3959
3960 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3961 {
3962 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3963 AssertRCReturn(rc, rc);
3964 }
3965 }
3966 }
3967
3968# ifdef VBOX_WITH_VMSVGA3D
3969 if (pThis->svga.f3DEnabled)
3970 {
3971# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
3972 vmsvga3dPowerOn(pThis);
3973# endif
3974
3975 VMSVGA_STATE_LOAD LoadState;
3976 LoadState.pSSM = pSSM;
3977 LoadState.uVersion = uVersion;
3978 LoadState.uPass = uPass;
3979 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
3980 AssertLogRelRCReturn(rc, rc);
3981 }
3982# endif
3983
3984 return VINF_SUCCESS;
3985}
3986
3987/**
3988 * Reinit the video mode after the state has been loaded.
3989 */
3990int vmsvgaLoadDone(PPDMDEVINS pDevIns)
3991{
3992 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3993 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3994
3995 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3996 vmsvgaChangeMode(pThis);
3997
3998 /* Set the active cursor. */
3999 if (pSVGAState->Cursor.fActive)
4000 {
4001 int rc;
4002
4003 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4004 true,
4005 true,
4006 pSVGAState->Cursor.xHotspot,
4007 pSVGAState->Cursor.yHotspot,
4008 pSVGAState->Cursor.width,
4009 pSVGAState->Cursor.height,
4010 pSVGAState->Cursor.pData);
4011 AssertRC(rc);
4012 }
4013 return VINF_SUCCESS;
4014}
4015
4016/**
4017 * @copydoc FNSSMDEVSAVEEXEC
4018 */
4019int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4020{
4021 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4022 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4023 int rc;
4024
4025 /* Save our part of the VGAState */
4026 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4027 AssertLogRelRCReturn(rc, rc);
4028
4029 /* Save the framebuffer backup. */
4030 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4031 AssertLogRelRCReturn(rc, rc);
4032
4033 /* Save the VMSVGA state. */
4034 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4035 AssertLogRelRCReturn(rc, rc);
4036
4037 /* Save the active cursor bitmaps. */
4038 if (pSVGAState->Cursor.fActive)
4039 {
4040 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4041 AssertLogRelRCReturn(rc, rc);
4042 }
4043
4044 /* Save the GMR state */
4045 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4046 {
4047 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4048 AssertLogRelRCReturn(rc, rc);
4049
4050 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4051 {
4052 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4053 AssertLogRelRCReturn(rc, rc);
4054 }
4055 }
4056
4057# ifdef VBOX_WITH_VMSVGA3D
4058 /*
4059 * Must save the 3d state in the FIFO thread.
4060 */
4061 if (pThis->svga.f3DEnabled)
4062 {
4063 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4064 AssertLogRelRCReturn(rc, rc);
4065 }
4066# endif
4067 return VINF_SUCCESS;
4068}
4069
4070/**
4071 * Resets the SVGA hardware state
4072 *
4073 * @returns VBox status code.
4074 * @param pDevIns The device instance.
4075 */
4076int vmsvgaReset(PPDMDEVINS pDevIns)
4077{
4078 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4079 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4080
4081 /* Reset before init? */
4082 if (!pSVGAState)
4083 return VINF_SUCCESS;
4084
4085 Log(("vmsvgaReset\n"));
4086
4087
4088 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4089 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4090 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4091
4092 /* Reset other stuff. */
4093 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4094 RT_ZERO(pThis->svga.au32ScratchRegion);
4095 RT_ZERO(*pThis->svga.pSvgaR3State);
4096 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4097
4098 /* Register caps. */
4099 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4100# ifdef VBOX_WITH_VMSVGA3D
4101 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4102# endif
4103
4104 /* Setup FIFO capabilities. */
4105 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4106
4107 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4108 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4109
4110 /* VRAM tracking is enabled by default during bootup. */
4111 pThis->svga.fVRAMTracking = true;
4112 pThis->svga.fEnabled = false;
4113
4114 /* Invalidate current settings. */
4115 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4116 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4117 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4118 pThis->svga.cbScanline = 0;
4119
4120 return rc;
4121}
4122
4123/**
4124 * Cleans up the SVGA hardware state
4125 *
4126 * @returns VBox status code.
4127 * @param pDevIns The device instance.
4128 */
4129int vmsvgaDestruct(PPDMDEVINS pDevIns)
4130{
4131 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4132
4133 /*
4134 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4135 */
4136 if (pThis->svga.pFIFOIOThread)
4137 {
4138 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4139 AssertLogRelRC(rc);
4140
4141 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4142 AssertLogRelRC(rc);
4143 pThis->svga.pFIFOIOThread = NULL;
4144 }
4145
4146 /*
4147 * Destroy the special SVGA state.
4148 */
4149 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4150 if (pSVGAState)
4151 {
4152# ifndef VMSVGA_USE_EMT_HALT_CODE
4153 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4154 {
4155 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4156 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4157 }
4158# endif
4159 if (pSVGAState->Cursor.fActive)
4160 RTMemFree(pSVGAState->Cursor.pData);
4161
4162 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4163 if (pSVGAState->aGMR[i].paDesc)
4164 RTMemFree(pSVGAState->aGMR[i].paDesc);
4165
4166 RTMemFree(pSVGAState);
4167 pThis->svga.pSvgaR3State = NULL;
4168 }
4169
4170 /*
4171 * Free our resources residing in the VGA state.
4172 */
4173 if (pThis->svga.pFrameBufferBackup)
4174 RTMemFree(pThis->svga.pFrameBufferBackup);
4175 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4176 {
4177 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4178 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4179 }
4180 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4181 {
4182 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4183 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4184 }
4185
4186 return VINF_SUCCESS;
4187}
4188
4189/**
4190 * Initialize the SVGA hardware state
4191 *
4192 * @returns VBox status code.
4193 * @param pDevIns The device instance.
4194 */
4195int vmsvgaInit(PPDMDEVINS pDevIns)
4196{
4197 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4198 PVMSVGAR3STATE pSVGAState;
4199 PVM pVM = PDMDevHlpGetVM(pDevIns);
4200 int rc;
4201
4202 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4203 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4204
4205 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4206 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4207 pSVGAState = pThis->svga.pSvgaR3State;
4208
4209 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4210 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4211 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4212
4213 /* Create event semaphore. */
4214 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4215
4216 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4217 if (RT_FAILURE(rc))
4218 {
4219 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4220 return rc;
4221 }
4222
4223 /* Create event semaphore. */
4224 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4225 if (RT_FAILURE(rc))
4226 {
4227 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4228 return rc;
4229 }
4230
4231# ifndef VMSVGA_USE_EMT_HALT_CODE
4232 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4233 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4234 AssertRCReturn(rc, rc);
4235# endif
4236
4237 /* Register caps. */
4238 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4239# ifdef VBOX_WITH_VMSVGA3D
4240 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4241# endif
4242
4243 /* Setup FIFO capabilities. */
4244 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4245
4246 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4247 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4248
4249 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4250# ifdef VBOX_WITH_VMSVGA3D
4251 if (pThis->svga.f3DEnabled)
4252 {
4253 rc = vmsvga3dInit(pThis);
4254 if (RT_FAILURE(rc))
4255 {
4256 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4257 pThis->svga.f3DEnabled = false;
4258 }
4259 }
4260# endif
4261 /* VRAM tracking is enabled by default during bootup. */
4262 pThis->svga.fVRAMTracking = true;
4263
4264 /* Invalidate current settings. */
4265 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4266 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4267 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4268 pThis->svga.cbScanline = 0;
4269
4270 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4271 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4272 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4273 {
4274 pThis->svga.u32MaxWidth -= 256;
4275 pThis->svga.u32MaxHeight -= 256;
4276 }
4277 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4278
4279# ifdef DEBUG_GMR_ACCESS
4280 /* Register the GMR access handler type. */
4281 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4282 vmsvgaR3GMRAccessHandler,
4283 NULL, NULL, NULL,
4284 NULL, NULL, NULL,
4285 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4286 AssertRCReturn(rc, rc);
4287# endif
4288# ifdef DEBUG_FIFO_ACCESS
4289 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4290 vmsvgaR3FIFOAccessHandler,
4291 NULL, NULL, NULL,
4292 NULL, NULL, NULL,
4293 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4294 AssertRCReturn(rc, rc);
4295#endif
4296
4297 /* Create the async IO thread. */
4298 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4299 RTTHREADTYPE_IO, "VMSVGA FIFO");
4300 if (RT_FAILURE(rc))
4301 {
4302 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4303 return rc;
4304 }
4305
4306 /*
4307 * Statistics.
4308 */
4309 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4310 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4311 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4312 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4313 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4314 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4315 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4316 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4317 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4318 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4319
4320 /*
4321 * Info handlers.
4322 */
4323 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4324# ifdef VBOX_WITH_VMSVGA3D
4325 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4326 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4327 "VMSVGA 3d surface details. "
4328 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4329 vmsvgaR3Info3dSurface);
4330# endif
4331
4332 return VINF_SUCCESS;
4333}
4334
4335# ifdef VBOX_WITH_VMSVGA3D
4336/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4337static const char * const g_apszVmSvgaDevCapNames[] =
4338{
4339 "x3D", /* = 0 */
4340 "xMAX_LIGHTS",
4341 "xMAX_TEXTURES",
4342 "xMAX_CLIP_PLANES",
4343 "xVERTEX_SHADER_VERSION",
4344 "xVERTEX_SHADER",
4345 "xFRAGMENT_SHADER_VERSION",
4346 "xFRAGMENT_SHADER",
4347 "xMAX_RENDER_TARGETS",
4348 "xS23E8_TEXTURES",
4349 "xS10E5_TEXTURES",
4350 "xMAX_FIXED_VERTEXBLEND",
4351 "xD16_BUFFER_FORMAT",
4352 "xD24S8_BUFFER_FORMAT",
4353 "xD24X8_BUFFER_FORMAT",
4354 "xQUERY_TYPES",
4355 "xTEXTURE_GRADIENT_SAMPLING",
4356 "rMAX_POINT_SIZE",
4357 "xMAX_SHADER_TEXTURES",
4358 "xMAX_TEXTURE_WIDTH",
4359 "xMAX_TEXTURE_HEIGHT",
4360 "xMAX_VOLUME_EXTENT",
4361 "xMAX_TEXTURE_REPEAT",
4362 "xMAX_TEXTURE_ASPECT_RATIO",
4363 "xMAX_TEXTURE_ANISOTROPY",
4364 "xMAX_PRIMITIVE_COUNT",
4365 "xMAX_VERTEX_INDEX",
4366 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4367 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4368 "xMAX_VERTEX_SHADER_TEMPS",
4369 "xMAX_FRAGMENT_SHADER_TEMPS",
4370 "xTEXTURE_OPS",
4371 "xSURFACEFMT_X8R8G8B8",
4372 "xSURFACEFMT_A8R8G8B8",
4373 "xSURFACEFMT_A2R10G10B10",
4374 "xSURFACEFMT_X1R5G5B5",
4375 "xSURFACEFMT_A1R5G5B5",
4376 "xSURFACEFMT_A4R4G4B4",
4377 "xSURFACEFMT_R5G6B5",
4378 "xSURFACEFMT_LUMINANCE16",
4379 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4380 "xSURFACEFMT_ALPHA8",
4381 "xSURFACEFMT_LUMINANCE8",
4382 "xSURFACEFMT_Z_D16",
4383 "xSURFACEFMT_Z_D24S8",
4384 "xSURFACEFMT_Z_D24X8",
4385 "xSURFACEFMT_DXT1",
4386 "xSURFACEFMT_DXT2",
4387 "xSURFACEFMT_DXT3",
4388 "xSURFACEFMT_DXT4",
4389 "xSURFACEFMT_DXT5",
4390 "xSURFACEFMT_BUMPX8L8V8U8",
4391 "xSURFACEFMT_A2W10V10U10",
4392 "xSURFACEFMT_BUMPU8V8",
4393 "xSURFACEFMT_Q8W8V8U8",
4394 "xSURFACEFMT_CxV8U8",
4395 "xSURFACEFMT_R_S10E5",
4396 "xSURFACEFMT_R_S23E8",
4397 "xSURFACEFMT_RG_S10E5",
4398 "xSURFACEFMT_RG_S23E8",
4399 "xSURFACEFMT_ARGB_S10E5",
4400 "xSURFACEFMT_ARGB_S23E8",
4401 "xMISSING62",
4402 "xMAX_VERTEX_SHADER_TEXTURES",
4403 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4404 "xSURFACEFMT_V16U16",
4405 "xSURFACEFMT_G16R16",
4406 "xSURFACEFMT_A16B16G16R16",
4407 "xSURFACEFMT_UYVY",
4408 "xSURFACEFMT_YUY2",
4409 "xMULTISAMPLE_NONMASKABLESAMPLES",
4410 "xMULTISAMPLE_MASKABLESAMPLES",
4411 "xALPHATOCOVERAGE",
4412 "xSUPERSAMPLE",
4413 "xAUTOGENMIPMAPS",
4414 "xSURFACEFMT_NV12",
4415 "xSURFACEFMT_AYUV",
4416 "xMAX_CONTEXT_IDS",
4417 "xMAX_SURFACE_IDS",
4418 "xSURFACEFMT_Z_DF16",
4419 "xSURFACEFMT_Z_DF24",
4420 "xSURFACEFMT_Z_D24S8_INT",
4421 "xSURFACEFMT_BC4_UNORM",
4422 "xSURFACEFMT_BC5_UNORM", /* 83 */
4423};
4424# endif
4425
4426
4427/**
4428 * Power On notification.
4429 *
4430 * @returns VBox status.
4431 * @param pDevIns The device instance data.
4432 *
4433 * @remarks Caller enters the device critical section.
4434 */
4435DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4436{
4437 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4438 int rc;
4439
4440# ifdef VBOX_WITH_VMSVGA3D
4441 if (pThis->svga.f3DEnabled)
4442 {
4443 rc = vmsvga3dPowerOn(pThis);
4444
4445 if (RT_SUCCESS(rc))
4446 {
4447 bool fSavedBuffering = RTLogRelSetBuffering(true);
4448 SVGA3dCapsRecord *pCaps;
4449 SVGA3dCapPair *pData;
4450 uint32_t idxCap = 0;
4451
4452 /* 3d hardware version; latest and greatest */
4453 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4454 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4455
4456 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4457 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4458 pData = (SVGA3dCapPair *)&pCaps->data;
4459
4460 /* Fill out all 3d capabilities. */
4461 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4462 {
4463 uint32_t val = 0;
4464
4465 rc = vmsvga3dQueryCaps(pThis, i, &val);
4466 if (RT_SUCCESS(rc))
4467 {
4468 pData[idxCap][0] = i;
4469 pData[idxCap][1] = val;
4470 idxCap++;
4471 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4472 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4473 else
4474 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4475 &g_apszVmSvgaDevCapNames[i][1]));
4476 }
4477 else
4478 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4479 }
4480 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4481 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4482
4483 /* Mark end of record array. */
4484 pCaps->header.length = 0;
4485
4486 RTLogRelSetBuffering(fSavedBuffering);
4487 }
4488 }
4489# endif // VBOX_WITH_VMSVGA3D
4490}
4491
4492#endif /* IN_RING3 */
4493
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