VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 58170

Last change on this file since 58170 was 58170, checked in by vboxsync, 9 years ago

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1/* $Id: DevVGA-SVGA.cpp 58170 2015-10-12 09:27:14Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2015 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295
296#ifdef LOG_ENABLED
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417/**
418 * FIFO command name lookup
419 *
420 * @returns FIFO command string or "UNKNOWN"
421 * @param u32Cmd FIFO command
422 */
423static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
424{
425 switch (u32Cmd)
426 {
427 case SVGA_CMD_INVALID_CMD:
428 return "SVGA_CMD_INVALID_CMD";
429 case SVGA_CMD_UPDATE:
430 return "SVGA_CMD_UPDATE";
431 case SVGA_CMD_RECT_COPY:
432 return "SVGA_CMD_RECT_COPY";
433 case SVGA_CMD_DEFINE_CURSOR:
434 return "SVGA_CMD_DEFINE_CURSOR";
435 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
436 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
437 case SVGA_CMD_UPDATE_VERBOSE:
438 return "SVGA_CMD_UPDATE_VERBOSE";
439 case SVGA_CMD_FRONT_ROP_FILL:
440 return "SVGA_CMD_FRONT_ROP_FILL";
441 case SVGA_CMD_FENCE:
442 return "SVGA_CMD_FENCE";
443 case SVGA_CMD_ESCAPE:
444 return "SVGA_CMD_ESCAPE";
445 case SVGA_CMD_DEFINE_SCREEN:
446 return "SVGA_CMD_DEFINE_SCREEN";
447 case SVGA_CMD_DESTROY_SCREEN:
448 return "SVGA_CMD_DESTROY_SCREEN";
449 case SVGA_CMD_DEFINE_GMRFB:
450 return "SVGA_CMD_DEFINE_GMRFB";
451 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
452 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
453 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
454 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
455 case SVGA_CMD_ANNOTATION_FILL:
456 return "SVGA_CMD_ANNOTATION_FILL";
457 case SVGA_CMD_ANNOTATION_COPY:
458 return "SVGA_CMD_ANNOTATION_COPY";
459 case SVGA_CMD_DEFINE_GMR2:
460 return "SVGA_CMD_DEFINE_GMR2";
461 case SVGA_CMD_REMAP_GMR2:
462 return "SVGA_CMD_REMAP_GMR2";
463 case SVGA_3D_CMD_SURFACE_DEFINE:
464 return "SVGA_3D_CMD_SURFACE_DEFINE";
465 case SVGA_3D_CMD_SURFACE_DESTROY:
466 return "SVGA_3D_CMD_SURFACE_DESTROY";
467 case SVGA_3D_CMD_SURFACE_COPY:
468 return "SVGA_3D_CMD_SURFACE_COPY";
469 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
470 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
471 case SVGA_3D_CMD_SURFACE_DMA:
472 return "SVGA_3D_CMD_SURFACE_DMA";
473 case SVGA_3D_CMD_CONTEXT_DEFINE:
474 return "SVGA_3D_CMD_CONTEXT_DEFINE";
475 case SVGA_3D_CMD_CONTEXT_DESTROY:
476 return "SVGA_3D_CMD_CONTEXT_DESTROY";
477 case SVGA_3D_CMD_SETTRANSFORM:
478 return "SVGA_3D_CMD_SETTRANSFORM";
479 case SVGA_3D_CMD_SETZRANGE:
480 return "SVGA_3D_CMD_SETZRANGE";
481 case SVGA_3D_CMD_SETRENDERSTATE:
482 return "SVGA_3D_CMD_SETRENDERSTATE";
483 case SVGA_3D_CMD_SETRENDERTARGET:
484 return "SVGA_3D_CMD_SETRENDERTARGET";
485 case SVGA_3D_CMD_SETTEXTURESTATE:
486 return "SVGA_3D_CMD_SETTEXTURESTATE";
487 case SVGA_3D_CMD_SETMATERIAL:
488 return "SVGA_3D_CMD_SETMATERIAL";
489 case SVGA_3D_CMD_SETLIGHTDATA:
490 return "SVGA_3D_CMD_SETLIGHTDATA";
491 case SVGA_3D_CMD_SETLIGHTENABLED:
492 return "SVGA_3D_CMD_SETLIGHTENABLED";
493 case SVGA_3D_CMD_SETVIEWPORT:
494 return "SVGA_3D_CMD_SETVIEWPORT";
495 case SVGA_3D_CMD_SETCLIPPLANE:
496 return "SVGA_3D_CMD_SETCLIPPLANE";
497 case SVGA_3D_CMD_CLEAR:
498 return "SVGA_3D_CMD_CLEAR";
499 case SVGA_3D_CMD_PRESENT:
500 return "SVGA_3D_CMD_PRESENT";
501 case SVGA_3D_CMD_SHADER_DEFINE:
502 return "SVGA_3D_CMD_SHADER_DEFINE";
503 case SVGA_3D_CMD_SHADER_DESTROY:
504 return "SVGA_3D_CMD_SHADER_DESTROY";
505 case SVGA_3D_CMD_SET_SHADER:
506 return "SVGA_3D_CMD_SET_SHADER";
507 case SVGA_3D_CMD_SET_SHADER_CONST:
508 return "SVGA_3D_CMD_SET_SHADER_CONST";
509 case SVGA_3D_CMD_DRAW_PRIMITIVES:
510 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
511 case SVGA_3D_CMD_SETSCISSORRECT:
512 return "SVGA_3D_CMD_SETSCISSORRECT";
513 case SVGA_3D_CMD_BEGIN_QUERY:
514 return "SVGA_3D_CMD_BEGIN_QUERY";
515 case SVGA_3D_CMD_END_QUERY:
516 return "SVGA_3D_CMD_END_QUERY";
517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
518 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
519 case SVGA_3D_CMD_PRESENT_READBACK:
520 return "SVGA_3D_CMD_PRESENT_READBACK";
521 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
522 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
523 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
524 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
525 case SVGA_3D_CMD_GENERATE_MIPMAPS:
526 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
527 case SVGA_3D_CMD_ACTIVATE_SURFACE:
528 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
529 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
530 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
531 default:
532 return "UNKNOWN";
533 }
534}
535#endif
536
537#ifdef IN_RING3
538/**
539 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
540 */
541DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
542{
543 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
544
545 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
546 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
547
548 if (x < pThis->svga.uWidth)
549 {
550 pThis->svga.viewport.x = x;
551 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
552 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
553 }
554 else
555 {
556 pThis->svga.viewport.x = pThis->svga.uWidth;
557 pThis->svga.viewport.cx = 0;
558 pThis->svga.viewport.xRight = pThis->svga.uWidth;
559 }
560 if (y < pThis->svga.uHeight)
561 {
562 pThis->svga.viewport.y = y;
563 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
564 pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
565 pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
566 }
567 else
568 {
569 pThis->svga.viewport.y = pThis->svga.uHeight;
570 pThis->svga.viewport.cy = 0;
571 pThis->svga.viewport.yLowWC = 0;
572 pThis->svga.viewport.yHighWC = 0;
573 }
574
575# ifdef VBOX_WITH_VMSVGA3D
576 /*
577 * Now inform the 3D backend.
578 */
579 if (pThis->svga.f3DEnabled)
580 vmsvga3dUpdateHostScreenViewport(pThis, uScreenId, &OldViewport);
581# endif
582}
583#endif /* IN_RING3 */
584
585/**
586 * Read port register
587 *
588 * @returns VBox status code.
589 * @param pThis VMSVGA State
590 * @param pu32 Where to store the read value
591 */
592PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
593{
594 int rc = VINF_SUCCESS;
595
596 *pu32 = 0;
597 switch (pThis->svga.u32IndexReg)
598 {
599 case SVGA_REG_ID:
600 *pu32 = pThis->svga.u32SVGAId;
601 break;
602
603 case SVGA_REG_ENABLE:
604 *pu32 = pThis->svga.fEnabled;
605 break;
606
607 case SVGA_REG_WIDTH:
608 {
609 if ( pThis->svga.fEnabled
610 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
611 {
612 *pu32 = pThis->svga.uWidth;
613 }
614 else
615 {
616#ifndef IN_RING3
617 rc = VINF_IOM_R3_IOPORT_READ;
618#else
619 *pu32 = pThis->pDrv->cx;
620#endif
621 }
622 break;
623 }
624
625 case SVGA_REG_HEIGHT:
626 {
627 if ( pThis->svga.fEnabled
628 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
629 {
630 *pu32 = pThis->svga.uHeight;
631 }
632 else
633 {
634#ifndef IN_RING3
635 rc = VINF_IOM_R3_IOPORT_READ;
636#else
637 *pu32 = pThis->pDrv->cy;
638#endif
639 }
640 break;
641 }
642
643 case SVGA_REG_MAX_WIDTH:
644 *pu32 = pThis->svga.u32MaxWidth;
645 break;
646
647 case SVGA_REG_MAX_HEIGHT:
648 *pu32 = pThis->svga.u32MaxHeight;
649 break;
650
651 case SVGA_REG_DEPTH:
652 /* This returns the color depth of the current mode. */
653 switch (pThis->svga.uBpp)
654 {
655 case 15:
656 case 16:
657 case 24:
658 *pu32 = pThis->svga.uBpp;
659 break;
660
661 default:
662 case 32:
663 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
664 break;
665 }
666 break;
667
668 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
669 if ( pThis->svga.fEnabled
670 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
671 {
672 *pu32 = pThis->svga.uBpp;
673 }
674 else
675 {
676#ifndef IN_RING3
677 rc = VINF_IOM_R3_IOPORT_READ;
678#else
679 *pu32 = pThis->pDrv->cBits;
680#endif
681 }
682 break;
683
684 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
685 if ( pThis->svga.fEnabled
686 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
687 {
688 *pu32 = (pThis->svga.uBpp + 7) & ~7;
689 }
690 else
691 {
692#ifndef IN_RING3
693 rc = VINF_IOM_R3_IOPORT_READ;
694#else
695 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
696#endif
697 }
698 break;
699
700 case SVGA_REG_PSEUDOCOLOR:
701 *pu32 = 0;
702 break;
703
704 case SVGA_REG_RED_MASK:
705 case SVGA_REG_GREEN_MASK:
706 case SVGA_REG_BLUE_MASK:
707 {
708 uint32_t uBpp;
709
710 if ( pThis->svga.fEnabled
711 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
712 {
713 uBpp = pThis->svga.uBpp;
714 }
715 else
716 {
717#ifndef IN_RING3
718 rc = VINF_IOM_R3_IOPORT_READ;
719 break;
720#else
721 uBpp = pThis->pDrv->cBits;
722#endif
723 }
724 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
725 switch (uBpp)
726 {
727 case 8:
728 u32RedMask = 0x07;
729 u32GreenMask = 0x38;
730 u32BlueMask = 0xc0;
731 break;
732
733 case 15:
734 u32RedMask = 0x0000001f;
735 u32GreenMask = 0x000003e0;
736 u32BlueMask = 0x00007c00;
737 break;
738
739 case 16:
740 u32RedMask = 0x0000001f;
741 u32GreenMask = 0x000007e0;
742 u32BlueMask = 0x0000f800;
743 break;
744
745 case 24:
746 case 32:
747 default:
748 u32RedMask = 0x00ff0000;
749 u32GreenMask = 0x0000ff00;
750 u32BlueMask = 0x000000ff;
751 break;
752 }
753 switch (pThis->svga.u32IndexReg)
754 {
755 case SVGA_REG_RED_MASK:
756 *pu32 = u32RedMask;
757 break;
758
759 case SVGA_REG_GREEN_MASK:
760 *pu32 = u32GreenMask;
761 break;
762
763 case SVGA_REG_BLUE_MASK:
764 *pu32 = u32BlueMask;
765 break;
766 }
767 break;
768 }
769
770 case SVGA_REG_BYTES_PER_LINE:
771 {
772 if ( pThis->svga.fEnabled
773 && pThis->svga.cbScanline)
774 {
775 *pu32 = pThis->svga.cbScanline;
776 }
777 else
778 {
779#ifndef IN_RING3
780 rc = VINF_IOM_R3_IOPORT_READ;
781#else
782 *pu32 = pThis->pDrv->cbScanline;
783#endif
784 }
785 break;
786 }
787
788 case SVGA_REG_VRAM_SIZE: /* VRAM size */
789 *pu32 = pThis->vram_size;
790 break;
791
792 case SVGA_REG_FB_START: /* Frame buffer physical address. */
793 Assert(pThis->GCPhysVRAM <= 0xffffffff);
794 *pu32 = pThis->GCPhysVRAM;
795 break;
796
797 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
798 /* Always zero in our case. */
799 *pu32 = 0;
800 break;
801
802 case SVGA_REG_FB_SIZE: /* Frame buffer size */
803 {
804#ifndef IN_RING3
805 rc = VINF_IOM_R3_IOPORT_READ;
806#else
807 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
808 if ( pThis->svga.fEnabled
809 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
810 {
811 /* Hardware enabled; return real framebuffer size .*/
812 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
813 }
814 else
815 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
816
817 *pu32 = RT_MIN(pThis->vram_size, *pu32);
818 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
819#endif
820 break;
821 }
822
823 case SVGA_REG_CAPABILITIES:
824 *pu32 = pThis->svga.u32RegCaps;
825 break;
826
827 case SVGA_REG_MEM_START: /* FIFO start */
828 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
829 *pu32 = pThis->svga.GCPhysFIFO;
830 break;
831
832 case SVGA_REG_MEM_SIZE: /* FIFO size */
833 *pu32 = pThis->svga.cbFIFO;
834 break;
835
836 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
837 *pu32 = pThis->svga.fConfigured;
838 break;
839
840 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
841 *pu32 = 0;
842 break;
843
844 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
845 if (pThis->svga.fBusy)
846 {
847#ifndef IN_RING3
848 /* Go to ring-3 and halt the CPU. */
849 rc = VINF_IOM_R3_IOPORT_READ;
850 break;
851#elif defined(VMSVGA_USE_EMT_HALT_CODE)
852 /* The guest is basically doing a HLT via the device here, but with
853 a special wake up condition on FIFO completion. */
854 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
855 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
856 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
857 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
858 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
859 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
860 if (pThis->svga.fBusy)
861 rc = VMR3WaitForDeviceReady(pVM, idCpu);
862 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
863 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
864#else
865
866 /* Delay the EMT a bit so the FIFO and others can get some work done.
867 This used to be a crude 50 ms sleep. The current code tries to be
868 more efficient, but the consept is still very crude. */
869 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
870 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
871 RTThreadYield();
872 if (pThis->svga.fBusy)
873 {
874 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
875
876 if (pThis->svga.fBusy && cRefs == 1)
877 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
878 if (pThis->svga.fBusy)
879 {
880 /** @todo If this code is going to stay, we need to call into the halt/wait
881 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
882 * suffer when the guest is polling on a busy FIFO. */
883 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
884 if (cNsMaxWait >= RT_NS_100US)
885 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
886 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
887 RT_MIN(cNsMaxWait, RT_NS_10MS));
888 }
889
890 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
891 }
892 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
893#endif
894 *pu32 = pThis->svga.fBusy != 0;
895 }
896 else
897 *pu32 = false;
898 break;
899
900 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
901 *pu32 = pThis->svga.u32GuestId;
902 break;
903
904 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
905 *pu32 = pThis->svga.cScratchRegion;
906 break;
907
908 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
909 *pu32 = SVGA_FIFO_NUM_REGS;
910 break;
911
912 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
913 *pu32 = pThis->svga.u32PitchLock;
914 break;
915
916 case SVGA_REG_IRQMASK: /* Interrupt mask */
917 *pu32 = pThis->svga.u32IrqMask;
918 break;
919
920 /* See "Guest memory regions" below. */
921 case SVGA_REG_GMR_ID:
922 *pu32 = pThis->svga.u32CurrentGMRId;
923 break;
924
925 case SVGA_REG_GMR_DESCRIPTOR:
926 /* Write only */
927 *pu32 = 0;
928 break;
929
930 case SVGA_REG_GMR_MAX_IDS:
931 *pu32 = VMSVGA_MAX_GMR_IDS;
932 break;
933
934 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
935 *pu32 = VMSVGA_MAX_GMR_PAGES;
936 break;
937
938 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
939 *pu32 = pThis->svga.fTraces;
940 break;
941
942 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
943 *pu32 = VMSVGA_MAX_GMR_PAGES;
944 break;
945
946 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
947 *pu32 = VMSVGA_SURFACE_SIZE;
948 break;
949
950 case SVGA_REG_TOP: /* Must be 1 more than the last register */
951 break;
952
953 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
954 break;
955 /* Next 768 (== 256*3) registers exist for colormap */
956
957 /* Mouse cursor support. */
958 case SVGA_REG_CURSOR_ID:
959 case SVGA_REG_CURSOR_X:
960 case SVGA_REG_CURSOR_Y:
961 case SVGA_REG_CURSOR_ON:
962 break;
963
964 /* Legacy multi-monitor support */
965 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
966 *pu32 = 1;
967 break;
968
969 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
970 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
971 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
972 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
973 *pu32 = 0;
974 break;
975
976 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
977 *pu32 = pThis->svga.uWidth;
978 break;
979
980 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
981 *pu32 = pThis->svga.uHeight;
982 break;
983
984 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
985 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
986 break;
987
988 default:
989 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
990 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
991 {
992 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
993 }
994 break;
995 }
996 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
997 return rc;
998}
999
1000#ifdef IN_RING3
1001/**
1002 * Apply the current resolution settings to change the video mode.
1003 *
1004 * @returns VBox status code.
1005 * @param pThis VMSVGA State
1006 */
1007int vmsvgaChangeMode(PVGASTATE pThis)
1008{
1009 int rc;
1010
1011 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1012 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1013 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1014 {
1015 /* Mode change in progress; wait for all values to be set. */
1016 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1017 return VINF_SUCCESS;
1018 }
1019
1020 if ( pThis->svga.uWidth == 0
1021 || pThis->svga.uHeight == 0
1022 || pThis->svga.uBpp == 0)
1023 {
1024 /* Invalid mode change - BB does this early in the boot up. */
1025 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1026 return VINF_SUCCESS;
1027 }
1028
1029 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1030 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1031 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1032 && pThis->last_width == (unsigned)pThis->svga.uWidth
1033 && pThis->last_height == (unsigned)pThis->svga.uHeight
1034 )
1035 {
1036 /* Nothing to do. */
1037 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1038 return VINF_SUCCESS;
1039 }
1040
1041 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1042 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1043
1044 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1045 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1046 AssertRC(rc);
1047 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1048
1049 /* last stuff */
1050 pThis->last_bpp = pThis->svga.uBpp;
1051 pThis->last_scr_width = pThis->svga.uWidth;
1052 pThis->last_scr_height = pThis->svga.uHeight;
1053 pThis->last_width = pThis->svga.uWidth;
1054 pThis->last_height = pThis->svga.uHeight;
1055
1056 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1057
1058 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1059 if ( pThis->svga.viewport.cx == 0
1060 && pThis->svga.viewport.cy == 0)
1061 {
1062 pThis->svga.viewport.cx = pThis->svga.uWidth;
1063 pThis->svga.viewport.xRight = pThis->svga.uWidth;
1064 pThis->svga.viewport.cy = pThis->svga.uHeight;
1065 pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1066 pThis->svga.viewport.yLowWC = 0;
1067 }
1068 return VINF_SUCCESS;
1069}
1070#endif /* IN_RING3 */
1071
1072#if defined(IN_RING0) || defined(IN_RING3)
1073/**
1074 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1075 *
1076 * @param pThis The VMSVGA state.
1077 * @param fState The busy state.
1078 */
1079DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1080{
1081 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1082
1083 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1084 {
1085 /* Race / unfortunately scheduling. Highly unlikly. */
1086 uint32_t cLoops = 64;
1087 do
1088 {
1089 ASMNopPause();
1090 fState = (pThis->svga.fBusy != 0);
1091 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1092 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1093 }
1094}
1095#endif
1096
1097/**
1098 * Write port register
1099 *
1100 * @returns VBox status code.
1101 * @param pThis VMSVGA State
1102 * @param u32 Value to write
1103 */
1104PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1105{
1106#ifdef IN_RING3
1107 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1108#endif
1109 int rc = VINF_SUCCESS;
1110
1111 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1112 switch (pThis->svga.u32IndexReg)
1113 {
1114 case SVGA_REG_ID:
1115 if ( u32 == SVGA_ID_0
1116 || u32 == SVGA_ID_1
1117 || u32 == SVGA_ID_2)
1118 pThis->svga.u32SVGAId = u32;
1119 break;
1120
1121 case SVGA_REG_ENABLE:
1122 if ( pThis->svga.fEnabled == u32
1123 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1124 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1125 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1126 && pThis->last_width == (unsigned)pThis->svga.uWidth
1127 && pThis->last_height == (unsigned)pThis->svga.uHeight
1128 )
1129 /* Nothing to do. */
1130 break;
1131
1132#ifdef IN_RING3
1133 if ( u32 == 1
1134 && pThis->svga.fEnabled == false)
1135 {
1136 /* Make a backup copy of the first 32k in order to save font data etc. */
1137 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1138 }
1139
1140 pThis->svga.fEnabled = u32;
1141 if (pThis->svga.fEnabled)
1142 {
1143 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1144 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1145 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1146 {
1147 /* Keep the current mode. */
1148 pThis->svga.uWidth = pThis->pDrv->cx;
1149 pThis->svga.uHeight = pThis->pDrv->cy;
1150 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1151 }
1152
1153 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1154 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1155 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1156 {
1157 rc = vmsvgaChangeMode(pThis);
1158 AssertRCReturn(rc, rc);
1159 }
1160 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1161 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1162 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1163
1164 /* Disable or enable dirty page tracking according to the current fTraces value. */
1165 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1166 }
1167 else
1168 {
1169 /* Restore the text mode backup. */
1170 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1171
1172/* pThis->svga.uHeight = -1;
1173 pThis->svga.uWidth = -1;
1174 pThis->svga.uBpp = -1;
1175 pThis->svga.cbScanline = 0; */
1176 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1177
1178 /* Enable dirty page tracking again when going into legacy mode. */
1179 vmsvgaSetTraces(pThis, true);
1180 }
1181#else
1182 rc = VINF_IOM_R3_IOPORT_WRITE;
1183#endif
1184 break;
1185
1186 case SVGA_REG_WIDTH:
1187 if (pThis->svga.uWidth != u32)
1188 {
1189 if (pThis->svga.fEnabled)
1190 {
1191#ifdef IN_RING3
1192 pThis->svga.uWidth = u32;
1193 rc = vmsvgaChangeMode(pThis);
1194 AssertRCReturn(rc, rc);
1195#else
1196 rc = VINF_IOM_R3_IOPORT_WRITE;
1197#endif
1198 }
1199 else
1200 pThis->svga.uWidth = u32;
1201 }
1202 /* else: nop */
1203 break;
1204
1205 case SVGA_REG_HEIGHT:
1206 if (pThis->svga.uHeight != u32)
1207 {
1208 if (pThis->svga.fEnabled)
1209 {
1210#ifdef IN_RING3
1211 pThis->svga.uHeight = u32;
1212 rc = vmsvgaChangeMode(pThis);
1213 AssertRCReturn(rc, rc);
1214#else
1215 rc = VINF_IOM_R3_IOPORT_WRITE;
1216#endif
1217 }
1218 else
1219 pThis->svga.uHeight = u32;
1220 }
1221 /* else: nop */
1222 break;
1223
1224 case SVGA_REG_DEPTH:
1225 /** @todo read-only?? */
1226 break;
1227
1228 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1229 if (pThis->svga.uBpp != u32)
1230 {
1231 if (pThis->svga.fEnabled)
1232 {
1233#ifdef IN_RING3
1234 pThis->svga.uBpp = u32;
1235 rc = vmsvgaChangeMode(pThis);
1236 AssertRCReturn(rc, rc);
1237#else
1238 rc = VINF_IOM_R3_IOPORT_WRITE;
1239#endif
1240 }
1241 else
1242 pThis->svga.uBpp = u32;
1243 }
1244 /* else: nop */
1245 break;
1246
1247 case SVGA_REG_PSEUDOCOLOR:
1248 break;
1249
1250 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1251#ifdef IN_RING3
1252 pThis->svga.fConfigured = u32;
1253 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1254 if (!pThis->svga.fConfigured)
1255 {
1256 pThis->svga.fTraces = true;
1257 }
1258 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1259#else
1260 rc = VINF_IOM_R3_IOPORT_WRITE;
1261#endif
1262 break;
1263
1264 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1265 if ( pThis->svga.fEnabled
1266 && pThis->svga.fConfigured)
1267 {
1268#if defined(IN_RING3) || defined(IN_RING0)
1269 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1270 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1271 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1272 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1273
1274 /* Kick the FIFO thread to start processing commands again. */
1275 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1276#else
1277 rc = VINF_IOM_R3_IOPORT_WRITE;
1278#endif
1279 }
1280 /* else nothing to do. */
1281 else
1282 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1283
1284 break;
1285
1286 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1287 break;
1288
1289 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1290 pThis->svga.u32GuestId = u32;
1291 break;
1292
1293 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1294 pThis->svga.u32PitchLock = u32;
1295 break;
1296
1297 case SVGA_REG_IRQMASK: /* Interrupt mask */
1298 pThis->svga.u32IrqMask = u32;
1299
1300 /* Irq pending after the above change? */
1301 if (pThis->svga.u32IrqStatus & u32)
1302 {
1303 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1304 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1305 }
1306 else
1307 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1308 break;
1309
1310 /* Mouse cursor support */
1311 case SVGA_REG_CURSOR_ID:
1312 case SVGA_REG_CURSOR_X:
1313 case SVGA_REG_CURSOR_Y:
1314 case SVGA_REG_CURSOR_ON:
1315 break;
1316
1317 /* Legacy multi-monitor support */
1318 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1319 break;
1320 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1321 break;
1322 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1323 break;
1324 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1325 break;
1326 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1327 break;
1328 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1329 break;
1330 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1331 break;
1332#ifdef VBOX_WITH_VMSVGA3D
1333 /* See "Guest memory regions" below. */
1334 case SVGA_REG_GMR_ID:
1335 pThis->svga.u32CurrentGMRId = u32;
1336 break;
1337
1338 case SVGA_REG_GMR_DESCRIPTOR:
1339# ifndef IN_RING3
1340 rc = VINF_IOM_R3_IOPORT_WRITE;
1341 break;
1342# else /* IN_RING3 */
1343 {
1344 SVGAGuestMemDescriptor desc;
1345 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1346 RTGCPHYS GCPhysBase = GCPhys;
1347 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1348 uint32_t cDescriptorsAllocated = 16;
1349 uint32_t iDescriptor = 0;
1350
1351 /* Validate current GMR id. */
1352 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1353
1354 /* Free the old GMR if present. */
1355 vmsvgaGMRFree(pThis, idGMR);
1356
1357 /* Just undefine the GMR? */
1358 if (GCPhys == 0)
1359 break;
1360
1361 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1362 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1363
1364 /* Never cross a page boundary automatically. */
1365 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1366 {
1367 /* Read descriptor. */
1368 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1369 AssertRCBreak(rc);
1370
1371 if ( desc.ppn == 0
1372 && desc.numPages == 0)
1373 break; /* terminator */
1374
1375 if ( desc.ppn != 0
1376 && desc.numPages == 0)
1377 {
1378 /* Pointer to the next physical page of descriptors. */
1379 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1380 }
1381 else
1382 {
1383 if (iDescriptor == cDescriptorsAllocated)
1384 {
1385 cDescriptorsAllocated += 16;
1386 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1387 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1388 }
1389
1390 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1391 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1392 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1393
1394 /* Continue with the next descriptor. */
1395 GCPhys += sizeof(desc);
1396 }
1397 }
1398 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1399 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1400
1401 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1402 {
1403 AssertFailed();
1404 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1405 pSVGAState->aGMR[idGMR].paDesc = NULL;
1406 }
1407 AssertRC(rc);
1408 break;
1409 }
1410# endif /* IN_RING3 */
1411#endif // VBOX_WITH_VMSVGA3D
1412
1413 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1414 if (pThis->svga.fTraces == u32)
1415 break; /* nothing to do */
1416
1417#ifdef IN_RING3
1418 vmsvgaSetTraces(pThis, !!u32);
1419#else
1420 rc = VINF_IOM_R3_IOPORT_WRITE;
1421#endif
1422 break;
1423
1424 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1425 break;
1426
1427 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1428 break;
1429 /* Next 768 (== 256*3) registers exist for colormap */
1430
1431 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1432 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1433 break;
1434
1435 case SVGA_REG_FB_START:
1436 case SVGA_REG_MEM_START:
1437 case SVGA_REG_HOST_BITS_PER_PIXEL:
1438 case SVGA_REG_MAX_WIDTH:
1439 case SVGA_REG_MAX_HEIGHT:
1440 case SVGA_REG_VRAM_SIZE:
1441 case SVGA_REG_FB_SIZE:
1442 case SVGA_REG_CAPABILITIES:
1443 case SVGA_REG_MEM_SIZE:
1444 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1445 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1446 case SVGA_REG_BYTES_PER_LINE:
1447 case SVGA_REG_FB_OFFSET:
1448 case SVGA_REG_RED_MASK:
1449 case SVGA_REG_GREEN_MASK:
1450 case SVGA_REG_BLUE_MASK:
1451 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1452 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1453 case SVGA_REG_GMR_MAX_IDS:
1454 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1455 /* Read only - ignore. */
1456 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1457 break;
1458
1459 default:
1460 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1461 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1462 {
1463 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1464 }
1465 break;
1466 }
1467 return rc;
1468}
1469
1470/**
1471 * Port I/O Handler for IN operations.
1472 *
1473 * @returns VINF_SUCCESS or VINF_EM_*.
1474 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1475 *
1476 * @param pDevIns The device instance.
1477 * @param pvUser User argument.
1478 * @param uPort Port number used for the IN operation.
1479 * @param pu32 Where to store the result. This is always a 32-bit
1480 * variable regardless of what @a cb might say.
1481 * @param cb Number of bytes read.
1482 */
1483PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1484{
1485 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1486 int rc = VINF_SUCCESS;
1487
1488 /* Ignore non-dword accesses. */
1489 if (cb != 4)
1490 {
1491 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1492 *pu32 = ~0;
1493 return VINF_SUCCESS;
1494 }
1495
1496 switch (Port - pThis->svga.BasePort)
1497 {
1498 case SVGA_INDEX_PORT:
1499 *pu32 = pThis->svga.u32IndexReg;
1500 break;
1501
1502 case SVGA_VALUE_PORT:
1503 return vmsvgaReadPort(pThis, pu32);
1504
1505 case SVGA_BIOS_PORT:
1506 Log(("Ignoring BIOS port read\n"));
1507 *pu32 = 0;
1508 break;
1509
1510 case SVGA_IRQSTATUS_PORT:
1511 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1512 *pu32 = pThis->svga.u32IrqStatus;
1513 break;
1514 }
1515 return rc;
1516}
1517
1518/**
1519 * Port I/O Handler for OUT operations.
1520 *
1521 * @returns VINF_SUCCESS or VINF_EM_*.
1522 *
1523 * @param pDevIns The device instance.
1524 * @param pvUser User argument.
1525 * @param uPort Port number used for the OUT operation.
1526 * @param u32 The value to output.
1527 * @param cb The value size in bytes.
1528 */
1529PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1530{
1531 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1532 int rc = VINF_SUCCESS;
1533
1534 /* Ignore non-dword accesses. */
1535 if (cb != 4)
1536 {
1537 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1538 return VINF_SUCCESS;
1539 }
1540
1541 switch (Port - pThis->svga.BasePort)
1542 {
1543 case SVGA_INDEX_PORT:
1544 pThis->svga.u32IndexReg = u32;
1545 break;
1546
1547 case SVGA_VALUE_PORT:
1548 return vmsvgaWritePort(pThis, u32);
1549
1550 case SVGA_BIOS_PORT:
1551 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1552 break;
1553
1554 case SVGA_IRQSTATUS_PORT:
1555 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1556 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1557 /* Clear the irq in case all events have been cleared. */
1558 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1559 {
1560 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1561 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1562 }
1563 break;
1564 }
1565 return rc;
1566}
1567
1568#ifdef DEBUG_FIFO_ACCESS
1569
1570# ifdef IN_RING3
1571/**
1572 * Handle LFB access.
1573 * @returns VBox status code.
1574 * @param pVM VM handle.
1575 * @param pThis VGA device instance data.
1576 * @param GCPhys The access physical address.
1577 * @param fWriteAccess Read or write access
1578 */
1579static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1580{
1581 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1582 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1583
1584 switch (GCPhysOffset >> 2)
1585 {
1586 case SVGA_FIFO_MIN:
1587 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1588 break;
1589 case SVGA_FIFO_MAX:
1590 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1591 break;
1592 case SVGA_FIFO_NEXT_CMD:
1593 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1594 break;
1595 case SVGA_FIFO_STOP:
1596 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1597 break;
1598 case SVGA_FIFO_CAPABILITIES:
1599 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1600 break;
1601 case SVGA_FIFO_FLAGS:
1602 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1603 break;
1604 case SVGA_FIFO_FENCE:
1605 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1606 break;
1607 case SVGA_FIFO_3D_HWVERSION:
1608 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1609 break;
1610 case SVGA_FIFO_PITCHLOCK:
1611 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1612 break;
1613 case SVGA_FIFO_CURSOR_ON:
1614 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1615 break;
1616 case SVGA_FIFO_CURSOR_X:
1617 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1618 break;
1619 case SVGA_FIFO_CURSOR_Y:
1620 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1621 break;
1622 case SVGA_FIFO_CURSOR_COUNT:
1623 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1624 break;
1625 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1626 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1627 break;
1628 case SVGA_FIFO_RESERVED:
1629 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1630 break;
1631 case SVGA_FIFO_CURSOR_SCREEN_ID:
1632 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1633 break;
1634 case SVGA_FIFO_DEAD:
1635 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1636 break;
1637 case SVGA_FIFO_3D_HWVERSION_REVISED:
1638 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1639 break;
1640 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1641 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1642 break;
1643 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1644 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1645 break;
1646 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1647 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1648 break;
1649 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1650 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1651 break;
1652 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1653 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1654 break;
1655 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1656 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1657 break;
1658 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1659 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1660 break;
1661 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1662 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1663 break;
1664 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1665 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1666 break;
1667 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1668 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1669 break;
1670 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1671 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1672 break;
1673 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1674 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1675 break;
1676 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1677 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1678 break;
1679 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1680 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1681 break;
1682 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1683 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1684 break;
1685 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1686 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1687 break;
1688 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1689 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1690 break;
1691 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1692 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1693 break;
1694 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1695 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1696 break;
1697 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1698 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1699 break;
1700 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1701 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1702 break;
1703 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1704 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1705 break;
1706 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1707 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1708 break;
1709 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1710 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1711 break;
1712 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1713 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1714 break;
1715 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1716 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1717 break;
1718 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1719 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1720 break;
1721 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1722 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1723 break;
1724 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1725 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1726 break;
1727 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1728 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1729 break;
1730 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1731 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1732 break;
1733 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1734 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1735 break;
1736 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1737 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1738 break;
1739 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1740 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1741 break;
1742 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1743 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1744 break;
1745 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1746 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1747 break;
1748 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1749 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1750 break;
1751 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1752 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1753 break;
1754 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1755 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1756 break;
1757 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1758 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1759 break;
1760 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1761 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1762 break;
1763 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1764 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1765 break;
1766 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1767 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1768 break;
1769 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1770 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1771 break;
1772 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1773 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1774 break;
1775 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1776 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1777 break;
1778 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1779 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1780 break;
1781 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1782 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1783 break;
1784 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1785 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1786 break;
1787 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1788 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1789 break;
1790 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1791 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1792 break;
1793 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1794 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1795 break;
1796 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1797 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1798 break;
1799 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1800 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1801 break;
1802 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1803 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1804 break;
1805 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1806 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1807 break;
1808 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1809 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1810 break;
1811 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1812 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1813 break;
1814 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1815 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1816 break;
1817 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1818 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1819 break;
1820 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1821 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1822 break;
1823 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1824 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1825 break;
1826 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1827 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1828 break;
1829 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1830 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1831 break;
1832 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1833 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1834 break;
1835 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1836 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1837 break;
1838 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1839 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1840 break;
1841 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1842 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1843 break;
1844 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1845 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1846 break;
1847 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1848 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1849 break;
1850 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1851 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1852 break;
1853 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1854 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1855 break;
1856 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1857 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1858 break;
1859 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1860 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1861 break;
1862 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1863 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1864 break;
1865 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1866 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1867 break;
1868 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1869 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1870 break;
1871 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1872 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1873 break;
1874 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1875 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1876 break;
1877 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1878 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1879 break;
1880 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1881 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1882 break;
1883 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1884 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1885 break;
1886 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1887 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1888 break;
1889 case SVGA_FIFO_3D_CAPS_LAST:
1890 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1891 break;
1892 case SVGA_FIFO_GUEST_3D_HWVERSION:
1893 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1894 break;
1895 case SVGA_FIFO_FENCE_GOAL:
1896 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1897 break;
1898 case SVGA_FIFO_BUSY:
1899 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1900 break;
1901 default:
1902 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1903 break;
1904 }
1905
1906 return VINF_EM_RAW_EMULATE_INSTR;
1907}
1908
1909/**
1910 * HC access handler for the FIFO.
1911 *
1912 * @returns VINF_SUCCESS if the handler have carried out the operation.
1913 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1914 * @param pVM VM Handle.
1915 * @param pVCpu The cross context CPU structure for the calling EMT.
1916 * @param GCPhys The physical address the guest is writing to.
1917 * @param pvPhys The HC mapping of that address.
1918 * @param pvBuf What the guest is reading/writing.
1919 * @param cbBuf How much it's reading/writing.
1920 * @param enmAccessType The access type.
1921 * @param enmOrigin Who is making the access.
1922 * @param pvUser User argument.
1923 */
1924static DECLCALLBACK(VBOXSTRICTRC)
1925vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1926 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1927{
1928 PVGASTATE pThis = (PVGASTATE)pvUser;
1929 int rc;
1930 Assert(pThis);
1931 Assert(GCPhys >= pThis->GCPhysVRAM);
1932 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1933
1934 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1935 if (RT_SUCCESS(rc))
1936 return VINF_PGM_HANDLER_DO_DEFAULT;
1937 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1938 return rc;
1939}
1940
1941# endif /* IN_RING3 */
1942#endif /* DEBUG_FIFO_ACCESS */
1943
1944#ifdef DEBUG_GMR_ACCESS
1945/**
1946 * HC access handler for the FIFO.
1947 *
1948 * @returns VINF_SUCCESS if the handler have carried out the operation.
1949 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1950 * @param pVM VM Handle.
1951 * @param pVCpu The cross context CPU structure for the calling EMT.
1952 * @param GCPhys The physical address the guest is writing to.
1953 * @param pvPhys The HC mapping of that address.
1954 * @param pvBuf What the guest is reading/writing.
1955 * @param cbBuf How much it's reading/writing.
1956 * @param enmAccessType The access type.
1957 * @param enmOrigin Who is making the access.
1958 * @param pvUser User argument.
1959 */
1960static DECLCALLBACK(VBOXSTRICTRC)
1961vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1962 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1963{
1964 PVGASTATE pThis = (PVGASTATE)pvUser;
1965 Assert(pThis);
1966 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1967 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1968
1969 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1970
1971 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1972 {
1973 PGMR pGMR = &pSVGAState->aGMR[i];
1974
1975 if (pGMR->numDescriptors)
1976 {
1977 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1978 {
1979 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1980 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1981 {
1982 /*
1983 * Turn off the write handler for this particular page and make it R/W.
1984 * Then return telling the caller to restart the guest instruction.
1985 */
1986 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1987 goto end;
1988 }
1989 }
1990 }
1991 }
1992end:
1993 return VINF_PGM_HANDLER_DO_DEFAULT;
1994}
1995
1996# ifdef IN_RING3
1997
1998/* Callback handler for VMR3ReqCallWait */
1999static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2000{
2001 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2002 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2003 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2004 int rc;
2005
2006 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2007 {
2008 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2009 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2010 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2011 AssertRC(rc);
2012 }
2013 return VINF_SUCCESS;
2014}
2015
2016/* Callback handler for VMR3ReqCallWait */
2017static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2018{
2019 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2020 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2021 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2022
2023 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2024 {
2025 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2026 AssertRC(rc);
2027 }
2028 return VINF_SUCCESS;
2029}
2030
2031/* Callback handler for VMR3ReqCallWait */
2032static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2033{
2034 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2035
2036 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2037 {
2038 PGMR pGMR = &pSVGAState->aGMR[i];
2039
2040 if (pGMR->numDescriptors)
2041 {
2042 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2043 {
2044 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2045 AssertRC(rc);
2046 }
2047 }
2048 }
2049 return VINF_SUCCESS;
2050}
2051
2052# endif /* IN_RING3 */
2053#endif /* DEBUG_GMR_ACCESS */
2054
2055/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2056
2057#ifdef IN_RING3
2058
2059/**
2060 * Worker for vmsvgaR3FifoThread that handles an external command.
2061 *
2062 * @param pThis VGA device instance data.
2063 */
2064static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2065{
2066 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2067 switch (pThis->svga.u8FIFOExtCommand)
2068 {
2069 case VMSVGA_FIFO_EXTCMD_RESET:
2070 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2071 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2072# ifdef VBOX_WITH_VMSVGA3D
2073 if (pThis->svga.f3DEnabled)
2074 {
2075 /* The 3d subsystem must be reset from the fifo thread. */
2076 vmsvga3dReset(pThis);
2077 }
2078# endif
2079 break;
2080
2081 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2082 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2083 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2084# ifdef VBOX_WITH_VMSVGA3D
2085 if (pThis->svga.f3DEnabled)
2086 {
2087 /* The 3d subsystem must be shut down from the fifo thread. */
2088 vmsvga3dTerminate(pThis);
2089 }
2090# endif
2091 break;
2092
2093 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2094 {
2095 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2096# ifdef VBOX_WITH_VMSVGA3D
2097 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2098 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2099 vmsvga3dSaveExec(pThis, pSSM);
2100# endif
2101 break;
2102 }
2103
2104 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2105 {
2106 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2107# ifdef VBOX_WITH_VMSVGA3D
2108 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2109 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2110 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2111# endif
2112 break;
2113 }
2114
2115 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2116 {
2117# ifdef VBOX_WITH_VMSVGA3D
2118 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2119 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2120 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2121# endif
2122 break;
2123 }
2124
2125
2126 default:
2127 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2128 break;
2129 }
2130
2131 /*
2132 * Signal the end of the external command.
2133 */
2134 pThis->svga.pvFIFOExtCmdParam = NULL;
2135 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2136 ASMMemoryFence(); /* paranoia^2 */
2137 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2138 AssertLogRelRC(rc);
2139}
2140
2141/**
2142 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2143 * doing a job on the FIFO thread (even when it's officially suspended).
2144 *
2145 * @returns VBox status code (fully asserted).
2146 * @param pThis VGA device instance data.
2147 * @param uExtCmd The command to execute on the FIFO thread.
2148 * @param pvParam Pointer to command parameters.
2149 * @param cMsWait The time to wait for the command, given in
2150 * milliseconds.
2151 */
2152static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2153{
2154 Assert(cMsWait >= RT_MS_1SEC * 5);
2155 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2156 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2157
2158 int rc;
2159 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2160 PDMTHREADSTATE enmState = pThread->enmState;
2161 if (enmState == PDMTHREADSTATE_SUSPENDED)
2162 {
2163 /*
2164 * The thread is suspended, we have to temporarily wake it up so it can
2165 * perform the task.
2166 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2167 */
2168 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2169 /* Post the request. */
2170 pThis->svga.fFifoExtCommandWakeup = true;
2171 pThis->svga.pvFIFOExtCmdParam = pvParam;
2172 pThis->svga.u8FIFOExtCommand = uExtCmd;
2173 ASMMemoryFence(); /* paranoia^3 */
2174
2175 /* Resume the thread. */
2176 rc = PDMR3ThreadResume(pThread);
2177 AssertLogRelRC(rc);
2178 if (RT_SUCCESS(rc))
2179 {
2180 /* Wait. Take care in case the semaphore was already posted (same as below). */
2181 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2182 if ( rc == VINF_SUCCESS
2183 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2184 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2185 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2186 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2187
2188 /* suspend the thread */
2189 pThis->svga.fFifoExtCommandWakeup = false;
2190 int rc2 = PDMR3ThreadSuspend(pThread);
2191 AssertLogRelRC(rc2);
2192 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2193 rc = rc2;
2194 }
2195 pThis->svga.fFifoExtCommandWakeup = false;
2196 pThis->svga.pvFIFOExtCmdParam = NULL;
2197 }
2198 else if (enmState == PDMTHREADSTATE_RUNNING)
2199 {
2200 /*
2201 * The thread is running, should only happen during reset and vmsvga3dsfc.
2202 * We ASSUME not racing code here, both wrt thread state and ext commands.
2203 */
2204 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2205 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2206
2207 /* Post the request. */
2208 pThis->svga.pvFIFOExtCmdParam = pvParam;
2209 pThis->svga.u8FIFOExtCommand = uExtCmd;
2210 ASMMemoryFence(); /* paranoia^2 */
2211 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2212 AssertLogRelRC(rc);
2213
2214 /* Wait. Take care in case the semaphore was already posted (same as above). */
2215 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2216 if ( rc == VINF_SUCCESS
2217 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2218 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2219 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2220 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2221
2222 pThis->svga.pvFIFOExtCmdParam = NULL;
2223 }
2224 else
2225 {
2226 /*
2227 * Something is wrong with the thread!
2228 */
2229 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2230 rc = VERR_INVALID_STATE;
2231 }
2232 return rc;
2233}
2234
2235
2236/**
2237 * Marks the FIFO non-busy, notifying any waiting EMTs.
2238 *
2239 * @param pThis The VGA state.
2240 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2241 * @param offFifoMin The start byte offset of the command FIFO.
2242 */
2243static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2244{
2245 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2246 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2247 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2248
2249 /* Wake up any waiting EMTs. */
2250 if (pSVGAState->cBusyDelayedEmts > 0)
2251 {
2252#ifdef VMSVGA_USE_EMT_HALT_CODE
2253 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2254 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2255 if (idCpu != NIL_VMCPUID)
2256 {
2257 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2258 while (idCpu-- > 0)
2259 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2260 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2261 }
2262#else
2263 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2264 AssertRC(rc2);
2265#endif
2266 }
2267}
2268
2269/**
2270 * Reads (more) payload into the command buffer.
2271 *
2272 * @returns pbBounceBuf on success
2273 * @retval (void *)1 if the thread was requested to stop.
2274 * @retval NULL on FIFO error.
2275 *
2276 * @param cbPayloadReq The number of bytes of payload requested.
2277 * @param pFIFO The FIFO.
2278 * @param offCurrentCmd The FIFO byte offset of the current command.
2279 * @param offFifoMin The start byte offset of the command FIFO.
2280 * @param offFifoMax The end byte offset of the command FIFO.
2281 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2282 * always sufficient size.
2283 * @param pcbAlreadyRead How much payload we've already read into the bounce
2284 * buffer. (We will NEVER re-read anything.)
2285 * @param pThread The calling PDM thread handle.
2286 * @param pThis The VGA state.
2287 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2288 * statistics collection.
2289 */
2290static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2291 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2292 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2293 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2294{
2295 Assert(pbBounceBuf);
2296 Assert(pcbAlreadyRead);
2297 Assert(offFifoMin < offFifoMax);
2298 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2299 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2300
2301 /*
2302 * Check if the requested payload size has already been satisfied .
2303 * .
2304 * When called to read more, the caller is responsible for making sure the .
2305 * new command size (cbRequsted) never is smaller than what has already .
2306 * been read.
2307 */
2308 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2309 if (cbPayloadReq <= cbAlreadyRead)
2310 {
2311 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2312 return pbBounceBuf;
2313 }
2314
2315 /*
2316 * Commands bigger than the fifo buffer are invalid.
2317 */
2318 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2319 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2320 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2321 NULL);
2322
2323 /*
2324 * Move offCurrentCmd past the command dword.
2325 */
2326 offCurrentCmd += sizeof(uint32_t);
2327 if (offCurrentCmd >= offFifoMax)
2328 offCurrentCmd = offFifoMin;
2329
2330 /*
2331 * Do we have sufficient payload data available already?
2332 */
2333 uint32_t cbAfter, cbBefore;
2334 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2335 if (offNextCmd > offCurrentCmd)
2336 {
2337 if (RT_LIKELY(offNextCmd < offFifoMax))
2338 cbAfter = offNextCmd - offCurrentCmd;
2339 else
2340 {
2341 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2342 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2343 offNextCmd, offFifoMin, offFifoMax));
2344 cbAfter = offFifoMax - offCurrentCmd;
2345 }
2346 cbBefore = 0;
2347 }
2348 else
2349 {
2350 cbAfter = offFifoMax - offCurrentCmd;
2351 if (offNextCmd >= offFifoMin)
2352 cbBefore = offNextCmd - offFifoMin;
2353 else
2354 {
2355 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2356 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2357 offNextCmd, offFifoMin, offFifoMax));
2358 cbBefore = 0;
2359 }
2360 }
2361 if (cbAfter + cbBefore < cbPayloadReq)
2362 {
2363 /*
2364 * Insufficient, must wait for it to arrive.
2365 */
2366 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2367 for (uint32_t i = 0;; i++)
2368 {
2369 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2370 {
2371 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2372 return (void *)(uintptr_t)1;
2373 }
2374 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2375 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2376
2377 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2378
2379 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2380 if (offNextCmd > offCurrentCmd)
2381 {
2382 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2383 cbBefore = 0;
2384 }
2385 else
2386 {
2387 cbAfter = offFifoMax - offCurrentCmd;
2388 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2389 }
2390
2391 if (cbAfter + cbBefore >= cbPayloadReq)
2392 break;
2393 }
2394 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2395 }
2396
2397 /*
2398 * Copy out the memory and update what pcbAlreadyRead points to.
2399 */
2400 if (cbAfter >= cbPayloadReq)
2401 memcpy(pbBounceBuf + cbAlreadyRead,
2402 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2403 cbPayloadReq - cbAlreadyRead);
2404 else
2405 {
2406 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2407 if (cbAlreadyRead < cbAfter)
2408 {
2409 memcpy(pbBounceBuf + cbAlreadyRead,
2410 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2411 cbAfter - cbAlreadyRead);
2412 cbAlreadyRead = cbAfter;
2413 }
2414 memcpy(pbBounceBuf + cbAlreadyRead,
2415 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2416 cbPayloadReq - cbAlreadyRead);
2417 }
2418 *pcbAlreadyRead = cbPayloadReq;
2419 return pbBounceBuf;
2420}
2421
2422/* The async FIFO handling thread. */
2423static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2424{
2425 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2426 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2427 int rc;
2428
2429 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2430 return VINF_SUCCESS;
2431
2432 /*
2433 * Special mode where we only execute an external command and the go back
2434 * to being suspended. Currently, all ext cmds ends up here, with the reset
2435 * one also being eligble for runtime execution further down as well.
2436 */
2437 if (pThis->svga.fFifoExtCommandWakeup)
2438 {
2439 vmsvgaR3FifoHandleExtCmd(pThis);
2440 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2441 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2442 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2443 else
2444 vmsvgaR3FifoHandleExtCmd(pThis);
2445 return VINF_SUCCESS;
2446 }
2447
2448
2449 /*
2450 * Signal the semaphore to make sure we don't wait for 250 after a
2451 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2452 */
2453 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2454
2455 /*
2456 * Allocate a bounce buffer for command we get from the FIFO.
2457 * (All code must return via the end of the function to free this buffer.)
2458 */
2459 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2460 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2461
2462 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2463 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2464 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2465 {
2466# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2467 /*
2468 * Should service the run loop every so often.
2469 */
2470 if (pThis->svga.f3DEnabled)
2471 vmsvga3dCocoaServiceRunLoop();
2472# endif
2473
2474 /*
2475 * Wait for at most 250 ms to start polling.
2476 */
2477 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2478 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2479 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2480 {
2481 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2482 break;
2483 }
2484 if (rc == VERR_TIMEOUT)
2485 {
2486 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2487 continue;
2488 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2489
2490 Log(("vmsvgaFIFOLoop: timeout\n"));
2491 }
2492 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2493 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2494
2495 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2496 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2497 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2498
2499 /*
2500 * Handle external commands (currently only reset).
2501 */
2502 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2503 {
2504 vmsvgaR3FifoHandleExtCmd(pThis);
2505 continue;
2506 }
2507
2508 /*
2509 * The device must be enabled and configured.
2510 */
2511 if ( !pThis->svga.fEnabled
2512 || !pThis->svga.fConfigured)
2513 {
2514 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2515 continue;
2516 }
2517
2518 /*
2519 * Get and check the min/max values. We ASSUME that they will remain
2520 * unchanged while we process requests. A further ASSUMPTION is that
2521 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2522 * we don't read it back while in the loop.
2523 */
2524 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2525 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2526 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2527 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2528 || offFifoMax <= offFifoMin
2529 || offFifoMax > VMSVGA_FIFO_SIZE
2530 || (offFifoMax & 3) != 0
2531 || (offFifoMin & 3) != 0
2532 || offCurrentCmd < offFifoMin
2533 || offCurrentCmd > offFifoMax))
2534 {
2535 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2536 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2537 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2538 continue;
2539 }
2540 if (RT_UNLIKELY(offCurrentCmd & 3))
2541 {
2542 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2543 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2544 offCurrentCmd = ~UINT32_C(3);
2545 }
2546
2547/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
2548 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2549 *
2550 * Will break out of the switch on failure.
2551 * Will restart and quit the loop if the thread was requested to stop.
2552 *
2553 * @param a_PtrVar Request variable pointer.
2554 * @param a_Type Request typedef (not pointer) for casting.
2555 * @param a_cbPayloadReq How much payload to fetch.
2556 * @remarks Accesses a bunch of variables in the current scope!
2557 */
2558# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2559 if (1) { \
2560 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2561 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2562 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2563 } else do {} while (0)
2564/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
2565 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2566 * buffer after figuring out the actual command size.
2567 *
2568 * Will break out of the switch on failure.
2569 *
2570 * @param a_PtrVar Request variable pointer.
2571 * @param a_Type Request typedef (not pointer) for casting.
2572 * @param a_cbPayloadReq How much payload to fetch.
2573 * @remarks Accesses a bunch of variables in the current scope!
2574 */
2575# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2576 if (1) { \
2577 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2578 } else do {} while (0)
2579
2580 /*
2581 * Mark the FIFO as busy.
2582 */
2583 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2584 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2585 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2586
2587 /*
2588 * Execute all queued FIFO commands.
2589 * Quit if pending external command or changes in the thread state.
2590 */
2591 bool fDone = false;
2592 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2593 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2594 {
2595 uint32_t cbPayload = 0;
2596 uint32_t u32IrqStatus = 0;
2597 bool fTriggerIrq = false;
2598
2599 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2600
2601 /* First check any pending actions. */
2602 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2603# ifdef VBOX_WITH_VMSVGA3D
2604 vmsvga3dChangeMode(pThis);
2605# else
2606 {/*nothing*/}
2607# endif
2608 /* Check for pending external commands (reset). */
2609 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2610 break;
2611
2612 /*
2613 * Process the command.
2614 */
2615 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2616 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2617 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2618 switch (enmCmdId)
2619 {
2620 case SVGA_CMD_INVALID_CMD:
2621 /* Nothing to do. */
2622 break;
2623
2624 case SVGA_CMD_FENCE:
2625 {
2626 SVGAFifoCmdFence *pCmdFence;
2627 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2628 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2629 {
2630 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2631 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2632
2633 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2634 {
2635 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2636 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2637 }
2638 else
2639 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2640 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2641 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2642 {
2643 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2644 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2645 }
2646 }
2647 else
2648 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2649 break;
2650 }
2651 case SVGA_CMD_UPDATE:
2652 case SVGA_CMD_UPDATE_VERBOSE:
2653 {
2654 SVGAFifoCmdUpdate *pUpdate;
2655 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2656 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2657 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2658 break;
2659 }
2660
2661 case SVGA_CMD_DEFINE_CURSOR:
2662 {
2663 /* Followed by bitmap data. */
2664 SVGAFifoCmdDefineCursor *pCursor;
2665 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2666 AssertFailed(); /** @todo implement when necessary. */
2667 break;
2668 }
2669
2670 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2671 {
2672 /* Followed by bitmap data. */
2673 uint32_t cbCursorShape, cbAndMask;
2674 uint8_t *pCursorCopy;
2675 uint32_t cbCmd;
2676
2677 SVGAFifoCmdDefineAlphaCursor *pCursor;
2678 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2679
2680 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2681
2682 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2683 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2684
2685 /* Refetch the bitmap data as well. */
2686 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2687 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2688 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2689
2690 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2691 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2692 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2693 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2694
2695 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2696 AssertBreak(pCursorCopy);
2697
2698 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2699
2700 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2701 memset(pCursorCopy, 0xff, cbAndMask);
2702 /* Colour data */
2703 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2704
2705 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2706 true,
2707 true,
2708 pCursor->hotspotX,
2709 pCursor->hotspotY,
2710 pCursor->width,
2711 pCursor->height,
2712 pCursorCopy);
2713 AssertRC(rc);
2714
2715 if (pSVGAState->Cursor.fActive)
2716 RTMemFree(pSVGAState->Cursor.pData);
2717
2718 pSVGAState->Cursor.fActive = true;
2719 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2720 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2721 pSVGAState->Cursor.width = pCursor->width;
2722 pSVGAState->Cursor.height = pCursor->height;
2723 pSVGAState->Cursor.cbData = cbCursorShape;
2724 pSVGAState->Cursor.pData = pCursorCopy;
2725 break;
2726 }
2727
2728 case SVGA_CMD_ESCAPE:
2729 {
2730 /* Followed by nsize bytes of data. */
2731 SVGAFifoCmdEscape *pEscape;
2732 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2733
2734 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2735 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2736 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2737 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2738
2739 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2740 {
2741 AssertBreak(pEscape->size >= sizeof(uint32_t));
2742 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2743 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2744
2745 switch (cmd)
2746 {
2747 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2748 {
2749 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2750 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2751 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2752
2753 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2754 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2755 {
2756 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2757 }
2758 break;
2759 }
2760
2761 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2762 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2763 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2764 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2765 break;
2766 }
2767 }
2768 else
2769 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2770
2771 break;
2772 }
2773# ifdef VBOX_WITH_VMSVGA3D
2774 case SVGA_CMD_DEFINE_GMR2:
2775 {
2776 SVGAFifoCmdDefineGMR2 *pCmd;
2777 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2778 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2779
2780 /* Validate current GMR id. */
2781 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2782 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2783
2784 if (!pCmd->numPages)
2785 {
2786 vmsvgaGMRFree(pThis, pCmd->gmrId);
2787 }
2788 else
2789 {
2790 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2791 pGMR->cMaxPages = pCmd->numPages;
2792 }
2793 /* everything done in remap */
2794 break;
2795 }
2796
2797 case SVGA_CMD_REMAP_GMR2:
2798 {
2799 /* Followed by page descriptors or guest ptr. */
2800 SVGAFifoCmdRemapGMR2 *pCmd;
2801 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2802 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2803 uint32_t cbCmd;
2804 uint64_t *paNewPage64 = NULL;
2805
2806 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2807 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2808
2809 /* Calculate the size of what comes after next and fetch it. */
2810 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2811 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2812 cbCmd += sizeof(SVGAGuestPtr);
2813 else
2814 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2815 {
2816 cbCmd += cbPageDesc;
2817 pCmd->numPages = 1;
2818 }
2819 else
2820 {
2821 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2822 cbCmd += cbPageDesc * pCmd->numPages;
2823 }
2824 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2825
2826 /* Validate current GMR id. */
2827 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2828 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2829 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2830 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2831
2832 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2833 if (pGMR->paDesc)
2834 {
2835 uint32_t idxPage = 0;
2836 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2837 AssertBreak(paNewPage64);
2838
2839 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2840 {
2841 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2842 {
2843 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2844 }
2845 }
2846 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2847 }
2848
2849 /* Free the old GMR if present. */
2850 if (pGMR->paDesc)
2851 RTMemFree(pGMR->paDesc);
2852
2853 /* Allocate the maximum amount possible (everything non-continuous) */
2854 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2855 AssertBreak(pGMR->paDesc);
2856
2857 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2858 {
2859 /** @todo */
2860 AssertFailed();
2861 }
2862 else
2863 {
2864 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2865 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2866 uint32_t iDescriptor = 0;
2867 RTGCPHYS GCPhys;
2868 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2869 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2870
2871 if (paNewPage64)
2872 {
2873 /* Overwrite the old page array with the new page values. */
2874 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2875 {
2876 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2877 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2878 else
2879 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2880 }
2881 /* Use the updated page array instead of the command data. */
2882 fGCPhys64 = true;
2883 pPage64 = paNewPage64;
2884 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2885 }
2886
2887 if (fGCPhys64)
2888 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2889 else
2890 GCPhys = pPage32[0] << PAGE_SHIFT;
2891
2892 pGMR->paDesc[0].GCPhys = GCPhys;
2893 pGMR->paDesc[0].numPages = 1;
2894 pGMR->cbTotal = PAGE_SIZE;
2895
2896 for (uint32_t i = 1; i < pCmd->numPages; i++)
2897 {
2898 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2899 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2900 else
2901 GCPhys = pPage32[i] << PAGE_SHIFT;
2902
2903 /* Continuous physical memory? */
2904 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2905 {
2906 Assert(pGMR->paDesc[iDescriptor].numPages);
2907 pGMR->paDesc[iDescriptor].numPages++;
2908 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2909 }
2910 else
2911 {
2912 iDescriptor++;
2913 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2914 pGMR->paDesc[iDescriptor].numPages = 1;
2915 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2916 }
2917
2918 pGMR->cbTotal += PAGE_SIZE;
2919 }
2920 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2921 pGMR->numDescriptors = iDescriptor + 1;
2922 }
2923
2924 if (paNewPage64)
2925 RTMemFree(paNewPage64);
2926
2927# ifdef DEBUG_GMR_ACCESS
2928 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2929# endif
2930 break;
2931 }
2932# endif // VBOX_WITH_VMSVGA3D
2933 case SVGA_CMD_DEFINE_SCREEN:
2934 {
2935 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2936 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2937 SVGAFifoCmdDefineScreen *pCmd;
2938 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2939 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2940 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2941
2942 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2943 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2944 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2945 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2946 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2947 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2948 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2949 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2950 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2951 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2952 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2953
2954 /** @todo multi monitor support and screen object capabilities. */
2955 pThis->svga.uWidth = pCmd->screen.size.width;
2956 pThis->svga.uHeight = pCmd->screen.size.height;
2957 vmsvgaChangeMode(pThis);
2958 break;
2959 }
2960
2961 case SVGA_CMD_DESTROY_SCREEN:
2962 {
2963 SVGAFifoCmdDestroyScreen *pCmd;
2964 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2965
2966 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2967 break;
2968 }
2969# ifdef VBOX_WITH_VMSVGA3D
2970 case SVGA_CMD_DEFINE_GMRFB:
2971 {
2972 SVGAFifoCmdDefineGMRFB *pCmd;
2973 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2974
2975 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2976 pSVGAState->GMRFB.ptr = pCmd->ptr;
2977 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2978 pSVGAState->GMRFB.format = pCmd->format;
2979 break;
2980 }
2981
2982 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2983 {
2984 uint32_t width, height;
2985 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2986 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2987
2988 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2989
2990 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2991 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2992 AssertBreak(pCmd->destScreenId == 0);
2993
2994 if (pCmd->destRect.left < 0)
2995 pCmd->destRect.left = 0;
2996 if (pCmd->destRect.top < 0)
2997 pCmd->destRect.top = 0;
2998 if (pCmd->destRect.right < 0)
2999 pCmd->destRect.right = 0;
3000 if (pCmd->destRect.bottom < 0)
3001 pCmd->destRect.bottom = 0;
3002
3003 width = pCmd->destRect.right - pCmd->destRect.left;
3004 height = pCmd->destRect.bottom - pCmd->destRect.top;
3005
3006 if ( width == 0
3007 || height == 0)
3008 break; /* Nothing to do. */
3009
3010 /* Clip to screen dimensions. */
3011 if (width > pThis->svga.uWidth)
3012 width = pThis->svga.uWidth;
3013 if (height > pThis->svga.uHeight)
3014 height = pThis->svga.uHeight;
3015
3016 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3017 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3018 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3019
3020 AssertBreak(offsetDest < pThis->vram_size);
3021
3022 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3023 AssertRC(rc);
3024 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3025 break;
3026 }
3027
3028 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3029 {
3030 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3031 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3032
3033 /* Note! This can fetch 3d render results as well!! */
3034 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3035 AssertFailed();
3036 break;
3037 }
3038# endif // VBOX_WITH_VMSVGA3D
3039 case SVGA_CMD_ANNOTATION_FILL:
3040 {
3041 SVGAFifoCmdAnnotationFill *pCmd;
3042 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3043
3044 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3045 pSVGAState->colorAnnotation = pCmd->color;
3046 break;
3047 }
3048
3049 case SVGA_CMD_ANNOTATION_COPY:
3050 {
3051 SVGAFifoCmdAnnotationCopy *pCmd;
3052 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3053
3054 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3055 AssertFailed();
3056 break;
3057 }
3058
3059 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3060
3061 default:
3062# ifdef VBOX_WITH_VMSVGA3D
3063 if ( enmCmdId >= SVGA_3D_CMD_BASE
3064 && enmCmdId < SVGA_3D_CMD_MAX)
3065 {
3066 /* All 3d commands start with a common header, which defines the size of the command. */
3067 SVGA3dCmdHeader *pHdr;
3068 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3069 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3070 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3071 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3072
3073/**
3074 * Check that the 3D command has at least a_cbMin of payload bytes after the
3075 * header. Will break out of the switch if it doesn't.
3076 */
3077# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3078 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3079 switch ((int)enmCmdId)
3080 {
3081 case SVGA_3D_CMD_SURFACE_DEFINE:
3082 {
3083 uint32_t cMipLevels;
3084 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3085 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3086
3087 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3088 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3089 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3090# ifdef DEBUG_GMR_ACCESS
3091 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3092# endif
3093 break;
3094 }
3095
3096 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3097 {
3098 uint32_t cMipLevels;
3099 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3100 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3101
3102 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3103 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3104 pCmd->multisampleCount, pCmd->autogenFilter,
3105 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3106 break;
3107 }
3108
3109 case SVGA_3D_CMD_SURFACE_DESTROY:
3110 {
3111 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3112 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3113 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3114 break;
3115 }
3116
3117 case SVGA_3D_CMD_SURFACE_COPY:
3118 {
3119 uint32_t cCopyBoxes;
3120 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3122
3123 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3124 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3125 break;
3126 }
3127
3128 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3129 {
3130 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3131 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3132
3133 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3134 break;
3135 }
3136
3137 case SVGA_3D_CMD_SURFACE_DMA:
3138 {
3139 uint32_t cCopyBoxes;
3140 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3141 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3142
3143 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3144 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3145 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3146 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3147 break;
3148 }
3149
3150 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3151 {
3152 uint32_t cRects;
3153 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3154 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3155
3156 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3157 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3158 break;
3159 }
3160
3161 case SVGA_3D_CMD_CONTEXT_DEFINE:
3162 {
3163 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3164 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3165
3166 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3167 break;
3168 }
3169
3170 case SVGA_3D_CMD_CONTEXT_DESTROY:
3171 {
3172 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3173 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3174
3175 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3176 break;
3177 }
3178
3179 case SVGA_3D_CMD_SETTRANSFORM:
3180 {
3181 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3183
3184 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3185 break;
3186 }
3187
3188 case SVGA_3D_CMD_SETZRANGE:
3189 {
3190 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3191 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3192
3193 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3194 break;
3195 }
3196
3197 case SVGA_3D_CMD_SETRENDERSTATE:
3198 {
3199 uint32_t cRenderStates;
3200 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3201 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3202
3203 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3204 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3205 break;
3206 }
3207
3208 case SVGA_3D_CMD_SETRENDERTARGET:
3209 {
3210 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3211 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3212
3213 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3214 break;
3215 }
3216
3217 case SVGA_3D_CMD_SETTEXTURESTATE:
3218 {
3219 uint32_t cTextureStates;
3220 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3221 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3222
3223 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3224 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3225 break;
3226 }
3227
3228 case SVGA_3D_CMD_SETMATERIAL:
3229 {
3230 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3231 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3232
3233 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3234 break;
3235 }
3236
3237 case SVGA_3D_CMD_SETLIGHTDATA:
3238 {
3239 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3240 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3241
3242 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3243 break;
3244 }
3245
3246 case SVGA_3D_CMD_SETLIGHTENABLED:
3247 {
3248 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3249 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3250
3251 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3252 break;
3253 }
3254
3255 case SVGA_3D_CMD_SETVIEWPORT:
3256 {
3257 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3258 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3259
3260 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3261 break;
3262 }
3263
3264 case SVGA_3D_CMD_SETCLIPPLANE:
3265 {
3266 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3267 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3268
3269 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3270 break;
3271 }
3272
3273 case SVGA_3D_CMD_CLEAR:
3274 {
3275 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3276 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3277 uint32_t cRects;
3278
3279 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3280 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3281 break;
3282 }
3283
3284 case SVGA_3D_CMD_PRESENT:
3285 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3286 {
3287 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3288 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3289 uint32_t cRects;
3290
3291 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3292
3293 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3294 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3295 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3296 break;
3297 }
3298
3299 case SVGA_3D_CMD_SHADER_DEFINE:
3300 {
3301 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3302 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3303 uint32_t cbData;
3304
3305 cbData = (pHdr->size - sizeof(*pCmd));
3306 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3307 break;
3308 }
3309
3310 case SVGA_3D_CMD_SHADER_DESTROY:
3311 {
3312 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3313 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3314
3315 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3316 break;
3317 }
3318
3319 case SVGA_3D_CMD_SET_SHADER:
3320 {
3321 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3322 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3323
3324 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3325 break;
3326 }
3327
3328 case SVGA_3D_CMD_SET_SHADER_CONST:
3329 {
3330 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3331 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3332
3333 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3334 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3335 break;
3336 }
3337
3338 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3339 {
3340 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3341 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3342 uint32_t cVertexDivisor;
3343
3344 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3345 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3346 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3347 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3348
3349 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3350 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3351 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3352
3353 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3354 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3355 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3356 break;
3357 }
3358
3359 case SVGA_3D_CMD_SETSCISSORRECT:
3360 {
3361 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3363
3364 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3365 break;
3366 }
3367
3368 case SVGA_3D_CMD_BEGIN_QUERY:
3369 {
3370 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3371 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3372
3373 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3374 break;
3375 }
3376
3377 case SVGA_3D_CMD_END_QUERY:
3378 {
3379 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3380 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3381
3382 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3383 break;
3384 }
3385
3386 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3387 {
3388 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3389 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3390
3391 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3392 break;
3393 }
3394
3395 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3396 {
3397 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3399
3400 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3401 break;
3402 }
3403
3404 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3405 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3406 /* context id + surface id? */
3407 break;
3408
3409 default:
3410 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3411 AssertFailed();
3412 break;
3413 }
3414 }
3415 else
3416# endif // VBOX_WITH_VMSVGA3D
3417 {
3418 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3419 AssertFailed();
3420 }
3421 }
3422
3423 /* Go to the next slot */
3424 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3425 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3426 if (offCurrentCmd >= offFifoMax)
3427 {
3428 offCurrentCmd -= offFifoMax - offFifoMin;
3429 Assert(offCurrentCmd >= offFifoMin);
3430 Assert(offCurrentCmd < offFifoMax);
3431 }
3432 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3433 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3434
3435 /*
3436 * Raise IRQ if required. Must enter the critical section here
3437 * before making final decisions here, otherwise cubebench and
3438 * others may end up waiting forever.
3439 */
3440 if ( u32IrqStatus
3441 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3442 {
3443 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3444
3445 /* FIFO progress might trigger an interrupt. */
3446 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3447 {
3448 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3449 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3450 }
3451
3452 /* Unmasked IRQ pending? */
3453 if (pThis->svga.u32IrqMask & u32IrqStatus)
3454 {
3455 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3456 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3457 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3458 }
3459
3460 PDMCritSectLeave(&pThis->CritSect);
3461 }
3462 }
3463
3464 /* If really done, clear the busy flag. */
3465 if (fDone)
3466 {
3467 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3468 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3469 }
3470 }
3471
3472 /*
3473 * Free the bounce buffer. (There are no returns above!)
3474 */
3475 RTMemFree(pbBounceBuf);
3476
3477 return VINF_SUCCESS;
3478}
3479
3480/**
3481 * Free the specified GMR
3482 *
3483 * @param pThis VGA device instance data.
3484 * @param idGMR GMR id
3485 */
3486void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3487{
3488 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3489
3490 /* Free the old descriptor if present. */
3491 if (pSVGAState->aGMR[idGMR].numDescriptors)
3492 {
3493 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3494# ifdef DEBUG_GMR_ACCESS
3495 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3496# endif
3497
3498 Assert(pGMR->paDesc);
3499 RTMemFree(pGMR->paDesc);
3500 pGMR->paDesc = NULL;
3501 pGMR->numDescriptors = 0;
3502 pGMR->cbTotal = 0;
3503 pGMR->cMaxPages = 0;
3504 }
3505 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3506}
3507
3508/**
3509 * Copy from a GMR to host memory or vice versa
3510 *
3511 * @returns VBox status code.
3512 * @param pThis VGA device instance data.
3513 * @param enmTransferType Transfer type (read/write)
3514 * @param pbDst Host destination pointer
3515 * @param cbDestPitch Destination buffer pitch
3516 * @param src GMR description
3517 * @param offSrc Source buffer offset
3518 * @param cbSrcPitch Source buffer pitch
3519 * @param cbWidth Source width in bytes
3520 * @param cHeight Source height
3521 */
3522int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3523 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3524{
3525 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3526 PGMR pGMR;
3527 int rc;
3528 PVMSVGAGMRDESCRIPTOR pDesc;
3529 unsigned offDesc = 0;
3530
3531 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3532 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3533 Assert(cbWidth && cHeight);
3534
3535 /* Shortcut for the framebuffer. */
3536 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3537 {
3538 offSrc += src.offset;
3539 AssertMsgReturn(src.offset < pThis->vram_size,
3540 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3541 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3542 VERR_INVALID_PARAMETER);
3543 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3544 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3545 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3546 VERR_INVALID_PARAMETER);
3547
3548 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3549
3550 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3551 {
3552 /* switch src & dest */
3553 uint8_t *pTemp = pbDst;
3554 int32_t cbTempPitch = cbDestPitch;
3555
3556 pbDst = pSrc;
3557 pSrc = pTemp;
3558
3559 cbDestPitch = cbSrcPitch;
3560 cbSrcPitch = cbTempPitch;
3561 }
3562
3563 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3564 && cbWidth == (uint32_t)cbDestPitch
3565 && cbSrcPitch == cbDestPitch)
3566 {
3567 memcpy(pbDst, pSrc, cbWidth * cHeight);
3568 }
3569 else
3570 {
3571 for(uint32_t i = 0; i < cHeight; i++)
3572 {
3573 memcpy(pbDst, pSrc, cbWidth);
3574
3575 pbDst += cbDestPitch;
3576 pSrc += cbSrcPitch;
3577 }
3578 }
3579 return VINF_SUCCESS;
3580 }
3581
3582 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3583 pGMR = &pSVGAState->aGMR[src.gmrId];
3584 pDesc = pGMR->paDesc;
3585
3586 offSrc += src.offset;
3587 AssertMsgReturn(src.offset < pGMR->cbTotal,
3588 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3589 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3590 VERR_INVALID_PARAMETER);
3591 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3592 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3593 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3594 VERR_INVALID_PARAMETER);
3595
3596 for (uint32_t i = 0; i < cHeight; i++)
3597 {
3598 uint32_t cbCurrentWidth = cbWidth;
3599 uint32_t offCurrent = offSrc;
3600 uint8_t *pCurrentDest = pbDst;
3601
3602 /* Find the right descriptor */
3603 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3604 {
3605 offDesc += pDesc->numPages * PAGE_SIZE;
3606 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3607 pDesc++;
3608 }
3609
3610 while (cbCurrentWidth)
3611 {
3612 uint32_t cbToCopy;
3613
3614 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3615 {
3616 cbToCopy = cbCurrentWidth;
3617 }
3618 else
3619 {
3620 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3621 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3622 }
3623
3624 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3625
3626 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3627 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3628 else
3629 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3630 AssertRCBreak(rc);
3631
3632 cbCurrentWidth -= cbToCopy;
3633 offCurrent += cbToCopy;
3634 pCurrentDest += cbToCopy;
3635
3636 /* Go to the next descriptor if there's anything left. */
3637 if (cbCurrentWidth)
3638 {
3639 offDesc += pDesc->numPages * PAGE_SIZE;
3640 pDesc++;
3641 }
3642 }
3643
3644 offSrc += cbSrcPitch;
3645 pbDst += cbDestPitch;
3646 }
3647
3648 return VINF_SUCCESS;
3649}
3650
3651/**
3652 * Unblock the FIFO I/O thread so it can respond to a state change.
3653 *
3654 * @returns VBox status code.
3655 * @param pDevIns The VGA device instance.
3656 * @param pThread The send thread.
3657 */
3658static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3659{
3660 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3661 Log(("vmsvgaFIFOLoopWakeUp\n"));
3662 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3663}
3664
3665/**
3666 * Enables or disables dirty page tracking for the framebuffer
3667 *
3668 * @param pThis VGA device instance data.
3669 * @param fTraces Enable/disable traces
3670 */
3671static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3672{
3673 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3674 && !fTraces)
3675 {
3676 //Assert(pThis->svga.fTraces);
3677 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3678 return;
3679 }
3680
3681 pThis->svga.fTraces = fTraces;
3682 if (pThis->svga.fTraces)
3683 {
3684 unsigned cbFrameBuffer = pThis->vram_size;
3685
3686 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3687 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3688 {
3689#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3690 Assert(pThis->svga.cbScanline);
3691#endif
3692 /* Hardware enabled; return real framebuffer size .*/
3693 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3694 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3695 }
3696
3697 if (!pThis->svga.fVRAMTracking)
3698 {
3699 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3700 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3701 pThis->svga.fVRAMTracking = true;
3702 }
3703 }
3704 else
3705 {
3706 if (pThis->svga.fVRAMTracking)
3707 {
3708 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3709 vgaR3UnregisterVRAMHandler(pThis);
3710 pThis->svga.fVRAMTracking = false;
3711 }
3712 }
3713}
3714
3715/**
3716 * Callback function for mapping a PCI I/O region.
3717 *
3718 * @return VBox status code.
3719 * @param pPciDev Pointer to PCI device.
3720 * Use pPciDev->pDevIns to get the device instance.
3721 * @param iRegion The region number.
3722 * @param GCPhysAddress Physical address of the region.
3723 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3724 * I/O port, else it's a physical address.
3725 * This address is *NOT* relative
3726 * to pci_mem_base like earlier!
3727 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3728 */
3729DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3730{
3731 int rc;
3732 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3733 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3734
3735 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3736 if (enmType == PCI_ADDRESS_SPACE_IO)
3737 {
3738 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3739 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3740 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3741 if (RT_FAILURE(rc))
3742 return rc;
3743 if (pThis->fR0Enabled)
3744 {
3745 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3746 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3747 if (RT_FAILURE(rc))
3748 return rc;
3749 }
3750 if (pThis->fGCEnabled)
3751 {
3752 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3753 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3754 if (RT_FAILURE(rc))
3755 return rc;
3756 }
3757
3758 pThis->svga.BasePort = GCPhysAddress;
3759 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3760 }
3761 else
3762 {
3763 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3764 if (GCPhysAddress != NIL_RTGCPHYS)
3765 {
3766 /*
3767 * Mapping the FIFO RAM.
3768 */
3769 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3770 AssertRC(rc);
3771
3772# ifdef DEBUG_FIFO_ACCESS
3773 if (RT_SUCCESS(rc))
3774 {
3775 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3776 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3777 "VMSVGA FIFO");
3778 AssertRC(rc);
3779 }
3780# endif
3781 if (RT_SUCCESS(rc))
3782 {
3783 pThis->svga.GCPhysFIFO = GCPhysAddress;
3784 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3785 }
3786 }
3787 else
3788 {
3789 Assert(pThis->svga.GCPhysFIFO);
3790# ifdef DEBUG_FIFO_ACCESS
3791 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3792 AssertRC(rc);
3793# endif
3794 pThis->svga.GCPhysFIFO = 0;
3795 }
3796
3797 }
3798 return VINF_SUCCESS;
3799}
3800
3801# ifdef VBOX_WITH_VMSVGA3D
3802
3803/**
3804 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3805 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3806 *
3807 * @param pThis The VGA device instance data.
3808 * @param sid Either UINT32_MAX or the ID of a specific
3809 * surface. If UINT32_MAX is used, all surfaces
3810 * are processed.
3811 */
3812void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3813{
3814 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3815 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3816}
3817
3818
3819/**
3820 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3821 */
3822DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3823{
3824 /* There might be a specific context ID at the start of the
3825 arguments, if not show all contexts. */
3826 uint32_t cid = UINT32_MAX;
3827 if (pszArgs)
3828 pszArgs = RTStrStripL(pszArgs);
3829 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3830 cid = RTStrToUInt32(pszArgs);
3831
3832 /* Verbose or terse display, we default to verbose. */
3833 bool fVerbose = true;
3834 if (RTStrIStr(pszArgs, "terse"))
3835 fVerbose = false;
3836
3837 /* The size of the ascii art (x direction, y is 3/4 of x). */
3838 uint32_t cxAscii = 80;
3839 if (RTStrIStr(pszArgs, "gigantic"))
3840 cxAscii = 300;
3841 else if (RTStrIStr(pszArgs, "huge"))
3842 cxAscii = 180;
3843 else if (RTStrIStr(pszArgs, "big"))
3844 cxAscii = 132;
3845 else if (RTStrIStr(pszArgs, "normal"))
3846 cxAscii = 80;
3847 else if (RTStrIStr(pszArgs, "medium"))
3848 cxAscii = 64;
3849 else if (RTStrIStr(pszArgs, "small"))
3850 cxAscii = 48;
3851 else if (RTStrIStr(pszArgs, "tiny"))
3852 cxAscii = 24;
3853
3854 /* Y invert the image when producing the ASCII art. */
3855 bool fInvY = false;
3856 if (RTStrIStr(pszArgs, "invy"))
3857 fInvY = true;
3858
3859 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3860}
3861
3862
3863/**
3864 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3865 */
3866DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3867{
3868 /* There might be a specific surface ID at the start of the
3869 arguments, if not show all contexts. */
3870 uint32_t sid = UINT32_MAX;
3871 if (pszArgs)
3872 pszArgs = RTStrStripL(pszArgs);
3873 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3874 sid = RTStrToUInt32(pszArgs);
3875
3876 /* Verbose or terse display, we default to verbose. */
3877 bool fVerbose = true;
3878 if (RTStrIStr(pszArgs, "terse"))
3879 fVerbose = false;
3880
3881 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3882}
3883
3884# endif /* VBOX_WITH_VMSVGA3D */
3885
3886/**
3887 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3888 */
3889static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3890{
3891 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3892 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3893
3894 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3895 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3896 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3897 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3898 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3899 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3900 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3901 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3902 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3903 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3904 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3905 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3906 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3907 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3908 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3909 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3910 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3911 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3912 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3913 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3914 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3915 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3916
3917 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3918 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3919 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3920 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3921
3922# ifdef VBOX_WITH_VMSVGA3D
3923 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3924 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3925 if (pThis->svga.u64HostWindowId != 0)
3926 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3927# endif
3928}
3929
3930
3931/**
3932 * @copydoc FNSSMDEVLOADEXEC
3933 */
3934int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3935{
3936 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3937 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3938 int rc;
3939
3940 /* Load our part of the VGAState */
3941 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3942 AssertRCReturn(rc, rc);
3943
3944 /* Load the framebuffer backup. */
3945 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3946 AssertRCReturn(rc, rc);
3947
3948 /* Load the VMSVGA state. */
3949 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3950 AssertRCReturn(rc, rc);
3951
3952 /* Load the active cursor bitmaps. */
3953 if (pSVGAState->Cursor.fActive)
3954 {
3955 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3956 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3957
3958 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3959 AssertRCReturn(rc, rc);
3960 }
3961
3962 /* Load the GMR state */
3963 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3964 {
3965 PGMR pGMR = &pSVGAState->aGMR[i];
3966
3967 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3968 AssertRCReturn(rc, rc);
3969
3970 if (pGMR->numDescriptors)
3971 {
3972 /* Allocate the maximum amount possible (everything non-continuous) */
3973 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3974 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3975 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3976
3977 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3978 {
3979 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3980 AssertRCReturn(rc, rc);
3981 }
3982 }
3983 }
3984
3985# ifdef VBOX_WITH_VMSVGA3D
3986 if (pThis->svga.f3DEnabled)
3987 {
3988# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
3989 vmsvga3dPowerOn(pThis);
3990# endif
3991
3992 VMSVGA_STATE_LOAD LoadState;
3993 LoadState.pSSM = pSSM;
3994 LoadState.uVersion = uVersion;
3995 LoadState.uPass = uPass;
3996 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
3997 AssertLogRelRCReturn(rc, rc);
3998 }
3999# endif
4000
4001 return VINF_SUCCESS;
4002}
4003
4004/**
4005 * Reinit the video mode after the state has been loaded.
4006 */
4007int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4008{
4009 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4010 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4011
4012 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4013 vmsvgaChangeMode(pThis);
4014
4015 /* Set the active cursor. */
4016 if (pSVGAState->Cursor.fActive)
4017 {
4018 int rc;
4019
4020 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4021 true,
4022 true,
4023 pSVGAState->Cursor.xHotspot,
4024 pSVGAState->Cursor.yHotspot,
4025 pSVGAState->Cursor.width,
4026 pSVGAState->Cursor.height,
4027 pSVGAState->Cursor.pData);
4028 AssertRC(rc);
4029 }
4030 return VINF_SUCCESS;
4031}
4032
4033/**
4034 * @copydoc FNSSMDEVSAVEEXEC
4035 */
4036int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4037{
4038 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4039 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4040 int rc;
4041
4042 /* Save our part of the VGAState */
4043 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4044 AssertLogRelRCReturn(rc, rc);
4045
4046 /* Save the framebuffer backup. */
4047 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4048 AssertLogRelRCReturn(rc, rc);
4049
4050 /* Save the VMSVGA state. */
4051 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4052 AssertLogRelRCReturn(rc, rc);
4053
4054 /* Save the active cursor bitmaps. */
4055 if (pSVGAState->Cursor.fActive)
4056 {
4057 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4058 AssertLogRelRCReturn(rc, rc);
4059 }
4060
4061 /* Save the GMR state */
4062 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4063 {
4064 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4065 AssertLogRelRCReturn(rc, rc);
4066
4067 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4068 {
4069 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4070 AssertLogRelRCReturn(rc, rc);
4071 }
4072 }
4073
4074# ifdef VBOX_WITH_VMSVGA3D
4075 /*
4076 * Must save the 3d state in the FIFO thread.
4077 */
4078 if (pThis->svga.f3DEnabled)
4079 {
4080 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4081 AssertLogRelRCReturn(rc, rc);
4082 }
4083# endif
4084 return VINF_SUCCESS;
4085}
4086
4087/**
4088 * Resets the SVGA hardware state
4089 *
4090 * @returns VBox status code.
4091 * @param pDevIns The device instance.
4092 */
4093int vmsvgaReset(PPDMDEVINS pDevIns)
4094{
4095 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4096 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4097
4098 /* Reset before init? */
4099 if (!pSVGAState)
4100 return VINF_SUCCESS;
4101
4102 Log(("vmsvgaReset\n"));
4103
4104
4105 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4106 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4107 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4108
4109 /* Reset other stuff. */
4110 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4111 RT_ZERO(pThis->svga.au32ScratchRegion);
4112 RT_ZERO(*pThis->svga.pSvgaR3State);
4113 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4114
4115 /* Register caps. */
4116 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4117# ifdef VBOX_WITH_VMSVGA3D
4118 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4119# endif
4120
4121 /* Setup FIFO capabilities. */
4122 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4123
4124 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4125 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4126
4127 /* VRAM tracking is enabled by default during bootup. */
4128 pThis->svga.fVRAMTracking = true;
4129 pThis->svga.fEnabled = false;
4130
4131 /* Invalidate current settings. */
4132 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4133 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4134 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4135 pThis->svga.cbScanline = 0;
4136
4137 return rc;
4138}
4139
4140/**
4141 * Cleans up the SVGA hardware state
4142 *
4143 * @returns VBox status code.
4144 * @param pDevIns The device instance.
4145 */
4146int vmsvgaDestruct(PPDMDEVINS pDevIns)
4147{
4148 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4149
4150 /*
4151 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4152 */
4153 if (pThis->svga.pFIFOIOThread)
4154 {
4155 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4156 AssertLogRelRC(rc);
4157
4158 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4159 AssertLogRelRC(rc);
4160 pThis->svga.pFIFOIOThread = NULL;
4161 }
4162
4163 /*
4164 * Destroy the special SVGA state.
4165 */
4166 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4167 if (pSVGAState)
4168 {
4169# ifndef VMSVGA_USE_EMT_HALT_CODE
4170 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4171 {
4172 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4173 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4174 }
4175# endif
4176 if (pSVGAState->Cursor.fActive)
4177 RTMemFree(pSVGAState->Cursor.pData);
4178
4179 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4180 if (pSVGAState->aGMR[i].paDesc)
4181 RTMemFree(pSVGAState->aGMR[i].paDesc);
4182
4183 RTMemFree(pSVGAState);
4184 pThis->svga.pSvgaR3State = NULL;
4185 }
4186
4187 /*
4188 * Free our resources residing in the VGA state.
4189 */
4190 if (pThis->svga.pFrameBufferBackup)
4191 RTMemFree(pThis->svga.pFrameBufferBackup);
4192 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4193 {
4194 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4195 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4196 }
4197 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4198 {
4199 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4200 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4201 }
4202
4203 return VINF_SUCCESS;
4204}
4205
4206/**
4207 * Initialize the SVGA hardware state
4208 *
4209 * @returns VBox status code.
4210 * @param pDevIns The device instance.
4211 */
4212int vmsvgaInit(PPDMDEVINS pDevIns)
4213{
4214 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4215 PVMSVGAR3STATE pSVGAState;
4216 PVM pVM = PDMDevHlpGetVM(pDevIns);
4217 int rc;
4218
4219 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4220 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4221
4222 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4223 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4224 pSVGAState = pThis->svga.pSvgaR3State;
4225
4226 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4227 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4228 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4229
4230 /* Create event semaphore. */
4231 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4232
4233 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4234 if (RT_FAILURE(rc))
4235 {
4236 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4237 return rc;
4238 }
4239
4240 /* Create event semaphore. */
4241 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4242 if (RT_FAILURE(rc))
4243 {
4244 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4245 return rc;
4246 }
4247
4248# ifndef VMSVGA_USE_EMT_HALT_CODE
4249 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4250 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4251 AssertRCReturn(rc, rc);
4252# endif
4253
4254 /* Register caps. */
4255 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4256# ifdef VBOX_WITH_VMSVGA3D
4257 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4258# endif
4259
4260 /* Setup FIFO capabilities. */
4261 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4262
4263 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4264 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4265
4266 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4267# ifdef VBOX_WITH_VMSVGA3D
4268 if (pThis->svga.f3DEnabled)
4269 {
4270 rc = vmsvga3dInit(pThis);
4271 if (RT_FAILURE(rc))
4272 {
4273 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4274 pThis->svga.f3DEnabled = false;
4275 }
4276 }
4277# endif
4278 /* VRAM tracking is enabled by default during bootup. */
4279 pThis->svga.fVRAMTracking = true;
4280
4281 /* Invalidate current settings. */
4282 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4283 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4284 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4285 pThis->svga.cbScanline = 0;
4286
4287 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4288 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4289 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4290 {
4291 pThis->svga.u32MaxWidth -= 256;
4292 pThis->svga.u32MaxHeight -= 256;
4293 }
4294 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4295
4296# ifdef DEBUG_GMR_ACCESS
4297 /* Register the GMR access handler type. */
4298 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4299 vmsvgaR3GMRAccessHandler,
4300 NULL, NULL, NULL,
4301 NULL, NULL, NULL,
4302 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4303 AssertRCReturn(rc, rc);
4304# endif
4305# ifdef DEBUG_FIFO_ACCESS
4306 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4307 vmsvgaR3FIFOAccessHandler,
4308 NULL, NULL, NULL,
4309 NULL, NULL, NULL,
4310 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4311 AssertRCReturn(rc, rc);
4312#endif
4313
4314 /* Create the async IO thread. */
4315 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4316 RTTHREADTYPE_IO, "VMSVGA FIFO");
4317 if (RT_FAILURE(rc))
4318 {
4319 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4320 return rc;
4321 }
4322
4323 /*
4324 * Statistics.
4325 */
4326 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4327 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4328 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4329 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4330 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4331 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4332 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4333 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4334 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4335 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4336
4337 /*
4338 * Info handlers.
4339 */
4340 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4341# ifdef VBOX_WITH_VMSVGA3D
4342 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4343 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4344 "VMSVGA 3d surface details. "
4345 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4346 vmsvgaR3Info3dSurface);
4347# endif
4348
4349 return VINF_SUCCESS;
4350}
4351
4352# ifdef VBOX_WITH_VMSVGA3D
4353/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4354static const char * const g_apszVmSvgaDevCapNames[] =
4355{
4356 "x3D", /* = 0 */
4357 "xMAX_LIGHTS",
4358 "xMAX_TEXTURES",
4359 "xMAX_CLIP_PLANES",
4360 "xVERTEX_SHADER_VERSION",
4361 "xVERTEX_SHADER",
4362 "xFRAGMENT_SHADER_VERSION",
4363 "xFRAGMENT_SHADER",
4364 "xMAX_RENDER_TARGETS",
4365 "xS23E8_TEXTURES",
4366 "xS10E5_TEXTURES",
4367 "xMAX_FIXED_VERTEXBLEND",
4368 "xD16_BUFFER_FORMAT",
4369 "xD24S8_BUFFER_FORMAT",
4370 "xD24X8_BUFFER_FORMAT",
4371 "xQUERY_TYPES",
4372 "xTEXTURE_GRADIENT_SAMPLING",
4373 "rMAX_POINT_SIZE",
4374 "xMAX_SHADER_TEXTURES",
4375 "xMAX_TEXTURE_WIDTH",
4376 "xMAX_TEXTURE_HEIGHT",
4377 "xMAX_VOLUME_EXTENT",
4378 "xMAX_TEXTURE_REPEAT",
4379 "xMAX_TEXTURE_ASPECT_RATIO",
4380 "xMAX_TEXTURE_ANISOTROPY",
4381 "xMAX_PRIMITIVE_COUNT",
4382 "xMAX_VERTEX_INDEX",
4383 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4384 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4385 "xMAX_VERTEX_SHADER_TEMPS",
4386 "xMAX_FRAGMENT_SHADER_TEMPS",
4387 "xTEXTURE_OPS",
4388 "xSURFACEFMT_X8R8G8B8",
4389 "xSURFACEFMT_A8R8G8B8",
4390 "xSURFACEFMT_A2R10G10B10",
4391 "xSURFACEFMT_X1R5G5B5",
4392 "xSURFACEFMT_A1R5G5B5",
4393 "xSURFACEFMT_A4R4G4B4",
4394 "xSURFACEFMT_R5G6B5",
4395 "xSURFACEFMT_LUMINANCE16",
4396 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4397 "xSURFACEFMT_ALPHA8",
4398 "xSURFACEFMT_LUMINANCE8",
4399 "xSURFACEFMT_Z_D16",
4400 "xSURFACEFMT_Z_D24S8",
4401 "xSURFACEFMT_Z_D24X8",
4402 "xSURFACEFMT_DXT1",
4403 "xSURFACEFMT_DXT2",
4404 "xSURFACEFMT_DXT3",
4405 "xSURFACEFMT_DXT4",
4406 "xSURFACEFMT_DXT5",
4407 "xSURFACEFMT_BUMPX8L8V8U8",
4408 "xSURFACEFMT_A2W10V10U10",
4409 "xSURFACEFMT_BUMPU8V8",
4410 "xSURFACEFMT_Q8W8V8U8",
4411 "xSURFACEFMT_CxV8U8",
4412 "xSURFACEFMT_R_S10E5",
4413 "xSURFACEFMT_R_S23E8",
4414 "xSURFACEFMT_RG_S10E5",
4415 "xSURFACEFMT_RG_S23E8",
4416 "xSURFACEFMT_ARGB_S10E5",
4417 "xSURFACEFMT_ARGB_S23E8",
4418 "xMISSING62",
4419 "xMAX_VERTEX_SHADER_TEXTURES",
4420 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4421 "xSURFACEFMT_V16U16",
4422 "xSURFACEFMT_G16R16",
4423 "xSURFACEFMT_A16B16G16R16",
4424 "xSURFACEFMT_UYVY",
4425 "xSURFACEFMT_YUY2",
4426 "xMULTISAMPLE_NONMASKABLESAMPLES",
4427 "xMULTISAMPLE_MASKABLESAMPLES",
4428 "xALPHATOCOVERAGE",
4429 "xSUPERSAMPLE",
4430 "xAUTOGENMIPMAPS",
4431 "xSURFACEFMT_NV12",
4432 "xSURFACEFMT_AYUV",
4433 "xMAX_CONTEXT_IDS",
4434 "xMAX_SURFACE_IDS",
4435 "xSURFACEFMT_Z_DF16",
4436 "xSURFACEFMT_Z_DF24",
4437 "xSURFACEFMT_Z_D24S8_INT",
4438 "xSURFACEFMT_BC4_UNORM",
4439 "xSURFACEFMT_BC5_UNORM", /* 83 */
4440};
4441# endif
4442
4443
4444/**
4445 * Power On notification.
4446 *
4447 * @returns VBox status code.
4448 * @param pDevIns The device instance data.
4449 *
4450 * @remarks Caller enters the device critical section.
4451 */
4452DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4453{
4454 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4455 int rc;
4456
4457# ifdef VBOX_WITH_VMSVGA3D
4458 if (pThis->svga.f3DEnabled)
4459 {
4460 rc = vmsvga3dPowerOn(pThis);
4461
4462 if (RT_SUCCESS(rc))
4463 {
4464 bool fSavedBuffering = RTLogRelSetBuffering(true);
4465 SVGA3dCapsRecord *pCaps;
4466 SVGA3dCapPair *pData;
4467 uint32_t idxCap = 0;
4468
4469 /* 3d hardware version; latest and greatest */
4470 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4471 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4472
4473 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4474 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4475 pData = (SVGA3dCapPair *)&pCaps->data;
4476
4477 /* Fill out all 3d capabilities. */
4478 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4479 {
4480 uint32_t val = 0;
4481
4482 rc = vmsvga3dQueryCaps(pThis, i, &val);
4483 if (RT_SUCCESS(rc))
4484 {
4485 pData[idxCap][0] = i;
4486 pData[idxCap][1] = val;
4487 idxCap++;
4488 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4489 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4490 else
4491 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4492 &g_apszVmSvgaDevCapNames[i][1]));
4493 }
4494 else
4495 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4496 }
4497 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4498 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4499
4500 /* Mark end of record array. */
4501 pCaps->header.length = 0;
4502
4503 RTLogRelSetBuffering(fSavedBuffering);
4504 }
4505 }
4506# endif // VBOX_WITH_VMSVGA3D
4507}
4508
4509#endif /* IN_RING3 */
4510
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