VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 62920

Last change on this file since 62920 was 62618, checked in by vboxsync, 8 years ago

Devices: unused parameter warnings.
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1/* $Id: DevVGA-SVGA.cpp 62618 2016-07-28 11:23:36Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2016 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.virtualbox.org. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295
296#ifdef LOG_ENABLED
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417/**
418 * FIFO command name lookup
419 *
420 * @returns FIFO command string or "UNKNOWN"
421 * @param u32Cmd FIFO command
422 */
423static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
424{
425 switch (u32Cmd)
426 {
427 case SVGA_CMD_INVALID_CMD:
428 return "SVGA_CMD_INVALID_CMD";
429 case SVGA_CMD_UPDATE:
430 return "SVGA_CMD_UPDATE";
431 case SVGA_CMD_RECT_COPY:
432 return "SVGA_CMD_RECT_COPY";
433 case SVGA_CMD_DEFINE_CURSOR:
434 return "SVGA_CMD_DEFINE_CURSOR";
435 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
436 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
437 case SVGA_CMD_UPDATE_VERBOSE:
438 return "SVGA_CMD_UPDATE_VERBOSE";
439 case SVGA_CMD_FRONT_ROP_FILL:
440 return "SVGA_CMD_FRONT_ROP_FILL";
441 case SVGA_CMD_FENCE:
442 return "SVGA_CMD_FENCE";
443 case SVGA_CMD_ESCAPE:
444 return "SVGA_CMD_ESCAPE";
445 case SVGA_CMD_DEFINE_SCREEN:
446 return "SVGA_CMD_DEFINE_SCREEN";
447 case SVGA_CMD_DESTROY_SCREEN:
448 return "SVGA_CMD_DESTROY_SCREEN";
449 case SVGA_CMD_DEFINE_GMRFB:
450 return "SVGA_CMD_DEFINE_GMRFB";
451 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
452 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
453 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
454 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
455 case SVGA_CMD_ANNOTATION_FILL:
456 return "SVGA_CMD_ANNOTATION_FILL";
457 case SVGA_CMD_ANNOTATION_COPY:
458 return "SVGA_CMD_ANNOTATION_COPY";
459 case SVGA_CMD_DEFINE_GMR2:
460 return "SVGA_CMD_DEFINE_GMR2";
461 case SVGA_CMD_REMAP_GMR2:
462 return "SVGA_CMD_REMAP_GMR2";
463 case SVGA_3D_CMD_SURFACE_DEFINE:
464 return "SVGA_3D_CMD_SURFACE_DEFINE";
465 case SVGA_3D_CMD_SURFACE_DESTROY:
466 return "SVGA_3D_CMD_SURFACE_DESTROY";
467 case SVGA_3D_CMD_SURFACE_COPY:
468 return "SVGA_3D_CMD_SURFACE_COPY";
469 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
470 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
471 case SVGA_3D_CMD_SURFACE_DMA:
472 return "SVGA_3D_CMD_SURFACE_DMA";
473 case SVGA_3D_CMD_CONTEXT_DEFINE:
474 return "SVGA_3D_CMD_CONTEXT_DEFINE";
475 case SVGA_3D_CMD_CONTEXT_DESTROY:
476 return "SVGA_3D_CMD_CONTEXT_DESTROY";
477 case SVGA_3D_CMD_SETTRANSFORM:
478 return "SVGA_3D_CMD_SETTRANSFORM";
479 case SVGA_3D_CMD_SETZRANGE:
480 return "SVGA_3D_CMD_SETZRANGE";
481 case SVGA_3D_CMD_SETRENDERSTATE:
482 return "SVGA_3D_CMD_SETRENDERSTATE";
483 case SVGA_3D_CMD_SETRENDERTARGET:
484 return "SVGA_3D_CMD_SETRENDERTARGET";
485 case SVGA_3D_CMD_SETTEXTURESTATE:
486 return "SVGA_3D_CMD_SETTEXTURESTATE";
487 case SVGA_3D_CMD_SETMATERIAL:
488 return "SVGA_3D_CMD_SETMATERIAL";
489 case SVGA_3D_CMD_SETLIGHTDATA:
490 return "SVGA_3D_CMD_SETLIGHTDATA";
491 case SVGA_3D_CMD_SETLIGHTENABLED:
492 return "SVGA_3D_CMD_SETLIGHTENABLED";
493 case SVGA_3D_CMD_SETVIEWPORT:
494 return "SVGA_3D_CMD_SETVIEWPORT";
495 case SVGA_3D_CMD_SETCLIPPLANE:
496 return "SVGA_3D_CMD_SETCLIPPLANE";
497 case SVGA_3D_CMD_CLEAR:
498 return "SVGA_3D_CMD_CLEAR";
499 case SVGA_3D_CMD_PRESENT:
500 return "SVGA_3D_CMD_PRESENT";
501 case SVGA_3D_CMD_SHADER_DEFINE:
502 return "SVGA_3D_CMD_SHADER_DEFINE";
503 case SVGA_3D_CMD_SHADER_DESTROY:
504 return "SVGA_3D_CMD_SHADER_DESTROY";
505 case SVGA_3D_CMD_SET_SHADER:
506 return "SVGA_3D_CMD_SET_SHADER";
507 case SVGA_3D_CMD_SET_SHADER_CONST:
508 return "SVGA_3D_CMD_SET_SHADER_CONST";
509 case SVGA_3D_CMD_DRAW_PRIMITIVES:
510 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
511 case SVGA_3D_CMD_SETSCISSORRECT:
512 return "SVGA_3D_CMD_SETSCISSORRECT";
513 case SVGA_3D_CMD_BEGIN_QUERY:
514 return "SVGA_3D_CMD_BEGIN_QUERY";
515 case SVGA_3D_CMD_END_QUERY:
516 return "SVGA_3D_CMD_END_QUERY";
517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
518 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
519 case SVGA_3D_CMD_PRESENT_READBACK:
520 return "SVGA_3D_CMD_PRESENT_READBACK";
521 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
522 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
523 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
524 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
525 case SVGA_3D_CMD_GENERATE_MIPMAPS:
526 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
527 case SVGA_3D_CMD_ACTIVATE_SURFACE:
528 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
529 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
530 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
531 default:
532 return "UNKNOWN";
533 }
534}
535#endif
536
537#ifdef IN_RING3
538/**
539 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
540 */
541DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
542{
543 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
544
545 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
546 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
547
548 if (x < pThis->svga.uWidth)
549 {
550 pThis->svga.viewport.x = x;
551 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
552 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
553 }
554 else
555 {
556 pThis->svga.viewport.x = pThis->svga.uWidth;
557 pThis->svga.viewport.cx = 0;
558 pThis->svga.viewport.xRight = pThis->svga.uWidth;
559 }
560 if (y < pThis->svga.uHeight)
561 {
562 pThis->svga.viewport.y = y;
563 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
564 pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
565 pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
566 }
567 else
568 {
569 pThis->svga.viewport.y = pThis->svga.uHeight;
570 pThis->svga.viewport.cy = 0;
571 pThis->svga.viewport.yLowWC = 0;
572 pThis->svga.viewport.yHighWC = 0;
573 }
574
575# ifdef VBOX_WITH_VMSVGA3D
576 /*
577 * Now inform the 3D backend.
578 */
579 if (pThis->svga.f3DEnabled)
580 vmsvga3dUpdateHostScreenViewport(pThis, uScreenId, &OldViewport);
581# endif
582}
583#endif /* IN_RING3 */
584
585/**
586 * Read port register
587 *
588 * @returns VBox status code.
589 * @param pThis VMSVGA State
590 * @param pu32 Where to store the read value
591 */
592PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
593{
594 int rc = VINF_SUCCESS;
595
596 *pu32 = 0;
597 switch (pThis->svga.u32IndexReg)
598 {
599 case SVGA_REG_ID:
600 *pu32 = pThis->svga.u32SVGAId;
601 break;
602
603 case SVGA_REG_ENABLE:
604 *pu32 = pThis->svga.fEnabled;
605 break;
606
607 case SVGA_REG_WIDTH:
608 {
609 if ( pThis->svga.fEnabled
610 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
611 {
612 *pu32 = pThis->svga.uWidth;
613 }
614 else
615 {
616#ifndef IN_RING3
617 rc = VINF_IOM_R3_IOPORT_READ;
618#else
619 *pu32 = pThis->pDrv->cx;
620#endif
621 }
622 break;
623 }
624
625 case SVGA_REG_HEIGHT:
626 {
627 if ( pThis->svga.fEnabled
628 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
629 {
630 *pu32 = pThis->svga.uHeight;
631 }
632 else
633 {
634#ifndef IN_RING3
635 rc = VINF_IOM_R3_IOPORT_READ;
636#else
637 *pu32 = pThis->pDrv->cy;
638#endif
639 }
640 break;
641 }
642
643 case SVGA_REG_MAX_WIDTH:
644 *pu32 = pThis->svga.u32MaxWidth;
645 break;
646
647 case SVGA_REG_MAX_HEIGHT:
648 *pu32 = pThis->svga.u32MaxHeight;
649 break;
650
651 case SVGA_REG_DEPTH:
652 /* This returns the color depth of the current mode. */
653 switch (pThis->svga.uBpp)
654 {
655 case 15:
656 case 16:
657 case 24:
658 *pu32 = pThis->svga.uBpp;
659 break;
660
661 default:
662 case 32:
663 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
664 break;
665 }
666 break;
667
668 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
669 if ( pThis->svga.fEnabled
670 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
671 {
672 *pu32 = pThis->svga.uBpp;
673 }
674 else
675 {
676#ifndef IN_RING3
677 rc = VINF_IOM_R3_IOPORT_READ;
678#else
679 *pu32 = pThis->pDrv->cBits;
680#endif
681 }
682 break;
683
684 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
685 if ( pThis->svga.fEnabled
686 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
687 {
688 *pu32 = (pThis->svga.uBpp + 7) & ~7;
689 }
690 else
691 {
692#ifndef IN_RING3
693 rc = VINF_IOM_R3_IOPORT_READ;
694#else
695 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
696#endif
697 }
698 break;
699
700 case SVGA_REG_PSEUDOCOLOR:
701 *pu32 = 0;
702 break;
703
704 case SVGA_REG_RED_MASK:
705 case SVGA_REG_GREEN_MASK:
706 case SVGA_REG_BLUE_MASK:
707 {
708 uint32_t uBpp;
709
710 if ( pThis->svga.fEnabled
711 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
712 {
713 uBpp = pThis->svga.uBpp;
714 }
715 else
716 {
717#ifndef IN_RING3
718 rc = VINF_IOM_R3_IOPORT_READ;
719 break;
720#else
721 uBpp = pThis->pDrv->cBits;
722#endif
723 }
724 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
725 switch (uBpp)
726 {
727 case 8:
728 u32RedMask = 0x07;
729 u32GreenMask = 0x38;
730 u32BlueMask = 0xc0;
731 break;
732
733 case 15:
734 u32RedMask = 0x0000001f;
735 u32GreenMask = 0x000003e0;
736 u32BlueMask = 0x00007c00;
737 break;
738
739 case 16:
740 u32RedMask = 0x0000001f;
741 u32GreenMask = 0x000007e0;
742 u32BlueMask = 0x0000f800;
743 break;
744
745 case 24:
746 case 32:
747 default:
748 u32RedMask = 0x00ff0000;
749 u32GreenMask = 0x0000ff00;
750 u32BlueMask = 0x000000ff;
751 break;
752 }
753 switch (pThis->svga.u32IndexReg)
754 {
755 case SVGA_REG_RED_MASK:
756 *pu32 = u32RedMask;
757 break;
758
759 case SVGA_REG_GREEN_MASK:
760 *pu32 = u32GreenMask;
761 break;
762
763 case SVGA_REG_BLUE_MASK:
764 *pu32 = u32BlueMask;
765 break;
766 }
767 break;
768 }
769
770 case SVGA_REG_BYTES_PER_LINE:
771 {
772 if ( pThis->svga.fEnabled
773 && pThis->svga.cbScanline)
774 {
775 *pu32 = pThis->svga.cbScanline;
776 }
777 else
778 {
779#ifndef IN_RING3
780 rc = VINF_IOM_R3_IOPORT_READ;
781#else
782 *pu32 = pThis->pDrv->cbScanline;
783#endif
784 }
785 break;
786 }
787
788 case SVGA_REG_VRAM_SIZE: /* VRAM size */
789 *pu32 = pThis->vram_size;
790 break;
791
792 case SVGA_REG_FB_START: /* Frame buffer physical address. */
793 Assert(pThis->GCPhysVRAM <= 0xffffffff);
794 *pu32 = pThis->GCPhysVRAM;
795 break;
796
797 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
798 /* Always zero in our case. */
799 *pu32 = 0;
800 break;
801
802 case SVGA_REG_FB_SIZE: /* Frame buffer size */
803 {
804#ifndef IN_RING3
805 rc = VINF_IOM_R3_IOPORT_READ;
806#else
807 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
808 if ( pThis->svga.fEnabled
809 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
810 {
811 /* Hardware enabled; return real framebuffer size .*/
812 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
813 }
814 else
815 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
816
817 *pu32 = RT_MIN(pThis->vram_size, *pu32);
818 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
819#endif
820 break;
821 }
822
823 case SVGA_REG_CAPABILITIES:
824 *pu32 = pThis->svga.u32RegCaps;
825 break;
826
827 case SVGA_REG_MEM_START: /* FIFO start */
828 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
829 *pu32 = pThis->svga.GCPhysFIFO;
830 break;
831
832 case SVGA_REG_MEM_SIZE: /* FIFO size */
833 *pu32 = pThis->svga.cbFIFO;
834 break;
835
836 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
837 *pu32 = pThis->svga.fConfigured;
838 break;
839
840 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
841 *pu32 = 0;
842 break;
843
844 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
845 if (pThis->svga.fBusy)
846 {
847#ifndef IN_RING3
848 /* Go to ring-3 and halt the CPU. */
849 rc = VINF_IOM_R3_IOPORT_READ;
850 break;
851#else
852# if defined(VMSVGA_USE_EMT_HALT_CODE)
853 /* The guest is basically doing a HLT via the device here, but with
854 a special wake up condition on FIFO completion. */
855 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
856 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
857 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
858 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
859 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
860 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
861 if (pThis->svga.fBusy)
862 rc = VMR3WaitForDeviceReady(pVM, idCpu);
863 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
864 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
865# else
866
867 /* Delay the EMT a bit so the FIFO and others can get some work done.
868 This used to be a crude 50 ms sleep. The current code tries to be
869 more efficient, but the consept is still very crude. */
870 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
871 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
872 RTThreadYield();
873 if (pThis->svga.fBusy)
874 {
875 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
876
877 if (pThis->svga.fBusy && cRefs == 1)
878 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
879 if (pThis->svga.fBusy)
880 {
881 /** @todo If this code is going to stay, we need to call into the halt/wait
882 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
883 * suffer when the guest is polling on a busy FIFO. */
884 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
885 if (cNsMaxWait >= RT_NS_100US)
886 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
887 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
888 RT_MIN(cNsMaxWait, RT_NS_10MS));
889 }
890
891 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
892 }
893 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
894# endif
895 *pu32 = pThis->svga.fBusy != 0;
896#endif
897 }
898 else
899 *pu32 = false;
900 break;
901
902 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
903 *pu32 = pThis->svga.u32GuestId;
904 break;
905
906 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
907 *pu32 = pThis->svga.cScratchRegion;
908 break;
909
910 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
911 *pu32 = SVGA_FIFO_NUM_REGS;
912 break;
913
914 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
915 *pu32 = pThis->svga.u32PitchLock;
916 break;
917
918 case SVGA_REG_IRQMASK: /* Interrupt mask */
919 *pu32 = pThis->svga.u32IrqMask;
920 break;
921
922 /* See "Guest memory regions" below. */
923 case SVGA_REG_GMR_ID:
924 *pu32 = pThis->svga.u32CurrentGMRId;
925 break;
926
927 case SVGA_REG_GMR_DESCRIPTOR:
928 /* Write only */
929 *pu32 = 0;
930 break;
931
932 case SVGA_REG_GMR_MAX_IDS:
933 *pu32 = VMSVGA_MAX_GMR_IDS;
934 break;
935
936 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
937 *pu32 = VMSVGA_MAX_GMR_PAGES;
938 break;
939
940 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
941 *pu32 = pThis->svga.fTraces;
942 break;
943
944 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
945 *pu32 = VMSVGA_MAX_GMR_PAGES;
946 break;
947
948 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
949 *pu32 = VMSVGA_SURFACE_SIZE;
950 break;
951
952 case SVGA_REG_TOP: /* Must be 1 more than the last register */
953 break;
954
955 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
956 break;
957 /* Next 768 (== 256*3) registers exist for colormap */
958
959 /* Mouse cursor support. */
960 case SVGA_REG_CURSOR_ID:
961 case SVGA_REG_CURSOR_X:
962 case SVGA_REG_CURSOR_Y:
963 case SVGA_REG_CURSOR_ON:
964 break;
965
966 /* Legacy multi-monitor support */
967 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
968 *pu32 = 1;
969 break;
970
971 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
972 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
973 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
974 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
975 *pu32 = 0;
976 break;
977
978 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
979 *pu32 = pThis->svga.uWidth;
980 break;
981
982 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
983 *pu32 = pThis->svga.uHeight;
984 break;
985
986 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
987 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
988 break;
989
990 default:
991 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
992 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
993 {
994 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
995 }
996 break;
997 }
998 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
999 return rc;
1000}
1001
1002#ifdef IN_RING3
1003/**
1004 * Apply the current resolution settings to change the video mode.
1005 *
1006 * @returns VBox status code.
1007 * @param pThis VMSVGA State
1008 */
1009int vmsvgaChangeMode(PVGASTATE pThis)
1010{
1011 int rc;
1012
1013 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1014 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1015 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1016 {
1017 /* Mode change in progress; wait for all values to be set. */
1018 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1019 return VINF_SUCCESS;
1020 }
1021
1022 if ( pThis->svga.uWidth == 0
1023 || pThis->svga.uHeight == 0
1024 || pThis->svga.uBpp == 0)
1025 {
1026 /* Invalid mode change - BB does this early in the boot up. */
1027 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1028 return VINF_SUCCESS;
1029 }
1030
1031 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1032 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1033 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1034 && pThis->last_width == (unsigned)pThis->svga.uWidth
1035 && pThis->last_height == (unsigned)pThis->svga.uHeight
1036 )
1037 {
1038 /* Nothing to do. */
1039 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1040 return VINF_SUCCESS;
1041 }
1042
1043 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1044 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1045
1046 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1047 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1048 AssertRC(rc);
1049 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1050
1051 /* last stuff */
1052 pThis->last_bpp = pThis->svga.uBpp;
1053 pThis->last_scr_width = pThis->svga.uWidth;
1054 pThis->last_scr_height = pThis->svga.uHeight;
1055 pThis->last_width = pThis->svga.uWidth;
1056 pThis->last_height = pThis->svga.uHeight;
1057
1058 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1059
1060 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1061 if ( pThis->svga.viewport.cx == 0
1062 && pThis->svga.viewport.cy == 0)
1063 {
1064 pThis->svga.viewport.cx = pThis->svga.uWidth;
1065 pThis->svga.viewport.xRight = pThis->svga.uWidth;
1066 pThis->svga.viewport.cy = pThis->svga.uHeight;
1067 pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1068 pThis->svga.viewport.yLowWC = 0;
1069 }
1070 return VINF_SUCCESS;
1071}
1072#endif /* IN_RING3 */
1073
1074#if defined(IN_RING0) || defined(IN_RING3)
1075/**
1076 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1077 *
1078 * @param pThis The VMSVGA state.
1079 * @param fState The busy state.
1080 */
1081DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1082{
1083 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1084
1085 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1086 {
1087 /* Race / unfortunately scheduling. Highly unlikly. */
1088 uint32_t cLoops = 64;
1089 do
1090 {
1091 ASMNopPause();
1092 fState = (pThis->svga.fBusy != 0);
1093 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1094 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1095 }
1096}
1097#endif
1098
1099/**
1100 * Write port register
1101 *
1102 * @returns VBox status code.
1103 * @param pThis VMSVGA State
1104 * @param u32 Value to write
1105 */
1106PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1107{
1108#ifdef IN_RING3
1109 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1110#endif
1111 int rc = VINF_SUCCESS;
1112
1113 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1114 switch (pThis->svga.u32IndexReg)
1115 {
1116 case SVGA_REG_ID:
1117 if ( u32 == SVGA_ID_0
1118 || u32 == SVGA_ID_1
1119 || u32 == SVGA_ID_2)
1120 pThis->svga.u32SVGAId = u32;
1121 break;
1122
1123 case SVGA_REG_ENABLE:
1124 if ( pThis->svga.fEnabled == u32
1125 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1126 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1127 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1128 && pThis->last_width == (unsigned)pThis->svga.uWidth
1129 && pThis->last_height == (unsigned)pThis->svga.uHeight
1130 )
1131 /* Nothing to do. */
1132 break;
1133
1134#ifdef IN_RING3
1135 if ( u32 == 1
1136 && pThis->svga.fEnabled == false)
1137 {
1138 /* Make a backup copy of the first 32k in order to save font data etc. */
1139 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1140 }
1141
1142 pThis->svga.fEnabled = u32;
1143 if (pThis->svga.fEnabled)
1144 {
1145 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1146 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1147 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1148 {
1149 /* Keep the current mode. */
1150 pThis->svga.uWidth = pThis->pDrv->cx;
1151 pThis->svga.uHeight = pThis->pDrv->cy;
1152 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1153 }
1154
1155 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1156 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1157 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1158 {
1159 rc = vmsvgaChangeMode(pThis);
1160 AssertRCReturn(rc, rc);
1161 }
1162 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1163 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1164 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1165
1166 /* Disable or enable dirty page tracking according to the current fTraces value. */
1167 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1168 }
1169 else
1170 {
1171 /* Restore the text mode backup. */
1172 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1173
1174/* pThis->svga.uHeight = -1;
1175 pThis->svga.uWidth = -1;
1176 pThis->svga.uBpp = -1;
1177 pThis->svga.cbScanline = 0; */
1178 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1179
1180 /* Enable dirty page tracking again when going into legacy mode. */
1181 vmsvgaSetTraces(pThis, true);
1182 }
1183#else
1184 rc = VINF_IOM_R3_IOPORT_WRITE;
1185#endif
1186 break;
1187
1188 case SVGA_REG_WIDTH:
1189 if (pThis->svga.uWidth != u32)
1190 {
1191 if (pThis->svga.fEnabled)
1192 {
1193#ifdef IN_RING3
1194 pThis->svga.uWidth = u32;
1195 rc = vmsvgaChangeMode(pThis);
1196 AssertRCReturn(rc, rc);
1197#else
1198 rc = VINF_IOM_R3_IOPORT_WRITE;
1199#endif
1200 }
1201 else
1202 pThis->svga.uWidth = u32;
1203 }
1204 /* else: nop */
1205 break;
1206
1207 case SVGA_REG_HEIGHT:
1208 if (pThis->svga.uHeight != u32)
1209 {
1210 if (pThis->svga.fEnabled)
1211 {
1212#ifdef IN_RING3
1213 pThis->svga.uHeight = u32;
1214 rc = vmsvgaChangeMode(pThis);
1215 AssertRCReturn(rc, rc);
1216#else
1217 rc = VINF_IOM_R3_IOPORT_WRITE;
1218#endif
1219 }
1220 else
1221 pThis->svga.uHeight = u32;
1222 }
1223 /* else: nop */
1224 break;
1225
1226 case SVGA_REG_DEPTH:
1227 /** @todo read-only?? */
1228 break;
1229
1230 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1231 if (pThis->svga.uBpp != u32)
1232 {
1233 if (pThis->svga.fEnabled)
1234 {
1235#ifdef IN_RING3
1236 pThis->svga.uBpp = u32;
1237 rc = vmsvgaChangeMode(pThis);
1238 AssertRCReturn(rc, rc);
1239#else
1240 rc = VINF_IOM_R3_IOPORT_WRITE;
1241#endif
1242 }
1243 else
1244 pThis->svga.uBpp = u32;
1245 }
1246 /* else: nop */
1247 break;
1248
1249 case SVGA_REG_PSEUDOCOLOR:
1250 break;
1251
1252 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1253#ifdef IN_RING3
1254 pThis->svga.fConfigured = u32;
1255 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1256 if (!pThis->svga.fConfigured)
1257 {
1258 pThis->svga.fTraces = true;
1259 }
1260 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1261#else
1262 rc = VINF_IOM_R3_IOPORT_WRITE;
1263#endif
1264 break;
1265
1266 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1267 if ( pThis->svga.fEnabled
1268 && pThis->svga.fConfigured)
1269 {
1270#if defined(IN_RING3) || defined(IN_RING0)
1271 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1272 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1273 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1274 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1275
1276 /* Kick the FIFO thread to start processing commands again. */
1277 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1278#else
1279 rc = VINF_IOM_R3_IOPORT_WRITE;
1280#endif
1281 }
1282 /* else nothing to do. */
1283 else
1284 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1285
1286 break;
1287
1288 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1289 break;
1290
1291 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1292 pThis->svga.u32GuestId = u32;
1293 break;
1294
1295 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1296 pThis->svga.u32PitchLock = u32;
1297 break;
1298
1299 case SVGA_REG_IRQMASK: /* Interrupt mask */
1300 pThis->svga.u32IrqMask = u32;
1301
1302 /* Irq pending after the above change? */
1303 if (pThis->svga.u32IrqStatus & u32)
1304 {
1305 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1306 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1307 }
1308 else
1309 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1310 break;
1311
1312 /* Mouse cursor support */
1313 case SVGA_REG_CURSOR_ID:
1314 case SVGA_REG_CURSOR_X:
1315 case SVGA_REG_CURSOR_Y:
1316 case SVGA_REG_CURSOR_ON:
1317 break;
1318
1319 /* Legacy multi-monitor support */
1320 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1321 break;
1322 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1323 break;
1324 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1325 break;
1326 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1327 break;
1328 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1329 break;
1330 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1331 break;
1332 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1333 break;
1334#ifdef VBOX_WITH_VMSVGA3D
1335 /* See "Guest memory regions" below. */
1336 case SVGA_REG_GMR_ID:
1337 pThis->svga.u32CurrentGMRId = u32;
1338 break;
1339
1340 case SVGA_REG_GMR_DESCRIPTOR:
1341# ifndef IN_RING3
1342 rc = VINF_IOM_R3_IOPORT_WRITE;
1343 break;
1344# else /* IN_RING3 */
1345 {
1346 SVGAGuestMemDescriptor desc;
1347 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1348 RTGCPHYS GCPhysBase = GCPhys;
1349 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1350 uint32_t cDescriptorsAllocated = 16;
1351 uint32_t iDescriptor = 0;
1352
1353 /* Validate current GMR id. */
1354 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1355
1356 /* Free the old GMR if present. */
1357 vmsvgaGMRFree(pThis, idGMR);
1358
1359 /* Just undefine the GMR? */
1360 if (GCPhys == 0)
1361 break;
1362
1363 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1364 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1365
1366 /* Never cross a page boundary automatically. */
1367 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1368 {
1369 /* Read descriptor. */
1370 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1371 AssertRCBreak(rc);
1372
1373 if ( desc.ppn == 0
1374 && desc.numPages == 0)
1375 break; /* terminator */
1376
1377 if ( desc.ppn != 0
1378 && desc.numPages == 0)
1379 {
1380 /* Pointer to the next physical page of descriptors. */
1381 GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1382 }
1383 else
1384 {
1385 if (iDescriptor == cDescriptorsAllocated)
1386 {
1387 cDescriptorsAllocated += 16;
1388 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1389 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1390 }
1391
1392 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1393 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1394 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1395
1396 /* Continue with the next descriptor. */
1397 GCPhys += sizeof(desc);
1398 }
1399 }
1400 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1401 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1402
1403 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1404 {
1405 AssertFailed();
1406 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1407 pSVGAState->aGMR[idGMR].paDesc = NULL;
1408 }
1409 AssertRC(rc);
1410 break;
1411 }
1412# endif /* IN_RING3 */
1413#endif // VBOX_WITH_VMSVGA3D
1414
1415 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1416 if (pThis->svga.fTraces == u32)
1417 break; /* nothing to do */
1418
1419#ifdef IN_RING3
1420 vmsvgaSetTraces(pThis, !!u32);
1421#else
1422 rc = VINF_IOM_R3_IOPORT_WRITE;
1423#endif
1424 break;
1425
1426 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1427 break;
1428
1429 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1430 break;
1431 /* Next 768 (== 256*3) registers exist for colormap */
1432
1433 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1434 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1435 break;
1436
1437 case SVGA_REG_FB_START:
1438 case SVGA_REG_MEM_START:
1439 case SVGA_REG_HOST_BITS_PER_PIXEL:
1440 case SVGA_REG_MAX_WIDTH:
1441 case SVGA_REG_MAX_HEIGHT:
1442 case SVGA_REG_VRAM_SIZE:
1443 case SVGA_REG_FB_SIZE:
1444 case SVGA_REG_CAPABILITIES:
1445 case SVGA_REG_MEM_SIZE:
1446 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1447 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1448 case SVGA_REG_BYTES_PER_LINE:
1449 case SVGA_REG_FB_OFFSET:
1450 case SVGA_REG_RED_MASK:
1451 case SVGA_REG_GREEN_MASK:
1452 case SVGA_REG_BLUE_MASK:
1453 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1454 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1455 case SVGA_REG_GMR_MAX_IDS:
1456 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1457 /* Read only - ignore. */
1458 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1459 break;
1460
1461 default:
1462 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1463 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1464 {
1465 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1466 }
1467 break;
1468 }
1469 return rc;
1470}
1471
1472/**
1473 * Port I/O Handler for IN operations.
1474 *
1475 * @returns VINF_SUCCESS or VINF_EM_*.
1476 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1477 *
1478 * @param pDevIns The device instance.
1479 * @param pvUser User argument.
1480 * @param uPort Port number used for the IN operation.
1481 * @param pu32 Where to store the result. This is always a 32-bit
1482 * variable regardless of what @a cb might say.
1483 * @param cb Number of bytes read.
1484 */
1485PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1486{
1487 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1488 RT_NOREF_PV(pvUser);
1489
1490 /* Ignore non-dword accesses. */
1491 if (cb != 4)
1492 {
1493 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1494 *pu32 = UINT32_MAX;
1495 return VINF_SUCCESS;
1496 }
1497
1498 switch (Port - pThis->svga.BasePort)
1499 {
1500 case SVGA_INDEX_PORT:
1501 *pu32 = pThis->svga.u32IndexReg;
1502 break;
1503
1504 case SVGA_VALUE_PORT:
1505 return vmsvgaReadPort(pThis, pu32);
1506
1507 case SVGA_BIOS_PORT:
1508 Log(("Ignoring BIOS port read\n"));
1509 *pu32 = 0;
1510 break;
1511
1512 case SVGA_IRQSTATUS_PORT:
1513 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1514 *pu32 = pThis->svga.u32IrqStatus;
1515 break;
1516 }
1517
1518 return VINF_SUCCESS;
1519}
1520
1521/**
1522 * Port I/O Handler for OUT operations.
1523 *
1524 * @returns VINF_SUCCESS or VINF_EM_*.
1525 *
1526 * @param pDevIns The device instance.
1527 * @param pvUser User argument.
1528 * @param uPort Port number used for the OUT operation.
1529 * @param u32 The value to output.
1530 * @param cb The value size in bytes.
1531 */
1532PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1533{
1534 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1535 RT_NOREF_PV(pvUser);
1536
1537 /* Ignore non-dword accesses. */
1538 if (cb != 4)
1539 {
1540 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1541 return VINF_SUCCESS;
1542 }
1543
1544 switch (Port - pThis->svga.BasePort)
1545 {
1546 case SVGA_INDEX_PORT:
1547 pThis->svga.u32IndexReg = u32;
1548 break;
1549
1550 case SVGA_VALUE_PORT:
1551 return vmsvgaWritePort(pThis, u32);
1552
1553 case SVGA_BIOS_PORT:
1554 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1555 break;
1556
1557 case SVGA_IRQSTATUS_PORT:
1558 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1559 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1560 /* Clear the irq in case all events have been cleared. */
1561 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1562 {
1563 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1564 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1565 }
1566 break;
1567 }
1568 return VINF_SUCCESS;
1569}
1570
1571#ifdef DEBUG_FIFO_ACCESS
1572
1573# ifdef IN_RING3
1574/**
1575 * Handle LFB access.
1576 * @returns VBox status code.
1577 * @param pVM VM handle.
1578 * @param pThis VGA device instance data.
1579 * @param GCPhys The access physical address.
1580 * @param fWriteAccess Read or write access
1581 */
1582static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1583{
1584 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1585 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1586
1587 switch (GCPhysOffset >> 2)
1588 {
1589 case SVGA_FIFO_MIN:
1590 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1591 break;
1592 case SVGA_FIFO_MAX:
1593 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1594 break;
1595 case SVGA_FIFO_NEXT_CMD:
1596 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1597 break;
1598 case SVGA_FIFO_STOP:
1599 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1600 break;
1601 case SVGA_FIFO_CAPABILITIES:
1602 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1603 break;
1604 case SVGA_FIFO_FLAGS:
1605 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1606 break;
1607 case SVGA_FIFO_FENCE:
1608 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1609 break;
1610 case SVGA_FIFO_3D_HWVERSION:
1611 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1612 break;
1613 case SVGA_FIFO_PITCHLOCK:
1614 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1615 break;
1616 case SVGA_FIFO_CURSOR_ON:
1617 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1618 break;
1619 case SVGA_FIFO_CURSOR_X:
1620 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1621 break;
1622 case SVGA_FIFO_CURSOR_Y:
1623 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1624 break;
1625 case SVGA_FIFO_CURSOR_COUNT:
1626 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1627 break;
1628 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1629 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1630 break;
1631 case SVGA_FIFO_RESERVED:
1632 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1633 break;
1634 case SVGA_FIFO_CURSOR_SCREEN_ID:
1635 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1636 break;
1637 case SVGA_FIFO_DEAD:
1638 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1639 break;
1640 case SVGA_FIFO_3D_HWVERSION_REVISED:
1641 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1642 break;
1643 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1644 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1645 break;
1646 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1647 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1648 break;
1649 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1650 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1651 break;
1652 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1653 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1654 break;
1655 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1656 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1657 break;
1658 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1659 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1660 break;
1661 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1662 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1663 break;
1664 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1665 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1666 break;
1667 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1668 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1669 break;
1670 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1671 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1672 break;
1673 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1674 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1675 break;
1676 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1677 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1678 break;
1679 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1680 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1681 break;
1682 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1683 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1684 break;
1685 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1686 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1687 break;
1688 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1689 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1690 break;
1691 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1692 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1693 break;
1694 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1695 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1696 break;
1697 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1698 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1699 break;
1700 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1701 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1702 break;
1703 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1704 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1705 break;
1706 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1707 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1708 break;
1709 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1710 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1711 break;
1712 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1713 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1714 break;
1715 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1716 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1717 break;
1718 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1719 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1720 break;
1721 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1722 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1723 break;
1724 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1725 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1726 break;
1727 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1728 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1729 break;
1730 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1731 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1732 break;
1733 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1734 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1735 break;
1736 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1737 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1738 break;
1739 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1740 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1741 break;
1742 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1743 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1744 break;
1745 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1746 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1747 break;
1748 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1749 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1750 break;
1751 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1752 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1753 break;
1754 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1755 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1756 break;
1757 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1758 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1759 break;
1760 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1761 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1762 break;
1763 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1764 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1765 break;
1766 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1767 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1768 break;
1769 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1770 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1771 break;
1772 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1773 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1774 break;
1775 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1776 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1777 break;
1778 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1779 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1780 break;
1781 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1782 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1783 break;
1784 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1785 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1786 break;
1787 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1788 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1789 break;
1790 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1791 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1792 break;
1793 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1794 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1795 break;
1796 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1797 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1798 break;
1799 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1800 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1801 break;
1802 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1803 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1804 break;
1805 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1806 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1807 break;
1808 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1809 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1810 break;
1811 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1812 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1813 break;
1814 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1815 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1816 break;
1817 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1818 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1819 break;
1820 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1821 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1822 break;
1823 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1824 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1825 break;
1826 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1827 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1828 break;
1829 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1830 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1831 break;
1832 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1833 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1834 break;
1835 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1836 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1837 break;
1838 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1839 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1840 break;
1841 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1842 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1843 break;
1844 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1845 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1846 break;
1847 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1848 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1849 break;
1850 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1851 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1852 break;
1853 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1854 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1855 break;
1856 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1857 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1858 break;
1859 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1860 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1861 break;
1862 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1863 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1864 break;
1865 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1866 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1867 break;
1868 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1869 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1870 break;
1871 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1872 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1873 break;
1874 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1875 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1876 break;
1877 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1878 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1879 break;
1880 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1881 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1882 break;
1883 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1884 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1885 break;
1886 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1887 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1888 break;
1889 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1890 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1891 break;
1892 case SVGA_FIFO_3D_CAPS_LAST:
1893 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1894 break;
1895 case SVGA_FIFO_GUEST_3D_HWVERSION:
1896 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1897 break;
1898 case SVGA_FIFO_FENCE_GOAL:
1899 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1900 break;
1901 case SVGA_FIFO_BUSY:
1902 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1903 break;
1904 default:
1905 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1906 break;
1907 }
1908
1909 return VINF_EM_RAW_EMULATE_INSTR;
1910}
1911
1912/**
1913 * HC access handler for the FIFO.
1914 *
1915 * @returns VINF_SUCCESS if the handler have carried out the operation.
1916 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1917 * @param pVM VM Handle.
1918 * @param pVCpu The cross context CPU structure for the calling EMT.
1919 * @param GCPhys The physical address the guest is writing to.
1920 * @param pvPhys The HC mapping of that address.
1921 * @param pvBuf What the guest is reading/writing.
1922 * @param cbBuf How much it's reading/writing.
1923 * @param enmAccessType The access type.
1924 * @param enmOrigin Who is making the access.
1925 * @param pvUser User argument.
1926 */
1927static DECLCALLBACK(VBOXSTRICTRC)
1928vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1929 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1930{
1931 PVGASTATE pThis = (PVGASTATE)pvUser;
1932 int rc;
1933 Assert(pThis);
1934 Assert(GCPhys >= pThis->GCPhysVRAM);
1935 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1936
1937 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1938 if (RT_SUCCESS(rc))
1939 return VINF_PGM_HANDLER_DO_DEFAULT;
1940 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1941 return rc;
1942}
1943
1944# endif /* IN_RING3 */
1945#endif /* DEBUG_FIFO_ACCESS */
1946
1947#ifdef DEBUG_GMR_ACCESS
1948/**
1949 * HC access handler for the FIFO.
1950 *
1951 * @returns VINF_SUCCESS if the handler have carried out the operation.
1952 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1953 * @param pVM VM Handle.
1954 * @param pVCpu The cross context CPU structure for the calling EMT.
1955 * @param GCPhys The physical address the guest is writing to.
1956 * @param pvPhys The HC mapping of that address.
1957 * @param pvBuf What the guest is reading/writing.
1958 * @param cbBuf How much it's reading/writing.
1959 * @param enmAccessType The access type.
1960 * @param enmOrigin Who is making the access.
1961 * @param pvUser User argument.
1962 */
1963static DECLCALLBACK(VBOXSTRICTRC)
1964vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1965 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1966{
1967 PVGASTATE pThis = (PVGASTATE)pvUser;
1968 Assert(pThis);
1969 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1970 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1971
1972 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1973
1974 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1975 {
1976 PGMR pGMR = &pSVGAState->aGMR[i];
1977
1978 if (pGMR->numDescriptors)
1979 {
1980 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1981 {
1982 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1983 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1984 {
1985 /*
1986 * Turn off the write handler for this particular page and make it R/W.
1987 * Then return telling the caller to restart the guest instruction.
1988 */
1989 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1990 goto end;
1991 }
1992 }
1993 }
1994 }
1995end:
1996 return VINF_PGM_HANDLER_DO_DEFAULT;
1997}
1998
1999# ifdef IN_RING3
2000
2001/* Callback handler for VMR3ReqCallWait */
2002static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2003{
2004 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2005 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2006 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2007 int rc;
2008
2009 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2010 {
2011 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2012 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2013 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2014 AssertRC(rc);
2015 }
2016 return VINF_SUCCESS;
2017}
2018
2019/* Callback handler for VMR3ReqCallWait */
2020static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2021{
2022 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2023 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2024 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2025
2026 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2027 {
2028 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2029 AssertRC(rc);
2030 }
2031 return VINF_SUCCESS;
2032}
2033
2034/* Callback handler for VMR3ReqCallWait */
2035static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2036{
2037 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2038
2039 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2040 {
2041 PGMR pGMR = &pSVGAState->aGMR[i];
2042
2043 if (pGMR->numDescriptors)
2044 {
2045 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2046 {
2047 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2048 AssertRC(rc);
2049 }
2050 }
2051 }
2052 return VINF_SUCCESS;
2053}
2054
2055# endif /* IN_RING3 */
2056#endif /* DEBUG_GMR_ACCESS */
2057
2058/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2059
2060#ifdef IN_RING3
2061
2062/**
2063 * Worker for vmsvgaR3FifoThread that handles an external command.
2064 *
2065 * @param pThis VGA device instance data.
2066 */
2067static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2068{
2069 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2070 switch (pThis->svga.u8FIFOExtCommand)
2071 {
2072 case VMSVGA_FIFO_EXTCMD_RESET:
2073 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2074 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2075# ifdef VBOX_WITH_VMSVGA3D
2076 if (pThis->svga.f3DEnabled)
2077 {
2078 /* The 3d subsystem must be reset from the fifo thread. */
2079 vmsvga3dReset(pThis);
2080 }
2081# endif
2082 break;
2083
2084 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2085 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2086 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2087# ifdef VBOX_WITH_VMSVGA3D
2088 if (pThis->svga.f3DEnabled)
2089 {
2090 /* The 3d subsystem must be shut down from the fifo thread. */
2091 vmsvga3dTerminate(pThis);
2092 }
2093# endif
2094 break;
2095
2096 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2097 {
2098 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2099# ifdef VBOX_WITH_VMSVGA3D
2100 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2101 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2102 vmsvga3dSaveExec(pThis, pSSM);
2103# endif
2104 break;
2105 }
2106
2107 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2108 {
2109 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2110# ifdef VBOX_WITH_VMSVGA3D
2111 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2112 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2113 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2114# endif
2115 break;
2116 }
2117
2118 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2119 {
2120# ifdef VBOX_WITH_VMSVGA3D
2121 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2122 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2123 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2124# endif
2125 break;
2126 }
2127
2128
2129 default:
2130 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2131 break;
2132 }
2133
2134 /*
2135 * Signal the end of the external command.
2136 */
2137 pThis->svga.pvFIFOExtCmdParam = NULL;
2138 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2139 ASMMemoryFence(); /* paranoia^2 */
2140 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2141 AssertLogRelRC(rc);
2142}
2143
2144/**
2145 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2146 * doing a job on the FIFO thread (even when it's officially suspended).
2147 *
2148 * @returns VBox status code (fully asserted).
2149 * @param pThis VGA device instance data.
2150 * @param uExtCmd The command to execute on the FIFO thread.
2151 * @param pvParam Pointer to command parameters.
2152 * @param cMsWait The time to wait for the command, given in
2153 * milliseconds.
2154 */
2155static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2156{
2157 Assert(cMsWait >= RT_MS_1SEC * 5);
2158 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2159 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2160
2161 int rc;
2162 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2163 PDMTHREADSTATE enmState = pThread->enmState;
2164 if (enmState == PDMTHREADSTATE_SUSPENDED)
2165 {
2166 /*
2167 * The thread is suspended, we have to temporarily wake it up so it can
2168 * perform the task.
2169 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2170 */
2171 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2172 /* Post the request. */
2173 pThis->svga.fFifoExtCommandWakeup = true;
2174 pThis->svga.pvFIFOExtCmdParam = pvParam;
2175 pThis->svga.u8FIFOExtCommand = uExtCmd;
2176 ASMMemoryFence(); /* paranoia^3 */
2177
2178 /* Resume the thread. */
2179 rc = PDMR3ThreadResume(pThread);
2180 AssertLogRelRC(rc);
2181 if (RT_SUCCESS(rc))
2182 {
2183 /* Wait. Take care in case the semaphore was already posted (same as below). */
2184 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2185 if ( rc == VINF_SUCCESS
2186 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2187 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2188 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2189 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2190
2191 /* suspend the thread */
2192 pThis->svga.fFifoExtCommandWakeup = false;
2193 int rc2 = PDMR3ThreadSuspend(pThread);
2194 AssertLogRelRC(rc2);
2195 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2196 rc = rc2;
2197 }
2198 pThis->svga.fFifoExtCommandWakeup = false;
2199 pThis->svga.pvFIFOExtCmdParam = NULL;
2200 }
2201 else if (enmState == PDMTHREADSTATE_RUNNING)
2202 {
2203 /*
2204 * The thread is running, should only happen during reset and vmsvga3dsfc.
2205 * We ASSUME not racing code here, both wrt thread state and ext commands.
2206 */
2207 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2208 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2209
2210 /* Post the request. */
2211 pThis->svga.pvFIFOExtCmdParam = pvParam;
2212 pThis->svga.u8FIFOExtCommand = uExtCmd;
2213 ASMMemoryFence(); /* paranoia^2 */
2214 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2215 AssertLogRelRC(rc);
2216
2217 /* Wait. Take care in case the semaphore was already posted (same as above). */
2218 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2219 if ( rc == VINF_SUCCESS
2220 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2221 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2222 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2223 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2224
2225 pThis->svga.pvFIFOExtCmdParam = NULL;
2226 }
2227 else
2228 {
2229 /*
2230 * Something is wrong with the thread!
2231 */
2232 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2233 rc = VERR_INVALID_STATE;
2234 }
2235 return rc;
2236}
2237
2238
2239/**
2240 * Marks the FIFO non-busy, notifying any waiting EMTs.
2241 *
2242 * @param pThis The VGA state.
2243 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2244 * @param offFifoMin The start byte offset of the command FIFO.
2245 */
2246static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2247{
2248 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2249 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2250 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2251
2252 /* Wake up any waiting EMTs. */
2253 if (pSVGAState->cBusyDelayedEmts > 0)
2254 {
2255#ifdef VMSVGA_USE_EMT_HALT_CODE
2256 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2257 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2258 if (idCpu != NIL_VMCPUID)
2259 {
2260 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2261 while (idCpu-- > 0)
2262 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2263 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2264 }
2265#else
2266 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2267 AssertRC(rc2);
2268#endif
2269 }
2270}
2271
2272/**
2273 * Reads (more) payload into the command buffer.
2274 *
2275 * @returns pbBounceBuf on success
2276 * @retval (void *)1 if the thread was requested to stop.
2277 * @retval NULL on FIFO error.
2278 *
2279 * @param cbPayloadReq The number of bytes of payload requested.
2280 * @param pFIFO The FIFO.
2281 * @param offCurrentCmd The FIFO byte offset of the current command.
2282 * @param offFifoMin The start byte offset of the command FIFO.
2283 * @param offFifoMax The end byte offset of the command FIFO.
2284 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2285 * always sufficient size.
2286 * @param pcbAlreadyRead How much payload we've already read into the bounce
2287 * buffer. (We will NEVER re-read anything.)
2288 * @param pThread The calling PDM thread handle.
2289 * @param pThis The VGA state.
2290 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2291 * statistics collection.
2292 */
2293static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2294 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2295 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2296 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2297{
2298 Assert(pbBounceBuf);
2299 Assert(pcbAlreadyRead);
2300 Assert(offFifoMin < offFifoMax);
2301 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2302 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2303
2304 /*
2305 * Check if the requested payload size has already been satisfied .
2306 * .
2307 * When called to read more, the caller is responsible for making sure the .
2308 * new command size (cbRequsted) never is smaller than what has already .
2309 * been read.
2310 */
2311 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2312 if (cbPayloadReq <= cbAlreadyRead)
2313 {
2314 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2315 return pbBounceBuf;
2316 }
2317
2318 /*
2319 * Commands bigger than the fifo buffer are invalid.
2320 */
2321 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2322 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2323 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2324 NULL);
2325
2326 /*
2327 * Move offCurrentCmd past the command dword.
2328 */
2329 offCurrentCmd += sizeof(uint32_t);
2330 if (offCurrentCmd >= offFifoMax)
2331 offCurrentCmd = offFifoMin;
2332
2333 /*
2334 * Do we have sufficient payload data available already?
2335 */
2336 uint32_t cbAfter, cbBefore;
2337 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2338 if (offNextCmd > offCurrentCmd)
2339 {
2340 if (RT_LIKELY(offNextCmd < offFifoMax))
2341 cbAfter = offNextCmd - offCurrentCmd;
2342 else
2343 {
2344 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2345 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2346 offNextCmd, offFifoMin, offFifoMax));
2347 cbAfter = offFifoMax - offCurrentCmd;
2348 }
2349 cbBefore = 0;
2350 }
2351 else
2352 {
2353 cbAfter = offFifoMax - offCurrentCmd;
2354 if (offNextCmd >= offFifoMin)
2355 cbBefore = offNextCmd - offFifoMin;
2356 else
2357 {
2358 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2359 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2360 offNextCmd, offFifoMin, offFifoMax));
2361 cbBefore = 0;
2362 }
2363 }
2364 if (cbAfter + cbBefore < cbPayloadReq)
2365 {
2366 /*
2367 * Insufficient, must wait for it to arrive.
2368 */
2369/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2370 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2371 for (uint32_t i = 0;; i++)
2372 {
2373 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2374 {
2375 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2376 return (void *)(uintptr_t)1;
2377 }
2378 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2379 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2380
2381 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2382
2383 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2384 if (offNextCmd > offCurrentCmd)
2385 {
2386 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2387 cbBefore = 0;
2388 }
2389 else
2390 {
2391 cbAfter = offFifoMax - offCurrentCmd;
2392 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2393 }
2394
2395 if (cbAfter + cbBefore >= cbPayloadReq)
2396 break;
2397 }
2398 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2399 }
2400
2401 /*
2402 * Copy out the memory and update what pcbAlreadyRead points to.
2403 */
2404 if (cbAfter >= cbPayloadReq)
2405 memcpy(pbBounceBuf + cbAlreadyRead,
2406 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2407 cbPayloadReq - cbAlreadyRead);
2408 else
2409 {
2410 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2411 if (cbAlreadyRead < cbAfter)
2412 {
2413 memcpy(pbBounceBuf + cbAlreadyRead,
2414 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2415 cbAfter - cbAlreadyRead);
2416 cbAlreadyRead = cbAfter;
2417 }
2418 memcpy(pbBounceBuf + cbAlreadyRead,
2419 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2420 cbPayloadReq - cbAlreadyRead);
2421 }
2422 *pcbAlreadyRead = cbPayloadReq;
2423 return pbBounceBuf;
2424}
2425
2426/* The async FIFO handling thread. */
2427static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2428{
2429 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2430 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2431 int rc;
2432
2433 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2434 return VINF_SUCCESS;
2435
2436 /*
2437 * Special mode where we only execute an external command and the go back
2438 * to being suspended. Currently, all ext cmds ends up here, with the reset
2439 * one also being eligble for runtime execution further down as well.
2440 */
2441 if (pThis->svga.fFifoExtCommandWakeup)
2442 {
2443 vmsvgaR3FifoHandleExtCmd(pThis);
2444 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2445 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2446 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2447 else
2448 vmsvgaR3FifoHandleExtCmd(pThis);
2449 return VINF_SUCCESS;
2450 }
2451
2452
2453 /*
2454 * Signal the semaphore to make sure we don't wait for 250ms after a
2455 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2456 */
2457 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2458
2459 /*
2460 * Allocate a bounce buffer for command we get from the FIFO.
2461 * (All code must return via the end of the function to free this buffer.)
2462 */
2463 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2464 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2465
2466 /*
2467 * Polling/sleep interval config.
2468 *
2469 * We wait for an a short interval if the guest has recently given us work
2470 * to do, but the interval increases the longer we're kept idle. With the
2471 * current parameters we'll be at a 64ms poll interval after 1 idle second,
2472 * at 90ms after 2 seconds, and reach the max 250ms interval after about
2473 * 16 seconds.
2474 */
2475 RTMSINTERVAL const cMsMinSleep = 16;
2476 RTMSINTERVAL const cMsIncSleep = 2;
2477 RTMSINTERVAL const cMsMaxSleep = 250;
2478 RTMSINTERVAL cMsSleep = cMsMaxSleep;
2479
2480 /*
2481 * The FIFO loop.
2482 */
2483 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2484 bool fBadOrDisabledFifo = false;
2485 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2486 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2487 {
2488# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2489 /*
2490 * Should service the run loop every so often.
2491 */
2492 if (pThis->svga.f3DEnabled)
2493 vmsvga3dCocoaServiceRunLoop();
2494# endif
2495
2496 /*
2497 * Unless there's already work pending, go to sleep for a short while.
2498 * (See polling/sleep interval config above.)
2499 */
2500 if ( fBadOrDisabledFifo
2501 || pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2502 {
2503 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
2504 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2505 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2506 {
2507 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2508 break;
2509 }
2510 }
2511 else
2512 rc = VINF_SUCCESS;
2513 fBadOrDisabledFifo = false;
2514 if (rc == VERR_TIMEOUT)
2515 {
2516 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2517 {
2518 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
2519 continue;
2520 }
2521 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2522
2523 Log(("vmsvgaFIFOLoop: timeout\n"));
2524 }
2525 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2526 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2527 cMsSleep = cMsMinSleep;
2528
2529 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2530 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2531 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2532
2533 /*
2534 * Handle external commands (currently only reset).
2535 */
2536 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2537 {
2538 vmsvgaR3FifoHandleExtCmd(pThis);
2539 continue;
2540 }
2541
2542 /*
2543 * The device must be enabled and configured.
2544 */
2545 if ( !pThis->svga.fEnabled
2546 || !pThis->svga.fConfigured)
2547 {
2548 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2549 fBadOrDisabledFifo = true;
2550 continue;
2551 }
2552
2553 /*
2554 * Get and check the min/max values. We ASSUME that they will remain
2555 * unchanged while we process requests. A further ASSUMPTION is that
2556 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2557 * we don't read it back while in the loop.
2558 */
2559 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2560 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2561 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2562 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2563 || offFifoMax <= offFifoMin
2564 || offFifoMax > VMSVGA_FIFO_SIZE
2565 || (offFifoMax & 3) != 0
2566 || (offFifoMin & 3) != 0
2567 || offCurrentCmd < offFifoMin
2568 || offCurrentCmd > offFifoMax))
2569 {
2570 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2571 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2572 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2573 fBadOrDisabledFifo = true;
2574 continue;
2575 }
2576 if (RT_UNLIKELY(offCurrentCmd & 3))
2577 {
2578 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2579 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2580 offCurrentCmd = ~UINT32_C(3);
2581 }
2582
2583/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
2584 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2585 *
2586 * Will break out of the switch on failure.
2587 * Will restart and quit the loop if the thread was requested to stop.
2588 *
2589 * @param a_PtrVar Request variable pointer.
2590 * @param a_Type Request typedef (not pointer) for casting.
2591 * @param a_cbPayloadReq How much payload to fetch.
2592 * @remarks Accesses a bunch of variables in the current scope!
2593 */
2594# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2595 if (1) { \
2596 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2597 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2598 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2599 } else do {} while (0)
2600/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
2601 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2602 * buffer after figuring out the actual command size.
2603 *
2604 * Will break out of the switch on failure.
2605 *
2606 * @param a_PtrVar Request variable pointer.
2607 * @param a_Type Request typedef (not pointer) for casting.
2608 * @param a_cbPayloadReq How much payload to fetch.
2609 * @remarks Accesses a bunch of variables in the current scope!
2610 */
2611# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2612 if (1) { \
2613 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2614 } else do {} while (0)
2615
2616 /*
2617 * Mark the FIFO as busy.
2618 */
2619 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2620 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2621 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2622
2623 /*
2624 * Execute all queued FIFO commands.
2625 * Quit if pending external command or changes in the thread state.
2626 */
2627 bool fDone = false;
2628 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2629 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2630 {
2631 uint32_t cbPayload = 0;
2632 uint32_t u32IrqStatus = 0;
2633 bool fTriggerIrq = false;
2634
2635 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2636
2637 /* First check any pending actions. */
2638 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2639# ifdef VBOX_WITH_VMSVGA3D
2640 vmsvga3dChangeMode(pThis);
2641# else
2642 {/*nothing*/}
2643# endif
2644 /* Check for pending external commands (reset). */
2645 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2646 break;
2647
2648 /*
2649 * Process the command.
2650 */
2651 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2652 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2653 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2654 switch (enmCmdId)
2655 {
2656 case SVGA_CMD_INVALID_CMD:
2657 /* Nothing to do. */
2658 break;
2659
2660 case SVGA_CMD_FENCE:
2661 {
2662 SVGAFifoCmdFence *pCmdFence;
2663 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2664 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2665 {
2666 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2667 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2668
2669 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2670 {
2671 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2672 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2673 }
2674 else
2675 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2676 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2677 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2678 {
2679 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2680 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2681 }
2682 }
2683 else
2684 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2685 break;
2686 }
2687 case SVGA_CMD_UPDATE:
2688 case SVGA_CMD_UPDATE_VERBOSE:
2689 {
2690 SVGAFifoCmdUpdate *pUpdate;
2691 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2692 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2693 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2694 break;
2695 }
2696
2697 case SVGA_CMD_DEFINE_CURSOR:
2698 {
2699 /* Followed by bitmap data. */
2700 SVGAFifoCmdDefineCursor *pCursor;
2701 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2702 AssertFailed(); /** @todo implement when necessary. */
2703 break;
2704 }
2705
2706 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2707 {
2708 /* Followed by bitmap data. */
2709 uint32_t cbCursorShape, cbAndMask;
2710 uint8_t *pCursorCopy;
2711 uint32_t cbCmd;
2712
2713 SVGAFifoCmdDefineAlphaCursor *pCursor;
2714 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2715
2716 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2717
2718 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2719 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2720
2721 /* Refetch the bitmap data as well. */
2722 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2723 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2724 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2725
2726 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2727 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2728 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2729 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2730
2731 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2732 AssertBreak(pCursorCopy);
2733
2734 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2735
2736 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2737 memset(pCursorCopy, 0xff, cbAndMask);
2738 /* Colour data */
2739 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2740
2741 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2742 true,
2743 true,
2744 pCursor->hotspotX,
2745 pCursor->hotspotY,
2746 pCursor->width,
2747 pCursor->height,
2748 pCursorCopy);
2749 AssertRC(rc);
2750
2751 if (pSVGAState->Cursor.fActive)
2752 RTMemFree(pSVGAState->Cursor.pData);
2753
2754 pSVGAState->Cursor.fActive = true;
2755 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2756 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2757 pSVGAState->Cursor.width = pCursor->width;
2758 pSVGAState->Cursor.height = pCursor->height;
2759 pSVGAState->Cursor.cbData = cbCursorShape;
2760 pSVGAState->Cursor.pData = pCursorCopy;
2761 break;
2762 }
2763
2764 case SVGA_CMD_ESCAPE:
2765 {
2766 /* Followed by nsize bytes of data. */
2767 SVGAFifoCmdEscape *pEscape;
2768 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2769
2770 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2771 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2772 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2773 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2774
2775 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2776 {
2777 AssertBreak(pEscape->size >= sizeof(uint32_t));
2778 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2779 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2780
2781 switch (cmd)
2782 {
2783 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2784 {
2785 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2786 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2787 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2788
2789 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2790 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2791 {
2792 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2793 }
2794 break;
2795 }
2796
2797 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2798 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2799 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2800 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2801 break;
2802 }
2803 }
2804 else
2805 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2806
2807 break;
2808 }
2809# ifdef VBOX_WITH_VMSVGA3D
2810 case SVGA_CMD_DEFINE_GMR2:
2811 {
2812 SVGAFifoCmdDefineGMR2 *pCmd;
2813 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2814 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2815
2816 /* Validate current GMR id. */
2817 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2818 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2819
2820 if (!pCmd->numPages)
2821 {
2822 vmsvgaGMRFree(pThis, pCmd->gmrId);
2823 }
2824 else
2825 {
2826 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2827 pGMR->cMaxPages = pCmd->numPages;
2828 }
2829 /* everything done in remap */
2830 break;
2831 }
2832
2833 case SVGA_CMD_REMAP_GMR2:
2834 {
2835 /* Followed by page descriptors or guest ptr. */
2836 SVGAFifoCmdRemapGMR2 *pCmd;
2837 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2838 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2839 uint32_t cbCmd;
2840 uint64_t *paNewPage64 = NULL;
2841
2842 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2843 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2844
2845 /* Calculate the size of what comes after next and fetch it. */
2846 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2847 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2848 cbCmd += sizeof(SVGAGuestPtr);
2849 else
2850 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2851 {
2852 cbCmd += cbPageDesc;
2853 pCmd->numPages = 1;
2854 }
2855 else
2856 {
2857 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2858 cbCmd += cbPageDesc * pCmd->numPages;
2859 }
2860 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2861
2862 /* Validate current GMR id. */
2863 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2864 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2865 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2866 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2867
2868 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2869 if (pGMR->paDesc)
2870 {
2871 uint32_t idxPage = 0;
2872 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2873 AssertBreak(paNewPage64);
2874
2875 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2876 {
2877 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2878 {
2879 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2880 }
2881 }
2882 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2883 }
2884
2885 /* Free the old GMR if present. */
2886 if (pGMR->paDesc)
2887 RTMemFree(pGMR->paDesc);
2888
2889 /* Allocate the maximum amount possible (everything non-continuous) */
2890 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2891 AssertBreak(pGMR->paDesc);
2892
2893 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2894 {
2895 /** @todo */
2896 AssertFailed();
2897 }
2898 else
2899 {
2900 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2901 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2902 uint32_t iDescriptor = 0;
2903 RTGCPHYS GCPhys;
2904 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2905 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2906
2907 if (paNewPage64)
2908 {
2909 /* Overwrite the old page array with the new page values. */
2910 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2911 {
2912 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2913 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2914 else
2915 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2916 }
2917 /* Use the updated page array instead of the command data. */
2918 fGCPhys64 = true;
2919 pPage64 = paNewPage64;
2920 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2921 }
2922
2923 if (fGCPhys64)
2924 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2925 else
2926 GCPhys = (RTGCPHYS)pPage32[0] << PAGE_SHIFT;
2927
2928 pGMR->paDesc[0].GCPhys = GCPhys;
2929 pGMR->paDesc[0].numPages = 1;
2930 pGMR->cbTotal = PAGE_SIZE;
2931
2932 for (uint32_t i = 1; i < pCmd->numPages; i++)
2933 {
2934 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2935 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2936 else
2937 GCPhys = (RTGCPHYS)pPage32[i] << PAGE_SHIFT;
2938
2939 /* Continuous physical memory? */
2940 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2941 {
2942 Assert(pGMR->paDesc[iDescriptor].numPages);
2943 pGMR->paDesc[iDescriptor].numPages++;
2944 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2945 }
2946 else
2947 {
2948 iDescriptor++;
2949 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2950 pGMR->paDesc[iDescriptor].numPages = 1;
2951 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2952 }
2953
2954 pGMR->cbTotal += PAGE_SIZE;
2955 }
2956 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2957 pGMR->numDescriptors = iDescriptor + 1;
2958 }
2959
2960 if (paNewPage64)
2961 RTMemFree(paNewPage64);
2962
2963# ifdef DEBUG_GMR_ACCESS
2964 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2965# endif
2966 break;
2967 }
2968# endif // VBOX_WITH_VMSVGA3D
2969 case SVGA_CMD_DEFINE_SCREEN:
2970 {
2971 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2972 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2973 SVGAFifoCmdDefineScreen *pCmd;
2974 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2975 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2976 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2977
2978 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2979 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2980 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2981 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2982 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2983 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2984 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2985 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2986 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2987 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2988 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2989
2990 /** @todo multi monitor support and screen object capabilities. */
2991 pThis->svga.uWidth = pCmd->screen.size.width;
2992 pThis->svga.uHeight = pCmd->screen.size.height;
2993 vmsvgaChangeMode(pThis);
2994 break;
2995 }
2996
2997 case SVGA_CMD_DESTROY_SCREEN:
2998 {
2999 SVGAFifoCmdDestroyScreen *pCmd;
3000 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3001
3002 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3003 break;
3004 }
3005# ifdef VBOX_WITH_VMSVGA3D
3006 case SVGA_CMD_DEFINE_GMRFB:
3007 {
3008 SVGAFifoCmdDefineGMRFB *pCmd;
3009 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3010
3011 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3012 pSVGAState->GMRFB.ptr = pCmd->ptr;
3013 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3014 pSVGAState->GMRFB.format = pCmd->format;
3015 break;
3016 }
3017
3018 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3019 {
3020 uint32_t width, height;
3021 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3022 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3023
3024 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3025
3026 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3027 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3028 AssertBreak(pCmd->destScreenId == 0);
3029
3030 if (pCmd->destRect.left < 0)
3031 pCmd->destRect.left = 0;
3032 if (pCmd->destRect.top < 0)
3033 pCmd->destRect.top = 0;
3034 if (pCmd->destRect.right < 0)
3035 pCmd->destRect.right = 0;
3036 if (pCmd->destRect.bottom < 0)
3037 pCmd->destRect.bottom = 0;
3038
3039 width = pCmd->destRect.right - pCmd->destRect.left;
3040 height = pCmd->destRect.bottom - pCmd->destRect.top;
3041
3042 if ( width == 0
3043 || height == 0)
3044 break; /* Nothing to do. */
3045
3046 /* Clip to screen dimensions. */
3047 if (width > pThis->svga.uWidth)
3048 width = pThis->svga.uWidth;
3049 if (height > pThis->svga.uHeight)
3050 height = pThis->svga.uHeight;
3051
3052 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3053 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3054 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3055
3056 AssertBreak(offsetDest < pThis->vram_size);
3057
3058 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3059 AssertRC(rc);
3060 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3061 break;
3062 }
3063
3064 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3065 {
3066 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3067 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3068
3069 /* Note! This can fetch 3d render results as well!! */
3070 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3071 AssertFailed();
3072 break;
3073 }
3074# endif // VBOX_WITH_VMSVGA3D
3075 case SVGA_CMD_ANNOTATION_FILL:
3076 {
3077 SVGAFifoCmdAnnotationFill *pCmd;
3078 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3079
3080 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3081 pSVGAState->colorAnnotation = pCmd->color;
3082 break;
3083 }
3084
3085 case SVGA_CMD_ANNOTATION_COPY:
3086 {
3087 SVGAFifoCmdAnnotationCopy *pCmd;
3088 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3089
3090 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3091 AssertFailed();
3092 break;
3093 }
3094
3095 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3096
3097 default:
3098# ifdef VBOX_WITH_VMSVGA3D
3099 if ( enmCmdId >= SVGA_3D_CMD_BASE
3100 && enmCmdId < SVGA_3D_CMD_MAX)
3101 {
3102 /* All 3d commands start with a common header, which defines the size of the command. */
3103 SVGA3dCmdHeader *pHdr;
3104 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3105 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3106 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3107 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3108
3109/**
3110 * Check that the 3D command has at least a_cbMin of payload bytes after the
3111 * header. Will break out of the switch if it doesn't.
3112 */
3113# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3114 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3115 switch ((int)enmCmdId)
3116 {
3117 case SVGA_3D_CMD_SURFACE_DEFINE:
3118 {
3119 uint32_t cMipLevels;
3120 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3122
3123 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3124 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3125 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3126# ifdef DEBUG_GMR_ACCESS
3127 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3128# endif
3129 break;
3130 }
3131
3132 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3133 {
3134 uint32_t cMipLevels;
3135 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3136 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3137
3138 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3139 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3140 pCmd->multisampleCount, pCmd->autogenFilter,
3141 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3142 break;
3143 }
3144
3145 case SVGA_3D_CMD_SURFACE_DESTROY:
3146 {
3147 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3148 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3149 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3150 break;
3151 }
3152
3153 case SVGA_3D_CMD_SURFACE_COPY:
3154 {
3155 uint32_t cCopyBoxes;
3156 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3157 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3158
3159 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3160 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3161 break;
3162 }
3163
3164 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3165 {
3166 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3167 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3168
3169 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3170 break;
3171 }
3172
3173 case SVGA_3D_CMD_SURFACE_DMA:
3174 {
3175 uint32_t cCopyBoxes;
3176 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3177 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3178
3179 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3180 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3181 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3182 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3183 break;
3184 }
3185
3186 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3187 {
3188 uint32_t cRects;
3189 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3190 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3191
3192 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3193 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3194 break;
3195 }
3196
3197 case SVGA_3D_CMD_CONTEXT_DEFINE:
3198 {
3199 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3200 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3201
3202 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3203 break;
3204 }
3205
3206 case SVGA_3D_CMD_CONTEXT_DESTROY:
3207 {
3208 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3209 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3210
3211 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3212 break;
3213 }
3214
3215 case SVGA_3D_CMD_SETTRANSFORM:
3216 {
3217 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3219
3220 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3221 break;
3222 }
3223
3224 case SVGA_3D_CMD_SETZRANGE:
3225 {
3226 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3227 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3228
3229 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3230 break;
3231 }
3232
3233 case SVGA_3D_CMD_SETRENDERSTATE:
3234 {
3235 uint32_t cRenderStates;
3236 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3237 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3238
3239 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3240 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3241 break;
3242 }
3243
3244 case SVGA_3D_CMD_SETRENDERTARGET:
3245 {
3246 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3247 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3248
3249 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3250 break;
3251 }
3252
3253 case SVGA_3D_CMD_SETTEXTURESTATE:
3254 {
3255 uint32_t cTextureStates;
3256 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3258
3259 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3260 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3261 break;
3262 }
3263
3264 case SVGA_3D_CMD_SETMATERIAL:
3265 {
3266 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3267 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3268
3269 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3270 break;
3271 }
3272
3273 case SVGA_3D_CMD_SETLIGHTDATA:
3274 {
3275 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3276 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3277
3278 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3279 break;
3280 }
3281
3282 case SVGA_3D_CMD_SETLIGHTENABLED:
3283 {
3284 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3285 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3286
3287 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3288 break;
3289 }
3290
3291 case SVGA_3D_CMD_SETVIEWPORT:
3292 {
3293 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3294 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3295
3296 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3297 break;
3298 }
3299
3300 case SVGA_3D_CMD_SETCLIPPLANE:
3301 {
3302 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3303 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3304
3305 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3306 break;
3307 }
3308
3309 case SVGA_3D_CMD_CLEAR:
3310 {
3311 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3312 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3313 uint32_t cRects;
3314
3315 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3316 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3317 break;
3318 }
3319
3320 case SVGA_3D_CMD_PRESENT:
3321 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3322 {
3323 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3324 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3325 uint32_t cRects;
3326
3327 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3328
3329 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3330 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3331 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3332 break;
3333 }
3334
3335 case SVGA_3D_CMD_SHADER_DEFINE:
3336 {
3337 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3339 uint32_t cbData;
3340
3341 cbData = (pHdr->size - sizeof(*pCmd));
3342 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3343 break;
3344 }
3345
3346 case SVGA_3D_CMD_SHADER_DESTROY:
3347 {
3348 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3349 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3350
3351 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3352 break;
3353 }
3354
3355 case SVGA_3D_CMD_SET_SHADER:
3356 {
3357 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3359
3360 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3361 break;
3362 }
3363
3364 case SVGA_3D_CMD_SET_SHADER_CONST:
3365 {
3366 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3367 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3368
3369 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3370 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3371 break;
3372 }
3373
3374 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3375 {
3376 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3377 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3378 uint32_t cVertexDivisor;
3379
3380 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3381 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3382 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3383 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3384
3385 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3386 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3387 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3388
3389 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3390 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3391 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3392 break;
3393 }
3394
3395 case SVGA_3D_CMD_SETSCISSORRECT:
3396 {
3397 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3398 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3399
3400 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3401 break;
3402 }
3403
3404 case SVGA_3D_CMD_BEGIN_QUERY:
3405 {
3406 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3407 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3408
3409 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3410 break;
3411 }
3412
3413 case SVGA_3D_CMD_END_QUERY:
3414 {
3415 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3416 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3417
3418 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3419 break;
3420 }
3421
3422 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3423 {
3424 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3425 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3426
3427 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3428 break;
3429 }
3430
3431 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3432 {
3433 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3435
3436 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3437 break;
3438 }
3439
3440 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3441 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3442 /* context id + surface id? */
3443 break;
3444
3445 default:
3446 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3447 AssertFailed();
3448 break;
3449 }
3450 }
3451 else
3452# endif // VBOX_WITH_VMSVGA3D
3453 {
3454 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3455 AssertFailed();
3456 }
3457 }
3458
3459 /* Go to the next slot */
3460 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3461 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3462 if (offCurrentCmd >= offFifoMax)
3463 {
3464 offCurrentCmd -= offFifoMax - offFifoMin;
3465 Assert(offCurrentCmd >= offFifoMin);
3466 Assert(offCurrentCmd < offFifoMax);
3467 }
3468 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3469 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3470
3471 /*
3472 * Raise IRQ if required. Must enter the critical section here
3473 * before making final decisions here, otherwise cubebench and
3474 * others may end up waiting forever.
3475 */
3476 if ( u32IrqStatus
3477 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3478 {
3479 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3480
3481 /* FIFO progress might trigger an interrupt. */
3482 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3483 {
3484 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3485 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3486 }
3487
3488 /* Unmasked IRQ pending? */
3489 if (pThis->svga.u32IrqMask & u32IrqStatus)
3490 {
3491 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3492 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3493 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3494 }
3495
3496 PDMCritSectLeave(&pThis->CritSect);
3497 }
3498 }
3499
3500 /* If really done, clear the busy flag. */
3501 if (fDone)
3502 {
3503 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3504 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3505 }
3506 }
3507
3508 /*
3509 * Free the bounce buffer. (There are no returns above!)
3510 */
3511 RTMemFree(pbBounceBuf);
3512
3513 return VINF_SUCCESS;
3514}
3515
3516/**
3517 * Free the specified GMR
3518 *
3519 * @param pThis VGA device instance data.
3520 * @param idGMR GMR id
3521 */
3522void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3523{
3524 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3525
3526 /* Free the old descriptor if present. */
3527 if (pSVGAState->aGMR[idGMR].numDescriptors)
3528 {
3529 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3530# ifdef DEBUG_GMR_ACCESS
3531 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3532# endif
3533
3534 Assert(pGMR->paDesc);
3535 RTMemFree(pGMR->paDesc);
3536 pGMR->paDesc = NULL;
3537 pGMR->numDescriptors = 0;
3538 pGMR->cbTotal = 0;
3539 pGMR->cMaxPages = 0;
3540 }
3541 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3542}
3543
3544/**
3545 * Copy from a GMR to host memory or vice versa
3546 *
3547 * @returns VBox status code.
3548 * @param pThis VGA device instance data.
3549 * @param enmTransferType Transfer type (read/write)
3550 * @param pbDst Host destination pointer
3551 * @param cbDestPitch Destination buffer pitch
3552 * @param src GMR description
3553 * @param offSrc Source buffer offset
3554 * @param cbSrcPitch Source buffer pitch
3555 * @param cbWidth Source width in bytes
3556 * @param cHeight Source height
3557 */
3558int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3559 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3560{
3561 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3562 PGMR pGMR;
3563 int rc;
3564 PVMSVGAGMRDESCRIPTOR pDesc;
3565 unsigned offDesc = 0;
3566
3567 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3568 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3569 Assert(cbWidth && cHeight);
3570
3571 /* Shortcut for the framebuffer. */
3572 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3573 {
3574 offSrc += src.offset;
3575 AssertMsgReturn(src.offset < pThis->vram_size,
3576 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3577 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3578 VERR_INVALID_PARAMETER);
3579 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3580 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3581 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3582 VERR_INVALID_PARAMETER);
3583
3584 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3585
3586 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3587 {
3588 /* switch src & dest */
3589 uint8_t *pTemp = pbDst;
3590 int32_t cbTempPitch = cbDestPitch;
3591
3592 pbDst = pSrc;
3593 pSrc = pTemp;
3594
3595 cbDestPitch = cbSrcPitch;
3596 cbSrcPitch = cbTempPitch;
3597 }
3598
3599 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3600 && cbWidth == (uint32_t)cbDestPitch
3601 && cbSrcPitch == cbDestPitch)
3602 {
3603 memcpy(pbDst, pSrc, cbWidth * cHeight);
3604 }
3605 else
3606 {
3607 for(uint32_t i = 0; i < cHeight; i++)
3608 {
3609 memcpy(pbDst, pSrc, cbWidth);
3610
3611 pbDst += cbDestPitch;
3612 pSrc += cbSrcPitch;
3613 }
3614 }
3615 return VINF_SUCCESS;
3616 }
3617
3618 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3619 pGMR = &pSVGAState->aGMR[src.gmrId];
3620 pDesc = pGMR->paDesc;
3621
3622 offSrc += src.offset;
3623 AssertMsgReturn(src.offset < pGMR->cbTotal,
3624 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3625 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3626 VERR_INVALID_PARAMETER);
3627 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3628 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3629 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3630 VERR_INVALID_PARAMETER);
3631
3632 for (uint32_t i = 0; i < cHeight; i++)
3633 {
3634 uint32_t cbCurrentWidth = cbWidth;
3635 uint32_t offCurrent = offSrc;
3636 uint8_t *pCurrentDest = pbDst;
3637
3638 /* Find the right descriptor */
3639 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3640 {
3641 offDesc += pDesc->numPages * PAGE_SIZE;
3642 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3643 pDesc++;
3644 }
3645
3646 while (cbCurrentWidth)
3647 {
3648 uint32_t cbToCopy;
3649
3650 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3651 {
3652 cbToCopy = cbCurrentWidth;
3653 }
3654 else
3655 {
3656 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3657 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3658 }
3659
3660 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3661
3662 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3663 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3664 else
3665 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3666 AssertRCBreak(rc);
3667
3668 cbCurrentWidth -= cbToCopy;
3669 offCurrent += cbToCopy;
3670 pCurrentDest += cbToCopy;
3671
3672 /* Go to the next descriptor if there's anything left. */
3673 if (cbCurrentWidth)
3674 {
3675 offDesc += pDesc->numPages * PAGE_SIZE;
3676 pDesc++;
3677 }
3678 }
3679
3680 offSrc += cbSrcPitch;
3681 pbDst += cbDestPitch;
3682 }
3683
3684 return VINF_SUCCESS;
3685}
3686
3687/**
3688 * Unblock the FIFO I/O thread so it can respond to a state change.
3689 *
3690 * @returns VBox status code.
3691 * @param pDevIns The VGA device instance.
3692 * @param pThread The send thread.
3693 */
3694static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3695{
3696 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3697 Log(("vmsvgaFIFOLoopWakeUp\n"));
3698 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3699}
3700
3701/**
3702 * Enables or disables dirty page tracking for the framebuffer
3703 *
3704 * @param pThis VGA device instance data.
3705 * @param fTraces Enable/disable traces
3706 */
3707static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3708{
3709 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3710 && !fTraces)
3711 {
3712 //Assert(pThis->svga.fTraces);
3713 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3714 return;
3715 }
3716
3717 pThis->svga.fTraces = fTraces;
3718 if (pThis->svga.fTraces)
3719 {
3720 unsigned cbFrameBuffer = pThis->vram_size;
3721
3722 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3723 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3724 {
3725#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3726 Assert(pThis->svga.cbScanline);
3727#endif
3728 /* Hardware enabled; return real framebuffer size .*/
3729 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3730 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3731 }
3732
3733 if (!pThis->svga.fVRAMTracking)
3734 {
3735 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3736 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3737 pThis->svga.fVRAMTracking = true;
3738 }
3739 }
3740 else
3741 {
3742 if (pThis->svga.fVRAMTracking)
3743 {
3744 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3745 vgaR3UnregisterVRAMHandler(pThis);
3746 pThis->svga.fVRAMTracking = false;
3747 }
3748 }
3749}
3750
3751/**
3752 * Callback function for mapping a PCI I/O region.
3753 *
3754 * @return VBox status code.
3755 * @param pPciDev Pointer to PCI device.
3756 * Use pPciDev->pDevIns to get the device instance.
3757 * @param iRegion The region number.
3758 * @param GCPhysAddress Physical address of the region.
3759 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3760 * I/O port, else it's a physical address.
3761 * This address is *NOT* relative
3762 * to pci_mem_base like earlier!
3763 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3764 */
3765DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3766{
3767 int rc;
3768 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3769 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3770
3771 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3772 if (enmType == PCI_ADDRESS_SPACE_IO)
3773 {
3774 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3775 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3776 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3777 if (RT_FAILURE(rc))
3778 return rc;
3779 if (pThis->fR0Enabled)
3780 {
3781 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3782 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3783 if (RT_FAILURE(rc))
3784 return rc;
3785 }
3786 if (pThis->fGCEnabled)
3787 {
3788 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3789 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3790 if (RT_FAILURE(rc))
3791 return rc;
3792 }
3793
3794 pThis->svga.BasePort = GCPhysAddress;
3795 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3796 }
3797 else
3798 {
3799 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3800 if (GCPhysAddress != NIL_RTGCPHYS)
3801 {
3802 /*
3803 * Mapping the FIFO RAM.
3804 */
3805 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3806 AssertRC(rc);
3807
3808# ifdef DEBUG_FIFO_ACCESS
3809 if (RT_SUCCESS(rc))
3810 {
3811 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3812 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3813 "VMSVGA FIFO");
3814 AssertRC(rc);
3815 }
3816# endif
3817 if (RT_SUCCESS(rc))
3818 {
3819 pThis->svga.GCPhysFIFO = GCPhysAddress;
3820 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3821 }
3822 }
3823 else
3824 {
3825 Assert(pThis->svga.GCPhysFIFO);
3826# ifdef DEBUG_FIFO_ACCESS
3827 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3828 AssertRC(rc);
3829# endif
3830 pThis->svga.GCPhysFIFO = 0;
3831 }
3832
3833 }
3834 return VINF_SUCCESS;
3835}
3836
3837# ifdef VBOX_WITH_VMSVGA3D
3838
3839/**
3840 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3841 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3842 *
3843 * @param pThis The VGA device instance data.
3844 * @param sid Either UINT32_MAX or the ID of a specific
3845 * surface. If UINT32_MAX is used, all surfaces
3846 * are processed.
3847 */
3848void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3849{
3850 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3851 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3852}
3853
3854
3855/**
3856 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3857 */
3858DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3859{
3860 /* There might be a specific context ID at the start of the
3861 arguments, if not show all contexts. */
3862 uint32_t cid = UINT32_MAX;
3863 if (pszArgs)
3864 pszArgs = RTStrStripL(pszArgs);
3865 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3866 cid = RTStrToUInt32(pszArgs);
3867
3868 /* Verbose or terse display, we default to verbose. */
3869 bool fVerbose = true;
3870 if (RTStrIStr(pszArgs, "terse"))
3871 fVerbose = false;
3872
3873 /* The size of the ascii art (x direction, y is 3/4 of x). */
3874 uint32_t cxAscii = 80;
3875 if (RTStrIStr(pszArgs, "gigantic"))
3876 cxAscii = 300;
3877 else if (RTStrIStr(pszArgs, "huge"))
3878 cxAscii = 180;
3879 else if (RTStrIStr(pszArgs, "big"))
3880 cxAscii = 132;
3881 else if (RTStrIStr(pszArgs, "normal"))
3882 cxAscii = 80;
3883 else if (RTStrIStr(pszArgs, "medium"))
3884 cxAscii = 64;
3885 else if (RTStrIStr(pszArgs, "small"))
3886 cxAscii = 48;
3887 else if (RTStrIStr(pszArgs, "tiny"))
3888 cxAscii = 24;
3889
3890 /* Y invert the image when producing the ASCII art. */
3891 bool fInvY = false;
3892 if (RTStrIStr(pszArgs, "invy"))
3893 fInvY = true;
3894
3895 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3896}
3897
3898
3899/**
3900 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3901 */
3902DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3903{
3904 /* There might be a specific surface ID at the start of the
3905 arguments, if not show all contexts. */
3906 uint32_t sid = UINT32_MAX;
3907 if (pszArgs)
3908 pszArgs = RTStrStripL(pszArgs);
3909 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3910 sid = RTStrToUInt32(pszArgs);
3911
3912 /* Verbose or terse display, we default to verbose. */
3913 bool fVerbose = true;
3914 if (RTStrIStr(pszArgs, "terse"))
3915 fVerbose = false;
3916
3917 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3918}
3919
3920# endif /* VBOX_WITH_VMSVGA3D */
3921
3922/**
3923 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3924 */
3925static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3926{
3927 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3928 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3929
3930 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3931 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3932 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3933 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3934 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3935 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3936 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3937 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3938 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3939 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3940 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3941 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3942 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3943 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3944 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3945 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3946 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3947 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3948 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3949 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3950 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3951 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3952
3953 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3954 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3955 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3956 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3957
3958# ifdef VBOX_WITH_VMSVGA3D
3959 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3960 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3961 if (pThis->svga.u64HostWindowId != 0)
3962 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3963# endif
3964}
3965
3966
3967/**
3968 * @copydoc FNSSMDEVLOADEXEC
3969 */
3970int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3971{
3972 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3973 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3974 int rc;
3975
3976 /* Load our part of the VGAState */
3977 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3978 AssertRCReturn(rc, rc);
3979
3980 /* Load the framebuffer backup. */
3981 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3982 AssertRCReturn(rc, rc);
3983
3984 /* Load the VMSVGA state. */
3985 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3986 AssertRCReturn(rc, rc);
3987
3988 /* Load the active cursor bitmaps. */
3989 if (pSVGAState->Cursor.fActive)
3990 {
3991 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3992 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3993
3994 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3995 AssertRCReturn(rc, rc);
3996 }
3997
3998 /* Load the GMR state */
3999 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4000 {
4001 PGMR pGMR = &pSVGAState->aGMR[i];
4002
4003 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4004 AssertRCReturn(rc, rc);
4005
4006 if (pGMR->numDescriptors)
4007 {
4008 /* Allocate the maximum amount possible (everything non-continuous) */
4009 Assert(pGMR->cMaxPages || pGMR->cbTotal);
4010 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
4011 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4012
4013 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
4014 {
4015 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4016 AssertRCReturn(rc, rc);
4017 }
4018 }
4019 }
4020
4021# ifdef VBOX_WITH_VMSVGA3D
4022 if (pThis->svga.f3DEnabled)
4023 {
4024# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4025 vmsvga3dPowerOn(pThis);
4026# endif
4027
4028 VMSVGA_STATE_LOAD LoadState;
4029 LoadState.pSSM = pSSM;
4030 LoadState.uVersion = uVersion;
4031 LoadState.uPass = uPass;
4032 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4033 AssertLogRelRCReturn(rc, rc);
4034 }
4035# endif
4036
4037 return VINF_SUCCESS;
4038}
4039
4040/**
4041 * Reinit the video mode after the state has been loaded.
4042 */
4043int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4044{
4045 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4046 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4047
4048 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4049 vmsvgaChangeMode(pThis);
4050
4051 /* Set the active cursor. */
4052 if (pSVGAState->Cursor.fActive)
4053 {
4054 int rc;
4055
4056 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4057 true,
4058 true,
4059 pSVGAState->Cursor.xHotspot,
4060 pSVGAState->Cursor.yHotspot,
4061 pSVGAState->Cursor.width,
4062 pSVGAState->Cursor.height,
4063 pSVGAState->Cursor.pData);
4064 AssertRC(rc);
4065 }
4066 return VINF_SUCCESS;
4067}
4068
4069/**
4070 * @copydoc FNSSMDEVSAVEEXEC
4071 */
4072int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4073{
4074 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4075 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4076 int rc;
4077
4078 /* Save our part of the VGAState */
4079 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4080 AssertLogRelRCReturn(rc, rc);
4081
4082 /* Save the framebuffer backup. */
4083 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4084 AssertLogRelRCReturn(rc, rc);
4085
4086 /* Save the VMSVGA state. */
4087 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4088 AssertLogRelRCReturn(rc, rc);
4089
4090 /* Save the active cursor bitmaps. */
4091 if (pSVGAState->Cursor.fActive)
4092 {
4093 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4094 AssertLogRelRCReturn(rc, rc);
4095 }
4096
4097 /* Save the GMR state */
4098 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4099 {
4100 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4101 AssertLogRelRCReturn(rc, rc);
4102
4103 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4104 {
4105 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4106 AssertLogRelRCReturn(rc, rc);
4107 }
4108 }
4109
4110# ifdef VBOX_WITH_VMSVGA3D
4111 /*
4112 * Must save the 3d state in the FIFO thread.
4113 */
4114 if (pThis->svga.f3DEnabled)
4115 {
4116 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4117 AssertLogRelRCReturn(rc, rc);
4118 }
4119# endif
4120 return VINF_SUCCESS;
4121}
4122
4123/**
4124 * Resets the SVGA hardware state
4125 *
4126 * @returns VBox status code.
4127 * @param pDevIns The device instance.
4128 */
4129int vmsvgaReset(PPDMDEVINS pDevIns)
4130{
4131 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4132 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4133
4134 /* Reset before init? */
4135 if (!pSVGAState)
4136 return VINF_SUCCESS;
4137
4138 Log(("vmsvgaReset\n"));
4139
4140
4141 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4142 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4143 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4144
4145 /* Reset other stuff. */
4146 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4147 RT_ZERO(pThis->svga.au32ScratchRegion);
4148 RT_ZERO(*pThis->svga.pSvgaR3State);
4149 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4150
4151 /* Register caps. */
4152 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4153# ifdef VBOX_WITH_VMSVGA3D
4154 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4155# endif
4156
4157 /* Setup FIFO capabilities. */
4158 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4159
4160 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4161 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4162
4163 /* VRAM tracking is enabled by default during bootup. */
4164 pThis->svga.fVRAMTracking = true;
4165 pThis->svga.fEnabled = false;
4166
4167 /* Invalidate current settings. */
4168 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4169 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4170 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4171 pThis->svga.cbScanline = 0;
4172
4173 return rc;
4174}
4175
4176/**
4177 * Cleans up the SVGA hardware state
4178 *
4179 * @returns VBox status code.
4180 * @param pDevIns The device instance.
4181 */
4182int vmsvgaDestruct(PPDMDEVINS pDevIns)
4183{
4184 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4185
4186 /*
4187 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4188 */
4189 if (pThis->svga.pFIFOIOThread)
4190 {
4191 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4192 AssertLogRelRC(rc);
4193
4194 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4195 AssertLogRelRC(rc);
4196 pThis->svga.pFIFOIOThread = NULL;
4197 }
4198
4199 /*
4200 * Destroy the special SVGA state.
4201 */
4202 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4203 if (pSVGAState)
4204 {
4205# ifndef VMSVGA_USE_EMT_HALT_CODE
4206 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4207 {
4208 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4209 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4210 }
4211# endif
4212 if (pSVGAState->Cursor.fActive)
4213 RTMemFree(pSVGAState->Cursor.pData);
4214
4215 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4216 if (pSVGAState->aGMR[i].paDesc)
4217 RTMemFree(pSVGAState->aGMR[i].paDesc);
4218
4219 RTMemFree(pSVGAState);
4220 pThis->svga.pSvgaR3State = NULL;
4221 }
4222
4223 /*
4224 * Free our resources residing in the VGA state.
4225 */
4226 if (pThis->svga.pFrameBufferBackup)
4227 RTMemFree(pThis->svga.pFrameBufferBackup);
4228 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4229 {
4230 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4231 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4232 }
4233 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4234 {
4235 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4236 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4237 }
4238
4239 return VINF_SUCCESS;
4240}
4241
4242/**
4243 * Initialize the SVGA hardware state
4244 *
4245 * @returns VBox status code.
4246 * @param pDevIns The device instance.
4247 */
4248int vmsvgaInit(PPDMDEVINS pDevIns)
4249{
4250 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4251 PVMSVGAR3STATE pSVGAState;
4252 PVM pVM = PDMDevHlpGetVM(pDevIns);
4253 int rc;
4254
4255 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4256 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4257
4258 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4259 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4260 pSVGAState = pThis->svga.pSvgaR3State;
4261
4262 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4263 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4264 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4265
4266 /* Create event semaphore. */
4267 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4268
4269 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4270 if (RT_FAILURE(rc))
4271 {
4272 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4273 return rc;
4274 }
4275
4276 /* Create event semaphore. */
4277 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4278 if (RT_FAILURE(rc))
4279 {
4280 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4281 return rc;
4282 }
4283
4284# ifndef VMSVGA_USE_EMT_HALT_CODE
4285 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4286 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4287 AssertRCReturn(rc, rc);
4288# endif
4289
4290 /* Register caps. */
4291 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4292# ifdef VBOX_WITH_VMSVGA3D
4293 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4294# endif
4295
4296 /* Setup FIFO capabilities. */
4297 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4298
4299 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4300 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4301
4302 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4303# ifdef VBOX_WITH_VMSVGA3D
4304 if (pThis->svga.f3DEnabled)
4305 {
4306 rc = vmsvga3dInit(pThis);
4307 if (RT_FAILURE(rc))
4308 {
4309 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4310 pThis->svga.f3DEnabled = false;
4311 }
4312 }
4313# endif
4314 /* VRAM tracking is enabled by default during bootup. */
4315 pThis->svga.fVRAMTracking = true;
4316
4317 /* Invalidate current settings. */
4318 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4319 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4320 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4321 pThis->svga.cbScanline = 0;
4322
4323 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4324 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4325 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4326 {
4327 pThis->svga.u32MaxWidth -= 256;
4328 pThis->svga.u32MaxHeight -= 256;
4329 }
4330 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4331
4332# ifdef DEBUG_GMR_ACCESS
4333 /* Register the GMR access handler type. */
4334 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4335 vmsvgaR3GMRAccessHandler,
4336 NULL, NULL, NULL,
4337 NULL, NULL, NULL,
4338 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4339 AssertRCReturn(rc, rc);
4340# endif
4341# ifdef DEBUG_FIFO_ACCESS
4342 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4343 vmsvgaR3FIFOAccessHandler,
4344 NULL, NULL, NULL,
4345 NULL, NULL, NULL,
4346 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4347 AssertRCReturn(rc, rc);
4348#endif
4349
4350 /* Create the async IO thread. */
4351 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4352 RTTHREADTYPE_IO, "VMSVGA FIFO");
4353 if (RT_FAILURE(rc))
4354 {
4355 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4356 return rc;
4357 }
4358
4359 /*
4360 * Statistics.
4361 */
4362 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4363 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4364 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4365 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4366 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4367 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4368 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4369 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4370 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4371 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4372
4373 /*
4374 * Info handlers.
4375 */
4376 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4377# ifdef VBOX_WITH_VMSVGA3D
4378 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4379 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4380 "VMSVGA 3d surface details. "
4381 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4382 vmsvgaR3Info3dSurface);
4383# endif
4384
4385 return VINF_SUCCESS;
4386}
4387
4388# ifdef VBOX_WITH_VMSVGA3D
4389/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4390static const char * const g_apszVmSvgaDevCapNames[] =
4391{
4392 "x3D", /* = 0 */
4393 "xMAX_LIGHTS",
4394 "xMAX_TEXTURES",
4395 "xMAX_CLIP_PLANES",
4396 "xVERTEX_SHADER_VERSION",
4397 "xVERTEX_SHADER",
4398 "xFRAGMENT_SHADER_VERSION",
4399 "xFRAGMENT_SHADER",
4400 "xMAX_RENDER_TARGETS",
4401 "xS23E8_TEXTURES",
4402 "xS10E5_TEXTURES",
4403 "xMAX_FIXED_VERTEXBLEND",
4404 "xD16_BUFFER_FORMAT",
4405 "xD24S8_BUFFER_FORMAT",
4406 "xD24X8_BUFFER_FORMAT",
4407 "xQUERY_TYPES",
4408 "xTEXTURE_GRADIENT_SAMPLING",
4409 "rMAX_POINT_SIZE",
4410 "xMAX_SHADER_TEXTURES",
4411 "xMAX_TEXTURE_WIDTH",
4412 "xMAX_TEXTURE_HEIGHT",
4413 "xMAX_VOLUME_EXTENT",
4414 "xMAX_TEXTURE_REPEAT",
4415 "xMAX_TEXTURE_ASPECT_RATIO",
4416 "xMAX_TEXTURE_ANISOTROPY",
4417 "xMAX_PRIMITIVE_COUNT",
4418 "xMAX_VERTEX_INDEX",
4419 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4420 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4421 "xMAX_VERTEX_SHADER_TEMPS",
4422 "xMAX_FRAGMENT_SHADER_TEMPS",
4423 "xTEXTURE_OPS",
4424 "xSURFACEFMT_X8R8G8B8",
4425 "xSURFACEFMT_A8R8G8B8",
4426 "xSURFACEFMT_A2R10G10B10",
4427 "xSURFACEFMT_X1R5G5B5",
4428 "xSURFACEFMT_A1R5G5B5",
4429 "xSURFACEFMT_A4R4G4B4",
4430 "xSURFACEFMT_R5G6B5",
4431 "xSURFACEFMT_LUMINANCE16",
4432 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4433 "xSURFACEFMT_ALPHA8",
4434 "xSURFACEFMT_LUMINANCE8",
4435 "xSURFACEFMT_Z_D16",
4436 "xSURFACEFMT_Z_D24S8",
4437 "xSURFACEFMT_Z_D24X8",
4438 "xSURFACEFMT_DXT1",
4439 "xSURFACEFMT_DXT2",
4440 "xSURFACEFMT_DXT3",
4441 "xSURFACEFMT_DXT4",
4442 "xSURFACEFMT_DXT5",
4443 "xSURFACEFMT_BUMPX8L8V8U8",
4444 "xSURFACEFMT_A2W10V10U10",
4445 "xSURFACEFMT_BUMPU8V8",
4446 "xSURFACEFMT_Q8W8V8U8",
4447 "xSURFACEFMT_CxV8U8",
4448 "xSURFACEFMT_R_S10E5",
4449 "xSURFACEFMT_R_S23E8",
4450 "xSURFACEFMT_RG_S10E5",
4451 "xSURFACEFMT_RG_S23E8",
4452 "xSURFACEFMT_ARGB_S10E5",
4453 "xSURFACEFMT_ARGB_S23E8",
4454 "xMISSING62",
4455 "xMAX_VERTEX_SHADER_TEXTURES",
4456 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4457 "xSURFACEFMT_V16U16",
4458 "xSURFACEFMT_G16R16",
4459 "xSURFACEFMT_A16B16G16R16",
4460 "xSURFACEFMT_UYVY",
4461 "xSURFACEFMT_YUY2",
4462 "xMULTISAMPLE_NONMASKABLESAMPLES",
4463 "xMULTISAMPLE_MASKABLESAMPLES",
4464 "xALPHATOCOVERAGE",
4465 "xSUPERSAMPLE",
4466 "xAUTOGENMIPMAPS",
4467 "xSURFACEFMT_NV12",
4468 "xSURFACEFMT_AYUV",
4469 "xMAX_CONTEXT_IDS",
4470 "xMAX_SURFACE_IDS",
4471 "xSURFACEFMT_Z_DF16",
4472 "xSURFACEFMT_Z_DF24",
4473 "xSURFACEFMT_Z_D24S8_INT",
4474 "xSURFACEFMT_BC4_UNORM",
4475 "xSURFACEFMT_BC5_UNORM", /* 83 */
4476};
4477# endif
4478
4479
4480/**
4481 * Power On notification.
4482 *
4483 * @returns VBox status code.
4484 * @param pDevIns The device instance data.
4485 *
4486 * @remarks Caller enters the device critical section.
4487 */
4488DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4489{
4490 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4491 int rc;
4492
4493# ifdef VBOX_WITH_VMSVGA3D
4494 if (pThis->svga.f3DEnabled)
4495 {
4496 rc = vmsvga3dPowerOn(pThis);
4497
4498 if (RT_SUCCESS(rc))
4499 {
4500 bool fSavedBuffering = RTLogRelSetBuffering(true);
4501 SVGA3dCapsRecord *pCaps;
4502 SVGA3dCapPair *pData;
4503 uint32_t idxCap = 0;
4504
4505 /* 3d hardware version; latest and greatest */
4506 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4507 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4508
4509 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4510 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4511 pData = (SVGA3dCapPair *)&pCaps->data;
4512
4513 /* Fill out all 3d capabilities. */
4514 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4515 {
4516 uint32_t val = 0;
4517
4518 rc = vmsvga3dQueryCaps(pThis, i, &val);
4519 if (RT_SUCCESS(rc))
4520 {
4521 pData[idxCap][0] = i;
4522 pData[idxCap][1] = val;
4523 idxCap++;
4524 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4525 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4526 else
4527 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4528 &g_apszVmSvgaDevCapNames[i][1]));
4529 }
4530 else
4531 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4532 }
4533 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4534 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4535
4536 /* Mark end of record array. */
4537 pCaps->header.length = 0;
4538
4539 RTLogRelSetBuffering(fSavedBuffering);
4540 }
4541 }
4542# endif // VBOX_WITH_VMSVGA3D
4543}
4544
4545#endif /* IN_RING3 */
4546
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