DevVGA-SVGA.cpp@ 68080

Last change on this file since 68080 was 65640, checked in by vboxsync, 8 years ago
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1	/* $Id: DevVGA-SVGA.cpp 65640 2017-02-07 10:53:23Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2016 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/VMMDev.h>
148	#include <VBoxVideo.h>
149	#include <VBox/bioslogo.h>
150
151	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
152	#include "DevVGA.h"
153
154	#include "DevVGA-SVGA.h"
155	#include "vmsvga/svga_reg.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_reg.h"
159	#include "vmsvga/svga3d_caps.h"
160	#ifdef VBOX_WITH_VMSVGA3D
161	# include "DevVGA-SVGA3d.h"
162	# ifdef RT_OS_DARWIN
163	# include "DevVGA-SVGA3d-cocoa.h"
164	# endif
165	#endif
166
167
168	/*********************************************************************************************************************************
169	* Defined Constants And Macros *
170	*********************************************************************************************************************************/
171	/**
172	* Macro for checking if a fixed FIFO register is valid according to the
173	* current FIFO configuration.
174	*
175	* @returns true / false.
176	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
177	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
178	*/
179	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* 64-bit GMR descriptor.
187	*/
188	typedef struct
189	{
190	RTGCPHYS GCPhys;
191	uint64_t numPages;
192	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
193
194	/**
195	* GMR slot
196	*/
197	typedef struct
198	{
199	uint32_t cMaxPages;
200	uint32_t cbTotal;
201	uint32_t numDescriptors;
202	PVMSVGAGMRDESCRIPTOR paDesc;
203	} GMR, *PGMR;
204
205	#ifdef IN_RING3
206	/**
207	* Internal SVGA ring-3 only state.
208	*/
209	typedef struct VMSVGAR3STATE
210	{
211	GMR aGMR[VMSVGA_MAX_GMR_IDS];
212	struct
213	{
214	SVGAGuestPtr ptr;
215	uint32_t bytesPerLine;
216	SVGAGMRImageFormat format;
217	} GMRFB;
218	struct
219	{
220	bool fActive;
221	uint32_t xHotspot;
222	uint32_t yHotspot;
223	uint32_t width;
224	uint32_t height;
225	uint32_t cbData;
226	void *pData;
227	} Cursor;
228	SVGAColorBGRX colorAnnotation;
229
230	# ifdef VMSVGA_USE_EMT_HALT_CODE
231	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
232	uint32_t volatile cBusyDelayedEmts;
233	/** Set of EMTs that are */
234	VMCPUSET BusyDelayedEmts;
235	# else
236	/** Number of EMTs waiting on hBusyDelayedEmts. */
237	uint32_t volatile cBusyDelayedEmts;
238	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
239	* busy (ugly). */
240	RTSEMEVENTMULTI hBusyDelayedEmts;
241	# endif
242	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
243	STAMPROFILE StatBusyDelayEmts;
244
245	STAMPROFILE StatR3Cmd3dPresentProf;
246	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
247	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
248	STAMCOUNTER StatR3CmdDefineGmr2;
249	STAMCOUNTER StatR3CmdDefineGmr2Free;
250	STAMCOUNTER StatR3CmdDefineGmr2Modify;
251	STAMCOUNTER StatR3CmdRemapGmr2;
252	STAMCOUNTER StatR3CmdRemapGmr2Modify;
253	STAMCOUNTER StatR3CmdInvalidCmd;
254	STAMCOUNTER StatR3CmdFence;
255	STAMCOUNTER StatR3CmdUpdate;
256	STAMCOUNTER StatR3CmdUpdateVerbose;
257	STAMCOUNTER StatR3CmdDefineCursor;
258	STAMCOUNTER StatR3CmdDefineAlphaCursor;
259	STAMCOUNTER StatR3CmdEscape;
260	STAMCOUNTER StatR3CmdDefineScreen;
261	STAMCOUNTER StatR3CmdDestroyScreen;
262	STAMCOUNTER StatR3CmdDefineGmrFb;
263	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
264	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
265	STAMCOUNTER StatR3CmdAnnotationFill;
266	STAMCOUNTER StatR3CmdAnnotationCopy;
267	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
268	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
269	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
270	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
271	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
272	STAMCOUNTER StatR3Cmd3dSurfaceDma;
273	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
274	STAMCOUNTER StatR3Cmd3dContextDefine;
275	STAMCOUNTER StatR3Cmd3dContextDestroy;
276	STAMCOUNTER StatR3Cmd3dSetTransform;
277	STAMCOUNTER StatR3Cmd3dSetZRange;
278	STAMCOUNTER StatR3Cmd3dSetRenderState;
279	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
280	STAMCOUNTER StatR3Cmd3dSetTextureState;
281	STAMCOUNTER StatR3Cmd3dSetMaterial;
282	STAMCOUNTER StatR3Cmd3dSetLightData;
283	STAMCOUNTER StatR3Cmd3dSetLightEnable;
284	STAMCOUNTER StatR3Cmd3dSetViewPort;
285	STAMCOUNTER StatR3Cmd3dSetClipPlane;
286	STAMCOUNTER StatR3Cmd3dClear;
287	STAMCOUNTER StatR3Cmd3dPresent;
288	STAMCOUNTER StatR3Cmd3dPresentReadBack;
289	STAMCOUNTER StatR3Cmd3dShaderDefine;
290	STAMCOUNTER StatR3Cmd3dShaderDestroy;
291	STAMCOUNTER StatR3Cmd3dSetShader;
292	STAMCOUNTER StatR3Cmd3dSetShaderConst;
293	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
294	STAMCOUNTER StatR3Cmd3dSetScissorRect;
295	STAMCOUNTER StatR3Cmd3dBeginQuery;
296	STAMCOUNTER StatR3Cmd3dEndQuery;
297	STAMCOUNTER StatR3Cmd3dWaitForQuery;
298	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
299	STAMCOUNTER StatR3Cmd3dActivateSurface;
300	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
301
302	STAMCOUNTER StatR3RegConfigDoneWr;
303	STAMCOUNTER StatR3RegGmrDescriptorWr;
304	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
305	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
306
307	STAMCOUNTER StatFifoCommands;
308	STAMCOUNTER StatFifoErrors;
309	STAMCOUNTER StatFifoUnkCmds;
310	STAMCOUNTER StatFifoTodoTimeout;
311	STAMCOUNTER StatFifoTodoWoken;
312	STAMPROFILE StatFifoStalls;
313
314	} VMSVGAR3STATE, *PVMSVGAR3STATE;
315	#endif /* IN_RING3 */
316
317
318	/*********************************************************************************************************************************
319	* Internal Functions *
320	*********************************************************************************************************************************/
321	#ifdef IN_RING3
322	# ifdef DEBUG_FIFO_ACCESS
323	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
324	# endif
325	# ifdef DEBUG_GMR_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
327	# endif
328	#endif
329
330
331	/*********************************************************************************************************************************
332	* Global Variables *
333	*********************************************************************************************************************************/
334	#ifdef IN_RING3
335
336	/**
337	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
338	*/
339	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
340	{
341	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
342	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
343	SSMFIELD_ENTRY_TERM()
344	};
345
346	/**
347	* SSM descriptor table for the GMR structure.
348	*/
349	static SSMFIELD const g_aGMRFields[] =
350	{
351	SSMFIELD_ENTRY( GMR, cMaxPages),
352	SSMFIELD_ENTRY( GMR, cbTotal),
353	SSMFIELD_ENTRY( GMR, numDescriptors),
354	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
355	SSMFIELD_ENTRY_TERM()
356	};
357
358	/**
359	* SSM descriptor table for the VMSVGAR3STATE structure.
360	*/
361	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
362	{
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
364	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
365	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
366	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
367	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
368	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
369	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
370	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
371	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
372	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
374	#ifdef VMSVGA_USE_EMT_HALT_CODE
375	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
376	#else
377	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
378	#endif
379	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
380	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
381	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
382	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
383	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
387	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
388	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
389	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
390	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
391	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
392	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
393	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
394	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
398	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
400	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
436
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
441
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
448	SSMFIELD_ENTRY_TERM()
449	};
450
451	/**
452	* SSM descriptor table for the VGAState.svga structure.
453	*/
454	static SSMFIELD const g_aVGAStateSVGAFields[] =
455	{
456	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
457	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
458	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
459	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
460	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
461	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
462	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
463	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
466	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
467	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
468	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
469	SSMFIELD_ENTRY( VMSVGAState, fBusy),
470	SSMFIELD_ENTRY( VMSVGAState, fTraces),
471	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
472	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
473	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
474	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
475	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
476	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
477	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
478	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
480	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
485	SSMFIELD_ENTRY( VMSVGAState, uWidth),
486	SSMFIELD_ENTRY( VMSVGAState, uHeight),
487	SSMFIELD_ENTRY( VMSVGAState, uBpp),
488	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
489	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
490	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
491	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
492	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
493	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
500
501	#endif /* IN_RING3 */
502
503	#ifdef LOG_ENABLED
504
505	/**
506	* Index register string name lookup
507	*
508	* @returns Index register string or "UNKNOWN"
509	* @param pThis VMSVGA State
510	* @param idxReg The index register.
511	*/
512	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
513	{
514	switch (idxReg)
515	{
516	case SVGA_REG_ID: return "SVGA_REG_ID";
517	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
518	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
519	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
520	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
521	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
522	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
523	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
524	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
525	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
526	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
527	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
528	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
529	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
530	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
531	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
532	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
533	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
534	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
535	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
536	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
537	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
538	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
539	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
540	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
541	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
542	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
543	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
544	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
545	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
546	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
547	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
548	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
549	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
550	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
551	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
552	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
553	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
554	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
555	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
556	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
557	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
558	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
559	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
560	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
561	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
562	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
563	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
564	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
565	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
566
567	default:
568	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
569	return "SVGA_SCRATCH_BASE reg";
570	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
571	return "SVGA_PALETTE_BASE reg";
572	return "UNKNOWN";
573	}
574	}
575
576	#ifdef IN_RING3
577	/**
578	* FIFO command name lookup
579	*
580	* @returns FIFO command string or "UNKNOWN"
581	* @param u32Cmd FIFO command
582	*/
583	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
584	{
585	switch (u32Cmd)
586	{
587	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
588	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
589	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
590	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
591	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
592	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
593	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
594	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
595	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
596	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
597	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
598	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
599	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
600	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
601	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
602	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
603	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
604	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
605	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
606	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
607	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
608	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
609	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
610	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
611	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
612	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
613	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
614	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
615	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
616	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
617	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
618	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
619	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
620	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
621	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
622	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
623	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
624	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
625	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
626	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
627	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
628	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
629	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
630	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
631	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
632	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
633	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
634	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
635	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
636	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
637	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
638	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
639	default: return "UNKNOWN";
640	}
641	}
642	# endif /* IN_RING3 */
643
644	#endif /* LOG_ENABLED */
645
646	#ifdef IN_RING3
647	/**
648	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
649	*/
650	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
651	{
652	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
653
654	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
655	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
656
657	if (x < pThis->svga.uWidth)
658	{
659	pThis->svga.viewport.x = x;
660	pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
661	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
662	}
663	else
664	{
665	pThis->svga.viewport.x = pThis->svga.uWidth;
666	pThis->svga.viewport.cx = 0;
667	pThis->svga.viewport.xRight = pThis->svga.uWidth;
668	}
669	if (y < pThis->svga.uHeight)
670	{
671	pThis->svga.viewport.y = y;
672	pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
673	pThis->svga.viewport.yLowWC = pThis->svga.uHeight - y - pThis->svga.viewport.cy;
674	pThis->svga.viewport.yHighWC = pThis->svga.uHeight - y;
675	}
676	else
677	{
678	pThis->svga.viewport.y = pThis->svga.uHeight;
679	pThis->svga.viewport.cy = 0;
680	pThis->svga.viewport.yLowWC = 0;
681	pThis->svga.viewport.yHighWC = 0;
682	}
683
684	# ifdef VBOX_WITH_VMSVGA3D
685	/*
686	* Now inform the 3D backend.
687	*/
688	if (pThis->svga.f3DEnabled)
689	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
690	# else
691	RT_NOREF(idScreen, OldViewport);
692	# endif
693	}
694	#endif /* IN_RING3 */
695
696	/**
697	* Read port register
698	*
699	* @returns VBox status code.
700	* @param pThis VMSVGA State
701	* @param pu32 Where to store the read value
702	*/
703	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
704	{
705	int rc = VINF_SUCCESS;
706	*pu32 = 0;
707
708	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
709	uint32_t idxReg = pThis->svga.u32IndexReg;
710	if ( idxReg >= SVGA_REG_CAPABILITIES
711	&& pThis->svga.u32SVGAId == SVGA_ID_0)
712	{
713	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
714	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
715	}
716
717	switch (idxReg)
718	{
719	case SVGA_REG_ID:
720	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
721	*pu32 = pThis->svga.u32SVGAId;
722	break;
723
724	case SVGA_REG_ENABLE:
725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
726	*pu32 = pThis->svga.fEnabled;
727	break;
728
729	case SVGA_REG_WIDTH:
730	{
731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
732	if ( pThis->svga.fEnabled
733	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
734	{
735	*pu32 = pThis->svga.uWidth;
736	}
737	else
738	{
739	#ifndef IN_RING3
740	rc = VINF_IOM_R3_IOPORT_READ;
741	#else
742	*pu32 = pThis->pDrv->cx;
743	#endif
744	}
745	break;
746	}
747
748	case SVGA_REG_HEIGHT:
749	{
750	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
751	if ( pThis->svga.fEnabled
752	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
753	{
754	*pu32 = pThis->svga.uHeight;
755	}
756	else
757	{
758	#ifndef IN_RING3
759	rc = VINF_IOM_R3_IOPORT_READ;
760	#else
761	*pu32 = pThis->pDrv->cy;
762	#endif
763	}
764	break;
765	}
766
767	case SVGA_REG_MAX_WIDTH:
768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
769	*pu32 = pThis->svga.u32MaxWidth;
770	break;
771
772	case SVGA_REG_MAX_HEIGHT:
773	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
774	*pu32 = pThis->svga.u32MaxHeight;
775	break;
776
777	case SVGA_REG_DEPTH:
778	/* This returns the color depth of the current mode. */
779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
780	switch (pThis->svga.uBpp)
781	{
782	case 15:
783	case 16:
784	case 24:
785	*pu32 = pThis->svga.uBpp;
786	break;
787
788	default:
789	case 32:
790	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
791	break;
792	}
793	break;
794
795	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
797	if ( pThis->svga.fEnabled
798	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
799	{
800	*pu32 = pThis->svga.uBpp;
801	}
802	else
803	{
804	#ifndef IN_RING3
805	rc = VINF_IOM_R3_IOPORT_READ;
806	#else
807	*pu32 = pThis->pDrv->cBits;
808	#endif
809	}
810	break;
811
812	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
813	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
814	if ( pThis->svga.fEnabled
815	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
816	{
817	*pu32 = (pThis->svga.uBpp + 7) & ~7;
818	}
819	else
820	{
821	#ifndef IN_RING3
822	rc = VINF_IOM_R3_IOPORT_READ;
823	#else
824	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
825	#endif
826	}
827	break;
828
829	case SVGA_REG_PSEUDOCOLOR:
830	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
831	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
832	break;
833
834	case SVGA_REG_RED_MASK:
835	case SVGA_REG_GREEN_MASK:
836	case SVGA_REG_BLUE_MASK:
837	{
838	uint32_t uBpp;
839
840	if ( pThis->svga.fEnabled
841	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
842	{
843	uBpp = pThis->svga.uBpp;
844	}
845	else
846	{
847	#ifndef IN_RING3
848	rc = VINF_IOM_R3_IOPORT_READ;
849	break;
850	#else
851	uBpp = pThis->pDrv->cBits;
852	#endif
853	}
854	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
855	switch (uBpp)
856	{
857	case 8:
858	u32RedMask = 0x07;
859	u32GreenMask = 0x38;
860	u32BlueMask = 0xc0;
861	break;
862
863	case 15:
864	u32RedMask = 0x0000001f;
865	u32GreenMask = 0x000003e0;
866	u32BlueMask = 0x00007c00;
867	break;
868
869	case 16:
870	u32RedMask = 0x0000001f;
871	u32GreenMask = 0x000007e0;
872	u32BlueMask = 0x0000f800;
873	break;
874
875	case 24:
876	case 32:
877	default:
878	u32RedMask = 0x00ff0000;
879	u32GreenMask = 0x0000ff00;
880	u32BlueMask = 0x000000ff;
881	break;
882	}
883	switch (idxReg)
884	{
885	case SVGA_REG_RED_MASK:
886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
887	*pu32 = u32RedMask;
888	break;
889
890	case SVGA_REG_GREEN_MASK:
891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
892	*pu32 = u32GreenMask;
893	break;
894
895	case SVGA_REG_BLUE_MASK:
896	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
897	*pu32 = u32BlueMask;
898	break;
899	}
900	break;
901	}
902
903	case SVGA_REG_BYTES_PER_LINE:
904	{
905	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
906	if ( pThis->svga.fEnabled
907	&& pThis->svga.cbScanline)
908	{
909	*pu32 = pThis->svga.cbScanline;
910	}
911	else
912	{
913	#ifndef IN_RING3
914	rc = VINF_IOM_R3_IOPORT_READ;
915	#else
916	*pu32 = pThis->pDrv->cbScanline;
917	#endif
918	}
919	break;
920	}
921
922	case SVGA_REG_VRAM_SIZE: /* VRAM size */
923	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
924	*pu32 = pThis->vram_size;
925	break;
926
927	case SVGA_REG_FB_START: /* Frame buffer physical address. */
928	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
929	Assert(pThis->GCPhysVRAM <= 0xffffffff);
930	*pu32 = pThis->GCPhysVRAM;
931	break;
932
933	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
935	/* Always zero in our case. */
936	*pu32 = 0;
937	break;
938
939	case SVGA_REG_FB_SIZE: /* Frame buffer size */
940	{
941	#ifndef IN_RING3
942	rc = VINF_IOM_R3_IOPORT_READ;
943	#else
944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
945
946	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
947	if ( pThis->svga.fEnabled
948	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
949	{
950	/* Hardware enabled; return real framebuffer size .*/
951	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
952	}
953	else
954	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
955
956	pu32 = RT_MIN(pThis->vram_size, pu32);
957	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
958	#endif
959	break;
960	}
961
962	case SVGA_REG_CAPABILITIES:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
964	*pu32 = pThis->svga.u32RegCaps;
965	break;
966
967	case SVGA_REG_MEM_START: /* FIFO start */
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
969	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
970	*pu32 = pThis->svga.GCPhysFIFO;
971	break;
972
973	case SVGA_REG_MEM_SIZE: /* FIFO size */
974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
975	*pu32 = pThis->svga.cbFIFO;
976	break;
977
978	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
979	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
980	*pu32 = pThis->svga.fConfigured;
981	break;
982
983	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
985	*pu32 = 0;
986	break;
987
988	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
989	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
990	if (pThis->svga.fBusy)
991	{
992	#ifndef IN_RING3
993	/* Go to ring-3 and halt the CPU. */
994	rc = VINF_IOM_R3_IOPORT_READ;
995	break;
996	#else
997	# if defined(VMSVGA_USE_EMT_HALT_CODE)
998	/* The guest is basically doing a HLT via the device here, but with
999	a special wake up condition on FIFO completion. */
1000	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1001	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1002	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1003	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1004	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1005	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1006	if (pThis->svga.fBusy)
1007	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1008	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1009	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1010	# else
1011
1012	/* Delay the EMT a bit so the FIFO and others can get some work done.
1013	This used to be a crude 50 ms sleep. The current code tries to be
1014	more efficient, but the consept is still very crude. */
1015	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1016	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1017	RTThreadYield();
1018	if (pThis->svga.fBusy)
1019	{
1020	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1021
1022	if (pThis->svga.fBusy && cRefs == 1)
1023	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1024	if (pThis->svga.fBusy)
1025	{
1026	/** @todo If this code is going to stay, we need to call into the halt/wait
1027	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1028	* suffer when the guest is polling on a busy FIFO. */
1029	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1030	if (cNsMaxWait >= RT_NS_100US)
1031	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1032	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1033	RT_MIN(cNsMaxWait, RT_NS_10MS));
1034	}
1035
1036	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1037	}
1038	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1039	# endif
1040	*pu32 = pThis->svga.fBusy != 0;
1041	#endif
1042	}
1043	else
1044	*pu32 = false;
1045	break;
1046
1047	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1048	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1049	*pu32 = pThis->svga.u32GuestId;
1050	break;
1051
1052	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1054	*pu32 = pThis->svga.cScratchRegion;
1055	break;
1056
1057	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1059	*pu32 = SVGA_FIFO_NUM_REGS;
1060	break;
1061
1062	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1063	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1064	*pu32 = pThis->svga.u32PitchLock;
1065	break;
1066
1067	case SVGA_REG_IRQMASK: /* Interrupt mask */
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1069	*pu32 = pThis->svga.u32IrqMask;
1070	break;
1071
1072	/* See "Guest memory regions" below. */
1073	case SVGA_REG_GMR_ID:
1074	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1075	*pu32 = pThis->svga.u32CurrentGMRId;
1076	break;
1077
1078	case SVGA_REG_GMR_DESCRIPTOR:
1079	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1080	/* Write only */
1081	*pu32 = 0;
1082	break;
1083
1084	case SVGA_REG_GMR_MAX_IDS:
1085	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1086	*pu32 = VMSVGA_MAX_GMR_IDS;
1087	break;
1088
1089	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1090	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1091	*pu32 = VMSVGA_MAX_GMR_PAGES;
1092	break;
1093
1094	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1095	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1096	*pu32 = pThis->svga.fTraces;
1097	break;
1098
1099	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1100	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1101	*pu32 = VMSVGA_MAX_GMR_PAGES;
1102	break;
1103
1104	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1105	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1106	*pu32 = VMSVGA_SURFACE_SIZE;
1107	break;
1108
1109	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1110	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1111	break;
1112
1113	/* Mouse cursor support. */
1114	case SVGA_REG_CURSOR_ID:
1115	case SVGA_REG_CURSOR_X:
1116	case SVGA_REG_CURSOR_Y:
1117	case SVGA_REG_CURSOR_ON:
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1119	break;
1120
1121	/* Legacy multi-monitor support */
1122	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1123	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1124	*pu32 = 1;
1125	break;
1126
1127	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1129	*pu32 = 0;
1130	break;
1131
1132	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1134	*pu32 = 0;
1135	break;
1136
1137	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1139	*pu32 = 0;
1140	break;
1141
1142	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1144	*pu32 = 0;
1145	break;
1146
1147	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1149	*pu32 = pThis->svga.uWidth;
1150	break;
1151
1152	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1154	*pu32 = pThis->svga.uHeight;
1155	break;
1156
1157	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1159	pu32 = 1; / Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
1160	break;
1161
1162	default:
1163	{
1164	uint32_t offReg;
1165	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1166	{
1167	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1169	}
1170	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1171	{
1172	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1174	uint32_t u32 = pThis->last_palette[offReg / 3];
1175	switch (offReg % 3)
1176	{
1177	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1178	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1179	case 2: pu32 = u32 & 0xff; break; / blue */
1180	}
1181	}
1182	else
1183	{
1184	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1185	rc = VINF_IOM_R3_IOPORT_READ;
1186	#else
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1188	AssertMsgFailed(("reg=%#x\n", idxReg));
1189	#endif
1190	}
1191	break;
1192	}
1193	}
1194	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1195	return rc;
1196	}
1197
1198	#ifdef IN_RING3
1199	/**
1200	* Apply the current resolution settings to change the video mode.
1201	*
1202	* @returns VBox status code.
1203	* @param pThis VMSVGA State
1204	*/
1205	int vmsvgaChangeMode(PVGASTATE pThis)
1206	{
1207	int rc;
1208
1209	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1210	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1211	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1212	{
1213	/* Mode change in progress; wait for all values to be set. */
1214	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1215	return VINF_SUCCESS;
1216	}
1217
1218	if ( pThis->svga.uWidth == 0
1219	\|\| pThis->svga.uHeight == 0
1220	\|\| pThis->svga.uBpp == 0)
1221	{
1222	/* Invalid mode change - BB does this early in the boot up. */
1223	Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1224	return VINF_SUCCESS;
1225	}
1226
1227	if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1228	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1229	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1230	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1231	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1232	)
1233	{
1234	/* Nothing to do. */
1235	Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1236	return VINF_SUCCESS;
1237	}
1238
1239	Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1240	pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1241
1242	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1243	rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1244	AssertRC(rc);
1245	AssertReturn(rc == VINF_SUCCESS \|\| rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1246
1247	/* last stuff */
1248	pThis->last_bpp = pThis->svga.uBpp;
1249	pThis->last_scr_width = pThis->svga.uWidth;
1250	pThis->last_scr_height = pThis->svga.uHeight;
1251	pThis->last_width = pThis->svga.uWidth;
1252	pThis->last_height = pThis->svga.uHeight;
1253
1254	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1255
1256	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1257	if ( pThis->svga.viewport.cx == 0
1258	&& pThis->svga.viewport.cy == 0)
1259	{
1260	pThis->svga.viewport.cx = pThis->svga.uWidth;
1261	pThis->svga.viewport.xRight = pThis->svga.uWidth;
1262	pThis->svga.viewport.cy = pThis->svga.uHeight;
1263	pThis->svga.viewport.yHighWC = pThis->svga.uHeight;
1264	pThis->svga.viewport.yLowWC = 0;
1265	}
1266	return VINF_SUCCESS;
1267	}
1268	#endif /* IN_RING3 */
1269
1270	#if defined(IN_RING0) \|\| defined(IN_RING3)
1271	/**
1272	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1273	*
1274	* @param pThis The VMSVGA state.
1275	* @param fState The busy state.
1276	*/
1277	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1278	{
1279	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1280
1281	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1282	{
1283	/* Race / unfortunately scheduling. Highly unlikly. */
1284	uint32_t cLoops = 64;
1285	do
1286	{
1287	ASMNopPause();
1288	fState = (pThis->svga.fBusy != 0);
1289	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1290	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1291	}
1292	}
1293	#endif
1294
1295	/**
1296	* Write port register
1297	*
1298	* @returns VBox status code.
1299	* @param pThis VMSVGA State
1300	* @param u32 Value to write
1301	*/
1302	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1303	{
1304	#ifdef IN_RING3
1305	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1306	#endif
1307	int rc = VINF_SUCCESS;
1308
1309	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1310	uint32_t idxReg = pThis->svga.u32IndexReg;
1311	if ( idxReg >= SVGA_REG_CAPABILITIES
1312	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1313	{
1314	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1315	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1316	}
1317	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1318	switch (idxReg)
1319	{
1320	case SVGA_REG_ID:
1321	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1322	if ( u32 == SVGA_ID_0
1323	\|\| u32 == SVGA_ID_1
1324	\|\| u32 == SVGA_ID_2)
1325	pThis->svga.u32SVGAId = u32;
1326	else
1327	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1328	break;
1329
1330	case SVGA_REG_ENABLE:
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1332	if ( pThis->svga.fEnabled == u32
1333	&& pThis->last_bpp == (unsigned)pThis->svga.uBpp
1334	&& pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1335	&& pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1336	&& pThis->last_width == (unsigned)pThis->svga.uWidth
1337	&& pThis->last_height == (unsigned)pThis->svga.uHeight
1338	)
1339	/* Nothing to do. */
1340	break;
1341
1342	#ifdef IN_RING3
1343	if ( u32 == 1
1344	&& pThis->svga.fEnabled == false)
1345	{
1346	/* Make a backup copy of the first 512kb in order to save font data etc. */
1347	/** @todo should probably swap here, rather than copy + zero */
1348	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1349	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1350	}
1351
1352	pThis->svga.fEnabled = u32;
1353	if (pThis->svga.fEnabled)
1354	{
1355	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1356	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1357	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1358	{
1359	/* Keep the current mode. */
1360	pThis->svga.uWidth = pThis->pDrv->cx;
1361	pThis->svga.uHeight = pThis->pDrv->cy;
1362	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1363	}
1364
1365	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1366	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1367	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1368	{
1369	rc = vmsvgaChangeMode(pThis);
1370	AssertRCReturn(rc, rc);
1371	}
1372	# ifdef LOG_ENABLED
1373	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1374	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1375	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1376	# endif
1377
1378	/* Disable or enable dirty page tracking according to the current fTraces value. */
1379	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1380	}
1381	else
1382	{
1383	/* Restore the text mode backup. */
1384	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1385
1386	/* pThis->svga.uHeight = -1;
1387	pThis->svga.uWidth = -1;
1388	pThis->svga.uBpp = -1;
1389	pThis->svga.cbScanline = 0; */
1390	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1391
1392	/* Enable dirty page tracking again when going into legacy mode. */
1393	vmsvgaSetTraces(pThis, true);
1394	}
1395	#else /* !IN_RING3 */
1396	rc = VINF_IOM_R3_IOPORT_WRITE;
1397	#endif /* !IN_RING3 */
1398	break;
1399
1400	case SVGA_REG_WIDTH:
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1402	if (pThis->svga.uWidth != u32)
1403	{
1404	if (pThis->svga.fEnabled)
1405	{
1406	#ifdef IN_RING3
1407	pThis->svga.uWidth = u32;
1408	rc = vmsvgaChangeMode(pThis);
1409	AssertRCReturn(rc, rc);
1410	#else
1411	rc = VINF_IOM_R3_IOPORT_WRITE;
1412	#endif
1413	}
1414	else
1415	pThis->svga.uWidth = u32;
1416	}
1417	/* else: nop */
1418	break;
1419
1420	case SVGA_REG_HEIGHT:
1421	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1422	if (pThis->svga.uHeight != u32)
1423	{
1424	if (pThis->svga.fEnabled)
1425	{
1426	#ifdef IN_RING3
1427	pThis->svga.uHeight = u32;
1428	rc = vmsvgaChangeMode(pThis);
1429	AssertRCReturn(rc, rc);
1430	#else
1431	rc = VINF_IOM_R3_IOPORT_WRITE;
1432	#endif
1433	}
1434	else
1435	pThis->svga.uHeight = u32;
1436	}
1437	/* else: nop */
1438	break;
1439
1440	case SVGA_REG_DEPTH:
1441	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1442	/** @todo read-only?? */
1443	break;
1444
1445	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1446	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1447	if (pThis->svga.uBpp != u32)
1448	{
1449	if (pThis->svga.fEnabled)
1450	{
1451	#ifdef IN_RING3
1452	pThis->svga.uBpp = u32;
1453	rc = vmsvgaChangeMode(pThis);
1454	AssertRCReturn(rc, rc);
1455	#else
1456	rc = VINF_IOM_R3_IOPORT_WRITE;
1457	#endif
1458	}
1459	else
1460	pThis->svga.uBpp = u32;
1461	}
1462	/* else: nop */
1463	break;
1464
1465	case SVGA_REG_PSEUDOCOLOR:
1466	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1467	break;
1468
1469	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1470	#ifdef IN_RING3
1471	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1472	pThis->svga.fConfigured = u32;
1473	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1474	if (!pThis->svga.fConfigured)
1475	{
1476	pThis->svga.fTraces = true;
1477	}
1478	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1479	#else
1480	rc = VINF_IOM_R3_IOPORT_WRITE;
1481	#endif
1482	break;
1483
1484	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1485	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1486	if ( pThis->svga.fEnabled
1487	&& pThis->svga.fConfigured)
1488	{
1489	#if defined(IN_RING3) \|\| defined(IN_RING0)
1490	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1491	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1492	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1493	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1494
1495	/* Kick the FIFO thread to start processing commands again. */
1496	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1497	#else
1498	rc = VINF_IOM_R3_IOPORT_WRITE;
1499	#endif
1500	}
1501	/* else nothing to do. */
1502	else
1503	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1504
1505	break;
1506
1507	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1508	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1509	break;
1510
1511	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1512	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1513	pThis->svga.u32GuestId = u32;
1514	break;
1515
1516	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1517	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1518	pThis->svga.u32PitchLock = u32;
1519	break;
1520
1521	case SVGA_REG_IRQMASK: /* Interrupt mask */
1522	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1523	pThis->svga.u32IrqMask = u32;
1524
1525	/* Irq pending after the above change? */
1526	if (pThis->svga.u32IrqStatus & u32)
1527	{
1528	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1529	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1530	}
1531	else
1532	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1533	break;
1534
1535	/* Mouse cursor support */
1536	case SVGA_REG_CURSOR_ID:
1537	case SVGA_REG_CURSOR_X:
1538	case SVGA_REG_CURSOR_Y:
1539	case SVGA_REG_CURSOR_ON:
1540	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1541	break;
1542
1543	/* Legacy multi-monitor support */
1544	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1545	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1546	break;
1547	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1548	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1549	break;
1550	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1551	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1552	break;
1553	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1554	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1555	break;
1556	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1557	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1558	break;
1559	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1560	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1561	break;
1562	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1563	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1564	break;
1565	#ifdef VBOX_WITH_VMSVGA3D
1566	/* See "Guest memory regions" below. */
1567	case SVGA_REG_GMR_ID:
1568	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1569	pThis->svga.u32CurrentGMRId = u32;
1570	break;
1571
1572	case SVGA_REG_GMR_DESCRIPTOR:
1573	# ifndef IN_RING3
1574	rc = VINF_IOM_R3_IOPORT_WRITE;
1575	break;
1576	# else /* IN_RING3 */
1577	{
1578	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1579
1580	/* Validate current GMR id. */
1581	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1582	AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1583
1584	/* Free the old GMR if present. */
1585	vmsvgaGMRFree(pThis, idGMR);
1586
1587	/* Just undefine the GMR? */
1588	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1589	if (GCPhys == 0)
1590	{
1591	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1592	break;
1593	}
1594
1595
1596	/* Never cross a page boundary automatically. */
1597	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1598	uint32_t cPagesTotal = 0;
1599	uint32_t iDesc = 0;
1600	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1601	uint32_t cLoops = 0;
1602	RTGCPHYS GCPhysBase = GCPhys;
1603	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1604	{
1605	/* Read descriptor. */
1606	SVGAGuestMemDescriptor desc;
1607	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1608	AssertRCBreak(rc);
1609
1610	if (desc.numPages != 0)
1611	{
1612	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1613	cPagesTotal += desc.numPages;
1614	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1615
1616	if ((iDesc & 15) == 0)
1617	{
1618	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1619	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1620	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1621	}
1622
1623	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1624	paDescs[iDesc++].numPages = desc.numPages;
1625
1626	/* Continue with the next descriptor. */
1627	GCPhys += sizeof(desc);
1628	}
1629	else if (desc.ppn == 0)
1630	break; /* terminator */
1631	else /* Pointer to the next physical page of descriptors. */
1632	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1633
1634	cLoops++;
1635	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1636	}
1637
1638	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1639	if (RT_SUCCESS(rc))
1640	{
1641	/* Commit the GMR. */
1642	pSVGAState->aGMR[idGMR].paDesc = paDescs;
1643	pSVGAState->aGMR[idGMR].numDescriptors = iDesc;
1644	pSVGAState->aGMR[idGMR].cMaxPages = cPagesTotal;
1645	pSVGAState->aGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1646	Assert((pSVGAState->aGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1647	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1648	idGMR, iDesc, pSVGAState->aGMR[idGMR].cbTotal, cPagesTotal));
1649	}
1650	else
1651	{
1652	RTMemFree(paDescs);
1653	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1654	}
1655	break;
1656	}
1657	# endif /* IN_RING3 */
1658	#endif // VBOX_WITH_VMSVGA3D
1659
1660	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1661	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1662	if (pThis->svga.fTraces == u32)
1663	break; /* nothing to do */
1664
1665	#ifdef IN_RING3
1666	vmsvgaSetTraces(pThis, !!u32);
1667	#else
1668	rc = VINF_IOM_R3_IOPORT_WRITE;
1669	#endif
1670	break;
1671
1672	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1673	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1674	break;
1675
1676	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1677	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1678	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1679	break;
1680
1681	case SVGA_REG_FB_START:
1682	case SVGA_REG_MEM_START:
1683	case SVGA_REG_HOST_BITS_PER_PIXEL:
1684	case SVGA_REG_MAX_WIDTH:
1685	case SVGA_REG_MAX_HEIGHT:
1686	case SVGA_REG_VRAM_SIZE:
1687	case SVGA_REG_FB_SIZE:
1688	case SVGA_REG_CAPABILITIES:
1689	case SVGA_REG_MEM_SIZE:
1690	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1691	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1692	case SVGA_REG_BYTES_PER_LINE:
1693	case SVGA_REG_FB_OFFSET:
1694	case SVGA_REG_RED_MASK:
1695	case SVGA_REG_GREEN_MASK:
1696	case SVGA_REG_BLUE_MASK:
1697	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1698	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1699	case SVGA_REG_GMR_MAX_IDS:
1700	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1701	/* Read only - ignore. */
1702	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1703	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1704	break;
1705
1706	default:
1707	{
1708	uint32_t offReg;
1709	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1710	{
1711	pThis->svga.au32ScratchRegion[offReg] = u32;
1712	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1713	}
1714	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1715	{
1716	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1717	Btw, see rgb_to_pixel32. */
1718	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1719	u32 &= 0xff;
1720	uint32_t uRgb = pThis->last_palette[offReg / 3];
1721	switch (offReg % 3)
1722	{
1723	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1724	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1725	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1726	}
1727	pThis->last_palette[offReg / 3] = uRgb;
1728	}
1729	else
1730	{
1731	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1732	rc = VINF_IOM_R3_IOPORT_WRITE;
1733	#else
1734	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1735	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1736	#endif
1737	}
1738	break;
1739	}
1740	}
1741	return rc;
1742	}
1743
1744	/**
1745	* Port I/O Handler for IN operations.
1746	*
1747	* @returns VINF_SUCCESS or VINF_EM_*.
1748	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1749	*
1750	* @param pDevIns The device instance.
1751	* @param pvUser User argument.
1752	* @param uPort Port number used for the IN operation.
1753	* @param pu32 Where to store the result. This is always a 32-bit
1754	* variable regardless of what @a cb might say.
1755	* @param cb Number of bytes read.
1756	*/
1757	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1758	{
1759	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1760	RT_NOREF_PV(pvUser);
1761
1762	/* Ignore non-dword accesses. */
1763	if (cb != 4)
1764	{
1765	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1766	*pu32 = UINT32_MAX;
1767	return VINF_SUCCESS;
1768	}
1769
1770	switch (uPort - pThis->svga.BasePort)
1771	{
1772	case SVGA_INDEX_PORT:
1773	*pu32 = pThis->svga.u32IndexReg;
1774	break;
1775
1776	case SVGA_VALUE_PORT:
1777	return vmsvgaReadPort(pThis, pu32);
1778
1779	case SVGA_BIOS_PORT:
1780	Log(("Ignoring BIOS port read\n"));
1781	*pu32 = 0;
1782	break;
1783
1784	case SVGA_IRQSTATUS_PORT:
1785	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1786	*pu32 = pThis->svga.u32IrqStatus;
1787	break;
1788	}
1789
1790	return VINF_SUCCESS;
1791	}
1792
1793	/**
1794	* Port I/O Handler for OUT operations.
1795	*
1796	* @returns VINF_SUCCESS or VINF_EM_*.
1797	*
1798	* @param pDevIns The device instance.
1799	* @param pvUser User argument.
1800	* @param uPort Port number used for the OUT operation.
1801	* @param u32 The value to output.
1802	* @param cb The value size in bytes.
1803	*/
1804	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1805	{
1806	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1807	RT_NOREF_PV(pvUser);
1808
1809	/* Ignore non-dword accesses. */
1810	if (cb != 4)
1811	{
1812	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1813	return VINF_SUCCESS;
1814	}
1815
1816	switch (uPort - pThis->svga.BasePort)
1817	{
1818	case SVGA_INDEX_PORT:
1819	pThis->svga.u32IndexReg = u32;
1820	break;
1821
1822	case SVGA_VALUE_PORT:
1823	return vmsvgaWritePort(pThis, u32);
1824
1825	case SVGA_BIOS_PORT:
1826	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1827	break;
1828
1829	case SVGA_IRQSTATUS_PORT:
1830	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1831	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1832	/* Clear the irq in case all events have been cleared. */
1833	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1834	{
1835	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1836	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1837	}
1838	break;
1839	}
1840	return VINF_SUCCESS;
1841	}
1842
1843	#ifdef DEBUG_FIFO_ACCESS
1844
1845	# ifdef IN_RING3
1846	/**
1847	* Handle LFB access.
1848	* @returns VBox status code.
1849	* @param pVM VM handle.
1850	* @param pThis VGA device instance data.
1851	* @param GCPhys The access physical address.
1852	* @param fWriteAccess Read or write access
1853	*/
1854	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1855	{
1856	RT_NOREF(pVM);
1857	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1858	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1859
1860	switch (GCPhysOffset >> 2)
1861	{
1862	case SVGA_FIFO_MIN:
1863	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1864	break;
1865	case SVGA_FIFO_MAX:
1866	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1867	break;
1868	case SVGA_FIFO_NEXT_CMD:
1869	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1870	break;
1871	case SVGA_FIFO_STOP:
1872	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1873	break;
1874	case SVGA_FIFO_CAPABILITIES:
1875	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1876	break;
1877	case SVGA_FIFO_FLAGS:
1878	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1879	break;
1880	case SVGA_FIFO_FENCE:
1881	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1882	break;
1883	case SVGA_FIFO_3D_HWVERSION:
1884	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1885	break;
1886	case SVGA_FIFO_PITCHLOCK:
1887	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1888	break;
1889	case SVGA_FIFO_CURSOR_ON:
1890	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1891	break;
1892	case SVGA_FIFO_CURSOR_X:
1893	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1894	break;
1895	case SVGA_FIFO_CURSOR_Y:
1896	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1897	break;
1898	case SVGA_FIFO_CURSOR_COUNT:
1899	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1900	break;
1901	case SVGA_FIFO_CURSOR_LAST_UPDATED:
1902	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1903	break;
1904	case SVGA_FIFO_RESERVED:
1905	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1906	break;
1907	case SVGA_FIFO_CURSOR_SCREEN_ID:
1908	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1909	break;
1910	case SVGA_FIFO_DEAD:
1911	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1912	break;
1913	case SVGA_FIFO_3D_HWVERSION_REVISED:
1914	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1915	break;
1916	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1917	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1918	break;
1919	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1920	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1921	break;
1922	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1923	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1924	break;
1925	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1926	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1927	break;
1928	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1929	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1930	break;
1931	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1932	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1933	break;
1934	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1935	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1936	break;
1937	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1938	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1939	break;
1940	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1941	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1942	break;
1943	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1944	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1945	break;
1946	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1947	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1948	break;
1949	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1950	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1951	break;
1952	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1953	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1954	break;
1955	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1956	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1957	break;
1958	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1959	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1960	break;
1961	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1962	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1963	break;
1964	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1965	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1966	break;
1967	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1968	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1969	break;
1970	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1971	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1972	break;
1973	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1974	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1975	break;
1976	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1977	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1978	break;
1979	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1980	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1981	break;
1982	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1983	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1984	break;
1985	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1986	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1987	break;
1988	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1989	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1990	break;
1991	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1992	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1993	break;
1994	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1995	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1996	break;
1997	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1998	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1999	break;
2000	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2001	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2002	break;
2003	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2004	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2005	break;
2006	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2007	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2008	break;
2009	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2010	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2011	break;
2012	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2013	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2014	break;
2015	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2016	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2017	break;
2018	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2019	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2020	break;
2021	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2022	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2023	break;
2024	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2025	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2026	break;
2027	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2028	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2029	break;
2030	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2031	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2032	break;
2033	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2034	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2035	break;
2036	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2037	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2038	break;
2039	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2040	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2041	break;
2042	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2043	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2044	break;
2045	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2046	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2047	break;
2048	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2049	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2050	break;
2051	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2052	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2053	break;
2054	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS_LAST:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_GUEST_3D_HWVERSION:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_FENCE_GOAL:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_BUSY:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	default:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	}
2181
2182	return VINF_EM_RAW_EMULATE_INSTR;
2183	}
2184
2185	/**
2186	* HC access handler for the FIFO.
2187	*
2188	* @returns VINF_SUCCESS if the handler have carried out the operation.
2189	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2190	* @param pVM VM Handle.
2191	* @param pVCpu The cross context CPU structure for the calling EMT.
2192	* @param GCPhys The physical address the guest is writing to.
2193	* @param pvPhys The HC mapping of that address.
2194	* @param pvBuf What the guest is reading/writing.
2195	* @param cbBuf How much it's reading/writing.
2196	* @param enmAccessType The access type.
2197	* @param enmOrigin Who is making the access.
2198	* @param pvUser User argument.
2199	*/
2200	static DECLCALLBACK(VBOXSTRICTRC)
2201	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2202	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2203	{
2204	PVGASTATE pThis = (PVGASTATE)pvUser;
2205	int rc;
2206	Assert(pThis);
2207	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2208	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2209
2210	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2211	if (RT_SUCCESS(rc))
2212	return VINF_PGM_HANDLER_DO_DEFAULT;
2213	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2214	return rc;
2215	}
2216
2217	# endif /* IN_RING3 */
2218	#endif /* DEBUG_FIFO_ACCESS */
2219
2220	#ifdef DEBUG_GMR_ACCESS
2221	# ifdef IN_RING3
2222
2223	/**
2224	* HC access handler for the FIFO.
2225	*
2226	* @returns VINF_SUCCESS if the handler have carried out the operation.
2227	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2228	* @param pVM VM Handle.
2229	* @param pVCpu The cross context CPU structure for the calling EMT.
2230	* @param GCPhys The physical address the guest is writing to.
2231	* @param pvPhys The HC mapping of that address.
2232	* @param pvBuf What the guest is reading/writing.
2233	* @param cbBuf How much it's reading/writing.
2234	* @param enmAccessType The access type.
2235	* @param enmOrigin Who is making the access.
2236	* @param pvUser User argument.
2237	*/
2238	static DECLCALLBACK(VBOXSTRICTRC)
2239	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2240	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2241	{
2242	PVGASTATE pThis = (PVGASTATE)pvUser;
2243	Assert(pThis);
2244	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2245	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2246
2247	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2248
2249	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2250	{
2251	PGMR pGMR = &pSVGAState->aGMR[i];
2252
2253	if (pGMR->numDescriptors)
2254	{
2255	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2256	{
2257	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2258	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2259	{
2260	/*
2261	* Turn off the write handler for this particular page and make it R/W.
2262	* Then return telling the caller to restart the guest instruction.
2263	*/
2264	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2265	AssertRC(rc);
2266	goto end;
2267	}
2268	}
2269	}
2270	}
2271	end:
2272	return VINF_PGM_HANDLER_DO_DEFAULT;
2273	}
2274
2275	/* Callback handler for VMR3ReqCallWaitU */
2276	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2277	{
2278	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2279	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2280	PGMR pGMR = &pSVGAState->aGMR[gmrId];
2281	int rc;
2282
2283	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2284	{
2285	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2286	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2287	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2288	AssertRC(rc);
2289	}
2290	return VINF_SUCCESS;
2291	}
2292
2293	/* Callback handler for VMR3ReqCallWaitU */
2294	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2295	{
2296	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2297	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2298	PGMR pGMR = &pSVGAState->aGMR[gmrId];
2299
2300	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2301	{
2302	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2303	AssertRC(rc);
2304	}
2305	return VINF_SUCCESS;
2306	}
2307
2308	/* Callback handler for VMR3ReqCallWaitU */
2309	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2310	{
2311	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2312
2313	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2314	{
2315	PGMR pGMR = &pSVGAState->aGMR[i];
2316
2317	if (pGMR->numDescriptors)
2318	{
2319	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2320	{
2321	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2322	AssertRC(rc);
2323	}
2324	}
2325	}
2326	return VINF_SUCCESS;
2327	}
2328
2329	# endif /* IN_RING3 */
2330	#endif /* DEBUG_GMR_ACCESS */
2331
2332	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2333
2334	#ifdef IN_RING3
2335
2336
2337	/**
2338	* Common worker for changing the pointer shape.
2339	*
2340	* @param pThis The VGA instance data.
2341	* @param pSVGAState The VMSVGA ring-3 instance data.
2342	* @param fAlpha Whether there is alpha or not.
2343	* @param xHot Hotspot x coordinate.
2344	* @param yHot Hotspot y coordinate.
2345	* @param cx Width.
2346	* @param cy Height.
2347	* @param pbData Heap copy of the cursor data. Consumed.
2348	* @param cbData The size of the data.
2349	*/
2350	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2351	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2352	{
2353	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2354	#ifdef LOG_ENABLED
2355	if (LogIs2Enabled())
2356	{
2357	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2358	if (!fAlpha)
2359	{
2360	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2361	for (uint32_t y = 0; y < cy; y++)
2362	{
2363	Log2(("%3u:", y));
2364	uint8_t const pbLine = &pbData[y cbAndLine];
2365	for (uint32_t x = 0; x < cx; x += 8)
2366	{
2367	uint8_t b = pbLine[x / 8];
2368	char szByte[12];
2369	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2370	szByte[1] = b & 0x40 ? '*' : ' ';
2371	szByte[2] = b & 0x20 ? '*' : ' ';
2372	szByte[3] = b & 0x10 ? '*' : ' ';
2373	szByte[4] = b & 0x08 ? '*' : ' ';
2374	szByte[5] = b & 0x04 ? '*' : ' ';
2375	szByte[6] = b & 0x02 ? '*' : ' ';
2376	szByte[7] = b & 0x01 ? '*' : ' ';
2377	szByte[8] = '\0';
2378	Log2(("%s", szByte));
2379	}
2380	Log2(("\n"));
2381	}
2382	}
2383
2384	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2385	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2386	for (uint32_t y = 0; y < cy; y++)
2387	{
2388	Log2(("%3u:", y));
2389	uint32_t const pu32Line = &pu32Xor[y cx];
2390	for (uint32_t x = 0; x < cx; x++)
2391	Log2((" %08x", pu32Line[x]));
2392	Log2(("\n"));
2393	}
2394	}
2395	#endif
2396
2397	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2398	AssertRC(rc);
2399
2400	if (pSVGAState->Cursor.fActive)
2401	RTMemFree(pSVGAState->Cursor.pData);
2402
2403	pSVGAState->Cursor.fActive = true;
2404	pSVGAState->Cursor.xHotspot = xHot;
2405	pSVGAState->Cursor.yHotspot = yHot;
2406	pSVGAState->Cursor.width = cx;
2407	pSVGAState->Cursor.height = cy;
2408	pSVGAState->Cursor.cbData = cbData;
2409	pSVGAState->Cursor.pData = pbData;
2410	}
2411
2412
2413	/**
2414	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2415	*
2416	* @param pThis The VGA instance data.
2417	* @param pSVGAState The VMSVGA ring-3 instance data.
2418	* @param pCursor The cursor.
2419	* @param pbSrcAndMask The AND mask.
2420	* @param cbSrcAndLine The scanline length of the AND mask.
2421	* @param pbSrcXorMask The XOR mask.
2422	* @param cbSrcXorLine The scanline length of the XOR mask.
2423	*/
2424	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2425	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2426	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2427	{
2428	uint32_t const cx = pCursor->width;
2429	uint32_t const cy = pCursor->height;
2430
2431	/*
2432	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2433	* The AND data uses 8-bit aligned scanlines.
2434	* The XOR data must be starting on a 32-bit boundrary.
2435	*/
2436	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2437	uint32_t cbDstAndMask = cbDstAndLine * cy;
2438	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2439	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2440
2441	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2442	AssertReturnVoid(pbCopy);
2443
2444	/* Convert the AND mask. */
2445	uint8_t *pbDst = pbCopy;
2446	uint8_t const *pbSrc = pbSrcAndMask;
2447	switch (pCursor->andMaskDepth)
2448	{
2449	case 1:
2450	if (cbSrcAndLine == cbDstAndLine)
2451	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2452	else
2453	{
2454	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2455	for (uint32_t y = 0; y < cy; y++)
2456	{
2457	memcpy(pbDst, pbSrc, cbDstAndLine);
2458	pbDst += cbDstAndLine;
2459	pbSrc += cbSrcAndLine;
2460	}
2461	}
2462	break;
2463	/* Should take the XOR mask into account for the multi-bit AND mask. */
2464	case 8:
2465	for (uint32_t y = 0; y < cy; y++)
2466	{
2467	for (uint32_t x = 0; x < cx; )
2468	{
2469	uint8_t bDst = 0;
2470	uint8_t fBit = 1;
2471	do
2472	{
2473	uintptr_t const idxPal = pbSrc[x] * 3;
2474	if ((( pThis->last_palette[idxPal]
2475	\| (pThis->last_palette[idxPal] >> 8)
2476	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2477	bDst \|= fBit;
2478	fBit <<= 1;
2479	x++;
2480	} while (x < cx && (x & 7));
2481	pbDst[(x - 1) / 8] = bDst;
2482	}
2483	pbDst += cbDstAndLine;
2484	pbSrc += cbSrcAndLine;
2485	}
2486	break;
2487	case 15:
2488	for (uint32_t y = 0; y < cy; y++)
2489	{
2490	for (uint32_t x = 0; x < cx; )
2491	{
2492	uint8_t bDst = 0;
2493	uint8_t fBit = 1;
2494	do
2495	{
2496	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2497	bDst \|= fBit;
2498	fBit <<= 1;
2499	x++;
2500	} while (x < cx && (x & 7));
2501	pbDst[(x - 1) / 8] = bDst;
2502	}
2503	pbDst += cbDstAndLine;
2504	pbSrc += cbSrcAndLine;
2505	}
2506	break;
2507	case 16:
2508	for (uint32_t y = 0; y < cy; y++)
2509	{
2510	for (uint32_t x = 0; x < cx; )
2511	{
2512	uint8_t bDst = 0;
2513	uint8_t fBit = 1;
2514	do
2515	{
2516	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2517	bDst \|= fBit;
2518	fBit <<= 1;
2519	x++;
2520	} while (x < cx && (x & 7));
2521	pbDst[(x - 1) / 8] = bDst;
2522	}
2523	pbDst += cbDstAndLine;
2524	pbSrc += cbSrcAndLine;
2525	}
2526	break;
2527	case 24:
2528	for (uint32_t y = 0; y < cy; y++)
2529	{
2530	for (uint32_t x = 0; x < cx; )
2531	{
2532	uint8_t bDst = 0;
2533	uint8_t fBit = 1;
2534	do
2535	{
2536	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2537	bDst \|= fBit;
2538	fBit <<= 1;
2539	x++;
2540	} while (x < cx && (x & 7));
2541	pbDst[(x - 1) / 8] = bDst;
2542	}
2543	pbDst += cbDstAndLine;
2544	pbSrc += cbSrcAndLine;
2545	}
2546	break;
2547	case 32:
2548	for (uint32_t y = 0; y < cy; y++)
2549	{
2550	for (uint32_t x = 0; x < cx; )
2551	{
2552	uint8_t bDst = 0;
2553	uint8_t fBit = 1;
2554	do
2555	{
2556	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2557	bDst \|= fBit;
2558	fBit <<= 1;
2559	x++;
2560	} while (x < cx && (x & 7));
2561	pbDst[(x - 1) / 8] = bDst;
2562	}
2563	pbDst += cbDstAndLine;
2564	pbSrc += cbSrcAndLine;
2565	}
2566	break;
2567	default:
2568	RTMemFree(pbCopy);
2569	AssertFailedReturnVoid();
2570	}
2571
2572	/* Convert the XOR mask. */
2573	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2574	pbSrc = pbSrcXorMask;
2575	switch (pCursor->xorMaskDepth)
2576	{
2577	case 1:
2578	for (uint32_t y = 0; y < cy; y++)
2579	{
2580	for (uint32_t x = 0; x < cx; )
2581	{
2582	/* most significant bit is the left most one. */
2583	uint8_t bSrc = pbSrc[x / 8];
2584	do
2585	{
2586	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2587	bSrc <<= 1;
2588	x++;
2589	} while ((x & 7) && x < cx);
2590	}
2591	pbSrc += cbSrcXorLine;
2592	}
2593	break;
2594	case 8:
2595	for (uint32_t y = 0; y < cy; y++)
2596	{
2597	for (uint32_t x = 0; x < cx; x++)
2598	{
2599	uint32_t u = pThis->last_palette[pbSrc[x]];
2600	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2601	}
2602	pbSrc += cbSrcXorLine;
2603	}
2604	break;
2605	case 15: /* Src: RGB-5-5-5 */
2606	for (uint32_t y = 0; y < cy; y++)
2607	{
2608	for (uint32_t x = 0; x < cx; x++)
2609	{
2610	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2611	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2612	((uValue >> 5) & 0x1f) << 3,
2613	((uValue >> 10) & 0x1f) << 3, 0);
2614	}
2615	pbSrc += cbSrcXorLine;
2616	}
2617	break;
2618	case 16: /* Src: RGB-5-6-5 */
2619	for (uint32_t y = 0; y < cy; y++)
2620	{
2621	for (uint32_t x = 0; x < cx; x++)
2622	{
2623	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2624	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2625	((uValue >> 5) & 0x3f) << 2,
2626	((uValue >> 11) & 0x1f) << 3, 0);
2627	}
2628	pbSrc += cbSrcXorLine;
2629	}
2630	break;
2631	case 24:
2632	for (uint32_t y = 0; y < cy; y++)
2633	{
2634	for (uint32_t x = 0; x < cx; x++)
2635	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2636	pbSrc += cbSrcXorLine;
2637	}
2638	break;
2639	case 32:
2640	for (uint32_t y = 0; y < cy; y++)
2641	{
2642	for (uint32_t x = 0; x < cx; x++)
2643	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2644	pbSrc += cbSrcXorLine;
2645	}
2646	break;
2647	default:
2648	RTMemFree(pbCopy);
2649	AssertFailedReturnVoid();
2650	}
2651
2652	/*
2653	* Pass it to the frontend/whatever.
2654	*/
2655	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2656	}
2657
2658
2659	/**
2660	* Worker for vmsvgaR3FifoThread that handles an external command.
2661	*
2662	* @param pThis VGA device instance data.
2663	*/
2664	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2665	{
2666	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2667	switch (pThis->svga.u8FIFOExtCommand)
2668	{
2669	case VMSVGA_FIFO_EXTCMD_RESET:
2670	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2671	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2672	# ifdef VBOX_WITH_VMSVGA3D
2673	if (pThis->svga.f3DEnabled)
2674	{
2675	/* The 3d subsystem must be reset from the fifo thread. */
2676	vmsvga3dReset(pThis);
2677	}
2678	# endif
2679	break;
2680
2681	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2682	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2683	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2684	# ifdef VBOX_WITH_VMSVGA3D
2685	if (pThis->svga.f3DEnabled)
2686	{
2687	/* The 3d subsystem must be shut down from the fifo thread. */
2688	vmsvga3dTerminate(pThis);
2689	}
2690	# endif
2691	break;
2692
2693	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2694	{
2695	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2696	# ifdef VBOX_WITH_VMSVGA3D
2697	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2698	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2699	vmsvga3dSaveExec(pThis, pSSM);
2700	# endif
2701	break;
2702	}
2703
2704	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2705	{
2706	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2707	# ifdef VBOX_WITH_VMSVGA3D
2708	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2709	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2710	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2711	# endif
2712	break;
2713	}
2714
2715	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2716	{
2717	# ifdef VBOX_WITH_VMSVGA3D
2718	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2719	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2720	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2721	# endif
2722	break;
2723	}
2724
2725
2726	default:
2727	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2728	break;
2729	}
2730
2731	/*
2732	* Signal the end of the external command.
2733	*/
2734	pThis->svga.pvFIFOExtCmdParam = NULL;
2735	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2736	ASMMemoryFence(); /* paranoia^2 */
2737	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2738	AssertLogRelRC(rc);
2739	}
2740
2741	/**
2742	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2743	* doing a job on the FIFO thread (even when it's officially suspended).
2744	*
2745	* @returns VBox status code (fully asserted).
2746	* @param pThis VGA device instance data.
2747	* @param uExtCmd The command to execute on the FIFO thread.
2748	* @param pvParam Pointer to command parameters.
2749	* @param cMsWait The time to wait for the command, given in
2750	* milliseconds.
2751	*/
2752	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2753	{
2754	Assert(cMsWait >= RT_MS_1SEC * 5);
2755	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2756	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2757
2758	int rc;
2759	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2760	PDMTHREADSTATE enmState = pThread->enmState;
2761	if (enmState == PDMTHREADSTATE_SUSPENDED)
2762	{
2763	/*
2764	* The thread is suspended, we have to temporarily wake it up so it can
2765	* perform the task.
2766	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2767	*/
2768	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2769	/* Post the request. */
2770	pThis->svga.fFifoExtCommandWakeup = true;
2771	pThis->svga.pvFIFOExtCmdParam = pvParam;
2772	pThis->svga.u8FIFOExtCommand = uExtCmd;
2773	ASMMemoryFence(); /* paranoia^3 */
2774
2775	/* Resume the thread. */
2776	rc = PDMR3ThreadResume(pThread);
2777	AssertLogRelRC(rc);
2778	if (RT_SUCCESS(rc))
2779	{
2780	/* Wait. Take care in case the semaphore was already posted (same as below). */
2781	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2782	if ( rc == VINF_SUCCESS
2783	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2784	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2785	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2786	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2787
2788	/* suspend the thread */
2789	pThis->svga.fFifoExtCommandWakeup = false;
2790	int rc2 = PDMR3ThreadSuspend(pThread);
2791	AssertLogRelRC(rc2);
2792	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2793	rc = rc2;
2794	}
2795	pThis->svga.fFifoExtCommandWakeup = false;
2796	pThis->svga.pvFIFOExtCmdParam = NULL;
2797	}
2798	else if (enmState == PDMTHREADSTATE_RUNNING)
2799	{
2800	/*
2801	* The thread is running, should only happen during reset and vmsvga3dsfc.
2802	* We ASSUME not racing code here, both wrt thread state and ext commands.
2803	*/
2804	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2805	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2806
2807	/* Post the request. */
2808	pThis->svga.pvFIFOExtCmdParam = pvParam;
2809	pThis->svga.u8FIFOExtCommand = uExtCmd;
2810	ASMMemoryFence(); /* paranoia^2 */
2811	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2812	AssertLogRelRC(rc);
2813
2814	/* Wait. Take care in case the semaphore was already posted (same as above). */
2815	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2816	if ( rc == VINF_SUCCESS
2817	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2818	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2819	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2820	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2821
2822	pThis->svga.pvFIFOExtCmdParam = NULL;
2823	}
2824	else
2825	{
2826	/*
2827	* Something is wrong with the thread!
2828	*/
2829	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2830	rc = VERR_INVALID_STATE;
2831	}
2832	return rc;
2833	}
2834
2835
2836	/**
2837	* Marks the FIFO non-busy, notifying any waiting EMTs.
2838	*
2839	* @param pThis The VGA state.
2840	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2841	* @param offFifoMin The start byte offset of the command FIFO.
2842	*/
2843	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2844	{
2845	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2846	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2847	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2848
2849	/* Wake up any waiting EMTs. */
2850	if (pSVGAState->cBusyDelayedEmts > 0)
2851	{
2852	#ifdef VMSVGA_USE_EMT_HALT_CODE
2853	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2854	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2855	if (idCpu != NIL_VMCPUID)
2856	{
2857	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2858	while (idCpu-- > 0)
2859	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2860	VMR3NotifyCpuDeviceReady(pVM, idCpu);
2861	}
2862	#else
2863	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2864	AssertRC(rc2);
2865	#endif
2866	}
2867	}
2868
2869	/**
2870	* Reads (more) payload into the command buffer.
2871	*
2872	* @returns pbBounceBuf on success
2873	* @retval (void *)1 if the thread was requested to stop.
2874	* @retval NULL on FIFO error.
2875	*
2876	* @param cbPayloadReq The number of bytes of payload requested.
2877	* @param pFIFO The FIFO.
2878	* @param offCurrentCmd The FIFO byte offset of the current command.
2879	* @param offFifoMin The start byte offset of the command FIFO.
2880	* @param offFifoMax The end byte offset of the command FIFO.
2881	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2882	* always sufficient size.
2883	* @param pcbAlreadyRead How much payload we've already read into the bounce
2884	* buffer. (We will NEVER re-read anything.)
2885	* @param pThread The calling PDM thread handle.
2886	* @param pThis The VGA state.
2887	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2888	* statistics collection.
2889	*/
2890	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile pFIFO,
2891	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2892	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
2893	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2894	{
2895	Assert(pbBounceBuf);
2896	Assert(pcbAlreadyRead);
2897	Assert(offFifoMin < offFifoMax);
2898	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2899	Assert(offFifoMax <= pThis->svga.cbFIFO);
2900
2901	/*
2902	* Check if the requested payload size has already been satisfied .
2903	* .
2904	* When called to read more, the caller is responsible for making sure the .
2905	* new command size (cbRequsted) never is smaller than what has already .
2906	* been read.
2907	*/
2908	uint32_t cbAlreadyRead = *pcbAlreadyRead;
2909	if (cbPayloadReq <= cbAlreadyRead)
2910	{
2911	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2912	return pbBounceBuf;
2913	}
2914
2915	/*
2916	* Commands bigger than the fifo buffer are invalid.
2917	*/
2918	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2919	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2920	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2921	NULL);
2922
2923	/*
2924	* Move offCurrentCmd past the command dword.
2925	*/
2926	offCurrentCmd += sizeof(uint32_t);
2927	if (offCurrentCmd >= offFifoMax)
2928	offCurrentCmd = offFifoMin;
2929
2930	/*
2931	* Do we have sufficient payload data available already?
2932	*/
2933	uint32_t cbAfter, cbBefore;
2934	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2935	if (offNextCmd > offCurrentCmd)
2936	{
2937	if (RT_LIKELY(offNextCmd < offFifoMax))
2938	cbAfter = offNextCmd - offCurrentCmd;
2939	else
2940	{
2941	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2942	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2943	offNextCmd, offFifoMin, offFifoMax));
2944	cbAfter = offFifoMax - offCurrentCmd;
2945	}
2946	cbBefore = 0;
2947	}
2948	else
2949	{
2950	cbAfter = offFifoMax - offCurrentCmd;
2951	if (offNextCmd >= offFifoMin)
2952	cbBefore = offNextCmd - offFifoMin;
2953	else
2954	{
2955	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2956	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2957	offNextCmd, offFifoMin, offFifoMax));
2958	cbBefore = 0;
2959	}
2960	}
2961	if (cbAfter + cbBefore < cbPayloadReq)
2962	{
2963	/*
2964	* Insufficient, must wait for it to arrive.
2965	*/
2966	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
2967	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2968	for (uint32_t i = 0;; i++)
2969	{
2970	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2971	{
2972	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2973	return (void *)(uintptr_t)1;
2974	}
2975	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2976	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2977
2978	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2979
2980	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2981	if (offNextCmd > offCurrentCmd)
2982	{
2983	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2984	cbBefore = 0;
2985	}
2986	else
2987	{
2988	cbAfter = offFifoMax - offCurrentCmd;
2989	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2990	}
2991
2992	if (cbAfter + cbBefore >= cbPayloadReq)
2993	break;
2994	}
2995	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2996	}
2997
2998	/*
2999	* Copy out the memory and update what pcbAlreadyRead points to.
3000	*/
3001	if (cbAfter >= cbPayloadReq)
3002	memcpy(pbBounceBuf + cbAlreadyRead,
3003	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3004	cbPayloadReq - cbAlreadyRead);
3005	else
3006	{
3007	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3008	if (cbAlreadyRead < cbAfter)
3009	{
3010	memcpy(pbBounceBuf + cbAlreadyRead,
3011	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3012	cbAfter - cbAlreadyRead);
3013	cbAlreadyRead = cbAfter;
3014	}
3015	memcpy(pbBounceBuf + cbAlreadyRead,
3016	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3017	cbPayloadReq - cbAlreadyRead);
3018	}
3019	*pcbAlreadyRead = cbPayloadReq;
3020	return pbBounceBuf;
3021	}
3022
3023	/* The async FIFO handling thread. */
3024	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3025	{
3026	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3027	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3028	int rc;
3029
3030	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3031	return VINF_SUCCESS;
3032
3033	/*
3034	* Special mode where we only execute an external command and the go back
3035	* to being suspended. Currently, all ext cmds ends up here, with the reset
3036	* one also being eligble for runtime execution further down as well.
3037	*/
3038	if (pThis->svga.fFifoExtCommandWakeup)
3039	{
3040	vmsvgaR3FifoHandleExtCmd(pThis);
3041	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3042	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3043	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3044	else
3045	vmsvgaR3FifoHandleExtCmd(pThis);
3046	return VINF_SUCCESS;
3047	}
3048
3049
3050	/*
3051	* Signal the semaphore to make sure we don't wait for 250ms after a
3052	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3053	*/
3054	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3055
3056	/*
3057	* Allocate a bounce buffer for command we get from the FIFO.
3058	* (All code must return via the end of the function to free this buffer.)
3059	*/
3060	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3061	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3062
3063	/*
3064	* Polling/sleep interval config.
3065	*
3066	* We wait for an a short interval if the guest has recently given us work
3067	* to do, but the interval increases the longer we're kept idle. With the
3068	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3069	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3070	* 16 seconds.
3071	*/
3072	RTMSINTERVAL const cMsMinSleep = 16;
3073	RTMSINTERVAL const cMsIncSleep = 2;
3074	RTMSINTERVAL const cMsMaxSleep = 250;
3075	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3076
3077	/*
3078	* The FIFO loop.
3079	*/
3080	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3081	bool fBadOrDisabledFifo = false;
3082	uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
3083	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3084	{
3085	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3086	/*
3087	* Should service the run loop every so often.
3088	*/
3089	if (pThis->svga.f3DEnabled)
3090	vmsvga3dCocoaServiceRunLoop();
3091	# endif
3092
3093	/*
3094	* Unless there's already work pending, go to sleep for a short while.
3095	* (See polling/sleep interval config above.)
3096	*/
3097	if ( fBadOrDisabledFifo
3098	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3099	{
3100	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3101	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3102	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3103	{
3104	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3105	break;
3106	}
3107	}
3108	else
3109	rc = VINF_SUCCESS;
3110	fBadOrDisabledFifo = false;
3111	if (rc == VERR_TIMEOUT)
3112	{
3113	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3114	{
3115	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3116	continue;
3117	}
3118	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3119
3120	Log(("vmsvgaFIFOLoop: timeout\n"));
3121	}
3122	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3123	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3124	cMsSleep = cMsMinSleep;
3125
3126	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3127	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3128	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3129
3130	/*
3131	* Handle external commands (currently only reset).
3132	*/
3133	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3134	{
3135	vmsvgaR3FifoHandleExtCmd(pThis);
3136	continue;
3137	}
3138
3139	/*
3140	* The device must be enabled and configured.
3141	*/
3142	if ( !pThis->svga.fEnabled
3143	\|\| !pThis->svga.fConfigured)
3144	{
3145	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3146	fBadOrDisabledFifo = true;
3147	continue;
3148	}
3149
3150	/*
3151	* Get and check the min/max values. We ASSUME that they will remain
3152	* unchanged while we process requests. A further ASSUMPTION is that
3153	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3154	* we don't read it back while in the loop.
3155	*/
3156	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3157	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3158	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3159	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3160	\|\| offFifoMax <= offFifoMin
3161	\|\| offFifoMax > pThis->svga.cbFIFO
3162	\|\| (offFifoMax & 3) != 0
3163	\|\| (offFifoMin & 3) != 0
3164	\|\| offCurrentCmd < offFifoMin
3165	\|\| offCurrentCmd > offFifoMax))
3166	{
3167	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3168	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3169	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3170	fBadOrDisabledFifo = true;
3171	continue;
3172	}
3173	if (RT_UNLIKELY(offCurrentCmd & 3))
3174	{
3175	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3176	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3177	offCurrentCmd = ~UINT32_C(3);
3178	}
3179
3180	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3181	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3182	*
3183	* Will break out of the switch on failure.
3184	* Will restart and quit the loop if the thread was requested to stop.
3185	*
3186	* @param a_PtrVar Request variable pointer.
3187	* @param a_Type Request typedef (not pointer) for casting.
3188	* @param a_cbPayloadReq How much payload to fetch.
3189	* @remarks Accesses a bunch of variables in the current scope!
3190	*/
3191	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3192	if (1) { \
3193	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3194	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3195	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3196	} else do {} while (0)
3197	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3198	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3199	* buffer after figuring out the actual command size.
3200	*
3201	* Will break out of the switch on failure.
3202	*
3203	* @param a_PtrVar Request variable pointer.
3204	* @param a_Type Request typedef (not pointer) for casting.
3205	* @param a_cbPayloadReq How much payload to fetch.
3206	* @remarks Accesses a bunch of variables in the current scope!
3207	*/
3208	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3209	if (1) { \
3210	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3211	} else do {} while (0)
3212
3213	/*
3214	* Mark the FIFO as busy.
3215	*/
3216	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3217	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3218	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3219
3220	/*
3221	* Execute all queued FIFO commands.
3222	* Quit if pending external command or changes in the thread state.
3223	*/
3224	bool fDone = false;
3225	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3226	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3227	{
3228	uint32_t cbPayload = 0;
3229	uint32_t u32IrqStatus = 0;
3230
3231	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3232
3233	/* First check any pending actions. */
3234	if ( ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT)
3235	&& pThis->svga.p3dState != NULL)
3236	# ifdef VBOX_WITH_VMSVGA3D
3237	vmsvga3dChangeMode(pThis);
3238	# else
3239	{/nothing/}
3240	# endif
3241	/* Check for pending external commands (reset). */
3242	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3243	break;
3244
3245	/*
3246	* Process the command.
3247	*/
3248	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3249	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3250	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3251	switch (enmCmdId)
3252	{
3253	case SVGA_CMD_INVALID_CMD:
3254	/* Nothing to do. */
3255	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3256	break;
3257
3258	case SVGA_CMD_FENCE:
3259	{
3260	SVGAFifoCmdFence *pCmdFence;
3261	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3262	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3263	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3264	{
3265	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3266	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3267
3268	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3269	{
3270	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3271	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3272	}
3273	else
3274	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3275	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3276	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3277	{
3278	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3279	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3280	}
3281	}
3282	else
3283	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3284	break;
3285	}
3286	case SVGA_CMD_UPDATE:
3287	case SVGA_CMD_UPDATE_VERBOSE:
3288	{
3289	SVGAFifoCmdUpdate *pUpdate;
3290	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3291	if (enmCmdId == SVGA_CMD_UPDATE)
3292	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3293	else
3294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3295	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3296	vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3297	break;
3298	}
3299
3300	case SVGA_CMD_DEFINE_CURSOR:
3301	{
3302	/* Followed by bitmap data. */
3303	SVGAFifoCmdDefineCursor *pCursor;
3304	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3305	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3306
3307	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3308	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3309	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3310	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3311
3312	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3313	uint32_t cbAndMask = cbAndLine * pCursor->height;
3314	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3315	uint32_t cbXorMask = cbXorLine * pCursor->height;
3316	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3317
3318	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3319	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3320	break;
3321	}
3322
3323	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3324	{
3325	/* Followed by bitmap data. */
3326	uint32_t cbCursorShape, cbAndMask;
3327	uint8_t *pCursorCopy;
3328	uint32_t cbCmd;
3329
3330	SVGAFifoCmdDefineAlphaCursor *pCursor;
3331	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3332	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3333
3334	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3335
3336	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3337	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3338
3339	/* Refetch the bitmap data as well. */
3340	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3341	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3342	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3343
3344	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3345	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3346	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3347	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3348
3349	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3350	AssertBreak(pCursorCopy);
3351
3352	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3353	memset(pCursorCopy, 0xff, cbAndMask);
3354	/* Colour data */
3355	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3356
3357	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3358	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3359	break;
3360	}
3361
3362	case SVGA_CMD_ESCAPE:
3363	{
3364	/* Followed by nsize bytes of data. */
3365	SVGAFifoCmdEscape *pEscape;
3366	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3367	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3368
3369	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3370	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3371	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3372	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3373
3374	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3375	{
3376	AssertBreak(pEscape->size >= sizeof(uint32_t));
3377	uint32_t cmd = (uint32_t )(pEscape + 1);
3378	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3379
3380	switch (cmd)
3381	{
3382	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3383	{
3384	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3385	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3386	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3387
3388	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3389	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3390	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3391
3392	RT_NOREF_PV(pVideoCmd);
3393	break;
3394
3395	}
3396
3397	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3398	{
3399	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3400	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3401	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3402	RT_NOREF_PV(pVideoCmd);
3403	break;
3404	}
3405	}
3406	}
3407	else
3408	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3409
3410	break;
3411	}
3412	# ifdef VBOX_WITH_VMSVGA3D
3413	case SVGA_CMD_DEFINE_GMR2:
3414	{
3415	SVGAFifoCmdDefineGMR2 *pCmd;
3416	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3417	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3418	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3419
3420	/* Validate current GMR id. */
3421	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3422	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3423
3424	if (!pCmd->numPages)
3425	{
3426	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3427	vmsvgaGMRFree(pThis, pCmd->gmrId);
3428	}
3429	else
3430	{
3431	PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
3432	if (pGMR->cMaxPages)
3433	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3434
3435	/* Not sure if we should always free the descriptor, but for simplicity
3436	we do so if the new size is smaller than the current. */
3437	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3438	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3439	vmsvgaGMRFree(pThis, pCmd->gmrId);
3440
3441	pGMR->cMaxPages = pCmd->numPages;
3442	/* The rest is done by the REMAP_GMR2 command. */
3443	}
3444	break;
3445	}
3446
3447	case SVGA_CMD_REMAP_GMR2:
3448	{
3449	/* Followed by page descriptors or guest ptr. */
3450	SVGAFifoCmdRemapGMR2 *pCmd;
3451	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3452	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3453
3454	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3455	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3456
3457	/* Calculate the size of what comes after next and fetch it. */
3458	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3459	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3460	cbCmd += sizeof(SVGAGuestPtr);
3461	else
3462	{
3463	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3464	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3465	{
3466	cbCmd += cbPageDesc;
3467	pCmd->numPages = 1;
3468	}
3469	else
3470	{
3471	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3472	cbCmd += cbPageDesc * pCmd->numPages;
3473	}
3474	}
3475	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3476
3477	/* Validate current GMR id and size. */
3478	AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
3479	PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
3480	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3481	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3482	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3483
3484	if (pCmd->numPages == 0)
3485	break;
3486
3487	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3488	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3489
3490	/*
3491	* We flatten the existing descriptors into a page array, overwrite the
3492	* pages specified in this command and then recompress the descriptor.
3493	*/
3494	/** @todo Optimize the GMR remap algorithm! */
3495
3496	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3497	uint64_t *paNewPage64 = NULL;
3498	if (pGMR->paDesc)
3499	{
3500	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3501
3502	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3503	AssertBreak(paNewPage64);
3504
3505	uint32_t idxPage = 0;
3506	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3507	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3508	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3509	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3510	}
3511
3512	/* Free the old GMR if present. */
3513	if (pGMR->paDesc)
3514	RTMemFree(pGMR->paDesc);
3515
3516	/* Allocate the maximum amount possible (everything non-continuous) */
3517	PVMSVGAGMRDESCRIPTOR paDescs;
3518	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3519	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3520
3521	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3522	{
3523	/** @todo */
3524	AssertFailed();
3525	pGMR->numDescriptors = 0;
3526	}
3527	else
3528	{
3529	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3530	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3531	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3532
3533	if (paNewPage64)
3534	{
3535	/* Overwrite the old page array with the new page values. */
3536	if (fGCPhys64)
3537	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3538	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3539	else
3540	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3541	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3542
3543	/* Use the updated page array instead of the command data. */
3544	fGCPhys64 = true;
3545	paPages64 = paNewPage64;
3546	pCmd->numPages = cNewTotalPages;
3547	}
3548
3549	/* The first page. */
3550	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3551	* applied to paNewPage64. */
3552	RTGCPHYS GCPhys;
3553	if (fGCPhys64)
3554	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3555	else
3556	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3557	paDescs[0].GCPhys = GCPhys;
3558	paDescs[0].numPages = 1;
3559
3560	/* Subsequent pages. */
3561	uint32_t iDescriptor = 0;
3562	for (uint32_t i = 1; i < pCmd->numPages; i++)
3563	{
3564	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3565	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3566	else
3567	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3568
3569	/* Continuous physical memory? */
3570	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3571	{
3572	Assert(paDescs[iDescriptor].numPages);
3573	paDescs[iDescriptor].numPages++;
3574	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3575	}
3576	else
3577	{
3578	iDescriptor++;
3579	paDescs[iDescriptor].GCPhys = GCPhys;
3580	paDescs[iDescriptor].numPages = 1;
3581	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3582	}
3583	}
3584
3585	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3586	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3587	pGMR->numDescriptors = iDescriptor + 1;
3588	}
3589
3590	if (paNewPage64)
3591	RTMemFree(paNewPage64);
3592
3593	# ifdef DEBUG_GMR_ACCESS
3594	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3595	# endif
3596	break;
3597	}
3598	# endif // VBOX_WITH_VMSVGA3D
3599	case SVGA_CMD_DEFINE_SCREEN:
3600	{
3601	/* Note! The size of this command is specified by the guest and depends on capabilities. */
3602	Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
3603	SVGAFifoCmdDefineScreen *pCmd;
3604	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3605	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
3606	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3607	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3608
3609	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
3610	if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
3611	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
3612	if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
3613	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
3614	if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
3615	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
3616	if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
3617	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
3618	if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
3619	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
3620
3621	/** @todo multi monitor support and screen object capabilities. */
3622	pThis->svga.uWidth = pCmd->screen.size.width;
3623	pThis->svga.uHeight = pCmd->screen.size.height;
3624	vmsvgaChangeMode(pThis);
3625	break;
3626	}
3627
3628	case SVGA_CMD_DESTROY_SCREEN:
3629	{
3630	SVGAFifoCmdDestroyScreen *pCmd;
3631	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3632	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3633
3634	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3635	break;
3636	}
3637	# ifdef VBOX_WITH_VMSVGA3D
3638	case SVGA_CMD_DEFINE_GMRFB:
3639	{
3640	SVGAFifoCmdDefineGMRFB *pCmd;
3641	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3642	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3643
3644	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3645	pSVGAState->GMRFB.ptr = pCmd->ptr;
3646	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3647	pSVGAState->GMRFB.format = pCmd->format;
3648	break;
3649	}
3650
3651	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3652	{
3653	uint32_t width, height;
3654	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3655	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3656	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3657
3658	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3659
3660	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3661	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
3662	AssertBreak(pCmd->destScreenId == 0);
3663
3664	if (pCmd->destRect.left < 0)
3665	pCmd->destRect.left = 0;
3666	if (pCmd->destRect.top < 0)
3667	pCmd->destRect.top = 0;
3668	if (pCmd->destRect.right < 0)
3669	pCmd->destRect.right = 0;
3670	if (pCmd->destRect.bottom < 0)
3671	pCmd->destRect.bottom = 0;
3672
3673	width = pCmd->destRect.right - pCmd->destRect.left;
3674	height = pCmd->destRect.bottom - pCmd->destRect.top;
3675
3676	if ( width == 0
3677	\|\| height == 0)
3678	break; /* Nothing to do. */
3679
3680	/* Clip to screen dimensions. */
3681	if (width > pThis->svga.uWidth)
3682	width = pThis->svga.uWidth;
3683	if (height > pThis->svga.uHeight)
3684	height = pThis->svga.uHeight;
3685
3686	unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3687	unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3688	unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
3689
3690	AssertBreak(offsetDest < pThis->vram_size);
3691
3692	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3693	AssertRC(rc);
3694	vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3695	break;
3696	}
3697
3698	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3699	{
3700	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3701	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3702	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3703
3704	/* Note! This can fetch 3d render results as well!! */
3705	Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3706	AssertFailed();
3707	break;
3708	}
3709	# endif // VBOX_WITH_VMSVGA3D
3710	case SVGA_CMD_ANNOTATION_FILL:
3711	{
3712	SVGAFifoCmdAnnotationFill *pCmd;
3713	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3714	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
3715
3716	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3717	pSVGAState->colorAnnotation = pCmd->color;
3718	break;
3719	}
3720
3721	case SVGA_CMD_ANNOTATION_COPY:
3722	{
3723	SVGAFifoCmdAnnotationCopy *pCmd;
3724	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
3726
3727	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3728	AssertFailed();
3729	break;
3730	}
3731
3732	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3733
3734	default:
3735	# ifdef VBOX_WITH_VMSVGA3D
3736	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
3737	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
3738	{
3739	/* All 3d commands start with a common header, which defines the size of the command. */
3740	SVGA3dCmdHeader *pHdr;
3741	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3742	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
3743	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3744	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3745
3746	/**
3747	* Check that the 3D command has at least a_cbMin of payload bytes after the
3748	* header. Will break out of the switch if it doesn't.
3749	*/
3750	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3751	AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3752	switch ((int)enmCmdId)
3753	{
3754	case SVGA_3D_CMD_SURFACE_DEFINE:
3755	{
3756	uint32_t cMipLevels;
3757	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
3758	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3759	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
3760
3761	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3762	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3763	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3764	# ifdef DEBUG_GMR_ACCESS
3765	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3766	# endif
3767	break;
3768	}
3769
3770	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3771	{
3772	uint32_t cMipLevels;
3773	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
3774	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3775	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
3776
3777	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3778	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3779	pCmd->multisampleCount, pCmd->autogenFilter,
3780	cMipLevels, (SVGA3dSize *)(pCmd + 1));
3781	break;
3782	}
3783
3784	case SVGA_3D_CMD_SURFACE_DESTROY:
3785	{
3786	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
3787	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3788	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
3789	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3790	break;
3791	}
3792
3793	case SVGA_3D_CMD_SURFACE_COPY:
3794	{
3795	uint32_t cCopyBoxes;
3796	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
3797	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3798	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
3799
3800	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3801	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3802	break;
3803	}
3804
3805	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3806	{
3807	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
3808	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3809	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
3810
3811	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3812	break;
3813	}
3814
3815	case SVGA_3D_CMD_SURFACE_DMA:
3816	{
3817	uint32_t cCopyBoxes;
3818	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
3819	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3820	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
3821
3822	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3823	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3824	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3825	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
3826	break;
3827	}
3828
3829	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3830	{
3831	uint32_t cRects;
3832	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
3833	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3834	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
3835
3836	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3837	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3838	break;
3839	}
3840
3841	case SVGA_3D_CMD_CONTEXT_DEFINE:
3842	{
3843	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
3844	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3845	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
3846
3847	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3848	break;
3849	}
3850
3851	case SVGA_3D_CMD_CONTEXT_DESTROY:
3852	{
3853	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
3854	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3855	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
3856
3857	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3858	break;
3859	}
3860
3861	case SVGA_3D_CMD_SETTRANSFORM:
3862	{
3863	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
3864	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3865	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
3866
3867	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3868	break;
3869	}
3870
3871	case SVGA_3D_CMD_SETZRANGE:
3872	{
3873	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
3874	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3875	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
3876
3877	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3878	break;
3879	}
3880
3881	case SVGA_3D_CMD_SETRENDERSTATE:
3882	{
3883	uint32_t cRenderStates;
3884	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
3885	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
3887
3888	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3889	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3890	break;
3891	}
3892
3893	case SVGA_3D_CMD_SETRENDERTARGET:
3894	{
3895	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
3896	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3897	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
3898
3899	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3900	break;
3901	}
3902
3903	case SVGA_3D_CMD_SETTEXTURESTATE:
3904	{
3905	uint32_t cTextureStates;
3906	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
3907	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3908	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
3909
3910	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3911	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3912	break;
3913	}
3914
3915	case SVGA_3D_CMD_SETMATERIAL:
3916	{
3917	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
3918	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3919	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
3920
3921	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3922	break;
3923	}
3924
3925	case SVGA_3D_CMD_SETLIGHTDATA:
3926	{
3927	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
3928	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3929	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
3930
3931	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3932	break;
3933	}
3934
3935	case SVGA_3D_CMD_SETLIGHTENABLED:
3936	{
3937	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
3938	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3939	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
3940
3941	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3942	break;
3943	}
3944
3945	case SVGA_3D_CMD_SETVIEWPORT:
3946	{
3947	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
3948	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3949	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
3950
3951	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3952	break;
3953	}
3954
3955	case SVGA_3D_CMD_SETCLIPPLANE:
3956	{
3957	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
3958	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3959	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
3960
3961	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3962	break;
3963	}
3964
3965	case SVGA_3D_CMD_CLEAR:
3966	{
3967	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
3968	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3969	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
3970
3971	uint32_t cRects;
3972	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3973	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3974	break;
3975	}
3976
3977	case SVGA_3D_CMD_PRESENT:
3978	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3979	{
3980	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
3981	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3982	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
3983	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
3984	else
3985	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
3986
3987	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3988
3989	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
3990	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3991	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
3992	break;
3993	}
3994
3995	case SVGA_3D_CMD_SHADER_DEFINE:
3996	{
3997	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
3998	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3999	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4000
4001	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4002	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4003	break;
4004	}
4005
4006	case SVGA_3D_CMD_SHADER_DESTROY:
4007	{
4008	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4009	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4010	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4011
4012	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4013	break;
4014	}
4015
4016	case SVGA_3D_CMD_SET_SHADER:
4017	{
4018	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4019	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4020	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4021
4022	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4023	break;
4024	}
4025
4026	case SVGA_3D_CMD_SET_SHADER_CONST:
4027	{
4028	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4029	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4030	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4031
4032	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4033	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4034	break;
4035	}
4036
4037	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4038	{
4039	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4040	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4041	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4042
4043	uint32_t cVertexDivisor = (pHdr->size - sizeof(pCmd) - sizeof(SVGA3dVertexDecl) pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
4044	Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4045	Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4046	Assert(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4047
4048	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4049	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange ) (&pVertexDecl[pCmd->numVertexDecls]);
4050	SVGA3dVertexDivisor pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor )(&pNumRange[pCmd->numRanges]) : NULL;
4051
4052	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4053	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
4054	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4055	break;
4056	}
4057
4058	case SVGA_3D_CMD_SETSCISSORRECT:
4059	{
4060	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4061	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4062	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4063
4064	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4065	break;
4066	}
4067
4068	case SVGA_3D_CMD_BEGIN_QUERY:
4069	{
4070	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4071	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4072	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4073
4074	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4075	break;
4076	}
4077
4078	case SVGA_3D_CMD_END_QUERY:
4079	{
4080	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4081	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4082	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4083
4084	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4085	break;
4086	}
4087
4088	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4089	{
4090	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4091	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4092	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4093
4094	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4095	break;
4096	}
4097
4098	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4099	{
4100	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4101	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4102	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4103
4104	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4105	break;
4106	}
4107
4108	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4109	/* context id + surface id? */
4110	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4111	break;
4112	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4113	/* context id + surface id? */
4114	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4115	break;
4116
4117	default:
4118	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4119	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4120	break;
4121	}
4122	}
4123	else
4124	# endif // VBOX_WITH_VMSVGA3D
4125	{
4126	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4127	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4128	}
4129	}
4130
4131	/* Go to the next slot */
4132	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4133	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4134	if (offCurrentCmd >= offFifoMax)
4135	{
4136	offCurrentCmd -= offFifoMax - offFifoMin;
4137	Assert(offCurrentCmd >= offFifoMin);
4138	Assert(offCurrentCmd < offFifoMax);
4139	}
4140	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4141	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4142
4143	/*
4144	* Raise IRQ if required. Must enter the critical section here
4145	* before making final decisions here, otherwise cubebench and
4146	* others may end up waiting forever.
4147	*/
4148	if ( u32IrqStatus
4149	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4150	{
4151	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4152	AssertRC(rc2);
4153
4154	/* FIFO progress might trigger an interrupt. */
4155	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4156	{
4157	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4158	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4159	}
4160
4161	/* Unmasked IRQ pending? */
4162	if (pThis->svga.u32IrqMask & u32IrqStatus)
4163	{
4164	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4165	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4166	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4167	}
4168
4169	PDMCritSectLeave(&pThis->CritSect);
4170	}
4171	}
4172
4173	/* If really done, clear the busy flag. */
4174	if (fDone)
4175	{
4176	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4177	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4178	}
4179	}
4180
4181	/*
4182	* Free the bounce buffer. (There are no returns above!)
4183	*/
4184	RTMemFree(pbBounceBuf);
4185
4186	return VINF_SUCCESS;
4187	}
4188
4189	/**
4190	* Free the specified GMR
4191	*
4192	* @param pThis VGA device instance data.
4193	* @param idGMR GMR id
4194	*/
4195	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4196	{
4197	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4198
4199	/* Free the old descriptor if present. */
4200	PGMR pGMR = &pSVGAState->aGMR[idGMR];
4201	if ( pGMR->numDescriptors
4202	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4203	{
4204	# ifdef DEBUG_GMR_ACCESS
4205	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4206	# endif
4207
4208	Assert(pGMR->paDesc);
4209	RTMemFree(pGMR->paDesc);
4210	pGMR->paDesc = NULL;
4211	pGMR->numDescriptors = 0;
4212	pGMR->cbTotal = 0;
4213	pGMR->cMaxPages = 0;
4214	}
4215	Assert(!pGMR->cMaxPages);
4216	Assert(!pGMR->cbTotal);
4217	}
4218
4219	/**
4220	* Copy from a GMR to host memory or vice versa
4221	*
4222	* @returns VBox status code.
4223	* @param pThis VGA device instance data.
4224	* @param enmTransferType Transfer type (read/write)
4225	* @param pbDst Host destination pointer
4226	* @param cbDestPitch Destination buffer pitch
4227	* @param src GMR description
4228	* @param offSrc Source buffer offset
4229	* @param cbSrcPitch Source buffer pitch
4230	* @param cbWidth Source width in bytes
4231	* @param cHeight Source height
4232	*/
4233	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
4234	SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
4235	{
4236	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4237	PGMR pGMR;
4238	int rc;
4239	PVMSVGAGMRDESCRIPTOR pDesc;
4240	unsigned offDesc = 0;
4241
4242	Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
4243	src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
4244	Assert(cbWidth && cHeight);
4245
4246	/* Shortcut for the framebuffer. */
4247	if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
4248	{
4249	offSrc += src.offset;
4250	AssertMsgReturn(src.offset < pThis->vram_size,
4251	("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
4252	src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
4253	VERR_INVALID_PARAMETER);
4254	AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
4255	("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
4256	src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
4257	VERR_INVALID_PARAMETER);
4258
4259	uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
4260
4261	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4262	{
4263	/* switch src & dest */
4264	uint8_t *pTemp = pbDst;
4265	int32_t cbTempPitch = cbDestPitch;
4266
4267	pbDst = pSrc;
4268	pSrc = pTemp;
4269
4270	cbDestPitch = cbSrcPitch;
4271	cbSrcPitch = cbTempPitch;
4272	}
4273
4274	if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
4275	&& cbWidth == (uint32_t)cbDestPitch
4276	&& cbSrcPitch == cbDestPitch)
4277	{
4278	memcpy(pbDst, pSrc, cbWidth * cHeight);
4279	}
4280	else
4281	{
4282	for(uint32_t i = 0; i < cHeight; i++)
4283	{
4284	memcpy(pbDst, pSrc, cbWidth);
4285
4286	pbDst += cbDestPitch;
4287	pSrc += cbSrcPitch;
4288	}
4289	}
4290	return VINF_SUCCESS;
4291	}
4292
4293	AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
4294	pGMR = &pSVGAState->aGMR[src.gmrId];
4295	pDesc = pGMR->paDesc;
4296
4297	offSrc += src.offset;
4298	AssertMsgReturn(src.offset < pGMR->cbTotal,
4299	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
4300	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
4301	VERR_INVALID_PARAMETER);
4302	AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
4303	("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
4304	src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
4305	VERR_INVALID_PARAMETER);
4306
4307	for (uint32_t i = 0; i < cHeight; i++)
4308	{
4309	uint32_t cbCurrentWidth = cbWidth;
4310	uint32_t offCurrent = offSrc;
4311	uint8_t *pCurrentDest = pbDst;
4312
4313	/* Find the right descriptor */
4314	while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
4315	{
4316	offDesc += pDesc->numPages * PAGE_SIZE;
4317	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4318	pDesc++;
4319	}
4320
4321	while (cbCurrentWidth)
4322	{
4323	uint32_t cbToCopy;
4324
4325	if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
4326	{
4327	cbToCopy = cbCurrentWidth;
4328	}
4329	else
4330	{
4331	cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
4332	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4333	}
4334
4335	LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
4336
4337	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4338	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4339	else
4340	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
4341	AssertRCBreak(rc);
4342
4343	cbCurrentWidth -= cbToCopy;
4344	offCurrent += cbToCopy;
4345	pCurrentDest += cbToCopy;
4346
4347	/* Go to the next descriptor if there's anything left. */
4348	if (cbCurrentWidth)
4349	{
4350	offDesc += pDesc->numPages * PAGE_SIZE;
4351	pDesc++;
4352	}
4353	}
4354
4355	offSrc += cbSrcPitch;
4356	pbDst += cbDestPitch;
4357	}
4358
4359	return VINF_SUCCESS;
4360	}
4361
4362	/**
4363	* Unblock the FIFO I/O thread so it can respond to a state change.
4364	*
4365	* @returns VBox status code.
4366	* @param pDevIns The VGA device instance.
4367	* @param pThread The send thread.
4368	*/
4369	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4370	{
4371	RT_NOREF(pDevIns);
4372	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4373	Log(("vmsvgaFIFOLoopWakeUp\n"));
4374	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4375	}
4376
4377	/**
4378	* Enables or disables dirty page tracking for the framebuffer
4379	*
4380	* @param pThis VGA device instance data.
4381	* @param fTraces Enable/disable traces
4382	*/
4383	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4384	{
4385	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4386	&& !fTraces)
4387	{
4388	//Assert(pThis->svga.fTraces);
4389	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4390	return;
4391	}
4392
4393	pThis->svga.fTraces = fTraces;
4394	if (pThis->svga.fTraces)
4395	{
4396	unsigned cbFrameBuffer = pThis->vram_size;
4397
4398	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4399	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4400	{
4401	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4402	Assert(pThis->svga.cbScanline);
4403	#endif
4404	/* Hardware enabled; return real framebuffer size .*/
4405	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4406	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4407	}
4408
4409	if (!pThis->svga.fVRAMTracking)
4410	{
4411	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4412	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4413	pThis->svga.fVRAMTracking = true;
4414	}
4415	}
4416	else
4417	{
4418	if (pThis->svga.fVRAMTracking)
4419	{
4420	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4421	vgaR3UnregisterVRAMHandler(pThis);
4422	pThis->svga.fVRAMTracking = false;
4423	}
4424	}
4425	}
4426
4427	/**
4428	* @callback_method_impl{FNPCIIOREGIONMAP}
4429	*/
4430	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4431	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4432	{
4433	int rc;
4434	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4435
4436	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4437	if (enmType == PCI_ADDRESS_SPACE_IO)
4438	{
4439	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4440	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4441	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4442	if (RT_FAILURE(rc))
4443	return rc;
4444	if (pThis->fR0Enabled)
4445	{
4446	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4447	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4448	if (RT_FAILURE(rc))
4449	return rc;
4450	}
4451	if (pThis->fGCEnabled)
4452	{
4453	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4454	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4455	if (RT_FAILURE(rc))
4456	return rc;
4457	}
4458
4459	pThis->svga.BasePort = GCPhysAddress;
4460	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
4461	}
4462	else
4463	{
4464	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
4465	if (GCPhysAddress != NIL_RTGCPHYS)
4466	{
4467	/*
4468	* Mapping the FIFO RAM.
4469	*/
4470	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
4471	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
4472	AssertRC(rc);
4473
4474	# ifdef DEBUG_FIFO_ACCESS
4475	if (RT_SUCCESS(rc))
4476	{
4477	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
4478	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
4479	"VMSVGA FIFO");
4480	AssertRC(rc);
4481	}
4482	# endif
4483	if (RT_SUCCESS(rc))
4484	{
4485	pThis->svga.GCPhysFIFO = GCPhysAddress;
4486	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
4487	}
4488	}
4489	else
4490	{
4491	Assert(pThis->svga.GCPhysFIFO);
4492	# ifdef DEBUG_FIFO_ACCESS
4493	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4494	AssertRC(rc);
4495	# endif
4496	pThis->svga.GCPhysFIFO = 0;
4497	}
4498
4499	}
4500	return VINF_SUCCESS;
4501	}
4502
4503	# ifdef VBOX_WITH_VMSVGA3D
4504
4505	/**
4506	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
4507	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
4508	*
4509	* @param pThis The VGA device instance data.
4510	* @param sid Either UINT32_MAX or the ID of a specific
4511	* surface. If UINT32_MAX is used, all surfaces
4512	* are processed.
4513	*/
4514	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
4515	{
4516	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
4517	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
4518	}
4519
4520
4521	/**
4522	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
4523	*/
4524	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4525	{
4526	/* There might be a specific context ID at the start of the
4527	arguments, if not show all contexts. */
4528	uint32_t cid = UINT32_MAX;
4529	if (pszArgs)
4530	pszArgs = RTStrStripL(pszArgs);
4531	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4532	cid = RTStrToUInt32(pszArgs);
4533
4534	/* Verbose or terse display, we default to verbose. */
4535	bool fVerbose = true;
4536	if (RTStrIStr(pszArgs, "terse"))
4537	fVerbose = false;
4538
4539	/* The size of the ascii art (x direction, y is 3/4 of x). */
4540	uint32_t cxAscii = 80;
4541	if (RTStrIStr(pszArgs, "gigantic"))
4542	cxAscii = 300;
4543	else if (RTStrIStr(pszArgs, "huge"))
4544	cxAscii = 180;
4545	else if (RTStrIStr(pszArgs, "big"))
4546	cxAscii = 132;
4547	else if (RTStrIStr(pszArgs, "normal"))
4548	cxAscii = 80;
4549	else if (RTStrIStr(pszArgs, "medium"))
4550	cxAscii = 64;
4551	else if (RTStrIStr(pszArgs, "small"))
4552	cxAscii = 48;
4553	else if (RTStrIStr(pszArgs, "tiny"))
4554	cxAscii = 24;
4555
4556	/* Y invert the image when producing the ASCII art. */
4557	bool fInvY = false;
4558	if (RTStrIStr(pszArgs, "invy"))
4559	fInvY = true;
4560
4561	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
4562	}
4563
4564
4565	/**
4566	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
4567	*/
4568	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4569	{
4570	/* There might be a specific surface ID at the start of the
4571	arguments, if not show all contexts. */
4572	uint32_t sid = UINT32_MAX;
4573	if (pszArgs)
4574	pszArgs = RTStrStripL(pszArgs);
4575	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4576	sid = RTStrToUInt32(pszArgs);
4577
4578	/* Verbose or terse display, we default to verbose. */
4579	bool fVerbose = true;
4580	if (RTStrIStr(pszArgs, "terse"))
4581	fVerbose = false;
4582
4583	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
4584	}
4585
4586	# endif /* VBOX_WITH_VMSVGA3D */
4587
4588	/**
4589	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
4590	*/
4591	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4592	{
4593	RT_NOREF(pszArgs);
4594	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4595	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4596
4597	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
4598	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
4599	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
4600	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
4601	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
4602	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
4603	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
4604	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
4605	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
4606	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
4607	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
4608	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
4609	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
4610	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
4611	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
4612	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
4613	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
4614	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
4615	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4616	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
4617	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
4618	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
4619
4620	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
4621	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
4622	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
4623	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
4624
4625	# ifdef VBOX_WITH_VMSVGA3D
4626	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
4627	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
4628	if (pThis->svga.u64HostWindowId != 0)
4629	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
4630	# endif
4631	}
4632
4633
4634	/**
4635	* @copydoc FNSSMDEVLOADEXEC
4636	*/
4637	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4638	{
4639	RT_NOREF(uVersion, uPass);
4640	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4641	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4642	int rc;
4643
4644	/* Load our part of the VGAState */
4645	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4646	AssertRCReturn(rc, rc);
4647
4648	/* Load the VGA framebuffer. */
4649	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
4650	uint32_t cbVgaFramebuffer = _32K;
4651	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
4652	{
4653	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
4654	AssertRCReturn(rc, rc);
4655	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
4656	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
4657	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4658	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
4659	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
4660	}
4661	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
4662	AssertRCReturn(rc, rc);
4663	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
4664	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
4665	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
4666	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
4667
4668	/* Load the VMSVGA state. */
4669	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4670	AssertRCReturn(rc, rc);
4671
4672	/* Load the active cursor bitmaps. */
4673	if (pSVGAState->Cursor.fActive)
4674	{
4675	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
4676	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
4677
4678	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4679	AssertRCReturn(rc, rc);
4680	}
4681
4682	/* Load the GMR state */
4683	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4684	{
4685	PGMR pGMR = &pSVGAState->aGMR[i];
4686
4687	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
4688	AssertRCReturn(rc, rc);
4689
4690	if (pGMR->numDescriptors)
4691	{
4692	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
4693	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
4694	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
4695
4696	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
4697	{
4698	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4699	AssertRCReturn(rc, rc);
4700	}
4701	}
4702	}
4703
4704	# ifdef VBOX_WITH_VMSVGA3D
4705	if (pThis->svga.f3DEnabled)
4706	{
4707	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
4708	vmsvga3dPowerOn(pThis);
4709	# endif
4710
4711	VMSVGA_STATE_LOAD LoadState;
4712	LoadState.pSSM = pSSM;
4713	LoadState.uVersion = uVersion;
4714	LoadState.uPass = uPass;
4715	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
4716	AssertLogRelRCReturn(rc, rc);
4717	}
4718	# endif
4719
4720	return VINF_SUCCESS;
4721	}
4722
4723	/**
4724	* Reinit the video mode after the state has been loaded.
4725	*/
4726	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
4727	{
4728	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4729	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4730
4731	pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
4732	vmsvgaChangeMode(pThis);
4733
4734	/* Set the active cursor. */
4735	if (pSVGAState->Cursor.fActive)
4736	{
4737	int rc;
4738
4739	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
4740	true,
4741	true,
4742	pSVGAState->Cursor.xHotspot,
4743	pSVGAState->Cursor.yHotspot,
4744	pSVGAState->Cursor.width,
4745	pSVGAState->Cursor.height,
4746	pSVGAState->Cursor.pData);
4747	AssertRC(rc);
4748	}
4749	return VINF_SUCCESS;
4750	}
4751
4752	/**
4753	* @copydoc FNSSMDEVSAVEEXEC
4754	*/
4755	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4756	{
4757	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4758	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4759	int rc;
4760
4761	/* Save our part of the VGAState */
4762	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4763	AssertLogRelRCReturn(rc, rc);
4764
4765	/* Save the framebuffer backup. */
4766	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
4767	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4768	AssertLogRelRCReturn(rc, rc);
4769
4770	/* Save the VMSVGA state. */
4771	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4772	AssertLogRelRCReturn(rc, rc);
4773
4774	/* Save the active cursor bitmaps. */
4775	if (pSVGAState->Cursor.fActive)
4776	{
4777	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4778	AssertLogRelRCReturn(rc, rc);
4779	}
4780
4781	/* Save the GMR state */
4782	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4783	{
4784	rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4785	AssertLogRelRCReturn(rc, rc);
4786
4787	for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4788	{
4789	rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4790	AssertLogRelRCReturn(rc, rc);
4791	}
4792	}
4793
4794	# ifdef VBOX_WITH_VMSVGA3D
4795	/*
4796	* Must save the 3d state in the FIFO thread.
4797	*/
4798	if (pThis->svga.f3DEnabled)
4799	{
4800	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4801	AssertLogRelRCReturn(rc, rc);
4802	}
4803	# endif
4804	return VINF_SUCCESS;
4805	}
4806
4807	/**
4808	* Resets the SVGA hardware state
4809	*
4810	* @returns VBox status code.
4811	* @param pDevIns The device instance.
4812	*/
4813	int vmsvgaReset(PPDMDEVINS pDevIns)
4814	{
4815	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4816	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4817
4818	/* Reset before init? */
4819	if (!pSVGAState)
4820	return VINF_SUCCESS;
4821
4822	Log(("vmsvgaReset\n"));
4823
4824
4825	/* Reset the FIFO processing as well as the 3d state (if we have one). */
4826	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4827	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
4828
4829	/* Reset other stuff. */
4830	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4831	RT_ZERO(pThis->svga.au32ScratchRegion);
4832	RT_ZERO(*pThis->svga.pSvgaR3State);
4833	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
4834
4835	/* Register caps. */
4836	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
4837	# ifdef VBOX_WITH_VMSVGA3D
4838	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
4839	# endif
4840
4841	/* Setup FIFO capabilities. */
4842	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4843
4844	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4845	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4846
4847	/* VRAM tracking is enabled by default during bootup. */
4848	pThis->svga.fVRAMTracking = true;
4849	pThis->svga.fEnabled = false;
4850
4851	/* Invalidate current settings. */
4852	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4853	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4854	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4855	pThis->svga.cbScanline = 0;
4856
4857	return rc;
4858	}
4859
4860	/**
4861	* Cleans up the SVGA hardware state
4862	*
4863	* @returns VBox status code.
4864	* @param pDevIns The device instance.
4865	*/
4866	int vmsvgaDestruct(PPDMDEVINS pDevIns)
4867	{
4868	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4869
4870	/*
4871	* Ask the FIFO thread to terminate the 3d state and then terminate it.
4872	*/
4873	if (pThis->svga.pFIFOIOThread)
4874	{
4875	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
4876	AssertLogRelRC(rc);
4877
4878	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4879	AssertLogRelRC(rc);
4880	pThis->svga.pFIFOIOThread = NULL;
4881	}
4882
4883	/*
4884	* Destroy the special SVGA state.
4885	*/
4886	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4887	if (pSVGAState)
4888	{
4889	# ifndef VMSVGA_USE_EMT_HALT_CODE
4890	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4891	{
4892	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4893	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4894	}
4895	# endif
4896	if (pSVGAState->Cursor.fActive)
4897	RTMemFree(pSVGAState->Cursor.pData);
4898
4899	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4900	if (pSVGAState->aGMR[i].paDesc)
4901	RTMemFree(pSVGAState->aGMR[i].paDesc);
4902
4903	RTMemFree(pSVGAState);
4904	pThis->svga.pSvgaR3State = NULL;
4905	}
4906
4907	/*
4908	* Free our resources residing in the VGA state.
4909	*/
4910	if (pThis->svga.pbVgaFrameBufferR3)
4911	{
4912	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
4913	pThis->svga.pbVgaFrameBufferR3 = NULL;
4914	}
4915	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4916	{
4917	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4918	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4919	}
4920	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4921	{
4922	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4923	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4924	}
4925
4926	return VINF_SUCCESS;
4927	}
4928
4929	/**
4930	* Initialize the SVGA hardware state
4931	*
4932	* @returns VBox status code.
4933	* @param pDevIns The device instance.
4934	*/
4935	int vmsvgaInit(PPDMDEVINS pDevIns)
4936	{
4937	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4938	PVMSVGAR3STATE pSVGAState;
4939	PVM pVM = PDMDevHlpGetVM(pDevIns);
4940	int rc;
4941
4942	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4943	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4944
4945	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4946	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4947	pSVGAState = pThis->svga.pSvgaR3State;
4948
4949	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4950	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
4951	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
4952
4953	/* Create event semaphore. */
4954	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4955
4956	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4957	if (RT_FAILURE(rc))
4958	{
4959	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4960	return rc;
4961	}
4962
4963	/* Create event semaphore. */
4964	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4965	if (RT_FAILURE(rc))
4966	{
4967	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4968	return rc;
4969	}
4970
4971	# ifndef VMSVGA_USE_EMT_HALT_CODE
4972	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4973	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4974	AssertRCReturn(rc, rc);
4975	# endif
4976
4977	/* Register caps. */
4978	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
4979	# ifdef VBOX_WITH_VMSVGA3D
4980	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
4981	# endif
4982
4983	/* Setup FIFO capabilities. */
4984	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4985
4986	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4987	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4988
4989	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4990	# ifdef VBOX_WITH_VMSVGA3D
4991	if (pThis->svga.f3DEnabled)
4992	{
4993	rc = vmsvga3dInit(pThis);
4994	if (RT_FAILURE(rc))
4995	{
4996	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4997	pThis->svga.f3DEnabled = false;
4998	}
4999	}
5000	# endif
5001	/* VRAM tracking is enabled by default during bootup. */
5002	pThis->svga.fVRAMTracking = true;
5003
5004	/* Invalidate current settings. */
5005	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5006	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5007	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5008	pThis->svga.cbScanline = 0;
5009
5010	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5011	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5012	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5013	{
5014	pThis->svga.u32MaxWidth -= 256;
5015	pThis->svga.u32MaxHeight -= 256;
5016	}
5017	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5018
5019	# ifdef DEBUG_GMR_ACCESS
5020	/* Register the GMR access handler type. */
5021	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5022	vmsvgaR3GMRAccessHandler,
5023	NULL, NULL, NULL,
5024	NULL, NULL, NULL,
5025	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5026	AssertRCReturn(rc, rc);
5027	# endif
5028	# ifdef DEBUG_FIFO_ACCESS
5029	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5030	vmsvgaR3FIFOAccessHandler,
5031	NULL, NULL, NULL,
5032	NULL, NULL, NULL,
5033	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5034	AssertRCReturn(rc, rc);
5035	#endif
5036
5037	/* Create the async IO thread. */
5038	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5039	RTTHREADTYPE_IO, "VMSVGA FIFO");
5040	if (RT_FAILURE(rc))
5041	{
5042	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5043	return rc;
5044	}
5045
5046	/*
5047	* Statistics.
5048	*/
5049	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5050	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5051	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5052	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5053	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5054	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5055	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5056	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5057	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5058	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5059	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5060	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5061	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5062	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5063	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5064	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5065	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5066	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5067	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5068	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5069	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5070	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5071	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5072	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5073	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5074	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5075	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5076	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5077	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5078	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5079	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5080	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5081	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5082	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5083	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5084	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5085	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5086	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5087	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5088	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5089	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5090	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5091	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5092	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5093	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5094	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5095	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5096	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5097	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5098	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5099	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5100	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5101	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5102	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5103	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5104	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5105
5106	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5107	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5108	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5109	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5110	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5111	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5112	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5113	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5114	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5115	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5116	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5117	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5118	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5119	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5120	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5121	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5122	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5123	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5124	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5125	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5126	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5127	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5128	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5129	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5130	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5131	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5132	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5133	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5134	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5135	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5136	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5137	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5138
5139	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5140	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5141	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5142	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5143	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5144	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5145	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5146	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5147	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5148	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5149	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5150	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5151	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5152	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5153	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5154	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5155	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5156	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5157	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5158	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5159	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5160	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5161	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5162	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5163	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5164	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5165	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5166	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5167	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5168	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5169	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5170	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5171	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5172	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5173	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5174	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5175	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5176	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5177	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5178	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5179	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5180	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5181	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5182	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5183	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5184	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5185	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5186	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5187	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5188
5189	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5190	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5191	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5192	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5193	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5194	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5195	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5196
5197	/*
5198	* Info handlers.
5199	*/
5200	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5201	# ifdef VBOX_WITH_VMSVGA3D
5202	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5203	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5204	"VMSVGA 3d surface details. "
5205	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5206	vmsvgaR3Info3dSurface);
5207	# endif
5208
5209	return VINF_SUCCESS;
5210	}
5211
5212	# ifdef VBOX_WITH_VMSVGA3D
5213	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5214	static const char * const g_apszVmSvgaDevCapNames[] =
5215	{
5216	"x3D", /* = 0 */
5217	"xMAX_LIGHTS",
5218	"xMAX_TEXTURES",
5219	"xMAX_CLIP_PLANES",
5220	"xVERTEX_SHADER_VERSION",
5221	"xVERTEX_SHADER",
5222	"xFRAGMENT_SHADER_VERSION",
5223	"xFRAGMENT_SHADER",
5224	"xMAX_RENDER_TARGETS",
5225	"xS23E8_TEXTURES",
5226	"xS10E5_TEXTURES",
5227	"xMAX_FIXED_VERTEXBLEND",
5228	"xD16_BUFFER_FORMAT",
5229	"xD24S8_BUFFER_FORMAT",
5230	"xD24X8_BUFFER_FORMAT",
5231	"xQUERY_TYPES",
5232	"xTEXTURE_GRADIENT_SAMPLING",
5233	"rMAX_POINT_SIZE",
5234	"xMAX_SHADER_TEXTURES",
5235	"xMAX_TEXTURE_WIDTH",
5236	"xMAX_TEXTURE_HEIGHT",
5237	"xMAX_VOLUME_EXTENT",
5238	"xMAX_TEXTURE_REPEAT",
5239	"xMAX_TEXTURE_ASPECT_RATIO",
5240	"xMAX_TEXTURE_ANISOTROPY",
5241	"xMAX_PRIMITIVE_COUNT",
5242	"xMAX_VERTEX_INDEX",
5243	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5244	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5245	"xMAX_VERTEX_SHADER_TEMPS",
5246	"xMAX_FRAGMENT_SHADER_TEMPS",
5247	"xTEXTURE_OPS",
5248	"xSURFACEFMT_X8R8G8B8",
5249	"xSURFACEFMT_A8R8G8B8",
5250	"xSURFACEFMT_A2R10G10B10",
5251	"xSURFACEFMT_X1R5G5B5",
5252	"xSURFACEFMT_A1R5G5B5",
5253	"xSURFACEFMT_A4R4G4B4",
5254	"xSURFACEFMT_R5G6B5",
5255	"xSURFACEFMT_LUMINANCE16",
5256	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5257	"xSURFACEFMT_ALPHA8",
5258	"xSURFACEFMT_LUMINANCE8",
5259	"xSURFACEFMT_Z_D16",
5260	"xSURFACEFMT_Z_D24S8",
5261	"xSURFACEFMT_Z_D24X8",
5262	"xSURFACEFMT_DXT1",
5263	"xSURFACEFMT_DXT2",
5264	"xSURFACEFMT_DXT3",
5265	"xSURFACEFMT_DXT4",
5266	"xSURFACEFMT_DXT5",
5267	"xSURFACEFMT_BUMPX8L8V8U8",
5268	"xSURFACEFMT_A2W10V10U10",
5269	"xSURFACEFMT_BUMPU8V8",
5270	"xSURFACEFMT_Q8W8V8U8",
5271	"xSURFACEFMT_CxV8U8",
5272	"xSURFACEFMT_R_S10E5",
5273	"xSURFACEFMT_R_S23E8",
5274	"xSURFACEFMT_RG_S10E5",
5275	"xSURFACEFMT_RG_S23E8",
5276	"xSURFACEFMT_ARGB_S10E5",
5277	"xSURFACEFMT_ARGB_S23E8",
5278	"xMISSING62",
5279	"xMAX_VERTEX_SHADER_TEXTURES",
5280	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5281	"xSURFACEFMT_V16U16",
5282	"xSURFACEFMT_G16R16",
5283	"xSURFACEFMT_A16B16G16R16",
5284	"xSURFACEFMT_UYVY",
5285	"xSURFACEFMT_YUY2",
5286	"xMULTISAMPLE_NONMASKABLESAMPLES",
5287	"xMULTISAMPLE_MASKABLESAMPLES",
5288	"xALPHATOCOVERAGE",
5289	"xSUPERSAMPLE",
5290	"xAUTOGENMIPMAPS",
5291	"xSURFACEFMT_NV12",
5292	"xSURFACEFMT_AYUV",
5293	"xMAX_CONTEXT_IDS",
5294	"xMAX_SURFACE_IDS",
5295	"xSURFACEFMT_Z_DF16",
5296	"xSURFACEFMT_Z_DF24",
5297	"xSURFACEFMT_Z_D24S8_INT",
5298	"xSURFACEFMT_BC4_UNORM",
5299	"xSURFACEFMT_BC5_UNORM", /* 83 */
5300	};
5301	# endif
5302
5303
5304	/**
5305	* Power On notification.
5306	*
5307	* @returns VBox status code.
5308	* @param pDevIns The device instance data.
5309	*
5310	* @remarks Caller enters the device critical section.
5311	*/
5312	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
5313	{
5314	# ifdef VBOX_WITH_VMSVGA3D
5315	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5316	if (pThis->svga.f3DEnabled)
5317	{
5318	int rc = vmsvga3dPowerOn(pThis);
5319
5320	if (RT_SUCCESS(rc))
5321	{
5322	bool fSavedBuffering = RTLogRelSetBuffering(true);
5323	SVGA3dCapsRecord *pCaps;
5324	SVGA3dCapPair *pData;
5325	uint32_t idxCap = 0;
5326
5327	/* 3d hardware version; latest and greatest */
5328	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5329	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5330
5331	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5332	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5333	pData = (SVGA3dCapPair *)&pCaps->data;
5334
5335	/* Fill out all 3d capabilities. */
5336	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5337	{
5338	uint32_t val = 0;
5339
5340	rc = vmsvga3dQueryCaps(pThis, i, &val);
5341	if (RT_SUCCESS(rc))
5342	{
5343	pData[idxCap][0] = i;
5344	pData[idxCap][1] = val;
5345	idxCap++;
5346	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5347	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5348	else
5349	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5350	&g_apszVmSvgaDevCapNames[i][1]));
5351	}
5352	else
5353	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5354	}
5355	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5356	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5357
5358	/* Mark end of record array. */
5359	pCaps->header.length = 0;
5360
5361	RTLogRelSetBuffering(fSavedBuffering);
5362	}
5363	}
5364	# else /* !VBOX_WITH_VMSVGA3D */
5365	RT_NOREF(pDevIns);
5366	# endif /* !VBOX_WITH_VMSVGA3D */
5367	}
5368
5369	#endif /* IN_RING3 */
5370

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 68080

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