DevVGA-SVGA.cpp@ 75717

Last change on this file since 75717 was 75717, checked in by vboxsync, 6 years ago
Device/Graphics: multiple screens for VMSVGA (build fix).
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1	/* $Id: DevVGA-SVGA.cpp 75717 2018-11-25 16:04:33Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2017 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/AssertGuest.h>
148	#include <VBox/VMMDev.h>
149	#include <VBoxVideo.h>
150	#include <VBox/bioslogo.h>
151
152	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
153	#include "DevVGA.h"
154
155	#include "DevVGA-SVGA.h"
156	#include "vmsvga/svga_reg.h"
157	#include "vmsvga/svga_escape.h"
158	#include "vmsvga/svga_overlay.h"
159	#include "vmsvga/svga3d_reg.h"
160	#include "vmsvga/svga3d_caps.h"
161	#ifdef VBOX_WITH_VMSVGA3D
162	# include "DevVGA-SVGA3d.h"
163	# ifdef RT_OS_DARWIN
164	# include "DevVGA-SVGA3d-cocoa.h"
165	# endif
166	#endif
167
168
169	/*********************************************************************************************************************************
170	* Defined Constants And Macros *
171	*********************************************************************************************************************************/
172	/**
173	* Macro for checking if a fixed FIFO register is valid according to the
174	* current FIFO configuration.
175	*
176	* @returns true / false.
177	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
178	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
179	*/
180	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
181
182
183	/*********************************************************************************************************************************
184	* Structures and Typedefs *
185	*********************************************************************************************************************************/
186	/**
187	* 64-bit GMR descriptor.
188	*/
189	typedef struct
190	{
191	RTGCPHYS GCPhys;
192	uint64_t numPages;
193	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
194
195	/**
196	* GMR slot
197	*/
198	typedef struct
199	{
200	uint32_t cMaxPages;
201	uint32_t cbTotal;
202	uint32_t numDescriptors;
203	PVMSVGAGMRDESCRIPTOR paDesc;
204	} GMR, *PGMR;
205
206	#ifdef IN_RING3
207	/**
208	* Internal SVGA ring-3 only state.
209	*/
210	typedef struct VMSVGAR3STATE
211	{
212	GMR *paGMR; // [VMSVGAState::cGMR]
213	struct
214	{
215	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
216	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
217	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
218	} GMRFB;
219	struct
220	{
221	bool fActive;
222	uint32_t xHotspot;
223	uint32_t yHotspot;
224	uint32_t width;
225	uint32_t height;
226	uint32_t cbData;
227	void *pData;
228	} Cursor;
229	SVGAColorBGRX colorAnnotation;
230
231	# ifdef VMSVGA_USE_EMT_HALT_CODE
232	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
233	uint32_t volatile cBusyDelayedEmts;
234	/** Set of EMTs that are */
235	VMCPUSET BusyDelayedEmts;
236	# else
237	/** Number of EMTs waiting on hBusyDelayedEmts. */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
240	* busy (ugly). */
241	RTSEMEVENTMULTI hBusyDelayedEmts;
242	# endif
243
244	/** Information obout screens. */
245	VMSVGASCREENOBJECT aScreens[64];
246
247	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
248	STAMPROFILE StatBusyDelayEmts;
249
250	STAMPROFILE StatR3Cmd3dPresentProf;
251	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
252	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
253	STAMCOUNTER StatR3CmdDefineGmr2;
254	STAMCOUNTER StatR3CmdDefineGmr2Free;
255	STAMCOUNTER StatR3CmdDefineGmr2Modify;
256	STAMCOUNTER StatR3CmdRemapGmr2;
257	STAMCOUNTER StatR3CmdRemapGmr2Modify;
258	STAMCOUNTER StatR3CmdInvalidCmd;
259	STAMCOUNTER StatR3CmdFence;
260	STAMCOUNTER StatR3CmdUpdate;
261	STAMCOUNTER StatR3CmdUpdateVerbose;
262	STAMCOUNTER StatR3CmdDefineCursor;
263	STAMCOUNTER StatR3CmdDefineAlphaCursor;
264	STAMCOUNTER StatR3CmdEscape;
265	STAMCOUNTER StatR3CmdDefineScreen;
266	STAMCOUNTER StatR3CmdDestroyScreen;
267	STAMCOUNTER StatR3CmdDefineGmrFb;
268	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
269	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
270	STAMCOUNTER StatR3CmdAnnotationFill;
271	STAMCOUNTER StatR3CmdAnnotationCopy;
272	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
274	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
275	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
276	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
277	STAMCOUNTER StatR3Cmd3dSurfaceDma;
278	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
279	STAMCOUNTER StatR3Cmd3dContextDefine;
280	STAMCOUNTER StatR3Cmd3dContextDestroy;
281	STAMCOUNTER StatR3Cmd3dSetTransform;
282	STAMCOUNTER StatR3Cmd3dSetZRange;
283	STAMCOUNTER StatR3Cmd3dSetRenderState;
284	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
285	STAMCOUNTER StatR3Cmd3dSetTextureState;
286	STAMCOUNTER StatR3Cmd3dSetMaterial;
287	STAMCOUNTER StatR3Cmd3dSetLightData;
288	STAMCOUNTER StatR3Cmd3dSetLightEnable;
289	STAMCOUNTER StatR3Cmd3dSetViewPort;
290	STAMCOUNTER StatR3Cmd3dSetClipPlane;
291	STAMCOUNTER StatR3Cmd3dClear;
292	STAMCOUNTER StatR3Cmd3dPresent;
293	STAMCOUNTER StatR3Cmd3dPresentReadBack;
294	STAMCOUNTER StatR3Cmd3dShaderDefine;
295	STAMCOUNTER StatR3Cmd3dShaderDestroy;
296	STAMCOUNTER StatR3Cmd3dSetShader;
297	STAMCOUNTER StatR3Cmd3dSetShaderConst;
298	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
299	STAMCOUNTER StatR3Cmd3dSetScissorRect;
300	STAMCOUNTER StatR3Cmd3dBeginQuery;
301	STAMCOUNTER StatR3Cmd3dEndQuery;
302	STAMCOUNTER StatR3Cmd3dWaitForQuery;
303	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
304	STAMCOUNTER StatR3Cmd3dActivateSurface;
305	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
306
307	STAMCOUNTER StatR3RegConfigDoneWr;
308	STAMCOUNTER StatR3RegGmrDescriptorWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
310	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
311
312	STAMCOUNTER StatFifoCommands;
313	STAMCOUNTER StatFifoErrors;
314	STAMCOUNTER StatFifoUnkCmds;
315	STAMCOUNTER StatFifoTodoTimeout;
316	STAMCOUNTER StatFifoTodoWoken;
317	STAMPROFILE StatFifoStalls;
318
319	} VMSVGAR3STATE, *PVMSVGAR3STATE;
320	#endif /* IN_RING3 */
321
322
323	/*********************************************************************************************************************************
324	* Internal Functions *
325	*********************************************************************************************************************************/
326	#ifdef IN_RING3
327	# ifdef DEBUG_FIFO_ACCESS
328	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
329	# endif
330	# ifdef DEBUG_GMR_ACCESS
331	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
332	# endif
333	#endif
334
335
336	/*********************************************************************************************************************************
337	* Global Variables *
338	*********************************************************************************************************************************/
339	#ifdef IN_RING3
340
341	/**
342	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
343	*/
344	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
345	{
346	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
347	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
348	SSMFIELD_ENTRY_TERM()
349	};
350
351	/**
352	* SSM descriptor table for the GMR structure.
353	*/
354	static SSMFIELD const g_aGMRFields[] =
355	{
356	SSMFIELD_ENTRY( GMR, cMaxPages),
357	SSMFIELD_ENTRY( GMR, cbTotal),
358	SSMFIELD_ENTRY( GMR, numDescriptors),
359	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
360	SSMFIELD_ENTRY_TERM()
361	};
362
363	/**
364	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
365	*/
366	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
367	{
368	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
369	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
370	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
371	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
372	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
373	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
374	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
375	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
376	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
379	SSMFIELD_ENTRY_TERM()
380	};
381
382	/**
383	* SSM descriptor table for the VMSVGAR3STATE structure.
384	*/
385	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
386	{
387	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
388	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
389	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
390	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
391	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
392	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
393	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
394	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
395	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
396	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
398	#ifdef VMSVGA_USE_EMT_HALT_CODE
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
400	#else
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
402	#endif
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
460
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
465
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
472	SSMFIELD_ENTRY_TERM()
473	};
474
475	/**
476	* SSM descriptor table for the VGAState.svga structure.
477	*/
478	static SSMFIELD const g_aVGAStateSVGAFields[] =
479	{
480	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
481	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
482	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
483	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
485	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
486	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
487	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
490	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
491	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
492	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
493	SSMFIELD_ENTRY( VMSVGAState, fBusy),
494	SSMFIELD_ENTRY( VMSVGAState, fTraces),
495	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
496	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
497	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
498	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
499	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
500	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
501	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
502	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
504	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
508	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
509	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
510	SSMFIELD_ENTRY( VMSVGAState, uWidth),
511	SSMFIELD_ENTRY( VMSVGAState, uHeight),
512	SSMFIELD_ENTRY( VMSVGAState, uBpp),
513	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
514	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
515	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
516	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
517	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
518	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
519	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
523	SSMFIELD_ENTRY_TERM()
524	};
525
526	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
527	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
528	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
529
530	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
531	{
532	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
533	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
534	&& pSVGAState->aScreens[idScreen].fDefined)
535	{
536	return &pSVGAState->aScreens[idScreen];
537	}
538	return NULL;
539	}
540
541	#endif /* IN_RING3 */
542
543	#ifdef LOG_ENABLED
544
545	/**
546	* Index register string name lookup
547	*
548	* @returns Index register string or "UNKNOWN"
549	* @param pThis VMSVGA State
550	* @param idxReg The index register.
551	*/
552	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
553	{
554	switch (idxReg)
555	{
556	case SVGA_REG_ID: return "SVGA_REG_ID";
557	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
558	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
559	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
560	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
561	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
562	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
563	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
564	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
565	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
566	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
567	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
568	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
569	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
570	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
571	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
572	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
573	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
574	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
575	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
576	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
577	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
578	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
579	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
580	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
581	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
582	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
583	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
584	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
585	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
586	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
587	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
588	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
589	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
590	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
591	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
592	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
593	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
594	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
595	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
596	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
597	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
598	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
599	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
600	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
601	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
602	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
603	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
604	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
605	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
606
607	default:
608	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
609	return "SVGA_SCRATCH_BASE reg";
610	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
611	return "SVGA_PALETTE_BASE reg";
612	return "UNKNOWN";
613	}
614	}
615
616	#ifdef IN_RING3
617	/**
618	* FIFO command name lookup
619	*
620	* @returns FIFO command string or "UNKNOWN"
621	* @param u32Cmd FIFO command
622	*/
623	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
624	{
625	switch (u32Cmd)
626	{
627	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
628	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
629	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
630	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
631	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
632	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
633	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
634	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
635	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
636	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
637	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
638	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
639	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
640	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
641	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
642	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
643	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
644	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
645	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
646	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
647	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
648	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
649	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
650	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
651	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
652	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
653	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
654	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
655	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
656	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
657	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
658	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
659	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
660	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
661	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
662	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
663	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
664	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
665	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
666	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
667	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
668	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
669	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
670	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
671	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
672	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
673	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
674	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
675	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
676	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
677	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
678	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
679	default: return "UNKNOWN";
680	}
681	}
682	# endif /* IN_RING3 */
683
684	#endif /* LOG_ENABLED */
685
686	#ifdef IN_RING3
687	/**
688	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
689	*/
690	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
691	{
692	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
693
694	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
695	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
696
697	/** @todo Test how it interacts with multiple screen objects. */
698	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
699	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
700	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
701
702	if (x < uWidth)
703	{
704	pThis->svga.viewport.x = x;
705	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
706	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
707	}
708	else
709	{
710	pThis->svga.viewport.x = uWidth;
711	pThis->svga.viewport.cx = 0;
712	pThis->svga.viewport.xRight = uWidth;
713	}
714	if (y < uHeight)
715	{
716	pThis->svga.viewport.y = y;
717	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
718	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
719	pThis->svga.viewport.yHighWC = uHeight - y;
720	}
721	else
722	{
723	pThis->svga.viewport.y = uHeight;
724	pThis->svga.viewport.cy = 0;
725	pThis->svga.viewport.yLowWC = 0;
726	pThis->svga.viewport.yHighWC = 0;
727	}
728
729	# ifdef VBOX_WITH_VMSVGA3D
730	/*
731	* Now inform the 3D backend.
732	*/
733	if (pThis->svga.f3DEnabled)
734	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
735	# else
736	RT_NOREF(OldViewport);
737	# endif
738	}
739	#endif /* IN_RING3 */
740
741	/**
742	* Read port register
743	*
744	* @returns VBox status code.
745	* @param pThis VMSVGA State
746	* @param pu32 Where to store the read value
747	*/
748	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
749	{
750	int rc = VINF_SUCCESS;
751	*pu32 = 0;
752
753	/* Rough index register validation. */
754	uint32_t idxReg = pThis->svga.u32IndexReg;
755	#if !defined(IN_RING3) && defined(VBOX_STRICT)
756	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
757	VINF_IOM_R3_IOPORT_READ);
758	#else
759	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
760	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
761	VINF_SUCCESS);
762	#endif
763	RT_UNTRUSTED_VALIDATED_FENCE();
764
765	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
766	if ( idxReg >= SVGA_REG_CAPABILITIES
767	&& pThis->svga.u32SVGAId == SVGA_ID_0)
768	{
769	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
770	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
771	}
772
773	switch (idxReg)
774	{
775	case SVGA_REG_ID:
776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
777	*pu32 = pThis->svga.u32SVGAId;
778	break;
779
780	case SVGA_REG_ENABLE:
781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
782	*pu32 = pThis->svga.fEnabled;
783	break;
784
785	case SVGA_REG_WIDTH:
786	{
787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
788	if ( pThis->svga.fEnabled
789	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
790	{
791	*pu32 = pThis->svga.uWidth;
792	}
793	else
794	{
795	#ifndef IN_RING3
796	rc = VINF_IOM_R3_IOPORT_READ;
797	#else
798	*pu32 = pThis->pDrv->cx;
799	#endif
800	}
801	break;
802	}
803
804	case SVGA_REG_HEIGHT:
805	{
806	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
807	if ( pThis->svga.fEnabled
808	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
809	{
810	*pu32 = pThis->svga.uHeight;
811	}
812	else
813	{
814	#ifndef IN_RING3
815	rc = VINF_IOM_R3_IOPORT_READ;
816	#else
817	*pu32 = pThis->pDrv->cy;
818	#endif
819	}
820	break;
821	}
822
823	case SVGA_REG_MAX_WIDTH:
824	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
825	*pu32 = pThis->svga.u32MaxWidth;
826	break;
827
828	case SVGA_REG_MAX_HEIGHT:
829	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
830	*pu32 = pThis->svga.u32MaxHeight;
831	break;
832
833	case SVGA_REG_DEPTH:
834	/* This returns the color depth of the current mode. */
835	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
836	switch (pThis->svga.uBpp)
837	{
838	case 15:
839	case 16:
840	case 24:
841	*pu32 = pThis->svga.uBpp;
842	break;
843
844	default:
845	case 32:
846	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
847	break;
848	}
849	break;
850
851	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
852	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
853	if ( pThis->svga.fEnabled
854	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
855	{
856	*pu32 = pThis->svga.uBpp;
857	}
858	else
859	{
860	#ifndef IN_RING3
861	rc = VINF_IOM_R3_IOPORT_READ;
862	#else
863	*pu32 = pThis->pDrv->cBits;
864	#endif
865	}
866	break;
867
868	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
869	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
870	if ( pThis->svga.fEnabled
871	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
872	{
873	*pu32 = (pThis->svga.uBpp + 7) & ~7;
874	}
875	else
876	{
877	#ifndef IN_RING3
878	rc = VINF_IOM_R3_IOPORT_READ;
879	#else
880	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
881	#endif
882	}
883	break;
884
885	case SVGA_REG_PSEUDOCOLOR:
886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
887	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
888	break;
889
890	case SVGA_REG_RED_MASK:
891	case SVGA_REG_GREEN_MASK:
892	case SVGA_REG_BLUE_MASK:
893	{
894	uint32_t uBpp;
895
896	if ( pThis->svga.fEnabled
897	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
898	{
899	uBpp = pThis->svga.uBpp;
900	}
901	else
902	{
903	#ifndef IN_RING3
904	rc = VINF_IOM_R3_IOPORT_READ;
905	break;
906	#else
907	uBpp = pThis->pDrv->cBits;
908	#endif
909	}
910	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
911	switch (uBpp)
912	{
913	case 8:
914	u32RedMask = 0x07;
915	u32GreenMask = 0x38;
916	u32BlueMask = 0xc0;
917	break;
918
919	case 15:
920	u32RedMask = 0x0000001f;
921	u32GreenMask = 0x000003e0;
922	u32BlueMask = 0x00007c00;
923	break;
924
925	case 16:
926	u32RedMask = 0x0000001f;
927	u32GreenMask = 0x000007e0;
928	u32BlueMask = 0x0000f800;
929	break;
930
931	case 24:
932	case 32:
933	default:
934	u32RedMask = 0x00ff0000;
935	u32GreenMask = 0x0000ff00;
936	u32BlueMask = 0x000000ff;
937	break;
938	}
939	switch (idxReg)
940	{
941	case SVGA_REG_RED_MASK:
942	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
943	*pu32 = u32RedMask;
944	break;
945
946	case SVGA_REG_GREEN_MASK:
947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
948	*pu32 = u32GreenMask;
949	break;
950
951	case SVGA_REG_BLUE_MASK:
952	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
953	*pu32 = u32BlueMask;
954	break;
955	}
956	break;
957	}
958
959	case SVGA_REG_BYTES_PER_LINE:
960	{
961	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
962	if ( pThis->svga.fEnabled
963	&& pThis->svga.cbScanline)
964	{
965	*pu32 = pThis->svga.cbScanline;
966	}
967	else
968	{
969	#ifndef IN_RING3
970	rc = VINF_IOM_R3_IOPORT_READ;
971	#else
972	*pu32 = pThis->pDrv->cbScanline;
973	#endif
974	}
975	break;
976	}
977
978	case SVGA_REG_VRAM_SIZE: /* VRAM size */
979	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
980	*pu32 = pThis->vram_size;
981	break;
982
983	case SVGA_REG_FB_START: /* Frame buffer physical address. */
984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
985	Assert(pThis->GCPhysVRAM <= 0xffffffff);
986	*pu32 = pThis->GCPhysVRAM;
987	break;
988
989	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
990	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
991	/* Always zero in our case. */
992	*pu32 = 0;
993	break;
994
995	case SVGA_REG_FB_SIZE: /* Frame buffer size */
996	{
997	#ifndef IN_RING3
998	rc = VINF_IOM_R3_IOPORT_READ;
999	#else
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1001
1002	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1003	if ( pThis->svga.fEnabled
1004	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1005	{
1006	/* Hardware enabled; return real framebuffer size .*/
1007	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1008	}
1009	else
1010	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1011
1012	pu32 = RT_MIN(pThis->vram_size, pu32);
1013	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1014	#endif
1015	break;
1016	}
1017
1018	case SVGA_REG_CAPABILITIES:
1019	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1020	*pu32 = pThis->svga.u32RegCaps;
1021	break;
1022
1023	case SVGA_REG_MEM_START: /* FIFO start */
1024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1025	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1026	*pu32 = pThis->svga.GCPhysFIFO;
1027	break;
1028
1029	case SVGA_REG_MEM_SIZE: /* FIFO size */
1030	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1031	*pu32 = pThis->svga.cbFIFO;
1032	break;
1033
1034	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1035	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1036	*pu32 = pThis->svga.fConfigured;
1037	break;
1038
1039	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1041	*pu32 = 0;
1042	break;
1043
1044	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1046	if (pThis->svga.fBusy)
1047	{
1048	#ifndef IN_RING3
1049	/* Go to ring-3 and halt the CPU. */
1050	rc = VINF_IOM_R3_IOPORT_READ;
1051	break;
1052	#else
1053	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1054	/* The guest is basically doing a HLT via the device here, but with
1055	a special wake up condition on FIFO completion. */
1056	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1057	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1058	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1059	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1060	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1061	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1062	if (pThis->svga.fBusy)
1063	{
1064	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1065	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1066	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1067	}
1068	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1069	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1070	# else
1071
1072	/* Delay the EMT a bit so the FIFO and others can get some work done.
1073	This used to be a crude 50 ms sleep. The current code tries to be
1074	more efficient, but the consept is still very crude. */
1075	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1076	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1077	RTThreadYield();
1078	if (pThis->svga.fBusy)
1079	{
1080	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1081
1082	if (pThis->svga.fBusy && cRefs == 1)
1083	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1084	if (pThis->svga.fBusy)
1085	{
1086	/** @todo If this code is going to stay, we need to call into the halt/wait
1087	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1088	* suffer when the guest is polling on a busy FIFO. */
1089	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1090	if (cNsMaxWait >= RT_NS_100US)
1091	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1092	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1093	RT_MIN(cNsMaxWait, RT_NS_10MS));
1094	}
1095
1096	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1097	}
1098	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1099	# endif
1100	*pu32 = pThis->svga.fBusy != 0;
1101	#endif
1102	}
1103	else
1104	*pu32 = false;
1105	break;
1106
1107	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1108	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1109	*pu32 = pThis->svga.u32GuestId;
1110	break;
1111
1112	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1114	*pu32 = pThis->svga.cScratchRegion;
1115	break;
1116
1117	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1119	*pu32 = SVGA_FIFO_NUM_REGS;
1120	break;
1121
1122	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1123	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1124	*pu32 = pThis->svga.u32PitchLock;
1125	break;
1126
1127	case SVGA_REG_IRQMASK: /* Interrupt mask */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1129	*pu32 = pThis->svga.u32IrqMask;
1130	break;
1131
1132	/* See "Guest memory regions" below. */
1133	case SVGA_REG_GMR_ID:
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1135	*pu32 = pThis->svga.u32CurrentGMRId;
1136	break;
1137
1138	case SVGA_REG_GMR_DESCRIPTOR:
1139	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1140	/* Write only */
1141	*pu32 = 0;
1142	break;
1143
1144	case SVGA_REG_GMR_MAX_IDS:
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1146	*pu32 = pThis->svga.cGMR;
1147	break;
1148
1149	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1151	*pu32 = VMSVGA_MAX_GMR_PAGES;
1152	break;
1153
1154	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1155	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1156	*pu32 = pThis->svga.fTraces;
1157	break;
1158
1159	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1160	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1161	*pu32 = VMSVGA_MAX_GMR_PAGES;
1162	break;
1163
1164	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1166	*pu32 = VMSVGA_SURFACE_SIZE;
1167	break;
1168
1169	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1171	break;
1172
1173	/* Mouse cursor support. */
1174	case SVGA_REG_CURSOR_ID:
1175	case SVGA_REG_CURSOR_X:
1176	case SVGA_REG_CURSOR_Y:
1177	case SVGA_REG_CURSOR_ON:
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1179	break;
1180
1181	/* Legacy multi-monitor support */
1182	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1183	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1184	*pu32 = 1;
1185	break;
1186
1187	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1189	*pu32 = 0;
1190	break;
1191
1192	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1194	*pu32 = 0;
1195	break;
1196
1197	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1199	*pu32 = 0;
1200	break;
1201
1202	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1204	*pu32 = 0;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1209	*pu32 = pThis->svga.uWidth;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1214	*pu32 = pThis->svga.uHeight;
1215	break;
1216
1217	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1219	/** @todo keep 1? */
1220	pu32 = 1; / Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
1221	break;
1222
1223	default:
1224	{
1225	uint32_t offReg;
1226	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1227	{
1228	RT_UNTRUSTED_VALIDATED_FENCE();
1229	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1231	}
1232	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1233	{
1234	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1236	RT_UNTRUSTED_VALIDATED_FENCE();
1237	uint32_t u32 = pThis->last_palette[offReg / 3];
1238	switch (offReg % 3)
1239	{
1240	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1241	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1242	case 2: pu32 = u32 & 0xff; break; / blue */
1243	}
1244	}
1245	else
1246	{
1247	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1248	rc = VINF_IOM_R3_IOPORT_READ;
1249	#else
1250	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1251
1252	/* Do not assert. The guest might be reading all registers. */
1253	LogFunc(("Unknown reg=%#x\n", idxReg));
1254	#endif
1255	}
1256	break;
1257	}
1258	}
1259	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1260	return rc;
1261	}
1262
1263	#ifdef IN_RING3
1264	/**
1265	* Apply the current resolution settings to change the video mode.
1266	*
1267	* @returns VBox status code.
1268	* @param pThis VMSVGA State
1269	*/
1270	static int vmsvgaChangeMode(PVGASTATE pThis)
1271	{
1272	int rc;
1273
1274	/* Always do changemode on FIFO thread. */
1275	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1276
1277	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1278
1279	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1280
1281	if (pThis->svga.fGFBRegisters)
1282	{
1283	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1284	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1285	* deletes all screens other than screen #0, and redefines screen
1286	* #0 according to the specified mode. Drivers that use
1287	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1288	*/
1289
1290	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1291	pScreen->fDefined = true;
1292	pScreen->fModified = true;
1293	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1294	pScreen->idScreen = 0;
1295	pScreen->xOrigin = 0;
1296	pScreen->yOrigin = 0;
1297	pScreen->offVRAM = 0;
1298	pScreen->cbPitch = pThis->svga.cbScanline;
1299	pScreen->cWidth = pThis->svga.uWidth;
1300	pScreen->cHeight = pThis->svga.uHeight;
1301	pScreen->cBpp = pThis->svga.uBpp;
1302
1303	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1304	{
1305	/* Delete screen. */
1306	pScreen = &pSVGAState->aScreens[iScreen];
1307	if (pScreen->fDefined)
1308	{
1309	pScreen->fModified = true;
1310	pScreen->fDefined = false;
1311	}
1312	}
1313	}
1314	else
1315	{
1316	/* "If Screen Objects are supported, they can be used to fully
1317	* replace the functionality provided by the framebuffer registers
1318	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1319	*/
1320	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1321	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1322	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1323	}
1324
1325	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1328	if (!pScreen->fModified)
1329	continue;
1330
1331	pScreen->fModified = false;
1332
1333	VBVAINFOVIEW view;
1334	RT_ZERO(view);
1335	view.u32ViewIndex = pScreen->idScreen;
1336	// view.u32ViewOffset = 0;
1337	view.u32ViewSize = pThis->vram_size;
1338	view.u32MaxScreenSize = pThis->vram_size;
1339
1340	VBVAINFOSCREEN screen;
1341	RT_ZERO(screen);
1342	screen.u32ViewIndex = pScreen->idScreen;
1343
1344	if (pScreen->fDefined)
1345	{
1346	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1347	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1348	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1349	{
1350	Assert(pThis->svga.fGFBRegisters);
1351	continue;
1352	}
1353
1354	screen.i32OriginX = pScreen->xOrigin;
1355	screen.i32OriginY = pScreen->yOrigin;
1356	screen.u32StartOffset = pScreen->offVRAM;
1357	screen.u32LineSize = pScreen->cbPitch;
1358	screen.u32Width = pScreen->cWidth;
1359	screen.u32Height = pScreen->cHeight;
1360	screen.u16BitsPerPixel = pScreen->cBpp;
1361	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1362	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1363	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1364	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1365	}
1366	else
1367	{
1368	/* Screen is destroyed. */
1369	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1370	}
1371
1372	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1373	AssertRC(rc);
1374	}
1375
1376	/* Last stuff. For the VGA device screenshot. */
1377	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1378	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1379	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1380	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1381	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1382
1383	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1384	if ( pThis->svga.viewport.cx == 0
1385	&& pThis->svga.viewport.cy == 0)
1386	{
1387	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1388	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1389	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1390	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1391	pThis->svga.viewport.yLowWC = 0;
1392	}
1393
1394	return VINF_SUCCESS;
1395	}
1396
1397	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1398	{
1399	if (pThis->svga.fGFBRegisters)
1400	{
1401	vgaR3UpdateDisplay(pThis, x, y, w, h);
1402	}
1403	else
1404	{
1405	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1406	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1407	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1408	}
1409
1410	return VINF_SUCCESS;
1411	}
1412
1413	#endif /* IN_RING3 */
1414
1415	#if defined(IN_RING0) \|\| defined(IN_RING3)
1416	/**
1417	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1418	*
1419	* @param pThis The VMSVGA state.
1420	* @param fState The busy state.
1421	*/
1422	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1423	{
1424	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1425
1426	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1427	{
1428	/* Race / unfortunately scheduling. Highly unlikly. */
1429	uint32_t cLoops = 64;
1430	do
1431	{
1432	ASMNopPause();
1433	fState = (pThis->svga.fBusy != 0);
1434	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1435	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1436	}
1437	}
1438	#endif
1439
1440	/**
1441	* Write port register
1442	*
1443	* @returns VBox status code.
1444	* @param pThis VMSVGA State
1445	* @param u32 Value to write
1446	*/
1447	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1448	{
1449	#ifdef IN_RING3
1450	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1451	#endif
1452	int rc = VINF_SUCCESS;
1453
1454	/* Rough index register validation. */
1455	uint32_t idxReg = pThis->svga.u32IndexReg;
1456	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1457	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1458	VINF_IOM_R3_IOPORT_WRITE);
1459	#else
1460	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1461	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1462	VINF_SUCCESS);
1463	#endif
1464	RT_UNTRUSTED_VALIDATED_FENCE();
1465
1466	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1467	if ( idxReg >= SVGA_REG_CAPABILITIES
1468	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1469	{
1470	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1471	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1472	}
1473	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1474	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1475	switch (idxReg)
1476	{
1477	case SVGA_REG_WIDTH:
1478	case SVGA_REG_HEIGHT:
1479	case SVGA_REG_PITCHLOCK:
1480	case SVGA_REG_BITS_PER_PIXEL:
1481	pThis->svga.fGFBRegisters = true;
1482	break;
1483	default:
1484	break;
1485	}
1486
1487	switch (idxReg)
1488	{
1489	case SVGA_REG_ID:
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1491	if ( u32 == SVGA_ID_0
1492	\|\| u32 == SVGA_ID_1
1493	\|\| u32 == SVGA_ID_2)
1494	pThis->svga.u32SVGAId = u32;
1495	else
1496	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1497	break;
1498
1499	case SVGA_REG_ENABLE:
1500	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1501	#ifdef IN_RING3
1502	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1503	&& pThis->svga.fEnabled == false)
1504	{
1505	/* Make a backup copy of the first 512kb in order to save font data etc. */
1506	/** @todo should probably swap here, rather than copy + zero */
1507	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1508	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1509	}
1510
1511	pThis->svga.fEnabled = u32;
1512	if (pThis->svga.fEnabled)
1513	{
1514	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1515	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1516	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1517	{
1518	/* Keep the current mode. */
1519	pThis->svga.uWidth = pThis->pDrv->cx;
1520	pThis->svga.uHeight = pThis->pDrv->cy;
1521	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1522	}
1523
1524	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1525	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1526	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1527	{
1528	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1529	}
1530	# ifdef LOG_ENABLED
1531	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1532	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1533	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1534	# endif
1535
1536	/* Disable or enable dirty page tracking according to the current fTraces value. */
1537	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1538	}
1539	else
1540	{
1541	/* Restore the text mode backup. */
1542	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1543
1544	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1545
1546	/* Enable dirty page tracking again when going into legacy mode. */
1547	vmsvgaSetTraces(pThis, true);
1548	}
1549	#else /* !IN_RING3 */
1550	rc = VINF_IOM_R3_IOPORT_WRITE;
1551	#endif /* !IN_RING3 */
1552	break;
1553
1554	case SVGA_REG_WIDTH:
1555	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1556	if (pThis->svga.uWidth != u32)
1557	{
1558	pThis->svga.uWidth = u32;
1559	if (pThis->svga.fEnabled)
1560	{
1561	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1562	}
1563	}
1564	/* else: nop */
1565	break;
1566
1567	case SVGA_REG_HEIGHT:
1568	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1569	if (pThis->svga.uHeight != u32)
1570	{
1571	pThis->svga.uHeight = u32;
1572	if (pThis->svga.fEnabled)
1573	{
1574	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1575	}
1576	}
1577	/* else: nop */
1578	break;
1579
1580	case SVGA_REG_DEPTH:
1581	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1582	/** @todo read-only?? */
1583	break;
1584
1585	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1586	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1587	if (pThis->svga.uBpp != u32)
1588	{
1589	pThis->svga.uBpp = u32;
1590	if (pThis->svga.fEnabled)
1591	{
1592	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1593	}
1594	}
1595	/* else: nop */
1596	break;
1597
1598	case SVGA_REG_PSEUDOCOLOR:
1599	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1600	break;
1601
1602	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1603	#ifdef IN_RING3
1604	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1605	pThis->svga.fConfigured = u32;
1606	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1607	if (!pThis->svga.fConfigured)
1608	{
1609	pThis->svga.fTraces = true;
1610	}
1611	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1612	#else
1613	rc = VINF_IOM_R3_IOPORT_WRITE;
1614	#endif
1615	break;
1616
1617	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1618	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1619	if ( pThis->svga.fEnabled
1620	&& pThis->svga.fConfigured)
1621	{
1622	#if defined(IN_RING3) \|\| defined(IN_RING0)
1623	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1624	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1625	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1626	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1627
1628	/* Kick the FIFO thread to start processing commands again. */
1629	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1630	#else
1631	rc = VINF_IOM_R3_IOPORT_WRITE;
1632	#endif
1633	}
1634	/* else nothing to do. */
1635	else
1636	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1637
1638	break;
1639
1640	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1641	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1642	break;
1643
1644	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1645	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1646	pThis->svga.u32GuestId = u32;
1647	break;
1648
1649	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1650	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1651	pThis->svga.u32PitchLock = u32;
1652	break;
1653
1654	case SVGA_REG_IRQMASK: /* Interrupt mask */
1655	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1656	pThis->svga.u32IrqMask = u32;
1657
1658	/* Irq pending after the above change? */
1659	if (pThis->svga.u32IrqStatus & u32)
1660	{
1661	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1662	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1663	}
1664	else
1665	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1666	break;
1667
1668	/* Mouse cursor support */
1669	case SVGA_REG_CURSOR_ID:
1670	case SVGA_REG_CURSOR_X:
1671	case SVGA_REG_CURSOR_Y:
1672	case SVGA_REG_CURSOR_ON:
1673	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1674	break;
1675
1676	/* Legacy multi-monitor support */
1677	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1678	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1679	break;
1680	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1681	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1682	break;
1683	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1684	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1685	break;
1686	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1687	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1688	break;
1689	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1690	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1691	break;
1692	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1693	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1694	break;
1695	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1696	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1697	break;
1698	#ifdef VBOX_WITH_VMSVGA3D
1699	/* See "Guest memory regions" below. */
1700	case SVGA_REG_GMR_ID:
1701	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1702	pThis->svga.u32CurrentGMRId = u32;
1703	break;
1704
1705	case SVGA_REG_GMR_DESCRIPTOR:
1706	# ifndef IN_RING3
1707	rc = VINF_IOM_R3_IOPORT_WRITE;
1708	break;
1709	# else /* IN_RING3 */
1710	{
1711	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1712
1713	/* Validate current GMR id. */
1714	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1715	AssertBreak(idGMR < pThis->svga.cGMR);
1716	RT_UNTRUSTED_VALIDATED_FENCE();
1717
1718	/* Free the old GMR if present. */
1719	vmsvgaGMRFree(pThis, idGMR);
1720
1721	/* Just undefine the GMR? */
1722	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1723	if (GCPhys == 0)
1724	{
1725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1726	break;
1727	}
1728
1729
1730	/* Never cross a page boundary automatically. */
1731	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1732	uint32_t cPagesTotal = 0;
1733	uint32_t iDesc = 0;
1734	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1735	uint32_t cLoops = 0;
1736	RTGCPHYS GCPhysBase = GCPhys;
1737	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1738	{
1739	/* Read descriptor. */
1740	SVGAGuestMemDescriptor desc;
1741	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1742	AssertRCBreak(rc);
1743
1744	if (desc.numPages != 0)
1745	{
1746	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1747	cPagesTotal += desc.numPages;
1748	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1749
1750	if ((iDesc & 15) == 0)
1751	{
1752	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1753	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1754	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1755	}
1756
1757	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1758	paDescs[iDesc++].numPages = desc.numPages;
1759
1760	/* Continue with the next descriptor. */
1761	GCPhys += sizeof(desc);
1762	}
1763	else if (desc.ppn == 0)
1764	break; /* terminator */
1765	else /* Pointer to the next physical page of descriptors. */
1766	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1767
1768	cLoops++;
1769	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1770	}
1771
1772	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1773	if (RT_SUCCESS(rc))
1774	{
1775	/* Commit the GMR. */
1776	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1777	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1778	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1779	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1780	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1781	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1782	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1783	}
1784	else
1785	{
1786	RTMemFree(paDescs);
1787	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1788	}
1789	break;
1790	}
1791	# endif /* IN_RING3 */
1792	#endif // VBOX_WITH_VMSVGA3D
1793
1794	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1795	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1796	if (pThis->svga.fTraces == u32)
1797	break; /* nothing to do */
1798
1799	#ifdef IN_RING3
1800	vmsvgaSetTraces(pThis, !!u32);
1801	#else
1802	rc = VINF_IOM_R3_IOPORT_WRITE;
1803	#endif
1804	break;
1805
1806	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1808	break;
1809
1810	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1811	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1812	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1813	break;
1814
1815	case SVGA_REG_FB_START:
1816	case SVGA_REG_MEM_START:
1817	case SVGA_REG_HOST_BITS_PER_PIXEL:
1818	case SVGA_REG_MAX_WIDTH:
1819	case SVGA_REG_MAX_HEIGHT:
1820	case SVGA_REG_VRAM_SIZE:
1821	case SVGA_REG_FB_SIZE:
1822	case SVGA_REG_CAPABILITIES:
1823	case SVGA_REG_MEM_SIZE:
1824	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1825	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1826	case SVGA_REG_BYTES_PER_LINE:
1827	case SVGA_REG_FB_OFFSET:
1828	case SVGA_REG_RED_MASK:
1829	case SVGA_REG_GREEN_MASK:
1830	case SVGA_REG_BLUE_MASK:
1831	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1832	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1833	case SVGA_REG_GMR_MAX_IDS:
1834	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1835	/* Read only - ignore. */
1836	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1837	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1838	break;
1839
1840	default:
1841	{
1842	uint32_t offReg;
1843	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1844	{
1845	RT_UNTRUSTED_VALIDATED_FENCE();
1846	pThis->svga.au32ScratchRegion[offReg] = u32;
1847	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1848	}
1849	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1850	{
1851	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1852	Btw, see rgb_to_pixel32. */
1853	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1854	u32 &= 0xff;
1855	RT_UNTRUSTED_VALIDATED_FENCE();
1856	uint32_t uRgb = pThis->last_palette[offReg / 3];
1857	switch (offReg % 3)
1858	{
1859	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1860	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1861	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1862	}
1863	pThis->last_palette[offReg / 3] = uRgb;
1864	}
1865	else
1866	{
1867	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1868	rc = VINF_IOM_R3_IOPORT_WRITE;
1869	#else
1870	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1871	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1872	#endif
1873	}
1874	break;
1875	}
1876	}
1877	return rc;
1878	}
1879
1880	/**
1881	* Port I/O Handler for IN operations.
1882	*
1883	* @returns VINF_SUCCESS or VINF_EM_*.
1884	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1885	*
1886	* @param pDevIns The device instance.
1887	* @param pvUser User argument.
1888	* @param uPort Port number used for the IN operation.
1889	* @param pu32 Where to store the result. This is always a 32-bit
1890	* variable regardless of what @a cb might say.
1891	* @param cb Number of bytes read.
1892	*/
1893	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1894	{
1895	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1896	RT_NOREF_PV(pvUser);
1897
1898	/* Ignore non-dword accesses. */
1899	if (cb != 4)
1900	{
1901	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1902	*pu32 = UINT32_MAX;
1903	return VINF_SUCCESS;
1904	}
1905
1906	switch (uPort - pThis->svga.BasePort)
1907	{
1908	case SVGA_INDEX_PORT:
1909	*pu32 = pThis->svga.u32IndexReg;
1910	break;
1911
1912	case SVGA_VALUE_PORT:
1913	return vmsvgaReadPort(pThis, pu32);
1914
1915	case SVGA_BIOS_PORT:
1916	Log(("Ignoring BIOS port read\n"));
1917	*pu32 = 0;
1918	break;
1919
1920	case SVGA_IRQSTATUS_PORT:
1921	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1922	*pu32 = pThis->svga.u32IrqStatus;
1923	break;
1924
1925	default:
1926	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1927	*pu32 = UINT32_MAX;
1928	break;
1929	}
1930
1931	return VINF_SUCCESS;
1932	}
1933
1934	/**
1935	* Port I/O Handler for OUT operations.
1936	*
1937	* @returns VINF_SUCCESS or VINF_EM_*.
1938	*
1939	* @param pDevIns The device instance.
1940	* @param pvUser User argument.
1941	* @param uPort Port number used for the OUT operation.
1942	* @param u32 The value to output.
1943	* @param cb The value size in bytes.
1944	*/
1945	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1946	{
1947	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1948	RT_NOREF_PV(pvUser);
1949
1950	/* Ignore non-dword accesses. */
1951	if (cb != 4)
1952	{
1953	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1954	return VINF_SUCCESS;
1955	}
1956
1957	switch (uPort - pThis->svga.BasePort)
1958	{
1959	case SVGA_INDEX_PORT:
1960	pThis->svga.u32IndexReg = u32;
1961	break;
1962
1963	case SVGA_VALUE_PORT:
1964	return vmsvgaWritePort(pThis, u32);
1965
1966	case SVGA_BIOS_PORT:
1967	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1968	break;
1969
1970	case SVGA_IRQSTATUS_PORT:
1971	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1972	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1973	/* Clear the irq in case all events have been cleared. */
1974	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1975	{
1976	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1977	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1978	}
1979	break;
1980
1981	default:
1982	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
1983	uPort - pThis->svga.BasePort, uPort, u32, cb));
1984	break;
1985	}
1986	return VINF_SUCCESS;
1987	}
1988
1989	#ifdef DEBUG_FIFO_ACCESS
1990
1991	# ifdef IN_RING3
1992	/**
1993	* Handle LFB access.
1994	* @returns VBox status code.
1995	* @param pVM VM handle.
1996	* @param pThis VGA device instance data.
1997	* @param GCPhys The access physical address.
1998	* @param fWriteAccess Read or write access
1999	*/
2000	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2001	{
2002	RT_NOREF(pVM);
2003	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2004	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2005
2006	switch (GCPhysOffset >> 2)
2007	{
2008	case SVGA_FIFO_MIN:
2009	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2010	break;
2011	case SVGA_FIFO_MAX:
2012	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2013	break;
2014	case SVGA_FIFO_NEXT_CMD:
2015	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2016	break;
2017	case SVGA_FIFO_STOP:
2018	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2019	break;
2020	case SVGA_FIFO_CAPABILITIES:
2021	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2022	break;
2023	case SVGA_FIFO_FLAGS:
2024	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2025	break;
2026	case SVGA_FIFO_FENCE:
2027	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2028	break;
2029	case SVGA_FIFO_3D_HWVERSION:
2030	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2031	break;
2032	case SVGA_FIFO_PITCHLOCK:
2033	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2034	break;
2035	case SVGA_FIFO_CURSOR_ON:
2036	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2037	break;
2038	case SVGA_FIFO_CURSOR_X:
2039	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2040	break;
2041	case SVGA_FIFO_CURSOR_Y:
2042	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2043	break;
2044	case SVGA_FIFO_CURSOR_COUNT:
2045	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2046	break;
2047	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2048	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2049	break;
2050	case SVGA_FIFO_RESERVED:
2051	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2052	break;
2053	case SVGA_FIFO_CURSOR_SCREEN_ID:
2054	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2055	break;
2056	case SVGA_FIFO_DEAD:
2057	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2058	break;
2059	case SVGA_FIFO_3D_HWVERSION_REVISED:
2060	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2061	break;
2062	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS_LAST:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_GUEST_3D_HWVERSION:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_FENCE_GOAL:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_BUSY:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	default:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	}
2327
2328	return VINF_EM_RAW_EMULATE_INSTR;
2329	}
2330
2331	/**
2332	* HC access handler for the FIFO.
2333	*
2334	* @returns VINF_SUCCESS if the handler have carried out the operation.
2335	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2336	* @param pVM VM Handle.
2337	* @param pVCpu The cross context CPU structure for the calling EMT.
2338	* @param GCPhys The physical address the guest is writing to.
2339	* @param pvPhys The HC mapping of that address.
2340	* @param pvBuf What the guest is reading/writing.
2341	* @param cbBuf How much it's reading/writing.
2342	* @param enmAccessType The access type.
2343	* @param enmOrigin Who is making the access.
2344	* @param pvUser User argument.
2345	*/
2346	static DECLCALLBACK(VBOXSTRICTRC)
2347	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2348	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2349	{
2350	PVGASTATE pThis = (PVGASTATE)pvUser;
2351	int rc;
2352	Assert(pThis);
2353	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2354	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2355
2356	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2357	if (RT_SUCCESS(rc))
2358	return VINF_PGM_HANDLER_DO_DEFAULT;
2359	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2360	return rc;
2361	}
2362
2363	# endif /* IN_RING3 */
2364	#endif /* DEBUG_FIFO_ACCESS */
2365
2366	#ifdef DEBUG_GMR_ACCESS
2367	# ifdef IN_RING3
2368
2369	/**
2370	* HC access handler for the FIFO.
2371	*
2372	* @returns VINF_SUCCESS if the handler have carried out the operation.
2373	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2374	* @param pVM VM Handle.
2375	* @param pVCpu The cross context CPU structure for the calling EMT.
2376	* @param GCPhys The physical address the guest is writing to.
2377	* @param pvPhys The HC mapping of that address.
2378	* @param pvBuf What the guest is reading/writing.
2379	* @param cbBuf How much it's reading/writing.
2380	* @param enmAccessType The access type.
2381	* @param enmOrigin Who is making the access.
2382	* @param pvUser User argument.
2383	*/
2384	static DECLCALLBACK(VBOXSTRICTRC)
2385	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2386	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2387	{
2388	PVGASTATE pThis = (PVGASTATE)pvUser;
2389	Assert(pThis);
2390	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2391	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2392
2393	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2394
2395	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2396	{
2397	PGMR pGMR = &pSVGAState->paGMR[i];
2398
2399	if (pGMR->numDescriptors)
2400	{
2401	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2402	{
2403	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2404	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2405	{
2406	/*
2407	* Turn off the write handler for this particular page and make it R/W.
2408	* Then return telling the caller to restart the guest instruction.
2409	*/
2410	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2411	AssertRC(rc);
2412	goto end;
2413	}
2414	}
2415	}
2416	}
2417	end:
2418	return VINF_PGM_HANDLER_DO_DEFAULT;
2419	}
2420
2421	/* Callback handler for VMR3ReqCallWaitU */
2422	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2423	{
2424	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2425	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2426	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2427	int rc;
2428
2429	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2430	{
2431	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2432	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2433	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2434	AssertRC(rc);
2435	}
2436	return VINF_SUCCESS;
2437	}
2438
2439	/* Callback handler for VMR3ReqCallWaitU */
2440	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2441	{
2442	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2443	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2444	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2445
2446	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2447	{
2448	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2449	AssertRC(rc);
2450	}
2451	return VINF_SUCCESS;
2452	}
2453
2454	/* Callback handler for VMR3ReqCallWaitU */
2455	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2456	{
2457	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2458
2459	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2460	{
2461	PGMR pGMR = &pSVGAState->paGMR[i];
2462
2463	if (pGMR->numDescriptors)
2464	{
2465	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2466	{
2467	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2468	AssertRC(rc);
2469	}
2470	}
2471	}
2472	return VINF_SUCCESS;
2473	}
2474
2475	# endif /* IN_RING3 */
2476	#endif /* DEBUG_GMR_ACCESS */
2477
2478	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2479
2480	#ifdef IN_RING3
2481
2482
2483	/**
2484	* Common worker for changing the pointer shape.
2485	*
2486	* @param pThis The VGA instance data.
2487	* @param pSVGAState The VMSVGA ring-3 instance data.
2488	* @param fAlpha Whether there is alpha or not.
2489	* @param xHot Hotspot x coordinate.
2490	* @param yHot Hotspot y coordinate.
2491	* @param cx Width.
2492	* @param cy Height.
2493	* @param pbData Heap copy of the cursor data. Consumed.
2494	* @param cbData The size of the data.
2495	*/
2496	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2497	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2498	{
2499	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2500	#ifdef LOG_ENABLED
2501	if (LogIs2Enabled())
2502	{
2503	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2504	if (!fAlpha)
2505	{
2506	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2507	for (uint32_t y = 0; y < cy; y++)
2508	{
2509	Log2(("%3u:", y));
2510	uint8_t const pbLine = &pbData[y cbAndLine];
2511	for (uint32_t x = 0; x < cx; x += 8)
2512	{
2513	uint8_t b = pbLine[x / 8];
2514	char szByte[12];
2515	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2516	szByte[1] = b & 0x40 ? '*' : ' ';
2517	szByte[2] = b & 0x20 ? '*' : ' ';
2518	szByte[3] = b & 0x10 ? '*' : ' ';
2519	szByte[4] = b & 0x08 ? '*' : ' ';
2520	szByte[5] = b & 0x04 ? '*' : ' ';
2521	szByte[6] = b & 0x02 ? '*' : ' ';
2522	szByte[7] = b & 0x01 ? '*' : ' ';
2523	szByte[8] = '\0';
2524	Log2(("%s", szByte));
2525	}
2526	Log2(("\n"));
2527	}
2528	}
2529
2530	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2531	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2532	for (uint32_t y = 0; y < cy; y++)
2533	{
2534	Log2(("%3u:", y));
2535	uint32_t const pu32Line = &pu32Xor[y cx];
2536	for (uint32_t x = 0; x < cx; x++)
2537	Log2((" %08x", pu32Line[x]));
2538	Log2(("\n"));
2539	}
2540	}
2541	#endif
2542
2543	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2544	AssertRC(rc);
2545
2546	if (pSVGAState->Cursor.fActive)
2547	RTMemFree(pSVGAState->Cursor.pData);
2548
2549	pSVGAState->Cursor.fActive = true;
2550	pSVGAState->Cursor.xHotspot = xHot;
2551	pSVGAState->Cursor.yHotspot = yHot;
2552	pSVGAState->Cursor.width = cx;
2553	pSVGAState->Cursor.height = cy;
2554	pSVGAState->Cursor.cbData = cbData;
2555	pSVGAState->Cursor.pData = pbData;
2556	}
2557
2558
2559	/**
2560	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2561	*
2562	* @param pThis The VGA instance data.
2563	* @param pSVGAState The VMSVGA ring-3 instance data.
2564	* @param pCursor The cursor.
2565	* @param pbSrcAndMask The AND mask.
2566	* @param cbSrcAndLine The scanline length of the AND mask.
2567	* @param pbSrcXorMask The XOR mask.
2568	* @param cbSrcXorLine The scanline length of the XOR mask.
2569	*/
2570	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2571	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2572	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2573	{
2574	uint32_t const cx = pCursor->width;
2575	uint32_t const cy = pCursor->height;
2576
2577	/*
2578	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2579	* The AND data uses 8-bit aligned scanlines.
2580	* The XOR data must be starting on a 32-bit boundrary.
2581	*/
2582	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2583	uint32_t cbDstAndMask = cbDstAndLine * cy;
2584	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2585	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2586
2587	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2588	AssertReturnVoid(pbCopy);
2589
2590	/* Convert the AND mask. */
2591	uint8_t *pbDst = pbCopy;
2592	uint8_t const *pbSrc = pbSrcAndMask;
2593	switch (pCursor->andMaskDepth)
2594	{
2595	case 1:
2596	if (cbSrcAndLine == cbDstAndLine)
2597	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2598	else
2599	{
2600	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2601	for (uint32_t y = 0; y < cy; y++)
2602	{
2603	memcpy(pbDst, pbSrc, cbDstAndLine);
2604	pbDst += cbDstAndLine;
2605	pbSrc += cbSrcAndLine;
2606	}
2607	}
2608	break;
2609	/* Should take the XOR mask into account for the multi-bit AND mask. */
2610	case 8:
2611	for (uint32_t y = 0; y < cy; y++)
2612	{
2613	for (uint32_t x = 0; x < cx; )
2614	{
2615	uint8_t bDst = 0;
2616	uint8_t fBit = 1;
2617	do
2618	{
2619	uintptr_t const idxPal = pbSrc[x] * 3;
2620	if ((( pThis->last_palette[idxPal]
2621	\| (pThis->last_palette[idxPal] >> 8)
2622	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2623	bDst \|= fBit;
2624	fBit <<= 1;
2625	x++;
2626	} while (x < cx && (x & 7));
2627	pbDst[(x - 1) / 8] = bDst;
2628	}
2629	pbDst += cbDstAndLine;
2630	pbSrc += cbSrcAndLine;
2631	}
2632	break;
2633	case 15:
2634	for (uint32_t y = 0; y < cy; y++)
2635	{
2636	for (uint32_t x = 0; x < cx; )
2637	{
2638	uint8_t bDst = 0;
2639	uint8_t fBit = 1;
2640	do
2641	{
2642	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2643	bDst \|= fBit;
2644	fBit <<= 1;
2645	x++;
2646	} while (x < cx && (x & 7));
2647	pbDst[(x - 1) / 8] = bDst;
2648	}
2649	pbDst += cbDstAndLine;
2650	pbSrc += cbSrcAndLine;
2651	}
2652	break;
2653	case 16:
2654	for (uint32_t y = 0; y < cy; y++)
2655	{
2656	for (uint32_t x = 0; x < cx; )
2657	{
2658	uint8_t bDst = 0;
2659	uint8_t fBit = 1;
2660	do
2661	{
2662	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2663	bDst \|= fBit;
2664	fBit <<= 1;
2665	x++;
2666	} while (x < cx && (x & 7));
2667	pbDst[(x - 1) / 8] = bDst;
2668	}
2669	pbDst += cbDstAndLine;
2670	pbSrc += cbSrcAndLine;
2671	}
2672	break;
2673	case 24:
2674	for (uint32_t y = 0; y < cy; y++)
2675	{
2676	for (uint32_t x = 0; x < cx; )
2677	{
2678	uint8_t bDst = 0;
2679	uint8_t fBit = 1;
2680	do
2681	{
2682	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2683	bDst \|= fBit;
2684	fBit <<= 1;
2685	x++;
2686	} while (x < cx && (x & 7));
2687	pbDst[(x - 1) / 8] = bDst;
2688	}
2689	pbDst += cbDstAndLine;
2690	pbSrc += cbSrcAndLine;
2691	}
2692	break;
2693	case 32:
2694	for (uint32_t y = 0; y < cy; y++)
2695	{
2696	for (uint32_t x = 0; x < cx; )
2697	{
2698	uint8_t bDst = 0;
2699	uint8_t fBit = 1;
2700	do
2701	{
2702	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2703	bDst \|= fBit;
2704	fBit <<= 1;
2705	x++;
2706	} while (x < cx && (x & 7));
2707	pbDst[(x - 1) / 8] = bDst;
2708	}
2709	pbDst += cbDstAndLine;
2710	pbSrc += cbSrcAndLine;
2711	}
2712	break;
2713	default:
2714	RTMemFree(pbCopy);
2715	AssertFailedReturnVoid();
2716	}
2717
2718	/* Convert the XOR mask. */
2719	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2720	pbSrc = pbSrcXorMask;
2721	switch (pCursor->xorMaskDepth)
2722	{
2723	case 1:
2724	for (uint32_t y = 0; y < cy; y++)
2725	{
2726	for (uint32_t x = 0; x < cx; )
2727	{
2728	/* most significant bit is the left most one. */
2729	uint8_t bSrc = pbSrc[x / 8];
2730	do
2731	{
2732	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2733	bSrc <<= 1;
2734	x++;
2735	} while ((x & 7) && x < cx);
2736	}
2737	pbSrc += cbSrcXorLine;
2738	}
2739	break;
2740	case 8:
2741	for (uint32_t y = 0; y < cy; y++)
2742	{
2743	for (uint32_t x = 0; x < cx; x++)
2744	{
2745	uint32_t u = pThis->last_palette[pbSrc[x]];
2746	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2747	}
2748	pbSrc += cbSrcXorLine;
2749	}
2750	break;
2751	case 15: /* Src: RGB-5-5-5 */
2752	for (uint32_t y = 0; y < cy; y++)
2753	{
2754	for (uint32_t x = 0; x < cx; x++)
2755	{
2756	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2757	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2758	((uValue >> 5) & 0x1f) << 3,
2759	((uValue >> 10) & 0x1f) << 3, 0);
2760	}
2761	pbSrc += cbSrcXorLine;
2762	}
2763	break;
2764	case 16: /* Src: RGB-5-6-5 */
2765	for (uint32_t y = 0; y < cy; y++)
2766	{
2767	for (uint32_t x = 0; x < cx; x++)
2768	{
2769	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2770	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2771	((uValue >> 5) & 0x3f) << 2,
2772	((uValue >> 11) & 0x1f) << 3, 0);
2773	}
2774	pbSrc += cbSrcXorLine;
2775	}
2776	break;
2777	case 24:
2778	for (uint32_t y = 0; y < cy; y++)
2779	{
2780	for (uint32_t x = 0; x < cx; x++)
2781	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2782	pbSrc += cbSrcXorLine;
2783	}
2784	break;
2785	case 32:
2786	for (uint32_t y = 0; y < cy; y++)
2787	{
2788	for (uint32_t x = 0; x < cx; x++)
2789	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2790	pbSrc += cbSrcXorLine;
2791	}
2792	break;
2793	default:
2794	RTMemFree(pbCopy);
2795	AssertFailedReturnVoid();
2796	}
2797
2798	/*
2799	* Pass it to the frontend/whatever.
2800	*/
2801	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2802	}
2803
2804
2805	/**
2806	* Worker for vmsvgaR3FifoThread that handles an external command.
2807	*
2808	* @param pThis VGA device instance data.
2809	*/
2810	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2811	{
2812	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2813	switch (pThis->svga.u8FIFOExtCommand)
2814	{
2815	case VMSVGA_FIFO_EXTCMD_RESET:
2816	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2817	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2818	# ifdef VBOX_WITH_VMSVGA3D
2819	if (pThis->svga.f3DEnabled)
2820	{
2821	/* The 3d subsystem must be reset from the fifo thread. */
2822	vmsvga3dReset(pThis);
2823	}
2824	# endif
2825	break;
2826
2827	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2828	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2829	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2830	# ifdef VBOX_WITH_VMSVGA3D
2831	if (pThis->svga.f3DEnabled)
2832	{
2833	/* The 3d subsystem must be shut down from the fifo thread. */
2834	vmsvga3dTerminate(pThis);
2835	}
2836	# endif
2837	break;
2838
2839	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2840	{
2841	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2842	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2843	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2844	vmsvgaSaveExecFifo(pThis, pSSM);
2845	# ifdef VBOX_WITH_VMSVGA3D
2846	vmsvga3dSaveExec(pThis, pSSM);
2847	# endif
2848	break;
2849	}
2850
2851	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2852	{
2853	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2854	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2855	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2856	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2857	# ifdef VBOX_WITH_VMSVGA3D
2858	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2859	# endif
2860	break;
2861	}
2862
2863	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2864	{
2865	# ifdef VBOX_WITH_VMSVGA3D
2866	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2867	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2868	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2869	# endif
2870	break;
2871	}
2872
2873
2874	default:
2875	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2876	break;
2877	}
2878
2879	/*
2880	* Signal the end of the external command.
2881	*/
2882	pThis->svga.pvFIFOExtCmdParam = NULL;
2883	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2884	ASMMemoryFence(); /* paranoia^2 */
2885	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2886	AssertLogRelRC(rc);
2887	}
2888
2889	/**
2890	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2891	* doing a job on the FIFO thread (even when it's officially suspended).
2892	*
2893	* @returns VBox status code (fully asserted).
2894	* @param pThis VGA device instance data.
2895	* @param uExtCmd The command to execute on the FIFO thread.
2896	* @param pvParam Pointer to command parameters.
2897	* @param cMsWait The time to wait for the command, given in
2898	* milliseconds.
2899	*/
2900	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2901	{
2902	Assert(cMsWait >= RT_MS_1SEC * 5);
2903	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2904	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2905
2906	int rc;
2907	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2908	PDMTHREADSTATE enmState = pThread->enmState;
2909	if (enmState == PDMTHREADSTATE_SUSPENDED)
2910	{
2911	/*
2912	* The thread is suspended, we have to temporarily wake it up so it can
2913	* perform the task.
2914	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2915	*/
2916	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2917	/* Post the request. */
2918	pThis->svga.fFifoExtCommandWakeup = true;
2919	pThis->svga.pvFIFOExtCmdParam = pvParam;
2920	pThis->svga.u8FIFOExtCommand = uExtCmd;
2921	ASMMemoryFence(); /* paranoia^3 */
2922
2923	/* Resume the thread. */
2924	rc = PDMR3ThreadResume(pThread);
2925	AssertLogRelRC(rc);
2926	if (RT_SUCCESS(rc))
2927	{
2928	/* Wait. Take care in case the semaphore was already posted (same as below). */
2929	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2930	if ( rc == VINF_SUCCESS
2931	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2932	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2933	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2934	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2935
2936	/* suspend the thread */
2937	pThis->svga.fFifoExtCommandWakeup = false;
2938	int rc2 = PDMR3ThreadSuspend(pThread);
2939	AssertLogRelRC(rc2);
2940	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2941	rc = rc2;
2942	}
2943	pThis->svga.fFifoExtCommandWakeup = false;
2944	pThis->svga.pvFIFOExtCmdParam = NULL;
2945	}
2946	else if (enmState == PDMTHREADSTATE_RUNNING)
2947	{
2948	/*
2949	* The thread is running, should only happen during reset and vmsvga3dsfc.
2950	* We ASSUME not racing code here, both wrt thread state and ext commands.
2951	*/
2952	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2953	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2954
2955	/* Post the request. */
2956	pThis->svga.pvFIFOExtCmdParam = pvParam;
2957	pThis->svga.u8FIFOExtCommand = uExtCmd;
2958	ASMMemoryFence(); /* paranoia^2 */
2959	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2960	AssertLogRelRC(rc);
2961
2962	/* Wait. Take care in case the semaphore was already posted (same as above). */
2963	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2964	if ( rc == VINF_SUCCESS
2965	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2966	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2967	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2968	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2969
2970	pThis->svga.pvFIFOExtCmdParam = NULL;
2971	}
2972	else
2973	{
2974	/*
2975	* Something is wrong with the thread!
2976	*/
2977	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2978	rc = VERR_INVALID_STATE;
2979	}
2980	return rc;
2981	}
2982
2983
2984	/**
2985	* Marks the FIFO non-busy, notifying any waiting EMTs.
2986	*
2987	* @param pThis The VGA state.
2988	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2989	* @param offFifoMin The start byte offset of the command FIFO.
2990	*/
2991	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2992	{
2993	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2994	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2995	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2996
2997	/* Wake up any waiting EMTs. */
2998	if (pSVGAState->cBusyDelayedEmts > 0)
2999	{
3000	#ifdef VMSVGA_USE_EMT_HALT_CODE
3001	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3002	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3003	if (idCpu != NIL_VMCPUID)
3004	{
3005	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3006	while (idCpu-- > 0)
3007	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3008	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3009	}
3010	#else
3011	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3012	AssertRC(rc2);
3013	#endif
3014	}
3015	}
3016
3017	/**
3018	* Reads (more) payload into the command buffer.
3019	*
3020	* @returns pbBounceBuf on success
3021	* @retval (void *)1 if the thread was requested to stop.
3022	* @retval NULL on FIFO error.
3023	*
3024	* @param cbPayloadReq The number of bytes of payload requested.
3025	* @param pFIFO The FIFO.
3026	* @param offCurrentCmd The FIFO byte offset of the current command.
3027	* @param offFifoMin The start byte offset of the command FIFO.
3028	* @param offFifoMax The end byte offset of the command FIFO.
3029	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3030	* always sufficient size.
3031	* @param pcbAlreadyRead How much payload we've already read into the bounce
3032	* buffer. (We will NEVER re-read anything.)
3033	* @param pThread The calling PDM thread handle.
3034	* @param pThis The VGA state.
3035	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3036	* statistics collection.
3037	*/
3038	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3039	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3040	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3041	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3042	{
3043	Assert(pbBounceBuf);
3044	Assert(pcbAlreadyRead);
3045	Assert(offFifoMin < offFifoMax);
3046	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3047	Assert(offFifoMax <= pThis->svga.cbFIFO);
3048
3049	/*
3050	* Check if the requested payload size has already been satisfied .
3051	* .
3052	* When called to read more, the caller is responsible for making sure the .
3053	* new command size (cbRequsted) never is smaller than what has already .
3054	* been read.
3055	*/
3056	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3057	if (cbPayloadReq <= cbAlreadyRead)
3058	{
3059	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3060	return pbBounceBuf;
3061	}
3062
3063	/*
3064	* Commands bigger than the fifo buffer are invalid.
3065	*/
3066	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3067	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3068	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3069	NULL);
3070
3071	/*
3072	* Move offCurrentCmd past the command dword.
3073	*/
3074	offCurrentCmd += sizeof(uint32_t);
3075	if (offCurrentCmd >= offFifoMax)
3076	offCurrentCmd = offFifoMin;
3077
3078	/*
3079	* Do we have sufficient payload data available already?
3080	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3081	*/
3082	uint32_t cbAfter, cbBefore;
3083	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3084	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3085	if (offNextCmd >= offCurrentCmd)
3086	{
3087	if (RT_LIKELY(offNextCmd < offFifoMax))
3088	cbAfter = offNextCmd - offCurrentCmd;
3089	else
3090	{
3091	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3092	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3093	offNextCmd, offFifoMin, offFifoMax));
3094	cbAfter = offFifoMax - offCurrentCmd;
3095	}
3096	cbBefore = 0;
3097	}
3098	else
3099	{
3100	cbAfter = offFifoMax - offCurrentCmd;
3101	if (offNextCmd >= offFifoMin)
3102	cbBefore = offNextCmd - offFifoMin;
3103	else
3104	{
3105	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3106	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3107	offNextCmd, offFifoMin, offFifoMax));
3108	cbBefore = 0;
3109	}
3110	}
3111	if (cbAfter + cbBefore < cbPayloadReq)
3112	{
3113	/*
3114	* Insufficient, must wait for it to arrive.
3115	*/
3116	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3117	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3118	for (uint32_t i = 0;; i++)
3119	{
3120	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3121	{
3122	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3123	return (void *)(uintptr_t)1;
3124	}
3125	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3126	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3127
3128	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3129
3130	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3131	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3132	if (offNextCmd >= offCurrentCmd)
3133	{
3134	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3135	cbBefore = 0;
3136	}
3137	else
3138	{
3139	cbAfter = offFifoMax - offCurrentCmd;
3140	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3141	}
3142
3143	if (cbAfter + cbBefore >= cbPayloadReq)
3144	break;
3145	}
3146	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3147	}
3148
3149	/*
3150	* Copy out the memory and update what pcbAlreadyRead points to.
3151	*/
3152	if (cbAfter >= cbPayloadReq)
3153	memcpy(pbBounceBuf + cbAlreadyRead,
3154	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3155	cbPayloadReq - cbAlreadyRead);
3156	else
3157	{
3158	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3159	if (cbAlreadyRead < cbAfter)
3160	{
3161	memcpy(pbBounceBuf + cbAlreadyRead,
3162	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3163	cbAfter - cbAlreadyRead);
3164	cbAlreadyRead = cbAfter;
3165	}
3166	memcpy(pbBounceBuf + cbAlreadyRead,
3167	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3168	cbPayloadReq - cbAlreadyRead);
3169	}
3170	*pcbAlreadyRead = cbPayloadReq;
3171	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3172	return pbBounceBuf;
3173	}
3174
3175	/* The async FIFO handling thread. */
3176	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3177	{
3178	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3179	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3180	int rc;
3181
3182	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3183	return VINF_SUCCESS;
3184
3185	/*
3186	* Special mode where we only execute an external command and the go back
3187	* to being suspended. Currently, all ext cmds ends up here, with the reset
3188	* one also being eligble for runtime execution further down as well.
3189	*/
3190	if (pThis->svga.fFifoExtCommandWakeup)
3191	{
3192	vmsvgaR3FifoHandleExtCmd(pThis);
3193	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3194	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3195	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3196	else
3197	vmsvgaR3FifoHandleExtCmd(pThis);
3198	return VINF_SUCCESS;
3199	}
3200
3201
3202	/*
3203	* Signal the semaphore to make sure we don't wait for 250ms after a
3204	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3205	*/
3206	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3207
3208	/*
3209	* Allocate a bounce buffer for command we get from the FIFO.
3210	* (All code must return via the end of the function to free this buffer.)
3211	*/
3212	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3213	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3214
3215	/*
3216	* Polling/sleep interval config.
3217	*
3218	* We wait for an a short interval if the guest has recently given us work
3219	* to do, but the interval increases the longer we're kept idle. With the
3220	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3221	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3222	* 16 seconds.
3223	*/
3224	RTMSINTERVAL const cMsMinSleep = 16;
3225	RTMSINTERVAL const cMsIncSleep = 2;
3226	RTMSINTERVAL const cMsMaxSleep = 250;
3227	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3228
3229	/*
3230	* The FIFO loop.
3231	*/
3232	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3233	bool fBadOrDisabledFifo = false;
3234	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3235	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3236	{
3237	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3238	/*
3239	* Should service the run loop every so often.
3240	*/
3241	if (pThis->svga.f3DEnabled)
3242	vmsvga3dCocoaServiceRunLoop();
3243	# endif
3244
3245	/*
3246	* Unless there's already work pending, go to sleep for a short while.
3247	* (See polling/sleep interval config above.)
3248	*/
3249	if ( fBadOrDisabledFifo
3250	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3251	{
3252	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3253	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3254	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3255	{
3256	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3257	break;
3258	}
3259	}
3260	else
3261	rc = VINF_SUCCESS;
3262	fBadOrDisabledFifo = false;
3263	if (rc == VERR_TIMEOUT)
3264	{
3265	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3266	{
3267	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3268	continue;
3269	}
3270	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3271
3272	Log(("vmsvgaFIFOLoop: timeout\n"));
3273	}
3274	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3275	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3276	cMsSleep = cMsMinSleep;
3277
3278	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3279	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3280	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3281
3282	/*
3283	* Handle external commands (currently only reset).
3284	*/
3285	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3286	{
3287	vmsvgaR3FifoHandleExtCmd(pThis);
3288	continue;
3289	}
3290
3291	/*
3292	* The device must be enabled and configured.
3293	*/
3294	if ( !pThis->svga.fEnabled
3295	\|\| !pThis->svga.fConfigured)
3296	{
3297	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3298	fBadOrDisabledFifo = true;
3299	continue;
3300	}
3301
3302	/*
3303	* Get and check the min/max values. We ASSUME that they will remain
3304	* unchanged while we process requests. A further ASSUMPTION is that
3305	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3306	* we don't read it back while in the loop.
3307	*/
3308	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3309	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3310	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3311	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3312	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3313	\|\| offFifoMax <= offFifoMin
3314	\|\| offFifoMax > pThis->svga.cbFIFO
3315	\|\| (offFifoMax & 3) != 0
3316	\|\| (offFifoMin & 3) != 0
3317	\|\| offCurrentCmd < offFifoMin
3318	\|\| offCurrentCmd > offFifoMax))
3319	{
3320	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3321	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3322	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3323	fBadOrDisabledFifo = true;
3324	continue;
3325	}
3326	RT_UNTRUSTED_VALIDATED_FENCE();
3327	if (RT_UNLIKELY(offCurrentCmd & 3))
3328	{
3329	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3330	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3331	offCurrentCmd = ~UINT32_C(3);
3332	}
3333
3334	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3335	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3336	*
3337	* Will break out of the switch on failure.
3338	* Will restart and quit the loop if the thread was requested to stop.
3339	*
3340	* @param a_PtrVar Request variable pointer.
3341	* @param a_Type Request typedef (not pointer) for casting.
3342	* @param a_cbPayloadReq How much payload to fetch.
3343	* @remarks Accesses a bunch of variables in the current scope!
3344	*/
3345	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3346	if (1) { \
3347	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3348	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3349	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3350	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3351	} else do {} while (0)
3352	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3353	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3354	* buffer after figuring out the actual command size.
3355	*
3356	* Will break out of the switch on failure.
3357	*
3358	* @param a_PtrVar Request variable pointer.
3359	* @param a_Type Request typedef (not pointer) for casting.
3360	* @param a_cbPayloadReq How much payload to fetch.
3361	* @remarks Accesses a bunch of variables in the current scope!
3362	*/
3363	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3364	if (1) { \
3365	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3366	} else do {} while (0)
3367
3368	/*
3369	* Mark the FIFO as busy.
3370	*/
3371	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3372	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3373	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3374
3375	/*
3376	* Execute all queued FIFO commands.
3377	* Quit if pending external command or changes in the thread state.
3378	*/
3379	bool fDone = false;
3380	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3381	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3382	{
3383	uint32_t cbPayload = 0;
3384	uint32_t u32IrqStatus = 0;
3385
3386	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3387
3388	/* First check any pending actions. */
3389	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3390	{
3391	vmsvgaChangeMode(pThis);
3392	# ifdef VBOX_WITH_VMSVGA3D
3393	if (pThis->svga.p3dState != NULL)
3394	vmsvga3dChangeMode(pThis);
3395	# endif
3396	}
3397
3398	/* Check for pending external commands (reset). */
3399	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3400	break;
3401
3402	/*
3403	* Process the command.
3404	*/
3405	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3406	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3407	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3408	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3409	switch (enmCmdId)
3410	{
3411	case SVGA_CMD_INVALID_CMD:
3412	/* Nothing to do. */
3413	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3414	break;
3415
3416	case SVGA_CMD_FENCE:
3417	{
3418	SVGAFifoCmdFence *pCmdFence;
3419	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3420	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3421	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3422	{
3423	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3424	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3425
3426	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3427	{
3428	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3429	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3430	}
3431	else
3432	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3433	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3434	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3435	{
3436	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3437	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3438	}
3439	}
3440	else
3441	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3442	break;
3443	}
3444	case SVGA_CMD_UPDATE:
3445	case SVGA_CMD_UPDATE_VERBOSE:
3446	{
3447	SVGAFifoCmdUpdate *pUpdate;
3448	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3449	if (enmCmdId == SVGA_CMD_UPDATE)
3450	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3451	else
3452	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3453	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3454	/** @todo Multiple screens? */
3455	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3456	AssertBreak(pScreen);
3457	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3458	break;
3459	}
3460
3461	case SVGA_CMD_DEFINE_CURSOR:
3462	{
3463	/* Followed by bitmap data. */
3464	SVGAFifoCmdDefineCursor *pCursor;
3465	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3466	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3467
3468	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3469	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3470	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3471	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3472	AssertBreak(pCursor->andMaskDepth <= 32);
3473	AssertBreak(pCursor->xorMaskDepth <= 32);
3474	RT_UNTRUSTED_VALIDATED_FENCE();
3475
3476	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3477	uint32_t cbAndMask = cbAndLine * pCursor->height;
3478	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3479	uint32_t cbXorMask = cbXorLine * pCursor->height;
3480	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3481
3482	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3483	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3484	break;
3485	}
3486
3487	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3488	{
3489	/* Followed by bitmap data. */
3490	uint32_t cbCursorShape, cbAndMask;
3491	uint8_t *pCursorCopy;
3492	uint32_t cbCmd;
3493
3494	SVGAFifoCmdDefineAlphaCursor *pCursor;
3495	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3496	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3497
3498	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3499
3500	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3501	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3502	RT_UNTRUSTED_VALIDATED_FENCE();
3503
3504	/* Refetch the bitmap data as well. */
3505	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3506	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3507	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3508
3509	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3510	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3511	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3512	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3513
3514	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3515	AssertBreak(pCursorCopy);
3516
3517	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3518	memset(pCursorCopy, 0xff, cbAndMask);
3519	/* Colour data */
3520	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3521
3522	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3523	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3524	break;
3525	}
3526
3527	case SVGA_CMD_ESCAPE:
3528	{
3529	/* Followed by nsize bytes of data. */
3530	SVGAFifoCmdEscape *pEscape;
3531	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3532	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3533
3534	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3535	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3536	RT_UNTRUSTED_VALIDATED_FENCE();
3537	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3538	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3539
3540	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3541	{
3542	AssertBreak(pEscape->size >= sizeof(uint32_t));
3543	RT_UNTRUSTED_VALIDATED_FENCE();
3544	uint32_t cmd = (uint32_t )(pEscape + 1);
3545	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3546
3547	switch (cmd)
3548	{
3549	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3550	{
3551	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3552	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3553	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3554
3555	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3556	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3557	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3558
3559	RT_NOREF_PV(pVideoCmd);
3560	break;
3561
3562	}
3563
3564	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3565	{
3566	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3567	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3568	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3569	RT_NOREF_PV(pVideoCmd);
3570	break;
3571	}
3572
3573	default:
3574	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3575	break;
3576	}
3577	}
3578	else
3579	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3580
3581	break;
3582	}
3583	# ifdef VBOX_WITH_VMSVGA3D
3584	case SVGA_CMD_DEFINE_GMR2:
3585	{
3586	SVGAFifoCmdDefineGMR2 *pCmd;
3587	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3588	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3589	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3590
3591	/* Validate current GMR id. */
3592	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3593	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3594	RT_UNTRUSTED_VALIDATED_FENCE();
3595
3596	if (!pCmd->numPages)
3597	{
3598	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3599	vmsvgaGMRFree(pThis, pCmd->gmrId);
3600	}
3601	else
3602	{
3603	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3604	if (pGMR->cMaxPages)
3605	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3606
3607	/* Not sure if we should always free the descriptor, but for simplicity
3608	we do so if the new size is smaller than the current. */
3609	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3610	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3611	vmsvgaGMRFree(pThis, pCmd->gmrId);
3612
3613	pGMR->cMaxPages = pCmd->numPages;
3614	/* The rest is done by the REMAP_GMR2 command. */
3615	}
3616	break;
3617	}
3618
3619	case SVGA_CMD_REMAP_GMR2:
3620	{
3621	/* Followed by page descriptors or guest ptr. */
3622	SVGAFifoCmdRemapGMR2 *pCmd;
3623	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3624	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3625
3626	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3627	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3628	RT_UNTRUSTED_VALIDATED_FENCE();
3629
3630	/* Calculate the size of what comes after next and fetch it. */
3631	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3632	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3633	cbCmd += sizeof(SVGAGuestPtr);
3634	else
3635	{
3636	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3637	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3638	{
3639	cbCmd += cbPageDesc;
3640	pCmd->numPages = 1;
3641	}
3642	else
3643	{
3644	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3645	cbCmd += cbPageDesc * pCmd->numPages;
3646	}
3647	}
3648	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3649
3650	/* Validate current GMR id and size. */
3651	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3652	RT_UNTRUSTED_VALIDATED_FENCE();
3653	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3654	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3655	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3656	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3657
3658	if (pCmd->numPages == 0)
3659	break;
3660
3661	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3662	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3663
3664	/*
3665	* We flatten the existing descriptors into a page array, overwrite the
3666	* pages specified in this command and then recompress the descriptor.
3667	*/
3668	/** @todo Optimize the GMR remap algorithm! */
3669
3670	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3671	uint64_t *paNewPage64 = NULL;
3672	if (pGMR->paDesc)
3673	{
3674	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3675
3676	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3677	AssertBreak(paNewPage64);
3678
3679	uint32_t idxPage = 0;
3680	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3681	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3682	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3683	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3684	RT_UNTRUSTED_VALIDATED_FENCE();
3685	}
3686
3687	/* Free the old GMR if present. */
3688	if (pGMR->paDesc)
3689	RTMemFree(pGMR->paDesc);
3690
3691	/* Allocate the maximum amount possible (everything non-continuous) */
3692	PVMSVGAGMRDESCRIPTOR paDescs;
3693	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3694	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3695
3696	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3697	{
3698	/** @todo */
3699	AssertFailed();
3700	pGMR->numDescriptors = 0;
3701	}
3702	else
3703	{
3704	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3705	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3706	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3707
3708	if (paNewPage64)
3709	{
3710	/* Overwrite the old page array with the new page values. */
3711	if (fGCPhys64)
3712	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3713	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3714	else
3715	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3716	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3717
3718	/* Use the updated page array instead of the command data. */
3719	fGCPhys64 = true;
3720	paPages64 = paNewPage64;
3721	pCmd->numPages = cNewTotalPages;
3722	}
3723
3724	/* The first page. */
3725	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3726	* applied to paNewPage64. */
3727	RTGCPHYS GCPhys;
3728	if (fGCPhys64)
3729	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3730	else
3731	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3732	paDescs[0].GCPhys = GCPhys;
3733	paDescs[0].numPages = 1;
3734
3735	/* Subsequent pages. */
3736	uint32_t iDescriptor = 0;
3737	for (uint32_t i = 1; i < pCmd->numPages; i++)
3738	{
3739	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3740	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3741	else
3742	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3743
3744	/* Continuous physical memory? */
3745	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3746	{
3747	Assert(paDescs[iDescriptor].numPages);
3748	paDescs[iDescriptor].numPages++;
3749	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3750	}
3751	else
3752	{
3753	iDescriptor++;
3754	paDescs[iDescriptor].GCPhys = GCPhys;
3755	paDescs[iDescriptor].numPages = 1;
3756	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3757	}
3758	}
3759
3760	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3761	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3762	pGMR->numDescriptors = iDescriptor + 1;
3763	}
3764
3765	if (paNewPage64)
3766	RTMemFree(paNewPage64);
3767
3768	# ifdef DEBUG_GMR_ACCESS
3769	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3770	# endif
3771	break;
3772	}
3773	# endif // VBOX_WITH_VMSVGA3D
3774	case SVGA_CMD_DEFINE_SCREEN:
3775	{
3776	/* The size of this command is specified by the guest and depends on capabilities. */
3777	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
3778
3779	SVGAFifoCmdDefineScreen *pCmd;
3780	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3781	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
3782	RT_UNTRUSTED_VALIDATED_FENCE();
3783
3784	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
3785	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3786	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3787
3788	LogRelFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
3789	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
3790	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
3791
3792	AssertBreak(pCmd->screen.id < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3793
3794	uint32_t const uWidth = pCmd->screen.size.width;
3795	AssertBreak(0 < uWidth && uWidth <= pThis->svga.u32MaxWidth);
3796
3797	uint32_t const uHeight = pCmd->screen.size.height;
3798	AssertBreak(0 < uHeight && uHeight <= pThis->svga.u32MaxHeight);
3799
3800	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
3801	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
3802	AssertBreak(0 < cbWidth && cbWidth <= cbPitch);
3803
3804	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
3805	AssertBreak(uScreenOffset < pThis->vram_size);
3806
3807	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
3808	AssertBreak(uHeight <= cbVram / cbPitch);
3809	RT_UNTRUSTED_VALIDATED_FENCE();
3810
3811	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screen.id];
3812	pScreen->fDefined = true;
3813	pScreen->fModified = true;
3814	pScreen->fuScreen = pCmd->screen.flags;
3815	pScreen->idScreen = pCmd->screen.id;
3816	pScreen->xOrigin = pCmd->screen.root.x;
3817	pScreen->yOrigin = pCmd->screen.root.y;
3818	pScreen->cWidth = uWidth;
3819	pScreen->cHeight = uHeight;
3820	pScreen->offVRAM = uScreenOffset;
3821	pScreen->cbPitch = cbPitch;
3822	pScreen->cBpp = 32;
3823
3824	pThis->svga.fGFBRegisters = false;
3825	vmsvgaChangeMode(pThis);
3826	break;
3827	}
3828
3829	case SVGA_CMD_DESTROY_SCREEN:
3830	{
3831	SVGAFifoCmdDestroyScreen *pCmd;
3832	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3833	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3834
3835	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3836	AssertBreak(pCmd->screenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3837	RT_UNTRUSTED_VALIDATED_FENCE();
3838
3839	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screenId];
3840	pScreen->fModified = true;
3841	pScreen->fDefined = false;
3842
3843	vmsvgaChangeMode(pThis);
3844	break;
3845	}
3846	# ifdef VBOX_WITH_VMSVGA3D
3847	case SVGA_CMD_DEFINE_GMRFB:
3848	{
3849	SVGAFifoCmdDefineGMRFB *pCmd;
3850	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3851	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3852
3853	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3854	pSVGAState->GMRFB.ptr = pCmd->ptr;
3855	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3856	pSVGAState->GMRFB.format = pCmd->format;
3857	break;
3858	}
3859
3860	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3861	{
3862	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3863	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3864	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3865
3866	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
3867	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3868
3869	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3870	RT_UNTRUSTED_VALIDATED_FENCE();
3871
3872	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
3873	AssertBreak(pScreen);
3874
3875	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3876	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3877
3878	/* Clip destRect to the screen dimensions. */
3879	SVGASignedRect screenRect;
3880	screenRect.left = 0;
3881	screenRect.top = 0;
3882	screenRect.right = pScreen->cWidth;
3883	screenRect.bottom = pScreen->cHeight;
3884	SVGASignedRect clipRect = pCmd->destRect;
3885	vmsvgaClipRect(&screenRect, &clipRect);
3886	RT_UNTRUSTED_VALIDATED_FENCE();
3887
3888	uint32_t const width = clipRect.right - clipRect.left;
3889	uint32_t const height = clipRect.bottom - clipRect.top;
3890
3891	if ( width == 0
3892	\|\| height == 0)
3893	break; /* Nothing to do. */
3894
3895	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
3896	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
3897
3898	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3899	* Prepare parameters for vmsvgaGMRTransfer.
3900	*/
3901	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3902
3903	/* Destination: host buffer which describes the screen 0 VRAM.
3904	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3905	*/
3906	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3907	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3908	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3909	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3910	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3911	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3912	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3913	+ cbScanline * clipRect.top;
3914	int32_t const cbHstPitch = cbScanline;
3915
3916	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
3917	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
3918	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
3919	+ pSVGAState->GMRFB.bytesPerLine * srcy;
3920	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
3921
3922	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
3923	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
3924	gstPtr, offGst, cbGstPitch,
3925	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
3926	AssertRC(rc);
3927	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
3928	break;
3929	}
3930
3931	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3932	{
3933	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3934	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3935	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3936
3937	/* Note! This can fetch 3d render results as well!! */
3938	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
3939	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3940
3941	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3942	RT_UNTRUSTED_VALIDATED_FENCE();
3943
3944	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
3945	AssertBreak(pScreen);
3946
3947	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
3948	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3949
3950	/* Clip destRect to the screen dimensions. */
3951	SVGASignedRect screenRect;
3952	screenRect.left = 0;
3953	screenRect.top = 0;
3954	screenRect.right = pScreen->cWidth;
3955	screenRect.bottom = pScreen->cHeight;
3956	SVGASignedRect clipRect = pCmd->srcRect;
3957	vmsvgaClipRect(&screenRect, &clipRect);
3958	RT_UNTRUSTED_VALIDATED_FENCE();
3959
3960	uint32_t const width = clipRect.right - clipRect.left;
3961	uint32_t const height = clipRect.bottom - clipRect.top;
3962
3963	if ( width == 0
3964	\|\| height == 0)
3965	break; /* Nothing to do. */
3966
3967	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
3968	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
3969
3970	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3971	* Prepare parameters for vmsvgaGMRTransfer.
3972	*/
3973	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3974
3975	/* Source: host buffer which describes the screen 0 VRAM.
3976	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3977	*/
3978	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3979	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3980	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3981	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3982	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3983	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3984	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3985	+ cbScanline * clipRect.top;
3986	int32_t const cbHstPitch = cbScanline;
3987
3988	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
3989	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
3990	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
3991	+ pSVGAState->GMRFB.bytesPerLine * dsty;
3992	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
3993
3994	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
3995	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
3996	gstPtr, offGst, cbGstPitch,
3997	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
3998	AssertRC(rc);
3999	break;
4000	}
4001	# endif // VBOX_WITH_VMSVGA3D
4002	case SVGA_CMD_ANNOTATION_FILL:
4003	{
4004	SVGAFifoCmdAnnotationFill *pCmd;
4005	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4006	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4007
4008	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4009	pSVGAState->colorAnnotation = pCmd->color;
4010	break;
4011	}
4012
4013	case SVGA_CMD_ANNOTATION_COPY:
4014	{
4015	SVGAFifoCmdAnnotationCopy *pCmd;
4016	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4017	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4018
4019	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4020	AssertFailed();
4021	break;
4022	}
4023
4024	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4025
4026	default:
4027	# ifdef VBOX_WITH_VMSVGA3D
4028	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4029	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4030	{
4031	RT_UNTRUSTED_VALIDATED_FENCE();
4032
4033	/* All 3d commands start with a common header, which defines the size of the command. */
4034	SVGA3dCmdHeader *pHdr;
4035	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4036	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4037	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4038	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4039
4040	/**
4041	* Check that the 3D command has at least a_cbMin of payload bytes after the
4042	* header. Will break out of the switch if it doesn't.
4043	*/
4044	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4045	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4046	RT_UNTRUSTED_VALIDATED_FENCE(); \
4047	} while (0)
4048	switch ((int)enmCmdId)
4049	{
4050	case SVGA_3D_CMD_SURFACE_DEFINE:
4051	{
4052	uint32_t cMipLevels;
4053	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4054	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4055	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4056
4057	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4058	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4059	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4060	# ifdef DEBUG_GMR_ACCESS
4061	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4062	# endif
4063	break;
4064	}
4065
4066	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4067	{
4068	uint32_t cMipLevels;
4069	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4070	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4071	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4072
4073	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4074	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4075	pCmd->multisampleCount, pCmd->autogenFilter,
4076	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4077	break;
4078	}
4079
4080	case SVGA_3D_CMD_SURFACE_DESTROY:
4081	{
4082	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4083	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4084	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4085	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4086	break;
4087	}
4088
4089	case SVGA_3D_CMD_SURFACE_COPY:
4090	{
4091	uint32_t cCopyBoxes;
4092	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4093	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4094	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4095
4096	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4097	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4098	break;
4099	}
4100
4101	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4102	{
4103	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4104	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4105	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4106
4107	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4108	break;
4109	}
4110
4111	case SVGA_3D_CMD_SURFACE_DMA:
4112	{
4113	uint32_t cCopyBoxes;
4114	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4115	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4116	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4117
4118	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4119	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4120	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4121	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4122	break;
4123	}
4124
4125	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4126	{
4127	uint32_t cRects;
4128	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4129	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4130	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4131
4132	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4133	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4134	break;
4135	}
4136
4137	case SVGA_3D_CMD_CONTEXT_DEFINE:
4138	{
4139	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4140	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4141	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4142
4143	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4144	break;
4145	}
4146
4147	case SVGA_3D_CMD_CONTEXT_DESTROY:
4148	{
4149	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4150	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4151	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4152
4153	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4154	break;
4155	}
4156
4157	case SVGA_3D_CMD_SETTRANSFORM:
4158	{
4159	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4160	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4161	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4162
4163	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4164	break;
4165	}
4166
4167	case SVGA_3D_CMD_SETZRANGE:
4168	{
4169	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4170	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4171	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4172
4173	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4174	break;
4175	}
4176
4177	case SVGA_3D_CMD_SETRENDERSTATE:
4178	{
4179	uint32_t cRenderStates;
4180	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4181	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4182	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4183
4184	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4185	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4186	break;
4187	}
4188
4189	case SVGA_3D_CMD_SETRENDERTARGET:
4190	{
4191	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4192	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4193	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4194
4195	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4196	break;
4197	}
4198
4199	case SVGA_3D_CMD_SETTEXTURESTATE:
4200	{
4201	uint32_t cTextureStates;
4202	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4203	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4204	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4205
4206	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4207	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4208	break;
4209	}
4210
4211	case SVGA_3D_CMD_SETMATERIAL:
4212	{
4213	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4214	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4215	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4216
4217	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4218	break;
4219	}
4220
4221	case SVGA_3D_CMD_SETLIGHTDATA:
4222	{
4223	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4224	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4225	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4226
4227	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4228	break;
4229	}
4230
4231	case SVGA_3D_CMD_SETLIGHTENABLED:
4232	{
4233	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4234	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4235	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4236
4237	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4238	break;
4239	}
4240
4241	case SVGA_3D_CMD_SETVIEWPORT:
4242	{
4243	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4244	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4245	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4246
4247	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4248	break;
4249	}
4250
4251	case SVGA_3D_CMD_SETCLIPPLANE:
4252	{
4253	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4254	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4255	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4256
4257	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4258	break;
4259	}
4260
4261	case SVGA_3D_CMD_CLEAR:
4262	{
4263	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4264	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4265	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4266
4267	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4268	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4269	break;
4270	}
4271
4272	case SVGA_3D_CMD_PRESENT:
4273	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4274	{
4275	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4276	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4277	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4278	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4279	else
4280	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4281
4282	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4283
4284	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4285	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4286	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4287	break;
4288	}
4289
4290	case SVGA_3D_CMD_SHADER_DEFINE:
4291	{
4292	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4293	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4295
4296	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4297	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4298	break;
4299	}
4300
4301	case SVGA_3D_CMD_SHADER_DESTROY:
4302	{
4303	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4304	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4305	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4306
4307	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4308	break;
4309	}
4310
4311	case SVGA_3D_CMD_SET_SHADER:
4312	{
4313	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4314	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4315	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4316
4317	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4318	break;
4319	}
4320
4321	case SVGA_3D_CMD_SET_SHADER_CONST:
4322	{
4323	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4326
4327	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4328	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4329	break;
4330	}
4331
4332	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4333	{
4334	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4335	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4336	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4337
4338	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4339	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4340	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4341	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4342	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4343
4344	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4345	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4346
4347	RT_UNTRUSTED_VALIDATED_FENCE();
4348
4349	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4350	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4351	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4352
4353	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4354	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4355	pNumRange, cVertexDivisor, pVertexDivisor);
4356	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4357	break;
4358	}
4359
4360	case SVGA_3D_CMD_SETSCISSORRECT:
4361	{
4362	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4363	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4364	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4365
4366	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4367	break;
4368	}
4369
4370	case SVGA_3D_CMD_BEGIN_QUERY:
4371	{
4372	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4373	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4374	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4375
4376	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4377	break;
4378	}
4379
4380	case SVGA_3D_CMD_END_QUERY:
4381	{
4382	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4383	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4384	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4385
4386	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4387	break;
4388	}
4389
4390	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4391	{
4392	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4393	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4394	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4395
4396	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4397	break;
4398	}
4399
4400	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4401	{
4402	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4403	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4404	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4405
4406	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4407	break;
4408	}
4409
4410	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4411	/* context id + surface id? */
4412	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4413	break;
4414	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4415	/* context id + surface id? */
4416	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4417	break;
4418
4419	default:
4420	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4421	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4422	break;
4423	}
4424	}
4425	else
4426	# endif // VBOX_WITH_VMSVGA3D
4427	{
4428	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4429	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4430	}
4431	}
4432
4433	/* Go to the next slot */
4434	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4435	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4436	if (offCurrentCmd >= offFifoMax)
4437	{
4438	offCurrentCmd -= offFifoMax - offFifoMin;
4439	Assert(offCurrentCmd >= offFifoMin);
4440	Assert(offCurrentCmd < offFifoMax);
4441	}
4442	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4443	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4444
4445	/*
4446	* Raise IRQ if required. Must enter the critical section here
4447	* before making final decisions here, otherwise cubebench and
4448	* others may end up waiting forever.
4449	*/
4450	if ( u32IrqStatus
4451	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4452	{
4453	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4454	AssertRC(rc2);
4455
4456	/* FIFO progress might trigger an interrupt. */
4457	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4458	{
4459	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4460	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4461	}
4462
4463	/* Unmasked IRQ pending? */
4464	if (pThis->svga.u32IrqMask & u32IrqStatus)
4465	{
4466	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4467	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4468	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4469	}
4470
4471	PDMCritSectLeave(&pThis->CritSect);
4472	}
4473	}
4474
4475	/* If really done, clear the busy flag. */
4476	if (fDone)
4477	{
4478	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4479	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4480	}
4481	}
4482
4483	/*
4484	* Free the bounce buffer. (There are no returns above!)
4485	*/
4486	RTMemFree(pbBounceBuf);
4487
4488	return VINF_SUCCESS;
4489	}
4490
4491	/**
4492	* Free the specified GMR
4493	*
4494	* @param pThis VGA device instance data.
4495	* @param idGMR GMR id
4496	*/
4497	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4498	{
4499	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4500
4501	/* Free the old descriptor if present. */
4502	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4503	if ( pGMR->numDescriptors
4504	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4505	{
4506	# ifdef DEBUG_GMR_ACCESS
4507	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4508	# endif
4509
4510	Assert(pGMR->paDesc);
4511	RTMemFree(pGMR->paDesc);
4512	pGMR->paDesc = NULL;
4513	pGMR->numDescriptors = 0;
4514	pGMR->cbTotal = 0;
4515	pGMR->cMaxPages = 0;
4516	}
4517	Assert(!pGMR->cMaxPages);
4518	Assert(!pGMR->cbTotal);
4519	}
4520
4521	/**
4522	* Copy between a GMR and a host memory buffer.
4523	*
4524	* @returns VBox status code.
4525	* @param pThis VGA device instance data.
4526	* @param enmTransferType Transfer type (read/write)
4527	* @param pbHstBuf Host buffer pointer (valid)
4528	* @param cbHstBuf Size of host buffer (valid)
4529	* @param offHst Host buffer offset of the first scanline
4530	* @param cbHstPitch Destination buffer pitch
4531	* @param gstPtr GMR description
4532	* @param offGst Guest buffer offset of the first scanline
4533	* @param cbGstPitch Guest buffer pitch
4534	* @param cbWidth Width in bytes to copy
4535	* @param cHeight Number of scanllines to copy
4536	*/
4537	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4538	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4539	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4540	uint32_t cbWidth, uint32_t cHeight)
4541	{
4542	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4543	int rc;
4544
4545	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4546	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4547	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4548	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4549	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4550
4551	PGMR pGMR;
4552	uint32_t cbGmr; /* The GMR size in bytes. */
4553	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4554	{
4555	pGMR = NULL;
4556	cbGmr = pThis->vram_size;
4557	}
4558	else
4559	{
4560	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4561	RT_UNTRUSTED_VALIDATED_FENCE();
4562	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4563	cbGmr = pGMR->cbTotal;
4564	}
4565
4566	/*
4567	* GMR
4568	*/
4569	/* Calculate GMR offset of the data to be copied. */
4570	AssertMsgReturn(gstPtr.offset < cbGmr,
4571	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4572	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4573	VERR_INVALID_PARAMETER);
4574	RT_UNTRUSTED_VALIDATED_FENCE();
4575	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4576	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4577	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4578	VERR_INVALID_PARAMETER);
4579	RT_UNTRUSTED_VALIDATED_FENCE();
4580	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4581
4582	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4583	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4584	AssertMsgReturn(cbGmrScanline != 0,
4585	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4586	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4587	VERR_INVALID_PARAMETER);
4588	RT_UNTRUSTED_VALIDATED_FENCE();
4589	AssertMsgReturn(cbWidth <= cbGmrScanline,
4590	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4591	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4592	VERR_INVALID_PARAMETER);
4593	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4594	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4595	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4596	VERR_INVALID_PARAMETER);
4597	RT_UNTRUSTED_VALIDATED_FENCE();
4598
4599	/* How many bytes are available for the data in the GMR. */
4600	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4601
4602	/* How many scanlines would fit into the available data. */
4603	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4604	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4605	if (cbWidth <= cbGmrLastScanline)
4606	++cGmrScanlines;
4607
4608	if (cHeight > cGmrScanlines)
4609	cHeight = cGmrScanlines;
4610
4611	AssertMsgReturn(cHeight > 0,
4612	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4613	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4614	VERR_INVALID_PARAMETER);
4615	RT_UNTRUSTED_VALIDATED_FENCE();
4616
4617	/*
4618	* Host buffer.
4619	*/
4620	AssertMsgReturn(offHst < cbHstBuf,
4621	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4622	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4623	VERR_INVALID_PARAMETER);
4624
4625	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4626	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4627	AssertMsgReturn(cbHstScanline != 0,
4628	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4629	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4630	VERR_INVALID_PARAMETER);
4631	AssertMsgReturn(cbWidth <= cbHstScanline,
4632	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4633	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4634	VERR_INVALID_PARAMETER);
4635	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4636	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4637	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4638	VERR_INVALID_PARAMETER);
4639
4640	/* How many bytes are available for the data in the buffer. */
4641	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4642
4643	/* How many scanlines would fit into the available data. */
4644	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4645	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4646	if (cbWidth <= cbHstLastScanline)
4647	++cHstScanlines;
4648
4649	if (cHeight > cHstScanlines)
4650	cHeight = cHstScanlines;
4651
4652	AssertMsgReturn(cHeight > 0,
4653	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4654	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4655	VERR_INVALID_PARAMETER);
4656
4657	uint8_t *pbHst = pbHstBuf + offHst;
4658
4659	/* Shortcut for the framebuffer. */
4660	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4661	{
4662	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4663
4664	uint8_t const *pbSrc;
4665	int32_t cbSrcPitch;
4666	uint8_t *pbDst;
4667	int32_t cbDstPitch;
4668
4669	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4670	{
4671	pbSrc = pbHst;
4672	cbSrcPitch = cbHstPitch;
4673	pbDst = pbGst;
4674	cbDstPitch = cbGstPitch;
4675	}
4676	else
4677	{
4678	pbSrc = pbGst;
4679	cbSrcPitch = cbGstPitch;
4680	pbDst = pbHst;
4681	cbDstPitch = cbHstPitch;
4682	}
4683
4684	if ( cbWidth == (uint32_t)cbGstPitch
4685	&& cbGstPitch == cbHstPitch)
4686	{
4687	/* Entire scanlines, positive pitch. */
4688	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4689	}
4690	else
4691	{
4692	for (uint32_t i = 0; i < cHeight; ++i)
4693	{
4694	memcpy(pbDst, pbSrc, cbWidth);
4695
4696	pbDst += cbDstPitch;
4697	pbSrc += cbSrcPitch;
4698	}
4699	}
4700	return VINF_SUCCESS;
4701	}
4702
4703	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4704	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4705
4706	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4707	uint32_t iDesc = 0; /* Index in the descriptor array. */
4708	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4709	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4710	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4711	for (uint32_t i = 0; i < cHeight; ++i)
4712	{
4713	uint32_t cbCurrentWidth = cbWidth;
4714	uint32_t offGmrCurrent = offGmrScanline;
4715	uint8_t *pbCurrentHost = pbHstScanline;
4716
4717	/* Find the right descriptor */
4718	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4719	{
4720	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4721	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4722	++iDesc;
4723	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4724	}
4725
4726	while (cbCurrentWidth)
4727	{
4728	uint32_t cbToCopy;
4729
4730	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4731	{
4732	cbToCopy = cbCurrentWidth;
4733	}
4734	else
4735	{
4736	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4737	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4738	}
4739
4740	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4741
4742	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4743
4744	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4745	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4746	else
4747	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4748	AssertRCBreak(rc);
4749
4750	cbCurrentWidth -= cbToCopy;
4751	offGmrCurrent += cbToCopy;
4752	pbCurrentHost += cbToCopy;
4753
4754	/* Go to the next descriptor if there's anything left. */
4755	if (cbCurrentWidth)
4756	{
4757	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4758	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
4759	++iDesc;
4760	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4761	}
4762	}
4763
4764	offGmrScanline += cbGstPitch;
4765	pbHstScanline += cbHstPitch;
4766	}
4767
4768	return VINF_SUCCESS;
4769	}
4770
4771	/**
4772	* Unblock the FIFO I/O thread so it can respond to a state change.
4773	*
4774	* @returns VBox status code.
4775	* @param pDevIns The VGA device instance.
4776	* @param pThread The send thread.
4777	*/
4778	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4779	{
4780	RT_NOREF(pDevIns);
4781	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4782	Log(("vmsvgaFIFOLoopWakeUp\n"));
4783	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4784	}
4785
4786	/**
4787	* Enables or disables dirty page tracking for the framebuffer
4788	*
4789	* @param pThis VGA device instance data.
4790	* @param fTraces Enable/disable traces
4791	*/
4792	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4793	{
4794	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4795	&& !fTraces)
4796	{
4797	//Assert(pThis->svga.fTraces);
4798	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4799	return;
4800	}
4801
4802	pThis->svga.fTraces = fTraces;
4803	if (pThis->svga.fTraces)
4804	{
4805	unsigned cbFrameBuffer = pThis->vram_size;
4806
4807	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4808	/** @todo How this works with screens? */
4809	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4810	{
4811	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4812	Assert(pThis->svga.cbScanline);
4813	#endif
4814	/* Hardware enabled; return real framebuffer size .*/
4815	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4816	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4817	}
4818
4819	if (!pThis->svga.fVRAMTracking)
4820	{
4821	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4822	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4823	pThis->svga.fVRAMTracking = true;
4824	}
4825	}
4826	else
4827	{
4828	if (pThis->svga.fVRAMTracking)
4829	{
4830	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4831	vgaR3UnregisterVRAMHandler(pThis);
4832	pThis->svga.fVRAMTracking = false;
4833	}
4834	}
4835	}
4836
4837	/**
4838	* @callback_method_impl{FNPCIIOREGIONMAP}
4839	*/
4840	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4841	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4842	{
4843	int rc;
4844	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4845
4846	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4847	if (enmType == PCI_ADDRESS_SPACE_IO)
4848	{
4849	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4850	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4851	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4852	if (RT_FAILURE(rc))
4853	return rc;
4854	if (pThis->fR0Enabled)
4855	{
4856	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4857	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4858	if (RT_FAILURE(rc))
4859	return rc;
4860	}
4861	if (pThis->fGCEnabled)
4862	{
4863	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4864	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4865	if (RT_FAILURE(rc))
4866	return rc;
4867	}
4868
4869	pThis->svga.BasePort = GCPhysAddress;
4870	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
4871	}
4872	else
4873	{
4874	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
4875	if (GCPhysAddress != NIL_RTGCPHYS)
4876	{
4877	/*
4878	* Mapping the FIFO RAM.
4879	*/
4880	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
4881	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
4882	AssertRC(rc);
4883
4884	# ifdef DEBUG_FIFO_ACCESS
4885	if (RT_SUCCESS(rc))
4886	{
4887	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
4888	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
4889	"VMSVGA FIFO");
4890	AssertRC(rc);
4891	}
4892	# endif
4893	if (RT_SUCCESS(rc))
4894	{
4895	pThis->svga.GCPhysFIFO = GCPhysAddress;
4896	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
4897	}
4898	}
4899	else
4900	{
4901	Assert(pThis->svga.GCPhysFIFO);
4902	# ifdef DEBUG_FIFO_ACCESS
4903	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4904	AssertRC(rc);
4905	# endif
4906	pThis->svga.GCPhysFIFO = 0;
4907	}
4908
4909	}
4910	return VINF_SUCCESS;
4911	}
4912
4913	# ifdef VBOX_WITH_VMSVGA3D
4914
4915	/**
4916	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
4917	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
4918	*
4919	* @param pThis The VGA device instance data.
4920	* @param sid Either UINT32_MAX or the ID of a specific
4921	* surface. If UINT32_MAX is used, all surfaces
4922	* are processed.
4923	*/
4924	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
4925	{
4926	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
4927	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
4928	}
4929
4930
4931	/**
4932	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
4933	*/
4934	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4935	{
4936	/* There might be a specific surface ID at the start of the
4937	arguments, if not show all surfaces. */
4938	uint32_t sid = UINT32_MAX;
4939	if (pszArgs)
4940	pszArgs = RTStrStripL(pszArgs);
4941	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4942	sid = RTStrToUInt32(pszArgs);
4943
4944	/* Verbose or terse display, we default to verbose. */
4945	bool fVerbose = true;
4946	if (RTStrIStr(pszArgs, "terse"))
4947	fVerbose = false;
4948
4949	/* The size of the ascii art (x direction, y is 3/4 of x). */
4950	uint32_t cxAscii = 80;
4951	if (RTStrIStr(pszArgs, "gigantic"))
4952	cxAscii = 300;
4953	else if (RTStrIStr(pszArgs, "huge"))
4954	cxAscii = 180;
4955	else if (RTStrIStr(pszArgs, "big"))
4956	cxAscii = 132;
4957	else if (RTStrIStr(pszArgs, "normal"))
4958	cxAscii = 80;
4959	else if (RTStrIStr(pszArgs, "medium"))
4960	cxAscii = 64;
4961	else if (RTStrIStr(pszArgs, "small"))
4962	cxAscii = 48;
4963	else if (RTStrIStr(pszArgs, "tiny"))
4964	cxAscii = 24;
4965
4966	/* Y invert the image when producing the ASCII art. */
4967	bool fInvY = false;
4968	if (RTStrIStr(pszArgs, "invy"))
4969	fInvY = true;
4970
4971	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
4972	}
4973
4974
4975	/**
4976	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
4977	*/
4978	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4979	{
4980	/* pszArg = "sid[>dir]"
4981	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
4982	*/
4983	char *pszBitmapPath = NULL;
4984	uint32_t sid = UINT32_MAX;
4985	if (pszArgs)
4986	pszArgs = RTStrStripL(pszArgs);
4987	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
4988	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
4989	if ( pszBitmapPath
4990	&& *pszBitmapPath == '>')
4991	++pszBitmapPath;
4992
4993	const bool fVerbose = true;
4994	const uint32_t cxAscii = 0; /* No ASCII */
4995	const bool fInvY = false; /* Do not invert. */
4996	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
4997	}
4998
4999
5000	/**
5001	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5002	*/
5003	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5004	{
5005	/* There might be a specific surface ID at the start of the
5006	arguments, if not show all contexts. */
5007	uint32_t sid = UINT32_MAX;
5008	if (pszArgs)
5009	pszArgs = RTStrStripL(pszArgs);
5010	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5011	sid = RTStrToUInt32(pszArgs);
5012
5013	/* Verbose or terse display, we default to verbose. */
5014	bool fVerbose = true;
5015	if (RTStrIStr(pszArgs, "terse"))
5016	fVerbose = false;
5017
5018	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5019	}
5020
5021	# endif /* VBOX_WITH_VMSVGA3D */
5022
5023	/**
5024	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5025	*/
5026	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5027	{
5028	RT_NOREF(pszArgs);
5029	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5030	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5031
5032	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5033	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5034	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5035	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5036	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5037	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5038	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5039	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5040	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5041	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5042	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5043	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5044	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5045	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5046	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5047	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5048	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5049	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5050	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5051	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5052	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5053	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5054
5055	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5056	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5057	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5058	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5059
5060	# ifdef VBOX_WITH_VMSVGA3D
5061	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5062	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
5063	if (pThis->svga.u64HostWindowId != 0)
5064	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
5065	# endif
5066	}
5067
5068	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5069	*/
5070	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5071	{
5072	RT_NOREF(uPass);
5073
5074	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5075	int rc;
5076
5077	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5078	{
5079	uint32_t cScreens = 0;
5080	rc = SSMR3GetU32(pSSM, &cScreens);
5081	AssertRCReturn(rc, rc);
5082	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5083	("cScreens=%#x\n", cScreens),
5084	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5085
5086	for (uint32_t i = 0; i < cScreens; ++i)
5087	{
5088	VMSVGASCREENOBJECT screen;
5089	RT_ZERO(screen);
5090
5091	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5092	AssertLogRelRCReturn(rc, rc);
5093
5094	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5095	{
5096	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5097	*pScreen = screen;
5098	pScreen->fModified = true;
5099	}
5100	else
5101	{
5102	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5103	}
5104	}
5105	}
5106	else
5107	{
5108	/* Try to setup at least the first screen. */
5109	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5110	pScreen->fDefined = true;
5111	pScreen->fModified = true;
5112	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5113	pScreen->idScreen = 0;
5114	pScreen->xOrigin = 0;
5115	pScreen->yOrigin = 0;
5116	pScreen->offVRAM = pThis->svga.uScreenOffset;
5117	pScreen->cbPitch = pThis->svga.cbScanline;
5118	pScreen->cWidth = pThis->svga.uWidth;
5119	pScreen->cHeight = pThis->svga.uHeight;
5120	pScreen->cBpp = pThis->svga.uBpp;
5121	}
5122
5123	return VINF_SUCCESS;
5124	}
5125
5126	/**
5127	* @copydoc FNSSMDEVLOADEXEC
5128	*/
5129	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5130	{
5131	RT_NOREF(uPass);
5132	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5133	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5134	int rc;
5135
5136	/* Load our part of the VGAState */
5137	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5138	AssertRCReturn(rc, rc);
5139
5140	/* Load the VGA framebuffer. */
5141	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5142	uint32_t cbVgaFramebuffer = _32K;
5143	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5144	{
5145	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5146	AssertRCReturn(rc, rc);
5147	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5148	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5149	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5150	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5151	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5152	}
5153	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5154	AssertRCReturn(rc, rc);
5155	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5156	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5157	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5158	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5159
5160	/* Load the VMSVGA state. */
5161	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5162	AssertRCReturn(rc, rc);
5163
5164	/* Load the active cursor bitmaps. */
5165	if (pSVGAState->Cursor.fActive)
5166	{
5167	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5168	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5169
5170	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5171	AssertRCReturn(rc, rc);
5172	}
5173
5174	/* Load the GMR state. */
5175	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5176	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5177	{
5178	rc = SSMR3GetU32(pSSM, &cGMR);
5179	AssertRCReturn(rc, rc);
5180	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5181	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5182	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5183	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5184	}
5185
5186	if (pThis->svga.cGMR != cGMR)
5187	{
5188	/* Reallocate GMR array. */
5189	Assert(pSVGAState->paGMR != NULL);
5190	RTMemFree(pSVGAState->paGMR);
5191	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5192	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5193	pThis->svga.cGMR = cGMR;
5194	}
5195
5196	for (uint32_t i = 0; i < cGMR; ++i)
5197	{
5198	PGMR pGMR = &pSVGAState->paGMR[i];
5199
5200	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5201	AssertRCReturn(rc, rc);
5202
5203	if (pGMR->numDescriptors)
5204	{
5205	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5206	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5207	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5208
5209	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5210	{
5211	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5212	AssertRCReturn(rc, rc);
5213	}
5214	}
5215	}
5216
5217	# ifdef VBOX_WITH_VMSVGA3D
5218	if (pThis->svga.f3DEnabled)
5219	{
5220	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5221	vmsvga3dPowerOn(pThis);
5222	# endif
5223
5224	VMSVGA_STATE_LOAD LoadState;
5225	LoadState.pSSM = pSSM;
5226	LoadState.uVersion = uVersion;
5227	LoadState.uPass = uPass;
5228	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5229	AssertLogRelRCReturn(rc, rc);
5230	}
5231	# endif
5232
5233	return VINF_SUCCESS;
5234	}
5235
5236	/**
5237	* Reinit the video mode after the state has been loaded.
5238	*/
5239	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5240	{
5241	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5242	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5243
5244	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5245
5246	/* Set the active cursor. */
5247	if (pSVGAState->Cursor.fActive)
5248	{
5249	int rc;
5250
5251	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5252	true,
5253	true,
5254	pSVGAState->Cursor.xHotspot,
5255	pSVGAState->Cursor.yHotspot,
5256	pSVGAState->Cursor.width,
5257	pSVGAState->Cursor.height,
5258	pSVGAState->Cursor.pData);
5259	AssertRC(rc);
5260	}
5261	return VINF_SUCCESS;
5262	}
5263
5264	/**
5265	* Portion of SVGA state which must be saved in the FIFO thread.
5266	*/
5267	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5268	{
5269	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5270	int rc;
5271
5272	/* Save the screen objects. */
5273	/* Count defined screen object. */
5274	uint32_t cScreens = 0;
5275	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5276	{
5277	if (pSVGAState->aScreens[i].fDefined)
5278	++cScreens;
5279	}
5280
5281	rc = SSMR3PutU32(pSSM, cScreens);
5282	AssertLogRelRCReturn(rc, rc);
5283
5284	for (uint32_t i = 0; i < cScreens; ++i)
5285	{
5286	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5287
5288	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5289	AssertLogRelRCReturn(rc, rc);
5290	}
5291	return VINF_SUCCESS;
5292	}
5293
5294	/**
5295	* @copydoc FNSSMDEVSAVEEXEC
5296	*/
5297	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5298	{
5299	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5300	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5301	int rc;
5302
5303	/* Save our part of the VGAState */
5304	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5305	AssertLogRelRCReturn(rc, rc);
5306
5307	/* Save the framebuffer backup. */
5308	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5309	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5310	AssertLogRelRCReturn(rc, rc);
5311
5312	/* Save the VMSVGA state. */
5313	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5314	AssertLogRelRCReturn(rc, rc);
5315
5316	/* Save the active cursor bitmaps. */
5317	if (pSVGAState->Cursor.fActive)
5318	{
5319	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5320	AssertLogRelRCReturn(rc, rc);
5321	}
5322
5323	/* Save the GMR state */
5324	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5325	AssertLogRelRCReturn(rc, rc);
5326	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5327	{
5328	PGMR pGMR = &pSVGAState->paGMR[i];
5329
5330	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5331	AssertLogRelRCReturn(rc, rc);
5332
5333	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5334	{
5335	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5336	AssertLogRelRCReturn(rc, rc);
5337	}
5338	}
5339
5340	# ifdef VBOX_WITH_VMSVGA3D
5341	/*
5342	* Must save the 3d state in the FIFO thread.
5343	*/
5344	if (pThis->svga.f3DEnabled)
5345	{
5346	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5347	AssertLogRelRCReturn(rc, rc);
5348	}
5349	# endif
5350	return VINF_SUCCESS;
5351	}
5352
5353	/**
5354	* Destructor for PVMSVGAR3STATE structure.
5355	*
5356	* @param pThis The VGA instance.
5357	* @param pSVGAState Pointer to the structure. It is not deallocated.
5358	*/
5359	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5360	{
5361	#ifndef VMSVGA_USE_EMT_HALT_CODE
5362	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5363	{
5364	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5365	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5366	}
5367	#endif
5368
5369	if (pSVGAState->Cursor.fActive)
5370	{
5371	RTMemFree(pSVGAState->Cursor.pData);
5372	pSVGAState->Cursor.pData = NULL;
5373	pSVGAState->Cursor.fActive = false;
5374	}
5375
5376	if (pSVGAState->paGMR)
5377	{
5378	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5379	if (pSVGAState->paGMR[i].paDesc)
5380	RTMemFree(pSVGAState->paGMR[i].paDesc);
5381
5382	RTMemFree(pSVGAState->paGMR);
5383	pSVGAState->paGMR = NULL;
5384	}
5385	}
5386
5387	/**
5388	* Constructor for PVMSVGAR3STATE structure.
5389	*
5390	* @returns VBox status code.
5391	* @param pThis The VGA instance.
5392	* @param pSVGAState Pointer to the structure. It is already allocated.
5393	*/
5394	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5395	{
5396	int rc = VINF_SUCCESS;
5397	RT_ZERO(*pSVGAState);
5398
5399	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5400	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5401
5402	#ifndef VMSVGA_USE_EMT_HALT_CODE
5403	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5404	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5405	AssertRCReturn(rc, rc);
5406	#endif
5407
5408	return rc;
5409	}
5410
5411	/**
5412	* Resets the SVGA hardware state
5413	*
5414	* @returns VBox status code.
5415	* @param pDevIns The device instance.
5416	*/
5417	int vmsvgaReset(PPDMDEVINS pDevIns)
5418	{
5419	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5420	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5421
5422	/* Reset before init? */
5423	if (!pSVGAState)
5424	return VINF_SUCCESS;
5425
5426	Log(("vmsvgaReset\n"));
5427
5428	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5429	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5430	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5431
5432	/* Reset other stuff. */
5433	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5434	RT_ZERO(pThis->svga.au32ScratchRegion);
5435
5436	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5437	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5438
5439	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5440
5441	/* Register caps. */
5442	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5443	# ifdef VBOX_WITH_VMSVGA3D
5444	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5445	# endif
5446
5447	/* Setup FIFO capabilities. */
5448	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5449
5450	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5451	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5452
5453	/* VRAM tracking is enabled by default during bootup. */
5454	pThis->svga.fVRAMTracking = true;
5455	pThis->svga.fEnabled = false;
5456
5457	/* Invalidate current settings. */
5458	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5459	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5460	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5461	pThis->svga.cbScanline = 0;
5462
5463	return rc;
5464	}
5465
5466	/**
5467	* Cleans up the SVGA hardware state
5468	*
5469	* @returns VBox status code.
5470	* @param pDevIns The device instance.
5471	*/
5472	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5473	{
5474	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5475
5476	/*
5477	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5478	*/
5479	if (pThis->svga.pFIFOIOThread)
5480	{
5481	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5482	AssertLogRelRC(rc);
5483
5484	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5485	AssertLogRelRC(rc);
5486	pThis->svga.pFIFOIOThread = NULL;
5487	}
5488
5489	/*
5490	* Destroy the special SVGA state.
5491	*/
5492	if (pThis->svga.pSvgaR3State)
5493	{
5494	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5495
5496	RTMemFree(pThis->svga.pSvgaR3State);
5497	pThis->svga.pSvgaR3State = NULL;
5498	}
5499
5500	/*
5501	* Free our resources residing in the VGA state.
5502	*/
5503	if (pThis->svga.pbVgaFrameBufferR3)
5504	{
5505	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5506	pThis->svga.pbVgaFrameBufferR3 = NULL;
5507	}
5508	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5509	{
5510	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5511	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5512	}
5513	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5514	{
5515	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5516	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5517	}
5518
5519	return VINF_SUCCESS;
5520	}
5521
5522	/**
5523	* Initialize the SVGA hardware state
5524	*
5525	* @returns VBox status code.
5526	* @param pDevIns The device instance.
5527	*/
5528	int vmsvgaInit(PPDMDEVINS pDevIns)
5529	{
5530	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5531	PVMSVGAR3STATE pSVGAState;
5532	PVM pVM = PDMDevHlpGetVM(pDevIns);
5533	int rc;
5534
5535	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5536	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5537
5538	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5539
5540	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5541	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5542	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5543
5544	/* Create event semaphore. */
5545	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5546
5547	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5548	if (RT_FAILURE(rc))
5549	{
5550	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5551	return rc;
5552	}
5553
5554	/* Create event semaphore. */
5555	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5556	if (RT_FAILURE(rc))
5557	{
5558	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5559	return rc;
5560	}
5561
5562	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5563	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5564
5565	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5566	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5567
5568	pSVGAState = pThis->svga.pSvgaR3State;
5569
5570	/* Register caps. */
5571	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5572	# ifdef VBOX_WITH_VMSVGA3D
5573	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5574	# endif
5575
5576	/* Setup FIFO capabilities. */
5577	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5578
5579	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5580	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5581
5582	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5583	# ifdef VBOX_WITH_VMSVGA3D
5584	if (pThis->svga.f3DEnabled)
5585	{
5586	rc = vmsvga3dInit(pThis);
5587	if (RT_FAILURE(rc))
5588	{
5589	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5590	pThis->svga.f3DEnabled = false;
5591	}
5592	}
5593	# endif
5594	/* VRAM tracking is enabled by default during bootup. */
5595	pThis->svga.fVRAMTracking = true;
5596
5597	/* Invalidate current settings. */
5598	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5599	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5600	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5601	pThis->svga.cbScanline = 0;
5602
5603	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5604	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5605	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5606	{
5607	pThis->svga.u32MaxWidth -= 256;
5608	pThis->svga.u32MaxHeight -= 256;
5609	}
5610	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5611
5612	# ifdef DEBUG_GMR_ACCESS
5613	/* Register the GMR access handler type. */
5614	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5615	vmsvgaR3GMRAccessHandler,
5616	NULL, NULL, NULL,
5617	NULL, NULL, NULL,
5618	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5619	AssertRCReturn(rc, rc);
5620	# endif
5621	# ifdef DEBUG_FIFO_ACCESS
5622	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5623	vmsvgaR3FIFOAccessHandler,
5624	NULL, NULL, NULL,
5625	NULL, NULL, NULL,
5626	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5627	AssertRCReturn(rc, rc);
5628	#endif
5629
5630	/* Create the async IO thread. */
5631	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5632	RTTHREADTYPE_IO, "VMSVGA FIFO");
5633	if (RT_FAILURE(rc))
5634	{
5635	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5636	return rc;
5637	}
5638
5639	/*
5640	* Statistics.
5641	*/
5642	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5643	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5644	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5645	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5646	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5647	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5648	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5649	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5650	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5651	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5652	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5653	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5654	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5655	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5656	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5657	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5658	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5659	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5660	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5661	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5662	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5663	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5664	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5665	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5666	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5667	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5668	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5669	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5670	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5671	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5672	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5673	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5674	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5675	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5676	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5677	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5678	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5679	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5680	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5681	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5682	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5683	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5684	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5685	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5686	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5687	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5688	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5689	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5690	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5691	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5692	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5693	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5694	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5695	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5696	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5697	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5698
5699	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5700	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5701	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5702	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5703	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5704	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5705	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5706	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5707	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5708	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5709	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5710	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5711	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5712	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5713	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5714	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5715	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5716	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5717	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5718	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5719	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5720	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5721	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5722	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5723	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5724	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5725	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5726	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5727	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5728	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5729	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5730	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5731
5732	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5733	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5734	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5735	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5736	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5737	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5738	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5739	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5740	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5741	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5742	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5743	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5744	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5745	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5746	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5747	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5748	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5749	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5750	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5751	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5752	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5753	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5754	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5755	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5756	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5757	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5758	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5759	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5760	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5761	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5762	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5763	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5764	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5765	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5766	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5767	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5768	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5769	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5770	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5771	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5772	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5773	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5774	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5775	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5776	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5777	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5778	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5779	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5780	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5781
5782	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5783	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5784	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5785	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5786	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5787	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5788	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5789
5790	/*
5791	* Info handlers.
5792	*/
5793	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5794	# ifdef VBOX_WITH_VMSVGA3D
5795	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5796	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5797	"VMSVGA 3d surface details. "
5798	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5799	vmsvgaR3Info3dSurface);
5800	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
5801	"VMSVGA 3d surface details and bitmap: "
5802	"sid[>dir]",
5803	vmsvgaR3Info3dSurfaceBmp);
5804	# endif
5805
5806	return VINF_SUCCESS;
5807	}
5808
5809	# ifdef VBOX_WITH_VMSVGA3D
5810	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5811	static const char * const g_apszVmSvgaDevCapNames[] =
5812	{
5813	"x3D", /* = 0 */
5814	"xMAX_LIGHTS",
5815	"xMAX_TEXTURES",
5816	"xMAX_CLIP_PLANES",
5817	"xVERTEX_SHADER_VERSION",
5818	"xVERTEX_SHADER",
5819	"xFRAGMENT_SHADER_VERSION",
5820	"xFRAGMENT_SHADER",
5821	"xMAX_RENDER_TARGETS",
5822	"xS23E8_TEXTURES",
5823	"xS10E5_TEXTURES",
5824	"xMAX_FIXED_VERTEXBLEND",
5825	"xD16_BUFFER_FORMAT",
5826	"xD24S8_BUFFER_FORMAT",
5827	"xD24X8_BUFFER_FORMAT",
5828	"xQUERY_TYPES",
5829	"xTEXTURE_GRADIENT_SAMPLING",
5830	"rMAX_POINT_SIZE",
5831	"xMAX_SHADER_TEXTURES",
5832	"xMAX_TEXTURE_WIDTH",
5833	"xMAX_TEXTURE_HEIGHT",
5834	"xMAX_VOLUME_EXTENT",
5835	"xMAX_TEXTURE_REPEAT",
5836	"xMAX_TEXTURE_ASPECT_RATIO",
5837	"xMAX_TEXTURE_ANISOTROPY",
5838	"xMAX_PRIMITIVE_COUNT",
5839	"xMAX_VERTEX_INDEX",
5840	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5841	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5842	"xMAX_VERTEX_SHADER_TEMPS",
5843	"xMAX_FRAGMENT_SHADER_TEMPS",
5844	"xTEXTURE_OPS",
5845	"xSURFACEFMT_X8R8G8B8",
5846	"xSURFACEFMT_A8R8G8B8",
5847	"xSURFACEFMT_A2R10G10B10",
5848	"xSURFACEFMT_X1R5G5B5",
5849	"xSURFACEFMT_A1R5G5B5",
5850	"xSURFACEFMT_A4R4G4B4",
5851	"xSURFACEFMT_R5G6B5",
5852	"xSURFACEFMT_LUMINANCE16",
5853	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5854	"xSURFACEFMT_ALPHA8",
5855	"xSURFACEFMT_LUMINANCE8",
5856	"xSURFACEFMT_Z_D16",
5857	"xSURFACEFMT_Z_D24S8",
5858	"xSURFACEFMT_Z_D24X8",
5859	"xSURFACEFMT_DXT1",
5860	"xSURFACEFMT_DXT2",
5861	"xSURFACEFMT_DXT3",
5862	"xSURFACEFMT_DXT4",
5863	"xSURFACEFMT_DXT5",
5864	"xSURFACEFMT_BUMPX8L8V8U8",
5865	"xSURFACEFMT_A2W10V10U10",
5866	"xSURFACEFMT_BUMPU8V8",
5867	"xSURFACEFMT_Q8W8V8U8",
5868	"xSURFACEFMT_CxV8U8",
5869	"xSURFACEFMT_R_S10E5",
5870	"xSURFACEFMT_R_S23E8",
5871	"xSURFACEFMT_RG_S10E5",
5872	"xSURFACEFMT_RG_S23E8",
5873	"xSURFACEFMT_ARGB_S10E5",
5874	"xSURFACEFMT_ARGB_S23E8",
5875	"xMISSING62",
5876	"xMAX_VERTEX_SHADER_TEXTURES",
5877	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5878	"xSURFACEFMT_V16U16",
5879	"xSURFACEFMT_G16R16",
5880	"xSURFACEFMT_A16B16G16R16",
5881	"xSURFACEFMT_UYVY",
5882	"xSURFACEFMT_YUY2",
5883	"xMULTISAMPLE_NONMASKABLESAMPLES",
5884	"xMULTISAMPLE_MASKABLESAMPLES",
5885	"xALPHATOCOVERAGE",
5886	"xSUPERSAMPLE",
5887	"xAUTOGENMIPMAPS",
5888	"xSURFACEFMT_NV12",
5889	"xSURFACEFMT_AYUV",
5890	"xMAX_CONTEXT_IDS",
5891	"xMAX_SURFACE_IDS",
5892	"xSURFACEFMT_Z_DF16",
5893	"xSURFACEFMT_Z_DF24",
5894	"xSURFACEFMT_Z_D24S8_INT",
5895	"xSURFACEFMT_BC4_UNORM",
5896	"xSURFACEFMT_BC5_UNORM", /* 83 */
5897	};
5898	# endif
5899
5900
5901	/**
5902	* Power On notification.
5903	*
5904	* @returns VBox status code.
5905	* @param pDevIns The device instance data.
5906	*
5907	* @remarks Caller enters the device critical section.
5908	*/
5909	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
5910	{
5911	# ifdef VBOX_WITH_VMSVGA3D
5912	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5913	if (pThis->svga.f3DEnabled)
5914	{
5915	int rc = vmsvga3dPowerOn(pThis);
5916
5917	if (RT_SUCCESS(rc))
5918	{
5919	bool fSavedBuffering = RTLogRelSetBuffering(true);
5920	SVGA3dCapsRecord *pCaps;
5921	SVGA3dCapPair *pData;
5922	uint32_t idxCap = 0;
5923
5924	/* 3d hardware version; latest and greatest */
5925	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5926	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5927
5928	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5929	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5930	pData = (SVGA3dCapPair *)&pCaps->data;
5931
5932	/* Fill out all 3d capabilities. */
5933	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5934	{
5935	uint32_t val = 0;
5936
5937	rc = vmsvga3dQueryCaps(pThis, i, &val);
5938	if (RT_SUCCESS(rc))
5939	{
5940	pData[idxCap][0] = i;
5941	pData[idxCap][1] = val;
5942	idxCap++;
5943	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5944	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5945	else
5946	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5947	&g_apszVmSvgaDevCapNames[i][1]));
5948	}
5949	else
5950	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5951	}
5952	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5953	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5954
5955	/* Mark end of record array. */
5956	pCaps->header.length = 0;
5957
5958	RTLogRelSetBuffering(fSavedBuffering);
5959	}
5960	}
5961	# else /* !VBOX_WITH_VMSVGA3D */
5962	RT_NOREF(pDevIns);
5963	# endif /* !VBOX_WITH_VMSVGA3D */
5964	}
5965
5966	#endif /* IN_RING3 */
5967

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 75717

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