DevVGA-SVGA.cpp@ 76201

Last change on this file since 76201 was 76181, checked in by vboxsync, 6 years ago
DevVGA-SVGA: process the three GMRFB related commands when VBOX_WITH_VMSVGA3D is not defined.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 277.6 KB

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1	/* $Id: DevVGA-SVGA.cpp 76181 2018-12-12 15:16:19Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2017 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/AssertGuest.h>
148	#include <VBox/VMMDev.h>
149	#include <VBoxVideo.h>
150	#include <VBox/bioslogo.h>
151
152	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
153	#include "DevVGA.h"
154
155	#include "DevVGA-SVGA.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_caps.h"
159	#ifdef VBOX_WITH_VMSVGA3D
160	# include "DevVGA-SVGA3d.h"
161	# ifdef RT_OS_DARWIN
162	# include "DevVGA-SVGA3d-cocoa.h"
163	# endif
164	#endif
165
166
167	/*********************************************************************************************************************************
168	* Defined Constants And Macros *
169	*********************************************************************************************************************************/
170	/**
171	* Macro for checking if a fixed FIFO register is valid according to the
172	* current FIFO configuration.
173	*
174	* @returns true / false.
175	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
176	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
177	*/
178	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
179
180
181	/*********************************************************************************************************************************
182	* Structures and Typedefs *
183	*********************************************************************************************************************************/
184	/**
185	* 64-bit GMR descriptor.
186	*/
187	typedef struct
188	{
189	RTGCPHYS GCPhys;
190	uint64_t numPages;
191	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
192
193	/**
194	* GMR slot
195	*/
196	typedef struct
197	{
198	uint32_t cMaxPages;
199	uint32_t cbTotal;
200	uint32_t numDescriptors;
201	PVMSVGAGMRDESCRIPTOR paDesc;
202	} GMR, *PGMR;
203
204	#ifdef IN_RING3
205	/**
206	* Internal SVGA ring-3 only state.
207	*/
208	typedef struct VMSVGAR3STATE
209	{
210	GMR *paGMR; // [VMSVGAState::cGMR]
211	struct
212	{
213	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
214	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
215	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
216	} GMRFB;
217	struct
218	{
219	bool fActive;
220	uint32_t xHotspot;
221	uint32_t yHotspot;
222	uint32_t width;
223	uint32_t height;
224	uint32_t cbData;
225	void *pData;
226	} Cursor;
227	SVGAColorBGRX colorAnnotation;
228
229	# ifdef VMSVGA_USE_EMT_HALT_CODE
230	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
231	uint32_t volatile cBusyDelayedEmts;
232	/** Set of EMTs that are */
233	VMCPUSET BusyDelayedEmts;
234	# else
235	/** Number of EMTs waiting on hBusyDelayedEmts. */
236	uint32_t volatile cBusyDelayedEmts;
237	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
238	* busy (ugly). */
239	RTSEMEVENTMULTI hBusyDelayedEmts;
240	# endif
241
242	/** Information obout screens. */
243	VMSVGASCREENOBJECT aScreens[64];
244
245	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
246	STAMPROFILE StatBusyDelayEmts;
247
248	STAMPROFILE StatR3Cmd3dPresentProf;
249	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
250	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
251	STAMCOUNTER StatR3CmdDefineGmr2;
252	STAMCOUNTER StatR3CmdDefineGmr2Free;
253	STAMCOUNTER StatR3CmdDefineGmr2Modify;
254	STAMCOUNTER StatR3CmdRemapGmr2;
255	STAMCOUNTER StatR3CmdRemapGmr2Modify;
256	STAMCOUNTER StatR3CmdInvalidCmd;
257	STAMCOUNTER StatR3CmdFence;
258	STAMCOUNTER StatR3CmdUpdate;
259	STAMCOUNTER StatR3CmdUpdateVerbose;
260	STAMCOUNTER StatR3CmdDefineCursor;
261	STAMCOUNTER StatR3CmdDefineAlphaCursor;
262	STAMCOUNTER StatR3CmdEscape;
263	STAMCOUNTER StatR3CmdDefineScreen;
264	STAMCOUNTER StatR3CmdDestroyScreen;
265	STAMCOUNTER StatR3CmdDefineGmrFb;
266	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
267	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
268	STAMCOUNTER StatR3CmdAnnotationFill;
269	STAMCOUNTER StatR3CmdAnnotationCopy;
270	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
271	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
272	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
273	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
275	STAMCOUNTER StatR3Cmd3dSurfaceDma;
276	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
277	STAMCOUNTER StatR3Cmd3dContextDefine;
278	STAMCOUNTER StatR3Cmd3dContextDestroy;
279	STAMCOUNTER StatR3Cmd3dSetTransform;
280	STAMCOUNTER StatR3Cmd3dSetZRange;
281	STAMCOUNTER StatR3Cmd3dSetRenderState;
282	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
283	STAMCOUNTER StatR3Cmd3dSetTextureState;
284	STAMCOUNTER StatR3Cmd3dSetMaterial;
285	STAMCOUNTER StatR3Cmd3dSetLightData;
286	STAMCOUNTER StatR3Cmd3dSetLightEnable;
287	STAMCOUNTER StatR3Cmd3dSetViewPort;
288	STAMCOUNTER StatR3Cmd3dSetClipPlane;
289	STAMCOUNTER StatR3Cmd3dClear;
290	STAMCOUNTER StatR3Cmd3dPresent;
291	STAMCOUNTER StatR3Cmd3dPresentReadBack;
292	STAMCOUNTER StatR3Cmd3dShaderDefine;
293	STAMCOUNTER StatR3Cmd3dShaderDestroy;
294	STAMCOUNTER StatR3Cmd3dSetShader;
295	STAMCOUNTER StatR3Cmd3dSetShaderConst;
296	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
297	STAMCOUNTER StatR3Cmd3dSetScissorRect;
298	STAMCOUNTER StatR3Cmd3dBeginQuery;
299	STAMCOUNTER StatR3Cmd3dEndQuery;
300	STAMCOUNTER StatR3Cmd3dWaitForQuery;
301	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
302	STAMCOUNTER StatR3Cmd3dActivateSurface;
303	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
304
305	STAMCOUNTER StatR3RegConfigDoneWr;
306	STAMCOUNTER StatR3RegGmrDescriptorWr;
307	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
308	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
309
310	STAMCOUNTER StatFifoCommands;
311	STAMCOUNTER StatFifoErrors;
312	STAMCOUNTER StatFifoUnkCmds;
313	STAMCOUNTER StatFifoTodoTimeout;
314	STAMCOUNTER StatFifoTodoWoken;
315	STAMPROFILE StatFifoStalls;
316
317	} VMSVGAR3STATE, *PVMSVGAR3STATE;
318	#endif /* IN_RING3 */
319
320
321	/*********************************************************************************************************************************
322	* Internal Functions *
323	*********************************************************************************************************************************/
324	#ifdef IN_RING3
325	# ifdef DEBUG_FIFO_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
327	# endif
328	# ifdef DEBUG_GMR_ACCESS
329	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
330	# endif
331	#endif
332
333
334	/*********************************************************************************************************************************
335	* Global Variables *
336	*********************************************************************************************************************************/
337	#ifdef IN_RING3
338
339	/**
340	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
341	*/
342	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
343	{
344	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
345	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
346	SSMFIELD_ENTRY_TERM()
347	};
348
349	/**
350	* SSM descriptor table for the GMR structure.
351	*/
352	static SSMFIELD const g_aGMRFields[] =
353	{
354	SSMFIELD_ENTRY( GMR, cMaxPages),
355	SSMFIELD_ENTRY( GMR, cbTotal),
356	SSMFIELD_ENTRY( GMR, numDescriptors),
357	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
363	*/
364	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
365	{
366	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
367	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
368	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
369	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
370	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
371	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
372	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
373	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
374	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
375	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
376	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
377	SSMFIELD_ENTRY_TERM()
378	};
379
380	/**
381	* SSM descriptor table for the VMSVGAR3STATE structure.
382	*/
383	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
384	{
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
386	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
387	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
388	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
389	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
390	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
391	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
392	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
393	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
394	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
396	#ifdef VMSVGA_USE_EMT_HALT_CODE
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
398	#else
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
400	#endif
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
458
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
463
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
470	SSMFIELD_ENTRY_TERM()
471	};
472
473	/**
474	* SSM descriptor table for the VGAState.svga structure.
475	*/
476	static SSMFIELD const g_aVGAStateSVGAFields[] =
477	{
478	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
479	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
480	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
481	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
482	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
483	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
484	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
485	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
488	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
489	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
490	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
491	SSMFIELD_ENTRY( VMSVGAState, fBusy),
492	SSMFIELD_ENTRY( VMSVGAState, fTraces),
493	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
494	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
495	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
496	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
497	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
498	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
499	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
500	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
501	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
502	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
504	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
506	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
507	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
508	SSMFIELD_ENTRY( VMSVGAState, uWidth),
509	SSMFIELD_ENTRY( VMSVGAState, uHeight),
510	SSMFIELD_ENTRY( VMSVGAState, uBpp),
511	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
512	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
513	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
514	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
515	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
516	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
517	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
519	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
521	SSMFIELD_ENTRY_TERM()
522	};
523
524	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
525	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
526	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
527
528	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
529	{
530	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
531	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
532	&& pSVGAState
533	&& pSVGAState->aScreens[idScreen].fDefined)
534	{
535	return &pSVGAState->aScreens[idScreen];
536	}
537	return NULL;
538	}
539
540	#endif /* IN_RING3 */
541
542	#ifdef LOG_ENABLED
543
544	/**
545	* Index register string name lookup
546	*
547	* @returns Index register string or "UNKNOWN"
548	* @param pThis VMSVGA State
549	* @param idxReg The index register.
550	*/
551	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
552	{
553	switch (idxReg)
554	{
555	case SVGA_REG_ID: return "SVGA_REG_ID";
556	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
557	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
558	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
559	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
560	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
561	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
562	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
563	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
564	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
565	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
566	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
567	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
568	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
569	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
570	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
571	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
572	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
573	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
574	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
575	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
576	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
577	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
578	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
579	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
580	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
581	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
582	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
583	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
584	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
585	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
586	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
587	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
588	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
589	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
590	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
591	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
592	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
593	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
594	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
595	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
596	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
597	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
598	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
599	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
600	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
601	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
602	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
603	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
604	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
605
606	default:
607	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
608	return "SVGA_SCRATCH_BASE reg";
609	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
610	return "SVGA_PALETTE_BASE reg";
611	return "UNKNOWN";
612	}
613	}
614
615	#ifdef IN_RING3
616	/**
617	* FIFO command name lookup
618	*
619	* @returns FIFO command string or "UNKNOWN"
620	* @param u32Cmd FIFO command
621	*/
622	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
623	{
624	switch (u32Cmd)
625	{
626	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
627	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
628	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
629	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
630	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
631	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
632	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
633	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
634	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
635	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
636	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
637	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
638	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
639	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
640	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
641	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
642	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
643	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
644	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
645	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
646	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
647	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
648	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
649	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
650	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
651	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
652	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
653	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
654	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
655	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
656	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
657	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
658	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
659	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
660	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
661	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
662	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
663	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
664	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
665	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
666	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
667	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
668	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
669	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
670	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
671	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
672	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
673	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
674	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
675	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
676	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
677	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
678	default: return "UNKNOWN";
679	}
680	}
681	# endif /* IN_RING3 */
682
683	#endif /* LOG_ENABLED */
684
685	#ifdef IN_RING3
686	/**
687	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
688	*/
689	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
690	{
691	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
692
693	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
694	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
695
696	/** @todo Test how it interacts with multiple screen objects. */
697	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
698	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
699	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
700
701	if (x < uWidth)
702	{
703	pThis->svga.viewport.x = x;
704	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
705	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
706	}
707	else
708	{
709	pThis->svga.viewport.x = uWidth;
710	pThis->svga.viewport.cx = 0;
711	pThis->svga.viewport.xRight = uWidth;
712	}
713	if (y < uHeight)
714	{
715	pThis->svga.viewport.y = y;
716	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
717	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
718	pThis->svga.viewport.yHighWC = uHeight - y;
719	}
720	else
721	{
722	pThis->svga.viewport.y = uHeight;
723	pThis->svga.viewport.cy = 0;
724	pThis->svga.viewport.yLowWC = 0;
725	pThis->svga.viewport.yHighWC = 0;
726	}
727
728	# ifdef VBOX_WITH_VMSVGA3D
729	/*
730	* Now inform the 3D backend.
731	*/
732	if (pThis->svga.f3DEnabled)
733	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
734	# else
735	RT_NOREF(OldViewport);
736	# endif
737	}
738	#endif /* IN_RING3 */
739
740	/**
741	* Read port register
742	*
743	* @returns VBox status code.
744	* @param pThis VMSVGA State
745	* @param pu32 Where to store the read value
746	*/
747	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
748	{
749	int rc = VINF_SUCCESS;
750	*pu32 = 0;
751
752	/* Rough index register validation. */
753	uint32_t idxReg = pThis->svga.u32IndexReg;
754	#if !defined(IN_RING3) && defined(VBOX_STRICT)
755	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
756	VINF_IOM_R3_IOPORT_READ);
757	#else
758	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
760	VINF_SUCCESS);
761	#endif
762	RT_UNTRUSTED_VALIDATED_FENCE();
763
764	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
765	if ( idxReg >= SVGA_REG_CAPABILITIES
766	&& pThis->svga.u32SVGAId == SVGA_ID_0)
767	{
768	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
769	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
770	}
771
772	switch (idxReg)
773	{
774	case SVGA_REG_ID:
775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
776	*pu32 = pThis->svga.u32SVGAId;
777	break;
778
779	case SVGA_REG_ENABLE:
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
781	*pu32 = pThis->svga.fEnabled;
782	break;
783
784	case SVGA_REG_WIDTH:
785	{
786	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
787	if ( pThis->svga.fEnabled
788	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
789	{
790	*pu32 = pThis->svga.uWidth;
791	}
792	else
793	{
794	#ifndef IN_RING3
795	rc = VINF_IOM_R3_IOPORT_READ;
796	#else
797	*pu32 = pThis->pDrv->cx;
798	#endif
799	}
800	break;
801	}
802
803	case SVGA_REG_HEIGHT:
804	{
805	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
806	if ( pThis->svga.fEnabled
807	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
808	{
809	*pu32 = pThis->svga.uHeight;
810	}
811	else
812	{
813	#ifndef IN_RING3
814	rc = VINF_IOM_R3_IOPORT_READ;
815	#else
816	*pu32 = pThis->pDrv->cy;
817	#endif
818	}
819	break;
820	}
821
822	case SVGA_REG_MAX_WIDTH:
823	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
824	*pu32 = pThis->svga.u32MaxWidth;
825	break;
826
827	case SVGA_REG_MAX_HEIGHT:
828	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
829	*pu32 = pThis->svga.u32MaxHeight;
830	break;
831
832	case SVGA_REG_DEPTH:
833	/* This returns the color depth of the current mode. */
834	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
835	switch (pThis->svga.uBpp)
836	{
837	case 15:
838	case 16:
839	case 24:
840	*pu32 = pThis->svga.uBpp;
841	break;
842
843	default:
844	case 32:
845	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
846	break;
847	}
848	break;
849
850	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
851	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
852	if ( pThis->svga.fEnabled
853	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
854	{
855	*pu32 = pThis->svga.uBpp;
856	}
857	else
858	{
859	#ifndef IN_RING3
860	rc = VINF_IOM_R3_IOPORT_READ;
861	#else
862	*pu32 = pThis->pDrv->cBits;
863	#endif
864	}
865	break;
866
867	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
868	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
869	if ( pThis->svga.fEnabled
870	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
871	{
872	*pu32 = (pThis->svga.uBpp + 7) & ~7;
873	}
874	else
875	{
876	#ifndef IN_RING3
877	rc = VINF_IOM_R3_IOPORT_READ;
878	#else
879	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
880	#endif
881	}
882	break;
883
884	case SVGA_REG_PSEUDOCOLOR:
885	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
886	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
887	break;
888
889	case SVGA_REG_RED_MASK:
890	case SVGA_REG_GREEN_MASK:
891	case SVGA_REG_BLUE_MASK:
892	{
893	uint32_t uBpp;
894
895	if ( pThis->svga.fEnabled
896	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
897	{
898	uBpp = pThis->svga.uBpp;
899	}
900	else
901	{
902	#ifndef IN_RING3
903	rc = VINF_IOM_R3_IOPORT_READ;
904	break;
905	#else
906	uBpp = pThis->pDrv->cBits;
907	#endif
908	}
909	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
910	switch (uBpp)
911	{
912	case 8:
913	u32RedMask = 0x07;
914	u32GreenMask = 0x38;
915	u32BlueMask = 0xc0;
916	break;
917
918	case 15:
919	u32RedMask = 0x0000001f;
920	u32GreenMask = 0x000003e0;
921	u32BlueMask = 0x00007c00;
922	break;
923
924	case 16:
925	u32RedMask = 0x0000001f;
926	u32GreenMask = 0x000007e0;
927	u32BlueMask = 0x0000f800;
928	break;
929
930	case 24:
931	case 32:
932	default:
933	u32RedMask = 0x00ff0000;
934	u32GreenMask = 0x0000ff00;
935	u32BlueMask = 0x000000ff;
936	break;
937	}
938	switch (idxReg)
939	{
940	case SVGA_REG_RED_MASK:
941	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
942	*pu32 = u32RedMask;
943	break;
944
945	case SVGA_REG_GREEN_MASK:
946	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
947	*pu32 = u32GreenMask;
948	break;
949
950	case SVGA_REG_BLUE_MASK:
951	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
952	*pu32 = u32BlueMask;
953	break;
954	}
955	break;
956	}
957
958	case SVGA_REG_BYTES_PER_LINE:
959	{
960	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
961	if ( pThis->svga.fEnabled
962	&& pThis->svga.cbScanline)
963	{
964	*pu32 = pThis->svga.cbScanline;
965	}
966	else
967	{
968	#ifndef IN_RING3
969	rc = VINF_IOM_R3_IOPORT_READ;
970	#else
971	*pu32 = pThis->pDrv->cbScanline;
972	#endif
973	}
974	break;
975	}
976
977	case SVGA_REG_VRAM_SIZE: /* VRAM size */
978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
979	*pu32 = pThis->vram_size;
980	break;
981
982	case SVGA_REG_FB_START: /* Frame buffer physical address. */
983	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
984	Assert(pThis->GCPhysVRAM <= 0xffffffff);
985	*pu32 = pThis->GCPhysVRAM;
986	break;
987
988	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
989	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
990	/* Always zero in our case. */
991	*pu32 = 0;
992	break;
993
994	case SVGA_REG_FB_SIZE: /* Frame buffer size */
995	{
996	#ifndef IN_RING3
997	rc = VINF_IOM_R3_IOPORT_READ;
998	#else
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1000
1001	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1002	if ( pThis->svga.fEnabled
1003	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1004	{
1005	/* Hardware enabled; return real framebuffer size .*/
1006	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1007	}
1008	else
1009	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1010
1011	pu32 = RT_MIN(pThis->vram_size, pu32);
1012	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1013	#endif
1014	break;
1015	}
1016
1017	case SVGA_REG_CAPABILITIES:
1018	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1019	*pu32 = pThis->svga.u32RegCaps;
1020	break;
1021
1022	case SVGA_REG_MEM_START: /* FIFO start */
1023	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1024	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1025	*pu32 = pThis->svga.GCPhysFIFO;
1026	break;
1027
1028	case SVGA_REG_MEM_SIZE: /* FIFO size */
1029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1030	*pu32 = pThis->svga.cbFIFO;
1031	break;
1032
1033	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1035	*pu32 = pThis->svga.fConfigured;
1036	break;
1037
1038	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1040	*pu32 = 0;
1041	break;
1042
1043	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1045	if (pThis->svga.fBusy)
1046	{
1047	#ifndef IN_RING3
1048	/* Go to ring-3 and halt the CPU. */
1049	rc = VINF_IOM_R3_IOPORT_READ;
1050	break;
1051	#else
1052	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1053	/* The guest is basically doing a HLT via the device here, but with
1054	a special wake up condition on FIFO completion. */
1055	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1056	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1057	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1058	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1059	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1060	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1061	if (pThis->svga.fBusy)
1062	{
1063	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1064	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1065	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1066	}
1067	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1068	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1069	# else
1070
1071	/* Delay the EMT a bit so the FIFO and others can get some work done.
1072	This used to be a crude 50 ms sleep. The current code tries to be
1073	more efficient, but the consept is still very crude. */
1074	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1075	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1076	RTThreadYield();
1077	if (pThis->svga.fBusy)
1078	{
1079	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1080
1081	if (pThis->svga.fBusy && cRefs == 1)
1082	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1083	if (pThis->svga.fBusy)
1084	{
1085	/** @todo If this code is going to stay, we need to call into the halt/wait
1086	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1087	* suffer when the guest is polling on a busy FIFO. */
1088	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1089	if (cNsMaxWait >= RT_NS_100US)
1090	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1091	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1092	RT_MIN(cNsMaxWait, RT_NS_10MS));
1093	}
1094
1095	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1096	}
1097	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1098	# endif
1099	*pu32 = pThis->svga.fBusy != 0;
1100	#endif
1101	}
1102	else
1103	*pu32 = false;
1104	break;
1105
1106	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1107	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1108	*pu32 = pThis->svga.u32GuestId;
1109	break;
1110
1111	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1112	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1113	*pu32 = pThis->svga.cScratchRegion;
1114	break;
1115
1116	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1117	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1118	*pu32 = SVGA_FIFO_NUM_REGS;
1119	break;
1120
1121	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1122	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1123	*pu32 = pThis->svga.u32PitchLock;
1124	break;
1125
1126	case SVGA_REG_IRQMASK: /* Interrupt mask */
1127	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1128	*pu32 = pThis->svga.u32IrqMask;
1129	break;
1130
1131	/* See "Guest memory regions" below. */
1132	case SVGA_REG_GMR_ID:
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1134	*pu32 = pThis->svga.u32CurrentGMRId;
1135	break;
1136
1137	case SVGA_REG_GMR_DESCRIPTOR:
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1139	/* Write only */
1140	*pu32 = 0;
1141	break;
1142
1143	case SVGA_REG_GMR_MAX_IDS:
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1145	*pu32 = pThis->svga.cGMR;
1146	break;
1147
1148	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1150	*pu32 = VMSVGA_MAX_GMR_PAGES;
1151	break;
1152
1153	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1155	*pu32 = pThis->svga.fTraces;
1156	break;
1157
1158	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1160	*pu32 = VMSVGA_MAX_GMR_PAGES;
1161	break;
1162
1163	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1165	*pu32 = VMSVGA_SURFACE_SIZE;
1166	break;
1167
1168	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1170	break;
1171
1172	/* Mouse cursor support. */
1173	case SVGA_REG_CURSOR_ID:
1174	case SVGA_REG_CURSOR_X:
1175	case SVGA_REG_CURSOR_Y:
1176	case SVGA_REG_CURSOR_ON:
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1178	break;
1179
1180	/* Legacy multi-monitor support */
1181	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1183	*pu32 = 1;
1184	break;
1185
1186	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1188	*pu32 = 0;
1189	break;
1190
1191	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1192	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1193	*pu32 = 0;
1194	break;
1195
1196	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1197	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1198	*pu32 = 0;
1199	break;
1200
1201	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1202	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1203	*pu32 = 0;
1204	break;
1205
1206	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1207	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1208	*pu32 = pThis->svga.uWidth;
1209	break;
1210
1211	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1212	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1213	*pu32 = pThis->svga.uHeight;
1214	break;
1215
1216	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1217	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1218	/* We must return something sensible here otherwise the Linux driver
1219	* will take a legacy code path without 3d support. This number also
1220	* limits how many screens Linux guests will allow. */
1221	*pu32 = pThis->cMonitors;
1222	break;
1223
1224	default:
1225	{
1226	uint32_t offReg;
1227	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1228	{
1229	RT_UNTRUSTED_VALIDATED_FENCE();
1230	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1231	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1232	}
1233	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1234	{
1235	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1236	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1237	RT_UNTRUSTED_VALIDATED_FENCE();
1238	uint32_t u32 = pThis->last_palette[offReg / 3];
1239	switch (offReg % 3)
1240	{
1241	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1242	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1243	case 2: pu32 = u32 & 0xff; break; / blue */
1244	}
1245	}
1246	else
1247	{
1248	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1249	rc = VINF_IOM_R3_IOPORT_READ;
1250	#else
1251	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1252
1253	/* Do not assert. The guest might be reading all registers. */
1254	LogFunc(("Unknown reg=%#x\n", idxReg));
1255	#endif
1256	}
1257	break;
1258	}
1259	}
1260	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1261	return rc;
1262	}
1263
1264	#ifdef IN_RING3
1265	/**
1266	* Apply the current resolution settings to change the video mode.
1267	*
1268	* @returns VBox status code.
1269	* @param pThis VMSVGA State
1270	*/
1271	static int vmsvgaChangeMode(PVGASTATE pThis)
1272	{
1273	int rc;
1274
1275	/* Always do changemode on FIFO thread. */
1276	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1277
1278	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1279
1280	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1281
1282	if (pThis->svga.fGFBRegisters)
1283	{
1284	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1285	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1286	* deletes all screens other than screen #0, and redefines screen
1287	* #0 according to the specified mode. Drivers that use
1288	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1289	*/
1290
1291	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1292	pScreen->fDefined = true;
1293	pScreen->fModified = true;
1294	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1295	pScreen->idScreen = 0;
1296	pScreen->xOrigin = 0;
1297	pScreen->yOrigin = 0;
1298	pScreen->offVRAM = 0;
1299	pScreen->cbPitch = pThis->svga.cbScanline;
1300	pScreen->cWidth = pThis->svga.uWidth;
1301	pScreen->cHeight = pThis->svga.uHeight;
1302	pScreen->cBpp = pThis->svga.uBpp;
1303
1304	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1305	{
1306	/* Delete screen. */
1307	pScreen = &pSVGAState->aScreens[iScreen];
1308	if (pScreen->fDefined)
1309	{
1310	pScreen->fModified = true;
1311	pScreen->fDefined = false;
1312	}
1313	}
1314	}
1315	else
1316	{
1317	/* "If Screen Objects are supported, they can be used to fully
1318	* replace the functionality provided by the framebuffer registers
1319	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1320	*/
1321	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1322	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1323	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1324	}
1325
1326	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1327	{
1328	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1329	if (!pScreen->fModified)
1330	continue;
1331
1332	pScreen->fModified = false;
1333
1334	VBVAINFOVIEW view;
1335	RT_ZERO(view);
1336	view.u32ViewIndex = pScreen->idScreen;
1337	// view.u32ViewOffset = 0;
1338	view.u32ViewSize = pThis->vram_size;
1339	view.u32MaxScreenSize = pThis->vram_size;
1340
1341	VBVAINFOSCREEN screen;
1342	RT_ZERO(screen);
1343	screen.u32ViewIndex = pScreen->idScreen;
1344
1345	if (pScreen->fDefined)
1346	{
1347	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1348	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1349	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1350	{
1351	Assert(pThis->svga.fGFBRegisters);
1352	continue;
1353	}
1354
1355	screen.i32OriginX = pScreen->xOrigin;
1356	screen.i32OriginY = pScreen->yOrigin;
1357	screen.u32StartOffset = pScreen->offVRAM;
1358	screen.u32LineSize = pScreen->cbPitch;
1359	screen.u32Width = pScreen->cWidth;
1360	screen.u32Height = pScreen->cHeight;
1361	screen.u16BitsPerPixel = pScreen->cBpp;
1362	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1363	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1364	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1365	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1366	}
1367	else
1368	{
1369	/* Screen is destroyed. */
1370	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1371	}
1372
1373	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1374	AssertRC(rc);
1375	}
1376
1377	/* Last stuff. For the VGA device screenshot. */
1378	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1379	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1380	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1381	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1382	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1383
1384	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1385	if ( pThis->svga.viewport.cx == 0
1386	&& pThis->svga.viewport.cy == 0)
1387	{
1388	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1389	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1390	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1391	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1392	pThis->svga.viewport.yLowWC = 0;
1393	}
1394
1395	return VINF_SUCCESS;
1396	}
1397
1398	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1399	{
1400	if (pThis->svga.fGFBRegisters)
1401	{
1402	vgaR3UpdateDisplay(pThis, x, y, w, h);
1403	}
1404	else
1405	{
1406	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1407	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1408	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1409	}
1410
1411	return VINF_SUCCESS;
1412	}
1413
1414	#endif /* IN_RING3 */
1415
1416	#if defined(IN_RING0) \|\| defined(IN_RING3)
1417	/**
1418	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1419	*
1420	* @param pThis The VMSVGA state.
1421	* @param fState The busy state.
1422	*/
1423	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1424	{
1425	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1426
1427	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1428	{
1429	/* Race / unfortunately scheduling. Highly unlikly. */
1430	uint32_t cLoops = 64;
1431	do
1432	{
1433	ASMNopPause();
1434	fState = (pThis->svga.fBusy != 0);
1435	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1436	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1437	}
1438	}
1439	#endif
1440
1441	/**
1442	* Write port register
1443	*
1444	* @returns VBox status code.
1445	* @param pThis VMSVGA State
1446	* @param u32 Value to write
1447	*/
1448	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1449	{
1450	#ifdef IN_RING3
1451	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1452	#endif
1453	int rc = VINF_SUCCESS;
1454
1455	/* Rough index register validation. */
1456	uint32_t idxReg = pThis->svga.u32IndexReg;
1457	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1458	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1459	VINF_IOM_R3_IOPORT_WRITE);
1460	#else
1461	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1462	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1463	VINF_SUCCESS);
1464	#endif
1465	RT_UNTRUSTED_VALIDATED_FENCE();
1466
1467	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1468	if ( idxReg >= SVGA_REG_CAPABILITIES
1469	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1470	{
1471	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1472	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1473	}
1474	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1475	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1476	switch (idxReg)
1477	{
1478	case SVGA_REG_WIDTH:
1479	case SVGA_REG_HEIGHT:
1480	case SVGA_REG_PITCHLOCK:
1481	case SVGA_REG_BITS_PER_PIXEL:
1482	pThis->svga.fGFBRegisters = true;
1483	break;
1484	default:
1485	break;
1486	}
1487
1488	switch (idxReg)
1489	{
1490	case SVGA_REG_ID:
1491	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1492	if ( u32 == SVGA_ID_0
1493	\|\| u32 == SVGA_ID_1
1494	\|\| u32 == SVGA_ID_2)
1495	pThis->svga.u32SVGAId = u32;
1496	else
1497	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1498	break;
1499
1500	case SVGA_REG_ENABLE:
1501	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1502	#ifdef IN_RING3
1503	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1504	&& pThis->svga.fEnabled == false)
1505	{
1506	/* Make a backup copy of the first 512kb in order to save font data etc. */
1507	/** @todo should probably swap here, rather than copy + zero */
1508	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1509	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1510	}
1511
1512	pThis->svga.fEnabled = u32;
1513	if (pThis->svga.fEnabled)
1514	{
1515	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1516	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1517	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1518	{
1519	/* Keep the current mode. */
1520	pThis->svga.uWidth = pThis->pDrv->cx;
1521	pThis->svga.uHeight = pThis->pDrv->cy;
1522	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1523	}
1524
1525	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1526	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1527	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1528	{
1529	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1530	}
1531	# ifdef LOG_ENABLED
1532	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1533	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1534	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1535	# endif
1536
1537	/* Disable or enable dirty page tracking according to the current fTraces value. */
1538	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1539	}
1540	else
1541	{
1542	/* Restore the text mode backup. */
1543	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1544
1545	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1546
1547	/* Enable dirty page tracking again when going into legacy mode. */
1548	vmsvgaSetTraces(pThis, true);
1549	}
1550	#else /* !IN_RING3 */
1551	rc = VINF_IOM_R3_IOPORT_WRITE;
1552	#endif /* !IN_RING3 */
1553	break;
1554
1555	case SVGA_REG_WIDTH:
1556	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1557	if (pThis->svga.uWidth != u32)
1558	{
1559	pThis->svga.uWidth = u32;
1560	if (pThis->svga.fEnabled)
1561	{
1562	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1563	}
1564	}
1565	/* else: nop */
1566	break;
1567
1568	case SVGA_REG_HEIGHT:
1569	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1570	if (pThis->svga.uHeight != u32)
1571	{
1572	pThis->svga.uHeight = u32;
1573	if (pThis->svga.fEnabled)
1574	{
1575	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1576	}
1577	}
1578	/* else: nop */
1579	break;
1580
1581	case SVGA_REG_DEPTH:
1582	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1583	/** @todo read-only?? */
1584	break;
1585
1586	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1587	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1588	if (pThis->svga.uBpp != u32)
1589	{
1590	pThis->svga.uBpp = u32;
1591	if (pThis->svga.fEnabled)
1592	{
1593	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1594	}
1595	}
1596	/* else: nop */
1597	break;
1598
1599	case SVGA_REG_PSEUDOCOLOR:
1600	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1601	break;
1602
1603	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1604	#ifdef IN_RING3
1605	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1606	pThis->svga.fConfigured = u32;
1607	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1608	if (!pThis->svga.fConfigured)
1609	{
1610	pThis->svga.fTraces = true;
1611	}
1612	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1613	#else
1614	rc = VINF_IOM_R3_IOPORT_WRITE;
1615	#endif
1616	break;
1617
1618	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1619	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1620	if ( pThis->svga.fEnabled
1621	&& pThis->svga.fConfigured)
1622	{
1623	#if defined(IN_RING3) \|\| defined(IN_RING0)
1624	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1625	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1626	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1627	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1628
1629	/* Kick the FIFO thread to start processing commands again. */
1630	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1631	#else
1632	rc = VINF_IOM_R3_IOPORT_WRITE;
1633	#endif
1634	}
1635	/* else nothing to do. */
1636	else
1637	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1638
1639	break;
1640
1641	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1642	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1643	break;
1644
1645	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1646	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1647	pThis->svga.u32GuestId = u32;
1648	break;
1649
1650	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1651	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1652	pThis->svga.u32PitchLock = u32;
1653	break;
1654
1655	case SVGA_REG_IRQMASK: /* Interrupt mask */
1656	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1657	pThis->svga.u32IrqMask = u32;
1658
1659	/* Irq pending after the above change? */
1660	if (pThis->svga.u32IrqStatus & u32)
1661	{
1662	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1663	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1664	}
1665	else
1666	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1667	break;
1668
1669	/* Mouse cursor support */
1670	case SVGA_REG_CURSOR_ID:
1671	case SVGA_REG_CURSOR_X:
1672	case SVGA_REG_CURSOR_Y:
1673	case SVGA_REG_CURSOR_ON:
1674	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1675	break;
1676
1677	/* Legacy multi-monitor support */
1678	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1679	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1680	break;
1681	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1682	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1683	break;
1684	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1685	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1686	break;
1687	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1688	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1689	break;
1690	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1691	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1692	break;
1693	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1694	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1695	break;
1696	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1697	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1698	break;
1699	#ifdef VBOX_WITH_VMSVGA3D
1700	/* See "Guest memory regions" below. */
1701	case SVGA_REG_GMR_ID:
1702	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1703	pThis->svga.u32CurrentGMRId = u32;
1704	break;
1705
1706	case SVGA_REG_GMR_DESCRIPTOR:
1707	# ifndef IN_RING3
1708	rc = VINF_IOM_R3_IOPORT_WRITE;
1709	break;
1710	# else /* IN_RING3 */
1711	{
1712	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1713
1714	/* Validate current GMR id. */
1715	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1716	AssertBreak(idGMR < pThis->svga.cGMR);
1717	RT_UNTRUSTED_VALIDATED_FENCE();
1718
1719	/* Free the old GMR if present. */
1720	vmsvgaGMRFree(pThis, idGMR);
1721
1722	/* Just undefine the GMR? */
1723	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1724	if (GCPhys == 0)
1725	{
1726	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1727	break;
1728	}
1729
1730
1731	/* Never cross a page boundary automatically. */
1732	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1733	uint32_t cPagesTotal = 0;
1734	uint32_t iDesc = 0;
1735	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1736	uint32_t cLoops = 0;
1737	RTGCPHYS GCPhysBase = GCPhys;
1738	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1739	{
1740	/* Read descriptor. */
1741	SVGAGuestMemDescriptor desc;
1742	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1743	AssertRCBreak(rc);
1744
1745	if (desc.numPages != 0)
1746	{
1747	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1748	cPagesTotal += desc.numPages;
1749	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1750
1751	if ((iDesc & 15) == 0)
1752	{
1753	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1754	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1755	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1756	}
1757
1758	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1759	paDescs[iDesc++].numPages = desc.numPages;
1760
1761	/* Continue with the next descriptor. */
1762	GCPhys += sizeof(desc);
1763	}
1764	else if (desc.ppn == 0)
1765	break; /* terminator */
1766	else /* Pointer to the next physical page of descriptors. */
1767	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1768
1769	cLoops++;
1770	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1771	}
1772
1773	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1774	if (RT_SUCCESS(rc))
1775	{
1776	/* Commit the GMR. */
1777	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1778	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1779	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1780	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1781	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1782	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1783	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1784	}
1785	else
1786	{
1787	RTMemFree(paDescs);
1788	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1789	}
1790	break;
1791	}
1792	# endif /* IN_RING3 */
1793	#endif // VBOX_WITH_VMSVGA3D
1794
1795	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1797	if (pThis->svga.fTraces == u32)
1798	break; /* nothing to do */
1799
1800	#ifdef IN_RING3
1801	vmsvgaSetTraces(pThis, !!u32);
1802	#else
1803	rc = VINF_IOM_R3_IOPORT_WRITE;
1804	#endif
1805	break;
1806
1807	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1809	break;
1810
1811	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1812	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1813	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1814	break;
1815
1816	case SVGA_REG_FB_START:
1817	case SVGA_REG_MEM_START:
1818	case SVGA_REG_HOST_BITS_PER_PIXEL:
1819	case SVGA_REG_MAX_WIDTH:
1820	case SVGA_REG_MAX_HEIGHT:
1821	case SVGA_REG_VRAM_SIZE:
1822	case SVGA_REG_FB_SIZE:
1823	case SVGA_REG_CAPABILITIES:
1824	case SVGA_REG_MEM_SIZE:
1825	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1826	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1827	case SVGA_REG_BYTES_PER_LINE:
1828	case SVGA_REG_FB_OFFSET:
1829	case SVGA_REG_RED_MASK:
1830	case SVGA_REG_GREEN_MASK:
1831	case SVGA_REG_BLUE_MASK:
1832	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1833	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1834	case SVGA_REG_GMR_MAX_IDS:
1835	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1836	/* Read only - ignore. */
1837	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1838	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1839	break;
1840
1841	default:
1842	{
1843	uint32_t offReg;
1844	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1845	{
1846	RT_UNTRUSTED_VALIDATED_FENCE();
1847	pThis->svga.au32ScratchRegion[offReg] = u32;
1848	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1849	}
1850	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1851	{
1852	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1853	Btw, see rgb_to_pixel32. */
1854	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1855	u32 &= 0xff;
1856	RT_UNTRUSTED_VALIDATED_FENCE();
1857	uint32_t uRgb = pThis->last_palette[offReg / 3];
1858	switch (offReg % 3)
1859	{
1860	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1861	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1862	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1863	}
1864	pThis->last_palette[offReg / 3] = uRgb;
1865	}
1866	else
1867	{
1868	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1869	rc = VINF_IOM_R3_IOPORT_WRITE;
1870	#else
1871	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1872	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1873	#endif
1874	}
1875	break;
1876	}
1877	}
1878	return rc;
1879	}
1880
1881	/**
1882	* Port I/O Handler for IN operations.
1883	*
1884	* @returns VINF_SUCCESS or VINF_EM_*.
1885	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1886	*
1887	* @param pDevIns The device instance.
1888	* @param pvUser User argument.
1889	* @param uPort Port number used for the IN operation.
1890	* @param pu32 Where to store the result. This is always a 32-bit
1891	* variable regardless of what @a cb might say.
1892	* @param cb Number of bytes read.
1893	*/
1894	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1895	{
1896	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1897	RT_NOREF_PV(pvUser);
1898
1899	/* Ignore non-dword accesses. */
1900	if (cb != 4)
1901	{
1902	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1903	*pu32 = UINT32_MAX;
1904	return VINF_SUCCESS;
1905	}
1906
1907	switch (uPort - pThis->svga.BasePort)
1908	{
1909	case SVGA_INDEX_PORT:
1910	*pu32 = pThis->svga.u32IndexReg;
1911	break;
1912
1913	case SVGA_VALUE_PORT:
1914	return vmsvgaReadPort(pThis, pu32);
1915
1916	case SVGA_BIOS_PORT:
1917	Log(("Ignoring BIOS port read\n"));
1918	*pu32 = 0;
1919	break;
1920
1921	case SVGA_IRQSTATUS_PORT:
1922	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1923	*pu32 = pThis->svga.u32IrqStatus;
1924	break;
1925
1926	default:
1927	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1928	*pu32 = UINT32_MAX;
1929	break;
1930	}
1931
1932	return VINF_SUCCESS;
1933	}
1934
1935	/**
1936	* Port I/O Handler for OUT operations.
1937	*
1938	* @returns VINF_SUCCESS or VINF_EM_*.
1939	*
1940	* @param pDevIns The device instance.
1941	* @param pvUser User argument.
1942	* @param uPort Port number used for the OUT operation.
1943	* @param u32 The value to output.
1944	* @param cb The value size in bytes.
1945	*/
1946	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1947	{
1948	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1949	RT_NOREF_PV(pvUser);
1950
1951	/* Ignore non-dword accesses. */
1952	if (cb != 4)
1953	{
1954	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1955	return VINF_SUCCESS;
1956	}
1957
1958	switch (uPort - pThis->svga.BasePort)
1959	{
1960	case SVGA_INDEX_PORT:
1961	pThis->svga.u32IndexReg = u32;
1962	break;
1963
1964	case SVGA_VALUE_PORT:
1965	return vmsvgaWritePort(pThis, u32);
1966
1967	case SVGA_BIOS_PORT:
1968	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1969	break;
1970
1971	case SVGA_IRQSTATUS_PORT:
1972	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1973	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1974	/* Clear the irq in case all events have been cleared. */
1975	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1976	{
1977	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1978	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1979	}
1980	break;
1981
1982	default:
1983	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
1984	uPort - pThis->svga.BasePort, uPort, u32, cb));
1985	break;
1986	}
1987	return VINF_SUCCESS;
1988	}
1989
1990	#ifdef DEBUG_FIFO_ACCESS
1991
1992	# ifdef IN_RING3
1993	/**
1994	* Handle LFB access.
1995	* @returns VBox status code.
1996	* @param pVM VM handle.
1997	* @param pThis VGA device instance data.
1998	* @param GCPhys The access physical address.
1999	* @param fWriteAccess Read or write access
2000	*/
2001	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2002	{
2003	RT_NOREF(pVM);
2004	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2005	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2006
2007	switch (GCPhysOffset >> 2)
2008	{
2009	case SVGA_FIFO_MIN:
2010	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2011	break;
2012	case SVGA_FIFO_MAX:
2013	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2014	break;
2015	case SVGA_FIFO_NEXT_CMD:
2016	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2017	break;
2018	case SVGA_FIFO_STOP:
2019	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2020	break;
2021	case SVGA_FIFO_CAPABILITIES:
2022	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2023	break;
2024	case SVGA_FIFO_FLAGS:
2025	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2026	break;
2027	case SVGA_FIFO_FENCE:
2028	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2029	break;
2030	case SVGA_FIFO_3D_HWVERSION:
2031	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2032	break;
2033	case SVGA_FIFO_PITCHLOCK:
2034	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2035	break;
2036	case SVGA_FIFO_CURSOR_ON:
2037	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2038	break;
2039	case SVGA_FIFO_CURSOR_X:
2040	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2041	break;
2042	case SVGA_FIFO_CURSOR_Y:
2043	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2044	break;
2045	case SVGA_FIFO_CURSOR_COUNT:
2046	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2047	break;
2048	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2049	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2050	break;
2051	case SVGA_FIFO_RESERVED:
2052	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2053	break;
2054	case SVGA_FIFO_CURSOR_SCREEN_ID:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_DEAD:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_3D_HWVERSION_REVISED:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS_LAST:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_GUEST_3D_HWVERSION:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_FENCE_GOAL:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_BUSY:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	default:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	}
2328
2329	return VINF_EM_RAW_EMULATE_INSTR;
2330	}
2331
2332	/**
2333	* HC access handler for the FIFO.
2334	*
2335	* @returns VINF_SUCCESS if the handler have carried out the operation.
2336	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2337	* @param pVM VM Handle.
2338	* @param pVCpu The cross context CPU structure for the calling EMT.
2339	* @param GCPhys The physical address the guest is writing to.
2340	* @param pvPhys The HC mapping of that address.
2341	* @param pvBuf What the guest is reading/writing.
2342	* @param cbBuf How much it's reading/writing.
2343	* @param enmAccessType The access type.
2344	* @param enmOrigin Who is making the access.
2345	* @param pvUser User argument.
2346	*/
2347	static DECLCALLBACK(VBOXSTRICTRC)
2348	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2349	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2350	{
2351	PVGASTATE pThis = (PVGASTATE)pvUser;
2352	int rc;
2353	Assert(pThis);
2354	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2355	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2356
2357	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2358	if (RT_SUCCESS(rc))
2359	return VINF_PGM_HANDLER_DO_DEFAULT;
2360	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2361	return rc;
2362	}
2363
2364	# endif /* IN_RING3 */
2365	#endif /* DEBUG_FIFO_ACCESS */
2366
2367	#ifdef DEBUG_GMR_ACCESS
2368	# ifdef IN_RING3
2369
2370	/**
2371	* HC access handler for the FIFO.
2372	*
2373	* @returns VINF_SUCCESS if the handler have carried out the operation.
2374	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2375	* @param pVM VM Handle.
2376	* @param pVCpu The cross context CPU structure for the calling EMT.
2377	* @param GCPhys The physical address the guest is writing to.
2378	* @param pvPhys The HC mapping of that address.
2379	* @param pvBuf What the guest is reading/writing.
2380	* @param cbBuf How much it's reading/writing.
2381	* @param enmAccessType The access type.
2382	* @param enmOrigin Who is making the access.
2383	* @param pvUser User argument.
2384	*/
2385	static DECLCALLBACK(VBOXSTRICTRC)
2386	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2387	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2388	{
2389	PVGASTATE pThis = (PVGASTATE)pvUser;
2390	Assert(pThis);
2391	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2392	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2393
2394	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2395
2396	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2397	{
2398	PGMR pGMR = &pSVGAState->paGMR[i];
2399
2400	if (pGMR->numDescriptors)
2401	{
2402	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2403	{
2404	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2405	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2406	{
2407	/*
2408	* Turn off the write handler for this particular page and make it R/W.
2409	* Then return telling the caller to restart the guest instruction.
2410	*/
2411	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2412	AssertRC(rc);
2413	goto end;
2414	}
2415	}
2416	}
2417	}
2418	end:
2419	return VINF_PGM_HANDLER_DO_DEFAULT;
2420	}
2421
2422	/* Callback handler for VMR3ReqCallWaitU */
2423	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2424	{
2425	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2426	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2427	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2428	int rc;
2429
2430	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2431	{
2432	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2433	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2434	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2435	AssertRC(rc);
2436	}
2437	return VINF_SUCCESS;
2438	}
2439
2440	/* Callback handler for VMR3ReqCallWaitU */
2441	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2442	{
2443	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2444	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2445	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2446
2447	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2448	{
2449	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2450	AssertRC(rc);
2451	}
2452	return VINF_SUCCESS;
2453	}
2454
2455	/* Callback handler for VMR3ReqCallWaitU */
2456	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2457	{
2458	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2459
2460	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2461	{
2462	PGMR pGMR = &pSVGAState->paGMR[i];
2463
2464	if (pGMR->numDescriptors)
2465	{
2466	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2467	{
2468	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2469	AssertRC(rc);
2470	}
2471	}
2472	}
2473	return VINF_SUCCESS;
2474	}
2475
2476	# endif /* IN_RING3 */
2477	#endif /* DEBUG_GMR_ACCESS */
2478
2479	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2480
2481	#ifdef IN_RING3
2482
2483
2484	/**
2485	* Common worker for changing the pointer shape.
2486	*
2487	* @param pThis The VGA instance data.
2488	* @param pSVGAState The VMSVGA ring-3 instance data.
2489	* @param fAlpha Whether there is alpha or not.
2490	* @param xHot Hotspot x coordinate.
2491	* @param yHot Hotspot y coordinate.
2492	* @param cx Width.
2493	* @param cy Height.
2494	* @param pbData Heap copy of the cursor data. Consumed.
2495	* @param cbData The size of the data.
2496	*/
2497	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2498	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2499	{
2500	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2501	#ifdef LOG_ENABLED
2502	if (LogIs2Enabled())
2503	{
2504	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2505	if (!fAlpha)
2506	{
2507	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2508	for (uint32_t y = 0; y < cy; y++)
2509	{
2510	Log2(("%3u:", y));
2511	uint8_t const pbLine = &pbData[y cbAndLine];
2512	for (uint32_t x = 0; x < cx; x += 8)
2513	{
2514	uint8_t b = pbLine[x / 8];
2515	char szByte[12];
2516	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2517	szByte[1] = b & 0x40 ? '*' : ' ';
2518	szByte[2] = b & 0x20 ? '*' : ' ';
2519	szByte[3] = b & 0x10 ? '*' : ' ';
2520	szByte[4] = b & 0x08 ? '*' : ' ';
2521	szByte[5] = b & 0x04 ? '*' : ' ';
2522	szByte[6] = b & 0x02 ? '*' : ' ';
2523	szByte[7] = b & 0x01 ? '*' : ' ';
2524	szByte[8] = '\0';
2525	Log2(("%s", szByte));
2526	}
2527	Log2(("\n"));
2528	}
2529	}
2530
2531	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2532	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2533	for (uint32_t y = 0; y < cy; y++)
2534	{
2535	Log2(("%3u:", y));
2536	uint32_t const pu32Line = &pu32Xor[y cx];
2537	for (uint32_t x = 0; x < cx; x++)
2538	Log2((" %08x", pu32Line[x]));
2539	Log2(("\n"));
2540	}
2541	}
2542	#endif
2543
2544	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2545	AssertRC(rc);
2546
2547	if (pSVGAState->Cursor.fActive)
2548	RTMemFree(pSVGAState->Cursor.pData);
2549
2550	pSVGAState->Cursor.fActive = true;
2551	pSVGAState->Cursor.xHotspot = xHot;
2552	pSVGAState->Cursor.yHotspot = yHot;
2553	pSVGAState->Cursor.width = cx;
2554	pSVGAState->Cursor.height = cy;
2555	pSVGAState->Cursor.cbData = cbData;
2556	pSVGAState->Cursor.pData = pbData;
2557	}
2558
2559
2560	/**
2561	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2562	*
2563	* @param pThis The VGA instance data.
2564	* @param pSVGAState The VMSVGA ring-3 instance data.
2565	* @param pCursor The cursor.
2566	* @param pbSrcAndMask The AND mask.
2567	* @param cbSrcAndLine The scanline length of the AND mask.
2568	* @param pbSrcXorMask The XOR mask.
2569	* @param cbSrcXorLine The scanline length of the XOR mask.
2570	*/
2571	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2572	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2573	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2574	{
2575	uint32_t const cx = pCursor->width;
2576	uint32_t const cy = pCursor->height;
2577
2578	/*
2579	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2580	* The AND data uses 8-bit aligned scanlines.
2581	* The XOR data must be starting on a 32-bit boundrary.
2582	*/
2583	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2584	uint32_t cbDstAndMask = cbDstAndLine * cy;
2585	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2586	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2587
2588	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2589	AssertReturnVoid(pbCopy);
2590
2591	/* Convert the AND mask. */
2592	uint8_t *pbDst = pbCopy;
2593	uint8_t const *pbSrc = pbSrcAndMask;
2594	switch (pCursor->andMaskDepth)
2595	{
2596	case 1:
2597	if (cbSrcAndLine == cbDstAndLine)
2598	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2599	else
2600	{
2601	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2602	for (uint32_t y = 0; y < cy; y++)
2603	{
2604	memcpy(pbDst, pbSrc, cbDstAndLine);
2605	pbDst += cbDstAndLine;
2606	pbSrc += cbSrcAndLine;
2607	}
2608	}
2609	break;
2610	/* Should take the XOR mask into account for the multi-bit AND mask. */
2611	case 8:
2612	for (uint32_t y = 0; y < cy; y++)
2613	{
2614	for (uint32_t x = 0; x < cx; )
2615	{
2616	uint8_t bDst = 0;
2617	uint8_t fBit = 1;
2618	do
2619	{
2620	uintptr_t const idxPal = pbSrc[x] * 3;
2621	if ((( pThis->last_palette[idxPal]
2622	\| (pThis->last_palette[idxPal] >> 8)
2623	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2624	bDst \|= fBit;
2625	fBit <<= 1;
2626	x++;
2627	} while (x < cx && (x & 7));
2628	pbDst[(x - 1) / 8] = bDst;
2629	}
2630	pbDst += cbDstAndLine;
2631	pbSrc += cbSrcAndLine;
2632	}
2633	break;
2634	case 15:
2635	for (uint32_t y = 0; y < cy; y++)
2636	{
2637	for (uint32_t x = 0; x < cx; )
2638	{
2639	uint8_t bDst = 0;
2640	uint8_t fBit = 1;
2641	do
2642	{
2643	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2644	bDst \|= fBit;
2645	fBit <<= 1;
2646	x++;
2647	} while (x < cx && (x & 7));
2648	pbDst[(x - 1) / 8] = bDst;
2649	}
2650	pbDst += cbDstAndLine;
2651	pbSrc += cbSrcAndLine;
2652	}
2653	break;
2654	case 16:
2655	for (uint32_t y = 0; y < cy; y++)
2656	{
2657	for (uint32_t x = 0; x < cx; )
2658	{
2659	uint8_t bDst = 0;
2660	uint8_t fBit = 1;
2661	do
2662	{
2663	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2664	bDst \|= fBit;
2665	fBit <<= 1;
2666	x++;
2667	} while (x < cx && (x & 7));
2668	pbDst[(x - 1) / 8] = bDst;
2669	}
2670	pbDst += cbDstAndLine;
2671	pbSrc += cbSrcAndLine;
2672	}
2673	break;
2674	case 24:
2675	for (uint32_t y = 0; y < cy; y++)
2676	{
2677	for (uint32_t x = 0; x < cx; )
2678	{
2679	uint8_t bDst = 0;
2680	uint8_t fBit = 1;
2681	do
2682	{
2683	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2684	bDst \|= fBit;
2685	fBit <<= 1;
2686	x++;
2687	} while (x < cx && (x & 7));
2688	pbDst[(x - 1) / 8] = bDst;
2689	}
2690	pbDst += cbDstAndLine;
2691	pbSrc += cbSrcAndLine;
2692	}
2693	break;
2694	case 32:
2695	for (uint32_t y = 0; y < cy; y++)
2696	{
2697	for (uint32_t x = 0; x < cx; )
2698	{
2699	uint8_t bDst = 0;
2700	uint8_t fBit = 1;
2701	do
2702	{
2703	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2704	bDst \|= fBit;
2705	fBit <<= 1;
2706	x++;
2707	} while (x < cx && (x & 7));
2708	pbDst[(x - 1) / 8] = bDst;
2709	}
2710	pbDst += cbDstAndLine;
2711	pbSrc += cbSrcAndLine;
2712	}
2713	break;
2714	default:
2715	RTMemFree(pbCopy);
2716	AssertFailedReturnVoid();
2717	}
2718
2719	/* Convert the XOR mask. */
2720	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2721	pbSrc = pbSrcXorMask;
2722	switch (pCursor->xorMaskDepth)
2723	{
2724	case 1:
2725	for (uint32_t y = 0; y < cy; y++)
2726	{
2727	for (uint32_t x = 0; x < cx; )
2728	{
2729	/* most significant bit is the left most one. */
2730	uint8_t bSrc = pbSrc[x / 8];
2731	do
2732	{
2733	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2734	bSrc <<= 1;
2735	x++;
2736	} while ((x & 7) && x < cx);
2737	}
2738	pbSrc += cbSrcXorLine;
2739	}
2740	break;
2741	case 8:
2742	for (uint32_t y = 0; y < cy; y++)
2743	{
2744	for (uint32_t x = 0; x < cx; x++)
2745	{
2746	uint32_t u = pThis->last_palette[pbSrc[x]];
2747	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2748	}
2749	pbSrc += cbSrcXorLine;
2750	}
2751	break;
2752	case 15: /* Src: RGB-5-5-5 */
2753	for (uint32_t y = 0; y < cy; y++)
2754	{
2755	for (uint32_t x = 0; x < cx; x++)
2756	{
2757	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2758	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2759	((uValue >> 5) & 0x1f) << 3,
2760	((uValue >> 10) & 0x1f) << 3, 0);
2761	}
2762	pbSrc += cbSrcXorLine;
2763	}
2764	break;
2765	case 16: /* Src: RGB-5-6-5 */
2766	for (uint32_t y = 0; y < cy; y++)
2767	{
2768	for (uint32_t x = 0; x < cx; x++)
2769	{
2770	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2771	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2772	((uValue >> 5) & 0x3f) << 2,
2773	((uValue >> 11) & 0x1f) << 3, 0);
2774	}
2775	pbSrc += cbSrcXorLine;
2776	}
2777	break;
2778	case 24:
2779	for (uint32_t y = 0; y < cy; y++)
2780	{
2781	for (uint32_t x = 0; x < cx; x++)
2782	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2783	pbSrc += cbSrcXorLine;
2784	}
2785	break;
2786	case 32:
2787	for (uint32_t y = 0; y < cy; y++)
2788	{
2789	for (uint32_t x = 0; x < cx; x++)
2790	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2791	pbSrc += cbSrcXorLine;
2792	}
2793	break;
2794	default:
2795	RTMemFree(pbCopy);
2796	AssertFailedReturnVoid();
2797	}
2798
2799	/*
2800	* Pass it to the frontend/whatever.
2801	*/
2802	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2803	}
2804
2805
2806	/**
2807	* Worker for vmsvgaR3FifoThread that handles an external command.
2808	*
2809	* @param pThis VGA device instance data.
2810	*/
2811	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2812	{
2813	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2814	switch (pThis->svga.u8FIFOExtCommand)
2815	{
2816	case VMSVGA_FIFO_EXTCMD_RESET:
2817	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2818	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2819	# ifdef VBOX_WITH_VMSVGA3D
2820	if (pThis->svga.f3DEnabled)
2821	{
2822	/* The 3d subsystem must be reset from the fifo thread. */
2823	vmsvga3dReset(pThis);
2824	}
2825	# endif
2826	break;
2827
2828	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2829	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2830	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2831	# ifdef VBOX_WITH_VMSVGA3D
2832	if (pThis->svga.f3DEnabled)
2833	{
2834	/* The 3d subsystem must be shut down from the fifo thread. */
2835	vmsvga3dTerminate(pThis);
2836	}
2837	# endif
2838	break;
2839
2840	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2841	{
2842	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2843	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2844	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2845	vmsvgaSaveExecFifo(pThis, pSSM);
2846	# ifdef VBOX_WITH_VMSVGA3D
2847	vmsvga3dSaveExec(pThis, pSSM);
2848	# endif
2849	break;
2850	}
2851
2852	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2853	{
2854	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2855	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2856	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2857	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2858	# ifdef VBOX_WITH_VMSVGA3D
2859	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2860	# endif
2861	break;
2862	}
2863
2864	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2865	{
2866	# ifdef VBOX_WITH_VMSVGA3D
2867	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2868	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2869	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2870	# endif
2871	break;
2872	}
2873
2874
2875	default:
2876	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2877	break;
2878	}
2879
2880	/*
2881	* Signal the end of the external command.
2882	*/
2883	pThis->svga.pvFIFOExtCmdParam = NULL;
2884	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2885	ASMMemoryFence(); /* paranoia^2 */
2886	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2887	AssertLogRelRC(rc);
2888	}
2889
2890	/**
2891	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2892	* doing a job on the FIFO thread (even when it's officially suspended).
2893	*
2894	* @returns VBox status code (fully asserted).
2895	* @param pThis VGA device instance data.
2896	* @param uExtCmd The command to execute on the FIFO thread.
2897	* @param pvParam Pointer to command parameters.
2898	* @param cMsWait The time to wait for the command, given in
2899	* milliseconds.
2900	*/
2901	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2902	{
2903	Assert(cMsWait >= RT_MS_1SEC * 5);
2904	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2905	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2906
2907	int rc;
2908	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2909	PDMTHREADSTATE enmState = pThread->enmState;
2910	if (enmState == PDMTHREADSTATE_SUSPENDED)
2911	{
2912	/*
2913	* The thread is suspended, we have to temporarily wake it up so it can
2914	* perform the task.
2915	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2916	*/
2917	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2918	/* Post the request. */
2919	pThis->svga.fFifoExtCommandWakeup = true;
2920	pThis->svga.pvFIFOExtCmdParam = pvParam;
2921	pThis->svga.u8FIFOExtCommand = uExtCmd;
2922	ASMMemoryFence(); /* paranoia^3 */
2923
2924	/* Resume the thread. */
2925	rc = PDMR3ThreadResume(pThread);
2926	AssertLogRelRC(rc);
2927	if (RT_SUCCESS(rc))
2928	{
2929	/* Wait. Take care in case the semaphore was already posted (same as below). */
2930	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2931	if ( rc == VINF_SUCCESS
2932	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2933	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2934	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2935	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2936
2937	/* suspend the thread */
2938	pThis->svga.fFifoExtCommandWakeup = false;
2939	int rc2 = PDMR3ThreadSuspend(pThread);
2940	AssertLogRelRC(rc2);
2941	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2942	rc = rc2;
2943	}
2944	pThis->svga.fFifoExtCommandWakeup = false;
2945	pThis->svga.pvFIFOExtCmdParam = NULL;
2946	}
2947	else if (enmState == PDMTHREADSTATE_RUNNING)
2948	{
2949	/*
2950	* The thread is running, should only happen during reset and vmsvga3dsfc.
2951	* We ASSUME not racing code here, both wrt thread state and ext commands.
2952	*/
2953	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2954	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2955
2956	/* Post the request. */
2957	pThis->svga.pvFIFOExtCmdParam = pvParam;
2958	pThis->svga.u8FIFOExtCommand = uExtCmd;
2959	ASMMemoryFence(); /* paranoia^2 */
2960	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2961	AssertLogRelRC(rc);
2962
2963	/* Wait. Take care in case the semaphore was already posted (same as above). */
2964	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2965	if ( rc == VINF_SUCCESS
2966	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2967	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2968	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2969	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2970
2971	pThis->svga.pvFIFOExtCmdParam = NULL;
2972	}
2973	else
2974	{
2975	/*
2976	* Something is wrong with the thread!
2977	*/
2978	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2979	rc = VERR_INVALID_STATE;
2980	}
2981	return rc;
2982	}
2983
2984
2985	/**
2986	* Marks the FIFO non-busy, notifying any waiting EMTs.
2987	*
2988	* @param pThis The VGA state.
2989	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
2990	* @param offFifoMin The start byte offset of the command FIFO.
2991	*/
2992	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2993	{
2994	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2995	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2996	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2997
2998	/* Wake up any waiting EMTs. */
2999	if (pSVGAState->cBusyDelayedEmts > 0)
3000	{
3001	#ifdef VMSVGA_USE_EMT_HALT_CODE
3002	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3003	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3004	if (idCpu != NIL_VMCPUID)
3005	{
3006	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3007	while (idCpu-- > 0)
3008	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3009	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3010	}
3011	#else
3012	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3013	AssertRC(rc2);
3014	#endif
3015	}
3016	}
3017
3018	/**
3019	* Reads (more) payload into the command buffer.
3020	*
3021	* @returns pbBounceBuf on success
3022	* @retval (void *)1 if the thread was requested to stop.
3023	* @retval NULL on FIFO error.
3024	*
3025	* @param cbPayloadReq The number of bytes of payload requested.
3026	* @param pFIFO The FIFO.
3027	* @param offCurrentCmd The FIFO byte offset of the current command.
3028	* @param offFifoMin The start byte offset of the command FIFO.
3029	* @param offFifoMax The end byte offset of the command FIFO.
3030	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3031	* always sufficient size.
3032	* @param pcbAlreadyRead How much payload we've already read into the bounce
3033	* buffer. (We will NEVER re-read anything.)
3034	* @param pThread The calling PDM thread handle.
3035	* @param pThis The VGA state.
3036	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3037	* statistics collection.
3038	*/
3039	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3040	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3041	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3042	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3043	{
3044	Assert(pbBounceBuf);
3045	Assert(pcbAlreadyRead);
3046	Assert(offFifoMin < offFifoMax);
3047	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3048	Assert(offFifoMax <= pThis->svga.cbFIFO);
3049
3050	/*
3051	* Check if the requested payload size has already been satisfied .
3052	* .
3053	* When called to read more, the caller is responsible for making sure the .
3054	* new command size (cbRequsted) never is smaller than what has already .
3055	* been read.
3056	*/
3057	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3058	if (cbPayloadReq <= cbAlreadyRead)
3059	{
3060	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3061	return pbBounceBuf;
3062	}
3063
3064	/*
3065	* Commands bigger than the fifo buffer are invalid.
3066	*/
3067	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3068	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3069	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3070	NULL);
3071
3072	/*
3073	* Move offCurrentCmd past the command dword.
3074	*/
3075	offCurrentCmd += sizeof(uint32_t);
3076	if (offCurrentCmd >= offFifoMax)
3077	offCurrentCmd = offFifoMin;
3078
3079	/*
3080	* Do we have sufficient payload data available already?
3081	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3082	*/
3083	uint32_t cbAfter, cbBefore;
3084	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3085	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3086	if (offNextCmd >= offCurrentCmd)
3087	{
3088	if (RT_LIKELY(offNextCmd < offFifoMax))
3089	cbAfter = offNextCmd - offCurrentCmd;
3090	else
3091	{
3092	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3093	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3094	offNextCmd, offFifoMin, offFifoMax));
3095	cbAfter = offFifoMax - offCurrentCmd;
3096	}
3097	cbBefore = 0;
3098	}
3099	else
3100	{
3101	cbAfter = offFifoMax - offCurrentCmd;
3102	if (offNextCmd >= offFifoMin)
3103	cbBefore = offNextCmd - offFifoMin;
3104	else
3105	{
3106	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3107	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3108	offNextCmd, offFifoMin, offFifoMax));
3109	cbBefore = 0;
3110	}
3111	}
3112	if (cbAfter + cbBefore < cbPayloadReq)
3113	{
3114	/*
3115	* Insufficient, must wait for it to arrive.
3116	*/
3117	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3118	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3119	for (uint32_t i = 0;; i++)
3120	{
3121	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3122	{
3123	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3124	return (void *)(uintptr_t)1;
3125	}
3126	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3127	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3128
3129	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3130
3131	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3132	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3133	if (offNextCmd >= offCurrentCmd)
3134	{
3135	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3136	cbBefore = 0;
3137	}
3138	else
3139	{
3140	cbAfter = offFifoMax - offCurrentCmd;
3141	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3142	}
3143
3144	if (cbAfter + cbBefore >= cbPayloadReq)
3145	break;
3146	}
3147	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3148	}
3149
3150	/*
3151	* Copy out the memory and update what pcbAlreadyRead points to.
3152	*/
3153	if (cbAfter >= cbPayloadReq)
3154	memcpy(pbBounceBuf + cbAlreadyRead,
3155	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3156	cbPayloadReq - cbAlreadyRead);
3157	else
3158	{
3159	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3160	if (cbAlreadyRead < cbAfter)
3161	{
3162	memcpy(pbBounceBuf + cbAlreadyRead,
3163	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3164	cbAfter - cbAlreadyRead);
3165	cbAlreadyRead = cbAfter;
3166	}
3167	memcpy(pbBounceBuf + cbAlreadyRead,
3168	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3169	cbPayloadReq - cbAlreadyRead);
3170	}
3171	*pcbAlreadyRead = cbPayloadReq;
3172	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3173	return pbBounceBuf;
3174	}
3175
3176	/* The async FIFO handling thread. */
3177	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3178	{
3179	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3180	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3181	int rc;
3182
3183	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3184	return VINF_SUCCESS;
3185
3186	/*
3187	* Special mode where we only execute an external command and the go back
3188	* to being suspended. Currently, all ext cmds ends up here, with the reset
3189	* one also being eligble for runtime execution further down as well.
3190	*/
3191	if (pThis->svga.fFifoExtCommandWakeup)
3192	{
3193	vmsvgaR3FifoHandleExtCmd(pThis);
3194	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3195	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3196	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3197	else
3198	vmsvgaR3FifoHandleExtCmd(pThis);
3199	return VINF_SUCCESS;
3200	}
3201
3202
3203	/*
3204	* Signal the semaphore to make sure we don't wait for 250ms after a
3205	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3206	*/
3207	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3208
3209	/*
3210	* Allocate a bounce buffer for command we get from the FIFO.
3211	* (All code must return via the end of the function to free this buffer.)
3212	*/
3213	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3214	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3215
3216	/*
3217	* Polling/sleep interval config.
3218	*
3219	* We wait for an a short interval if the guest has recently given us work
3220	* to do, but the interval increases the longer we're kept idle. With the
3221	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3222	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3223	* 16 seconds.
3224	*/
3225	RTMSINTERVAL const cMsMinSleep = 16;
3226	RTMSINTERVAL const cMsIncSleep = 2;
3227	RTMSINTERVAL const cMsMaxSleep = 250;
3228	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3229
3230	/*
3231	* The FIFO loop.
3232	*/
3233	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3234	bool fBadOrDisabledFifo = false;
3235	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3236	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3237	{
3238	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3239	/*
3240	* Should service the run loop every so often.
3241	*/
3242	if (pThis->svga.f3DEnabled)
3243	vmsvga3dCocoaServiceRunLoop();
3244	# endif
3245
3246	/*
3247	* Unless there's already work pending, go to sleep for a short while.
3248	* (See polling/sleep interval config above.)
3249	*/
3250	if ( fBadOrDisabledFifo
3251	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3252	{
3253	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3254	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3255	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3256	{
3257	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3258	break;
3259	}
3260	}
3261	else
3262	rc = VINF_SUCCESS;
3263	fBadOrDisabledFifo = false;
3264	if (rc == VERR_TIMEOUT)
3265	{
3266	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3267	{
3268	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3269	continue;
3270	}
3271	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3272
3273	Log(("vmsvgaFIFOLoop: timeout\n"));
3274	}
3275	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3276	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3277	cMsSleep = cMsMinSleep;
3278
3279	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3280	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3281	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3282
3283	/*
3284	* Handle external commands (currently only reset).
3285	*/
3286	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3287	{
3288	vmsvgaR3FifoHandleExtCmd(pThis);
3289	continue;
3290	}
3291
3292	/*
3293	* The device must be enabled and configured.
3294	*/
3295	if ( !pThis->svga.fEnabled
3296	\|\| !pThis->svga.fConfigured)
3297	{
3298	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3299	fBadOrDisabledFifo = true;
3300	continue;
3301	}
3302
3303	/*
3304	* Get and check the min/max values. We ASSUME that they will remain
3305	* unchanged while we process requests. A further ASSUMPTION is that
3306	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3307	* we don't read it back while in the loop.
3308	*/
3309	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3310	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3311	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3312	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3313	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3314	\|\| offFifoMax <= offFifoMin
3315	\|\| offFifoMax > pThis->svga.cbFIFO
3316	\|\| (offFifoMax & 3) != 0
3317	\|\| (offFifoMin & 3) != 0
3318	\|\| offCurrentCmd < offFifoMin
3319	\|\| offCurrentCmd > offFifoMax))
3320	{
3321	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3322	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3323	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3324	fBadOrDisabledFifo = true;
3325	continue;
3326	}
3327	RT_UNTRUSTED_VALIDATED_FENCE();
3328	if (RT_UNLIKELY(offCurrentCmd & 3))
3329	{
3330	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3331	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3332	offCurrentCmd = ~UINT32_C(3);
3333	}
3334
3335	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3336	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3337	*
3338	* Will break out of the switch on failure.
3339	* Will restart and quit the loop if the thread was requested to stop.
3340	*
3341	* @param a_PtrVar Request variable pointer.
3342	* @param a_Type Request typedef (not pointer) for casting.
3343	* @param a_cbPayloadReq How much payload to fetch.
3344	* @remarks Accesses a bunch of variables in the current scope!
3345	*/
3346	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3347	if (1) { \
3348	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3349	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3350	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3351	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3352	} else do {} while (0)
3353	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3354	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3355	* buffer after figuring out the actual command size.
3356	*
3357	* Will break out of the switch on failure.
3358	*
3359	* @param a_PtrVar Request variable pointer.
3360	* @param a_Type Request typedef (not pointer) for casting.
3361	* @param a_cbPayloadReq How much payload to fetch.
3362	* @remarks Accesses a bunch of variables in the current scope!
3363	*/
3364	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3365	if (1) { \
3366	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3367	} else do {} while (0)
3368
3369	/*
3370	* Mark the FIFO as busy.
3371	*/
3372	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3373	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3374	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3375
3376	/*
3377	* Execute all queued FIFO commands.
3378	* Quit if pending external command or changes in the thread state.
3379	*/
3380	bool fDone = false;
3381	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3382	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3383	{
3384	uint32_t cbPayload = 0;
3385	uint32_t u32IrqStatus = 0;
3386
3387	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3388
3389	/* First check any pending actions. */
3390	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3391	{
3392	vmsvgaChangeMode(pThis);
3393	# ifdef VBOX_WITH_VMSVGA3D
3394	if (pThis->svga.p3dState != NULL)
3395	vmsvga3dChangeMode(pThis);
3396	# endif
3397	}
3398
3399	/* Check for pending external commands (reset). */
3400	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3401	break;
3402
3403	/*
3404	* Process the command.
3405	*/
3406	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3407	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3408	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3409	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3410	switch (enmCmdId)
3411	{
3412	case SVGA_CMD_INVALID_CMD:
3413	/* Nothing to do. */
3414	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3415	break;
3416
3417	case SVGA_CMD_FENCE:
3418	{
3419	SVGAFifoCmdFence *pCmdFence;
3420	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3421	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3422	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3423	{
3424	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3425	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3426
3427	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3428	{
3429	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3430	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3431	}
3432	else
3433	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3434	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3435	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3436	{
3437	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3438	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3439	}
3440	}
3441	else
3442	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3443	break;
3444	}
3445	case SVGA_CMD_UPDATE:
3446	case SVGA_CMD_UPDATE_VERBOSE:
3447	{
3448	SVGAFifoCmdUpdate *pUpdate;
3449	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3450	if (enmCmdId == SVGA_CMD_UPDATE)
3451	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3452	else
3453	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3454	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3455	/** @todo Multiple screens? */
3456	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3457	AssertBreak(pScreen);
3458	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3459	break;
3460	}
3461
3462	case SVGA_CMD_DEFINE_CURSOR:
3463	{
3464	/* Followed by bitmap data. */
3465	SVGAFifoCmdDefineCursor *pCursor;
3466	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3467	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3468
3469	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3470	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3471	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3472	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3473	AssertBreak(pCursor->andMaskDepth <= 32);
3474	AssertBreak(pCursor->xorMaskDepth <= 32);
3475	RT_UNTRUSTED_VALIDATED_FENCE();
3476
3477	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3478	uint32_t cbAndMask = cbAndLine * pCursor->height;
3479	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3480	uint32_t cbXorMask = cbXorLine * pCursor->height;
3481	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3482
3483	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3484	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3485	break;
3486	}
3487
3488	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3489	{
3490	/* Followed by bitmap data. */
3491	uint32_t cbCursorShape, cbAndMask;
3492	uint8_t *pCursorCopy;
3493	uint32_t cbCmd;
3494
3495	SVGAFifoCmdDefineAlphaCursor *pCursor;
3496	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3497	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3498
3499	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3500
3501	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3502	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3503	RT_UNTRUSTED_VALIDATED_FENCE();
3504
3505	/* Refetch the bitmap data as well. */
3506	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3507	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3508	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3509
3510	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3511	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3512	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3513	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3514
3515	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3516	AssertBreak(pCursorCopy);
3517
3518	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3519	memset(pCursorCopy, 0xff, cbAndMask);
3520	/* Colour data */
3521	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3522
3523	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3524	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3525	break;
3526	}
3527
3528	case SVGA_CMD_ESCAPE:
3529	{
3530	/* Followed by nsize bytes of data. */
3531	SVGAFifoCmdEscape *pEscape;
3532	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3533	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3534
3535	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3536	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3537	RT_UNTRUSTED_VALIDATED_FENCE();
3538	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3539	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3540
3541	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3542	{
3543	AssertBreak(pEscape->size >= sizeof(uint32_t));
3544	RT_UNTRUSTED_VALIDATED_FENCE();
3545	uint32_t cmd = (uint32_t )(pEscape + 1);
3546	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3547
3548	switch (cmd)
3549	{
3550	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3551	{
3552	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3553	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3554	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3555
3556	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3557	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3558	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3559
3560	RT_NOREF_PV(pVideoCmd);
3561	break;
3562
3563	}
3564
3565	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3566	{
3567	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3568	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3569	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3570	RT_NOREF_PV(pVideoCmd);
3571	break;
3572	}
3573
3574	default:
3575	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3576	break;
3577	}
3578	}
3579	else
3580	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3581
3582	break;
3583	}
3584	# ifdef VBOX_WITH_VMSVGA3D
3585	case SVGA_CMD_DEFINE_GMR2:
3586	{
3587	SVGAFifoCmdDefineGMR2 *pCmd;
3588	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3589	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3590	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3591
3592	/* Validate current GMR id. */
3593	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3594	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3595	RT_UNTRUSTED_VALIDATED_FENCE();
3596
3597	if (!pCmd->numPages)
3598	{
3599	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3600	vmsvgaGMRFree(pThis, pCmd->gmrId);
3601	}
3602	else
3603	{
3604	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3605	if (pGMR->cMaxPages)
3606	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3607
3608	/* Not sure if we should always free the descriptor, but for simplicity
3609	we do so if the new size is smaller than the current. */
3610	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3611	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3612	vmsvgaGMRFree(pThis, pCmd->gmrId);
3613
3614	pGMR->cMaxPages = pCmd->numPages;
3615	/* The rest is done by the REMAP_GMR2 command. */
3616	}
3617	break;
3618	}
3619
3620	case SVGA_CMD_REMAP_GMR2:
3621	{
3622	/* Followed by page descriptors or guest ptr. */
3623	SVGAFifoCmdRemapGMR2 *pCmd;
3624	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3625	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3626
3627	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3628	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3629	RT_UNTRUSTED_VALIDATED_FENCE();
3630
3631	/* Calculate the size of what comes after next and fetch it. */
3632	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3633	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3634	cbCmd += sizeof(SVGAGuestPtr);
3635	else
3636	{
3637	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3638	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3639	{
3640	cbCmd += cbPageDesc;
3641	pCmd->numPages = 1;
3642	}
3643	else
3644	{
3645	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3646	cbCmd += cbPageDesc * pCmd->numPages;
3647	}
3648	}
3649	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3650
3651	/* Validate current GMR id and size. */
3652	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3653	RT_UNTRUSTED_VALIDATED_FENCE();
3654	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3655	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3656	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3657	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3658
3659	if (pCmd->numPages == 0)
3660	break;
3661
3662	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3663	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3664
3665	/*
3666	* We flatten the existing descriptors into a page array, overwrite the
3667	* pages specified in this command and then recompress the descriptor.
3668	*/
3669	/** @todo Optimize the GMR remap algorithm! */
3670
3671	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3672	uint64_t *paNewPage64 = NULL;
3673	if (pGMR->paDesc)
3674	{
3675	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3676
3677	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3678	AssertBreak(paNewPage64);
3679
3680	uint32_t idxPage = 0;
3681	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3682	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3683	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3684	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3685	RT_UNTRUSTED_VALIDATED_FENCE();
3686	}
3687
3688	/* Free the old GMR if present. */
3689	if (pGMR->paDesc)
3690	RTMemFree(pGMR->paDesc);
3691
3692	/* Allocate the maximum amount possible (everything non-continuous) */
3693	PVMSVGAGMRDESCRIPTOR paDescs;
3694	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3695	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3696
3697	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3698	{
3699	/** @todo */
3700	AssertFailed();
3701	pGMR->numDescriptors = 0;
3702	}
3703	else
3704	{
3705	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3706	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3707	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3708
3709	if (paNewPage64)
3710	{
3711	/* Overwrite the old page array with the new page values. */
3712	if (fGCPhys64)
3713	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3714	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3715	else
3716	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3717	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3718
3719	/* Use the updated page array instead of the command data. */
3720	fGCPhys64 = true;
3721	paPages64 = paNewPage64;
3722	pCmd->numPages = cNewTotalPages;
3723	}
3724
3725	/* The first page. */
3726	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3727	* applied to paNewPage64. */
3728	RTGCPHYS GCPhys;
3729	if (fGCPhys64)
3730	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3731	else
3732	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3733	paDescs[0].GCPhys = GCPhys;
3734	paDescs[0].numPages = 1;
3735
3736	/* Subsequent pages. */
3737	uint32_t iDescriptor = 0;
3738	for (uint32_t i = 1; i < pCmd->numPages; i++)
3739	{
3740	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3741	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3742	else
3743	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3744
3745	/* Continuous physical memory? */
3746	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3747	{
3748	Assert(paDescs[iDescriptor].numPages);
3749	paDescs[iDescriptor].numPages++;
3750	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3751	}
3752	else
3753	{
3754	iDescriptor++;
3755	paDescs[iDescriptor].GCPhys = GCPhys;
3756	paDescs[iDescriptor].numPages = 1;
3757	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3758	}
3759	}
3760
3761	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3762	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3763	pGMR->numDescriptors = iDescriptor + 1;
3764	}
3765
3766	if (paNewPage64)
3767	RTMemFree(paNewPage64);
3768
3769	# ifdef DEBUG_GMR_ACCESS
3770	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3771	# endif
3772	break;
3773	}
3774	# endif // VBOX_WITH_VMSVGA3D
3775	case SVGA_CMD_DEFINE_SCREEN:
3776	{
3777	/* The size of this command is specified by the guest and depends on capabilities. */
3778	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
3779
3780	SVGAFifoCmdDefineScreen *pCmd;
3781	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3782	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
3783	RT_UNTRUSTED_VALIDATED_FENCE();
3784
3785	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
3786	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3787	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3788
3789	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
3790	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
3791	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
3792
3793	AssertBreak(pCmd->screen.id < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3794
3795	uint32_t const uWidth = pCmd->screen.size.width;
3796	AssertBreak(0 < uWidth && uWidth <= pThis->svga.u32MaxWidth);
3797
3798	uint32_t const uHeight = pCmd->screen.size.height;
3799	AssertBreak(0 < uHeight && uHeight <= pThis->svga.u32MaxHeight);
3800
3801	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
3802	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
3803	AssertBreak(0 < cbWidth && cbWidth <= cbPitch);
3804
3805	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
3806	AssertBreak(uScreenOffset < pThis->vram_size);
3807
3808	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
3809	AssertBreak(uHeight <= cbVram / cbPitch);
3810	RT_UNTRUSTED_VALIDATED_FENCE();
3811
3812	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screen.id];
3813	pScreen->fDefined = true;
3814	pScreen->fModified = true;
3815	pScreen->fuScreen = pCmd->screen.flags;
3816	pScreen->idScreen = pCmd->screen.id;
3817	pScreen->xOrigin = pCmd->screen.root.x;
3818	pScreen->yOrigin = pCmd->screen.root.y;
3819	pScreen->cWidth = uWidth;
3820	pScreen->cHeight = uHeight;
3821	pScreen->offVRAM = uScreenOffset;
3822	pScreen->cbPitch = cbPitch;
3823	pScreen->cBpp = 32;
3824
3825	pThis->svga.fGFBRegisters = false;
3826	vmsvgaChangeMode(pThis);
3827	break;
3828	}
3829
3830	case SVGA_CMD_DESTROY_SCREEN:
3831	{
3832	SVGAFifoCmdDestroyScreen *pCmd;
3833	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3834	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3835
3836	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3837	AssertBreak(pCmd->screenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3838	RT_UNTRUSTED_VALIDATED_FENCE();
3839
3840	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screenId];
3841	pScreen->fModified = true;
3842	pScreen->fDefined = false;
3843
3844	vmsvgaChangeMode(pThis);
3845	break;
3846	}
3847
3848	case SVGA_CMD_DEFINE_GMRFB:
3849	{
3850	SVGAFifoCmdDefineGMRFB *pCmd;
3851	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3852	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3853
3854	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3855	pSVGAState->GMRFB.ptr = pCmd->ptr;
3856	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3857	pSVGAState->GMRFB.format = pCmd->format;
3858	break;
3859	}
3860
3861	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3862	{
3863	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3864	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3865	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3866
3867	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
3868	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3869
3870	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3871	RT_UNTRUSTED_VALIDATED_FENCE();
3872
3873	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
3874	AssertBreak(pScreen);
3875
3876	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3877	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3878
3879	/* Clip destRect to the screen dimensions. */
3880	SVGASignedRect screenRect;
3881	screenRect.left = 0;
3882	screenRect.top = 0;
3883	screenRect.right = pScreen->cWidth;
3884	screenRect.bottom = pScreen->cHeight;
3885	SVGASignedRect clipRect = pCmd->destRect;
3886	vmsvgaClipRect(&screenRect, &clipRect);
3887	RT_UNTRUSTED_VALIDATED_FENCE();
3888
3889	uint32_t const width = clipRect.right - clipRect.left;
3890	uint32_t const height = clipRect.bottom - clipRect.top;
3891
3892	if ( width == 0
3893	\|\| height == 0)
3894	break; /* Nothing to do. */
3895
3896	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
3897	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
3898
3899	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3900	* Prepare parameters for vmsvgaGMRTransfer.
3901	*/
3902	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3903
3904	/* Destination: host buffer which describes the screen 0 VRAM.
3905	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3906	*/
3907	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3908	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3909	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3910	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3911	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3912	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3913	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3914	+ cbScanline * clipRect.top;
3915	int32_t const cbHstPitch = cbScanline;
3916
3917	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
3918	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
3919	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
3920	+ pSVGAState->GMRFB.bytesPerLine * srcy;
3921	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
3922
3923	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
3924	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
3925	gstPtr, offGst, cbGstPitch,
3926	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
3927	AssertRC(rc);
3928	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
3929	break;
3930	}
3931
3932	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3933	{
3934	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3935	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3936	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3937
3938	/* Note! This can fetch 3d render results as well!! */
3939	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
3940	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3941
3942	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3943	RT_UNTRUSTED_VALIDATED_FENCE();
3944
3945	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
3946	AssertBreak(pScreen);
3947
3948	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
3949	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3950
3951	/* Clip destRect to the screen dimensions. */
3952	SVGASignedRect screenRect;
3953	screenRect.left = 0;
3954	screenRect.top = 0;
3955	screenRect.right = pScreen->cWidth;
3956	screenRect.bottom = pScreen->cHeight;
3957	SVGASignedRect clipRect = pCmd->srcRect;
3958	vmsvgaClipRect(&screenRect, &clipRect);
3959	RT_UNTRUSTED_VALIDATED_FENCE();
3960
3961	uint32_t const width = clipRect.right - clipRect.left;
3962	uint32_t const height = clipRect.bottom - clipRect.top;
3963
3964	if ( width == 0
3965	\|\| height == 0)
3966	break; /* Nothing to do. */
3967
3968	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
3969	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
3970
3971	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3972	* Prepare parameters for vmsvgaGMRTransfer.
3973	*/
3974	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3975
3976	/* Source: host buffer which describes the screen 0 VRAM.
3977	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3978	*/
3979	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3980	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3981	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3982	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3983	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3984	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3985	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3986	+ cbScanline * clipRect.top;
3987	int32_t const cbHstPitch = cbScanline;
3988
3989	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
3990	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
3991	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
3992	+ pSVGAState->GMRFB.bytesPerLine * dsty;
3993	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
3994
3995	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
3996	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
3997	gstPtr, offGst, cbGstPitch,
3998	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
3999	AssertRC(rc);
4000	break;
4001	}
4002
4003	case SVGA_CMD_ANNOTATION_FILL:
4004	{
4005	SVGAFifoCmdAnnotationFill *pCmd;
4006	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4007	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4008
4009	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4010	pSVGAState->colorAnnotation = pCmd->color;
4011	break;
4012	}
4013
4014	case SVGA_CMD_ANNOTATION_COPY:
4015	{
4016	SVGAFifoCmdAnnotationCopy *pCmd;
4017	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4018	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4019
4020	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4021	AssertFailed();
4022	break;
4023	}
4024
4025	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4026
4027	default:
4028	# ifdef VBOX_WITH_VMSVGA3D
4029	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4030	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4031	{
4032	RT_UNTRUSTED_VALIDATED_FENCE();
4033
4034	/* All 3d commands start with a common header, which defines the size of the command. */
4035	SVGA3dCmdHeader *pHdr;
4036	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4037	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4038	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4039	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4040
4041	/**
4042	* Check that the 3D command has at least a_cbMin of payload bytes after the
4043	* header. Will break out of the switch if it doesn't.
4044	*/
4045	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4046	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4047	RT_UNTRUSTED_VALIDATED_FENCE(); \
4048	} while (0)
4049	switch ((int)enmCmdId)
4050	{
4051	case SVGA_3D_CMD_SURFACE_DEFINE:
4052	{
4053	uint32_t cMipLevels;
4054	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4055	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4056	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4057
4058	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4059	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4060	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4061	# ifdef DEBUG_GMR_ACCESS
4062	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4063	# endif
4064	break;
4065	}
4066
4067	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4068	{
4069	uint32_t cMipLevels;
4070	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4071	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4072	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4073
4074	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4075	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4076	pCmd->multisampleCount, pCmd->autogenFilter,
4077	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4078	break;
4079	}
4080
4081	case SVGA_3D_CMD_SURFACE_DESTROY:
4082	{
4083	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4084	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4085	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4086	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4087	break;
4088	}
4089
4090	case SVGA_3D_CMD_SURFACE_COPY:
4091	{
4092	uint32_t cCopyBoxes;
4093	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4094	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4095	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4096
4097	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4098	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4099	break;
4100	}
4101
4102	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4103	{
4104	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4105	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4106	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4107
4108	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4109	break;
4110	}
4111
4112	case SVGA_3D_CMD_SURFACE_DMA:
4113	{
4114	uint32_t cCopyBoxes;
4115	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4116	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4117	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4118
4119	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4120	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4121	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4122	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4123	break;
4124	}
4125
4126	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4127	{
4128	uint32_t cRects;
4129	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4130	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4131	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4132
4133	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4134	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4135	break;
4136	}
4137
4138	case SVGA_3D_CMD_CONTEXT_DEFINE:
4139	{
4140	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4141	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4142	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4143
4144	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4145	break;
4146	}
4147
4148	case SVGA_3D_CMD_CONTEXT_DESTROY:
4149	{
4150	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4151	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4152	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4153
4154	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4155	break;
4156	}
4157
4158	case SVGA_3D_CMD_SETTRANSFORM:
4159	{
4160	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4161	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4162	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4163
4164	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4165	break;
4166	}
4167
4168	case SVGA_3D_CMD_SETZRANGE:
4169	{
4170	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4171	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4172	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4173
4174	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4175	break;
4176	}
4177
4178	case SVGA_3D_CMD_SETRENDERSTATE:
4179	{
4180	uint32_t cRenderStates;
4181	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4182	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4183	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4184
4185	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4186	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4187	break;
4188	}
4189
4190	case SVGA_3D_CMD_SETRENDERTARGET:
4191	{
4192	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4193	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4194	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4195
4196	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4197	break;
4198	}
4199
4200	case SVGA_3D_CMD_SETTEXTURESTATE:
4201	{
4202	uint32_t cTextureStates;
4203	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4204	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4205	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4206
4207	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4208	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4209	break;
4210	}
4211
4212	case SVGA_3D_CMD_SETMATERIAL:
4213	{
4214	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4215	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4216	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4217
4218	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4219	break;
4220	}
4221
4222	case SVGA_3D_CMD_SETLIGHTDATA:
4223	{
4224	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4225	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4226	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4227
4228	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4229	break;
4230	}
4231
4232	case SVGA_3D_CMD_SETLIGHTENABLED:
4233	{
4234	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4235	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4236	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4237
4238	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4239	break;
4240	}
4241
4242	case SVGA_3D_CMD_SETVIEWPORT:
4243	{
4244	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4245	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4246	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4247
4248	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4249	break;
4250	}
4251
4252	case SVGA_3D_CMD_SETCLIPPLANE:
4253	{
4254	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4255	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4256	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4257
4258	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4259	break;
4260	}
4261
4262	case SVGA_3D_CMD_CLEAR:
4263	{
4264	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4265	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4266	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4267
4268	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4269	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4270	break;
4271	}
4272
4273	case SVGA_3D_CMD_PRESENT:
4274	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4275	{
4276	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4277	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4278	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4279	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4280	else
4281	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4282
4283	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4284
4285	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4286	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4287	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4288	break;
4289	}
4290
4291	case SVGA_3D_CMD_SHADER_DEFINE:
4292	{
4293	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4294	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4295	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4296
4297	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4298	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4299	break;
4300	}
4301
4302	case SVGA_3D_CMD_SHADER_DESTROY:
4303	{
4304	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4305	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4306	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4307
4308	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4309	break;
4310	}
4311
4312	case SVGA_3D_CMD_SET_SHADER:
4313	{
4314	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4315	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4316	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4317
4318	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4319	break;
4320	}
4321
4322	case SVGA_3D_CMD_SET_SHADER_CONST:
4323	{
4324	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4325	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4326	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4327
4328	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4329	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4330	break;
4331	}
4332
4333	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4334	{
4335	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4336	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4337	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4338
4339	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4340	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4341	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4342	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4343	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4344
4345	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4346	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4347
4348	RT_UNTRUSTED_VALIDATED_FENCE();
4349
4350	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4351	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4352	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4353
4354	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4355	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4356	pNumRange, cVertexDivisor, pVertexDivisor);
4357	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4358	break;
4359	}
4360
4361	case SVGA_3D_CMD_SETSCISSORRECT:
4362	{
4363	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4364	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4365	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4366
4367	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4368	break;
4369	}
4370
4371	case SVGA_3D_CMD_BEGIN_QUERY:
4372	{
4373	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4374	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4375	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4376
4377	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4378	break;
4379	}
4380
4381	case SVGA_3D_CMD_END_QUERY:
4382	{
4383	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4384	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4385	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4386
4387	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4388	break;
4389	}
4390
4391	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4392	{
4393	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4394	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4396
4397	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4398	break;
4399	}
4400
4401	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4402	{
4403	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4404	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4405	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4406
4407	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4408	break;
4409	}
4410
4411	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4412	/* context id + surface id? */
4413	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4414	break;
4415	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4416	/* context id + surface id? */
4417	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4418	break;
4419
4420	default:
4421	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4422	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4423	break;
4424	}
4425	}
4426	else
4427	# endif // VBOX_WITH_VMSVGA3D
4428	{
4429	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4430	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4431	}
4432	}
4433
4434	/* Go to the next slot */
4435	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4436	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4437	if (offCurrentCmd >= offFifoMax)
4438	{
4439	offCurrentCmd -= offFifoMax - offFifoMin;
4440	Assert(offCurrentCmd >= offFifoMin);
4441	Assert(offCurrentCmd < offFifoMax);
4442	}
4443	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4444	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4445
4446	/*
4447	* Raise IRQ if required. Must enter the critical section here
4448	* before making final decisions here, otherwise cubebench and
4449	* others may end up waiting forever.
4450	*/
4451	if ( u32IrqStatus
4452	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4453	{
4454	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4455	AssertRC(rc2);
4456
4457	/* FIFO progress might trigger an interrupt. */
4458	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4459	{
4460	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4461	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4462	}
4463
4464	/* Unmasked IRQ pending? */
4465	if (pThis->svga.u32IrqMask & u32IrqStatus)
4466	{
4467	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4468	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4469	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4470	}
4471
4472	PDMCritSectLeave(&pThis->CritSect);
4473	}
4474	}
4475
4476	/* If really done, clear the busy flag. */
4477	if (fDone)
4478	{
4479	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4480	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4481	}
4482	}
4483
4484	/*
4485	* Free the bounce buffer. (There are no returns above!)
4486	*/
4487	RTMemFree(pbBounceBuf);
4488
4489	return VINF_SUCCESS;
4490	}
4491
4492	/**
4493	* Free the specified GMR
4494	*
4495	* @param pThis VGA device instance data.
4496	* @param idGMR GMR id
4497	*/
4498	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4499	{
4500	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4501
4502	/* Free the old descriptor if present. */
4503	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4504	if ( pGMR->numDescriptors
4505	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4506	{
4507	# ifdef DEBUG_GMR_ACCESS
4508	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4509	# endif
4510
4511	Assert(pGMR->paDesc);
4512	RTMemFree(pGMR->paDesc);
4513	pGMR->paDesc = NULL;
4514	pGMR->numDescriptors = 0;
4515	pGMR->cbTotal = 0;
4516	pGMR->cMaxPages = 0;
4517	}
4518	Assert(!pGMR->cMaxPages);
4519	Assert(!pGMR->cbTotal);
4520	}
4521
4522	/**
4523	* Copy between a GMR and a host memory buffer.
4524	*
4525	* @returns VBox status code.
4526	* @param pThis VGA device instance data.
4527	* @param enmTransferType Transfer type (read/write)
4528	* @param pbHstBuf Host buffer pointer (valid)
4529	* @param cbHstBuf Size of host buffer (valid)
4530	* @param offHst Host buffer offset of the first scanline
4531	* @param cbHstPitch Destination buffer pitch
4532	* @param gstPtr GMR description
4533	* @param offGst Guest buffer offset of the first scanline
4534	* @param cbGstPitch Guest buffer pitch
4535	* @param cbWidth Width in bytes to copy
4536	* @param cHeight Number of scanllines to copy
4537	*/
4538	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4539	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4540	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4541	uint32_t cbWidth, uint32_t cHeight)
4542	{
4543	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4544	int rc;
4545
4546	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4547	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4548	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4549	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4550	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4551
4552	PGMR pGMR;
4553	uint32_t cbGmr; /* The GMR size in bytes. */
4554	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4555	{
4556	pGMR = NULL;
4557	cbGmr = pThis->vram_size;
4558	}
4559	else
4560	{
4561	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4562	RT_UNTRUSTED_VALIDATED_FENCE();
4563	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4564	cbGmr = pGMR->cbTotal;
4565	}
4566
4567	/*
4568	* GMR
4569	*/
4570	/* Calculate GMR offset of the data to be copied. */
4571	AssertMsgReturn(gstPtr.offset < cbGmr,
4572	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4573	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4574	VERR_INVALID_PARAMETER);
4575	RT_UNTRUSTED_VALIDATED_FENCE();
4576	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4577	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4578	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4579	VERR_INVALID_PARAMETER);
4580	RT_UNTRUSTED_VALIDATED_FENCE();
4581	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4582
4583	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4584	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4585	AssertMsgReturn(cbGmrScanline != 0,
4586	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4587	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4588	VERR_INVALID_PARAMETER);
4589	RT_UNTRUSTED_VALIDATED_FENCE();
4590	AssertMsgReturn(cbWidth <= cbGmrScanline,
4591	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4592	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4593	VERR_INVALID_PARAMETER);
4594	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4595	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4596	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4597	VERR_INVALID_PARAMETER);
4598	RT_UNTRUSTED_VALIDATED_FENCE();
4599
4600	/* How many bytes are available for the data in the GMR. */
4601	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4602
4603	/* How many scanlines would fit into the available data. */
4604	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4605	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4606	if (cbWidth <= cbGmrLastScanline)
4607	++cGmrScanlines;
4608
4609	if (cHeight > cGmrScanlines)
4610	cHeight = cGmrScanlines;
4611
4612	AssertMsgReturn(cHeight > 0,
4613	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4614	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4615	VERR_INVALID_PARAMETER);
4616	RT_UNTRUSTED_VALIDATED_FENCE();
4617
4618	/*
4619	* Host buffer.
4620	*/
4621	AssertMsgReturn(offHst < cbHstBuf,
4622	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4623	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4624	VERR_INVALID_PARAMETER);
4625
4626	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4627	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4628	AssertMsgReturn(cbHstScanline != 0,
4629	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4630	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4631	VERR_INVALID_PARAMETER);
4632	AssertMsgReturn(cbWidth <= cbHstScanline,
4633	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4634	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4635	VERR_INVALID_PARAMETER);
4636	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4637	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4638	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4639	VERR_INVALID_PARAMETER);
4640
4641	/* How many bytes are available for the data in the buffer. */
4642	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4643
4644	/* How many scanlines would fit into the available data. */
4645	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4646	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4647	if (cbWidth <= cbHstLastScanline)
4648	++cHstScanlines;
4649
4650	if (cHeight > cHstScanlines)
4651	cHeight = cHstScanlines;
4652
4653	AssertMsgReturn(cHeight > 0,
4654	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4655	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4656	VERR_INVALID_PARAMETER);
4657
4658	uint8_t *pbHst = pbHstBuf + offHst;
4659
4660	/* Shortcut for the framebuffer. */
4661	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4662	{
4663	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4664
4665	uint8_t const *pbSrc;
4666	int32_t cbSrcPitch;
4667	uint8_t *pbDst;
4668	int32_t cbDstPitch;
4669
4670	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4671	{
4672	pbSrc = pbHst;
4673	cbSrcPitch = cbHstPitch;
4674	pbDst = pbGst;
4675	cbDstPitch = cbGstPitch;
4676	}
4677	else
4678	{
4679	pbSrc = pbGst;
4680	cbSrcPitch = cbGstPitch;
4681	pbDst = pbHst;
4682	cbDstPitch = cbHstPitch;
4683	}
4684
4685	if ( cbWidth == (uint32_t)cbGstPitch
4686	&& cbGstPitch == cbHstPitch)
4687	{
4688	/* Entire scanlines, positive pitch. */
4689	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4690	}
4691	else
4692	{
4693	for (uint32_t i = 0; i < cHeight; ++i)
4694	{
4695	memcpy(pbDst, pbSrc, cbWidth);
4696
4697	pbDst += cbDstPitch;
4698	pbSrc += cbSrcPitch;
4699	}
4700	}
4701	return VINF_SUCCESS;
4702	}
4703
4704	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4705	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4706
4707	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4708	uint32_t iDesc = 0; /* Index in the descriptor array. */
4709	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4710	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4711	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4712	for (uint32_t i = 0; i < cHeight; ++i)
4713	{
4714	uint32_t cbCurrentWidth = cbWidth;
4715	uint32_t offGmrCurrent = offGmrScanline;
4716	uint8_t *pbCurrentHost = pbHstScanline;
4717
4718	/* Find the right descriptor */
4719	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4720	{
4721	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4722	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4723	++iDesc;
4724	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4725	}
4726
4727	while (cbCurrentWidth)
4728	{
4729	uint32_t cbToCopy;
4730
4731	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4732	{
4733	cbToCopy = cbCurrentWidth;
4734	}
4735	else
4736	{
4737	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4738	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4739	}
4740
4741	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4742
4743	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4744
4745	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4746	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4747	else
4748	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4749	AssertRCBreak(rc);
4750
4751	cbCurrentWidth -= cbToCopy;
4752	offGmrCurrent += cbToCopy;
4753	pbCurrentHost += cbToCopy;
4754
4755	/* Go to the next descriptor if there's anything left. */
4756	if (cbCurrentWidth)
4757	{
4758	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4759	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
4760	++iDesc;
4761	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4762	}
4763	}
4764
4765	offGmrScanline += cbGstPitch;
4766	pbHstScanline += cbHstPitch;
4767	}
4768
4769	return VINF_SUCCESS;
4770	}
4771
4772
4773	/** Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0;pSizeDest).
4774	*
4775	* @param pSizeSrc Source surface dimensions.
4776	* @param pSizeDest Destination surface dimensions.
4777	* @param pBox Coordinates to be clipped.
4778	*/
4779	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
4780	const SVGA3dSize *pSizeDest,
4781	SVGA3dCopyBox *pBox)
4782	{
4783	/* Src x, w */
4784	if (pBox->srcx > pSizeSrc->width)
4785	pBox->srcx = pSizeSrc->width;
4786	if (pBox->w > pSizeSrc->width - pBox->srcx)
4787	pBox->w = pSizeSrc->width - pBox->srcx;
4788
4789	/* Src y, h */
4790	if (pBox->srcy > pSizeSrc->height)
4791	pBox->srcy = pSizeSrc->height;
4792	if (pBox->h > pSizeSrc->height - pBox->srcy)
4793	pBox->h = pSizeSrc->height - pBox->srcy;
4794
4795	/* Src z, d */
4796	if (pBox->srcz > pSizeSrc->depth)
4797	pBox->srcz = pSizeSrc->depth;
4798	if (pBox->d > pSizeSrc->depth - pBox->srcz)
4799	pBox->d = pSizeSrc->depth - pBox->srcz;
4800
4801	/* Dest x, w */
4802	if (pBox->x > pSizeDest->width)
4803	pBox->x = pSizeDest->width;
4804	if (pBox->w > pSizeDest->width - pBox->x)
4805	pBox->w = pSizeDest->width - pBox->x;
4806
4807	/* Dest y, h */
4808	if (pBox->y > pSizeDest->height)
4809	pBox->y = pSizeDest->height;
4810	if (pBox->h > pSizeDest->height - pBox->y)
4811	pBox->h = pSizeDest->height - pBox->y;
4812
4813	/* Dest z, d */
4814	if (pBox->z > pSizeDest->depth)
4815	pBox->z = pSizeDest->depth;
4816	if (pBox->d > pSizeDest->depth - pBox->z)
4817	pBox->d = pSizeDest->depth - pBox->z;
4818	}
4819
4820	/** Unsigned coordinates in pBox. Clip to [0; pSize).
4821	*
4822	* @param pSize Source surface dimensions.
4823	* @param pBox Coordinates to be clipped.
4824	*/
4825	void vmsvgaClipBox(const SVGA3dSize *pSize,
4826	SVGA3dBox *pBox)
4827	{
4828	/* x, w */
4829	if (pBox->x > pSize->width)
4830	pBox->x = pSize->width;
4831	if (pBox->w > pSize->width - pBox->x)
4832	pBox->w = pSize->width - pBox->x;
4833
4834	/* y, h */
4835	if (pBox->y > pSize->height)
4836	pBox->y = pSize->height;
4837	if (pBox->h > pSize->height - pBox->y)
4838	pBox->h = pSize->height - pBox->y;
4839
4840	/* z, d */
4841	if (pBox->z > pSize->depth)
4842	pBox->z = pSize->depth;
4843	if (pBox->d > pSize->depth - pBox->z)
4844	pBox->d = pSize->depth - pBox->z;
4845	}
4846
4847	/** Clip.
4848	*
4849	* @param pBound Bounding rectangle.
4850	* @param pRect Rectangle to be clipped.
4851	*/
4852	void vmsvgaClipRect(SVGASignedRect const *pBound,
4853	SVGASignedRect *pRect)
4854	{
4855	int32_t left;
4856	int32_t top;
4857	int32_t right;
4858	int32_t bottom;
4859
4860	/* Right order. */
4861	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
4862	if (pRect->left < pRect->right)
4863	{
4864	left = pRect->left;
4865	right = pRect->right;
4866	}
4867	else
4868	{
4869	left = pRect->right;
4870	right = pRect->left;
4871	}
4872	if (pRect->top < pRect->bottom)
4873	{
4874	top = pRect->top;
4875	bottom = pRect->bottom;
4876	}
4877	else
4878	{
4879	top = pRect->bottom;
4880	bottom = pRect->top;
4881	}
4882
4883	if (left < pBound->left)
4884	left = pBound->left;
4885	if (right < pBound->left)
4886	right = pBound->left;
4887
4888	if (left > pBound->right)
4889	left = pBound->right;
4890	if (right > pBound->right)
4891	right = pBound->right;
4892
4893	if (top < pBound->top)
4894	top = pBound->top;
4895	if (bottom < pBound->top)
4896	bottom = pBound->top;
4897
4898	if (top > pBound->bottom)
4899	top = pBound->bottom;
4900	if (bottom > pBound->bottom)
4901	bottom = pBound->bottom;
4902
4903	pRect->left = left;
4904	pRect->right = right;
4905	pRect->top = top;
4906	pRect->bottom = bottom;
4907	}
4908
4909	/**
4910	* Unblock the FIFO I/O thread so it can respond to a state change.
4911	*
4912	* @returns VBox status code.
4913	* @param pDevIns The VGA device instance.
4914	* @param pThread The send thread.
4915	*/
4916	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4917	{
4918	RT_NOREF(pDevIns);
4919	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4920	Log(("vmsvgaFIFOLoopWakeUp\n"));
4921	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4922	}
4923
4924	/**
4925	* Enables or disables dirty page tracking for the framebuffer
4926	*
4927	* @param pThis VGA device instance data.
4928	* @param fTraces Enable/disable traces
4929	*/
4930	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4931	{
4932	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4933	&& !fTraces)
4934	{
4935	//Assert(pThis->svga.fTraces);
4936	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4937	return;
4938	}
4939
4940	pThis->svga.fTraces = fTraces;
4941	if (pThis->svga.fTraces)
4942	{
4943	unsigned cbFrameBuffer = pThis->vram_size;
4944
4945	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4946	/** @todo How this works with screens? */
4947	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4948	{
4949	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4950	Assert(pThis->svga.cbScanline);
4951	#endif
4952	/* Hardware enabled; return real framebuffer size .*/
4953	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4954	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4955	}
4956
4957	if (!pThis->svga.fVRAMTracking)
4958	{
4959	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4960	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4961	pThis->svga.fVRAMTracking = true;
4962	}
4963	}
4964	else
4965	{
4966	if (pThis->svga.fVRAMTracking)
4967	{
4968	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4969	vgaR3UnregisterVRAMHandler(pThis);
4970	pThis->svga.fVRAMTracking = false;
4971	}
4972	}
4973	}
4974
4975	/**
4976	* @callback_method_impl{FNPCIIOREGIONMAP}
4977	*/
4978	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4979	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4980	{
4981	int rc;
4982	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4983
4984	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4985	if (enmType == PCI_ADDRESS_SPACE_IO)
4986	{
4987	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
4988	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4989	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
4990	if (RT_FAILURE(rc))
4991	return rc;
4992	if (pThis->fR0Enabled)
4993	{
4994	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4995	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
4996	if (RT_FAILURE(rc))
4997	return rc;
4998	}
4999	if (pThis->fGCEnabled)
5000	{
5001	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5002	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5003	if (RT_FAILURE(rc))
5004	return rc;
5005	}
5006
5007	pThis->svga.BasePort = GCPhysAddress;
5008	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5009	}
5010	else
5011	{
5012	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5013	if (GCPhysAddress != NIL_RTGCPHYS)
5014	{
5015	/*
5016	* Mapping the FIFO RAM.
5017	*/
5018	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5019	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5020	AssertRC(rc);
5021
5022	# ifdef DEBUG_FIFO_ACCESS
5023	if (RT_SUCCESS(rc))
5024	{
5025	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
5026	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5027	"VMSVGA FIFO");
5028	AssertRC(rc);
5029	}
5030	# endif
5031	if (RT_SUCCESS(rc))
5032	{
5033	pThis->svga.GCPhysFIFO = GCPhysAddress;
5034	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5035	}
5036	}
5037	else
5038	{
5039	Assert(pThis->svga.GCPhysFIFO);
5040	# ifdef DEBUG_FIFO_ACCESS
5041	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5042	AssertRC(rc);
5043	# endif
5044	pThis->svga.GCPhysFIFO = 0;
5045	}
5046
5047	}
5048	return VINF_SUCCESS;
5049	}
5050
5051	# ifdef VBOX_WITH_VMSVGA3D
5052
5053	/**
5054	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5055	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5056	*
5057	* @param pThis The VGA device instance data.
5058	* @param sid Either UINT32_MAX or the ID of a specific
5059	* surface. If UINT32_MAX is used, all surfaces
5060	* are processed.
5061	*/
5062	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5063	{
5064	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5065	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5066	}
5067
5068
5069	/**
5070	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5071	*/
5072	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5073	{
5074	/* There might be a specific surface ID at the start of the
5075	arguments, if not show all surfaces. */
5076	uint32_t sid = UINT32_MAX;
5077	if (pszArgs)
5078	pszArgs = RTStrStripL(pszArgs);
5079	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5080	sid = RTStrToUInt32(pszArgs);
5081
5082	/* Verbose or terse display, we default to verbose. */
5083	bool fVerbose = true;
5084	if (RTStrIStr(pszArgs, "terse"))
5085	fVerbose = false;
5086
5087	/* The size of the ascii art (x direction, y is 3/4 of x). */
5088	uint32_t cxAscii = 80;
5089	if (RTStrIStr(pszArgs, "gigantic"))
5090	cxAscii = 300;
5091	else if (RTStrIStr(pszArgs, "huge"))
5092	cxAscii = 180;
5093	else if (RTStrIStr(pszArgs, "big"))
5094	cxAscii = 132;
5095	else if (RTStrIStr(pszArgs, "normal"))
5096	cxAscii = 80;
5097	else if (RTStrIStr(pszArgs, "medium"))
5098	cxAscii = 64;
5099	else if (RTStrIStr(pszArgs, "small"))
5100	cxAscii = 48;
5101	else if (RTStrIStr(pszArgs, "tiny"))
5102	cxAscii = 24;
5103
5104	/* Y invert the image when producing the ASCII art. */
5105	bool fInvY = false;
5106	if (RTStrIStr(pszArgs, "invy"))
5107	fInvY = true;
5108
5109	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5110	}
5111
5112
5113	/**
5114	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5115	*/
5116	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5117	{
5118	/* pszArg = "sid[>dir]"
5119	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5120	*/
5121	char *pszBitmapPath = NULL;
5122	uint32_t sid = UINT32_MAX;
5123	if (pszArgs)
5124	pszArgs = RTStrStripL(pszArgs);
5125	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5126	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5127	if ( pszBitmapPath
5128	&& *pszBitmapPath == '>')
5129	++pszBitmapPath;
5130
5131	const bool fVerbose = true;
5132	const uint32_t cxAscii = 0; /* No ASCII */
5133	const bool fInvY = false; /* Do not invert. */
5134	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5135	}
5136
5137
5138	/**
5139	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5140	*/
5141	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5142	{
5143	/* There might be a specific surface ID at the start of the
5144	arguments, if not show all contexts. */
5145	uint32_t sid = UINT32_MAX;
5146	if (pszArgs)
5147	pszArgs = RTStrStripL(pszArgs);
5148	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5149	sid = RTStrToUInt32(pszArgs);
5150
5151	/* Verbose or terse display, we default to verbose. */
5152	bool fVerbose = true;
5153	if (RTStrIStr(pszArgs, "terse"))
5154	fVerbose = false;
5155
5156	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5157	}
5158
5159	# endif /* VBOX_WITH_VMSVGA3D */
5160
5161	/**
5162	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5163	*/
5164	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5165	{
5166	RT_NOREF(pszArgs);
5167	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5168	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5169
5170	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5171	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5172	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5173	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5174	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5175	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5176	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5177	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5178	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5179	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5180	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5181	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5182	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5183	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5184	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5185	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5186	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5187	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5188	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5189	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5190	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5191	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5192
5193	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5194	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5195	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5196	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5197
5198	# ifdef VBOX_WITH_VMSVGA3D
5199	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5200	pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
5201	if (pThis->svga.u64HostWindowId != 0)
5202	vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
5203	# endif
5204	}
5205
5206	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5207	*/
5208	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5209	{
5210	RT_NOREF(uPass);
5211
5212	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5213	int rc;
5214
5215	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5216	{
5217	uint32_t cScreens = 0;
5218	rc = SSMR3GetU32(pSSM, &cScreens);
5219	AssertRCReturn(rc, rc);
5220	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5221	("cScreens=%#x\n", cScreens),
5222	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5223
5224	for (uint32_t i = 0; i < cScreens; ++i)
5225	{
5226	VMSVGASCREENOBJECT screen;
5227	RT_ZERO(screen);
5228
5229	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5230	AssertLogRelRCReturn(rc, rc);
5231
5232	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5233	{
5234	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5235	*pScreen = screen;
5236	pScreen->fModified = true;
5237	}
5238	else
5239	{
5240	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5241	}
5242	}
5243	}
5244	else
5245	{
5246	/* Try to setup at least the first screen. */
5247	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5248	pScreen->fDefined = true;
5249	pScreen->fModified = true;
5250	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5251	pScreen->idScreen = 0;
5252	pScreen->xOrigin = 0;
5253	pScreen->yOrigin = 0;
5254	pScreen->offVRAM = pThis->svga.uScreenOffset;
5255	pScreen->cbPitch = pThis->svga.cbScanline;
5256	pScreen->cWidth = pThis->svga.uWidth;
5257	pScreen->cHeight = pThis->svga.uHeight;
5258	pScreen->cBpp = pThis->svga.uBpp;
5259	}
5260
5261	return VINF_SUCCESS;
5262	}
5263
5264	/**
5265	* @copydoc FNSSMDEVLOADEXEC
5266	*/
5267	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5268	{
5269	RT_NOREF(uPass);
5270	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5271	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5272	int rc;
5273
5274	/* Load our part of the VGAState */
5275	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5276	AssertRCReturn(rc, rc);
5277
5278	/* Load the VGA framebuffer. */
5279	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5280	uint32_t cbVgaFramebuffer = _32K;
5281	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5282	{
5283	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5284	AssertRCReturn(rc, rc);
5285	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5286	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5287	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5288	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5289	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5290	}
5291	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5292	AssertRCReturn(rc, rc);
5293	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5294	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5295	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5296	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5297
5298	/* Load the VMSVGA state. */
5299	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5300	AssertRCReturn(rc, rc);
5301
5302	/* Load the active cursor bitmaps. */
5303	if (pSVGAState->Cursor.fActive)
5304	{
5305	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5306	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5307
5308	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5309	AssertRCReturn(rc, rc);
5310	}
5311
5312	/* Load the GMR state. */
5313	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5314	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5315	{
5316	rc = SSMR3GetU32(pSSM, &cGMR);
5317	AssertRCReturn(rc, rc);
5318	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5319	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5320	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5321	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5322	}
5323
5324	if (pThis->svga.cGMR != cGMR)
5325	{
5326	/* Reallocate GMR array. */
5327	Assert(pSVGAState->paGMR != NULL);
5328	RTMemFree(pSVGAState->paGMR);
5329	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5330	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5331	pThis->svga.cGMR = cGMR;
5332	}
5333
5334	for (uint32_t i = 0; i < cGMR; ++i)
5335	{
5336	PGMR pGMR = &pSVGAState->paGMR[i];
5337
5338	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5339	AssertRCReturn(rc, rc);
5340
5341	if (pGMR->numDescriptors)
5342	{
5343	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5344	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5345	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5346
5347	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5348	{
5349	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5350	AssertRCReturn(rc, rc);
5351	}
5352	}
5353	}
5354
5355	# ifdef VBOX_WITH_VMSVGA3D
5356	if (pThis->svga.f3DEnabled)
5357	{
5358	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5359	vmsvga3dPowerOn(pThis);
5360	# endif
5361
5362	VMSVGA_STATE_LOAD LoadState;
5363	LoadState.pSSM = pSSM;
5364	LoadState.uVersion = uVersion;
5365	LoadState.uPass = uPass;
5366	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5367	AssertLogRelRCReturn(rc, rc);
5368	}
5369	# endif
5370
5371	return VINF_SUCCESS;
5372	}
5373
5374	/**
5375	* Reinit the video mode after the state has been loaded.
5376	*/
5377	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5378	{
5379	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5380	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5381
5382	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5383
5384	/* Set the active cursor. */
5385	if (pSVGAState->Cursor.fActive)
5386	{
5387	int rc;
5388
5389	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5390	true,
5391	true,
5392	pSVGAState->Cursor.xHotspot,
5393	pSVGAState->Cursor.yHotspot,
5394	pSVGAState->Cursor.width,
5395	pSVGAState->Cursor.height,
5396	pSVGAState->Cursor.pData);
5397	AssertRC(rc);
5398	}
5399	return VINF_SUCCESS;
5400	}
5401
5402	/**
5403	* Portion of SVGA state which must be saved in the FIFO thread.
5404	*/
5405	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5406	{
5407	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5408	int rc;
5409
5410	/* Save the screen objects. */
5411	/* Count defined screen object. */
5412	uint32_t cScreens = 0;
5413	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5414	{
5415	if (pSVGAState->aScreens[i].fDefined)
5416	++cScreens;
5417	}
5418
5419	rc = SSMR3PutU32(pSSM, cScreens);
5420	AssertLogRelRCReturn(rc, rc);
5421
5422	for (uint32_t i = 0; i < cScreens; ++i)
5423	{
5424	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5425
5426	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5427	AssertLogRelRCReturn(rc, rc);
5428	}
5429	return VINF_SUCCESS;
5430	}
5431
5432	/**
5433	* @copydoc FNSSMDEVSAVEEXEC
5434	*/
5435	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5436	{
5437	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5438	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5439	int rc;
5440
5441	/* Save our part of the VGAState */
5442	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5443	AssertLogRelRCReturn(rc, rc);
5444
5445	/* Save the framebuffer backup. */
5446	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5447	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5448	AssertLogRelRCReturn(rc, rc);
5449
5450	/* Save the VMSVGA state. */
5451	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5452	AssertLogRelRCReturn(rc, rc);
5453
5454	/* Save the active cursor bitmaps. */
5455	if (pSVGAState->Cursor.fActive)
5456	{
5457	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5458	AssertLogRelRCReturn(rc, rc);
5459	}
5460
5461	/* Save the GMR state */
5462	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5463	AssertLogRelRCReturn(rc, rc);
5464	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5465	{
5466	PGMR pGMR = &pSVGAState->paGMR[i];
5467
5468	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5469	AssertLogRelRCReturn(rc, rc);
5470
5471	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5472	{
5473	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5474	AssertLogRelRCReturn(rc, rc);
5475	}
5476	}
5477
5478	# ifdef VBOX_WITH_VMSVGA3D
5479	/*
5480	* Must save the 3d state in the FIFO thread.
5481	*/
5482	if (pThis->svga.f3DEnabled)
5483	{
5484	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5485	AssertLogRelRCReturn(rc, rc);
5486	}
5487	# endif
5488	return VINF_SUCCESS;
5489	}
5490
5491	/**
5492	* Destructor for PVMSVGAR3STATE structure.
5493	*
5494	* @param pThis The VGA instance.
5495	* @param pSVGAState Pointer to the structure. It is not deallocated.
5496	*/
5497	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5498	{
5499	#ifndef VMSVGA_USE_EMT_HALT_CODE
5500	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5501	{
5502	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5503	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5504	}
5505	#endif
5506
5507	if (pSVGAState->Cursor.fActive)
5508	{
5509	RTMemFree(pSVGAState->Cursor.pData);
5510	pSVGAState->Cursor.pData = NULL;
5511	pSVGAState->Cursor.fActive = false;
5512	}
5513
5514	if (pSVGAState->paGMR)
5515	{
5516	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5517	if (pSVGAState->paGMR[i].paDesc)
5518	RTMemFree(pSVGAState->paGMR[i].paDesc);
5519
5520	RTMemFree(pSVGAState->paGMR);
5521	pSVGAState->paGMR = NULL;
5522	}
5523	}
5524
5525	/**
5526	* Constructor for PVMSVGAR3STATE structure.
5527	*
5528	* @returns VBox status code.
5529	* @param pThis The VGA instance.
5530	* @param pSVGAState Pointer to the structure. It is already allocated.
5531	*/
5532	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5533	{
5534	int rc = VINF_SUCCESS;
5535	RT_ZERO(*pSVGAState);
5536
5537	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5538	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5539
5540	#ifndef VMSVGA_USE_EMT_HALT_CODE
5541	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5542	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5543	AssertRCReturn(rc, rc);
5544	#endif
5545
5546	return rc;
5547	}
5548
5549	/**
5550	* Resets the SVGA hardware state
5551	*
5552	* @returns VBox status code.
5553	* @param pDevIns The device instance.
5554	*/
5555	int vmsvgaReset(PPDMDEVINS pDevIns)
5556	{
5557	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5558	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5559
5560	/* Reset before init? */
5561	if (!pSVGAState)
5562	return VINF_SUCCESS;
5563
5564	Log(("vmsvgaReset\n"));
5565
5566	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5567	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5568	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5569
5570	/* Reset other stuff. */
5571	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5572	RT_ZERO(pThis->svga.au32ScratchRegion);
5573
5574	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5575	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5576
5577	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5578
5579	/* Register caps. */
5580	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5581	# ifdef VBOX_WITH_VMSVGA3D
5582	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5583	# endif
5584
5585	/* Setup FIFO capabilities. */
5586	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5587
5588	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5589	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5590
5591	/* VRAM tracking is enabled by default during bootup. */
5592	pThis->svga.fVRAMTracking = true;
5593	pThis->svga.fEnabled = false;
5594
5595	/* Invalidate current settings. */
5596	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5597	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5598	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5599	pThis->svga.cbScanline = 0;
5600
5601	return rc;
5602	}
5603
5604	/**
5605	* Cleans up the SVGA hardware state
5606	*
5607	* @returns VBox status code.
5608	* @param pDevIns The device instance.
5609	*/
5610	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5611	{
5612	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5613
5614	/*
5615	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5616	*/
5617	if (pThis->svga.pFIFOIOThread)
5618	{
5619	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5620	AssertLogRelRC(rc);
5621
5622	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5623	AssertLogRelRC(rc);
5624	pThis->svga.pFIFOIOThread = NULL;
5625	}
5626
5627	/*
5628	* Destroy the special SVGA state.
5629	*/
5630	if (pThis->svga.pSvgaR3State)
5631	{
5632	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5633
5634	RTMemFree(pThis->svga.pSvgaR3State);
5635	pThis->svga.pSvgaR3State = NULL;
5636	}
5637
5638	/*
5639	* Free our resources residing in the VGA state.
5640	*/
5641	if (pThis->svga.pbVgaFrameBufferR3)
5642	{
5643	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5644	pThis->svga.pbVgaFrameBufferR3 = NULL;
5645	}
5646	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5647	{
5648	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5649	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5650	}
5651	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5652	{
5653	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5654	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5655	}
5656
5657	return VINF_SUCCESS;
5658	}
5659
5660	/**
5661	* Initialize the SVGA hardware state
5662	*
5663	* @returns VBox status code.
5664	* @param pDevIns The device instance.
5665	*/
5666	int vmsvgaInit(PPDMDEVINS pDevIns)
5667	{
5668	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5669	PVMSVGAR3STATE pSVGAState;
5670	PVM pVM = PDMDevHlpGetVM(pDevIns);
5671	int rc;
5672
5673	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5674	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5675
5676	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5677
5678	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5679	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5680	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5681
5682	/* Create event semaphore. */
5683	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5684
5685	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5686	if (RT_FAILURE(rc))
5687	{
5688	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5689	return rc;
5690	}
5691
5692	/* Create event semaphore. */
5693	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5694	if (RT_FAILURE(rc))
5695	{
5696	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5697	return rc;
5698	}
5699
5700	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5701	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5702
5703	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5704	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5705
5706	pSVGAState = pThis->svga.pSvgaR3State;
5707
5708	/* Register caps. */
5709	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5710	# ifdef VBOX_WITH_VMSVGA3D
5711	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5712	# endif
5713
5714	/* Setup FIFO capabilities. */
5715	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5716
5717	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5718	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5719
5720	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5721	# ifdef VBOX_WITH_VMSVGA3D
5722	if (pThis->svga.f3DEnabled)
5723	{
5724	rc = vmsvga3dInit(pThis);
5725	if (RT_FAILURE(rc))
5726	{
5727	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5728	pThis->svga.f3DEnabled = false;
5729	}
5730	}
5731	# endif
5732	/* VRAM tracking is enabled by default during bootup. */
5733	pThis->svga.fVRAMTracking = true;
5734
5735	/* Invalidate current settings. */
5736	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5737	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5738	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5739	pThis->svga.cbScanline = 0;
5740
5741	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5742	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5743	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5744	{
5745	pThis->svga.u32MaxWidth -= 256;
5746	pThis->svga.u32MaxHeight -= 256;
5747	}
5748	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5749
5750	# ifdef DEBUG_GMR_ACCESS
5751	/* Register the GMR access handler type. */
5752	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5753	vmsvgaR3GMRAccessHandler,
5754	NULL, NULL, NULL,
5755	NULL, NULL, NULL,
5756	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5757	AssertRCReturn(rc, rc);
5758	# endif
5759	# ifdef DEBUG_FIFO_ACCESS
5760	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5761	vmsvgaR3FIFOAccessHandler,
5762	NULL, NULL, NULL,
5763	NULL, NULL, NULL,
5764	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5765	AssertRCReturn(rc, rc);
5766	#endif
5767
5768	/* Create the async IO thread. */
5769	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5770	RTTHREADTYPE_IO, "VMSVGA FIFO");
5771	if (RT_FAILURE(rc))
5772	{
5773	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5774	return rc;
5775	}
5776
5777	/*
5778	* Statistics.
5779	*/
5780	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5781	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5782	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5783	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5784	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5785	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5786	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5787	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5788	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5789	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5790	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5791	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5792	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5793	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5794	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5795	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5796	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5797	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5798	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5799	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5800	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5801	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5802	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5803	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5804	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5805	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5806	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5807	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5808	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5809	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5810	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5811	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5812	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5813	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5814	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5815	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5816	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5817	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5818	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5819	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5820	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5821	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5822	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5823	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5824	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5825	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5826	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5827	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5828	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5829	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5830	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5831	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5832	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5833	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5834	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5835	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5836
5837	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5838	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5839	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5840	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5841	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5842	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5843	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5844	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5845	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5846	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5847	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5848	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5849	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5850	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5851	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5852	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5853	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5854	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5855	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5856	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5857	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5858	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5859	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5860	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5861	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5862	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5863	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5864	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5865	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5866	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5867	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5868	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5869
5870	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5871	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5872	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5873	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5874	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5875	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5876	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5877	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5878	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5879	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5880	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5881	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5882	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5883	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5884	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5885	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5886	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5887	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5888	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5889	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5890	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5891	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5892	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5893	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5894	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5895	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5896	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5897	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5898	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5899	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5900	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5901	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5902	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5903	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5904	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5905	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5906	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5907	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5908	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5909	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5910	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5911	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5912	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5913	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5914	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5915	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5916	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5917	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5918	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5919
5920	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5921	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5922	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5923	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5924	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5925	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5926	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5927
5928	/*
5929	* Info handlers.
5930	*/
5931	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5932	# ifdef VBOX_WITH_VMSVGA3D
5933	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5934	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5935	"VMSVGA 3d surface details. "
5936	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5937	vmsvgaR3Info3dSurface);
5938	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
5939	"VMSVGA 3d surface details and bitmap: "
5940	"sid[>dir]",
5941	vmsvgaR3Info3dSurfaceBmp);
5942	# endif
5943
5944	return VINF_SUCCESS;
5945	}
5946
5947	# ifdef VBOX_WITH_VMSVGA3D
5948	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5949	static const char * const g_apszVmSvgaDevCapNames[] =
5950	{
5951	"x3D", /* = 0 */
5952	"xMAX_LIGHTS",
5953	"xMAX_TEXTURES",
5954	"xMAX_CLIP_PLANES",
5955	"xVERTEX_SHADER_VERSION",
5956	"xVERTEX_SHADER",
5957	"xFRAGMENT_SHADER_VERSION",
5958	"xFRAGMENT_SHADER",
5959	"xMAX_RENDER_TARGETS",
5960	"xS23E8_TEXTURES",
5961	"xS10E5_TEXTURES",
5962	"xMAX_FIXED_VERTEXBLEND",
5963	"xD16_BUFFER_FORMAT",
5964	"xD24S8_BUFFER_FORMAT",
5965	"xD24X8_BUFFER_FORMAT",
5966	"xQUERY_TYPES",
5967	"xTEXTURE_GRADIENT_SAMPLING",
5968	"rMAX_POINT_SIZE",
5969	"xMAX_SHADER_TEXTURES",
5970	"xMAX_TEXTURE_WIDTH",
5971	"xMAX_TEXTURE_HEIGHT",
5972	"xMAX_VOLUME_EXTENT",
5973	"xMAX_TEXTURE_REPEAT",
5974	"xMAX_TEXTURE_ASPECT_RATIO",
5975	"xMAX_TEXTURE_ANISOTROPY",
5976	"xMAX_PRIMITIVE_COUNT",
5977	"xMAX_VERTEX_INDEX",
5978	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5979	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5980	"xMAX_VERTEX_SHADER_TEMPS",
5981	"xMAX_FRAGMENT_SHADER_TEMPS",
5982	"xTEXTURE_OPS",
5983	"xSURFACEFMT_X8R8G8B8",
5984	"xSURFACEFMT_A8R8G8B8",
5985	"xSURFACEFMT_A2R10G10B10",
5986	"xSURFACEFMT_X1R5G5B5",
5987	"xSURFACEFMT_A1R5G5B5",
5988	"xSURFACEFMT_A4R4G4B4",
5989	"xSURFACEFMT_R5G6B5",
5990	"xSURFACEFMT_LUMINANCE16",
5991	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5992	"xSURFACEFMT_ALPHA8",
5993	"xSURFACEFMT_LUMINANCE8",
5994	"xSURFACEFMT_Z_D16",
5995	"xSURFACEFMT_Z_D24S8",
5996	"xSURFACEFMT_Z_D24X8",
5997	"xSURFACEFMT_DXT1",
5998	"xSURFACEFMT_DXT2",
5999	"xSURFACEFMT_DXT3",
6000	"xSURFACEFMT_DXT4",
6001	"xSURFACEFMT_DXT5",
6002	"xSURFACEFMT_BUMPX8L8V8U8",
6003	"xSURFACEFMT_A2W10V10U10",
6004	"xSURFACEFMT_BUMPU8V8",
6005	"xSURFACEFMT_Q8W8V8U8",
6006	"xSURFACEFMT_CxV8U8",
6007	"xSURFACEFMT_R_S10E5",
6008	"xSURFACEFMT_R_S23E8",
6009	"xSURFACEFMT_RG_S10E5",
6010	"xSURFACEFMT_RG_S23E8",
6011	"xSURFACEFMT_ARGB_S10E5",
6012	"xSURFACEFMT_ARGB_S23E8",
6013	"xMISSING62",
6014	"xMAX_VERTEX_SHADER_TEXTURES",
6015	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6016	"xSURFACEFMT_V16U16",
6017	"xSURFACEFMT_G16R16",
6018	"xSURFACEFMT_A16B16G16R16",
6019	"xSURFACEFMT_UYVY",
6020	"xSURFACEFMT_YUY2",
6021	"xMULTISAMPLE_NONMASKABLESAMPLES",
6022	"xMULTISAMPLE_MASKABLESAMPLES",
6023	"xALPHATOCOVERAGE",
6024	"xSUPERSAMPLE",
6025	"xAUTOGENMIPMAPS",
6026	"xSURFACEFMT_NV12",
6027	"xSURFACEFMT_AYUV",
6028	"xMAX_CONTEXT_IDS",
6029	"xMAX_SURFACE_IDS",
6030	"xSURFACEFMT_Z_DF16",
6031	"xSURFACEFMT_Z_DF24",
6032	"xSURFACEFMT_Z_D24S8_INT",
6033	"xSURFACEFMT_BC4_UNORM",
6034	"xSURFACEFMT_BC5_UNORM", /* 83 */
6035	};
6036	# endif
6037
6038
6039	/**
6040	* Power On notification.
6041	*
6042	* @returns VBox status code.
6043	* @param pDevIns The device instance data.
6044	*
6045	* @remarks Caller enters the device critical section.
6046	*/
6047	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6048	{
6049	# ifdef VBOX_WITH_VMSVGA3D
6050	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6051	if (pThis->svga.f3DEnabled)
6052	{
6053	int rc = vmsvga3dPowerOn(pThis);
6054
6055	if (RT_SUCCESS(rc))
6056	{
6057	bool fSavedBuffering = RTLogRelSetBuffering(true);
6058	SVGA3dCapsRecord *pCaps;
6059	SVGA3dCapPair *pData;
6060	uint32_t idxCap = 0;
6061
6062	/* 3d hardware version; latest and greatest */
6063	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6064	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6065
6066	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6067	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6068	pData = (SVGA3dCapPair *)&pCaps->data;
6069
6070	/* Fill out all 3d capabilities. */
6071	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6072	{
6073	uint32_t val = 0;
6074
6075	rc = vmsvga3dQueryCaps(pThis, i, &val);
6076	if (RT_SUCCESS(rc))
6077	{
6078	pData[idxCap][0] = i;
6079	pData[idxCap][1] = val;
6080	idxCap++;
6081	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6082	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6083	else
6084	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6085	&g_apszVmSvgaDevCapNames[i][1]));
6086	}
6087	else
6088	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6089	}
6090	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6091	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6092
6093	/* Mark end of record array. */
6094	pCaps->header.length = 0;
6095
6096	RTLogRelSetBuffering(fSavedBuffering);
6097	}
6098	}
6099	# else /* !VBOX_WITH_VMSVGA3D */
6100	RT_NOREF(pDevIns);
6101	# endif /* !VBOX_WITH_VMSVGA3D */
6102	}
6103
6104	#endif /* IN_RING3 */
6105

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 76201

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