DevVGA-SVGA.cpp@ 76785

Last change on this file since 76785 was 76635, checked in by vboxsync, 6 years ago
DevVGA-SVGA.cpp: fixed VMSVGA saved state with 3D disabled
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1	/* $Id: DevVGA-SVGA.cpp 76635 2019-01-04 13:57:30Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	#endif
146
147	#include <VBox/AssertGuest.h>
148	#include <VBox/VMMDev.h>
149	#include <VBoxVideo.h>
150	#include <VBox/bioslogo.h>
151
152	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
153	#include "DevVGA.h"
154
155	#include "DevVGA-SVGA.h"
156	#include "vmsvga/svga_escape.h"
157	#include "vmsvga/svga_overlay.h"
158	#include "vmsvga/svga3d_caps.h"
159	#ifdef VBOX_WITH_VMSVGA3D
160	# include "DevVGA-SVGA3d.h"
161	# ifdef RT_OS_DARWIN
162	# include "DevVGA-SVGA3d-cocoa.h"
163	# endif
164	#endif
165
166
167	/*********************************************************************************************************************************
168	* Defined Constants And Macros *
169	*********************************************************************************************************************************/
170	/**
171	* Macro for checking if a fixed FIFO register is valid according to the
172	* current FIFO configuration.
173	*
174	* @returns true / false.
175	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
176	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
177	*/
178	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
179
180
181	/*********************************************************************************************************************************
182	* Structures and Typedefs *
183	*********************************************************************************************************************************/
184	/**
185	* 64-bit GMR descriptor.
186	*/
187	typedef struct
188	{
189	RTGCPHYS GCPhys;
190	uint64_t numPages;
191	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
192
193	/**
194	* GMR slot
195	*/
196	typedef struct
197	{
198	uint32_t cMaxPages;
199	uint32_t cbTotal;
200	uint32_t numDescriptors;
201	PVMSVGAGMRDESCRIPTOR paDesc;
202	} GMR, *PGMR;
203
204	#ifdef IN_RING3
205	/**
206	* Internal SVGA ring-3 only state.
207	*/
208	typedef struct VMSVGAR3STATE
209	{
210	GMR *paGMR; // [VMSVGAState::cGMR]
211	struct
212	{
213	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
214	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
215	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
216	} GMRFB;
217	struct
218	{
219	bool fActive;
220	uint32_t xHotspot;
221	uint32_t yHotspot;
222	uint32_t width;
223	uint32_t height;
224	uint32_t cbData;
225	void *pData;
226	} Cursor;
227	SVGAColorBGRX colorAnnotation;
228
229	# ifdef VMSVGA_USE_EMT_HALT_CODE
230	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
231	uint32_t volatile cBusyDelayedEmts;
232	/** Set of EMTs that are */
233	VMCPUSET BusyDelayedEmts;
234	# else
235	/** Number of EMTs waiting on hBusyDelayedEmts. */
236	uint32_t volatile cBusyDelayedEmts;
237	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
238	* busy (ugly). */
239	RTSEMEVENTMULTI hBusyDelayedEmts;
240	# endif
241
242	/** Information obout screens. */
243	VMSVGASCREENOBJECT aScreens[64];
244
245	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
246	STAMPROFILE StatBusyDelayEmts;
247
248	STAMPROFILE StatR3Cmd3dPresentProf;
249	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
250	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
251	STAMCOUNTER StatR3CmdDefineGmr2;
252	STAMCOUNTER StatR3CmdDefineGmr2Free;
253	STAMCOUNTER StatR3CmdDefineGmr2Modify;
254	STAMCOUNTER StatR3CmdRemapGmr2;
255	STAMCOUNTER StatR3CmdRemapGmr2Modify;
256	STAMCOUNTER StatR3CmdInvalidCmd;
257	STAMCOUNTER StatR3CmdFence;
258	STAMCOUNTER StatR3CmdUpdate;
259	STAMCOUNTER StatR3CmdUpdateVerbose;
260	STAMCOUNTER StatR3CmdDefineCursor;
261	STAMCOUNTER StatR3CmdDefineAlphaCursor;
262	STAMCOUNTER StatR3CmdEscape;
263	STAMCOUNTER StatR3CmdDefineScreen;
264	STAMCOUNTER StatR3CmdDestroyScreen;
265	STAMCOUNTER StatR3CmdDefineGmrFb;
266	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
267	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
268	STAMCOUNTER StatR3CmdAnnotationFill;
269	STAMCOUNTER StatR3CmdAnnotationCopy;
270	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
271	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
272	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
273	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
275	STAMCOUNTER StatR3Cmd3dSurfaceDma;
276	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
277	STAMCOUNTER StatR3Cmd3dContextDefine;
278	STAMCOUNTER StatR3Cmd3dContextDestroy;
279	STAMCOUNTER StatR3Cmd3dSetTransform;
280	STAMCOUNTER StatR3Cmd3dSetZRange;
281	STAMCOUNTER StatR3Cmd3dSetRenderState;
282	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
283	STAMCOUNTER StatR3Cmd3dSetTextureState;
284	STAMCOUNTER StatR3Cmd3dSetMaterial;
285	STAMCOUNTER StatR3Cmd3dSetLightData;
286	STAMCOUNTER StatR3Cmd3dSetLightEnable;
287	STAMCOUNTER StatR3Cmd3dSetViewPort;
288	STAMCOUNTER StatR3Cmd3dSetClipPlane;
289	STAMCOUNTER StatR3Cmd3dClear;
290	STAMCOUNTER StatR3Cmd3dPresent;
291	STAMCOUNTER StatR3Cmd3dPresentReadBack;
292	STAMCOUNTER StatR3Cmd3dShaderDefine;
293	STAMCOUNTER StatR3Cmd3dShaderDestroy;
294	STAMCOUNTER StatR3Cmd3dSetShader;
295	STAMCOUNTER StatR3Cmd3dSetShaderConst;
296	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
297	STAMCOUNTER StatR3Cmd3dSetScissorRect;
298	STAMCOUNTER StatR3Cmd3dBeginQuery;
299	STAMCOUNTER StatR3Cmd3dEndQuery;
300	STAMCOUNTER StatR3Cmd3dWaitForQuery;
301	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
302	STAMCOUNTER StatR3Cmd3dActivateSurface;
303	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
304
305	STAMCOUNTER StatR3RegConfigDoneWr;
306	STAMCOUNTER StatR3RegGmrDescriptorWr;
307	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
308	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
309
310	STAMCOUNTER StatFifoCommands;
311	STAMCOUNTER StatFifoErrors;
312	STAMCOUNTER StatFifoUnkCmds;
313	STAMCOUNTER StatFifoTodoTimeout;
314	STAMCOUNTER StatFifoTodoWoken;
315	STAMPROFILE StatFifoStalls;
316
317	} VMSVGAR3STATE, *PVMSVGAR3STATE;
318	#endif /* IN_RING3 */
319
320
321	/*********************************************************************************************************************************
322	* Internal Functions *
323	*********************************************************************************************************************************/
324	#ifdef IN_RING3
325	# ifdef DEBUG_FIFO_ACCESS
326	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
327	# endif
328	# ifdef DEBUG_GMR_ACCESS
329	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
330	# endif
331	#endif
332
333
334	/*********************************************************************************************************************************
335	* Global Variables *
336	*********************************************************************************************************************************/
337	#ifdef IN_RING3
338
339	/**
340	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
341	*/
342	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
343	{
344	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
345	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
346	SSMFIELD_ENTRY_TERM()
347	};
348
349	/**
350	* SSM descriptor table for the GMR structure.
351	*/
352	static SSMFIELD const g_aGMRFields[] =
353	{
354	SSMFIELD_ENTRY( GMR, cMaxPages),
355	SSMFIELD_ENTRY( GMR, cbTotal),
356	SSMFIELD_ENTRY( GMR, numDescriptors),
357	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
363	*/
364	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
365	{
366	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
367	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
368	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
369	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
370	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
371	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
372	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
373	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
374	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
375	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
376	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
377	SSMFIELD_ENTRY_TERM()
378	};
379
380	/**
381	* SSM descriptor table for the VMSVGAR3STATE structure.
382	*/
383	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
384	{
385	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
386	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
387	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
388	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
389	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
390	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
391	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
392	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
393	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
394	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
395	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
396	#ifdef VMSVGA_USE_EMT_HALT_CODE
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
398	#else
399	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
400	#endif
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
405	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
458
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
463
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
470	SSMFIELD_ENTRY_TERM()
471	};
472
473	/**
474	* SSM descriptor table for the VGAState.svga structure.
475	*/
476	static SSMFIELD const g_aVGAStateSVGAFields[] =
477	{
478	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
479	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
480	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
481	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
482	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
483	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
484	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
487	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
488	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
489	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
490	SSMFIELD_ENTRY( VMSVGAState, fBusy),
491	SSMFIELD_ENTRY( VMSVGAState, fTraces),
492	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
493	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
494	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
495	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
496	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
497	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
498	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
499	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
501	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
504	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
505	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
506	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
507	SSMFIELD_ENTRY( VMSVGAState, uWidth),
508	SSMFIELD_ENTRY( VMSVGAState, uHeight),
509	SSMFIELD_ENTRY( VMSVGAState, uBpp),
510	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
511	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
512	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
513	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
514	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
515	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
516	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
517	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
519	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
520	SSMFIELD_ENTRY_TERM()
521	};
522
523	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
524	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
525	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
526
527	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
528	{
529	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
530	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
531	&& pSVGAState
532	&& pSVGAState->aScreens[idScreen].fDefined)
533	{
534	return &pSVGAState->aScreens[idScreen];
535	}
536	return NULL;
537	}
538
539	#endif /* IN_RING3 */
540
541	#ifdef LOG_ENABLED
542
543	/**
544	* Index register string name lookup
545	*
546	* @returns Index register string or "UNKNOWN"
547	* @param pThis VMSVGA State
548	* @param idxReg The index register.
549	*/
550	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
551	{
552	switch (idxReg)
553	{
554	case SVGA_REG_ID: return "SVGA_REG_ID";
555	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
556	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
557	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
558	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
559	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
560	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
561	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
562	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
563	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
564	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
565	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
566	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
567	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
568	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
569	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
570	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
571	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
572	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
573	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
574	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
575	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
576	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
577	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
578	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
579	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
580	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
581	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
582	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
583	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
584	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
585	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
586	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
587	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
588	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
589	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
590	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
591	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
592	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
593	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
594	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
595	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
596	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
597	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
598	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
599	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
600	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
601	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
602	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
603	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
604
605	default:
606	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
607	return "SVGA_SCRATCH_BASE reg";
608	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
609	return "SVGA_PALETTE_BASE reg";
610	return "UNKNOWN";
611	}
612	}
613
614	#ifdef IN_RING3
615	/**
616	* FIFO command name lookup
617	*
618	* @returns FIFO command string or "UNKNOWN"
619	* @param u32Cmd FIFO command
620	*/
621	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
622	{
623	switch (u32Cmd)
624	{
625	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
626	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
627	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
628	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
629	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
630	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
631	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
632	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
633	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
634	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
635	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
636	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
637	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
638	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
639	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
640	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
641	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
642	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
643	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
644	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
645	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
646	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
647	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
648	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
649	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
650	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
651	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
652	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
653	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
654	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
655	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
656	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
657	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
658	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
659	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
660	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
661	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
662	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
663	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
664	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
665	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
666	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
667	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
668	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
669	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
670	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
671	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
672	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
673	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
674	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
675	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
676	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
677	default: return "UNKNOWN";
678	}
679	}
680	# endif /* IN_RING3 */
681
682	#endif /* LOG_ENABLED */
683
684	#ifdef IN_RING3
685	/**
686	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
687	*/
688	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
689	{
690	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
691
692	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
693	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
694
695	/** @todo Test how it interacts with multiple screen objects. */
696	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
697	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
698	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
699
700	if (x < uWidth)
701	{
702	pThis->svga.viewport.x = x;
703	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
704	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
705	}
706	else
707	{
708	pThis->svga.viewport.x = uWidth;
709	pThis->svga.viewport.cx = 0;
710	pThis->svga.viewport.xRight = uWidth;
711	}
712	if (y < uHeight)
713	{
714	pThis->svga.viewport.y = y;
715	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
716	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
717	pThis->svga.viewport.yHighWC = uHeight - y;
718	}
719	else
720	{
721	pThis->svga.viewport.y = uHeight;
722	pThis->svga.viewport.cy = 0;
723	pThis->svga.viewport.yLowWC = 0;
724	pThis->svga.viewport.yHighWC = 0;
725	}
726
727	# ifdef VBOX_WITH_VMSVGA3D
728	/*
729	* Now inform the 3D backend.
730	*/
731	if (pThis->svga.f3DEnabled)
732	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
733	# else
734	RT_NOREF(OldViewport);
735	# endif
736	}
737	#endif /* IN_RING3 */
738
739	/**
740	* Read port register
741	*
742	* @returns VBox status code.
743	* @param pThis VMSVGA State
744	* @param pu32 Where to store the read value
745	*/
746	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
747	{
748	int rc = VINF_SUCCESS;
749	*pu32 = 0;
750
751	/* Rough index register validation. */
752	uint32_t idxReg = pThis->svga.u32IndexReg;
753	#if !defined(IN_RING3) && defined(VBOX_STRICT)
754	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
755	VINF_IOM_R3_IOPORT_READ);
756	#else
757	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
758	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
759	VINF_SUCCESS);
760	#endif
761	RT_UNTRUSTED_VALIDATED_FENCE();
762
763	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
764	if ( idxReg >= SVGA_REG_CAPABILITIES
765	&& pThis->svga.u32SVGAId == SVGA_ID_0)
766	{
767	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
768	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
769	}
770
771	switch (idxReg)
772	{
773	case SVGA_REG_ID:
774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
775	*pu32 = pThis->svga.u32SVGAId;
776	break;
777
778	case SVGA_REG_ENABLE:
779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
780	*pu32 = pThis->svga.fEnabled;
781	break;
782
783	case SVGA_REG_WIDTH:
784	{
785	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
786	if ( pThis->svga.fEnabled
787	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
788	{
789	*pu32 = pThis->svga.uWidth;
790	}
791	else
792	{
793	#ifndef IN_RING3
794	rc = VINF_IOM_R3_IOPORT_READ;
795	#else
796	*pu32 = pThis->pDrv->cx;
797	#endif
798	}
799	break;
800	}
801
802	case SVGA_REG_HEIGHT:
803	{
804	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
805	if ( pThis->svga.fEnabled
806	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
807	{
808	*pu32 = pThis->svga.uHeight;
809	}
810	else
811	{
812	#ifndef IN_RING3
813	rc = VINF_IOM_R3_IOPORT_READ;
814	#else
815	*pu32 = pThis->pDrv->cy;
816	#endif
817	}
818	break;
819	}
820
821	case SVGA_REG_MAX_WIDTH:
822	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
823	*pu32 = pThis->svga.u32MaxWidth;
824	break;
825
826	case SVGA_REG_MAX_HEIGHT:
827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
828	*pu32 = pThis->svga.u32MaxHeight;
829	break;
830
831	case SVGA_REG_DEPTH:
832	/* This returns the color depth of the current mode. */
833	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
834	switch (pThis->svga.uBpp)
835	{
836	case 15:
837	case 16:
838	case 24:
839	*pu32 = pThis->svga.uBpp;
840	break;
841
842	default:
843	case 32:
844	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
845	break;
846	}
847	break;
848
849	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
851	if ( pThis->svga.fEnabled
852	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
853	{
854	*pu32 = pThis->svga.uBpp;
855	}
856	else
857	{
858	#ifndef IN_RING3
859	rc = VINF_IOM_R3_IOPORT_READ;
860	#else
861	*pu32 = pThis->pDrv->cBits;
862	#endif
863	}
864	break;
865
866	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
867	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
868	if ( pThis->svga.fEnabled
869	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
870	{
871	*pu32 = (pThis->svga.uBpp + 7) & ~7;
872	}
873	else
874	{
875	#ifndef IN_RING3
876	rc = VINF_IOM_R3_IOPORT_READ;
877	#else
878	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
879	#endif
880	}
881	break;
882
883	case SVGA_REG_PSEUDOCOLOR:
884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
885	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
886	break;
887
888	case SVGA_REG_RED_MASK:
889	case SVGA_REG_GREEN_MASK:
890	case SVGA_REG_BLUE_MASK:
891	{
892	uint32_t uBpp;
893
894	if ( pThis->svga.fEnabled
895	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
896	{
897	uBpp = pThis->svga.uBpp;
898	}
899	else
900	{
901	#ifndef IN_RING3
902	rc = VINF_IOM_R3_IOPORT_READ;
903	break;
904	#else
905	uBpp = pThis->pDrv->cBits;
906	#endif
907	}
908	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
909	switch (uBpp)
910	{
911	case 8:
912	u32RedMask = 0x07;
913	u32GreenMask = 0x38;
914	u32BlueMask = 0xc0;
915	break;
916
917	case 15:
918	u32RedMask = 0x0000001f;
919	u32GreenMask = 0x000003e0;
920	u32BlueMask = 0x00007c00;
921	break;
922
923	case 16:
924	u32RedMask = 0x0000001f;
925	u32GreenMask = 0x000007e0;
926	u32BlueMask = 0x0000f800;
927	break;
928
929	case 24:
930	case 32:
931	default:
932	u32RedMask = 0x00ff0000;
933	u32GreenMask = 0x0000ff00;
934	u32BlueMask = 0x000000ff;
935	break;
936	}
937	switch (idxReg)
938	{
939	case SVGA_REG_RED_MASK:
940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
941	*pu32 = u32RedMask;
942	break;
943
944	case SVGA_REG_GREEN_MASK:
945	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
946	*pu32 = u32GreenMask;
947	break;
948
949	case SVGA_REG_BLUE_MASK:
950	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
951	*pu32 = u32BlueMask;
952	break;
953	}
954	break;
955	}
956
957	case SVGA_REG_BYTES_PER_LINE:
958	{
959	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
960	if ( pThis->svga.fEnabled
961	&& pThis->svga.cbScanline)
962	{
963	*pu32 = pThis->svga.cbScanline;
964	}
965	else
966	{
967	#ifndef IN_RING3
968	rc = VINF_IOM_R3_IOPORT_READ;
969	#else
970	*pu32 = pThis->pDrv->cbScanline;
971	#endif
972	}
973	break;
974	}
975
976	case SVGA_REG_VRAM_SIZE: /* VRAM size */
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
978	*pu32 = pThis->vram_size;
979	break;
980
981	case SVGA_REG_FB_START: /* Frame buffer physical address. */
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
983	Assert(pThis->GCPhysVRAM <= 0xffffffff);
984	*pu32 = pThis->GCPhysVRAM;
985	break;
986
987	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
988	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
989	/* Always zero in our case. */
990	*pu32 = 0;
991	break;
992
993	case SVGA_REG_FB_SIZE: /* Frame buffer size */
994	{
995	#ifndef IN_RING3
996	rc = VINF_IOM_R3_IOPORT_READ;
997	#else
998	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
999
1000	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1001	if ( pThis->svga.fEnabled
1002	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1003	{
1004	/* Hardware enabled; return real framebuffer size .*/
1005	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1006	}
1007	else
1008	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1009
1010	pu32 = RT_MIN(pThis->vram_size, pu32);
1011	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1012	#endif
1013	break;
1014	}
1015
1016	case SVGA_REG_CAPABILITIES:
1017	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1018	*pu32 = pThis->svga.u32RegCaps;
1019	break;
1020
1021	case SVGA_REG_MEM_START: /* FIFO start */
1022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1023	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1024	*pu32 = pThis->svga.GCPhysFIFO;
1025	break;
1026
1027	case SVGA_REG_MEM_SIZE: /* FIFO size */
1028	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1029	*pu32 = pThis->svga.cbFIFO;
1030	break;
1031
1032	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1033	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1034	*pu32 = pThis->svga.fConfigured;
1035	break;
1036
1037	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1038	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1039	*pu32 = 0;
1040	break;
1041
1042	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1044	if (pThis->svga.fBusy)
1045	{
1046	#ifndef IN_RING3
1047	/* Go to ring-3 and halt the CPU. */
1048	rc = VINF_IOM_R3_IOPORT_READ;
1049	break;
1050	#else
1051	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1052	/* The guest is basically doing a HLT via the device here, but with
1053	a special wake up condition on FIFO completion. */
1054	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1055	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1056	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1057	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1058	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1059	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1060	if (pThis->svga.fBusy)
1061	{
1062	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1063	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1064	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1065	}
1066	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1067	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1068	# else
1069
1070	/* Delay the EMT a bit so the FIFO and others can get some work done.
1071	This used to be a crude 50 ms sleep. The current code tries to be
1072	more efficient, but the consept is still very crude. */
1073	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1074	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1075	RTThreadYield();
1076	if (pThis->svga.fBusy)
1077	{
1078	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1079
1080	if (pThis->svga.fBusy && cRefs == 1)
1081	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	/** @todo If this code is going to stay, we need to call into the halt/wait
1085	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1086	* suffer when the guest is polling on a busy FIFO. */
1087	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1088	if (cNsMaxWait >= RT_NS_100US)
1089	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1090	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1091	RT_MIN(cNsMaxWait, RT_NS_10MS));
1092	}
1093
1094	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1095	}
1096	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	# endif
1098	*pu32 = pThis->svga.fBusy != 0;
1099	#endif
1100	}
1101	else
1102	*pu32 = false;
1103	break;
1104
1105	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1107	*pu32 = pThis->svga.u32GuestId;
1108	break;
1109
1110	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1112	*pu32 = pThis->svga.cScratchRegion;
1113	break;
1114
1115	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1117	*pu32 = SVGA_FIFO_NUM_REGS;
1118	break;
1119
1120	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1121	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1122	*pu32 = pThis->svga.u32PitchLock;
1123	break;
1124
1125	case SVGA_REG_IRQMASK: /* Interrupt mask */
1126	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1127	*pu32 = pThis->svga.u32IrqMask;
1128	break;
1129
1130	/* See "Guest memory regions" below. */
1131	case SVGA_REG_GMR_ID:
1132	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1133	*pu32 = pThis->svga.u32CurrentGMRId;
1134	break;
1135
1136	case SVGA_REG_GMR_DESCRIPTOR:
1137	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1138	/* Write only */
1139	*pu32 = 0;
1140	break;
1141
1142	case SVGA_REG_GMR_MAX_IDS:
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1144	*pu32 = pThis->svga.cGMR;
1145	break;
1146
1147	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1149	*pu32 = VMSVGA_MAX_GMR_PAGES;
1150	break;
1151
1152	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1154	*pu32 = pThis->svga.fTraces;
1155	break;
1156
1157	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1159	*pu32 = VMSVGA_MAX_GMR_PAGES;
1160	break;
1161
1162	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1164	*pu32 = VMSVGA_SURFACE_SIZE;
1165	break;
1166
1167	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1169	break;
1170
1171	/* Mouse cursor support. */
1172	case SVGA_REG_CURSOR_ID:
1173	case SVGA_REG_CURSOR_X:
1174	case SVGA_REG_CURSOR_Y:
1175	case SVGA_REG_CURSOR_ON:
1176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1177	break;
1178
1179	/* Legacy multi-monitor support */
1180	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1181	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1182	*pu32 = 1;
1183	break;
1184
1185	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1186	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1187	*pu32 = 0;
1188	break;
1189
1190	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1191	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1192	*pu32 = 0;
1193	break;
1194
1195	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1196	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1197	*pu32 = 0;
1198	break;
1199
1200	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1201	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1202	*pu32 = 0;
1203	break;
1204
1205	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1207	*pu32 = pThis->svga.uWidth;
1208	break;
1209
1210	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1211	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1212	*pu32 = pThis->svga.uHeight;
1213	break;
1214
1215	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1217	/* We must return something sensible here otherwise the Linux driver
1218	* will take a legacy code path without 3d support. This number also
1219	* limits how many screens Linux guests will allow. */
1220	*pu32 = pThis->cMonitors;
1221	break;
1222
1223	default:
1224	{
1225	uint32_t offReg;
1226	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1227	{
1228	RT_UNTRUSTED_VALIDATED_FENCE();
1229	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1231	}
1232	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1233	{
1234	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1236	RT_UNTRUSTED_VALIDATED_FENCE();
1237	uint32_t u32 = pThis->last_palette[offReg / 3];
1238	switch (offReg % 3)
1239	{
1240	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1241	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1242	case 2: pu32 = u32 & 0xff; break; / blue */
1243	}
1244	}
1245	else
1246	{
1247	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1248	rc = VINF_IOM_R3_IOPORT_READ;
1249	#else
1250	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1251
1252	/* Do not assert. The guest might be reading all registers. */
1253	LogFunc(("Unknown reg=%#x\n", idxReg));
1254	#endif
1255	}
1256	break;
1257	}
1258	}
1259	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1260	return rc;
1261	}
1262
1263	#ifdef IN_RING3
1264	/**
1265	* Apply the current resolution settings to change the video mode.
1266	*
1267	* @returns VBox status code.
1268	* @param pThis VMSVGA State
1269	*/
1270	static int vmsvgaChangeMode(PVGASTATE pThis)
1271	{
1272	int rc;
1273
1274	/* Always do changemode on FIFO thread. */
1275	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1276
1277	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1278
1279	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1280
1281	if (pThis->svga.fGFBRegisters)
1282	{
1283	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1284	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1285	* deletes all screens other than screen #0, and redefines screen
1286	* #0 according to the specified mode. Drivers that use
1287	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1288	*/
1289
1290	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1291	pScreen->fDefined = true;
1292	pScreen->fModified = true;
1293	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1294	pScreen->idScreen = 0;
1295	pScreen->xOrigin = 0;
1296	pScreen->yOrigin = 0;
1297	pScreen->offVRAM = 0;
1298	pScreen->cbPitch = pThis->svga.cbScanline;
1299	pScreen->cWidth = pThis->svga.uWidth;
1300	pScreen->cHeight = pThis->svga.uHeight;
1301	pScreen->cBpp = pThis->svga.uBpp;
1302
1303	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1304	{
1305	/* Delete screen. */
1306	pScreen = &pSVGAState->aScreens[iScreen];
1307	if (pScreen->fDefined)
1308	{
1309	pScreen->fModified = true;
1310	pScreen->fDefined = false;
1311	}
1312	}
1313	}
1314	else
1315	{
1316	/* "If Screen Objects are supported, they can be used to fully
1317	* replace the functionality provided by the framebuffer registers
1318	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1319	*/
1320	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1321	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1322	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1323	}
1324
1325	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1328	if (!pScreen->fModified)
1329	continue;
1330
1331	pScreen->fModified = false;
1332
1333	VBVAINFOVIEW view;
1334	RT_ZERO(view);
1335	view.u32ViewIndex = pScreen->idScreen;
1336	// view.u32ViewOffset = 0;
1337	view.u32ViewSize = pThis->vram_size;
1338	view.u32MaxScreenSize = pThis->vram_size;
1339
1340	VBVAINFOSCREEN screen;
1341	RT_ZERO(screen);
1342	screen.u32ViewIndex = pScreen->idScreen;
1343
1344	if (pScreen->fDefined)
1345	{
1346	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1347	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1348	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1349	{
1350	Assert(pThis->svga.fGFBRegisters);
1351	continue;
1352	}
1353
1354	screen.i32OriginX = pScreen->xOrigin;
1355	screen.i32OriginY = pScreen->yOrigin;
1356	screen.u32StartOffset = pScreen->offVRAM;
1357	screen.u32LineSize = pScreen->cbPitch;
1358	screen.u32Width = pScreen->cWidth;
1359	screen.u32Height = pScreen->cHeight;
1360	screen.u16BitsPerPixel = pScreen->cBpp;
1361	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1362	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1363	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1364	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1365	}
1366	else
1367	{
1368	/* Screen is destroyed. */
1369	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1370	}
1371
1372	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1373	AssertRC(rc);
1374	}
1375
1376	/* Last stuff. For the VGA device screenshot. */
1377	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1378	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1379	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1380	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1381	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1382
1383	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1384	if ( pThis->svga.viewport.cx == 0
1385	&& pThis->svga.viewport.cy == 0)
1386	{
1387	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1388	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1389	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1390	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1391	pThis->svga.viewport.yLowWC = 0;
1392	}
1393
1394	return VINF_SUCCESS;
1395	}
1396
1397	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1398	{
1399	if (pThis->svga.fGFBRegisters)
1400	{
1401	vgaR3UpdateDisplay(pThis, x, y, w, h);
1402	}
1403	else
1404	{
1405	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1406	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1407	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1408	}
1409
1410	return VINF_SUCCESS;
1411	}
1412
1413	#endif /* IN_RING3 */
1414
1415	#if defined(IN_RING0) \|\| defined(IN_RING3)
1416	/**
1417	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1418	*
1419	* @param pThis The VMSVGA state.
1420	* @param fState The busy state.
1421	*/
1422	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1423	{
1424	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1425
1426	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1427	{
1428	/* Race / unfortunately scheduling. Highly unlikly. */
1429	uint32_t cLoops = 64;
1430	do
1431	{
1432	ASMNopPause();
1433	fState = (pThis->svga.fBusy != 0);
1434	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1435	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1436	}
1437	}
1438	#endif
1439
1440	/**
1441	* Write port register
1442	*
1443	* @returns VBox status code.
1444	* @param pThis VMSVGA State
1445	* @param u32 Value to write
1446	*/
1447	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1448	{
1449	#ifdef IN_RING3
1450	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1451	#endif
1452	int rc = VINF_SUCCESS;
1453
1454	/* Rough index register validation. */
1455	uint32_t idxReg = pThis->svga.u32IndexReg;
1456	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1457	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1458	VINF_IOM_R3_IOPORT_WRITE);
1459	#else
1460	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1461	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1462	VINF_SUCCESS);
1463	#endif
1464	RT_UNTRUSTED_VALIDATED_FENCE();
1465
1466	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1467	if ( idxReg >= SVGA_REG_CAPABILITIES
1468	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1469	{
1470	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1471	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1472	}
1473	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1474	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1475	switch (idxReg)
1476	{
1477	case SVGA_REG_WIDTH:
1478	case SVGA_REG_HEIGHT:
1479	case SVGA_REG_PITCHLOCK:
1480	case SVGA_REG_BITS_PER_PIXEL:
1481	pThis->svga.fGFBRegisters = true;
1482	break;
1483	default:
1484	break;
1485	}
1486
1487	switch (idxReg)
1488	{
1489	case SVGA_REG_ID:
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1491	if ( u32 == SVGA_ID_0
1492	\|\| u32 == SVGA_ID_1
1493	\|\| u32 == SVGA_ID_2)
1494	pThis->svga.u32SVGAId = u32;
1495	else
1496	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1497	break;
1498
1499	case SVGA_REG_ENABLE:
1500	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1501	#ifdef IN_RING3
1502	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1503	&& pThis->svga.fEnabled == false)
1504	{
1505	/* Make a backup copy of the first 512kb in order to save font data etc. */
1506	/** @todo should probably swap here, rather than copy + zero */
1507	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1508	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1509	}
1510
1511	pThis->svga.fEnabled = u32;
1512	if (pThis->svga.fEnabled)
1513	{
1514	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1515	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1516	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1517	{
1518	/* Keep the current mode. */
1519	pThis->svga.uWidth = pThis->pDrv->cx;
1520	pThis->svga.uHeight = pThis->pDrv->cy;
1521	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1522	}
1523
1524	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1525	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1526	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1527	{
1528	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1529	}
1530	# ifdef LOG_ENABLED
1531	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1532	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1533	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1534	# endif
1535
1536	/* Disable or enable dirty page tracking according to the current fTraces value. */
1537	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1538
1539	for (uint32_t iScreen = 0; iScreen < pThis->cMonitors; ++iScreen)
1540	{
1541	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, iScreen, NULL, false);
1542	}
1543	}
1544	else
1545	{
1546	/* Restore the text mode backup. */
1547	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1548
1549	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1550
1551	/* Enable dirty page tracking again when going into legacy mode. */
1552	vmsvgaSetTraces(pThis, true);
1553
1554	for (uint32_t iScreen = 0; iScreen < pThis->cMonitors; ++iScreen)
1555	{
1556	pThis->pDrv->pfnVBVADisable(pThis->pDrv, iScreen);
1557	}
1558	}
1559	#else /* !IN_RING3 */
1560	rc = VINF_IOM_R3_IOPORT_WRITE;
1561	#endif /* !IN_RING3 */
1562	break;
1563
1564	case SVGA_REG_WIDTH:
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1566	if (pThis->svga.uWidth != u32)
1567	{
1568	pThis->svga.uWidth = u32;
1569	if (pThis->svga.fEnabled)
1570	{
1571	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1572	}
1573	}
1574	/* else: nop */
1575	break;
1576
1577	case SVGA_REG_HEIGHT:
1578	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1579	if (pThis->svga.uHeight != u32)
1580	{
1581	pThis->svga.uHeight = u32;
1582	if (pThis->svga.fEnabled)
1583	{
1584	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1585	}
1586	}
1587	/* else: nop */
1588	break;
1589
1590	case SVGA_REG_DEPTH:
1591	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1592	/** @todo read-only?? */
1593	break;
1594
1595	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1596	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1597	if (pThis->svga.uBpp != u32)
1598	{
1599	pThis->svga.uBpp = u32;
1600	if (pThis->svga.fEnabled)
1601	{
1602	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1603	}
1604	}
1605	/* else: nop */
1606	break;
1607
1608	case SVGA_REG_PSEUDOCOLOR:
1609	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1610	break;
1611
1612	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1613	#ifdef IN_RING3
1614	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1615	pThis->svga.fConfigured = u32;
1616	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1617	if (!pThis->svga.fConfigured)
1618	{
1619	pThis->svga.fTraces = true;
1620	}
1621	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1622	#else
1623	rc = VINF_IOM_R3_IOPORT_WRITE;
1624	#endif
1625	break;
1626
1627	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1628	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1629	if ( pThis->svga.fEnabled
1630	&& pThis->svga.fConfigured)
1631	{
1632	#if defined(IN_RING3) \|\| defined(IN_RING0)
1633	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1634	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1635	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1636	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1637
1638	/* Kick the FIFO thread to start processing commands again. */
1639	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1640	#else
1641	rc = VINF_IOM_R3_IOPORT_WRITE;
1642	#endif
1643	}
1644	/* else nothing to do. */
1645	else
1646	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1647
1648	break;
1649
1650	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1651	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1652	break;
1653
1654	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1655	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1656	pThis->svga.u32GuestId = u32;
1657	break;
1658
1659	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1660	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1661	pThis->svga.u32PitchLock = u32;
1662	break;
1663
1664	case SVGA_REG_IRQMASK: /* Interrupt mask */
1665	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1666	pThis->svga.u32IrqMask = u32;
1667
1668	/* Irq pending after the above change? */
1669	if (pThis->svga.u32IrqStatus & u32)
1670	{
1671	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1672	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1673	}
1674	else
1675	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1676	break;
1677
1678	/* Mouse cursor support */
1679	case SVGA_REG_CURSOR_ID:
1680	case SVGA_REG_CURSOR_X:
1681	case SVGA_REG_CURSOR_Y:
1682	case SVGA_REG_CURSOR_ON:
1683	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1684	break;
1685
1686	/* Legacy multi-monitor support */
1687	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1688	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1689	break;
1690	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1691	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1692	break;
1693	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1694	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1695	break;
1696	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1697	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1698	break;
1699	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1700	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1701	break;
1702	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1703	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1704	break;
1705	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1706	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1707	break;
1708	#ifdef VBOX_WITH_VMSVGA3D
1709	/* See "Guest memory regions" below. */
1710	case SVGA_REG_GMR_ID:
1711	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1712	pThis->svga.u32CurrentGMRId = u32;
1713	break;
1714
1715	case SVGA_REG_GMR_DESCRIPTOR:
1716	# ifndef IN_RING3
1717	rc = VINF_IOM_R3_IOPORT_WRITE;
1718	break;
1719	# else /* IN_RING3 */
1720	{
1721	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1722
1723	/* Validate current GMR id. */
1724	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1725	AssertBreak(idGMR < pThis->svga.cGMR);
1726	RT_UNTRUSTED_VALIDATED_FENCE();
1727
1728	/* Free the old GMR if present. */
1729	vmsvgaGMRFree(pThis, idGMR);
1730
1731	/* Just undefine the GMR? */
1732	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1733	if (GCPhys == 0)
1734	{
1735	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1736	break;
1737	}
1738
1739
1740	/* Never cross a page boundary automatically. */
1741	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1742	uint32_t cPagesTotal = 0;
1743	uint32_t iDesc = 0;
1744	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1745	uint32_t cLoops = 0;
1746	RTGCPHYS GCPhysBase = GCPhys;
1747	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1748	{
1749	/* Read descriptor. */
1750	SVGAGuestMemDescriptor desc;
1751	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1752	AssertRCBreak(rc);
1753
1754	if (desc.numPages != 0)
1755	{
1756	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1757	cPagesTotal += desc.numPages;
1758	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1759
1760	if ((iDesc & 15) == 0)
1761	{
1762	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1763	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1764	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1765	}
1766
1767	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1768	paDescs[iDesc++].numPages = desc.numPages;
1769
1770	/* Continue with the next descriptor. */
1771	GCPhys += sizeof(desc);
1772	}
1773	else if (desc.ppn == 0)
1774	break; /* terminator */
1775	else /* Pointer to the next physical page of descriptors. */
1776	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1777
1778	cLoops++;
1779	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1780	}
1781
1782	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1783	if (RT_SUCCESS(rc))
1784	{
1785	/* Commit the GMR. */
1786	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1787	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1788	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1789	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1790	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1791	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1792	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1793	}
1794	else
1795	{
1796	RTMemFree(paDescs);
1797	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1798	}
1799	break;
1800	}
1801	# endif /* IN_RING3 */
1802	#endif // VBOX_WITH_VMSVGA3D
1803
1804	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1805	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1806	if (pThis->svga.fTraces == u32)
1807	break; /* nothing to do */
1808
1809	#ifdef IN_RING3
1810	vmsvgaSetTraces(pThis, !!u32);
1811	#else
1812	rc = VINF_IOM_R3_IOPORT_WRITE;
1813	#endif
1814	break;
1815
1816	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1817	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1818	break;
1819
1820	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1821	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1822	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1823	break;
1824
1825	case SVGA_REG_FB_START:
1826	case SVGA_REG_MEM_START:
1827	case SVGA_REG_HOST_BITS_PER_PIXEL:
1828	case SVGA_REG_MAX_WIDTH:
1829	case SVGA_REG_MAX_HEIGHT:
1830	case SVGA_REG_VRAM_SIZE:
1831	case SVGA_REG_FB_SIZE:
1832	case SVGA_REG_CAPABILITIES:
1833	case SVGA_REG_MEM_SIZE:
1834	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1835	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1836	case SVGA_REG_BYTES_PER_LINE:
1837	case SVGA_REG_FB_OFFSET:
1838	case SVGA_REG_RED_MASK:
1839	case SVGA_REG_GREEN_MASK:
1840	case SVGA_REG_BLUE_MASK:
1841	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1842	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1843	case SVGA_REG_GMR_MAX_IDS:
1844	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1845	/* Read only - ignore. */
1846	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1847	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1848	break;
1849
1850	default:
1851	{
1852	uint32_t offReg;
1853	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1854	{
1855	RT_UNTRUSTED_VALIDATED_FENCE();
1856	pThis->svga.au32ScratchRegion[offReg] = u32;
1857	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1858	}
1859	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1860	{
1861	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1862	Btw, see rgb_to_pixel32. */
1863	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1864	u32 &= 0xff;
1865	RT_UNTRUSTED_VALIDATED_FENCE();
1866	uint32_t uRgb = pThis->last_palette[offReg / 3];
1867	switch (offReg % 3)
1868	{
1869	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1870	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1871	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1872	}
1873	pThis->last_palette[offReg / 3] = uRgb;
1874	}
1875	else
1876	{
1877	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1878	rc = VINF_IOM_R3_IOPORT_WRITE;
1879	#else
1880	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1881	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1882	#endif
1883	}
1884	break;
1885	}
1886	}
1887	return rc;
1888	}
1889
1890	/**
1891	* Port I/O Handler for IN operations.
1892	*
1893	* @returns VINF_SUCCESS or VINF_EM_*.
1894	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1895	*
1896	* @param pDevIns The device instance.
1897	* @param pvUser User argument.
1898	* @param uPort Port number used for the IN operation.
1899	* @param pu32 Where to store the result. This is always a 32-bit
1900	* variable regardless of what @a cb might say.
1901	* @param cb Number of bytes read.
1902	*/
1903	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1904	{
1905	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1906	RT_NOREF_PV(pvUser);
1907
1908	/* Ignore non-dword accesses. */
1909	if (cb != 4)
1910	{
1911	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1912	*pu32 = UINT32_MAX;
1913	return VINF_SUCCESS;
1914	}
1915
1916	switch (uPort - pThis->svga.BasePort)
1917	{
1918	case SVGA_INDEX_PORT:
1919	*pu32 = pThis->svga.u32IndexReg;
1920	break;
1921
1922	case SVGA_VALUE_PORT:
1923	return vmsvgaReadPort(pThis, pu32);
1924
1925	case SVGA_BIOS_PORT:
1926	Log(("Ignoring BIOS port read\n"));
1927	*pu32 = 0;
1928	break;
1929
1930	case SVGA_IRQSTATUS_PORT:
1931	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1932	*pu32 = pThis->svga.u32IrqStatus;
1933	break;
1934
1935	default:
1936	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1937	*pu32 = UINT32_MAX;
1938	break;
1939	}
1940
1941	return VINF_SUCCESS;
1942	}
1943
1944	/**
1945	* Port I/O Handler for OUT operations.
1946	*
1947	* @returns VINF_SUCCESS or VINF_EM_*.
1948	*
1949	* @param pDevIns The device instance.
1950	* @param pvUser User argument.
1951	* @param uPort Port number used for the OUT operation.
1952	* @param u32 The value to output.
1953	* @param cb The value size in bytes.
1954	*/
1955	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1956	{
1957	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1958	RT_NOREF_PV(pvUser);
1959
1960	/* Ignore non-dword accesses. */
1961	if (cb != 4)
1962	{
1963	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1964	return VINF_SUCCESS;
1965	}
1966
1967	switch (uPort - pThis->svga.BasePort)
1968	{
1969	case SVGA_INDEX_PORT:
1970	pThis->svga.u32IndexReg = u32;
1971	break;
1972
1973	case SVGA_VALUE_PORT:
1974	return vmsvgaWritePort(pThis, u32);
1975
1976	case SVGA_BIOS_PORT:
1977	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1978	break;
1979
1980	case SVGA_IRQSTATUS_PORT:
1981	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1982	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1983	/* Clear the irq in case all events have been cleared. */
1984	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1985	{
1986	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1987	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1988	}
1989	break;
1990
1991	default:
1992	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
1993	uPort - pThis->svga.BasePort, uPort, u32, cb));
1994	break;
1995	}
1996	return VINF_SUCCESS;
1997	}
1998
1999	#ifdef DEBUG_FIFO_ACCESS
2000
2001	# ifdef IN_RING3
2002	/**
2003	* Handle LFB access.
2004	* @returns VBox status code.
2005	* @param pVM VM handle.
2006	* @param pThis VGA device instance data.
2007	* @param GCPhys The access physical address.
2008	* @param fWriteAccess Read or write access
2009	*/
2010	static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2011	{
2012	RT_NOREF(pVM);
2013	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2014	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2015
2016	switch (GCPhysOffset >> 2)
2017	{
2018	case SVGA_FIFO_MIN:
2019	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2020	break;
2021	case SVGA_FIFO_MAX:
2022	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2023	break;
2024	case SVGA_FIFO_NEXT_CMD:
2025	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2026	break;
2027	case SVGA_FIFO_STOP:
2028	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2029	break;
2030	case SVGA_FIFO_CAPABILITIES:
2031	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2032	break;
2033	case SVGA_FIFO_FLAGS:
2034	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2035	break;
2036	case SVGA_FIFO_FENCE:
2037	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2038	break;
2039	case SVGA_FIFO_3D_HWVERSION:
2040	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2041	break;
2042	case SVGA_FIFO_PITCHLOCK:
2043	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2044	break;
2045	case SVGA_FIFO_CURSOR_ON:
2046	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2047	break;
2048	case SVGA_FIFO_CURSOR_X:
2049	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2050	break;
2051	case SVGA_FIFO_CURSOR_Y:
2052	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2053	break;
2054	case SVGA_FIFO_CURSOR_COUNT:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_RESERVED:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_CURSOR_SCREEN_ID:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_DEAD:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_3D_HWVERSION_REVISED:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS_LAST:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_GUEST_3D_HWVERSION:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_FENCE_GOAL:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_BUSY:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	default:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	}
2337
2338	return VINF_EM_RAW_EMULATE_INSTR;
2339	}
2340
2341	/**
2342	* HC access handler for the FIFO.
2343	*
2344	* @returns VINF_SUCCESS if the handler have carried out the operation.
2345	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2346	* @param pVM VM Handle.
2347	* @param pVCpu The cross context CPU structure for the calling EMT.
2348	* @param GCPhys The physical address the guest is writing to.
2349	* @param pvPhys The HC mapping of that address.
2350	* @param pvBuf What the guest is reading/writing.
2351	* @param cbBuf How much it's reading/writing.
2352	* @param enmAccessType The access type.
2353	* @param enmOrigin Who is making the access.
2354	* @param pvUser User argument.
2355	*/
2356	static DECLCALLBACK(VBOXSTRICTRC)
2357	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2358	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2359	{
2360	PVGASTATE pThis = (PVGASTATE)pvUser;
2361	int rc;
2362	Assert(pThis);
2363	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2364	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
2365
2366	rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2367	if (RT_SUCCESS(rc))
2368	return VINF_PGM_HANDLER_DO_DEFAULT;
2369	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2370	return rc;
2371	}
2372
2373	# endif /* IN_RING3 */
2374	#endif /* DEBUG_FIFO_ACCESS */
2375
2376	#ifdef DEBUG_GMR_ACCESS
2377	# ifdef IN_RING3
2378
2379	/**
2380	* HC access handler for the FIFO.
2381	*
2382	* @returns VINF_SUCCESS if the handler have carried out the operation.
2383	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2384	* @param pVM VM Handle.
2385	* @param pVCpu The cross context CPU structure for the calling EMT.
2386	* @param GCPhys The physical address the guest is writing to.
2387	* @param pvPhys The HC mapping of that address.
2388	* @param pvBuf What the guest is reading/writing.
2389	* @param cbBuf How much it's reading/writing.
2390	* @param enmAccessType The access type.
2391	* @param enmOrigin Who is making the access.
2392	* @param pvUser User argument.
2393	*/
2394	static DECLCALLBACK(VBOXSTRICTRC)
2395	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2396	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2397	{
2398	PVGASTATE pThis = (PVGASTATE)pvUser;
2399	Assert(pThis);
2400	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2401	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2402
2403	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2404
2405	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2406	{
2407	PGMR pGMR = &pSVGAState->paGMR[i];
2408
2409	if (pGMR->numDescriptors)
2410	{
2411	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2412	{
2413	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2414	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2415	{
2416	/*
2417	* Turn off the write handler for this particular page and make it R/W.
2418	* Then return telling the caller to restart the guest instruction.
2419	*/
2420	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2421	AssertRC(rc);
2422	goto end;
2423	}
2424	}
2425	}
2426	}
2427	end:
2428	return VINF_PGM_HANDLER_DO_DEFAULT;
2429	}
2430
2431	/* Callback handler for VMR3ReqCallWaitU */
2432	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2433	{
2434	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2435	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2436	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2437	int rc;
2438
2439	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2440	{
2441	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2442	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2443	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2444	AssertRC(rc);
2445	}
2446	return VINF_SUCCESS;
2447	}
2448
2449	/* Callback handler for VMR3ReqCallWaitU */
2450	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2451	{
2452	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2453	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2454	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2455
2456	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2457	{
2458	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2459	AssertRC(rc);
2460	}
2461	return VINF_SUCCESS;
2462	}
2463
2464	/* Callback handler for VMR3ReqCallWaitU */
2465	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2466	{
2467	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2468
2469	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2470	{
2471	PGMR pGMR = &pSVGAState->paGMR[i];
2472
2473	if (pGMR->numDescriptors)
2474	{
2475	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2476	{
2477	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2478	AssertRC(rc);
2479	}
2480	}
2481	}
2482	return VINF_SUCCESS;
2483	}
2484
2485	# endif /* IN_RING3 */
2486	#endif /* DEBUG_GMR_ACCESS */
2487
2488	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2489
2490	#ifdef IN_RING3
2491
2492
2493	/**
2494	* Common worker for changing the pointer shape.
2495	*
2496	* @param pThis The VGA instance data.
2497	* @param pSVGAState The VMSVGA ring-3 instance data.
2498	* @param fAlpha Whether there is alpha or not.
2499	* @param xHot Hotspot x coordinate.
2500	* @param yHot Hotspot y coordinate.
2501	* @param cx Width.
2502	* @param cy Height.
2503	* @param pbData Heap copy of the cursor data. Consumed.
2504	* @param cbData The size of the data.
2505	*/
2506	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2507	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2508	{
2509	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2510	#ifdef LOG_ENABLED
2511	if (LogIs2Enabled())
2512	{
2513	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2514	if (!fAlpha)
2515	{
2516	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2517	for (uint32_t y = 0; y < cy; y++)
2518	{
2519	Log2(("%3u:", y));
2520	uint8_t const pbLine = &pbData[y cbAndLine];
2521	for (uint32_t x = 0; x < cx; x += 8)
2522	{
2523	uint8_t b = pbLine[x / 8];
2524	char szByte[12];
2525	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2526	szByte[1] = b & 0x40 ? '*' : ' ';
2527	szByte[2] = b & 0x20 ? '*' : ' ';
2528	szByte[3] = b & 0x10 ? '*' : ' ';
2529	szByte[4] = b & 0x08 ? '*' : ' ';
2530	szByte[5] = b & 0x04 ? '*' : ' ';
2531	szByte[6] = b & 0x02 ? '*' : ' ';
2532	szByte[7] = b & 0x01 ? '*' : ' ';
2533	szByte[8] = '\0';
2534	Log2(("%s", szByte));
2535	}
2536	Log2(("\n"));
2537	}
2538	}
2539
2540	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2541	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2542	for (uint32_t y = 0; y < cy; y++)
2543	{
2544	Log2(("%3u:", y));
2545	uint32_t const pu32Line = &pu32Xor[y cx];
2546	for (uint32_t x = 0; x < cx; x++)
2547	Log2((" %08x", pu32Line[x]));
2548	Log2(("\n"));
2549	}
2550	}
2551	#endif
2552
2553	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2554	AssertRC(rc);
2555
2556	if (pSVGAState->Cursor.fActive)
2557	RTMemFree(pSVGAState->Cursor.pData);
2558
2559	pSVGAState->Cursor.fActive = true;
2560	pSVGAState->Cursor.xHotspot = xHot;
2561	pSVGAState->Cursor.yHotspot = yHot;
2562	pSVGAState->Cursor.width = cx;
2563	pSVGAState->Cursor.height = cy;
2564	pSVGAState->Cursor.cbData = cbData;
2565	pSVGAState->Cursor.pData = pbData;
2566	}
2567
2568
2569	/**
2570	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2571	*
2572	* @param pThis The VGA instance data.
2573	* @param pSVGAState The VMSVGA ring-3 instance data.
2574	* @param pCursor The cursor.
2575	* @param pbSrcAndMask The AND mask.
2576	* @param cbSrcAndLine The scanline length of the AND mask.
2577	* @param pbSrcXorMask The XOR mask.
2578	* @param cbSrcXorLine The scanline length of the XOR mask.
2579	*/
2580	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2581	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2582	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2583	{
2584	uint32_t const cx = pCursor->width;
2585	uint32_t const cy = pCursor->height;
2586
2587	/*
2588	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2589	* The AND data uses 8-bit aligned scanlines.
2590	* The XOR data must be starting on a 32-bit boundrary.
2591	*/
2592	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2593	uint32_t cbDstAndMask = cbDstAndLine * cy;
2594	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2595	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2596
2597	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2598	AssertReturnVoid(pbCopy);
2599
2600	/* Convert the AND mask. */
2601	uint8_t *pbDst = pbCopy;
2602	uint8_t const *pbSrc = pbSrcAndMask;
2603	switch (pCursor->andMaskDepth)
2604	{
2605	case 1:
2606	if (cbSrcAndLine == cbDstAndLine)
2607	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2608	else
2609	{
2610	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2611	for (uint32_t y = 0; y < cy; y++)
2612	{
2613	memcpy(pbDst, pbSrc, cbDstAndLine);
2614	pbDst += cbDstAndLine;
2615	pbSrc += cbSrcAndLine;
2616	}
2617	}
2618	break;
2619	/* Should take the XOR mask into account for the multi-bit AND mask. */
2620	case 8:
2621	for (uint32_t y = 0; y < cy; y++)
2622	{
2623	for (uint32_t x = 0; x < cx; )
2624	{
2625	uint8_t bDst = 0;
2626	uint8_t fBit = 1;
2627	do
2628	{
2629	uintptr_t const idxPal = pbSrc[x] * 3;
2630	if ((( pThis->last_palette[idxPal]
2631	\| (pThis->last_palette[idxPal] >> 8)
2632	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2633	bDst \|= fBit;
2634	fBit <<= 1;
2635	x++;
2636	} while (x < cx && (x & 7));
2637	pbDst[(x - 1) / 8] = bDst;
2638	}
2639	pbDst += cbDstAndLine;
2640	pbSrc += cbSrcAndLine;
2641	}
2642	break;
2643	case 15:
2644	for (uint32_t y = 0; y < cy; y++)
2645	{
2646	for (uint32_t x = 0; x < cx; )
2647	{
2648	uint8_t bDst = 0;
2649	uint8_t fBit = 1;
2650	do
2651	{
2652	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2653	bDst \|= fBit;
2654	fBit <<= 1;
2655	x++;
2656	} while (x < cx && (x & 7));
2657	pbDst[(x - 1) / 8] = bDst;
2658	}
2659	pbDst += cbDstAndLine;
2660	pbSrc += cbSrcAndLine;
2661	}
2662	break;
2663	case 16:
2664	for (uint32_t y = 0; y < cy; y++)
2665	{
2666	for (uint32_t x = 0; x < cx; )
2667	{
2668	uint8_t bDst = 0;
2669	uint8_t fBit = 1;
2670	do
2671	{
2672	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2673	bDst \|= fBit;
2674	fBit <<= 1;
2675	x++;
2676	} while (x < cx && (x & 7));
2677	pbDst[(x - 1) / 8] = bDst;
2678	}
2679	pbDst += cbDstAndLine;
2680	pbSrc += cbSrcAndLine;
2681	}
2682	break;
2683	case 24:
2684	for (uint32_t y = 0; y < cy; y++)
2685	{
2686	for (uint32_t x = 0; x < cx; )
2687	{
2688	uint8_t bDst = 0;
2689	uint8_t fBit = 1;
2690	do
2691	{
2692	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2693	bDst \|= fBit;
2694	fBit <<= 1;
2695	x++;
2696	} while (x < cx && (x & 7));
2697	pbDst[(x - 1) / 8] = bDst;
2698	}
2699	pbDst += cbDstAndLine;
2700	pbSrc += cbSrcAndLine;
2701	}
2702	break;
2703	case 32:
2704	for (uint32_t y = 0; y < cy; y++)
2705	{
2706	for (uint32_t x = 0; x < cx; )
2707	{
2708	uint8_t bDst = 0;
2709	uint8_t fBit = 1;
2710	do
2711	{
2712	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2713	bDst \|= fBit;
2714	fBit <<= 1;
2715	x++;
2716	} while (x < cx && (x & 7));
2717	pbDst[(x - 1) / 8] = bDst;
2718	}
2719	pbDst += cbDstAndLine;
2720	pbSrc += cbSrcAndLine;
2721	}
2722	break;
2723	default:
2724	RTMemFree(pbCopy);
2725	AssertFailedReturnVoid();
2726	}
2727
2728	/* Convert the XOR mask. */
2729	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2730	pbSrc = pbSrcXorMask;
2731	switch (pCursor->xorMaskDepth)
2732	{
2733	case 1:
2734	for (uint32_t y = 0; y < cy; y++)
2735	{
2736	for (uint32_t x = 0; x < cx; )
2737	{
2738	/* most significant bit is the left most one. */
2739	uint8_t bSrc = pbSrc[x / 8];
2740	do
2741	{
2742	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2743	bSrc <<= 1;
2744	x++;
2745	} while ((x & 7) && x < cx);
2746	}
2747	pbSrc += cbSrcXorLine;
2748	}
2749	break;
2750	case 8:
2751	for (uint32_t y = 0; y < cy; y++)
2752	{
2753	for (uint32_t x = 0; x < cx; x++)
2754	{
2755	uint32_t u = pThis->last_palette[pbSrc[x]];
2756	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2757	}
2758	pbSrc += cbSrcXorLine;
2759	}
2760	break;
2761	case 15: /* Src: RGB-5-5-5 */
2762	for (uint32_t y = 0; y < cy; y++)
2763	{
2764	for (uint32_t x = 0; x < cx; x++)
2765	{
2766	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2767	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2768	((uValue >> 5) & 0x1f) << 3,
2769	((uValue >> 10) & 0x1f) << 3, 0);
2770	}
2771	pbSrc += cbSrcXorLine;
2772	}
2773	break;
2774	case 16: /* Src: RGB-5-6-5 */
2775	for (uint32_t y = 0; y < cy; y++)
2776	{
2777	for (uint32_t x = 0; x < cx; x++)
2778	{
2779	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2780	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2781	((uValue >> 5) & 0x3f) << 2,
2782	((uValue >> 11) & 0x1f) << 3, 0);
2783	}
2784	pbSrc += cbSrcXorLine;
2785	}
2786	break;
2787	case 24:
2788	for (uint32_t y = 0; y < cy; y++)
2789	{
2790	for (uint32_t x = 0; x < cx; x++)
2791	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2792	pbSrc += cbSrcXorLine;
2793	}
2794	break;
2795	case 32:
2796	for (uint32_t y = 0; y < cy; y++)
2797	{
2798	for (uint32_t x = 0; x < cx; x++)
2799	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2800	pbSrc += cbSrcXorLine;
2801	}
2802	break;
2803	default:
2804	RTMemFree(pbCopy);
2805	AssertFailedReturnVoid();
2806	}
2807
2808	/*
2809	* Pass it to the frontend/whatever.
2810	*/
2811	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2812	}
2813
2814
2815	/**
2816	* Worker for vmsvgaR3FifoThread that handles an external command.
2817	*
2818	* @param pThis VGA device instance data.
2819	*/
2820	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2821	{
2822	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2823	switch (pThis->svga.u8FIFOExtCommand)
2824	{
2825	case VMSVGA_FIFO_EXTCMD_RESET:
2826	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2827	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2828	# ifdef VBOX_WITH_VMSVGA3D
2829	if (pThis->svga.f3DEnabled)
2830	{
2831	/* The 3d subsystem must be reset from the fifo thread. */
2832	vmsvga3dReset(pThis);
2833	}
2834	# endif
2835	break;
2836
2837	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2838	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2839	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2840	# ifdef VBOX_WITH_VMSVGA3D
2841	if (pThis->svga.f3DEnabled)
2842	{
2843	/* The 3d subsystem must be shut down from the fifo thread. */
2844	vmsvga3dTerminate(pThis);
2845	}
2846	# endif
2847	break;
2848
2849	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2850	{
2851	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2852	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2853	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2854	vmsvgaSaveExecFifo(pThis, pSSM);
2855	# ifdef VBOX_WITH_VMSVGA3D
2856	if (pThis->svga.f3DEnabled)
2857	vmsvga3dSaveExec(pThis, pSSM);
2858	# endif
2859	break;
2860	}
2861
2862	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2863	{
2864	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2865	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2866	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2867	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2868	# ifdef VBOX_WITH_VMSVGA3D
2869	if (pThis->svga.f3DEnabled)
2870	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2871	# endif
2872	break;
2873	}
2874
2875	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2876	{
2877	# ifdef VBOX_WITH_VMSVGA3D
2878	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2879	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2880	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2881	# endif
2882	break;
2883	}
2884
2885
2886	default:
2887	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2888	break;
2889	}
2890
2891	/*
2892	* Signal the end of the external command.
2893	*/
2894	pThis->svga.pvFIFOExtCmdParam = NULL;
2895	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2896	ASMMemoryFence(); /* paranoia^2 */
2897	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2898	AssertLogRelRC(rc);
2899	}
2900
2901	/**
2902	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2903	* doing a job on the FIFO thread (even when it's officially suspended).
2904	*
2905	* @returns VBox status code (fully asserted).
2906	* @param pThis VGA device instance data.
2907	* @param uExtCmd The command to execute on the FIFO thread.
2908	* @param pvParam Pointer to command parameters.
2909	* @param cMsWait The time to wait for the command, given in
2910	* milliseconds.
2911	*/
2912	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2913	{
2914	Assert(cMsWait >= RT_MS_1SEC * 5);
2915	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2916	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2917
2918	int rc;
2919	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2920	PDMTHREADSTATE enmState = pThread->enmState;
2921	if (enmState == PDMTHREADSTATE_SUSPENDED)
2922	{
2923	/*
2924	* The thread is suspended, we have to temporarily wake it up so it can
2925	* perform the task.
2926	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2927	*/
2928	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2929	/* Post the request. */
2930	pThis->svga.fFifoExtCommandWakeup = true;
2931	pThis->svga.pvFIFOExtCmdParam = pvParam;
2932	pThis->svga.u8FIFOExtCommand = uExtCmd;
2933	ASMMemoryFence(); /* paranoia^3 */
2934
2935	/* Resume the thread. */
2936	rc = PDMR3ThreadResume(pThread);
2937	AssertLogRelRC(rc);
2938	if (RT_SUCCESS(rc))
2939	{
2940	/* Wait. Take care in case the semaphore was already posted (same as below). */
2941	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2942	if ( rc == VINF_SUCCESS
2943	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2944	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2945	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2946	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2947
2948	/* suspend the thread */
2949	pThis->svga.fFifoExtCommandWakeup = false;
2950	int rc2 = PDMR3ThreadSuspend(pThread);
2951	AssertLogRelRC(rc2);
2952	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2953	rc = rc2;
2954	}
2955	pThis->svga.fFifoExtCommandWakeup = false;
2956	pThis->svga.pvFIFOExtCmdParam = NULL;
2957	}
2958	else if (enmState == PDMTHREADSTATE_RUNNING)
2959	{
2960	/*
2961	* The thread is running, should only happen during reset and vmsvga3dsfc.
2962	* We ASSUME not racing code here, both wrt thread state and ext commands.
2963	*/
2964	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2965	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2966
2967	/* Post the request. */
2968	pThis->svga.pvFIFOExtCmdParam = pvParam;
2969	pThis->svga.u8FIFOExtCommand = uExtCmd;
2970	ASMMemoryFence(); /* paranoia^2 */
2971	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2972	AssertLogRelRC(rc);
2973
2974	/* Wait. Take care in case the semaphore was already posted (same as above). */
2975	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2976	if ( rc == VINF_SUCCESS
2977	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2978	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2979	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2980	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2981
2982	pThis->svga.pvFIFOExtCmdParam = NULL;
2983	}
2984	else
2985	{
2986	/*
2987	* Something is wrong with the thread!
2988	*/
2989	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2990	rc = VERR_INVALID_STATE;
2991	}
2992	return rc;
2993	}
2994
2995
2996	/**
2997	* Marks the FIFO non-busy, notifying any waiting EMTs.
2998	*
2999	* @param pThis The VGA state.
3000	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3001	* @param offFifoMin The start byte offset of the command FIFO.
3002	*/
3003	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3004	{
3005	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3006	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3007	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3008
3009	/* Wake up any waiting EMTs. */
3010	if (pSVGAState->cBusyDelayedEmts > 0)
3011	{
3012	#ifdef VMSVGA_USE_EMT_HALT_CODE
3013	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3014	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3015	if (idCpu != NIL_VMCPUID)
3016	{
3017	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3018	while (idCpu-- > 0)
3019	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3020	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3021	}
3022	#else
3023	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3024	AssertRC(rc2);
3025	#endif
3026	}
3027	}
3028
3029	/**
3030	* Reads (more) payload into the command buffer.
3031	*
3032	* @returns pbBounceBuf on success
3033	* @retval (void *)1 if the thread was requested to stop.
3034	* @retval NULL on FIFO error.
3035	*
3036	* @param cbPayloadReq The number of bytes of payload requested.
3037	* @param pFIFO The FIFO.
3038	* @param offCurrentCmd The FIFO byte offset of the current command.
3039	* @param offFifoMin The start byte offset of the command FIFO.
3040	* @param offFifoMax The end byte offset of the command FIFO.
3041	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3042	* always sufficient size.
3043	* @param pcbAlreadyRead How much payload we've already read into the bounce
3044	* buffer. (We will NEVER re-read anything.)
3045	* @param pThread The calling PDM thread handle.
3046	* @param pThis The VGA state.
3047	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3048	* statistics collection.
3049	*/
3050	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3051	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3052	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3053	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3054	{
3055	Assert(pbBounceBuf);
3056	Assert(pcbAlreadyRead);
3057	Assert(offFifoMin < offFifoMax);
3058	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3059	Assert(offFifoMax <= pThis->svga.cbFIFO);
3060
3061	/*
3062	* Check if the requested payload size has already been satisfied .
3063	* .
3064	* When called to read more, the caller is responsible for making sure the .
3065	* new command size (cbRequsted) never is smaller than what has already .
3066	* been read.
3067	*/
3068	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3069	if (cbPayloadReq <= cbAlreadyRead)
3070	{
3071	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3072	return pbBounceBuf;
3073	}
3074
3075	/*
3076	* Commands bigger than the fifo buffer are invalid.
3077	*/
3078	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3079	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3080	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3081	NULL);
3082
3083	/*
3084	* Move offCurrentCmd past the command dword.
3085	*/
3086	offCurrentCmd += sizeof(uint32_t);
3087	if (offCurrentCmd >= offFifoMax)
3088	offCurrentCmd = offFifoMin;
3089
3090	/*
3091	* Do we have sufficient payload data available already?
3092	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3093	*/
3094	uint32_t cbAfter, cbBefore;
3095	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3096	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3097	if (offNextCmd >= offCurrentCmd)
3098	{
3099	if (RT_LIKELY(offNextCmd < offFifoMax))
3100	cbAfter = offNextCmd - offCurrentCmd;
3101	else
3102	{
3103	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3104	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3105	offNextCmd, offFifoMin, offFifoMax));
3106	cbAfter = offFifoMax - offCurrentCmd;
3107	}
3108	cbBefore = 0;
3109	}
3110	else
3111	{
3112	cbAfter = offFifoMax - offCurrentCmd;
3113	if (offNextCmd >= offFifoMin)
3114	cbBefore = offNextCmd - offFifoMin;
3115	else
3116	{
3117	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3118	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3119	offNextCmd, offFifoMin, offFifoMax));
3120	cbBefore = 0;
3121	}
3122	}
3123	if (cbAfter + cbBefore < cbPayloadReq)
3124	{
3125	/*
3126	* Insufficient, must wait for it to arrive.
3127	*/
3128	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3129	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3130	for (uint32_t i = 0;; i++)
3131	{
3132	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3133	{
3134	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3135	return (void *)(uintptr_t)1;
3136	}
3137	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3138	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3139
3140	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3141
3142	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3143	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3144	if (offNextCmd >= offCurrentCmd)
3145	{
3146	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3147	cbBefore = 0;
3148	}
3149	else
3150	{
3151	cbAfter = offFifoMax - offCurrentCmd;
3152	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3153	}
3154
3155	if (cbAfter + cbBefore >= cbPayloadReq)
3156	break;
3157	}
3158	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3159	}
3160
3161	/*
3162	* Copy out the memory and update what pcbAlreadyRead points to.
3163	*/
3164	if (cbAfter >= cbPayloadReq)
3165	memcpy(pbBounceBuf + cbAlreadyRead,
3166	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3167	cbPayloadReq - cbAlreadyRead);
3168	else
3169	{
3170	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3171	if (cbAlreadyRead < cbAfter)
3172	{
3173	memcpy(pbBounceBuf + cbAlreadyRead,
3174	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3175	cbAfter - cbAlreadyRead);
3176	cbAlreadyRead = cbAfter;
3177	}
3178	memcpy(pbBounceBuf + cbAlreadyRead,
3179	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3180	cbPayloadReq - cbAlreadyRead);
3181	}
3182	*pcbAlreadyRead = cbPayloadReq;
3183	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3184	return pbBounceBuf;
3185	}
3186
3187	/* The async FIFO handling thread. */
3188	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3189	{
3190	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3191	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3192	int rc;
3193
3194	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3195	return VINF_SUCCESS;
3196
3197	/*
3198	* Special mode where we only execute an external command and the go back
3199	* to being suspended. Currently, all ext cmds ends up here, with the reset
3200	* one also being eligble for runtime execution further down as well.
3201	*/
3202	if (pThis->svga.fFifoExtCommandWakeup)
3203	{
3204	vmsvgaR3FifoHandleExtCmd(pThis);
3205	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3206	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3207	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3208	else
3209	vmsvgaR3FifoHandleExtCmd(pThis);
3210	return VINF_SUCCESS;
3211	}
3212
3213
3214	/*
3215	* Signal the semaphore to make sure we don't wait for 250ms after a
3216	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3217	*/
3218	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3219
3220	/*
3221	* Allocate a bounce buffer for command we get from the FIFO.
3222	* (All code must return via the end of the function to free this buffer.)
3223	*/
3224	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3225	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3226
3227	/*
3228	* Polling/sleep interval config.
3229	*
3230	* We wait for an a short interval if the guest has recently given us work
3231	* to do, but the interval increases the longer we're kept idle. With the
3232	* current parameters we'll be at a 64ms poll interval after 1 idle second,
3233	* at 90ms after 2 seconds, and reach the max 250ms interval after about
3234	* 16 seconds.
3235	*/
3236	RTMSINTERVAL const cMsMinSleep = 16;
3237	RTMSINTERVAL const cMsIncSleep = 2;
3238	RTMSINTERVAL const cMsMaxSleep = 250;
3239	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3240
3241	/*
3242	* The FIFO loop.
3243	*/
3244	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3245	bool fBadOrDisabledFifo = false;
3246	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3247	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3248	{
3249	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3250	/*
3251	* Should service the run loop every so often.
3252	*/
3253	if (pThis->svga.f3DEnabled)
3254	vmsvga3dCocoaServiceRunLoop();
3255	# endif
3256
3257	/*
3258	* Unless there's already work pending, go to sleep for a short while.
3259	* (See polling/sleep interval config above.)
3260	*/
3261	if ( fBadOrDisabledFifo
3262	\|\| pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3263	{
3264	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3265	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3266	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3267	{
3268	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3269	break;
3270	}
3271	}
3272	else
3273	rc = VINF_SUCCESS;
3274	fBadOrDisabledFifo = false;
3275	if (rc == VERR_TIMEOUT)
3276	{
3277	if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
3278	{
3279	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3280	continue;
3281	}
3282	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3283
3284	Log(("vmsvgaFIFOLoop: timeout\n"));
3285	}
3286	else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3287	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3288	cMsSleep = cMsMinSleep;
3289
3290	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3291	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3292	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3293
3294	/*
3295	* Handle external commands (currently only reset).
3296	*/
3297	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3298	{
3299	vmsvgaR3FifoHandleExtCmd(pThis);
3300	continue;
3301	}
3302
3303	/*
3304	* The device must be enabled and configured.
3305	*/
3306	if ( !pThis->svga.fEnabled
3307	\|\| !pThis->svga.fConfigured)
3308	{
3309	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3310	fBadOrDisabledFifo = true;
3311	continue;
3312	}
3313
3314	/*
3315	* Get and check the min/max values. We ASSUME that they will remain
3316	* unchanged while we process requests. A further ASSUMPTION is that
3317	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3318	* we don't read it back while in the loop.
3319	*/
3320	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3321	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3322	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3323	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3324	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3325	\|\| offFifoMax <= offFifoMin
3326	\|\| offFifoMax > pThis->svga.cbFIFO
3327	\|\| (offFifoMax & 3) != 0
3328	\|\| (offFifoMin & 3) != 0
3329	\|\| offCurrentCmd < offFifoMin
3330	\|\| offCurrentCmd > offFifoMax))
3331	{
3332	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3333	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3334	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3335	fBadOrDisabledFifo = true;
3336	continue;
3337	}
3338	RT_UNTRUSTED_VALIDATED_FENCE();
3339	if (RT_UNLIKELY(offCurrentCmd & 3))
3340	{
3341	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3342	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3343	offCurrentCmd = ~UINT32_C(3);
3344	}
3345
3346	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3347	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3348	*
3349	* Will break out of the switch on failure.
3350	* Will restart and quit the loop if the thread was requested to stop.
3351	*
3352	* @param a_PtrVar Request variable pointer.
3353	* @param a_Type Request typedef (not pointer) for casting.
3354	* @param a_cbPayloadReq How much payload to fetch.
3355	* @remarks Accesses a bunch of variables in the current scope!
3356	*/
3357	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3358	if (1) { \
3359	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3360	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3361	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3362	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3363	} else do {} while (0)
3364	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3365	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3366	* buffer after figuring out the actual command size.
3367	*
3368	* Will break out of the switch on failure.
3369	*
3370	* @param a_PtrVar Request variable pointer.
3371	* @param a_Type Request typedef (not pointer) for casting.
3372	* @param a_cbPayloadReq How much payload to fetch.
3373	* @remarks Accesses a bunch of variables in the current scope!
3374	*/
3375	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3376	if (1) { \
3377	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3378	} else do {} while (0)
3379
3380	/*
3381	* Mark the FIFO as busy.
3382	*/
3383	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3384	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3385	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3386
3387	/*
3388	* Execute all queued FIFO commands.
3389	* Quit if pending external command or changes in the thread state.
3390	*/
3391	bool fDone = false;
3392	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3393	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3394	{
3395	uint32_t cbPayload = 0;
3396	uint32_t u32IrqStatus = 0;
3397
3398	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3399
3400	/* First check any pending actions. */
3401	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3402	{
3403	vmsvgaChangeMode(pThis);
3404	# ifdef VBOX_WITH_VMSVGA3D
3405	if (pThis->svga.p3dState != NULL)
3406	vmsvga3dChangeMode(pThis);
3407	# endif
3408	}
3409
3410	/* Check for pending external commands (reset). */
3411	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3412	break;
3413
3414	/*
3415	* Process the command.
3416	*/
3417	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3418	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3419	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3420	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3421	switch (enmCmdId)
3422	{
3423	case SVGA_CMD_INVALID_CMD:
3424	/* Nothing to do. */
3425	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3426	break;
3427
3428	case SVGA_CMD_FENCE:
3429	{
3430	SVGAFifoCmdFence *pCmdFence;
3431	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3432	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3433	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3434	{
3435	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3436	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3437
3438	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3439	{
3440	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3441	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3442	}
3443	else
3444	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3445	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3446	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3447	{
3448	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3449	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3450	}
3451	}
3452	else
3453	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3454	break;
3455	}
3456	case SVGA_CMD_UPDATE:
3457	case SVGA_CMD_UPDATE_VERBOSE:
3458	{
3459	SVGAFifoCmdUpdate *pUpdate;
3460	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3461	if (enmCmdId == SVGA_CMD_UPDATE)
3462	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3463	else
3464	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3465	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3466	/** @todo Multiple screens? */
3467	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3468	AssertBreak(pScreen);
3469	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3470	break;
3471	}
3472
3473	case SVGA_CMD_DEFINE_CURSOR:
3474	{
3475	/* Followed by bitmap data. */
3476	SVGAFifoCmdDefineCursor *pCursor;
3477	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3478	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3479
3480	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3481	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3482	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3483	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3484	AssertBreak(pCursor->andMaskDepth <= 32);
3485	AssertBreak(pCursor->xorMaskDepth <= 32);
3486	RT_UNTRUSTED_VALIDATED_FENCE();
3487
3488	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3489	uint32_t cbAndMask = cbAndLine * pCursor->height;
3490	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3491	uint32_t cbXorMask = cbXorLine * pCursor->height;
3492	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3493
3494	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3495	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3496	break;
3497	}
3498
3499	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3500	{
3501	/* Followed by bitmap data. */
3502	uint32_t cbCursorShape, cbAndMask;
3503	uint8_t *pCursorCopy;
3504	uint32_t cbCmd;
3505
3506	SVGAFifoCmdDefineAlphaCursor *pCursor;
3507	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3508	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3509
3510	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3511
3512	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3513	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3514	RT_UNTRUSTED_VALIDATED_FENCE();
3515
3516	/* Refetch the bitmap data as well. */
3517	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3518	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3519	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3520
3521	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3522	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3523	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3524	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3525
3526	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3527	AssertBreak(pCursorCopy);
3528
3529	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3530	memset(pCursorCopy, 0xff, cbAndMask);
3531	/* Colour data */
3532	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3533
3534	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3535	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3536	break;
3537	}
3538
3539	case SVGA_CMD_ESCAPE:
3540	{
3541	/* Followed by nsize bytes of data. */
3542	SVGAFifoCmdEscape *pEscape;
3543	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3544	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3545
3546	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3547	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3548	RT_UNTRUSTED_VALIDATED_FENCE();
3549	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3550	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3551
3552	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3553	{
3554	AssertBreak(pEscape->size >= sizeof(uint32_t));
3555	RT_UNTRUSTED_VALIDATED_FENCE();
3556	uint32_t cmd = (uint32_t )(pEscape + 1);
3557	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3558
3559	switch (cmd)
3560	{
3561	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3562	{
3563	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3564	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3565	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3566
3567	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3568	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3569	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3570
3571	RT_NOREF_PV(pVideoCmd);
3572	break;
3573
3574	}
3575
3576	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3577	{
3578	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3579	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3580	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3581	RT_NOREF_PV(pVideoCmd);
3582	break;
3583	}
3584
3585	default:
3586	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3587	break;
3588	}
3589	}
3590	else
3591	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3592
3593	break;
3594	}
3595	# ifdef VBOX_WITH_VMSVGA3D
3596	case SVGA_CMD_DEFINE_GMR2:
3597	{
3598	SVGAFifoCmdDefineGMR2 *pCmd;
3599	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3600	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3601	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3602
3603	/* Validate current GMR id. */
3604	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3605	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3606	RT_UNTRUSTED_VALIDATED_FENCE();
3607
3608	if (!pCmd->numPages)
3609	{
3610	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3611	vmsvgaGMRFree(pThis, pCmd->gmrId);
3612	}
3613	else
3614	{
3615	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3616	if (pGMR->cMaxPages)
3617	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3618
3619	/* Not sure if we should always free the descriptor, but for simplicity
3620	we do so if the new size is smaller than the current. */
3621	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3622	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3623	vmsvgaGMRFree(pThis, pCmd->gmrId);
3624
3625	pGMR->cMaxPages = pCmd->numPages;
3626	/* The rest is done by the REMAP_GMR2 command. */
3627	}
3628	break;
3629	}
3630
3631	case SVGA_CMD_REMAP_GMR2:
3632	{
3633	/* Followed by page descriptors or guest ptr. */
3634	SVGAFifoCmdRemapGMR2 *pCmd;
3635	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3637
3638	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3639	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3640	RT_UNTRUSTED_VALIDATED_FENCE();
3641
3642	/* Calculate the size of what comes after next and fetch it. */
3643	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3644	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3645	cbCmd += sizeof(SVGAGuestPtr);
3646	else
3647	{
3648	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3649	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3650	{
3651	cbCmd += cbPageDesc;
3652	pCmd->numPages = 1;
3653	}
3654	else
3655	{
3656	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3657	cbCmd += cbPageDesc * pCmd->numPages;
3658	}
3659	}
3660	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3661
3662	/* Validate current GMR id and size. */
3663	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3664	RT_UNTRUSTED_VALIDATED_FENCE();
3665	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3666	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3667	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3668	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3669
3670	if (pCmd->numPages == 0)
3671	break;
3672
3673	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3674	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3675
3676	/*
3677	* We flatten the existing descriptors into a page array, overwrite the
3678	* pages specified in this command and then recompress the descriptor.
3679	*/
3680	/** @todo Optimize the GMR remap algorithm! */
3681
3682	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3683	uint64_t *paNewPage64 = NULL;
3684	if (pGMR->paDesc)
3685	{
3686	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3687
3688	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3689	AssertBreak(paNewPage64);
3690
3691	uint32_t idxPage = 0;
3692	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3693	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3694	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3695	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3696	RT_UNTRUSTED_VALIDATED_FENCE();
3697	}
3698
3699	/* Free the old GMR if present. */
3700	if (pGMR->paDesc)
3701	RTMemFree(pGMR->paDesc);
3702
3703	/* Allocate the maximum amount possible (everything non-continuous) */
3704	PVMSVGAGMRDESCRIPTOR paDescs;
3705	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3706	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3707
3708	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3709	{
3710	/** @todo */
3711	AssertFailed();
3712	pGMR->numDescriptors = 0;
3713	}
3714	else
3715	{
3716	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3717	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3718	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3719
3720	if (paNewPage64)
3721	{
3722	/* Overwrite the old page array with the new page values. */
3723	if (fGCPhys64)
3724	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3725	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3726	else
3727	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3728	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3729
3730	/* Use the updated page array instead of the command data. */
3731	fGCPhys64 = true;
3732	paPages64 = paNewPage64;
3733	pCmd->numPages = cNewTotalPages;
3734	}
3735
3736	/* The first page. */
3737	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3738	* applied to paNewPage64. */
3739	RTGCPHYS GCPhys;
3740	if (fGCPhys64)
3741	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3742	else
3743	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3744	paDescs[0].GCPhys = GCPhys;
3745	paDescs[0].numPages = 1;
3746
3747	/* Subsequent pages. */
3748	uint32_t iDescriptor = 0;
3749	for (uint32_t i = 1; i < pCmd->numPages; i++)
3750	{
3751	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3752	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3753	else
3754	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3755
3756	/* Continuous physical memory? */
3757	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3758	{
3759	Assert(paDescs[iDescriptor].numPages);
3760	paDescs[iDescriptor].numPages++;
3761	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3762	}
3763	else
3764	{
3765	iDescriptor++;
3766	paDescs[iDescriptor].GCPhys = GCPhys;
3767	paDescs[iDescriptor].numPages = 1;
3768	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3769	}
3770	}
3771
3772	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3773	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3774	pGMR->numDescriptors = iDescriptor + 1;
3775	}
3776
3777	if (paNewPage64)
3778	RTMemFree(paNewPage64);
3779
3780	# ifdef DEBUG_GMR_ACCESS
3781	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3782	# endif
3783	break;
3784	}
3785	# endif // VBOX_WITH_VMSVGA3D
3786	case SVGA_CMD_DEFINE_SCREEN:
3787	{
3788	/* The size of this command is specified by the guest and depends on capabilities. */
3789	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
3790
3791	SVGAFifoCmdDefineScreen *pCmd;
3792	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3793	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
3794	RT_UNTRUSTED_VALIDATED_FENCE();
3795
3796	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
3797	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
3798	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
3799
3800	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
3801	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
3802	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
3803
3804	AssertBreak(pCmd->screen.id < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3805
3806	uint32_t const uWidth = pCmd->screen.size.width;
3807	AssertBreak(0 < uWidth && uWidth <= pThis->svga.u32MaxWidth);
3808
3809	uint32_t const uHeight = pCmd->screen.size.height;
3810	AssertBreak(0 < uHeight && uHeight <= pThis->svga.u32MaxHeight);
3811
3812	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
3813	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
3814	AssertBreak(0 < cbWidth && cbWidth <= cbPitch);
3815
3816	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
3817	AssertBreak(uScreenOffset < pThis->vram_size);
3818
3819	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
3820	AssertBreak(uHeight <= cbVram / cbPitch);
3821	RT_UNTRUSTED_VALIDATED_FENCE();
3822
3823	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screen.id];
3824	pScreen->fDefined = true;
3825	pScreen->fModified = true;
3826	pScreen->fuScreen = pCmd->screen.flags;
3827	pScreen->idScreen = pCmd->screen.id;
3828	pScreen->xOrigin = pCmd->screen.root.x;
3829	pScreen->yOrigin = pCmd->screen.root.y;
3830	pScreen->cWidth = uWidth;
3831	pScreen->cHeight = uHeight;
3832	pScreen->offVRAM = uScreenOffset;
3833	pScreen->cbPitch = cbPitch;
3834	pScreen->cBpp = 32;
3835
3836	pThis->svga.fGFBRegisters = false;
3837	vmsvgaChangeMode(pThis);
3838	break;
3839	}
3840
3841	case SVGA_CMD_DESTROY_SCREEN:
3842	{
3843	SVGAFifoCmdDestroyScreen *pCmd;
3844	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
3845	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
3846
3847	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
3848	AssertBreak(pCmd->screenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3849	RT_UNTRUSTED_VALIDATED_FENCE();
3850
3851	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[pCmd->screenId];
3852	pScreen->fModified = true;
3853	pScreen->fDefined = false;
3854
3855	vmsvgaChangeMode(pThis);
3856	break;
3857	}
3858
3859	case SVGA_CMD_DEFINE_GMRFB:
3860	{
3861	SVGAFifoCmdDefineGMRFB *pCmd;
3862	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
3863	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
3864
3865	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
3866	pSVGAState->GMRFB.ptr = pCmd->ptr;
3867	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
3868	pSVGAState->GMRFB.format = pCmd->format;
3869	break;
3870	}
3871
3872	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3873	{
3874	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
3875	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
3876	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
3877
3878	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
3879	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
3880
3881	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3882	RT_UNTRUSTED_VALIDATED_FENCE();
3883
3884	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
3885	AssertBreak(pScreen);
3886
3887	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3888	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3889
3890	/* Clip destRect to the screen dimensions. */
3891	SVGASignedRect screenRect;
3892	screenRect.left = 0;
3893	screenRect.top = 0;
3894	screenRect.right = pScreen->cWidth;
3895	screenRect.bottom = pScreen->cHeight;
3896	SVGASignedRect clipRect = pCmd->destRect;
3897	vmsvgaClipRect(&screenRect, &clipRect);
3898	RT_UNTRUSTED_VALIDATED_FENCE();
3899
3900	uint32_t const width = clipRect.right - clipRect.left;
3901	uint32_t const height = clipRect.bottom - clipRect.top;
3902
3903	if ( width == 0
3904	\|\| height == 0)
3905	break; /* Nothing to do. */
3906
3907	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
3908	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
3909
3910	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3911	* Prepare parameters for vmsvgaGMRTransfer.
3912	*/
3913	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3914
3915	/* Destination: host buffer which describes the screen 0 VRAM.
3916	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3917	*/
3918	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3919	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3920	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3921	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3922	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3923	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3924	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3925	+ cbScanline * clipRect.top;
3926	int32_t const cbHstPitch = cbScanline;
3927
3928	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
3929	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
3930	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
3931	+ pSVGAState->GMRFB.bytesPerLine * srcy;
3932	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
3933
3934	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
3935	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
3936	gstPtr, offGst, cbGstPitch,
3937	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
3938	AssertRC(rc);
3939	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
3940	break;
3941	}
3942
3943	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3944	{
3945	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3946	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3947	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
3948
3949	/* Note! This can fetch 3d render results as well!! */
3950	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
3951	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3952
3953	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
3954	RT_UNTRUSTED_VALIDATED_FENCE();
3955
3956	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
3957	AssertBreak(pScreen);
3958
3959	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
3960	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
3961
3962	/* Clip destRect to the screen dimensions. */
3963	SVGASignedRect screenRect;
3964	screenRect.left = 0;
3965	screenRect.top = 0;
3966	screenRect.right = pScreen->cWidth;
3967	screenRect.bottom = pScreen->cHeight;
3968	SVGASignedRect clipRect = pCmd->srcRect;
3969	vmsvgaClipRect(&screenRect, &clipRect);
3970	RT_UNTRUSTED_VALIDATED_FENCE();
3971
3972	uint32_t const width = clipRect.right - clipRect.left;
3973	uint32_t const height = clipRect.bottom - clipRect.top;
3974
3975	if ( width == 0
3976	\|\| height == 0)
3977	break; /* Nothing to do. */
3978
3979	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
3980	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
3981
3982	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
3983	* Prepare parameters for vmsvgaGMRTransfer.
3984	*/
3985	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
3986
3987	/* Source: host buffer which describes the screen 0 VRAM.
3988	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
3989	*/
3990	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
3991	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
3992	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
3993	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
3994	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
3995	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
3996	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
3997	+ cbScanline * clipRect.top;
3998	int32_t const cbHstPitch = cbScanline;
3999
4000	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4001	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4002	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4003	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4004	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4005
4006	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4007	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4008	gstPtr, offGst, cbGstPitch,
4009	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4010	AssertRC(rc);
4011	break;
4012	}
4013
4014	case SVGA_CMD_ANNOTATION_FILL:
4015	{
4016	SVGAFifoCmdAnnotationFill *pCmd;
4017	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4018	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4019
4020	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4021	pSVGAState->colorAnnotation = pCmd->color;
4022	break;
4023	}
4024
4025	case SVGA_CMD_ANNOTATION_COPY:
4026	{
4027	SVGAFifoCmdAnnotationCopy *pCmd;
4028	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4029	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4030
4031	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4032	AssertFailed();
4033	break;
4034	}
4035
4036	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4037
4038	default:
4039	# ifdef VBOX_WITH_VMSVGA3D
4040	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4041	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4042	{
4043	RT_UNTRUSTED_VALIDATED_FENCE();
4044
4045	/* All 3d commands start with a common header, which defines the size of the command. */
4046	SVGA3dCmdHeader *pHdr;
4047	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4048	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4049	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4050	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4051
4052	if (RT_LIKELY(pThis->svga.f3DEnabled))
4053	{ /* likely */ }
4054	else
4055	{
4056	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4057	break;
4058	}
4059
4060	/**
4061	* Check that the 3D command has at least a_cbMin of payload bytes after the
4062	* header. Will break out of the switch if it doesn't.
4063	*/
4064	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4065	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4066	RT_UNTRUSTED_VALIDATED_FENCE(); \
4067	} while (0)
4068	switch ((int)enmCmdId)
4069	{
4070	case SVGA_3D_CMD_SURFACE_DEFINE:
4071	{
4072	uint32_t cMipLevels;
4073	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4074	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4075	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4076
4077	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4078	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4079	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4080	# ifdef DEBUG_GMR_ACCESS
4081	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4082	# endif
4083	break;
4084	}
4085
4086	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4087	{
4088	uint32_t cMipLevels;
4089	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4090	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4091	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4092
4093	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4094	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4095	pCmd->multisampleCount, pCmd->autogenFilter,
4096	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4097	break;
4098	}
4099
4100	case SVGA_3D_CMD_SURFACE_DESTROY:
4101	{
4102	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4103	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4104	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4105	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4106	break;
4107	}
4108
4109	case SVGA_3D_CMD_SURFACE_COPY:
4110	{
4111	uint32_t cCopyBoxes;
4112	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4113	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4114	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4115
4116	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4117	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4118	break;
4119	}
4120
4121	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4122	{
4123	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4124	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4125	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4126
4127	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4128	break;
4129	}
4130
4131	case SVGA_3D_CMD_SURFACE_DMA:
4132	{
4133	uint32_t cCopyBoxes;
4134	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4135	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4136	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4137
4138	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4139	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4140	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4141	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4142	break;
4143	}
4144
4145	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4146	{
4147	uint32_t cRects;
4148	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4149	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4150	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4151
4152	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4153	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4154	break;
4155	}
4156
4157	case SVGA_3D_CMD_CONTEXT_DEFINE:
4158	{
4159	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4160	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4161	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4162
4163	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4164	break;
4165	}
4166
4167	case SVGA_3D_CMD_CONTEXT_DESTROY:
4168	{
4169	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4170	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4171	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4172
4173	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4174	break;
4175	}
4176
4177	case SVGA_3D_CMD_SETTRANSFORM:
4178	{
4179	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4180	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4181	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4182
4183	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4184	break;
4185	}
4186
4187	case SVGA_3D_CMD_SETZRANGE:
4188	{
4189	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4190	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4191	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4192
4193	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4194	break;
4195	}
4196
4197	case SVGA_3D_CMD_SETRENDERSTATE:
4198	{
4199	uint32_t cRenderStates;
4200	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4201	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4202	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4203
4204	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4205	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4206	break;
4207	}
4208
4209	case SVGA_3D_CMD_SETRENDERTARGET:
4210	{
4211	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4212	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4213	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4214
4215	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4216	break;
4217	}
4218
4219	case SVGA_3D_CMD_SETTEXTURESTATE:
4220	{
4221	uint32_t cTextureStates;
4222	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4223	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4224	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4225
4226	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4227	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4228	break;
4229	}
4230
4231	case SVGA_3D_CMD_SETMATERIAL:
4232	{
4233	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4234	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4235	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4236
4237	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4238	break;
4239	}
4240
4241	case SVGA_3D_CMD_SETLIGHTDATA:
4242	{
4243	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4244	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4245	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4246
4247	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4248	break;
4249	}
4250
4251	case SVGA_3D_CMD_SETLIGHTENABLED:
4252	{
4253	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4254	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4255	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4256
4257	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4258	break;
4259	}
4260
4261	case SVGA_3D_CMD_SETVIEWPORT:
4262	{
4263	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4264	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4265	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4266
4267	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4268	break;
4269	}
4270
4271	case SVGA_3D_CMD_SETCLIPPLANE:
4272	{
4273	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4274	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4275	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4276
4277	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4278	break;
4279	}
4280
4281	case SVGA_3D_CMD_CLEAR:
4282	{
4283	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4284	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4285	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4286
4287	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4288	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4289	break;
4290	}
4291
4292	case SVGA_3D_CMD_PRESENT:
4293	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4294	{
4295	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4296	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4297	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4298	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4299	else
4300	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4301
4302	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4303
4304	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4305	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4306	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4307	break;
4308	}
4309
4310	case SVGA_3D_CMD_SHADER_DEFINE:
4311	{
4312	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4313	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4314	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4315
4316	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4317	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4318	break;
4319	}
4320
4321	case SVGA_3D_CMD_SHADER_DESTROY:
4322	{
4323	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4326
4327	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4328	break;
4329	}
4330
4331	case SVGA_3D_CMD_SET_SHADER:
4332	{
4333	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4334	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4335	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4336
4337	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4338	break;
4339	}
4340
4341	case SVGA_3D_CMD_SET_SHADER_CONST:
4342	{
4343	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4344	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4345	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4346
4347	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4348	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4349	break;
4350	}
4351
4352	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4353	{
4354	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4355	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4356	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4357
4358	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4359	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4360	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4361	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4362	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4363
4364	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4365	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4366
4367	RT_UNTRUSTED_VALIDATED_FENCE();
4368
4369	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4370	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4371	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4372
4373	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4374	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4375	pNumRange, cVertexDivisor, pVertexDivisor);
4376	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4377	break;
4378	}
4379
4380	case SVGA_3D_CMD_SETSCISSORRECT:
4381	{
4382	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4383	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4384	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4385
4386	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4387	break;
4388	}
4389
4390	case SVGA_3D_CMD_BEGIN_QUERY:
4391	{
4392	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4393	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4394	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4395
4396	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4397	break;
4398	}
4399
4400	case SVGA_3D_CMD_END_QUERY:
4401	{
4402	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4403	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4404	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4405
4406	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4407	break;
4408	}
4409
4410	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4411	{
4412	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4413	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4414	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4415
4416	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4417	break;
4418	}
4419
4420	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4421	{
4422	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4423	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4424	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4425
4426	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4427	break;
4428	}
4429
4430	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4431	/* context id + surface id? */
4432	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4433	break;
4434	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4435	/* context id + surface id? */
4436	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4437	break;
4438
4439	default:
4440	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4441	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4442	break;
4443	}
4444	}
4445	else
4446	# endif // VBOX_WITH_VMSVGA3D
4447	{
4448	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4449	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4450	}
4451	}
4452
4453	/* Go to the next slot */
4454	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4455	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4456	if (offCurrentCmd >= offFifoMax)
4457	{
4458	offCurrentCmd -= offFifoMax - offFifoMin;
4459	Assert(offCurrentCmd >= offFifoMin);
4460	Assert(offCurrentCmd < offFifoMax);
4461	}
4462	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4463	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4464
4465	/*
4466	* Raise IRQ if required. Must enter the critical section here
4467	* before making final decisions here, otherwise cubebench and
4468	* others may end up waiting forever.
4469	*/
4470	if ( u32IrqStatus
4471	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4472	{
4473	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4474	AssertRC(rc2);
4475
4476	/* FIFO progress might trigger an interrupt. */
4477	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4478	{
4479	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4480	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4481	}
4482
4483	/* Unmasked IRQ pending? */
4484	if (pThis->svga.u32IrqMask & u32IrqStatus)
4485	{
4486	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4487	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4488	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4489	}
4490
4491	PDMCritSectLeave(&pThis->CritSect);
4492	}
4493	}
4494
4495	/* If really done, clear the busy flag. */
4496	if (fDone)
4497	{
4498	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4499	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4500	}
4501	}
4502
4503	/*
4504	* Free the bounce buffer. (There are no returns above!)
4505	*/
4506	RTMemFree(pbBounceBuf);
4507
4508	return VINF_SUCCESS;
4509	}
4510
4511	/**
4512	* Free the specified GMR
4513	*
4514	* @param pThis VGA device instance data.
4515	* @param idGMR GMR id
4516	*/
4517	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4518	{
4519	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4520
4521	/* Free the old descriptor if present. */
4522	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4523	if ( pGMR->numDescriptors
4524	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4525	{
4526	# ifdef DEBUG_GMR_ACCESS
4527	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4528	# endif
4529
4530	Assert(pGMR->paDesc);
4531	RTMemFree(pGMR->paDesc);
4532	pGMR->paDesc = NULL;
4533	pGMR->numDescriptors = 0;
4534	pGMR->cbTotal = 0;
4535	pGMR->cMaxPages = 0;
4536	}
4537	Assert(!pGMR->cMaxPages);
4538	Assert(!pGMR->cbTotal);
4539	}
4540
4541	/**
4542	* Copy between a GMR and a host memory buffer.
4543	*
4544	* @returns VBox status code.
4545	* @param pThis VGA device instance data.
4546	* @param enmTransferType Transfer type (read/write)
4547	* @param pbHstBuf Host buffer pointer (valid)
4548	* @param cbHstBuf Size of host buffer (valid)
4549	* @param offHst Host buffer offset of the first scanline
4550	* @param cbHstPitch Destination buffer pitch
4551	* @param gstPtr GMR description
4552	* @param offGst Guest buffer offset of the first scanline
4553	* @param cbGstPitch Guest buffer pitch
4554	* @param cbWidth Width in bytes to copy
4555	* @param cHeight Number of scanllines to copy
4556	*/
4557	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4558	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4559	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4560	uint32_t cbWidth, uint32_t cHeight)
4561	{
4562	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4563	int rc;
4564
4565	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4566	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4567	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4568	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4569	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4570
4571	PGMR pGMR;
4572	uint32_t cbGmr; /* The GMR size in bytes. */
4573	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4574	{
4575	pGMR = NULL;
4576	cbGmr = pThis->vram_size;
4577	}
4578	else
4579	{
4580	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4581	RT_UNTRUSTED_VALIDATED_FENCE();
4582	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4583	cbGmr = pGMR->cbTotal;
4584	}
4585
4586	/*
4587	* GMR
4588	*/
4589	/* Calculate GMR offset of the data to be copied. */
4590	AssertMsgReturn(gstPtr.offset < cbGmr,
4591	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4592	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4593	VERR_INVALID_PARAMETER);
4594	RT_UNTRUSTED_VALIDATED_FENCE();
4595	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4596	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4597	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4598	VERR_INVALID_PARAMETER);
4599	RT_UNTRUSTED_VALIDATED_FENCE();
4600	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4601
4602	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4603	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4604	AssertMsgReturn(cbGmrScanline != 0,
4605	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4606	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4607	VERR_INVALID_PARAMETER);
4608	RT_UNTRUSTED_VALIDATED_FENCE();
4609	AssertMsgReturn(cbWidth <= cbGmrScanline,
4610	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4611	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4612	VERR_INVALID_PARAMETER);
4613	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4614	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4615	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4616	VERR_INVALID_PARAMETER);
4617	RT_UNTRUSTED_VALIDATED_FENCE();
4618
4619	/* How many bytes are available for the data in the GMR. */
4620	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4621
4622	/* How many scanlines would fit into the available data. */
4623	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4624	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4625	if (cbWidth <= cbGmrLastScanline)
4626	++cGmrScanlines;
4627
4628	if (cHeight > cGmrScanlines)
4629	cHeight = cGmrScanlines;
4630
4631	AssertMsgReturn(cHeight > 0,
4632	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4633	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4634	VERR_INVALID_PARAMETER);
4635	RT_UNTRUSTED_VALIDATED_FENCE();
4636
4637	/*
4638	* Host buffer.
4639	*/
4640	AssertMsgReturn(offHst < cbHstBuf,
4641	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4642	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4643	VERR_INVALID_PARAMETER);
4644
4645	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4646	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4647	AssertMsgReturn(cbHstScanline != 0,
4648	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4649	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4650	VERR_INVALID_PARAMETER);
4651	AssertMsgReturn(cbWidth <= cbHstScanline,
4652	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4653	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4654	VERR_INVALID_PARAMETER);
4655	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4656	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4657	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4658	VERR_INVALID_PARAMETER);
4659
4660	/* How many bytes are available for the data in the buffer. */
4661	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4662
4663	/* How many scanlines would fit into the available data. */
4664	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4665	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4666	if (cbWidth <= cbHstLastScanline)
4667	++cHstScanlines;
4668
4669	if (cHeight > cHstScanlines)
4670	cHeight = cHstScanlines;
4671
4672	AssertMsgReturn(cHeight > 0,
4673	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4674	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4675	VERR_INVALID_PARAMETER);
4676
4677	uint8_t *pbHst = pbHstBuf + offHst;
4678
4679	/* Shortcut for the framebuffer. */
4680	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4681	{
4682	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4683
4684	uint8_t const *pbSrc;
4685	int32_t cbSrcPitch;
4686	uint8_t *pbDst;
4687	int32_t cbDstPitch;
4688
4689	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4690	{
4691	pbSrc = pbHst;
4692	cbSrcPitch = cbHstPitch;
4693	pbDst = pbGst;
4694	cbDstPitch = cbGstPitch;
4695	}
4696	else
4697	{
4698	pbSrc = pbGst;
4699	cbSrcPitch = cbGstPitch;
4700	pbDst = pbHst;
4701	cbDstPitch = cbHstPitch;
4702	}
4703
4704	if ( cbWidth == (uint32_t)cbGstPitch
4705	&& cbGstPitch == cbHstPitch)
4706	{
4707	/* Entire scanlines, positive pitch. */
4708	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4709	}
4710	else
4711	{
4712	for (uint32_t i = 0; i < cHeight; ++i)
4713	{
4714	memcpy(pbDst, pbSrc, cbWidth);
4715
4716	pbDst += cbDstPitch;
4717	pbSrc += cbSrcPitch;
4718	}
4719	}
4720	return VINF_SUCCESS;
4721	}
4722
4723	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4724	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4725
4726	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4727	uint32_t iDesc = 0; /* Index in the descriptor array. */
4728	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4729	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4730	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4731	for (uint32_t i = 0; i < cHeight; ++i)
4732	{
4733	uint32_t cbCurrentWidth = cbWidth;
4734	uint32_t offGmrCurrent = offGmrScanline;
4735	uint8_t *pbCurrentHost = pbHstScanline;
4736
4737	/* Find the right descriptor */
4738	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4739	{
4740	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4741	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4742	++iDesc;
4743	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4744	}
4745
4746	while (cbCurrentWidth)
4747	{
4748	uint32_t cbToCopy;
4749
4750	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4751	{
4752	cbToCopy = cbCurrentWidth;
4753	}
4754	else
4755	{
4756	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4757	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4758	}
4759
4760	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4761
4762	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4763
4764	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4765	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4766	else
4767	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4768	AssertRCBreak(rc);
4769
4770	cbCurrentWidth -= cbToCopy;
4771	offGmrCurrent += cbToCopy;
4772	pbCurrentHost += cbToCopy;
4773
4774	/* Go to the next descriptor if there's anything left. */
4775	if (cbCurrentWidth)
4776	{
4777	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4778	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
4779	++iDesc;
4780	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4781	}
4782	}
4783
4784	offGmrScanline += cbGstPitch;
4785	pbHstScanline += cbHstPitch;
4786	}
4787
4788	return VINF_SUCCESS;
4789	}
4790
4791
4792	/** Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0;pSizeDest).
4793	*
4794	* @param pSizeSrc Source surface dimensions.
4795	* @param pSizeDest Destination surface dimensions.
4796	* @param pBox Coordinates to be clipped.
4797	*/
4798	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
4799	const SVGA3dSize *pSizeDest,
4800	SVGA3dCopyBox *pBox)
4801	{
4802	/* Src x, w */
4803	if (pBox->srcx > pSizeSrc->width)
4804	pBox->srcx = pSizeSrc->width;
4805	if (pBox->w > pSizeSrc->width - pBox->srcx)
4806	pBox->w = pSizeSrc->width - pBox->srcx;
4807
4808	/* Src y, h */
4809	if (pBox->srcy > pSizeSrc->height)
4810	pBox->srcy = pSizeSrc->height;
4811	if (pBox->h > pSizeSrc->height - pBox->srcy)
4812	pBox->h = pSizeSrc->height - pBox->srcy;
4813
4814	/* Src z, d */
4815	if (pBox->srcz > pSizeSrc->depth)
4816	pBox->srcz = pSizeSrc->depth;
4817	if (pBox->d > pSizeSrc->depth - pBox->srcz)
4818	pBox->d = pSizeSrc->depth - pBox->srcz;
4819
4820	/* Dest x, w */
4821	if (pBox->x > pSizeDest->width)
4822	pBox->x = pSizeDest->width;
4823	if (pBox->w > pSizeDest->width - pBox->x)
4824	pBox->w = pSizeDest->width - pBox->x;
4825
4826	/* Dest y, h */
4827	if (pBox->y > pSizeDest->height)
4828	pBox->y = pSizeDest->height;
4829	if (pBox->h > pSizeDest->height - pBox->y)
4830	pBox->h = pSizeDest->height - pBox->y;
4831
4832	/* Dest z, d */
4833	if (pBox->z > pSizeDest->depth)
4834	pBox->z = pSizeDest->depth;
4835	if (pBox->d > pSizeDest->depth - pBox->z)
4836	pBox->d = pSizeDest->depth - pBox->z;
4837	}
4838
4839	/** Unsigned coordinates in pBox. Clip to [0; pSize).
4840	*
4841	* @param pSize Source surface dimensions.
4842	* @param pBox Coordinates to be clipped.
4843	*/
4844	void vmsvgaClipBox(const SVGA3dSize *pSize,
4845	SVGA3dBox *pBox)
4846	{
4847	/* x, w */
4848	if (pBox->x > pSize->width)
4849	pBox->x = pSize->width;
4850	if (pBox->w > pSize->width - pBox->x)
4851	pBox->w = pSize->width - pBox->x;
4852
4853	/* y, h */
4854	if (pBox->y > pSize->height)
4855	pBox->y = pSize->height;
4856	if (pBox->h > pSize->height - pBox->y)
4857	pBox->h = pSize->height - pBox->y;
4858
4859	/* z, d */
4860	if (pBox->z > pSize->depth)
4861	pBox->z = pSize->depth;
4862	if (pBox->d > pSize->depth - pBox->z)
4863	pBox->d = pSize->depth - pBox->z;
4864	}
4865
4866	/** Clip.
4867	*
4868	* @param pBound Bounding rectangle.
4869	* @param pRect Rectangle to be clipped.
4870	*/
4871	void vmsvgaClipRect(SVGASignedRect const *pBound,
4872	SVGASignedRect *pRect)
4873	{
4874	int32_t left;
4875	int32_t top;
4876	int32_t right;
4877	int32_t bottom;
4878
4879	/* Right order. */
4880	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
4881	if (pRect->left < pRect->right)
4882	{
4883	left = pRect->left;
4884	right = pRect->right;
4885	}
4886	else
4887	{
4888	left = pRect->right;
4889	right = pRect->left;
4890	}
4891	if (pRect->top < pRect->bottom)
4892	{
4893	top = pRect->top;
4894	bottom = pRect->bottom;
4895	}
4896	else
4897	{
4898	top = pRect->bottom;
4899	bottom = pRect->top;
4900	}
4901
4902	if (left < pBound->left)
4903	left = pBound->left;
4904	if (right < pBound->left)
4905	right = pBound->left;
4906
4907	if (left > pBound->right)
4908	left = pBound->right;
4909	if (right > pBound->right)
4910	right = pBound->right;
4911
4912	if (top < pBound->top)
4913	top = pBound->top;
4914	if (bottom < pBound->top)
4915	bottom = pBound->top;
4916
4917	if (top > pBound->bottom)
4918	top = pBound->bottom;
4919	if (bottom > pBound->bottom)
4920	bottom = pBound->bottom;
4921
4922	pRect->left = left;
4923	pRect->right = right;
4924	pRect->top = top;
4925	pRect->bottom = bottom;
4926	}
4927
4928	/**
4929	* Unblock the FIFO I/O thread so it can respond to a state change.
4930	*
4931	* @returns VBox status code.
4932	* @param pDevIns The VGA device instance.
4933	* @param pThread The send thread.
4934	*/
4935	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4936	{
4937	RT_NOREF(pDevIns);
4938	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
4939	Log(("vmsvgaFIFOLoopWakeUp\n"));
4940	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4941	}
4942
4943	/**
4944	* Enables or disables dirty page tracking for the framebuffer
4945	*
4946	* @param pThis VGA device instance data.
4947	* @param fTraces Enable/disable traces
4948	*/
4949	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
4950	{
4951	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
4952	&& !fTraces)
4953	{
4954	//Assert(pThis->svga.fTraces);
4955	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
4956	return;
4957	}
4958
4959	pThis->svga.fTraces = fTraces;
4960	if (pThis->svga.fTraces)
4961	{
4962	unsigned cbFrameBuffer = pThis->vram_size;
4963
4964	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
4965	/** @todo How this works with screens? */
4966	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
4967	{
4968	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
4969	Assert(pThis->svga.cbScanline);
4970	#endif
4971	/* Hardware enabled; return real framebuffer size .*/
4972	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
4973	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
4974	}
4975
4976	if (!pThis->svga.fVRAMTracking)
4977	{
4978	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
4979	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
4980	pThis->svga.fVRAMTracking = true;
4981	}
4982	}
4983	else
4984	{
4985	if (pThis->svga.fVRAMTracking)
4986	{
4987	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
4988	vgaR3UnregisterVRAMHandler(pThis);
4989	pThis->svga.fVRAMTracking = false;
4990	}
4991	}
4992	}
4993
4994	/**
4995	* @callback_method_impl{FNPCIIOREGIONMAP}
4996	*/
4997	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4998	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4999	{
5000	int rc;
5001	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5002
5003	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5004	if (enmType == PCI_ADDRESS_SPACE_IO)
5005	{
5006	AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
5007	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5008	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5009	if (RT_FAILURE(rc))
5010	return rc;
5011	if (pThis->fR0Enabled)
5012	{
5013	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5014	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5015	if (RT_FAILURE(rc))
5016	return rc;
5017	}
5018	if (pThis->fGCEnabled)
5019	{
5020	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5021	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5022	if (RT_FAILURE(rc))
5023	return rc;
5024	}
5025
5026	pThis->svga.BasePort = GCPhysAddress;
5027	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5028	}
5029	else
5030	{
5031	AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5032	if (GCPhysAddress != NIL_RTGCPHYS)
5033	{
5034	/*
5035	* Mapping the FIFO RAM.
5036	*/
5037	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5038	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5039	AssertRC(rc);
5040
5041	# ifdef DEBUG_FIFO_ACCESS
5042	if (RT_SUCCESS(rc))
5043	{
5044	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->svga.cbFIFO - 1),
5045	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5046	"VMSVGA FIFO");
5047	AssertRC(rc);
5048	}
5049	# endif
5050	if (RT_SUCCESS(rc))
5051	{
5052	pThis->svga.GCPhysFIFO = GCPhysAddress;
5053	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5054	}
5055	}
5056	else
5057	{
5058	Assert(pThis->svga.GCPhysFIFO);
5059	# ifdef DEBUG_FIFO_ACCESS
5060	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5061	AssertRC(rc);
5062	# endif
5063	pThis->svga.GCPhysFIFO = 0;
5064	}
5065
5066	}
5067	return VINF_SUCCESS;
5068	}
5069
5070	# ifdef VBOX_WITH_VMSVGA3D
5071
5072	/**
5073	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5074	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5075	*
5076	* @param pThis The VGA device instance data.
5077	* @param sid Either UINT32_MAX or the ID of a specific
5078	* surface. If UINT32_MAX is used, all surfaces
5079	* are processed.
5080	*/
5081	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5082	{
5083	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5084	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5085	}
5086
5087
5088	/**
5089	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5090	*/
5091	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5092	{
5093	/* There might be a specific surface ID at the start of the
5094	arguments, if not show all surfaces. */
5095	uint32_t sid = UINT32_MAX;
5096	if (pszArgs)
5097	pszArgs = RTStrStripL(pszArgs);
5098	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5099	sid = RTStrToUInt32(pszArgs);
5100
5101	/* Verbose or terse display, we default to verbose. */
5102	bool fVerbose = true;
5103	if (RTStrIStr(pszArgs, "terse"))
5104	fVerbose = false;
5105
5106	/* The size of the ascii art (x direction, y is 3/4 of x). */
5107	uint32_t cxAscii = 80;
5108	if (RTStrIStr(pszArgs, "gigantic"))
5109	cxAscii = 300;
5110	else if (RTStrIStr(pszArgs, "huge"))
5111	cxAscii = 180;
5112	else if (RTStrIStr(pszArgs, "big"))
5113	cxAscii = 132;
5114	else if (RTStrIStr(pszArgs, "normal"))
5115	cxAscii = 80;
5116	else if (RTStrIStr(pszArgs, "medium"))
5117	cxAscii = 64;
5118	else if (RTStrIStr(pszArgs, "small"))
5119	cxAscii = 48;
5120	else if (RTStrIStr(pszArgs, "tiny"))
5121	cxAscii = 24;
5122
5123	/* Y invert the image when producing the ASCII art. */
5124	bool fInvY = false;
5125	if (RTStrIStr(pszArgs, "invy"))
5126	fInvY = true;
5127
5128	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5129	}
5130
5131
5132	/**
5133	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5134	*/
5135	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5136	{
5137	/* pszArg = "sid[>dir]"
5138	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5139	*/
5140	char *pszBitmapPath = NULL;
5141	uint32_t sid = UINT32_MAX;
5142	if (pszArgs)
5143	pszArgs = RTStrStripL(pszArgs);
5144	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5145	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5146	if ( pszBitmapPath
5147	&& *pszBitmapPath == '>')
5148	++pszBitmapPath;
5149
5150	const bool fVerbose = true;
5151	const uint32_t cxAscii = 0; /* No ASCII */
5152	const bool fInvY = false; /* Do not invert. */
5153	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5154	}
5155
5156
5157	/**
5158	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5159	*/
5160	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5161	{
5162	/* There might be a specific surface ID at the start of the
5163	arguments, if not show all contexts. */
5164	uint32_t sid = UINT32_MAX;
5165	if (pszArgs)
5166	pszArgs = RTStrStripL(pszArgs);
5167	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5168	sid = RTStrToUInt32(pszArgs);
5169
5170	/* Verbose or terse display, we default to verbose. */
5171	bool fVerbose = true;
5172	if (RTStrIStr(pszArgs, "terse"))
5173	fVerbose = false;
5174
5175	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5176	}
5177
5178	# endif /* VBOX_WITH_VMSVGA3D */
5179
5180	/**
5181	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5182	*/
5183	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5184	{
5185	RT_NOREF(pszArgs);
5186	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5187	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5188
5189	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5190	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5191	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5192	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5193	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5194	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5195	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5196	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5197	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5198	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5199	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5200	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5201	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5202	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5203	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5204	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5205	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5206	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5207	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5208	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5209	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5210	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5211
5212	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5213	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5214	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5215	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5216
5217	# ifdef VBOX_WITH_VMSVGA3D
5218	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5219	# endif
5220	}
5221
5222	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5223	*/
5224	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5225	{
5226	RT_NOREF(uPass);
5227
5228	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5229	int rc;
5230
5231	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5232	{
5233	uint32_t cScreens = 0;
5234	rc = SSMR3GetU32(pSSM, &cScreens);
5235	AssertRCReturn(rc, rc);
5236	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5237	("cScreens=%#x\n", cScreens),
5238	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5239
5240	for (uint32_t i = 0; i < cScreens; ++i)
5241	{
5242	VMSVGASCREENOBJECT screen;
5243	RT_ZERO(screen);
5244
5245	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5246	AssertLogRelRCReturn(rc, rc);
5247
5248	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5249	{
5250	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5251	*pScreen = screen;
5252	pScreen->fModified = true;
5253	}
5254	else
5255	{
5256	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5257	}
5258	}
5259	}
5260	else
5261	{
5262	/* Try to setup at least the first screen. */
5263	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5264	pScreen->fDefined = true;
5265	pScreen->fModified = true;
5266	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5267	pScreen->idScreen = 0;
5268	pScreen->xOrigin = 0;
5269	pScreen->yOrigin = 0;
5270	pScreen->offVRAM = pThis->svga.uScreenOffset;
5271	pScreen->cbPitch = pThis->svga.cbScanline;
5272	pScreen->cWidth = pThis->svga.uWidth;
5273	pScreen->cHeight = pThis->svga.uHeight;
5274	pScreen->cBpp = pThis->svga.uBpp;
5275	}
5276
5277	return VINF_SUCCESS;
5278	}
5279
5280	/**
5281	* @copydoc FNSSMDEVLOADEXEC
5282	*/
5283	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5284	{
5285	RT_NOREF(uPass);
5286	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5287	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5288	int rc;
5289
5290	/* Load our part of the VGAState */
5291	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5292	AssertRCReturn(rc, rc);
5293
5294	/* Load the VGA framebuffer. */
5295	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5296	uint32_t cbVgaFramebuffer = _32K;
5297	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5298	{
5299	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5300	AssertRCReturn(rc, rc);
5301	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5302	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5303	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5304	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5305	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5306	}
5307	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5308	AssertRCReturn(rc, rc);
5309	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5310	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5311	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5312	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5313
5314	/* Load the VMSVGA state. */
5315	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5316	AssertRCReturn(rc, rc);
5317
5318	/* Load the active cursor bitmaps. */
5319	if (pSVGAState->Cursor.fActive)
5320	{
5321	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5322	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5323
5324	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5325	AssertRCReturn(rc, rc);
5326	}
5327
5328	/* Load the GMR state. */
5329	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5330	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5331	{
5332	rc = SSMR3GetU32(pSSM, &cGMR);
5333	AssertRCReturn(rc, rc);
5334	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5335	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5336	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5337	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5338	}
5339
5340	if (pThis->svga.cGMR != cGMR)
5341	{
5342	/* Reallocate GMR array. */
5343	Assert(pSVGAState->paGMR != NULL);
5344	RTMemFree(pSVGAState->paGMR);
5345	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5346	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5347	pThis->svga.cGMR = cGMR;
5348	}
5349
5350	for (uint32_t i = 0; i < cGMR; ++i)
5351	{
5352	PGMR pGMR = &pSVGAState->paGMR[i];
5353
5354	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5355	AssertRCReturn(rc, rc);
5356
5357	if (pGMR->numDescriptors)
5358	{
5359	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5360	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5361	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5362
5363	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5364	{
5365	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5366	AssertRCReturn(rc, rc);
5367	}
5368	}
5369	}
5370
5371	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5372	vmsvga3dPowerOn(pThis);
5373	# endif
5374
5375	VMSVGA_STATE_LOAD LoadState;
5376	LoadState.pSSM = pSSM;
5377	LoadState.uVersion = uVersion;
5378	LoadState.uPass = uPass;
5379	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5380	AssertLogRelRCReturn(rc, rc);
5381
5382	return VINF_SUCCESS;
5383	}
5384
5385	/**
5386	* Reinit the video mode after the state has been loaded.
5387	*/
5388	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5389	{
5390	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5391	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5392
5393	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5394
5395	/* Set the active cursor. */
5396	if (pSVGAState->Cursor.fActive)
5397	{
5398	int rc;
5399
5400	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5401	true,
5402	true,
5403	pSVGAState->Cursor.xHotspot,
5404	pSVGAState->Cursor.yHotspot,
5405	pSVGAState->Cursor.width,
5406	pSVGAState->Cursor.height,
5407	pSVGAState->Cursor.pData);
5408	AssertRC(rc);
5409	}
5410	return VINF_SUCCESS;
5411	}
5412
5413	/**
5414	* Portion of SVGA state which must be saved in the FIFO thread.
5415	*/
5416	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5417	{
5418	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5419	int rc;
5420
5421	/* Save the screen objects. */
5422	/* Count defined screen object. */
5423	uint32_t cScreens = 0;
5424	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5425	{
5426	if (pSVGAState->aScreens[i].fDefined)
5427	++cScreens;
5428	}
5429
5430	rc = SSMR3PutU32(pSSM, cScreens);
5431	AssertLogRelRCReturn(rc, rc);
5432
5433	for (uint32_t i = 0; i < cScreens; ++i)
5434	{
5435	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5436
5437	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5438	AssertLogRelRCReturn(rc, rc);
5439	}
5440	return VINF_SUCCESS;
5441	}
5442
5443	/**
5444	* @copydoc FNSSMDEVSAVEEXEC
5445	*/
5446	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5447	{
5448	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5449	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5450	int rc;
5451
5452	/* Save our part of the VGAState */
5453	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5454	AssertLogRelRCReturn(rc, rc);
5455
5456	/* Save the framebuffer backup. */
5457	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5458	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5459	AssertLogRelRCReturn(rc, rc);
5460
5461	/* Save the VMSVGA state. */
5462	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5463	AssertLogRelRCReturn(rc, rc);
5464
5465	/* Save the active cursor bitmaps. */
5466	if (pSVGAState->Cursor.fActive)
5467	{
5468	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5469	AssertLogRelRCReturn(rc, rc);
5470	}
5471
5472	/* Save the GMR state */
5473	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5474	AssertLogRelRCReturn(rc, rc);
5475	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5476	{
5477	PGMR pGMR = &pSVGAState->paGMR[i];
5478
5479	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5480	AssertLogRelRCReturn(rc, rc);
5481
5482	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5483	{
5484	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5485	AssertLogRelRCReturn(rc, rc);
5486	}
5487	}
5488
5489	/*
5490	* Must save the some state (3D in particular) in the FIFO thread.
5491	*/
5492	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5493	AssertLogRelRCReturn(rc, rc);
5494
5495	return VINF_SUCCESS;
5496	}
5497
5498	/**
5499	* Destructor for PVMSVGAR3STATE structure.
5500	*
5501	* @param pThis The VGA instance.
5502	* @param pSVGAState Pointer to the structure. It is not deallocated.
5503	*/
5504	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5505	{
5506	#ifndef VMSVGA_USE_EMT_HALT_CODE
5507	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5508	{
5509	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5510	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5511	}
5512	#endif
5513
5514	if (pSVGAState->Cursor.fActive)
5515	{
5516	RTMemFree(pSVGAState->Cursor.pData);
5517	pSVGAState->Cursor.pData = NULL;
5518	pSVGAState->Cursor.fActive = false;
5519	}
5520
5521	if (pSVGAState->paGMR)
5522	{
5523	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5524	if (pSVGAState->paGMR[i].paDesc)
5525	RTMemFree(pSVGAState->paGMR[i].paDesc);
5526
5527	RTMemFree(pSVGAState->paGMR);
5528	pSVGAState->paGMR = NULL;
5529	}
5530	}
5531
5532	/**
5533	* Constructor for PVMSVGAR3STATE structure.
5534	*
5535	* @returns VBox status code.
5536	* @param pThis The VGA instance.
5537	* @param pSVGAState Pointer to the structure. It is already allocated.
5538	*/
5539	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5540	{
5541	int rc = VINF_SUCCESS;
5542	RT_ZERO(*pSVGAState);
5543
5544	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5545	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5546
5547	#ifndef VMSVGA_USE_EMT_HALT_CODE
5548	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5549	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5550	AssertRCReturn(rc, rc);
5551	#endif
5552
5553	return rc;
5554	}
5555
5556	/**
5557	* Resets the SVGA hardware state
5558	*
5559	* @returns VBox status code.
5560	* @param pDevIns The device instance.
5561	*/
5562	int vmsvgaReset(PPDMDEVINS pDevIns)
5563	{
5564	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5565	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5566
5567	/* Reset before init? */
5568	if (!pSVGAState)
5569	return VINF_SUCCESS;
5570
5571	Log(("vmsvgaReset\n"));
5572
5573	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5574	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5575	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5576
5577	/* Reset other stuff. */
5578	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5579	RT_ZERO(pThis->svga.au32ScratchRegion);
5580
5581	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5582	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5583
5584	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5585
5586	/* Register caps. */
5587	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5588	# ifdef VBOX_WITH_VMSVGA3D
5589	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5590	# endif
5591
5592	/* Setup FIFO capabilities. */
5593	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5594
5595	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5596	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5597
5598	/* VRAM tracking is enabled by default during bootup. */
5599	pThis->svga.fVRAMTracking = true;
5600	pThis->svga.fEnabled = false;
5601
5602	/* Invalidate current settings. */
5603	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5604	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5605	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5606	pThis->svga.cbScanline = 0;
5607
5608	return rc;
5609	}
5610
5611	/**
5612	* Cleans up the SVGA hardware state
5613	*
5614	* @returns VBox status code.
5615	* @param pDevIns The device instance.
5616	*/
5617	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5618	{
5619	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5620
5621	/*
5622	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5623	*/
5624	if (pThis->svga.pFIFOIOThread)
5625	{
5626	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5627	AssertLogRelRC(rc);
5628
5629	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5630	AssertLogRelRC(rc);
5631	pThis->svga.pFIFOIOThread = NULL;
5632	}
5633
5634	/*
5635	* Destroy the special SVGA state.
5636	*/
5637	if (pThis->svga.pSvgaR3State)
5638	{
5639	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5640
5641	RTMemFree(pThis->svga.pSvgaR3State);
5642	pThis->svga.pSvgaR3State = NULL;
5643	}
5644
5645	/*
5646	* Free our resources residing in the VGA state.
5647	*/
5648	if (pThis->svga.pbVgaFrameBufferR3)
5649	{
5650	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5651	pThis->svga.pbVgaFrameBufferR3 = NULL;
5652	}
5653	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5654	{
5655	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5656	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5657	}
5658	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5659	{
5660	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5661	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5662	}
5663
5664	return VINF_SUCCESS;
5665	}
5666
5667	/**
5668	* Initialize the SVGA hardware state
5669	*
5670	* @returns VBox status code.
5671	* @param pDevIns The device instance.
5672	*/
5673	int vmsvgaInit(PPDMDEVINS pDevIns)
5674	{
5675	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5676	PVMSVGAR3STATE pSVGAState;
5677	PVM pVM = PDMDevHlpGetVM(pDevIns);
5678	int rc;
5679
5680	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5681	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5682
5683	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5684
5685	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5686	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5687	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5688
5689	/* Create event semaphore. */
5690	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5691
5692	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5693	if (RT_FAILURE(rc))
5694	{
5695	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5696	return rc;
5697	}
5698
5699	/* Create event semaphore. */
5700	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5701	if (RT_FAILURE(rc))
5702	{
5703	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5704	return rc;
5705	}
5706
5707	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5708	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5709
5710	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5711	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5712
5713	pSVGAState = pThis->svga.pSvgaR3State;
5714
5715	/* Register caps. */
5716	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5717	# ifdef VBOX_WITH_VMSVGA3D
5718	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5719	# endif
5720
5721	/* Setup FIFO capabilities. */
5722	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5723
5724	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5725	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5726
5727	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5728	# ifdef VBOX_WITH_VMSVGA3D
5729	if (pThis->svga.f3DEnabled)
5730	{
5731	rc = vmsvga3dInit(pThis);
5732	if (RT_FAILURE(rc))
5733	{
5734	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5735	pThis->svga.f3DEnabled = false;
5736	}
5737	}
5738	# endif
5739	/* VRAM tracking is enabled by default during bootup. */
5740	pThis->svga.fVRAMTracking = true;
5741
5742	/* Invalidate current settings. */
5743	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5744	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5745	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5746	pThis->svga.cbScanline = 0;
5747
5748	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5749	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5750	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5751	{
5752	pThis->svga.u32MaxWidth -= 256;
5753	pThis->svga.u32MaxHeight -= 256;
5754	}
5755	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5756
5757	# ifdef DEBUG_GMR_ACCESS
5758	/* Register the GMR access handler type. */
5759	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5760	vmsvgaR3GMRAccessHandler,
5761	NULL, NULL, NULL,
5762	NULL, NULL, NULL,
5763	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5764	AssertRCReturn(rc, rc);
5765	# endif
5766	# ifdef DEBUG_FIFO_ACCESS
5767	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
5768	vmsvgaR3FIFOAccessHandler,
5769	NULL, NULL, NULL,
5770	NULL, NULL, NULL,
5771	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
5772	AssertRCReturn(rc, rc);
5773	#endif
5774
5775	/* Create the async IO thread. */
5776	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
5777	RTTHREADTYPE_IO, "VMSVGA FIFO");
5778	if (RT_FAILURE(rc))
5779	{
5780	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
5781	return rc;
5782	}
5783
5784	/*
5785	* Statistics.
5786	*/
5787	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
5788	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
5789	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
5790	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
5791	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
5792	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
5793	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
5794	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
5795	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
5796	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
5797	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
5798	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
5799	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
5800	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
5801	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
5802	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
5803	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
5804	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
5805	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
5806	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
5807	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
5808	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
5809	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
5810	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
5811	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
5812	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
5813	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
5814	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
5815	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
5816	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
5817	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
5818	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
5819	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
5820	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
5821	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
5822	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
5823	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
5824	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
5825	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
5826	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
5827	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
5828	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
5829	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
5830	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
5831	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
5832	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
5833	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
5834	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
5835	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
5836	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
5837	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
5838	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
5839	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2.");
5840	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
5841	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPATE");
5842	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
5843
5844	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
5845	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
5846	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
5847	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
5848	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
5849	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
5850	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
5851	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
5852	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
5853	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
5854	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
5855	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
5856	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
5857	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
5858	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
5859	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
5860	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
5861	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
5862	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
5863	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
5864	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
5865	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
5866	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
5867	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
5868	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
5869	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
5870	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
5871	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
5872	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
5873	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
5874	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
5875	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
5876
5877	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
5878	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
5879	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
5880	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
5881	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
5882	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
5883	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
5884	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
5885	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
5886	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
5887	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
5888	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
5889	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
5890	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
5891	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
5892	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
5893	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
5894	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
5895	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
5896	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
5897	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
5898	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
5899	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
5900	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
5901	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
5902	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
5903	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
5904	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
5905	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
5906	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
5907	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
5908	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
5909	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
5910	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
5911	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
5912	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
5913	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
5914	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
5915	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
5916	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
5917	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
5918	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
5919	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
5920	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
5921	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
5922	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
5923	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
5924	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
5925	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
5926
5927	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
5928	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
5929	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
5930	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
5931	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
5932	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
5933	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
5934
5935	/*
5936	* Info handlers.
5937	*/
5938	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
5939	# ifdef VBOX_WITH_VMSVGA3D
5940	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
5941	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
5942	"VMSVGA 3d surface details. "
5943	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
5944	vmsvgaR3Info3dSurface);
5945	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
5946	"VMSVGA 3d surface details and bitmap: "
5947	"sid[>dir]",
5948	vmsvgaR3Info3dSurfaceBmp);
5949	# endif
5950
5951	return VINF_SUCCESS;
5952	}
5953
5954	# ifdef VBOX_WITH_VMSVGA3D
5955	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5956	static const char * const g_apszVmSvgaDevCapNames[] =
5957	{
5958	"x3D", /* = 0 */
5959	"xMAX_LIGHTS",
5960	"xMAX_TEXTURES",
5961	"xMAX_CLIP_PLANES",
5962	"xVERTEX_SHADER_VERSION",
5963	"xVERTEX_SHADER",
5964	"xFRAGMENT_SHADER_VERSION",
5965	"xFRAGMENT_SHADER",
5966	"xMAX_RENDER_TARGETS",
5967	"xS23E8_TEXTURES",
5968	"xS10E5_TEXTURES",
5969	"xMAX_FIXED_VERTEXBLEND",
5970	"xD16_BUFFER_FORMAT",
5971	"xD24S8_BUFFER_FORMAT",
5972	"xD24X8_BUFFER_FORMAT",
5973	"xQUERY_TYPES",
5974	"xTEXTURE_GRADIENT_SAMPLING",
5975	"rMAX_POINT_SIZE",
5976	"xMAX_SHADER_TEXTURES",
5977	"xMAX_TEXTURE_WIDTH",
5978	"xMAX_TEXTURE_HEIGHT",
5979	"xMAX_VOLUME_EXTENT",
5980	"xMAX_TEXTURE_REPEAT",
5981	"xMAX_TEXTURE_ASPECT_RATIO",
5982	"xMAX_TEXTURE_ANISOTROPY",
5983	"xMAX_PRIMITIVE_COUNT",
5984	"xMAX_VERTEX_INDEX",
5985	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5986	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5987	"xMAX_VERTEX_SHADER_TEMPS",
5988	"xMAX_FRAGMENT_SHADER_TEMPS",
5989	"xTEXTURE_OPS",
5990	"xSURFACEFMT_X8R8G8B8",
5991	"xSURFACEFMT_A8R8G8B8",
5992	"xSURFACEFMT_A2R10G10B10",
5993	"xSURFACEFMT_X1R5G5B5",
5994	"xSURFACEFMT_A1R5G5B5",
5995	"xSURFACEFMT_A4R4G4B4",
5996	"xSURFACEFMT_R5G6B5",
5997	"xSURFACEFMT_LUMINANCE16",
5998	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5999	"xSURFACEFMT_ALPHA8",
6000	"xSURFACEFMT_LUMINANCE8",
6001	"xSURFACEFMT_Z_D16",
6002	"xSURFACEFMT_Z_D24S8",
6003	"xSURFACEFMT_Z_D24X8",
6004	"xSURFACEFMT_DXT1",
6005	"xSURFACEFMT_DXT2",
6006	"xSURFACEFMT_DXT3",
6007	"xSURFACEFMT_DXT4",
6008	"xSURFACEFMT_DXT5",
6009	"xSURFACEFMT_BUMPX8L8V8U8",
6010	"xSURFACEFMT_A2W10V10U10",
6011	"xSURFACEFMT_BUMPU8V8",
6012	"xSURFACEFMT_Q8W8V8U8",
6013	"xSURFACEFMT_CxV8U8",
6014	"xSURFACEFMT_R_S10E5",
6015	"xSURFACEFMT_R_S23E8",
6016	"xSURFACEFMT_RG_S10E5",
6017	"xSURFACEFMT_RG_S23E8",
6018	"xSURFACEFMT_ARGB_S10E5",
6019	"xSURFACEFMT_ARGB_S23E8",
6020	"xMISSING62",
6021	"xMAX_VERTEX_SHADER_TEXTURES",
6022	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6023	"xSURFACEFMT_V16U16",
6024	"xSURFACEFMT_G16R16",
6025	"xSURFACEFMT_A16B16G16R16",
6026	"xSURFACEFMT_UYVY",
6027	"xSURFACEFMT_YUY2",
6028	"xMULTISAMPLE_NONMASKABLESAMPLES",
6029	"xMULTISAMPLE_MASKABLESAMPLES",
6030	"xALPHATOCOVERAGE",
6031	"xSUPERSAMPLE",
6032	"xAUTOGENMIPMAPS",
6033	"xSURFACEFMT_NV12",
6034	"xSURFACEFMT_AYUV",
6035	"xMAX_CONTEXT_IDS",
6036	"xMAX_SURFACE_IDS",
6037	"xSURFACEFMT_Z_DF16",
6038	"xSURFACEFMT_Z_DF24",
6039	"xSURFACEFMT_Z_D24S8_INT",
6040	"xSURFACEFMT_BC4_UNORM",
6041	"xSURFACEFMT_BC5_UNORM", /* 83 */
6042	};
6043	# endif
6044
6045
6046	/**
6047	* Power On notification.
6048	*
6049	* @returns VBox status code.
6050	* @param pDevIns The device instance data.
6051	*
6052	* @remarks Caller enters the device critical section.
6053	*/
6054	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6055	{
6056	# ifdef VBOX_WITH_VMSVGA3D
6057	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6058	if (pThis->svga.f3DEnabled)
6059	{
6060	int rc = vmsvga3dPowerOn(pThis);
6061
6062	if (RT_SUCCESS(rc))
6063	{
6064	bool fSavedBuffering = RTLogRelSetBuffering(true);
6065	SVGA3dCapsRecord *pCaps;
6066	SVGA3dCapPair *pData;
6067	uint32_t idxCap = 0;
6068
6069	/* 3d hardware version; latest and greatest */
6070	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6071	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6072
6073	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6074	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6075	pData = (SVGA3dCapPair *)&pCaps->data;
6076
6077	/* Fill out all 3d capabilities. */
6078	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6079	{
6080	uint32_t val = 0;
6081
6082	rc = vmsvga3dQueryCaps(pThis, i, &val);
6083	if (RT_SUCCESS(rc))
6084	{
6085	pData[idxCap][0] = i;
6086	pData[idxCap][1] = val;
6087	idxCap++;
6088	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6089	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6090	else
6091	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6092	&g_apszVmSvgaDevCapNames[i][1]));
6093	}
6094	else
6095	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6096	}
6097	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6098	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6099
6100	/* Mark end of record array. */
6101	pCaps->header.length = 0;
6102
6103	RTLogRelSetBuffering(fSavedBuffering);
6104	}
6105	}
6106	# else /* !VBOX_WITH_VMSVGA3D */
6107	RT_NOREF(pDevIns);
6108	# endif /* !VBOX_WITH_VMSVGA3D */
6109	}
6110
6111	#endif /* IN_RING3 */
6112

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 76785

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