DevVGA-SVGA.cpp@ 77611

Last change on this file since 77611 was 77288, checked in by vboxsync, 6 years ago
DevVGA-SVGA: Use the VGA refresh timer to babysit the FIFO thread and make sure it's woken up when needed. Disabled the access handler based babysitter with #ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER. [build fix] bugref:9376
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File size: 289.7 KB

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1	/* $Id: DevVGA-SVGA.cpp 77288 2019-02-12 16:49:26Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
249	STAMPROFILE StatBusyDelayEmts;
250
251	STAMPROFILE StatR3Cmd3dPresentProf;
252	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
253	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
254	STAMCOUNTER StatR3CmdDefineGmr2;
255	STAMCOUNTER StatR3CmdDefineGmr2Free;
256	STAMCOUNTER StatR3CmdDefineGmr2Modify;
257	STAMCOUNTER StatR3CmdRemapGmr2;
258	STAMCOUNTER StatR3CmdRemapGmr2Modify;
259	STAMCOUNTER StatR3CmdInvalidCmd;
260	STAMCOUNTER StatR3CmdFence;
261	STAMCOUNTER StatR3CmdUpdate;
262	STAMCOUNTER StatR3CmdUpdateVerbose;
263	STAMCOUNTER StatR3CmdDefineCursor;
264	STAMCOUNTER StatR3CmdDefineAlphaCursor;
265	STAMCOUNTER StatR3CmdEscape;
266	STAMCOUNTER StatR3CmdDefineScreen;
267	STAMCOUNTER StatR3CmdDestroyScreen;
268	STAMCOUNTER StatR3CmdDefineGmrFb;
269	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
270	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
271	STAMCOUNTER StatR3CmdAnnotationFill;
272	STAMCOUNTER StatR3CmdAnnotationCopy;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
275	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
276	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
277	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
278	STAMCOUNTER StatR3Cmd3dSurfaceDma;
279	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
280	STAMCOUNTER StatR3Cmd3dContextDefine;
281	STAMCOUNTER StatR3Cmd3dContextDestroy;
282	STAMCOUNTER StatR3Cmd3dSetTransform;
283	STAMCOUNTER StatR3Cmd3dSetZRange;
284	STAMCOUNTER StatR3Cmd3dSetRenderState;
285	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
286	STAMCOUNTER StatR3Cmd3dSetTextureState;
287	STAMCOUNTER StatR3Cmd3dSetMaterial;
288	STAMCOUNTER StatR3Cmd3dSetLightData;
289	STAMCOUNTER StatR3Cmd3dSetLightEnable;
290	STAMCOUNTER StatR3Cmd3dSetViewPort;
291	STAMCOUNTER StatR3Cmd3dSetClipPlane;
292	STAMCOUNTER StatR3Cmd3dClear;
293	STAMCOUNTER StatR3Cmd3dPresent;
294	STAMCOUNTER StatR3Cmd3dPresentReadBack;
295	STAMCOUNTER StatR3Cmd3dShaderDefine;
296	STAMCOUNTER StatR3Cmd3dShaderDestroy;
297	STAMCOUNTER StatR3Cmd3dSetShader;
298	STAMCOUNTER StatR3Cmd3dSetShaderConst;
299	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
300	STAMCOUNTER StatR3Cmd3dSetScissorRect;
301	STAMCOUNTER StatR3Cmd3dBeginQuery;
302	STAMCOUNTER StatR3Cmd3dEndQuery;
303	STAMCOUNTER StatR3Cmd3dWaitForQuery;
304	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
305	STAMCOUNTER StatR3Cmd3dActivateSurface;
306	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
307
308	STAMCOUNTER StatR3RegConfigDoneWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
311	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
312
313	STAMCOUNTER StatFifoCommands;
314	STAMCOUNTER StatFifoErrors;
315	STAMCOUNTER StatFifoUnkCmds;
316	STAMCOUNTER StatFifoTodoTimeout;
317	STAMCOUNTER StatFifoTodoWoken;
318	STAMPROFILE StatFifoStalls;
319	STAMPROFILE StatFifoExtendedSleep;
320	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
321	STAMCOUNTER StatFifoAccessHandler;
322	# endif
323	STAMCOUNTER StatFifoCursorFetchAgain;
324	STAMCOUNTER StatFifoCursorNoChange;
325	STAMCOUNTER StatFifoCursorPosition;
326	STAMCOUNTER StatFifoCursorVisiblity;
327	STAMCOUNTER StatFifoWatchdogWakeUps;
328	} VMSVGAR3STATE, *PVMSVGAR3STATE;
329	#endif /* IN_RING3 */
330
331
332	/*********************************************************************************************************************************
333	* Internal Functions *
334	*********************************************************************************************************************************/
335	#ifdef IN_RING3
336	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
337	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
338	# endif
339	# ifdef DEBUG_GMR_ACCESS
340	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
341	# endif
342	#endif
343
344
345	/*********************************************************************************************************************************
346	* Global Variables *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349
350	/**
351	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
352	*/
353	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
354	{
355	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
356	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
357	SSMFIELD_ENTRY_TERM()
358	};
359
360	/**
361	* SSM descriptor table for the GMR structure.
362	*/
363	static SSMFIELD const g_aGMRFields[] =
364	{
365	SSMFIELD_ENTRY( GMR, cMaxPages),
366	SSMFIELD_ENTRY( GMR, cbTotal),
367	SSMFIELD_ENTRY( GMR, numDescriptors),
368	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
369	SSMFIELD_ENTRY_TERM()
370	};
371
372	/**
373	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
374	*/
375	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
376	{
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
388	SSMFIELD_ENTRY_TERM()
389	};
390
391	/**
392	* SSM descriptor table for the VMSVGAR3STATE structure.
393	*/
394	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
395	{
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
397	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
404	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
407	#ifdef VMSVGA_USE_EMT_HALT_CODE
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
409	#else
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
411	#endif
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
469
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
474
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
482	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
484	# endif
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
489
490	SSMFIELD_ENTRY_TERM()
491	};
492
493	/**
494	* SSM descriptor table for the VGAState.svga structure.
495	*/
496	static SSMFIELD const g_aVGAStateSVGAFields[] =
497	{
498	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	{
811	*pu32 = pThis->svga.uWidth;
812	}
813	else
814	{
815	#ifndef IN_RING3
816	rc = VINF_IOM_R3_IOPORT_READ;
817	#else
818	*pu32 = pThis->pDrv->cx;
819	#endif
820	}
821	break;
822	}
823
824	case SVGA_REG_HEIGHT:
825	{
826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
827	if ( pThis->svga.fEnabled
828	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
829	{
830	*pu32 = pThis->svga.uHeight;
831	}
832	else
833	{
834	#ifndef IN_RING3
835	rc = VINF_IOM_R3_IOPORT_READ;
836	#else
837	*pu32 = pThis->pDrv->cy;
838	#endif
839	}
840	break;
841	}
842
843	case SVGA_REG_MAX_WIDTH:
844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
845	*pu32 = pThis->svga.u32MaxWidth;
846	break;
847
848	case SVGA_REG_MAX_HEIGHT:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
850	*pu32 = pThis->svga.u32MaxHeight;
851	break;
852
853	case SVGA_REG_DEPTH:
854	/* This returns the color depth of the current mode. */
855	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
856	switch (pThis->svga.uBpp)
857	{
858	case 15:
859	case 16:
860	case 24:
861	*pu32 = pThis->svga.uBpp;
862	break;
863
864	default:
865	case 32:
866	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
867	break;
868	}
869	break;
870
871	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
873	if ( pThis->svga.fEnabled
874	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
875	{
876	*pu32 = pThis->svga.uBpp;
877	}
878	else
879	{
880	#ifndef IN_RING3
881	rc = VINF_IOM_R3_IOPORT_READ;
882	#else
883	*pu32 = pThis->pDrv->cBits;
884	#endif
885	}
886	break;
887
888	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
890	if ( pThis->svga.fEnabled
891	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
892	{
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	}
895	else
896	{
897	#ifndef IN_RING3
898	rc = VINF_IOM_R3_IOPORT_READ;
899	#else
900	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
901	#endif
902	}
903	break;
904
905	case SVGA_REG_PSEUDOCOLOR:
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
907	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
908	break;
909
910	case SVGA_REG_RED_MASK:
911	case SVGA_REG_GREEN_MASK:
912	case SVGA_REG_BLUE_MASK:
913	{
914	uint32_t uBpp;
915
916	if ( pThis->svga.fEnabled
917	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
918	{
919	uBpp = pThis->svga.uBpp;
920	}
921	else
922	{
923	#ifndef IN_RING3
924	rc = VINF_IOM_R3_IOPORT_READ;
925	break;
926	#else
927	uBpp = pThis->pDrv->cBits;
928	#endif
929	}
930	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
931	switch (uBpp)
932	{
933	case 8:
934	u32RedMask = 0x07;
935	u32GreenMask = 0x38;
936	u32BlueMask = 0xc0;
937	break;
938
939	case 15:
940	u32RedMask = 0x0000001f;
941	u32GreenMask = 0x000003e0;
942	u32BlueMask = 0x00007c00;
943	break;
944
945	case 16:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000007e0;
948	u32BlueMask = 0x0000f800;
949	break;
950
951	case 24:
952	case 32:
953	default:
954	u32RedMask = 0x00ff0000;
955	u32GreenMask = 0x0000ff00;
956	u32BlueMask = 0x000000ff;
957	break;
958	}
959	switch (idxReg)
960	{
961	case SVGA_REG_RED_MASK:
962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
963	*pu32 = u32RedMask;
964	break;
965
966	case SVGA_REG_GREEN_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
968	*pu32 = u32GreenMask;
969	break;
970
971	case SVGA_REG_BLUE_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
973	*pu32 = u32BlueMask;
974	break;
975	}
976	break;
977	}
978
979	case SVGA_REG_BYTES_PER_LINE:
980	{
981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
982	if ( pThis->svga.fEnabled
983	&& pThis->svga.cbScanline)
984	{
985	*pu32 = pThis->svga.cbScanline;
986	}
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThis->pDrv->cbScanline;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_VRAM_SIZE: /* VRAM size */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1000	*pu32 = pThis->vram_size;
1001	break;
1002
1003	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1005	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1006	*pu32 = pThis->GCPhysVRAM;
1007	break;
1008
1009	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1011	/* Always zero in our case. */
1012	*pu32 = 0;
1013	break;
1014
1015	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1016	{
1017	#ifndef IN_RING3
1018	rc = VINF_IOM_R3_IOPORT_READ;
1019	#else
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1021
1022	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1023	if ( pThis->svga.fEnabled
1024	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1025	{
1026	/* Hardware enabled; return real framebuffer size .*/
1027	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1028	}
1029	else
1030	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1031
1032	pu32 = RT_MIN(pThis->vram_size, pu32);
1033	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1034	#endif
1035	break;
1036	}
1037
1038	case SVGA_REG_CAPABILITIES:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1040	*pu32 = pThis->svga.u32RegCaps;
1041	break;
1042
1043	case SVGA_REG_MEM_START: /* FIFO start */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1045	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1046	*pu32 = pThis->svga.GCPhysFIFO;
1047	break;
1048
1049	case SVGA_REG_MEM_SIZE: /* FIFO size */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1051	*pu32 = pThis->svga.cbFIFO;
1052	break;
1053
1054	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1056	*pu32 = pThis->svga.fConfigured;
1057	break;
1058
1059	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1061	*pu32 = 0;
1062	break;
1063
1064	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1066	if (pThis->svga.fBusy)
1067	{
1068	#ifndef IN_RING3
1069	/* Go to ring-3 and halt the CPU. */
1070	rc = VINF_IOM_R3_IOPORT_READ;
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	if (pThis->svga.fGFBRegisters)
1422	{
1423	vgaR3UpdateDisplay(pThis, x, y, w, h);
1424	}
1425	else
1426	{
1427	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1428	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1429	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1430	}
1431
1432	return VINF_SUCCESS;
1433	}
1434
1435	#endif /* IN_RING3 */
1436
1437	#if defined(IN_RING0) \|\| defined(IN_RING3)
1438	/**
1439	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1440	*
1441	* @param pThis The VMSVGA state.
1442	* @param fState The busy state.
1443	*/
1444	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1445	{
1446	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1447
1448	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1449	{
1450	/* Race / unfortunately scheduling. Highly unlikly. */
1451	uint32_t cLoops = 64;
1452	do
1453	{
1454	ASMNopPause();
1455	fState = (pThis->svga.fBusy != 0);
1456	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1457	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1458	}
1459	}
1460	#endif
1461
1462	/**
1463	* Write port register
1464	*
1465	* @returns VBox status code.
1466	* @param pThis VMSVGA State
1467	* @param u32 Value to write
1468	*/
1469	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1470	{
1471	#ifdef IN_RING3
1472	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1473	#endif
1474	int rc = VINF_SUCCESS;
1475
1476	/* Rough index register validation. */
1477	uint32_t idxReg = pThis->svga.u32IndexReg;
1478	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1479	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1480	VINF_IOM_R3_IOPORT_WRITE);
1481	#else
1482	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1483	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1484	VINF_SUCCESS);
1485	#endif
1486	RT_UNTRUSTED_VALIDATED_FENCE();
1487
1488	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1489	if ( idxReg >= SVGA_REG_CAPABILITIES
1490	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1491	{
1492	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1493	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1494	}
1495	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1496	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1497	switch (idxReg)
1498	{
1499	case SVGA_REG_WIDTH:
1500	case SVGA_REG_HEIGHT:
1501	case SVGA_REG_PITCHLOCK:
1502	case SVGA_REG_BITS_PER_PIXEL:
1503	pThis->svga.fGFBRegisters = true;
1504	break;
1505	default:
1506	break;
1507	}
1508
1509	switch (idxReg)
1510	{
1511	case SVGA_REG_ID:
1512	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1513	if ( u32 == SVGA_ID_0
1514	\|\| u32 == SVGA_ID_1
1515	\|\| u32 == SVGA_ID_2)
1516	pThis->svga.u32SVGAId = u32;
1517	else
1518	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1519	break;
1520
1521	case SVGA_REG_ENABLE:
1522	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1523	#ifdef IN_RING3
1524	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1525	&& pThis->svga.fEnabled == false)
1526	{
1527	/* Make a backup copy of the first 512kb in order to save font data etc. */
1528	/** @todo should probably swap here, rather than copy + zero */
1529	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1530	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1531	}
1532
1533	pThis->svga.fEnabled = u32;
1534	if (pThis->svga.fEnabled)
1535	{
1536	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1537	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1538	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1539	{
1540	/* Keep the current mode. */
1541	pThis->svga.uWidth = pThis->pDrv->cx;
1542	pThis->svga.uHeight = pThis->pDrv->cy;
1543	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1544	}
1545
1546	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1547	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1548	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1549	{
1550	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1551	}
1552	# ifdef LOG_ENABLED
1553	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1554	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1555	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1556	# endif
1557
1558	/* Disable or enable dirty page tracking according to the current fTraces value. */
1559	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1560
1561	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1562	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1563	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1564	}
1565	else
1566	{
1567	/* Restore the text mode backup. */
1568	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1569
1570	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1571
1572	/* Enable dirty page tracking again when going into legacy mode. */
1573	vmsvgaSetTraces(pThis, true);
1574
1575	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1576	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1577	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1578	}
1579	#else /* !IN_RING3 */
1580	rc = VINF_IOM_R3_IOPORT_WRITE;
1581	#endif /* !IN_RING3 */
1582	break;
1583
1584	case SVGA_REG_WIDTH:
1585	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1586	if (pThis->svga.uWidth != u32)
1587	{
1588	pThis->svga.uWidth = u32;
1589	if (pThis->svga.fEnabled)
1590	{
1591	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1592	}
1593	}
1594	/* else: nop */
1595	break;
1596
1597	case SVGA_REG_HEIGHT:
1598	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1599	if (pThis->svga.uHeight != u32)
1600	{
1601	pThis->svga.uHeight = u32;
1602	if (pThis->svga.fEnabled)
1603	{
1604	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1605	}
1606	}
1607	/* else: nop */
1608	break;
1609
1610	case SVGA_REG_DEPTH:
1611	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1612	/** @todo read-only?? */
1613	break;
1614
1615	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1616	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1617	if (pThis->svga.uBpp != u32)
1618	{
1619	pThis->svga.uBpp = u32;
1620	if (pThis->svga.fEnabled)
1621	{
1622	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1623	}
1624	}
1625	/* else: nop */
1626	break;
1627
1628	case SVGA_REG_PSEUDOCOLOR:
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1630	break;
1631
1632	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1633	#ifdef IN_RING3
1634	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1635	pThis->svga.fConfigured = u32;
1636	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1637	if (!pThis->svga.fConfigured)
1638	{
1639	pThis->svga.fTraces = true;
1640	}
1641	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1642	#else
1643	rc = VINF_IOM_R3_IOPORT_WRITE;
1644	#endif
1645	break;
1646
1647	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1648	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1649	if ( pThis->svga.fEnabled
1650	&& pThis->svga.fConfigured)
1651	{
1652	#if defined(IN_RING3) \|\| defined(IN_RING0)
1653	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1654	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1655	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1656	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1657
1658	/* Kick the FIFO thread to start processing commands again. */
1659	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1660	#else
1661	rc = VINF_IOM_R3_IOPORT_WRITE;
1662	#endif
1663	}
1664	/* else nothing to do. */
1665	else
1666	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1667
1668	break;
1669
1670	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1671	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1672	break;
1673
1674	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1675	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1676	pThis->svga.u32GuestId = u32;
1677	break;
1678
1679	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1680	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1681	pThis->svga.u32PitchLock = u32;
1682	break;
1683
1684	case SVGA_REG_IRQMASK: /* Interrupt mask */
1685	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1686	pThis->svga.u32IrqMask = u32;
1687
1688	/* Irq pending after the above change? */
1689	if (pThis->svga.u32IrqStatus & u32)
1690	{
1691	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1692	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1693	}
1694	else
1695	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1696	break;
1697
1698	/* Mouse cursor support */
1699	case SVGA_REG_CURSOR_ID:
1700	case SVGA_REG_CURSOR_X:
1701	case SVGA_REG_CURSOR_Y:
1702	case SVGA_REG_CURSOR_ON:
1703	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1704	break;
1705
1706	/* Legacy multi-monitor support */
1707	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1708	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1709	break;
1710	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1711	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1712	break;
1713	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1714	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1715	break;
1716	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1717	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1718	break;
1719	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1720	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1721	break;
1722	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1724	break;
1725	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1726	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1727	break;
1728	#ifdef VBOX_WITH_VMSVGA3D
1729	/* See "Guest memory regions" below. */
1730	case SVGA_REG_GMR_ID:
1731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1732	pThis->svga.u32CurrentGMRId = u32;
1733	break;
1734
1735	case SVGA_REG_GMR_DESCRIPTOR:
1736	# ifndef IN_RING3
1737	rc = VINF_IOM_R3_IOPORT_WRITE;
1738	break;
1739	# else /* IN_RING3 */
1740	{
1741	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1742
1743	/* Validate current GMR id. */
1744	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1745	AssertBreak(idGMR < pThis->svga.cGMR);
1746	RT_UNTRUSTED_VALIDATED_FENCE();
1747
1748	/* Free the old GMR if present. */
1749	vmsvgaGMRFree(pThis, idGMR);
1750
1751	/* Just undefine the GMR? */
1752	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1753	if (GCPhys == 0)
1754	{
1755	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1756	break;
1757	}
1758
1759
1760	/* Never cross a page boundary automatically. */
1761	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1762	uint32_t cPagesTotal = 0;
1763	uint32_t iDesc = 0;
1764	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1765	uint32_t cLoops = 0;
1766	RTGCPHYS GCPhysBase = GCPhys;
1767	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1768	{
1769	/* Read descriptor. */
1770	SVGAGuestMemDescriptor desc;
1771	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1772	AssertRCBreak(rc);
1773
1774	if (desc.numPages != 0)
1775	{
1776	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1777	cPagesTotal += desc.numPages;
1778	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1779
1780	if ((iDesc & 15) == 0)
1781	{
1782	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1783	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1784	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1785	}
1786
1787	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1788	paDescs[iDesc++].numPages = desc.numPages;
1789
1790	/* Continue with the next descriptor. */
1791	GCPhys += sizeof(desc);
1792	}
1793	else if (desc.ppn == 0)
1794	break; /* terminator */
1795	else /* Pointer to the next physical page of descriptors. */
1796	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1797
1798	cLoops++;
1799	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1800	}
1801
1802	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1803	if (RT_SUCCESS(rc))
1804	{
1805	/* Commit the GMR. */
1806	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1807	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1808	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1809	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1810	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1811	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1812	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1813	}
1814	else
1815	{
1816	RTMemFree(paDescs);
1817	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1818	}
1819	break;
1820	}
1821	# endif /* IN_RING3 */
1822	#endif // VBOX_WITH_VMSVGA3D
1823
1824	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1825	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1826	if (pThis->svga.fTraces == u32)
1827	break; /* nothing to do */
1828
1829	#ifdef IN_RING3
1830	vmsvgaSetTraces(pThis, !!u32);
1831	#else
1832	rc = VINF_IOM_R3_IOPORT_WRITE;
1833	#endif
1834	break;
1835
1836	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1837	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1838	break;
1839
1840	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1841	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1842	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1843	break;
1844
1845	case SVGA_REG_FB_START:
1846	case SVGA_REG_MEM_START:
1847	case SVGA_REG_HOST_BITS_PER_PIXEL:
1848	case SVGA_REG_MAX_WIDTH:
1849	case SVGA_REG_MAX_HEIGHT:
1850	case SVGA_REG_VRAM_SIZE:
1851	case SVGA_REG_FB_SIZE:
1852	case SVGA_REG_CAPABILITIES:
1853	case SVGA_REG_MEM_SIZE:
1854	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1855	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1856	case SVGA_REG_BYTES_PER_LINE:
1857	case SVGA_REG_FB_OFFSET:
1858	case SVGA_REG_RED_MASK:
1859	case SVGA_REG_GREEN_MASK:
1860	case SVGA_REG_BLUE_MASK:
1861	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1862	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1863	case SVGA_REG_GMR_MAX_IDS:
1864	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1865	/* Read only - ignore. */
1866	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1867	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1868	break;
1869
1870	default:
1871	{
1872	uint32_t offReg;
1873	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1874	{
1875	RT_UNTRUSTED_VALIDATED_FENCE();
1876	pThis->svga.au32ScratchRegion[offReg] = u32;
1877	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1878	}
1879	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1880	{
1881	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1882	Btw, see rgb_to_pixel32. */
1883	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1884	u32 &= 0xff;
1885	RT_UNTRUSTED_VALIDATED_FENCE();
1886	uint32_t uRgb = pThis->last_palette[offReg / 3];
1887	switch (offReg % 3)
1888	{
1889	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1890	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1891	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1892	}
1893	pThis->last_palette[offReg / 3] = uRgb;
1894	}
1895	else
1896	{
1897	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1898	rc = VINF_IOM_R3_IOPORT_WRITE;
1899	#else
1900	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1901	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1902	#endif
1903	}
1904	break;
1905	}
1906	}
1907	return rc;
1908	}
1909
1910	/**
1911	* Port I/O Handler for IN operations.
1912	*
1913	* @returns VINF_SUCCESS or VINF_EM_*.
1914	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1915	*
1916	* @param pDevIns The device instance.
1917	* @param pvUser User argument.
1918	* @param uPort Port number used for the IN operation.
1919	* @param pu32 Where to store the result. This is always a 32-bit
1920	* variable regardless of what @a cb might say.
1921	* @param cb Number of bytes read.
1922	*/
1923	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1924	{
1925	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1926	RT_NOREF_PV(pvUser);
1927
1928	/* Ignore non-dword accesses. */
1929	if (cb != 4)
1930	{
1931	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1932	*pu32 = UINT32_MAX;
1933	return VINF_SUCCESS;
1934	}
1935
1936	switch (uPort - pThis->svga.BasePort)
1937	{
1938	case SVGA_INDEX_PORT:
1939	*pu32 = pThis->svga.u32IndexReg;
1940	break;
1941
1942	case SVGA_VALUE_PORT:
1943	return vmsvgaReadPort(pThis, pu32);
1944
1945	case SVGA_BIOS_PORT:
1946	Log(("Ignoring BIOS port read\n"));
1947	*pu32 = 0;
1948	break;
1949
1950	case SVGA_IRQSTATUS_PORT:
1951	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1952	*pu32 = pThis->svga.u32IrqStatus;
1953	break;
1954
1955	default:
1956	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1957	*pu32 = UINT32_MAX;
1958	break;
1959	}
1960
1961	return VINF_SUCCESS;
1962	}
1963
1964	/**
1965	* Port I/O Handler for OUT operations.
1966	*
1967	* @returns VINF_SUCCESS or VINF_EM_*.
1968	*
1969	* @param pDevIns The device instance.
1970	* @param pvUser User argument.
1971	* @param uPort Port number used for the OUT operation.
1972	* @param u32 The value to output.
1973	* @param cb The value size in bytes.
1974	*/
1975	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1976	{
1977	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1978	RT_NOREF_PV(pvUser);
1979
1980	/* Ignore non-dword accesses. */
1981	if (cb != 4)
1982	{
1983	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1984	return VINF_SUCCESS;
1985	}
1986
1987	switch (uPort - pThis->svga.BasePort)
1988	{
1989	case SVGA_INDEX_PORT:
1990	pThis->svga.u32IndexReg = u32;
1991	break;
1992
1993	case SVGA_VALUE_PORT:
1994	return vmsvgaWritePort(pThis, u32);
1995
1996	case SVGA_BIOS_PORT:
1997	Log(("Ignoring BIOS port write (val=%x)\n", u32));
1998	break;
1999
2000	case SVGA_IRQSTATUS_PORT:
2001	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2002	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2003	/* Clear the irq in case all events have been cleared. */
2004	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2005	{
2006	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2007	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2008	}
2009	break;
2010
2011	default:
2012	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2013	uPort - pThis->svga.BasePort, uPort, u32, cb));
2014	break;
2015	}
2016	return VINF_SUCCESS;
2017	}
2018
2019	#ifdef IN_RING3
2020
2021	# ifdef DEBUG_FIFO_ACCESS
2022	/**
2023	* Handle FIFO memory access.
2024	* @returns VBox status code.
2025	* @param pVM VM handle.
2026	* @param pThis VGA device instance data.
2027	* @param GCPhys The access physical address.
2028	* @param fWriteAccess Read or write access
2029	*/
2030	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2031	{
2032	RT_NOREF(pVM);
2033	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2034	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2035
2036	switch (GCPhysOffset >> 2)
2037	{
2038	case SVGA_FIFO_MIN:
2039	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2040	break;
2041	case SVGA_FIFO_MAX:
2042	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2043	break;
2044	case SVGA_FIFO_NEXT_CMD:
2045	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2046	break;
2047	case SVGA_FIFO_STOP:
2048	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2049	break;
2050	case SVGA_FIFO_CAPABILITIES:
2051	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2052	break;
2053	case SVGA_FIFO_FLAGS:
2054	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2055	break;
2056	case SVGA_FIFO_FENCE:
2057	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2058	break;
2059	case SVGA_FIFO_3D_HWVERSION:
2060	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2061	break;
2062	case SVGA_FIFO_PITCHLOCK:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_CURSOR_ON:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_CURSOR_X:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_CURSOR_Y:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_CURSOR_COUNT:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_RESERVED:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_CURSOR_SCREEN_ID:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_DEAD:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_3D_HWVERSION_REVISED:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS_LAST:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_GUEST_3D_HWVERSION:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_FENCE_GOAL:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_BUSY:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	default:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	}
2357
2358	return VINF_EM_RAW_EMULATE_INSTR;
2359	}
2360	# endif /* DEBUG_FIFO_ACCESS */
2361
2362	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2363	/**
2364	* HC access handler for the FIFO.
2365	*
2366	* @returns VINF_SUCCESS if the handler have carried out the operation.
2367	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2368	* @param pVM VM Handle.
2369	* @param pVCpu The cross context CPU structure for the calling EMT.
2370	* @param GCPhys The physical address the guest is writing to.
2371	* @param pvPhys The HC mapping of that address.
2372	* @param pvBuf What the guest is reading/writing.
2373	* @param cbBuf How much it's reading/writing.
2374	* @param enmAccessType The access type.
2375	* @param enmOrigin Who is making the access.
2376	* @param pvUser User argument.
2377	*/
2378	static DECLCALLBACK(VBOXSTRICTRC)
2379	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2380	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2381	{
2382	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2383	PVGASTATE pThis = (PVGASTATE)pvUser;
2384	AssertPtr(pThis);
2385
2386	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2387	/*
2388	* Wake up the FIFO thread as it might have work to do now.
2389	*/
2390	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2391	AssertLogRelRC(rc);
2392	# endif
2393
2394	# ifdef DEBUG_FIFO_ACCESS
2395	/*
2396	* When in debug-fifo-access mode, we do not disable the access handler,
2397	* but leave it on as we wish to catch all access.
2398	*/
2399	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2400	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2401	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2402	/*
2403	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2404	*/
2405	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2406	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2407	# endif
2408	if (RT_SUCCESS(rc))
2409	return VINF_PGM_HANDLER_DO_DEFAULT;
2410	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2411	return rc;
2412	}
2413	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2414
2415	#endif /* IN_RING3 */
2416
2417	#ifdef DEBUG_GMR_ACCESS
2418	# ifdef IN_RING3
2419
2420	/**
2421	* HC access handler for the FIFO.
2422	*
2423	* @returns VINF_SUCCESS if the handler have carried out the operation.
2424	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2425	* @param pVM VM Handle.
2426	* @param pVCpu The cross context CPU structure for the calling EMT.
2427	* @param GCPhys The physical address the guest is writing to.
2428	* @param pvPhys The HC mapping of that address.
2429	* @param pvBuf What the guest is reading/writing.
2430	* @param cbBuf How much it's reading/writing.
2431	* @param enmAccessType The access type.
2432	* @param enmOrigin Who is making the access.
2433	* @param pvUser User argument.
2434	*/
2435	static DECLCALLBACK(VBOXSTRICTRC)
2436	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2437	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2438	{
2439	PVGASTATE pThis = (PVGASTATE)pvUser;
2440	Assert(pThis);
2441	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2442	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2443
2444	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2445
2446	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2447	{
2448	PGMR pGMR = &pSVGAState->paGMR[i];
2449
2450	if (pGMR->numDescriptors)
2451	{
2452	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2453	{
2454	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2455	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2456	{
2457	/*
2458	* Turn off the write handler for this particular page and make it R/W.
2459	* Then return telling the caller to restart the guest instruction.
2460	*/
2461	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2462	AssertRC(rc);
2463	goto end;
2464	}
2465	}
2466	}
2467	}
2468	end:
2469	return VINF_PGM_HANDLER_DO_DEFAULT;
2470	}
2471
2472	/* Callback handler for VMR3ReqCallWaitU */
2473	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2474	{
2475	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2476	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2477	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2478	int rc;
2479
2480	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2481	{
2482	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2483	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2484	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2485	AssertRC(rc);
2486	}
2487	return VINF_SUCCESS;
2488	}
2489
2490	/* Callback handler for VMR3ReqCallWaitU */
2491	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2492	{
2493	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2494	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2495	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2496
2497	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2498	{
2499	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2500	AssertRC(rc);
2501	}
2502	return VINF_SUCCESS;
2503	}
2504
2505	/* Callback handler for VMR3ReqCallWaitU */
2506	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2507	{
2508	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2509
2510	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2511	{
2512	PGMR pGMR = &pSVGAState->paGMR[i];
2513
2514	if (pGMR->numDescriptors)
2515	{
2516	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2517	{
2518	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2519	AssertRC(rc);
2520	}
2521	}
2522	}
2523	return VINF_SUCCESS;
2524	}
2525
2526	# endif /* IN_RING3 */
2527	#endif /* DEBUG_GMR_ACCESS */
2528
2529	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2530
2531	#ifdef IN_RING3
2532
2533
2534	/**
2535	* Common worker for changing the pointer shape.
2536	*
2537	* @param pThis The VGA instance data.
2538	* @param pSVGAState The VMSVGA ring-3 instance data.
2539	* @param fAlpha Whether there is alpha or not.
2540	* @param xHot Hotspot x coordinate.
2541	* @param yHot Hotspot y coordinate.
2542	* @param cx Width.
2543	* @param cy Height.
2544	* @param pbData Heap copy of the cursor data. Consumed.
2545	* @param cbData The size of the data.
2546	*/
2547	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2548	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2549	{
2550	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2551	#ifdef LOG_ENABLED
2552	if (LogIs2Enabled())
2553	{
2554	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2555	if (!fAlpha)
2556	{
2557	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2558	for (uint32_t y = 0; y < cy; y++)
2559	{
2560	Log2(("%3u:", y));
2561	uint8_t const pbLine = &pbData[y cbAndLine];
2562	for (uint32_t x = 0; x < cx; x += 8)
2563	{
2564	uint8_t b = pbLine[x / 8];
2565	char szByte[12];
2566	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2567	szByte[1] = b & 0x40 ? '*' : ' ';
2568	szByte[2] = b & 0x20 ? '*' : ' ';
2569	szByte[3] = b & 0x10 ? '*' : ' ';
2570	szByte[4] = b & 0x08 ? '*' : ' ';
2571	szByte[5] = b & 0x04 ? '*' : ' ';
2572	szByte[6] = b & 0x02 ? '*' : ' ';
2573	szByte[7] = b & 0x01 ? '*' : ' ';
2574	szByte[8] = '\0';
2575	Log2(("%s", szByte));
2576	}
2577	Log2(("\n"));
2578	}
2579	}
2580
2581	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2582	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2583	for (uint32_t y = 0; y < cy; y++)
2584	{
2585	Log2(("%3u:", y));
2586	uint32_t const pu32Line = &pu32Xor[y cx];
2587	for (uint32_t x = 0; x < cx; x++)
2588	Log2((" %08x", pu32Line[x]));
2589	Log2(("\n"));
2590	}
2591	}
2592	#endif
2593
2594	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2595	AssertRC(rc);
2596
2597	if (pSVGAState->Cursor.fActive)
2598	RTMemFree(pSVGAState->Cursor.pData);
2599
2600	pSVGAState->Cursor.fActive = true;
2601	pSVGAState->Cursor.xHotspot = xHot;
2602	pSVGAState->Cursor.yHotspot = yHot;
2603	pSVGAState->Cursor.width = cx;
2604	pSVGAState->Cursor.height = cy;
2605	pSVGAState->Cursor.cbData = cbData;
2606	pSVGAState->Cursor.pData = pbData;
2607	}
2608
2609
2610	/**
2611	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2612	*
2613	* @param pThis The VGA instance data.
2614	* @param pSVGAState The VMSVGA ring-3 instance data.
2615	* @param pCursor The cursor.
2616	* @param pbSrcAndMask The AND mask.
2617	* @param cbSrcAndLine The scanline length of the AND mask.
2618	* @param pbSrcXorMask The XOR mask.
2619	* @param cbSrcXorLine The scanline length of the XOR mask.
2620	*/
2621	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2622	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2623	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2624	{
2625	uint32_t const cx = pCursor->width;
2626	uint32_t const cy = pCursor->height;
2627
2628	/*
2629	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2630	* The AND data uses 8-bit aligned scanlines.
2631	* The XOR data must be starting on a 32-bit boundrary.
2632	*/
2633	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2634	uint32_t cbDstAndMask = cbDstAndLine * cy;
2635	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2636	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2637
2638	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2639	AssertReturnVoid(pbCopy);
2640
2641	/* Convert the AND mask. */
2642	uint8_t *pbDst = pbCopy;
2643	uint8_t const *pbSrc = pbSrcAndMask;
2644	switch (pCursor->andMaskDepth)
2645	{
2646	case 1:
2647	if (cbSrcAndLine == cbDstAndLine)
2648	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2649	else
2650	{
2651	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2652	for (uint32_t y = 0; y < cy; y++)
2653	{
2654	memcpy(pbDst, pbSrc, cbDstAndLine);
2655	pbDst += cbDstAndLine;
2656	pbSrc += cbSrcAndLine;
2657	}
2658	}
2659	break;
2660	/* Should take the XOR mask into account for the multi-bit AND mask. */
2661	case 8:
2662	for (uint32_t y = 0; y < cy; y++)
2663	{
2664	for (uint32_t x = 0; x < cx; )
2665	{
2666	uint8_t bDst = 0;
2667	uint8_t fBit = 1;
2668	do
2669	{
2670	uintptr_t const idxPal = pbSrc[x] * 3;
2671	if ((( pThis->last_palette[idxPal]
2672	\| (pThis->last_palette[idxPal] >> 8)
2673	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2674	bDst \|= fBit;
2675	fBit <<= 1;
2676	x++;
2677	} while (x < cx && (x & 7));
2678	pbDst[(x - 1) / 8] = bDst;
2679	}
2680	pbDst += cbDstAndLine;
2681	pbSrc += cbSrcAndLine;
2682	}
2683	break;
2684	case 15:
2685	for (uint32_t y = 0; y < cy; y++)
2686	{
2687	for (uint32_t x = 0; x < cx; )
2688	{
2689	uint8_t bDst = 0;
2690	uint8_t fBit = 1;
2691	do
2692	{
2693	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2694	bDst \|= fBit;
2695	fBit <<= 1;
2696	x++;
2697	} while (x < cx && (x & 7));
2698	pbDst[(x - 1) / 8] = bDst;
2699	}
2700	pbDst += cbDstAndLine;
2701	pbSrc += cbSrcAndLine;
2702	}
2703	break;
2704	case 16:
2705	for (uint32_t y = 0; y < cy; y++)
2706	{
2707	for (uint32_t x = 0; x < cx; )
2708	{
2709	uint8_t bDst = 0;
2710	uint8_t fBit = 1;
2711	do
2712	{
2713	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2714	bDst \|= fBit;
2715	fBit <<= 1;
2716	x++;
2717	} while (x < cx && (x & 7));
2718	pbDst[(x - 1) / 8] = bDst;
2719	}
2720	pbDst += cbDstAndLine;
2721	pbSrc += cbSrcAndLine;
2722	}
2723	break;
2724	case 24:
2725	for (uint32_t y = 0; y < cy; y++)
2726	{
2727	for (uint32_t x = 0; x < cx; )
2728	{
2729	uint8_t bDst = 0;
2730	uint8_t fBit = 1;
2731	do
2732	{
2733	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2734	bDst \|= fBit;
2735	fBit <<= 1;
2736	x++;
2737	} while (x < cx && (x & 7));
2738	pbDst[(x - 1) / 8] = bDst;
2739	}
2740	pbDst += cbDstAndLine;
2741	pbSrc += cbSrcAndLine;
2742	}
2743	break;
2744	case 32:
2745	for (uint32_t y = 0; y < cy; y++)
2746	{
2747	for (uint32_t x = 0; x < cx; )
2748	{
2749	uint8_t bDst = 0;
2750	uint8_t fBit = 1;
2751	do
2752	{
2753	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2754	bDst \|= fBit;
2755	fBit <<= 1;
2756	x++;
2757	} while (x < cx && (x & 7));
2758	pbDst[(x - 1) / 8] = bDst;
2759	}
2760	pbDst += cbDstAndLine;
2761	pbSrc += cbSrcAndLine;
2762	}
2763	break;
2764	default:
2765	RTMemFree(pbCopy);
2766	AssertFailedReturnVoid();
2767	}
2768
2769	/* Convert the XOR mask. */
2770	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2771	pbSrc = pbSrcXorMask;
2772	switch (pCursor->xorMaskDepth)
2773	{
2774	case 1:
2775	for (uint32_t y = 0; y < cy; y++)
2776	{
2777	for (uint32_t x = 0; x < cx; )
2778	{
2779	/* most significant bit is the left most one. */
2780	uint8_t bSrc = pbSrc[x / 8];
2781	do
2782	{
2783	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2784	bSrc <<= 1;
2785	x++;
2786	} while ((x & 7) && x < cx);
2787	}
2788	pbSrc += cbSrcXorLine;
2789	}
2790	break;
2791	case 8:
2792	for (uint32_t y = 0; y < cy; y++)
2793	{
2794	for (uint32_t x = 0; x < cx; x++)
2795	{
2796	uint32_t u = pThis->last_palette[pbSrc[x]];
2797	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2798	}
2799	pbSrc += cbSrcXorLine;
2800	}
2801	break;
2802	case 15: /* Src: RGB-5-5-5 */
2803	for (uint32_t y = 0; y < cy; y++)
2804	{
2805	for (uint32_t x = 0; x < cx; x++)
2806	{
2807	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2808	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2809	((uValue >> 5) & 0x1f) << 3,
2810	((uValue >> 10) & 0x1f) << 3, 0);
2811	}
2812	pbSrc += cbSrcXorLine;
2813	}
2814	break;
2815	case 16: /* Src: RGB-5-6-5 */
2816	for (uint32_t y = 0; y < cy; y++)
2817	{
2818	for (uint32_t x = 0; x < cx; x++)
2819	{
2820	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2821	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2822	((uValue >> 5) & 0x3f) << 2,
2823	((uValue >> 11) & 0x1f) << 3, 0);
2824	}
2825	pbSrc += cbSrcXorLine;
2826	}
2827	break;
2828	case 24:
2829	for (uint32_t y = 0; y < cy; y++)
2830	{
2831	for (uint32_t x = 0; x < cx; x++)
2832	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2833	pbSrc += cbSrcXorLine;
2834	}
2835	break;
2836	case 32:
2837	for (uint32_t y = 0; y < cy; y++)
2838	{
2839	for (uint32_t x = 0; x < cx; x++)
2840	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2841	pbSrc += cbSrcXorLine;
2842	}
2843	break;
2844	default:
2845	RTMemFree(pbCopy);
2846	AssertFailedReturnVoid();
2847	}
2848
2849	/*
2850	* Pass it to the frontend/whatever.
2851	*/
2852	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2853	}
2854
2855
2856	/**
2857	* Worker for vmsvgaR3FifoThread that handles an external command.
2858	*
2859	* @param pThis VGA device instance data.
2860	*/
2861	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2862	{
2863	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2864	switch (pThis->svga.u8FIFOExtCommand)
2865	{
2866	case VMSVGA_FIFO_EXTCMD_RESET:
2867	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2868	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2869	# ifdef VBOX_WITH_VMSVGA3D
2870	if (pThis->svga.f3DEnabled)
2871	{
2872	/* The 3d subsystem must be reset from the fifo thread. */
2873	vmsvga3dReset(pThis);
2874	}
2875	# endif
2876	break;
2877
2878	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2879	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2880	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2881	# ifdef VBOX_WITH_VMSVGA3D
2882	if (pThis->svga.f3DEnabled)
2883	{
2884	/* The 3d subsystem must be shut down from the fifo thread. */
2885	vmsvga3dTerminate(pThis);
2886	}
2887	# endif
2888	break;
2889
2890	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2891	{
2892	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2893	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2894	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2895	vmsvgaSaveExecFifo(pThis, pSSM);
2896	# ifdef VBOX_WITH_VMSVGA3D
2897	if (pThis->svga.f3DEnabled)
2898	vmsvga3dSaveExec(pThis, pSSM);
2899	# endif
2900	break;
2901	}
2902
2903	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2904	{
2905	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2906	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2907	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2908	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2909	# ifdef VBOX_WITH_VMSVGA3D
2910	if (pThis->svga.f3DEnabled)
2911	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2912	# endif
2913	break;
2914	}
2915
2916	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2917	{
2918	# ifdef VBOX_WITH_VMSVGA3D
2919	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2920	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2921	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2922	# endif
2923	break;
2924	}
2925
2926
2927	default:
2928	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2929	break;
2930	}
2931
2932	/*
2933	* Signal the end of the external command.
2934	*/
2935	pThis->svga.pvFIFOExtCmdParam = NULL;
2936	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2937	ASMMemoryFence(); /* paranoia^2 */
2938	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2939	AssertLogRelRC(rc);
2940	}
2941
2942	/**
2943	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2944	* doing a job on the FIFO thread (even when it's officially suspended).
2945	*
2946	* @returns VBox status code (fully asserted).
2947	* @param pThis VGA device instance data.
2948	* @param uExtCmd The command to execute on the FIFO thread.
2949	* @param pvParam Pointer to command parameters.
2950	* @param cMsWait The time to wait for the command, given in
2951	* milliseconds.
2952	*/
2953	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2954	{
2955	Assert(cMsWait >= RT_MS_1SEC * 5);
2956	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2957	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2958
2959	int rc;
2960	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2961	PDMTHREADSTATE enmState = pThread->enmState;
2962	if (enmState == PDMTHREADSTATE_SUSPENDED)
2963	{
2964	/*
2965	* The thread is suspended, we have to temporarily wake it up so it can
2966	* perform the task.
2967	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2968	*/
2969	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2970	/* Post the request. */
2971	pThis->svga.fFifoExtCommandWakeup = true;
2972	pThis->svga.pvFIFOExtCmdParam = pvParam;
2973	pThis->svga.u8FIFOExtCommand = uExtCmd;
2974	ASMMemoryFence(); /* paranoia^3 */
2975
2976	/* Resume the thread. */
2977	rc = PDMR3ThreadResume(pThread);
2978	AssertLogRelRC(rc);
2979	if (RT_SUCCESS(rc))
2980	{
2981	/* Wait. Take care in case the semaphore was already posted (same as below). */
2982	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2983	if ( rc == VINF_SUCCESS
2984	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2985	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2986	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2987	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2988
2989	/* suspend the thread */
2990	pThis->svga.fFifoExtCommandWakeup = false;
2991	int rc2 = PDMR3ThreadSuspend(pThread);
2992	AssertLogRelRC(rc2);
2993	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2994	rc = rc2;
2995	}
2996	pThis->svga.fFifoExtCommandWakeup = false;
2997	pThis->svga.pvFIFOExtCmdParam = NULL;
2998	}
2999	else if (enmState == PDMTHREADSTATE_RUNNING)
3000	{
3001	/*
3002	* The thread is running, should only happen during reset and vmsvga3dsfc.
3003	* We ASSUME not racing code here, both wrt thread state and ext commands.
3004	*/
3005	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3006	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3007
3008	/* Post the request. */
3009	pThis->svga.pvFIFOExtCmdParam = pvParam;
3010	pThis->svga.u8FIFOExtCommand = uExtCmd;
3011	ASMMemoryFence(); /* paranoia^2 */
3012	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3013	AssertLogRelRC(rc);
3014
3015	/* Wait. Take care in case the semaphore was already posted (same as above). */
3016	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3017	if ( rc == VINF_SUCCESS
3018	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3019	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3020	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3021	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3022
3023	pThis->svga.pvFIFOExtCmdParam = NULL;
3024	}
3025	else
3026	{
3027	/*
3028	* Something is wrong with the thread!
3029	*/
3030	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3031	rc = VERR_INVALID_STATE;
3032	}
3033	return rc;
3034	}
3035
3036
3037	/**
3038	* Marks the FIFO non-busy, notifying any waiting EMTs.
3039	*
3040	* @param pThis The VGA state.
3041	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3042	* @param offFifoMin The start byte offset of the command FIFO.
3043	*/
3044	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3045	{
3046	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3047	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3048	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3049
3050	/* Wake up any waiting EMTs. */
3051	if (pSVGAState->cBusyDelayedEmts > 0)
3052	{
3053	#ifdef VMSVGA_USE_EMT_HALT_CODE
3054	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3055	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3056	if (idCpu != NIL_VMCPUID)
3057	{
3058	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3059	while (idCpu-- > 0)
3060	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3061	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3062	}
3063	#else
3064	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3065	AssertRC(rc2);
3066	#endif
3067	}
3068	}
3069
3070	/**
3071	* Reads (more) payload into the command buffer.
3072	*
3073	* @returns pbBounceBuf on success
3074	* @retval (void *)1 if the thread was requested to stop.
3075	* @retval NULL on FIFO error.
3076	*
3077	* @param cbPayloadReq The number of bytes of payload requested.
3078	* @param pFIFO The FIFO.
3079	* @param offCurrentCmd The FIFO byte offset of the current command.
3080	* @param offFifoMin The start byte offset of the command FIFO.
3081	* @param offFifoMax The end byte offset of the command FIFO.
3082	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3083	* always sufficient size.
3084	* @param pcbAlreadyRead How much payload we've already read into the bounce
3085	* buffer. (We will NEVER re-read anything.)
3086	* @param pThread The calling PDM thread handle.
3087	* @param pThis The VGA state.
3088	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3089	* statistics collection.
3090	*/
3091	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3092	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3093	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3094	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3095	{
3096	Assert(pbBounceBuf);
3097	Assert(pcbAlreadyRead);
3098	Assert(offFifoMin < offFifoMax);
3099	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3100	Assert(offFifoMax <= pThis->svga.cbFIFO);
3101
3102	/*
3103	* Check if the requested payload size has already been satisfied .
3104	* .
3105	* When called to read more, the caller is responsible for making sure the .
3106	* new command size (cbRequsted) never is smaller than what has already .
3107	* been read.
3108	*/
3109	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3110	if (cbPayloadReq <= cbAlreadyRead)
3111	{
3112	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3113	return pbBounceBuf;
3114	}
3115
3116	/*
3117	* Commands bigger than the fifo buffer are invalid.
3118	*/
3119	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3120	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3121	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3122	NULL);
3123
3124	/*
3125	* Move offCurrentCmd past the command dword.
3126	*/
3127	offCurrentCmd += sizeof(uint32_t);
3128	if (offCurrentCmd >= offFifoMax)
3129	offCurrentCmd = offFifoMin;
3130
3131	/*
3132	* Do we have sufficient payload data available already?
3133	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3134	*/
3135	uint32_t cbAfter, cbBefore;
3136	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3137	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3138	if (offNextCmd >= offCurrentCmd)
3139	{
3140	if (RT_LIKELY(offNextCmd < offFifoMax))
3141	cbAfter = offNextCmd - offCurrentCmd;
3142	else
3143	{
3144	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3145	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3146	offNextCmd, offFifoMin, offFifoMax));
3147	cbAfter = offFifoMax - offCurrentCmd;
3148	}
3149	cbBefore = 0;
3150	}
3151	else
3152	{
3153	cbAfter = offFifoMax - offCurrentCmd;
3154	if (offNextCmd >= offFifoMin)
3155	cbBefore = offNextCmd - offFifoMin;
3156	else
3157	{
3158	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3159	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3160	offNextCmd, offFifoMin, offFifoMax));
3161	cbBefore = 0;
3162	}
3163	}
3164	if (cbAfter + cbBefore < cbPayloadReq)
3165	{
3166	/*
3167	* Insufficient, must wait for it to arrive.
3168	*/
3169	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3170	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3171	for (uint32_t i = 0;; i++)
3172	{
3173	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3174	{
3175	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3176	return (void *)(uintptr_t)1;
3177	}
3178	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3179	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3180
3181	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3182
3183	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3184	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3185	if (offNextCmd >= offCurrentCmd)
3186	{
3187	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3188	cbBefore = 0;
3189	}
3190	else
3191	{
3192	cbAfter = offFifoMax - offCurrentCmd;
3193	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3194	}
3195
3196	if (cbAfter + cbBefore >= cbPayloadReq)
3197	break;
3198	}
3199	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3200	}
3201
3202	/*
3203	* Copy out the memory and update what pcbAlreadyRead points to.
3204	*/
3205	if (cbAfter >= cbPayloadReq)
3206	memcpy(pbBounceBuf + cbAlreadyRead,
3207	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3208	cbPayloadReq - cbAlreadyRead);
3209	else
3210	{
3211	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3212	if (cbAlreadyRead < cbAfter)
3213	{
3214	memcpy(pbBounceBuf + cbAlreadyRead,
3215	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3216	cbAfter - cbAlreadyRead);
3217	cbAlreadyRead = cbAfter;
3218	}
3219	memcpy(pbBounceBuf + cbAlreadyRead,
3220	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3221	cbPayloadReq - cbAlreadyRead);
3222	}
3223	*pcbAlreadyRead = cbPayloadReq;
3224	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3225	return pbBounceBuf;
3226	}
3227
3228
3229	/**
3230	* Sends cursor position and visibility information from the FIFO to the front-end.
3231	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3232	*/
3233	static uint32_t
3234	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3235	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3236	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3237	{
3238	/*
3239	* Check if the cursor update counter has changed and try get a stable
3240	* set of values if it has. This is race-prone, especially consindering
3241	* the screen ID, but little we can do about that.
3242	*/
3243	uint32_t x, y, fVisible, idScreen;
3244	for (uint32_t i = 0; ; i++)
3245	{
3246	x = pFIFO[SVGA_FIFO_CURSOR_X];
3247	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3248	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3249	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3250	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3251	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3252	\|\| i > 3)
3253	break;
3254	if (i == 0)
3255	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3256	ASMNopPause();
3257	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3258	}
3259
3260	/*
3261	* Check if anything has changed, as calling into pDrv is not light-weight.
3262	*/
3263	if ( *pxLast == x
3264	&& *pyLast == y
3265	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3266	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3267	else
3268	{
3269	/*
3270	* Detected changes.
3271	*
3272	* We handle global, not per-screen visibility information by sending
3273	* pfnVBVAMousePointerShape without shape data.
3274	*/
3275	*pxLast = x;
3276	*pyLast = y;
3277	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3278	if (idScreen != SVGA_ID_INVALID)
3279	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3280	else if (*pfLastVisible != fVisible)
3281	{
3282	*pfLastVisible = fVisible;
3283	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3284	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3285	}
3286	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3287	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3288	}
3289
3290	/*
3291	* Update done. Signal this to the guest.
3292	*/
3293	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3294
3295	return uCursorUpdateCount;
3296	}
3297
3298
3299	/**
3300	* Checks if there is work to be done, either cursor updating or FIFO commands.
3301	*
3302	* @returns true if pending work, false if not.
3303	* @param pFIFO The FIFO to examine.
3304	* @param uLastCursorCount The last cursor update counter value.
3305	*/
3306	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3307	{
3308	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3309	return true;
3310
3311	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3312	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3313	return true;
3314
3315	return false;
3316	}
3317
3318
3319	/**
3320	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3321	*
3322	* @param pThis The VGA state.
3323	*/
3324	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3325	{
3326	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3327	to recheck it before doing the signalling. */
3328	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3329	AssertReturnVoid(pThis->svga.pFIFOR3);
3330	if ( vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount)
3331	&& pThis->svga.fFIFOThreadSleeping)
3332	{
3333	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3334	AssertRC(rc);
3335	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3336	}
3337	}
3338
3339
3340	/* The async FIFO handling thread. */
3341	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3342	{
3343	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3344	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3345	int rc;
3346
3347	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3348	return VINF_SUCCESS;
3349
3350	/*
3351	* Special mode where we only execute an external command and the go back
3352	* to being suspended. Currently, all ext cmds ends up here, with the reset
3353	* one also being eligble for runtime execution further down as well.
3354	*/
3355	if (pThis->svga.fFifoExtCommandWakeup)
3356	{
3357	vmsvgaR3FifoHandleExtCmd(pThis);
3358	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3359	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3360	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3361	else
3362	vmsvgaR3FifoHandleExtCmd(pThis);
3363	return VINF_SUCCESS;
3364	}
3365
3366
3367	/*
3368	* Signal the semaphore to make sure we don't wait for 250ms after a
3369	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3370	*/
3371	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3372
3373	/*
3374	* Allocate a bounce buffer for command we get from the FIFO.
3375	* (All code must return via the end of the function to free this buffer.)
3376	*/
3377	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3378	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3379
3380	/*
3381	* Polling/sleep interval config.
3382	*
3383	* We wait for an a short interval if the guest has recently given us work
3384	* to do, but the interval increases the longer we're kept idle. Once we've
3385	* reached the refresh timer interval, we'll switch to extended waits,
3386	* depending on it or the guest to kick us into action when needed.
3387	*
3388	* Should the refresh time go fishing, we'll just continue increasing the
3389	* sleep length till we reaches the 250 ms max after about 16 seconds.
3390	*/
3391	RTMSINTERVAL const cMsMinSleep = 16;
3392	RTMSINTERVAL const cMsIncSleep = 2;
3393	RTMSINTERVAL const cMsMaxSleep = 250;
3394	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3395	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3396
3397	/*
3398	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3399	* Initialize with values that will trigger an update as soon as maybe.
3400	*/
3401	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3402	uint32_t uLastCursorCount = pThis->svga.uLastCursorUpdateCount = ~pFIFO[SVGA_FIFO_CURSOR_COUNT];
3403	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3404	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3405	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3406
3407	/*
3408	* The FIFO loop.
3409	*/
3410	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3411	bool fBadOrDisabledFifo = false;
3412	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3413	{
3414	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3415	/*
3416	* Should service the run loop every so often.
3417	*/
3418	if (pThis->svga.f3DEnabled)
3419	vmsvga3dCocoaServiceRunLoop();
3420	# endif
3421
3422	/*
3423	* Unless there's already work pending, go to sleep for a short while.
3424	* (See polling/sleep interval config above.)
3425	*/
3426	if ( fBadOrDisabledFifo
3427	\|\| !vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3428	{
3429	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3430	Assert(pThis->cMilliesRefreshInterval > 0);
3431	if (cMsSleep < pThis->cMilliesRefreshInterval)
3432	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3433	else
3434	{
3435	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3436	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3437	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3438	# endif
3439	if ( !fBadOrDisabledFifo
3440	&& vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3441	rc = VINF_SUCCESS;
3442	else
3443	{
3444	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3445	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3446	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3447	}
3448	}
3449	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3450	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3451	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3452	{
3453	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3454	break;
3455	}
3456	}
3457	else
3458	rc = VINF_SUCCESS;
3459	fBadOrDisabledFifo = false;
3460	if (rc == VERR_TIMEOUT)
3461	{
3462	if (!vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3463	{
3464	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3465	continue;
3466	}
3467	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3468
3469	Log(("vmsvgaFIFOLoop: timeout\n"));
3470	}
3471	else if (vmsvgaFIFOHasWork(pFIFO, uLastCursorCount))
3472	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3473	cMsSleep = cMsMinSleep;
3474
3475	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3476	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3477	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3478
3479	/*
3480	* Handle external commands (currently only reset).
3481	*/
3482	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3483	{
3484	vmsvgaR3FifoHandleExtCmd(pThis);
3485	continue;
3486	}
3487
3488	/*
3489	* The device must be enabled and configured.
3490	*/
3491	if ( !pThis->svga.fEnabled
3492	\|\| !pThis->svga.fConfigured)
3493	{
3494	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3495	fBadOrDisabledFifo = true;
3496	cMsSleep = cMsMaxSleep; /* cheat */
3497	continue;
3498	}
3499
3500	/*
3501	* Get and check the min/max values. We ASSUME that they will remain
3502	* unchanged while we process requests. A further ASSUMPTION is that
3503	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3504	* we don't read it back while in the loop.
3505	*/
3506	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3507	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3508	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3509	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3510	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3511	\|\| offFifoMax <= offFifoMin
3512	\|\| offFifoMax > pThis->svga.cbFIFO
3513	\|\| (offFifoMax & 3) != 0
3514	\|\| (offFifoMin & 3) != 0
3515	\|\| offCurrentCmd < offFifoMin
3516	\|\| offCurrentCmd > offFifoMax))
3517	{
3518	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3519	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3520	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3521	fBadOrDisabledFifo = true;
3522	continue;
3523	}
3524	RT_UNTRUSTED_VALIDATED_FENCE();
3525	if (RT_UNLIKELY(offCurrentCmd & 3))
3526	{
3527	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3528	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3529	offCurrentCmd = ~UINT32_C(3);
3530	}
3531
3532	/*
3533	* Update the cursor position before we start on the FIFO commands.
3534	*/
3535	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3536	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3537	{
3538	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3539	if (uCursorUpdateCount == uLastCursorCount)
3540	{ /* halfways likely */ }
3541	else
3542	{
3543	uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3544	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3545	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3546	}
3547	}
3548
3549	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3550	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3551	*
3552	* Will break out of the switch on failure.
3553	* Will restart and quit the loop if the thread was requested to stop.
3554	*
3555	* @param a_PtrVar Request variable pointer.
3556	* @param a_Type Request typedef (not pointer) for casting.
3557	* @param a_cbPayloadReq How much payload to fetch.
3558	* @remarks Accesses a bunch of variables in the current scope!
3559	*/
3560	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3561	if (1) { \
3562	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3563	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3564	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3565	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3566	} else do {} while (0)
3567	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3568	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3569	* buffer after figuring out the actual command size.
3570	*
3571	* Will break out of the switch on failure.
3572	*
3573	* @param a_PtrVar Request variable pointer.
3574	* @param a_Type Request typedef (not pointer) for casting.
3575	* @param a_cbPayloadReq How much payload to fetch.
3576	* @remarks Accesses a bunch of variables in the current scope!
3577	*/
3578	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3579	if (1) { \
3580	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3581	} else do {} while (0)
3582
3583	/*
3584	* Mark the FIFO as busy.
3585	*/
3586	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3587	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3588	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3589
3590	/*
3591	* Execute all queued FIFO commands.
3592	* Quit if pending external command or changes in the thread state.
3593	*/
3594	bool fDone = false;
3595	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3596	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3597	{
3598	uint32_t cbPayload = 0;
3599	uint32_t u32IrqStatus = 0;
3600
3601	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3602
3603	/* First check any pending actions. */
3604	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3605	{
3606	vmsvgaChangeMode(pThis);
3607	# ifdef VBOX_WITH_VMSVGA3D
3608	if (pThis->svga.p3dState != NULL)
3609	vmsvga3dChangeMode(pThis);
3610	# endif
3611	}
3612
3613	/* Check for pending external commands (reset). */
3614	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3615	break;
3616
3617	/*
3618	* Process the command.
3619	*/
3620	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3621	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3622	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3623	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3624	switch (enmCmdId)
3625	{
3626	case SVGA_CMD_INVALID_CMD:
3627	/* Nothing to do. */
3628	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3629	break;
3630
3631	case SVGA_CMD_FENCE:
3632	{
3633	SVGAFifoCmdFence *pCmdFence;
3634	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3635	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3636	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3637	{
3638	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3639	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3640
3641	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3642	{
3643	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3644	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3645	}
3646	else
3647	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3648	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3649	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3650	{
3651	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3652	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3653	}
3654	}
3655	else
3656	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3657	break;
3658	}
3659	case SVGA_CMD_UPDATE:
3660	case SVGA_CMD_UPDATE_VERBOSE:
3661	{
3662	SVGAFifoCmdUpdate *pUpdate;
3663	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3664	if (enmCmdId == SVGA_CMD_UPDATE)
3665	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3666	else
3667	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3668	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3669	/** @todo Multiple screens? */
3670	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3671	AssertBreak(pScreen);
3672	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3673	break;
3674	}
3675
3676	case SVGA_CMD_DEFINE_CURSOR:
3677	{
3678	/* Followed by bitmap data. */
3679	SVGAFifoCmdDefineCursor *pCursor;
3680	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3681	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3682
3683	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3684	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3685	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3686	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3687	AssertBreak(pCursor->andMaskDepth <= 32);
3688	AssertBreak(pCursor->xorMaskDepth <= 32);
3689	RT_UNTRUSTED_VALIDATED_FENCE();
3690
3691	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3692	uint32_t cbAndMask = cbAndLine * pCursor->height;
3693	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3694	uint32_t cbXorMask = cbXorLine * pCursor->height;
3695	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3696
3697	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3698	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3699	break;
3700	}
3701
3702	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3703	{
3704	/* Followed by bitmap data. */
3705	uint32_t cbCursorShape, cbAndMask;
3706	uint8_t *pCursorCopy;
3707	uint32_t cbCmd;
3708
3709	SVGAFifoCmdDefineAlphaCursor *pCursor;
3710	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3711	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3712
3713	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3714
3715	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3716	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3717	RT_UNTRUSTED_VALIDATED_FENCE();
3718
3719	/* Refetch the bitmap data as well. */
3720	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3721	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3722	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3723
3724	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3725	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3726	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3727	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3728
3729	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3730	AssertBreak(pCursorCopy);
3731
3732	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3733	memset(pCursorCopy, 0xff, cbAndMask);
3734	/* Colour data */
3735	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3736
3737	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3738	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3739	break;
3740	}
3741
3742	case SVGA_CMD_ESCAPE:
3743	{
3744	/* Followed by nsize bytes of data. */
3745	SVGAFifoCmdEscape *pEscape;
3746	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3747	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3748
3749	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3750	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3751	RT_UNTRUSTED_VALIDATED_FENCE();
3752	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3753	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3754
3755	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3756	{
3757	AssertBreak(pEscape->size >= sizeof(uint32_t));
3758	RT_UNTRUSTED_VALIDATED_FENCE();
3759	uint32_t cmd = (uint32_t )(pEscape + 1);
3760	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3761
3762	switch (cmd)
3763	{
3764	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3765	{
3766	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3767	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3768	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3769
3770	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3771	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3772	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3773
3774	RT_NOREF_PV(pVideoCmd);
3775	break;
3776
3777	}
3778
3779	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3780	{
3781	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3782	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3783	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3784	RT_NOREF_PV(pVideoCmd);
3785	break;
3786	}
3787
3788	default:
3789	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3790	break;
3791	}
3792	}
3793	else
3794	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3795
3796	break;
3797	}
3798	# ifdef VBOX_WITH_VMSVGA3D
3799	case SVGA_CMD_DEFINE_GMR2:
3800	{
3801	SVGAFifoCmdDefineGMR2 *pCmd;
3802	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3803	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3805
3806	/* Validate current GMR id. */
3807	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3808	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3809	RT_UNTRUSTED_VALIDATED_FENCE();
3810
3811	if (!pCmd->numPages)
3812	{
3813	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3814	vmsvgaGMRFree(pThis, pCmd->gmrId);
3815	}
3816	else
3817	{
3818	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3819	if (pGMR->cMaxPages)
3820	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3821
3822	/* Not sure if we should always free the descriptor, but for simplicity
3823	we do so if the new size is smaller than the current. */
3824	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3825	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3826	vmsvgaGMRFree(pThis, pCmd->gmrId);
3827
3828	pGMR->cMaxPages = pCmd->numPages;
3829	/* The rest is done by the REMAP_GMR2 command. */
3830	}
3831	break;
3832	}
3833
3834	case SVGA_CMD_REMAP_GMR2:
3835	{
3836	/* Followed by page descriptors or guest ptr. */
3837	SVGAFifoCmdRemapGMR2 *pCmd;
3838	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3839	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3840
3841	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3842	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3843	RT_UNTRUSTED_VALIDATED_FENCE();
3844
3845	/* Calculate the size of what comes after next and fetch it. */
3846	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3847	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3848	cbCmd += sizeof(SVGAGuestPtr);
3849	else
3850	{
3851	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3852	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3853	{
3854	cbCmd += cbPageDesc;
3855	pCmd->numPages = 1;
3856	}
3857	else
3858	{
3859	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3860	cbCmd += cbPageDesc * pCmd->numPages;
3861	}
3862	}
3863	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3864
3865	/* Validate current GMR id and size. */
3866	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3867	RT_UNTRUSTED_VALIDATED_FENCE();
3868	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3869	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3870	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3871	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3872
3873	if (pCmd->numPages == 0)
3874	break;
3875
3876	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3877	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3878
3879	/*
3880	* We flatten the existing descriptors into a page array, overwrite the
3881	* pages specified in this command and then recompress the descriptor.
3882	*/
3883	/** @todo Optimize the GMR remap algorithm! */
3884
3885	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3886	uint64_t *paNewPage64 = NULL;
3887	if (pGMR->paDesc)
3888	{
3889	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3890
3891	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3892	AssertBreak(paNewPage64);
3893
3894	uint32_t idxPage = 0;
3895	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3896	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3897	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3898	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3899	RT_UNTRUSTED_VALIDATED_FENCE();
3900	}
3901
3902	/* Free the old GMR if present. */
3903	if (pGMR->paDesc)
3904	RTMemFree(pGMR->paDesc);
3905
3906	/* Allocate the maximum amount possible (everything non-continuous) */
3907	PVMSVGAGMRDESCRIPTOR paDescs;
3908	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3909	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3910
3911	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3912	{
3913	/** @todo */
3914	AssertFailed();
3915	pGMR->numDescriptors = 0;
3916	}
3917	else
3918	{
3919	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3920	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3921	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3922
3923	if (paNewPage64)
3924	{
3925	/* Overwrite the old page array with the new page values. */
3926	if (fGCPhys64)
3927	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3928	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3929	else
3930	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3931	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3932
3933	/* Use the updated page array instead of the command data. */
3934	fGCPhys64 = true;
3935	paPages64 = paNewPage64;
3936	pCmd->numPages = cNewTotalPages;
3937	}
3938
3939	/* The first page. */
3940	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3941	* applied to paNewPage64. */
3942	RTGCPHYS GCPhys;
3943	if (fGCPhys64)
3944	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3945	else
3946	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3947	paDescs[0].GCPhys = GCPhys;
3948	paDescs[0].numPages = 1;
3949
3950	/* Subsequent pages. */
3951	uint32_t iDescriptor = 0;
3952	for (uint32_t i = 1; i < pCmd->numPages; i++)
3953	{
3954	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3955	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3956	else
3957	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3958
3959	/* Continuous physical memory? */
3960	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3961	{
3962	Assert(paDescs[iDescriptor].numPages);
3963	paDescs[iDescriptor].numPages++;
3964	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3965	}
3966	else
3967	{
3968	iDescriptor++;
3969	paDescs[iDescriptor].GCPhys = GCPhys;
3970	paDescs[iDescriptor].numPages = 1;
3971	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3972	}
3973	}
3974
3975	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3976	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3977	pGMR->numDescriptors = iDescriptor + 1;
3978	}
3979
3980	if (paNewPage64)
3981	RTMemFree(paNewPage64);
3982
3983	# ifdef DEBUG_GMR_ACCESS
3984	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3985	# endif
3986	break;
3987	}
3988	# endif // VBOX_WITH_VMSVGA3D
3989	case SVGA_CMD_DEFINE_SCREEN:
3990	{
3991	/* The size of this command is specified by the guest and depends on capabilities. */
3992	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
3993
3994	SVGAFifoCmdDefineScreen *pCmd;
3995	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
3996	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
3997	RT_UNTRUSTED_VALIDATED_FENCE();
3998
3999	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4000	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4001	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4002
4003	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4004	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4005	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4006
4007	uint32_t const idScreen = pCmd->screen.id;
4008	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4009
4010	uint32_t const uWidth = pCmd->screen.size.width;
4011	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4012
4013	uint32_t const uHeight = pCmd->screen.size.height;
4014	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4015
4016	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4017	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4018	AssertBreak(cbWidth <= cbPitch);
4019
4020	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4021	AssertBreak(uScreenOffset < pThis->vram_size);
4022
4023	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4024	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4025	AssertBreak( (uHeight == 0 && cbPitch == 0)
4026	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4027	RT_UNTRUSTED_VALIDATED_FENCE();
4028
4029	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4030
4031	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4032
4033	pScreen->fDefined = true;
4034	pScreen->fModified = true;
4035	pScreen->fuScreen = pCmd->screen.flags;
4036	pScreen->idScreen = idScreen;
4037	if (!fBlank)
4038	{
4039	AssertBreak(uWidth > 0 && uHeight > 0);
4040
4041	pScreen->xOrigin = pCmd->screen.root.x;
4042	pScreen->yOrigin = pCmd->screen.root.y;
4043	pScreen->cWidth = uWidth;
4044	pScreen->cHeight = uHeight;
4045	pScreen->offVRAM = uScreenOffset;
4046	pScreen->cbPitch = cbPitch;
4047	pScreen->cBpp = 32;
4048	}
4049	else
4050	{
4051	/* Keep old values. */
4052	}
4053
4054	pThis->svga.fGFBRegisters = false;
4055	vmsvgaChangeMode(pThis);
4056	break;
4057	}
4058
4059	case SVGA_CMD_DESTROY_SCREEN:
4060	{
4061	SVGAFifoCmdDestroyScreen *pCmd;
4062	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4063	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4064
4065	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4066
4067	uint32_t const idScreen = pCmd->screenId;
4068	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4069	RT_UNTRUSTED_VALIDATED_FENCE();
4070
4071	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4072	pScreen->fModified = true;
4073	pScreen->fDefined = false;
4074	pScreen->idScreen = idScreen;
4075
4076	vmsvgaChangeMode(pThis);
4077	break;
4078	}
4079
4080	case SVGA_CMD_DEFINE_GMRFB:
4081	{
4082	SVGAFifoCmdDefineGMRFB *pCmd;
4083	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4084	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4085
4086	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4087	pSVGAState->GMRFB.ptr = pCmd->ptr;
4088	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4089	pSVGAState->GMRFB.format = pCmd->format;
4090	break;
4091	}
4092
4093	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4094	{
4095	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4096	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4097	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4098
4099	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4100	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4101
4102	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4103	RT_UNTRUSTED_VALIDATED_FENCE();
4104
4105	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4106	AssertBreak(pScreen);
4107
4108	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4109	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4110
4111	/* Clip destRect to the screen dimensions. */
4112	SVGASignedRect screenRect;
4113	screenRect.left = 0;
4114	screenRect.top = 0;
4115	screenRect.right = pScreen->cWidth;
4116	screenRect.bottom = pScreen->cHeight;
4117	SVGASignedRect clipRect = pCmd->destRect;
4118	vmsvgaClipRect(&screenRect, &clipRect);
4119	RT_UNTRUSTED_VALIDATED_FENCE();
4120
4121	uint32_t const width = clipRect.right - clipRect.left;
4122	uint32_t const height = clipRect.bottom - clipRect.top;
4123
4124	if ( width == 0
4125	\|\| height == 0)
4126	break; /* Nothing to do. */
4127
4128	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4129	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4130
4131	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4132	* Prepare parameters for vmsvgaGMRTransfer.
4133	*/
4134	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4135
4136	/* Destination: host buffer which describes the screen 0 VRAM.
4137	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4138	*/
4139	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4140	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4141	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4142	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4143	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4144	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4145	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4146	+ cbScanline * clipRect.top;
4147	int32_t const cbHstPitch = cbScanline;
4148
4149	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4150	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4151	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4152	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4153	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4154
4155	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4156	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4157	gstPtr, offGst, cbGstPitch,
4158	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4159	AssertRC(rc);
4160	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4161	break;
4162	}
4163
4164	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4165	{
4166	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4167	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4168	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4169
4170	/* Note! This can fetch 3d render results as well!! */
4171	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4172	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4173
4174	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4175	RT_UNTRUSTED_VALIDATED_FENCE();
4176
4177	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4178	AssertBreak(pScreen);
4179
4180	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4181	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4182
4183	/* Clip destRect to the screen dimensions. */
4184	SVGASignedRect screenRect;
4185	screenRect.left = 0;
4186	screenRect.top = 0;
4187	screenRect.right = pScreen->cWidth;
4188	screenRect.bottom = pScreen->cHeight;
4189	SVGASignedRect clipRect = pCmd->srcRect;
4190	vmsvgaClipRect(&screenRect, &clipRect);
4191	RT_UNTRUSTED_VALIDATED_FENCE();
4192
4193	uint32_t const width = clipRect.right - clipRect.left;
4194	uint32_t const height = clipRect.bottom - clipRect.top;
4195
4196	if ( width == 0
4197	\|\| height == 0)
4198	break; /* Nothing to do. */
4199
4200	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4201	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4202
4203	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4204	* Prepare parameters for vmsvgaGMRTransfer.
4205	*/
4206	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4207
4208	/* Source: host buffer which describes the screen 0 VRAM.
4209	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4210	*/
4211	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4212	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4213	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4214	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4215	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4216	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4217	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4218	+ cbScanline * clipRect.top;
4219	int32_t const cbHstPitch = cbScanline;
4220
4221	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4222	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4223	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4224	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4225	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4226
4227	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4228	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4229	gstPtr, offGst, cbGstPitch,
4230	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4231	AssertRC(rc);
4232	break;
4233	}
4234
4235	case SVGA_CMD_ANNOTATION_FILL:
4236	{
4237	SVGAFifoCmdAnnotationFill *pCmd;
4238	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4239	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4240
4241	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4242	pSVGAState->colorAnnotation = pCmd->color;
4243	break;
4244	}
4245
4246	case SVGA_CMD_ANNOTATION_COPY:
4247	{
4248	SVGAFifoCmdAnnotationCopy *pCmd;
4249	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4250	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4251
4252	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4253	AssertFailed();
4254	break;
4255	}
4256
4257	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4258
4259	default:
4260	# ifdef VBOX_WITH_VMSVGA3D
4261	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4262	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4263	{
4264	RT_UNTRUSTED_VALIDATED_FENCE();
4265
4266	/* All 3d commands start with a common header, which defines the size of the command. */
4267	SVGA3dCmdHeader *pHdr;
4268	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4269	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4270	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4271	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4272
4273	if (RT_LIKELY(pThis->svga.f3DEnabled))
4274	{ /* likely */ }
4275	else
4276	{
4277	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4278	break;
4279	}
4280
4281	/**
4282	* Check that the 3D command has at least a_cbMin of payload bytes after the
4283	* header. Will break out of the switch if it doesn't.
4284	*/
4285	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4286	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4287	RT_UNTRUSTED_VALIDATED_FENCE(); \
4288	} while (0)
4289	switch ((int)enmCmdId)
4290	{
4291	case SVGA_3D_CMD_SURFACE_DEFINE:
4292	{
4293	uint32_t cMipLevels;
4294	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4295	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4296	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4297
4298	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4299	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4300	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4301	# ifdef DEBUG_GMR_ACCESS
4302	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4303	# endif
4304	break;
4305	}
4306
4307	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4308	{
4309	uint32_t cMipLevels;
4310	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4311	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4312	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4313
4314	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4315	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4316	pCmd->multisampleCount, pCmd->autogenFilter,
4317	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4318	break;
4319	}
4320
4321	case SVGA_3D_CMD_SURFACE_DESTROY:
4322	{
4323	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4324	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4326	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4327	break;
4328	}
4329
4330	case SVGA_3D_CMD_SURFACE_COPY:
4331	{
4332	uint32_t cCopyBoxes;
4333	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4334	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4335	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4336
4337	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4338	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4339	break;
4340	}
4341
4342	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4343	{
4344	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4345	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4346	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4347
4348	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4349	break;
4350	}
4351
4352	case SVGA_3D_CMD_SURFACE_DMA:
4353	{
4354	uint32_t cCopyBoxes;
4355	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4356	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4357	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4358
4359	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4360	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4361	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4362	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4363	break;
4364	}
4365
4366	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4367	{
4368	uint32_t cRects;
4369	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4370	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4372
4373	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4374	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4375	break;
4376	}
4377
4378	case SVGA_3D_CMD_CONTEXT_DEFINE:
4379	{
4380	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4381	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4383
4384	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4385	break;
4386	}
4387
4388	case SVGA_3D_CMD_CONTEXT_DESTROY:
4389	{
4390	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4391	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4392	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4393
4394	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4395	break;
4396	}
4397
4398	case SVGA_3D_CMD_SETTRANSFORM:
4399	{
4400	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4401	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4403
4404	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4405	break;
4406	}
4407
4408	case SVGA_3D_CMD_SETZRANGE:
4409	{
4410	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4411	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4412	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4413
4414	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4415	break;
4416	}
4417
4418	case SVGA_3D_CMD_SETRENDERSTATE:
4419	{
4420	uint32_t cRenderStates;
4421	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4422	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4423	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4424
4425	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4426	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4427	break;
4428	}
4429
4430	case SVGA_3D_CMD_SETRENDERTARGET:
4431	{
4432	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4433	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4434	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4435
4436	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4437	break;
4438	}
4439
4440	case SVGA_3D_CMD_SETTEXTURESTATE:
4441	{
4442	uint32_t cTextureStates;
4443	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4446
4447	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4448	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4449	break;
4450	}
4451
4452	case SVGA_3D_CMD_SETMATERIAL:
4453	{
4454	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4455	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4457
4458	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4459	break;
4460	}
4461
4462	case SVGA_3D_CMD_SETLIGHTDATA:
4463	{
4464	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4465	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4466	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4467
4468	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4469	break;
4470	}
4471
4472	case SVGA_3D_CMD_SETLIGHTENABLED:
4473	{
4474	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4475	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4476	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4477
4478	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4479	break;
4480	}
4481
4482	case SVGA_3D_CMD_SETVIEWPORT:
4483	{
4484	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4485	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4486	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4487
4488	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4489	break;
4490	}
4491
4492	case SVGA_3D_CMD_SETCLIPPLANE:
4493	{
4494	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4495	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4496	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4497
4498	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4499	break;
4500	}
4501
4502	case SVGA_3D_CMD_CLEAR:
4503	{
4504	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4505	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4506	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4507
4508	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4509	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4510	break;
4511	}
4512
4513	case SVGA_3D_CMD_PRESENT:
4514	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4515	{
4516	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4517	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4518	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4520	else
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4522
4523	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4524
4525	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4526	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4527	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4528	break;
4529	}
4530
4531	case SVGA_3D_CMD_SHADER_DEFINE:
4532	{
4533	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4534	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4535	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4536
4537	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4538	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4539	break;
4540	}
4541
4542	case SVGA_3D_CMD_SHADER_DESTROY:
4543	{
4544	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4545	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4546	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4547
4548	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4549	break;
4550	}
4551
4552	case SVGA_3D_CMD_SET_SHADER:
4553	{
4554	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4555	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4556	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4557
4558	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4559	break;
4560	}
4561
4562	case SVGA_3D_CMD_SET_SHADER_CONST:
4563	{
4564	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4565	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4566	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4567
4568	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4569	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4570	break;
4571	}
4572
4573	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4574	{
4575	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4576	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4578
4579	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4580	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4581	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4582	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4583	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4584
4585	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4586	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4587
4588	RT_UNTRUSTED_VALIDATED_FENCE();
4589
4590	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4591	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4592	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4593
4594	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4595	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4596	pNumRange, cVertexDivisor, pVertexDivisor);
4597	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4598	break;
4599	}
4600
4601	case SVGA_3D_CMD_SETSCISSORRECT:
4602	{
4603	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4604	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4605	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4606
4607	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4608	break;
4609	}
4610
4611	case SVGA_3D_CMD_BEGIN_QUERY:
4612	{
4613	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4614	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4616
4617	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4618	break;
4619	}
4620
4621	case SVGA_3D_CMD_END_QUERY:
4622	{
4623	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4624	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4625	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4626
4627	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4628	break;
4629	}
4630
4631	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4632	{
4633	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4634	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4635	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4636
4637	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4638	break;
4639	}
4640
4641	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4642	{
4643	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4644	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4645	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4646
4647	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4648	break;
4649	}
4650
4651	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4652	/* context id + surface id? */
4653	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4654	break;
4655	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4656	/* context id + surface id? */
4657	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4658	break;
4659
4660	default:
4661	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4662	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4663	break;
4664	}
4665	}
4666	else
4667	# endif // VBOX_WITH_VMSVGA3D
4668	{
4669	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4670	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4671	}
4672	}
4673
4674	/* Go to the next slot */
4675	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4676	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4677	if (offCurrentCmd >= offFifoMax)
4678	{
4679	offCurrentCmd -= offFifoMax - offFifoMin;
4680	Assert(offCurrentCmd >= offFifoMin);
4681	Assert(offCurrentCmd < offFifoMax);
4682	}
4683	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4684	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4685
4686	/*
4687	* Raise IRQ if required. Must enter the critical section here
4688	* before making final decisions here, otherwise cubebench and
4689	* others may end up waiting forever.
4690	*/
4691	if ( u32IrqStatus
4692	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4693	{
4694	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4695	AssertRC(rc2);
4696
4697	/* FIFO progress might trigger an interrupt. */
4698	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4699	{
4700	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4701	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4702	}
4703
4704	/* Unmasked IRQ pending? */
4705	if (pThis->svga.u32IrqMask & u32IrqStatus)
4706	{
4707	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4708	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4709	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4710	}
4711
4712	PDMCritSectLeave(&pThis->CritSect);
4713	}
4714	}
4715
4716	/* If really done, clear the busy flag. */
4717	if (fDone)
4718	{
4719	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4720	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4721	}
4722	}
4723
4724	/*
4725	* Free the bounce buffer. (There are no returns above!)
4726	*/
4727	RTMemFree(pbBounceBuf);
4728
4729	return VINF_SUCCESS;
4730	}
4731
4732	/**
4733	* Free the specified GMR
4734	*
4735	* @param pThis VGA device instance data.
4736	* @param idGMR GMR id
4737	*/
4738	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4739	{
4740	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4741
4742	/* Free the old descriptor if present. */
4743	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4744	if ( pGMR->numDescriptors
4745	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4746	{
4747	# ifdef DEBUG_GMR_ACCESS
4748	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4749	# endif
4750
4751	Assert(pGMR->paDesc);
4752	RTMemFree(pGMR->paDesc);
4753	pGMR->paDesc = NULL;
4754	pGMR->numDescriptors = 0;
4755	pGMR->cbTotal = 0;
4756	pGMR->cMaxPages = 0;
4757	}
4758	Assert(!pGMR->cMaxPages);
4759	Assert(!pGMR->cbTotal);
4760	}
4761
4762	/**
4763	* Copy between a GMR and a host memory buffer.
4764	*
4765	* @returns VBox status code.
4766	* @param pThis VGA device instance data.
4767	* @param enmTransferType Transfer type (read/write)
4768	* @param pbHstBuf Host buffer pointer (valid)
4769	* @param cbHstBuf Size of host buffer (valid)
4770	* @param offHst Host buffer offset of the first scanline
4771	* @param cbHstPitch Destination buffer pitch
4772	* @param gstPtr GMR description
4773	* @param offGst Guest buffer offset of the first scanline
4774	* @param cbGstPitch Guest buffer pitch
4775	* @param cbWidth Width in bytes to copy
4776	* @param cHeight Number of scanllines to copy
4777	*/
4778	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4779	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4780	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4781	uint32_t cbWidth, uint32_t cHeight)
4782	{
4783	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4784	int rc;
4785
4786	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4787	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4788	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4789	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4790	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4791
4792	PGMR pGMR;
4793	uint32_t cbGmr; /* The GMR size in bytes. */
4794	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4795	{
4796	pGMR = NULL;
4797	cbGmr = pThis->vram_size;
4798	}
4799	else
4800	{
4801	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4802	RT_UNTRUSTED_VALIDATED_FENCE();
4803	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4804	cbGmr = pGMR->cbTotal;
4805	}
4806
4807	/*
4808	* GMR
4809	*/
4810	/* Calculate GMR offset of the data to be copied. */
4811	AssertMsgReturn(gstPtr.offset < cbGmr,
4812	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4813	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4814	VERR_INVALID_PARAMETER);
4815	RT_UNTRUSTED_VALIDATED_FENCE();
4816	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4817	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4818	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4819	VERR_INVALID_PARAMETER);
4820	RT_UNTRUSTED_VALIDATED_FENCE();
4821	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4822
4823	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4824	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4825	AssertMsgReturn(cbGmrScanline != 0,
4826	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4827	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4828	VERR_INVALID_PARAMETER);
4829	RT_UNTRUSTED_VALIDATED_FENCE();
4830	AssertMsgReturn(cbWidth <= cbGmrScanline,
4831	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4832	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4833	VERR_INVALID_PARAMETER);
4834	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4835	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4836	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4837	VERR_INVALID_PARAMETER);
4838	RT_UNTRUSTED_VALIDATED_FENCE();
4839
4840	/* How many bytes are available for the data in the GMR. */
4841	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4842
4843	/* How many scanlines would fit into the available data. */
4844	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4845	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4846	if (cbWidth <= cbGmrLastScanline)
4847	++cGmrScanlines;
4848
4849	if (cHeight > cGmrScanlines)
4850	cHeight = cGmrScanlines;
4851
4852	AssertMsgReturn(cHeight > 0,
4853	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4854	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4855	VERR_INVALID_PARAMETER);
4856	RT_UNTRUSTED_VALIDATED_FENCE();
4857
4858	/*
4859	* Host buffer.
4860	*/
4861	AssertMsgReturn(offHst < cbHstBuf,
4862	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4863	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4864	VERR_INVALID_PARAMETER);
4865
4866	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4867	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4868	AssertMsgReturn(cbHstScanline != 0,
4869	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4870	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4871	VERR_INVALID_PARAMETER);
4872	AssertMsgReturn(cbWidth <= cbHstScanline,
4873	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4874	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4875	VERR_INVALID_PARAMETER);
4876	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4877	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4878	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4879	VERR_INVALID_PARAMETER);
4880
4881	/* How many bytes are available for the data in the buffer. */
4882	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4883
4884	/* How many scanlines would fit into the available data. */
4885	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4886	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4887	if (cbWidth <= cbHstLastScanline)
4888	++cHstScanlines;
4889
4890	if (cHeight > cHstScanlines)
4891	cHeight = cHstScanlines;
4892
4893	AssertMsgReturn(cHeight > 0,
4894	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4895	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4896	VERR_INVALID_PARAMETER);
4897
4898	uint8_t *pbHst = pbHstBuf + offHst;
4899
4900	/* Shortcut for the framebuffer. */
4901	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4902	{
4903	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4904
4905	uint8_t const *pbSrc;
4906	int32_t cbSrcPitch;
4907	uint8_t *pbDst;
4908	int32_t cbDstPitch;
4909
4910	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4911	{
4912	pbSrc = pbHst;
4913	cbSrcPitch = cbHstPitch;
4914	pbDst = pbGst;
4915	cbDstPitch = cbGstPitch;
4916	}
4917	else
4918	{
4919	pbSrc = pbGst;
4920	cbSrcPitch = cbGstPitch;
4921	pbDst = pbHst;
4922	cbDstPitch = cbHstPitch;
4923	}
4924
4925	if ( cbWidth == (uint32_t)cbGstPitch
4926	&& cbGstPitch == cbHstPitch)
4927	{
4928	/* Entire scanlines, positive pitch. */
4929	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4930	}
4931	else
4932	{
4933	for (uint32_t i = 0; i < cHeight; ++i)
4934	{
4935	memcpy(pbDst, pbSrc, cbWidth);
4936
4937	pbDst += cbDstPitch;
4938	pbSrc += cbSrcPitch;
4939	}
4940	}
4941	return VINF_SUCCESS;
4942	}
4943
4944	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4945	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4946
4947	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4948	uint32_t iDesc = 0; /* Index in the descriptor array. */
4949	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4950	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4951	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4952	for (uint32_t i = 0; i < cHeight; ++i)
4953	{
4954	uint32_t cbCurrentWidth = cbWidth;
4955	uint32_t offGmrCurrent = offGmrScanline;
4956	uint8_t *pbCurrentHost = pbHstScanline;
4957
4958	/* Find the right descriptor */
4959	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4960	{
4961	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4962	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4963	++iDesc;
4964	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4965	}
4966
4967	while (cbCurrentWidth)
4968	{
4969	uint32_t cbToCopy;
4970
4971	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4972	{
4973	cbToCopy = cbCurrentWidth;
4974	}
4975	else
4976	{
4977	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4978	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4979	}
4980
4981	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4982
4983	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4984
4985	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4986	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4987	else
4988	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4989	AssertRCBreak(rc);
4990
4991	cbCurrentWidth -= cbToCopy;
4992	offGmrCurrent += cbToCopy;
4993	pbCurrentHost += cbToCopy;
4994
4995	/* Go to the next descriptor if there's anything left. */
4996	if (cbCurrentWidth)
4997	{
4998	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4999	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5000	++iDesc;
5001	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5002	}
5003	}
5004
5005	offGmrScanline += cbGstPitch;
5006	pbHstScanline += cbHstPitch;
5007	}
5008
5009	return VINF_SUCCESS;
5010	}
5011
5012
5013	/**
5014	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5015	*
5016	* @param pSizeSrc Source surface dimensions.
5017	* @param pSizeDest Destination surface dimensions.
5018	* @param pBox Coordinates to be clipped.
5019	*/
5020	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5021	const SVGA3dSize *pSizeDest,
5022	SVGA3dCopyBox *pBox)
5023	{
5024	/* Src x, w */
5025	if (pBox->srcx > pSizeSrc->width)
5026	pBox->srcx = pSizeSrc->width;
5027	if (pBox->w > pSizeSrc->width - pBox->srcx)
5028	pBox->w = pSizeSrc->width - pBox->srcx;
5029
5030	/* Src y, h */
5031	if (pBox->srcy > pSizeSrc->height)
5032	pBox->srcy = pSizeSrc->height;
5033	if (pBox->h > pSizeSrc->height - pBox->srcy)
5034	pBox->h = pSizeSrc->height - pBox->srcy;
5035
5036	/* Src z, d */
5037	if (pBox->srcz > pSizeSrc->depth)
5038	pBox->srcz = pSizeSrc->depth;
5039	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5040	pBox->d = pSizeSrc->depth - pBox->srcz;
5041
5042	/* Dest x, w */
5043	if (pBox->x > pSizeDest->width)
5044	pBox->x = pSizeDest->width;
5045	if (pBox->w > pSizeDest->width - pBox->x)
5046	pBox->w = pSizeDest->width - pBox->x;
5047
5048	/* Dest y, h */
5049	if (pBox->y > pSizeDest->height)
5050	pBox->y = pSizeDest->height;
5051	if (pBox->h > pSizeDest->height - pBox->y)
5052	pBox->h = pSizeDest->height - pBox->y;
5053
5054	/* Dest z, d */
5055	if (pBox->z > pSizeDest->depth)
5056	pBox->z = pSizeDest->depth;
5057	if (pBox->d > pSizeDest->depth - pBox->z)
5058	pBox->d = pSizeDest->depth - pBox->z;
5059	}
5060
5061	/**
5062	* Unsigned coordinates in pBox. Clip to [0; pSize).
5063	*
5064	* @param pSize Source surface dimensions.
5065	* @param pBox Coordinates to be clipped.
5066	*/
5067	void vmsvgaClipBox(const SVGA3dSize *pSize,
5068	SVGA3dBox *pBox)
5069	{
5070	/* x, w */
5071	if (pBox->x > pSize->width)
5072	pBox->x = pSize->width;
5073	if (pBox->w > pSize->width - pBox->x)
5074	pBox->w = pSize->width - pBox->x;
5075
5076	/* y, h */
5077	if (pBox->y > pSize->height)
5078	pBox->y = pSize->height;
5079	if (pBox->h > pSize->height - pBox->y)
5080	pBox->h = pSize->height - pBox->y;
5081
5082	/* z, d */
5083	if (pBox->z > pSize->depth)
5084	pBox->z = pSize->depth;
5085	if (pBox->d > pSize->depth - pBox->z)
5086	pBox->d = pSize->depth - pBox->z;
5087	}
5088
5089	/**
5090	* Clip.
5091	*
5092	* @param pBound Bounding rectangle.
5093	* @param pRect Rectangle to be clipped.
5094	*/
5095	void vmsvgaClipRect(SVGASignedRect const *pBound,
5096	SVGASignedRect *pRect)
5097	{
5098	int32_t left;
5099	int32_t top;
5100	int32_t right;
5101	int32_t bottom;
5102
5103	/* Right order. */
5104	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5105	if (pRect->left < pRect->right)
5106	{
5107	left = pRect->left;
5108	right = pRect->right;
5109	}
5110	else
5111	{
5112	left = pRect->right;
5113	right = pRect->left;
5114	}
5115	if (pRect->top < pRect->bottom)
5116	{
5117	top = pRect->top;
5118	bottom = pRect->bottom;
5119	}
5120	else
5121	{
5122	top = pRect->bottom;
5123	bottom = pRect->top;
5124	}
5125
5126	if (left < pBound->left)
5127	left = pBound->left;
5128	if (right < pBound->left)
5129	right = pBound->left;
5130
5131	if (left > pBound->right)
5132	left = pBound->right;
5133	if (right > pBound->right)
5134	right = pBound->right;
5135
5136	if (top < pBound->top)
5137	top = pBound->top;
5138	if (bottom < pBound->top)
5139	bottom = pBound->top;
5140
5141	if (top > pBound->bottom)
5142	top = pBound->bottom;
5143	if (bottom > pBound->bottom)
5144	bottom = pBound->bottom;
5145
5146	pRect->left = left;
5147	pRect->right = right;
5148	pRect->top = top;
5149	pRect->bottom = bottom;
5150	}
5151
5152	/**
5153	* Unblock the FIFO I/O thread so it can respond to a state change.
5154	*
5155	* @returns VBox status code.
5156	* @param pDevIns The VGA device instance.
5157	* @param pThread The send thread.
5158	*/
5159	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5160	{
5161	RT_NOREF(pDevIns);
5162	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5163	Log(("vmsvgaFIFOLoopWakeUp\n"));
5164	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5165	}
5166
5167	/**
5168	* Enables or disables dirty page tracking for the framebuffer
5169	*
5170	* @param pThis VGA device instance data.
5171	* @param fTraces Enable/disable traces
5172	*/
5173	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5174	{
5175	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5176	&& !fTraces)
5177	{
5178	//Assert(pThis->svga.fTraces);
5179	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5180	return;
5181	}
5182
5183	pThis->svga.fTraces = fTraces;
5184	if (pThis->svga.fTraces)
5185	{
5186	unsigned cbFrameBuffer = pThis->vram_size;
5187
5188	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5189	/** @todo How does this work with screens? */
5190	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5191	{
5192	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5193	Assert(pThis->svga.cbScanline);
5194	#endif
5195	/* Hardware enabled; return real framebuffer size .*/
5196	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5197	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5198	}
5199
5200	if (!pThis->svga.fVRAMTracking)
5201	{
5202	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5203	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5204	pThis->svga.fVRAMTracking = true;
5205	}
5206	}
5207	else
5208	{
5209	if (pThis->svga.fVRAMTracking)
5210	{
5211	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5212	vgaR3UnregisterVRAMHandler(pThis);
5213	pThis->svga.fVRAMTracking = false;
5214	}
5215	}
5216	}
5217
5218	/**
5219	* @callback_method_impl{FNPCIIOREGIONMAP}
5220	*/
5221	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5222	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5223	{
5224	int rc;
5225	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5226
5227	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5228	if (enmType == PCI_ADDRESS_SPACE_IO)
5229	{
5230	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5231	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5232	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5233	if (RT_FAILURE(rc))
5234	return rc;
5235	if (pThis->fR0Enabled)
5236	{
5237	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5238	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5239	if (RT_FAILURE(rc))
5240	return rc;
5241	}
5242	if (pThis->fGCEnabled)
5243	{
5244	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5245	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5246	if (RT_FAILURE(rc))
5247	return rc;
5248	}
5249
5250	pThis->svga.BasePort = GCPhysAddress;
5251	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5252	}
5253	else
5254	{
5255	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5256	if (GCPhysAddress != NIL_RTGCPHYS)
5257	{
5258	/*
5259	* Mapping the FIFO RAM.
5260	*/
5261	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5262	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5263	AssertRC(rc);
5264
5265	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5266	if (RT_SUCCESS(rc))
5267	{
5268	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5269	# ifdef DEBUG_FIFO_ACCESS
5270	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5271	# else
5272	GCPhysAddress + PAGE_SIZE - 1,
5273	# endif
5274	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5275	"VMSVGA FIFO");
5276	AssertRC(rc);
5277	}
5278	# endif
5279	if (RT_SUCCESS(rc))
5280	{
5281	pThis->svga.GCPhysFIFO = GCPhysAddress;
5282	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5283	}
5284	}
5285	else
5286	{
5287	Assert(pThis->svga.GCPhysFIFO);
5288	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5289	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5290	AssertRC(rc);
5291	# endif
5292	pThis->svga.GCPhysFIFO = 0;
5293	}
5294	}
5295	return VINF_SUCCESS;
5296	}
5297
5298	# ifdef VBOX_WITH_VMSVGA3D
5299
5300	/**
5301	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5302	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5303	*
5304	* @param pThis The VGA device instance data.
5305	* @param sid Either UINT32_MAX or the ID of a specific
5306	* surface. If UINT32_MAX is used, all surfaces
5307	* are processed.
5308	*/
5309	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5310	{
5311	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5312	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5313	}
5314
5315
5316	/**
5317	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5318	*/
5319	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5320	{
5321	/* There might be a specific surface ID at the start of the
5322	arguments, if not show all surfaces. */
5323	uint32_t sid = UINT32_MAX;
5324	if (pszArgs)
5325	pszArgs = RTStrStripL(pszArgs);
5326	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5327	sid = RTStrToUInt32(pszArgs);
5328
5329	/* Verbose or terse display, we default to verbose. */
5330	bool fVerbose = true;
5331	if (RTStrIStr(pszArgs, "terse"))
5332	fVerbose = false;
5333
5334	/* The size of the ascii art (x direction, y is 3/4 of x). */
5335	uint32_t cxAscii = 80;
5336	if (RTStrIStr(pszArgs, "gigantic"))
5337	cxAscii = 300;
5338	else if (RTStrIStr(pszArgs, "huge"))
5339	cxAscii = 180;
5340	else if (RTStrIStr(pszArgs, "big"))
5341	cxAscii = 132;
5342	else if (RTStrIStr(pszArgs, "normal"))
5343	cxAscii = 80;
5344	else if (RTStrIStr(pszArgs, "medium"))
5345	cxAscii = 64;
5346	else if (RTStrIStr(pszArgs, "small"))
5347	cxAscii = 48;
5348	else if (RTStrIStr(pszArgs, "tiny"))
5349	cxAscii = 24;
5350
5351	/* Y invert the image when producing the ASCII art. */
5352	bool fInvY = false;
5353	if (RTStrIStr(pszArgs, "invy"))
5354	fInvY = true;
5355
5356	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5357	}
5358
5359
5360	/**
5361	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5362	*/
5363	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5364	{
5365	/* pszArg = "sid[>dir]"
5366	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5367	*/
5368	char *pszBitmapPath = NULL;
5369	uint32_t sid = UINT32_MAX;
5370	if (pszArgs)
5371	pszArgs = RTStrStripL(pszArgs);
5372	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5373	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5374	if ( pszBitmapPath
5375	&& *pszBitmapPath == '>')
5376	++pszBitmapPath;
5377
5378	const bool fVerbose = true;
5379	const uint32_t cxAscii = 0; /* No ASCII */
5380	const bool fInvY = false; /* Do not invert. */
5381	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5382	}
5383
5384
5385	/**
5386	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5387	*/
5388	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5389	{
5390	/* There might be a specific surface ID at the start of the
5391	arguments, if not show all contexts. */
5392	uint32_t sid = UINT32_MAX;
5393	if (pszArgs)
5394	pszArgs = RTStrStripL(pszArgs);
5395	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5396	sid = RTStrToUInt32(pszArgs);
5397
5398	/* Verbose or terse display, we default to verbose. */
5399	bool fVerbose = true;
5400	if (RTStrIStr(pszArgs, "terse"))
5401	fVerbose = false;
5402
5403	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5404	}
5405
5406	# endif /* VBOX_WITH_VMSVGA3D */
5407
5408	/**
5409	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5410	*/
5411	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5412	{
5413	RT_NOREF(pszArgs);
5414	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5415	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5416
5417	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5418	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5419	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5420	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5421	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5422	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5423	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5424	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5425	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5426	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5427	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5428	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5429	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5430	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5431	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5432	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5433	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5434	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5435	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5436	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5437	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5438	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5439
5440	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5441	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5442	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5443	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5444
5445	# ifdef VBOX_WITH_VMSVGA3D
5446	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5447	# endif
5448	}
5449
5450	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5451	*/
5452	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5453	{
5454	RT_NOREF(uPass);
5455
5456	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5457	int rc;
5458
5459	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5460	{
5461	uint32_t cScreens = 0;
5462	rc = SSMR3GetU32(pSSM, &cScreens);
5463	AssertRCReturn(rc, rc);
5464	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5465	("cScreens=%#x\n", cScreens),
5466	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5467
5468	for (uint32_t i = 0; i < cScreens; ++i)
5469	{
5470	VMSVGASCREENOBJECT screen;
5471	RT_ZERO(screen);
5472
5473	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5474	AssertLogRelRCReturn(rc, rc);
5475
5476	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5477	{
5478	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5479	*pScreen = screen;
5480	pScreen->fModified = true;
5481	}
5482	else
5483	{
5484	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5485	}
5486	}
5487	}
5488	else
5489	{
5490	/* Try to setup at least the first screen. */
5491	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5492	pScreen->fDefined = true;
5493	pScreen->fModified = true;
5494	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5495	pScreen->idScreen = 0;
5496	pScreen->xOrigin = 0;
5497	pScreen->yOrigin = 0;
5498	pScreen->offVRAM = pThis->svga.uScreenOffset;
5499	pScreen->cbPitch = pThis->svga.cbScanline;
5500	pScreen->cWidth = pThis->svga.uWidth;
5501	pScreen->cHeight = pThis->svga.uHeight;
5502	pScreen->cBpp = pThis->svga.uBpp;
5503	}
5504
5505	return VINF_SUCCESS;
5506	}
5507
5508	/**
5509	* @copydoc FNSSMDEVLOADEXEC
5510	*/
5511	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5512	{
5513	RT_NOREF(uPass);
5514	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5515	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5516	int rc;
5517
5518	/* Load our part of the VGAState */
5519	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5520	AssertRCReturn(rc, rc);
5521
5522	/* Load the VGA framebuffer. */
5523	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5524	uint32_t cbVgaFramebuffer = _32K;
5525	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5526	{
5527	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5528	AssertRCReturn(rc, rc);
5529	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5530	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5531	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5532	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5533	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5534	}
5535	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5536	AssertRCReturn(rc, rc);
5537	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5538	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5539	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5540	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5541
5542	/* Load the VMSVGA state. */
5543	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5544	AssertRCReturn(rc, rc);
5545
5546	/* Load the active cursor bitmaps. */
5547	if (pSVGAState->Cursor.fActive)
5548	{
5549	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5550	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5551
5552	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5553	AssertRCReturn(rc, rc);
5554	}
5555
5556	/* Load the GMR state. */
5557	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5558	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5559	{
5560	rc = SSMR3GetU32(pSSM, &cGMR);
5561	AssertRCReturn(rc, rc);
5562	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5563	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5564	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5565	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5566	}
5567
5568	if (pThis->svga.cGMR != cGMR)
5569	{
5570	/* Reallocate GMR array. */
5571	Assert(pSVGAState->paGMR != NULL);
5572	RTMemFree(pSVGAState->paGMR);
5573	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5574	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5575	pThis->svga.cGMR = cGMR;
5576	}
5577
5578	for (uint32_t i = 0; i < cGMR; ++i)
5579	{
5580	PGMR pGMR = &pSVGAState->paGMR[i];
5581
5582	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5583	AssertRCReturn(rc, rc);
5584
5585	if (pGMR->numDescriptors)
5586	{
5587	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5588	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5589	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5590
5591	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5592	{
5593	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5594	AssertRCReturn(rc, rc);
5595	}
5596	}
5597	}
5598
5599	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5600	vmsvga3dPowerOn(pThis);
5601	# endif
5602
5603	VMSVGA_STATE_LOAD LoadState;
5604	LoadState.pSSM = pSSM;
5605	LoadState.uVersion = uVersion;
5606	LoadState.uPass = uPass;
5607	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5608	AssertLogRelRCReturn(rc, rc);
5609
5610	return VINF_SUCCESS;
5611	}
5612
5613	/**
5614	* Reinit the video mode after the state has been loaded.
5615	*/
5616	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5617	{
5618	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5619	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5620
5621	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5622
5623	/* Set the active cursor. */
5624	if (pSVGAState->Cursor.fActive)
5625	{
5626	int rc;
5627
5628	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5629	true,
5630	true,
5631	pSVGAState->Cursor.xHotspot,
5632	pSVGAState->Cursor.yHotspot,
5633	pSVGAState->Cursor.width,
5634	pSVGAState->Cursor.height,
5635	pSVGAState->Cursor.pData);
5636	AssertRC(rc);
5637	}
5638	return VINF_SUCCESS;
5639	}
5640
5641	/**
5642	* Portion of SVGA state which must be saved in the FIFO thread.
5643	*/
5644	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5645	{
5646	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5647	int rc;
5648
5649	/* Save the screen objects. */
5650	/* Count defined screen object. */
5651	uint32_t cScreens = 0;
5652	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5653	{
5654	if (pSVGAState->aScreens[i].fDefined)
5655	++cScreens;
5656	}
5657
5658	rc = SSMR3PutU32(pSSM, cScreens);
5659	AssertLogRelRCReturn(rc, rc);
5660
5661	for (uint32_t i = 0; i < cScreens; ++i)
5662	{
5663	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5664
5665	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5666	AssertLogRelRCReturn(rc, rc);
5667	}
5668	return VINF_SUCCESS;
5669	}
5670
5671	/**
5672	* @copydoc FNSSMDEVSAVEEXEC
5673	*/
5674	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5675	{
5676	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5677	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5678	int rc;
5679
5680	/* Save our part of the VGAState */
5681	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5682	AssertLogRelRCReturn(rc, rc);
5683
5684	/* Save the framebuffer backup. */
5685	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5686	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5687	AssertLogRelRCReturn(rc, rc);
5688
5689	/* Save the VMSVGA state. */
5690	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5691	AssertLogRelRCReturn(rc, rc);
5692
5693	/* Save the active cursor bitmaps. */
5694	if (pSVGAState->Cursor.fActive)
5695	{
5696	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5697	AssertLogRelRCReturn(rc, rc);
5698	}
5699
5700	/* Save the GMR state */
5701	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5702	AssertLogRelRCReturn(rc, rc);
5703	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5704	{
5705	PGMR pGMR = &pSVGAState->paGMR[i];
5706
5707	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5708	AssertLogRelRCReturn(rc, rc);
5709
5710	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5711	{
5712	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5713	AssertLogRelRCReturn(rc, rc);
5714	}
5715	}
5716
5717	/*
5718	* Must save some state (3D in particular) in the FIFO thread.
5719	*/
5720	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5721	AssertLogRelRCReturn(rc, rc);
5722
5723	return VINF_SUCCESS;
5724	}
5725
5726	/**
5727	* Destructor for PVMSVGAR3STATE structure.
5728	*
5729	* @param pThis The VGA instance.
5730	* @param pSVGAState Pointer to the structure. It is not deallocated.
5731	*/
5732	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5733	{
5734	#ifndef VMSVGA_USE_EMT_HALT_CODE
5735	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5736	{
5737	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5738	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5739	}
5740	#endif
5741
5742	if (pSVGAState->Cursor.fActive)
5743	{
5744	RTMemFree(pSVGAState->Cursor.pData);
5745	pSVGAState->Cursor.pData = NULL;
5746	pSVGAState->Cursor.fActive = false;
5747	}
5748
5749	if (pSVGAState->paGMR)
5750	{
5751	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5752	if (pSVGAState->paGMR[i].paDesc)
5753	RTMemFree(pSVGAState->paGMR[i].paDesc);
5754
5755	RTMemFree(pSVGAState->paGMR);
5756	pSVGAState->paGMR = NULL;
5757	}
5758	}
5759
5760	/**
5761	* Constructor for PVMSVGAR3STATE structure.
5762	*
5763	* @returns VBox status code.
5764	* @param pThis The VGA instance.
5765	* @param pSVGAState Pointer to the structure. It is already allocated.
5766	*/
5767	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5768	{
5769	int rc = VINF_SUCCESS;
5770	RT_ZERO(*pSVGAState);
5771
5772	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5773	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5774
5775	#ifndef VMSVGA_USE_EMT_HALT_CODE
5776	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5777	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5778	AssertRCReturn(rc, rc);
5779	#endif
5780
5781	return rc;
5782	}
5783
5784	/**
5785	* Resets the SVGA hardware state
5786	*
5787	* @returns VBox status code.
5788	* @param pDevIns The device instance.
5789	*/
5790	int vmsvgaReset(PPDMDEVINS pDevIns)
5791	{
5792	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5793	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5794
5795	/* Reset before init? */
5796	if (!pSVGAState)
5797	return VINF_SUCCESS;
5798
5799	Log(("vmsvgaReset\n"));
5800
5801	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5802	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5803	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5804
5805	/* Reset other stuff. */
5806	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5807	RT_ZERO(pThis->svga.au32ScratchRegion);
5808
5809	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5810	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5811
5812	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5813
5814	/* Register caps. */
5815	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5816	# ifdef VBOX_WITH_VMSVGA3D
5817	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5818	# endif
5819
5820	/* Setup FIFO capabilities. */
5821	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5822
5823	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5824	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5825
5826	/* VRAM tracking is enabled by default during bootup. */
5827	pThis->svga.fVRAMTracking = true;
5828	pThis->svga.fEnabled = false;
5829
5830	/* Invalidate current settings. */
5831	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5832	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5833	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5834	pThis->svga.cbScanline = 0;
5835
5836	return rc;
5837	}
5838
5839	/**
5840	* Cleans up the SVGA hardware state
5841	*
5842	* @returns VBox status code.
5843	* @param pDevIns The device instance.
5844	*/
5845	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5846	{
5847	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5848
5849	/*
5850	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5851	*/
5852	if (pThis->svga.pFIFOIOThread)
5853	{
5854	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5855	AssertLogRelRC(rc);
5856
5857	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5858	AssertLogRelRC(rc);
5859	pThis->svga.pFIFOIOThread = NULL;
5860	}
5861
5862	/*
5863	* Destroy the special SVGA state.
5864	*/
5865	if (pThis->svga.pSvgaR3State)
5866	{
5867	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5868
5869	RTMemFree(pThis->svga.pSvgaR3State);
5870	pThis->svga.pSvgaR3State = NULL;
5871	}
5872
5873	/*
5874	* Free our resources residing in the VGA state.
5875	*/
5876	if (pThis->svga.pbVgaFrameBufferR3)
5877	{
5878	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5879	pThis->svga.pbVgaFrameBufferR3 = NULL;
5880	}
5881	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5882	{
5883	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5884	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5885	}
5886	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5887	{
5888	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5889	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5890	}
5891
5892	return VINF_SUCCESS;
5893	}
5894
5895	/**
5896	* Initialize the SVGA hardware state
5897	*
5898	* @returns VBox status code.
5899	* @param pDevIns The device instance.
5900	*/
5901	int vmsvgaInit(PPDMDEVINS pDevIns)
5902	{
5903	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5904	PVMSVGAR3STATE pSVGAState;
5905	PVM pVM = PDMDevHlpGetVM(pDevIns);
5906	int rc;
5907
5908	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5909	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5910
5911	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5912
5913	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5914	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5915	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5916
5917	/* Create event semaphore. */
5918	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5919
5920	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5921	if (RT_FAILURE(rc))
5922	{
5923	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5924	return rc;
5925	}
5926
5927	/* Create event semaphore. */
5928	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5929	if (RT_FAILURE(rc))
5930	{
5931	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5932	return rc;
5933	}
5934
5935	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5936	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5937
5938	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5939	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5940
5941	pSVGAState = pThis->svga.pSvgaR3State;
5942
5943	/* Register caps. */
5944	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5945	# ifdef VBOX_WITH_VMSVGA3D
5946	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5947	# endif
5948
5949	/* Setup FIFO capabilities. */
5950	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5951
5952	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5953	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5954
5955	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5956	# ifdef VBOX_WITH_VMSVGA3D
5957	if (pThis->svga.f3DEnabled)
5958	{
5959	rc = vmsvga3dInit(pThis);
5960	if (RT_FAILURE(rc))
5961	{
5962	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5963	pThis->svga.f3DEnabled = false;
5964	}
5965	}
5966	# endif
5967	/* VRAM tracking is enabled by default during bootup. */
5968	pThis->svga.fVRAMTracking = true;
5969
5970	/* Invalidate current settings. */
5971	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5972	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5973	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5974	pThis->svga.cbScanline = 0;
5975
5976	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5977	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5978	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5979	{
5980	pThis->svga.u32MaxWidth -= 256;
5981	pThis->svga.u32MaxHeight -= 256;
5982	}
5983	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5984
5985	# ifdef DEBUG_GMR_ACCESS
5986	/* Register the GMR access handler type. */
5987	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5988	vmsvgaR3GMRAccessHandler,
5989	NULL, NULL, NULL,
5990	NULL, NULL, NULL,
5991	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
5992	AssertRCReturn(rc, rc);
5993	# endif
5994
5995	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5996	/* Register the FIFO access handler type. In addition to
5997	debugging FIFO access, this is also used to facilitate
5998	extended fifo thread sleeps. */
5999	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6000	# ifdef DEBUG_FIFO_ACCESS
6001	PGMPHYSHANDLERKIND_ALL,
6002	# else
6003	PGMPHYSHANDLERKIND_WRITE,
6004	# endif
6005	vmsvgaR3FIFOAccessHandler,
6006	NULL, NULL, NULL,
6007	NULL, NULL, NULL,
6008	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6009	AssertRCReturn(rc, rc);
6010	# endif
6011
6012	/* Create the async IO thread. */
6013	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6014	RTTHREADTYPE_IO, "VMSVGA FIFO");
6015	if (RT_FAILURE(rc))
6016	{
6017	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6018	return rc;
6019	}
6020
6021	/*
6022	* Statistics.
6023	*/
6024	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6025	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6026	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6027	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6028	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6029	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6030	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6031	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6032	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6033	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6034	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6035	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6036	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6037	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6038	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6039	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6040	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6041	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6042	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6043	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6044	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6045	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6046	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6047	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6048	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6049	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6050	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6051	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6052	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6053	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6054	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6055	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6056	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6057	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6058	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6059	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6060	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6061	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6062	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6063	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6064	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6065	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6066	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6067	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6068	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6069	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6070	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6071	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6072	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6073	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6074	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6075	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6076	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6077	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6078	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6079	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6080
6081	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6082	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6083	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6084	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6085	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6086	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6087	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6088	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6089	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6090	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6091	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6092	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6093	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6094	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6095	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6096	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6097	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6098	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6099	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6100	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6101	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6102	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6103	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6104	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6105	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6106	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6107	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6108	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6109	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6110	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6111	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6112	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6113
6114	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6115	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6116	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6117	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6118	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6119	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6120	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6121	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6122	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6123	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6124	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6125	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6126	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6127	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6128	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6129	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6130	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6131	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6132	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6133	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6134	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6135	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6136	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6137	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6138	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6139	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6140	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6141	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6142	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6143	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6144	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6145	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6146	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6147	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6148	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6149	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6150	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6151	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6152	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6153	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6154	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6155	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6156	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6157	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6158	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6159	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6160	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6161	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6162	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6163
6164	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6165	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6166	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6167	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6168	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6169	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6170	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6171	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6172	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6173	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6174	# endif
6175	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6176	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6177	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6178	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6179	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6180
6181	/*
6182	* Info handlers.
6183	*/
6184	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6185	# ifdef VBOX_WITH_VMSVGA3D
6186	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6187	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6188	"VMSVGA 3d surface details. "
6189	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6190	vmsvgaR3Info3dSurface);
6191	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6192	"VMSVGA 3d surface details and bitmap: "
6193	"sid[>dir]",
6194	vmsvgaR3Info3dSurfaceBmp);
6195	# endif
6196
6197	return VINF_SUCCESS;
6198	}
6199
6200	# ifdef VBOX_WITH_VMSVGA3D
6201	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6202	static const char * const g_apszVmSvgaDevCapNames[] =
6203	{
6204	"x3D", /* = 0 */
6205	"xMAX_LIGHTS",
6206	"xMAX_TEXTURES",
6207	"xMAX_CLIP_PLANES",
6208	"xVERTEX_SHADER_VERSION",
6209	"xVERTEX_SHADER",
6210	"xFRAGMENT_SHADER_VERSION",
6211	"xFRAGMENT_SHADER",
6212	"xMAX_RENDER_TARGETS",
6213	"xS23E8_TEXTURES",
6214	"xS10E5_TEXTURES",
6215	"xMAX_FIXED_VERTEXBLEND",
6216	"xD16_BUFFER_FORMAT",
6217	"xD24S8_BUFFER_FORMAT",
6218	"xD24X8_BUFFER_FORMAT",
6219	"xQUERY_TYPES",
6220	"xTEXTURE_GRADIENT_SAMPLING",
6221	"rMAX_POINT_SIZE",
6222	"xMAX_SHADER_TEXTURES",
6223	"xMAX_TEXTURE_WIDTH",
6224	"xMAX_TEXTURE_HEIGHT",
6225	"xMAX_VOLUME_EXTENT",
6226	"xMAX_TEXTURE_REPEAT",
6227	"xMAX_TEXTURE_ASPECT_RATIO",
6228	"xMAX_TEXTURE_ANISOTROPY",
6229	"xMAX_PRIMITIVE_COUNT",
6230	"xMAX_VERTEX_INDEX",
6231	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6232	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6233	"xMAX_VERTEX_SHADER_TEMPS",
6234	"xMAX_FRAGMENT_SHADER_TEMPS",
6235	"xTEXTURE_OPS",
6236	"xSURFACEFMT_X8R8G8B8",
6237	"xSURFACEFMT_A8R8G8B8",
6238	"xSURFACEFMT_A2R10G10B10",
6239	"xSURFACEFMT_X1R5G5B5",
6240	"xSURFACEFMT_A1R5G5B5",
6241	"xSURFACEFMT_A4R4G4B4",
6242	"xSURFACEFMT_R5G6B5",
6243	"xSURFACEFMT_LUMINANCE16",
6244	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6245	"xSURFACEFMT_ALPHA8",
6246	"xSURFACEFMT_LUMINANCE8",
6247	"xSURFACEFMT_Z_D16",
6248	"xSURFACEFMT_Z_D24S8",
6249	"xSURFACEFMT_Z_D24X8",
6250	"xSURFACEFMT_DXT1",
6251	"xSURFACEFMT_DXT2",
6252	"xSURFACEFMT_DXT3",
6253	"xSURFACEFMT_DXT4",
6254	"xSURFACEFMT_DXT5",
6255	"xSURFACEFMT_BUMPX8L8V8U8",
6256	"xSURFACEFMT_A2W10V10U10",
6257	"xSURFACEFMT_BUMPU8V8",
6258	"xSURFACEFMT_Q8W8V8U8",
6259	"xSURFACEFMT_CxV8U8",
6260	"xSURFACEFMT_R_S10E5",
6261	"xSURFACEFMT_R_S23E8",
6262	"xSURFACEFMT_RG_S10E5",
6263	"xSURFACEFMT_RG_S23E8",
6264	"xSURFACEFMT_ARGB_S10E5",
6265	"xSURFACEFMT_ARGB_S23E8",
6266	"xMISSING62",
6267	"xMAX_VERTEX_SHADER_TEXTURES",
6268	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6269	"xSURFACEFMT_V16U16",
6270	"xSURFACEFMT_G16R16",
6271	"xSURFACEFMT_A16B16G16R16",
6272	"xSURFACEFMT_UYVY",
6273	"xSURFACEFMT_YUY2",
6274	"xMULTISAMPLE_NONMASKABLESAMPLES",
6275	"xMULTISAMPLE_MASKABLESAMPLES",
6276	"xALPHATOCOVERAGE",
6277	"xSUPERSAMPLE",
6278	"xAUTOGENMIPMAPS",
6279	"xSURFACEFMT_NV12",
6280	"xSURFACEFMT_AYUV",
6281	"xMAX_CONTEXT_IDS",
6282	"xMAX_SURFACE_IDS",
6283	"xSURFACEFMT_Z_DF16",
6284	"xSURFACEFMT_Z_DF24",
6285	"xSURFACEFMT_Z_D24S8_INT",
6286	"xSURFACEFMT_BC4_UNORM",
6287	"xSURFACEFMT_BC5_UNORM", /* 83 */
6288	};
6289	# endif
6290
6291
6292	/**
6293	* Power On notification.
6294	*
6295	* @returns VBox status code.
6296	* @param pDevIns The device instance data.
6297	*
6298	* @remarks Caller enters the device critical section.
6299	*/
6300	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6301	{
6302	# ifdef VBOX_WITH_VMSVGA3D
6303	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6304	if (pThis->svga.f3DEnabled)
6305	{
6306	int rc = vmsvga3dPowerOn(pThis);
6307
6308	if (RT_SUCCESS(rc))
6309	{
6310	bool fSavedBuffering = RTLogRelSetBuffering(true);
6311	SVGA3dCapsRecord *pCaps;
6312	SVGA3dCapPair *pData;
6313	uint32_t idxCap = 0;
6314
6315	/* 3d hardware version; latest and greatest */
6316	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6317	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6318
6319	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6320	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6321	pData = (SVGA3dCapPair *)&pCaps->data;
6322
6323	/* Fill out all 3d capabilities. */
6324	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6325	{
6326	uint32_t val = 0;
6327
6328	rc = vmsvga3dQueryCaps(pThis, i, &val);
6329	if (RT_SUCCESS(rc))
6330	{
6331	pData[idxCap][0] = i;
6332	pData[idxCap][1] = val;
6333	idxCap++;
6334	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6335	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6336	else
6337	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6338	&g_apszVmSvgaDevCapNames[i][1]));
6339	}
6340	else
6341	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6342	}
6343	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6344	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6345
6346	/* Mark end of record array. */
6347	pCaps->header.length = 0;
6348
6349	RTLogRelSetBuffering(fSavedBuffering);
6350	}
6351	}
6352	# else /* !VBOX_WITH_VMSVGA3D */
6353	RT_NOREF(pDevIns);
6354	# endif /* !VBOX_WITH_VMSVGA3D */
6355	}
6356
6357	#endif /* IN_RING3 */
6358

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 77611

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