DevVGA-SVGA.cpp@ 77914

Last change on this file since 77914 was 77869, checked in by vboxsync, 6 years ago
DevVGA-SVGA: report the mouse cursor position only if the guest actually updated it
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1	/* $Id: DevVGA-SVGA.cpp 77869 2019-03-25 11:15:32Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
249	STAMPROFILE StatBusyDelayEmts;
250
251	STAMPROFILE StatR3Cmd3dPresentProf;
252	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
253	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
254	STAMCOUNTER StatR3CmdDefineGmr2;
255	STAMCOUNTER StatR3CmdDefineGmr2Free;
256	STAMCOUNTER StatR3CmdDefineGmr2Modify;
257	STAMCOUNTER StatR3CmdRemapGmr2;
258	STAMCOUNTER StatR3CmdRemapGmr2Modify;
259	STAMCOUNTER StatR3CmdInvalidCmd;
260	STAMCOUNTER StatR3CmdFence;
261	STAMCOUNTER StatR3CmdUpdate;
262	STAMCOUNTER StatR3CmdUpdateVerbose;
263	STAMCOUNTER StatR3CmdDefineCursor;
264	STAMCOUNTER StatR3CmdDefineAlphaCursor;
265	STAMCOUNTER StatR3CmdEscape;
266	STAMCOUNTER StatR3CmdDefineScreen;
267	STAMCOUNTER StatR3CmdDestroyScreen;
268	STAMCOUNTER StatR3CmdDefineGmrFb;
269	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
270	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
271	STAMCOUNTER StatR3CmdAnnotationFill;
272	STAMCOUNTER StatR3CmdAnnotationCopy;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
275	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
276	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
277	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
278	STAMCOUNTER StatR3Cmd3dSurfaceDma;
279	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
280	STAMCOUNTER StatR3Cmd3dContextDefine;
281	STAMCOUNTER StatR3Cmd3dContextDestroy;
282	STAMCOUNTER StatR3Cmd3dSetTransform;
283	STAMCOUNTER StatR3Cmd3dSetZRange;
284	STAMCOUNTER StatR3Cmd3dSetRenderState;
285	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
286	STAMCOUNTER StatR3Cmd3dSetTextureState;
287	STAMCOUNTER StatR3Cmd3dSetMaterial;
288	STAMCOUNTER StatR3Cmd3dSetLightData;
289	STAMCOUNTER StatR3Cmd3dSetLightEnable;
290	STAMCOUNTER StatR3Cmd3dSetViewPort;
291	STAMCOUNTER StatR3Cmd3dSetClipPlane;
292	STAMCOUNTER StatR3Cmd3dClear;
293	STAMCOUNTER StatR3Cmd3dPresent;
294	STAMCOUNTER StatR3Cmd3dPresentReadBack;
295	STAMCOUNTER StatR3Cmd3dShaderDefine;
296	STAMCOUNTER StatR3Cmd3dShaderDestroy;
297	STAMCOUNTER StatR3Cmd3dSetShader;
298	STAMCOUNTER StatR3Cmd3dSetShaderConst;
299	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
300	STAMCOUNTER StatR3Cmd3dSetScissorRect;
301	STAMCOUNTER StatR3Cmd3dBeginQuery;
302	STAMCOUNTER StatR3Cmd3dEndQuery;
303	STAMCOUNTER StatR3Cmd3dWaitForQuery;
304	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
305	STAMCOUNTER StatR3Cmd3dActivateSurface;
306	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
307
308	STAMCOUNTER StatR3RegConfigDoneWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
311	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
312
313	STAMCOUNTER StatFifoCommands;
314	STAMCOUNTER StatFifoErrors;
315	STAMCOUNTER StatFifoUnkCmds;
316	STAMCOUNTER StatFifoTodoTimeout;
317	STAMCOUNTER StatFifoTodoWoken;
318	STAMPROFILE StatFifoStalls;
319	STAMPROFILE StatFifoExtendedSleep;
320	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
321	STAMCOUNTER StatFifoAccessHandler;
322	# endif
323	STAMCOUNTER StatFifoCursorFetchAgain;
324	STAMCOUNTER StatFifoCursorNoChange;
325	STAMCOUNTER StatFifoCursorPosition;
326	STAMCOUNTER StatFifoCursorVisiblity;
327	STAMCOUNTER StatFifoWatchdogWakeUps;
328	} VMSVGAR3STATE, *PVMSVGAR3STATE;
329	#endif /* IN_RING3 */
330
331
332	/*********************************************************************************************************************************
333	* Internal Functions *
334	*********************************************************************************************************************************/
335	#ifdef IN_RING3
336	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
337	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
338	# endif
339	# ifdef DEBUG_GMR_ACCESS
340	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
341	# endif
342	#endif
343
344
345	/*********************************************************************************************************************************
346	* Global Variables *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349
350	/**
351	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
352	*/
353	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
354	{
355	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
356	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
357	SSMFIELD_ENTRY_TERM()
358	};
359
360	/**
361	* SSM descriptor table for the GMR structure.
362	*/
363	static SSMFIELD const g_aGMRFields[] =
364	{
365	SSMFIELD_ENTRY( GMR, cMaxPages),
366	SSMFIELD_ENTRY( GMR, cbTotal),
367	SSMFIELD_ENTRY( GMR, numDescriptors),
368	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
369	SSMFIELD_ENTRY_TERM()
370	};
371
372	/**
373	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
374	*/
375	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
376	{
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
388	SSMFIELD_ENTRY_TERM()
389	};
390
391	/**
392	* SSM descriptor table for the VMSVGAR3STATE structure.
393	*/
394	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
395	{
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
397	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
404	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
407	#ifdef VMSVGA_USE_EMT_HALT_CODE
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
409	#else
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
411	#endif
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
469
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
474
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
482	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
484	# endif
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
489
490	SSMFIELD_ENTRY_TERM()
491	};
492
493	/**
494	* SSM descriptor table for the VGAState.svga structure.
495	*/
496	static SSMFIELD const g_aVGAStateSVGAFields[] =
497	{
498	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	{
811	*pu32 = pThis->svga.uWidth;
812	}
813	else
814	{
815	#ifndef IN_RING3
816	rc = VINF_IOM_R3_IOPORT_READ;
817	#else
818	*pu32 = pThis->pDrv->cx;
819	#endif
820	}
821	break;
822	}
823
824	case SVGA_REG_HEIGHT:
825	{
826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
827	if ( pThis->svga.fEnabled
828	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
829	{
830	*pu32 = pThis->svga.uHeight;
831	}
832	else
833	{
834	#ifndef IN_RING3
835	rc = VINF_IOM_R3_IOPORT_READ;
836	#else
837	*pu32 = pThis->pDrv->cy;
838	#endif
839	}
840	break;
841	}
842
843	case SVGA_REG_MAX_WIDTH:
844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
845	*pu32 = pThis->svga.u32MaxWidth;
846	break;
847
848	case SVGA_REG_MAX_HEIGHT:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
850	*pu32 = pThis->svga.u32MaxHeight;
851	break;
852
853	case SVGA_REG_DEPTH:
854	/* This returns the color depth of the current mode. */
855	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
856	switch (pThis->svga.uBpp)
857	{
858	case 15:
859	case 16:
860	case 24:
861	*pu32 = pThis->svga.uBpp;
862	break;
863
864	default:
865	case 32:
866	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
867	break;
868	}
869	break;
870
871	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
873	if ( pThis->svga.fEnabled
874	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
875	{
876	*pu32 = pThis->svga.uBpp;
877	}
878	else
879	{
880	#ifndef IN_RING3
881	rc = VINF_IOM_R3_IOPORT_READ;
882	#else
883	*pu32 = pThis->pDrv->cBits;
884	#endif
885	}
886	break;
887
888	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
890	if ( pThis->svga.fEnabled
891	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
892	{
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	}
895	else
896	{
897	#ifndef IN_RING3
898	rc = VINF_IOM_R3_IOPORT_READ;
899	#else
900	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
901	#endif
902	}
903	break;
904
905	case SVGA_REG_PSEUDOCOLOR:
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
907	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
908	break;
909
910	case SVGA_REG_RED_MASK:
911	case SVGA_REG_GREEN_MASK:
912	case SVGA_REG_BLUE_MASK:
913	{
914	uint32_t uBpp;
915
916	if ( pThis->svga.fEnabled
917	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
918	{
919	uBpp = pThis->svga.uBpp;
920	}
921	else
922	{
923	#ifndef IN_RING3
924	rc = VINF_IOM_R3_IOPORT_READ;
925	break;
926	#else
927	uBpp = pThis->pDrv->cBits;
928	#endif
929	}
930	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
931	switch (uBpp)
932	{
933	case 8:
934	u32RedMask = 0x07;
935	u32GreenMask = 0x38;
936	u32BlueMask = 0xc0;
937	break;
938
939	case 15:
940	u32RedMask = 0x0000001f;
941	u32GreenMask = 0x000003e0;
942	u32BlueMask = 0x00007c00;
943	break;
944
945	case 16:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000007e0;
948	u32BlueMask = 0x0000f800;
949	break;
950
951	case 24:
952	case 32:
953	default:
954	u32RedMask = 0x00ff0000;
955	u32GreenMask = 0x0000ff00;
956	u32BlueMask = 0x000000ff;
957	break;
958	}
959	switch (idxReg)
960	{
961	case SVGA_REG_RED_MASK:
962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
963	*pu32 = u32RedMask;
964	break;
965
966	case SVGA_REG_GREEN_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
968	*pu32 = u32GreenMask;
969	break;
970
971	case SVGA_REG_BLUE_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
973	*pu32 = u32BlueMask;
974	break;
975	}
976	break;
977	}
978
979	case SVGA_REG_BYTES_PER_LINE:
980	{
981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
982	if ( pThis->svga.fEnabled
983	&& pThis->svga.cbScanline)
984	{
985	*pu32 = pThis->svga.cbScanline;
986	}
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThis->pDrv->cbScanline;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_VRAM_SIZE: /* VRAM size */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1000	*pu32 = pThis->vram_size;
1001	break;
1002
1003	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1005	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1006	*pu32 = pThis->GCPhysVRAM;
1007	break;
1008
1009	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1011	/* Always zero in our case. */
1012	*pu32 = 0;
1013	break;
1014
1015	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1016	{
1017	#ifndef IN_RING3
1018	rc = VINF_IOM_R3_IOPORT_READ;
1019	#else
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1021
1022	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1023	if ( pThis->svga.fEnabled
1024	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1025	{
1026	/* Hardware enabled; return real framebuffer size .*/
1027	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1028	}
1029	else
1030	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1031
1032	pu32 = RT_MIN(pThis->vram_size, pu32);
1033	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1034	#endif
1035	break;
1036	}
1037
1038	case SVGA_REG_CAPABILITIES:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1040	*pu32 = pThis->svga.u32RegCaps;
1041	break;
1042
1043	case SVGA_REG_MEM_START: /* FIFO start */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1045	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1046	*pu32 = pThis->svga.GCPhysFIFO;
1047	break;
1048
1049	case SVGA_REG_MEM_SIZE: /* FIFO size */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1051	*pu32 = pThis->svga.cbFIFO;
1052	break;
1053
1054	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1056	*pu32 = pThis->svga.fConfigured;
1057	break;
1058
1059	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1061	*pu32 = 0;
1062	break;
1063
1064	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1066	if (pThis->svga.fBusy)
1067	{
1068	#ifndef IN_RING3
1069	/* Go to ring-3 and halt the CPU. */
1070	rc = VINF_IOM_R3_IOPORT_READ;
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	if (pThis->svga.fGFBRegisters)
1422	{
1423	vgaR3UpdateDisplay(pThis, x, y, w, h);
1424	}
1425	else
1426	{
1427	VBVACMDHDR cmd;
1428	cmd.x = (int16_t)(pScreen->xOrigin + x);
1429	cmd.y = (int16_t)(pScreen->yOrigin + y);
1430	cmd.w = (uint16_t)w;
1431	cmd.h = (uint16_t)h;
1432
1433	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1434	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1435	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1436	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1437	}
1438
1439	return VINF_SUCCESS;
1440	}
1441
1442	#endif /* IN_RING3 */
1443
1444	#if defined(IN_RING0) \|\| defined(IN_RING3)
1445	/**
1446	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1447	*
1448	* @param pThis The VMSVGA state.
1449	* @param fState The busy state.
1450	*/
1451	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1452	{
1453	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1454
1455	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1456	{
1457	/* Race / unfortunately scheduling. Highly unlikly. */
1458	uint32_t cLoops = 64;
1459	do
1460	{
1461	ASMNopPause();
1462	fState = (pThis->svga.fBusy != 0);
1463	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1464	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1465	}
1466	}
1467	#endif
1468
1469	/**
1470	* Write port register
1471	*
1472	* @returns VBox status code.
1473	* @param pThis VMSVGA State
1474	* @param u32 Value to write
1475	*/
1476	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1477	{
1478	#ifdef IN_RING3
1479	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1480	#endif
1481	int rc = VINF_SUCCESS;
1482
1483	/* Rough index register validation. */
1484	uint32_t idxReg = pThis->svga.u32IndexReg;
1485	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1486	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1487	VINF_IOM_R3_IOPORT_WRITE);
1488	#else
1489	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1490	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1491	VINF_SUCCESS);
1492	#endif
1493	RT_UNTRUSTED_VALIDATED_FENCE();
1494
1495	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1496	if ( idxReg >= SVGA_REG_CAPABILITIES
1497	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1498	{
1499	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1500	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1501	}
1502	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1503	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1504	switch (idxReg)
1505	{
1506	case SVGA_REG_WIDTH:
1507	case SVGA_REG_HEIGHT:
1508	case SVGA_REG_PITCHLOCK:
1509	case SVGA_REG_BITS_PER_PIXEL:
1510	pThis->svga.fGFBRegisters = true;
1511	break;
1512	default:
1513	break;
1514	}
1515
1516	switch (idxReg)
1517	{
1518	case SVGA_REG_ID:
1519	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1520	if ( u32 == SVGA_ID_0
1521	\|\| u32 == SVGA_ID_1
1522	\|\| u32 == SVGA_ID_2)
1523	pThis->svga.u32SVGAId = u32;
1524	else
1525	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1526	break;
1527
1528	case SVGA_REG_ENABLE:
1529	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1530	#ifdef IN_RING3
1531	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1532	&& pThis->svga.fEnabled == false)
1533	{
1534	/* Make a backup copy of the first 512kb in order to save font data etc. */
1535	/** @todo should probably swap here, rather than copy + zero */
1536	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1537	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1538	}
1539
1540	pThis->svga.fEnabled = u32;
1541	if (pThis->svga.fEnabled)
1542	{
1543	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1544	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1545	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1546	{
1547	/* Keep the current mode. */
1548	pThis->svga.uWidth = pThis->pDrv->cx;
1549	pThis->svga.uHeight = pThis->pDrv->cy;
1550	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1551	}
1552
1553	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1554	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1555	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1556	{
1557	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1558	}
1559	# ifdef LOG_ENABLED
1560	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1561	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1562	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1563	# endif
1564
1565	/* Disable or enable dirty page tracking according to the current fTraces value. */
1566	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1567
1568	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1569	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1570	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1571	}
1572	else
1573	{
1574	/* Restore the text mode backup. */
1575	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1576
1577	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1578
1579	/* Enable dirty page tracking again when going into legacy mode. */
1580	vmsvgaSetTraces(pThis, true);
1581
1582	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1583	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1584	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1585	}
1586	#else /* !IN_RING3 */
1587	rc = VINF_IOM_R3_IOPORT_WRITE;
1588	#endif /* !IN_RING3 */
1589	break;
1590
1591	case SVGA_REG_WIDTH:
1592	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1593	if (pThis->svga.uWidth != u32)
1594	{
1595	pThis->svga.uWidth = u32;
1596	if (pThis->svga.fEnabled)
1597	{
1598	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1599	}
1600	}
1601	/* else: nop */
1602	break;
1603
1604	case SVGA_REG_HEIGHT:
1605	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1606	if (pThis->svga.uHeight != u32)
1607	{
1608	pThis->svga.uHeight = u32;
1609	if (pThis->svga.fEnabled)
1610	{
1611	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1612	}
1613	}
1614	/* else: nop */
1615	break;
1616
1617	case SVGA_REG_DEPTH:
1618	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1619	/** @todo read-only?? */
1620	break;
1621
1622	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1623	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1624	if (pThis->svga.uBpp != u32)
1625	{
1626	pThis->svga.uBpp = u32;
1627	if (pThis->svga.fEnabled)
1628	{
1629	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1630	}
1631	}
1632	/* else: nop */
1633	break;
1634
1635	case SVGA_REG_PSEUDOCOLOR:
1636	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1637	break;
1638
1639	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1640	#ifdef IN_RING3
1641	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1642	pThis->svga.fConfigured = u32;
1643	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1644	if (!pThis->svga.fConfigured)
1645	{
1646	pThis->svga.fTraces = true;
1647	}
1648	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1649	#else
1650	rc = VINF_IOM_R3_IOPORT_WRITE;
1651	#endif
1652	break;
1653
1654	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1655	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1656	if ( pThis->svga.fEnabled
1657	&& pThis->svga.fConfigured)
1658	{
1659	#if defined(IN_RING3) \|\| defined(IN_RING0)
1660	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1661	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1662	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1663	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1664
1665	/* Kick the FIFO thread to start processing commands again. */
1666	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1667	#else
1668	rc = VINF_IOM_R3_IOPORT_WRITE;
1669	#endif
1670	}
1671	/* else nothing to do. */
1672	else
1673	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1674
1675	break;
1676
1677	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1678	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1679	break;
1680
1681	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1682	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1683	pThis->svga.u32GuestId = u32;
1684	break;
1685
1686	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1687	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1688	pThis->svga.u32PitchLock = u32;
1689	break;
1690
1691	case SVGA_REG_IRQMASK: /* Interrupt mask */
1692	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1693	pThis->svga.u32IrqMask = u32;
1694
1695	/* Irq pending after the above change? */
1696	if (pThis->svga.u32IrqStatus & u32)
1697	{
1698	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1699	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1700	}
1701	else
1702	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1703	break;
1704
1705	/* Mouse cursor support */
1706	case SVGA_REG_CURSOR_ID:
1707	case SVGA_REG_CURSOR_X:
1708	case SVGA_REG_CURSOR_Y:
1709	case SVGA_REG_CURSOR_ON:
1710	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1711	break;
1712
1713	/* Legacy multi-monitor support */
1714	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1715	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1716	break;
1717	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1718	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1719	break;
1720	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1722	break;
1723	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1724	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1725	break;
1726	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1727	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1728	break;
1729	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1730	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1731	break;
1732	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1733	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1734	break;
1735	#ifdef VBOX_WITH_VMSVGA3D
1736	/* See "Guest memory regions" below. */
1737	case SVGA_REG_GMR_ID:
1738	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1739	pThis->svga.u32CurrentGMRId = u32;
1740	break;
1741
1742	case SVGA_REG_GMR_DESCRIPTOR:
1743	# ifndef IN_RING3
1744	rc = VINF_IOM_R3_IOPORT_WRITE;
1745	break;
1746	# else /* IN_RING3 */
1747	{
1748	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1749
1750	/* Validate current GMR id. */
1751	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1752	AssertBreak(idGMR < pThis->svga.cGMR);
1753	RT_UNTRUSTED_VALIDATED_FENCE();
1754
1755	/* Free the old GMR if present. */
1756	vmsvgaGMRFree(pThis, idGMR);
1757
1758	/* Just undefine the GMR? */
1759	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1760	if (GCPhys == 0)
1761	{
1762	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1763	break;
1764	}
1765
1766
1767	/* Never cross a page boundary automatically. */
1768	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1769	uint32_t cPagesTotal = 0;
1770	uint32_t iDesc = 0;
1771	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1772	uint32_t cLoops = 0;
1773	RTGCPHYS GCPhysBase = GCPhys;
1774	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1775	{
1776	/* Read descriptor. */
1777	SVGAGuestMemDescriptor desc;
1778	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1779	AssertRCBreak(rc);
1780
1781	if (desc.numPages != 0)
1782	{
1783	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1784	cPagesTotal += desc.numPages;
1785	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1786
1787	if ((iDesc & 15) == 0)
1788	{
1789	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1790	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1791	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1792	}
1793
1794	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1795	paDescs[iDesc++].numPages = desc.numPages;
1796
1797	/* Continue with the next descriptor. */
1798	GCPhys += sizeof(desc);
1799	}
1800	else if (desc.ppn == 0)
1801	break; /* terminator */
1802	else /* Pointer to the next physical page of descriptors. */
1803	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1804
1805	cLoops++;
1806	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1807	}
1808
1809	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1810	if (RT_SUCCESS(rc))
1811	{
1812	/* Commit the GMR. */
1813	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1814	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1815	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1816	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1817	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1818	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1819	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1820	}
1821	else
1822	{
1823	RTMemFree(paDescs);
1824	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1825	}
1826	break;
1827	}
1828	# endif /* IN_RING3 */
1829	#endif // VBOX_WITH_VMSVGA3D
1830
1831	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1832	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1833	if (pThis->svga.fTraces == u32)
1834	break; /* nothing to do */
1835
1836	#ifdef IN_RING3
1837	vmsvgaSetTraces(pThis, !!u32);
1838	#else
1839	rc = VINF_IOM_R3_IOPORT_WRITE;
1840	#endif
1841	break;
1842
1843	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1845	break;
1846
1847	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1848	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1849	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1850	break;
1851
1852	case SVGA_REG_FB_START:
1853	case SVGA_REG_MEM_START:
1854	case SVGA_REG_HOST_BITS_PER_PIXEL:
1855	case SVGA_REG_MAX_WIDTH:
1856	case SVGA_REG_MAX_HEIGHT:
1857	case SVGA_REG_VRAM_SIZE:
1858	case SVGA_REG_FB_SIZE:
1859	case SVGA_REG_CAPABILITIES:
1860	case SVGA_REG_MEM_SIZE:
1861	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1862	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1863	case SVGA_REG_BYTES_PER_LINE:
1864	case SVGA_REG_FB_OFFSET:
1865	case SVGA_REG_RED_MASK:
1866	case SVGA_REG_GREEN_MASK:
1867	case SVGA_REG_BLUE_MASK:
1868	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1869	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1870	case SVGA_REG_GMR_MAX_IDS:
1871	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1872	/* Read only - ignore. */
1873	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1874	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1875	break;
1876
1877	default:
1878	{
1879	uint32_t offReg;
1880	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1881	{
1882	RT_UNTRUSTED_VALIDATED_FENCE();
1883	pThis->svga.au32ScratchRegion[offReg] = u32;
1884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1885	}
1886	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1887	{
1888	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1889	Btw, see rgb_to_pixel32. */
1890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1891	u32 &= 0xff;
1892	RT_UNTRUSTED_VALIDATED_FENCE();
1893	uint32_t uRgb = pThis->last_palette[offReg / 3];
1894	switch (offReg % 3)
1895	{
1896	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1897	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1898	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1899	}
1900	pThis->last_palette[offReg / 3] = uRgb;
1901	}
1902	else
1903	{
1904	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1905	rc = VINF_IOM_R3_IOPORT_WRITE;
1906	#else
1907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1908	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1909	#endif
1910	}
1911	break;
1912	}
1913	}
1914	return rc;
1915	}
1916
1917	/**
1918	* Port I/O Handler for IN operations.
1919	*
1920	* @returns VINF_SUCCESS or VINF_EM_*.
1921	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1922	*
1923	* @param pDevIns The device instance.
1924	* @param pvUser User argument.
1925	* @param uPort Port number used for the IN operation.
1926	* @param pu32 Where to store the result. This is always a 32-bit
1927	* variable regardless of what @a cb might say.
1928	* @param cb Number of bytes read.
1929	*/
1930	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1931	{
1932	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1933	RT_NOREF_PV(pvUser);
1934
1935	/* Ignore non-dword accesses. */
1936	if (cb != 4)
1937	{
1938	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1939	*pu32 = UINT32_MAX;
1940	return VINF_SUCCESS;
1941	}
1942
1943	switch (uPort - pThis->svga.BasePort)
1944	{
1945	case SVGA_INDEX_PORT:
1946	*pu32 = pThis->svga.u32IndexReg;
1947	break;
1948
1949	case SVGA_VALUE_PORT:
1950	return vmsvgaReadPort(pThis, pu32);
1951
1952	case SVGA_BIOS_PORT:
1953	Log(("Ignoring BIOS port read\n"));
1954	*pu32 = 0;
1955	break;
1956
1957	case SVGA_IRQSTATUS_PORT:
1958	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1959	*pu32 = pThis->svga.u32IrqStatus;
1960	break;
1961
1962	default:
1963	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
1964	*pu32 = UINT32_MAX;
1965	break;
1966	}
1967
1968	return VINF_SUCCESS;
1969	}
1970
1971	/**
1972	* Port I/O Handler for OUT operations.
1973	*
1974	* @returns VINF_SUCCESS or VINF_EM_*.
1975	*
1976	* @param pDevIns The device instance.
1977	* @param pvUser User argument.
1978	* @param uPort Port number used for the OUT operation.
1979	* @param u32 The value to output.
1980	* @param cb The value size in bytes.
1981	*/
1982	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
1983	{
1984	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1985	RT_NOREF_PV(pvUser);
1986
1987	/* Ignore non-dword accesses. */
1988	if (cb != 4)
1989	{
1990	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
1991	return VINF_SUCCESS;
1992	}
1993
1994	switch (uPort - pThis->svga.BasePort)
1995	{
1996	case SVGA_INDEX_PORT:
1997	pThis->svga.u32IndexReg = u32;
1998	break;
1999
2000	case SVGA_VALUE_PORT:
2001	return vmsvgaWritePort(pThis, u32);
2002
2003	case SVGA_BIOS_PORT:
2004	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2005	break;
2006
2007	case SVGA_IRQSTATUS_PORT:
2008	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2009	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2010	/* Clear the irq in case all events have been cleared. */
2011	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2012	{
2013	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2014	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2015	}
2016	break;
2017
2018	default:
2019	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2020	uPort - pThis->svga.BasePort, uPort, u32, cb));
2021	break;
2022	}
2023	return VINF_SUCCESS;
2024	}
2025
2026	#ifdef IN_RING3
2027
2028	# ifdef DEBUG_FIFO_ACCESS
2029	/**
2030	* Handle FIFO memory access.
2031	* @returns VBox status code.
2032	* @param pVM VM handle.
2033	* @param pThis VGA device instance data.
2034	* @param GCPhys The access physical address.
2035	* @param fWriteAccess Read or write access
2036	*/
2037	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2038	{
2039	RT_NOREF(pVM);
2040	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2041	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2042
2043	switch (GCPhysOffset >> 2)
2044	{
2045	case SVGA_FIFO_MIN:
2046	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2047	break;
2048	case SVGA_FIFO_MAX:
2049	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2050	break;
2051	case SVGA_FIFO_NEXT_CMD:
2052	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2053	break;
2054	case SVGA_FIFO_STOP:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_CAPABILITIES:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_FLAGS:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_FENCE:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_3D_HWVERSION:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_PITCHLOCK:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_CURSOR_ON:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_CURSOR_X:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_CURSOR_Y:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_CURSOR_COUNT:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_RESERVED:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_CURSOR_SCREEN_ID:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_DEAD:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_3D_HWVERSION_REVISED:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS_LAST:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_GUEST_3D_HWVERSION:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_FENCE_GOAL:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_BUSY:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	default:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	}
2364
2365	return VINF_EM_RAW_EMULATE_INSTR;
2366	}
2367	# endif /* DEBUG_FIFO_ACCESS */
2368
2369	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2370	/**
2371	* HC access handler for the FIFO.
2372	*
2373	* @returns VINF_SUCCESS if the handler have carried out the operation.
2374	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2375	* @param pVM VM Handle.
2376	* @param pVCpu The cross context CPU structure for the calling EMT.
2377	* @param GCPhys The physical address the guest is writing to.
2378	* @param pvPhys The HC mapping of that address.
2379	* @param pvBuf What the guest is reading/writing.
2380	* @param cbBuf How much it's reading/writing.
2381	* @param enmAccessType The access type.
2382	* @param enmOrigin Who is making the access.
2383	* @param pvUser User argument.
2384	*/
2385	static DECLCALLBACK(VBOXSTRICTRC)
2386	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2387	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2388	{
2389	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2390	PVGASTATE pThis = (PVGASTATE)pvUser;
2391	AssertPtr(pThis);
2392
2393	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2394	/*
2395	* Wake up the FIFO thread as it might have work to do now.
2396	*/
2397	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2398	AssertLogRelRC(rc);
2399	# endif
2400
2401	# ifdef DEBUG_FIFO_ACCESS
2402	/*
2403	* When in debug-fifo-access mode, we do not disable the access handler,
2404	* but leave it on as we wish to catch all access.
2405	*/
2406	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2407	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2408	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2409	/*
2410	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2411	*/
2412	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2413	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2414	# endif
2415	if (RT_SUCCESS(rc))
2416	return VINF_PGM_HANDLER_DO_DEFAULT;
2417	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2418	return rc;
2419	}
2420	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2421
2422	#endif /* IN_RING3 */
2423
2424	#ifdef DEBUG_GMR_ACCESS
2425	# ifdef IN_RING3
2426
2427	/**
2428	* HC access handler for the FIFO.
2429	*
2430	* @returns VINF_SUCCESS if the handler have carried out the operation.
2431	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2432	* @param pVM VM Handle.
2433	* @param pVCpu The cross context CPU structure for the calling EMT.
2434	* @param GCPhys The physical address the guest is writing to.
2435	* @param pvPhys The HC mapping of that address.
2436	* @param pvBuf What the guest is reading/writing.
2437	* @param cbBuf How much it's reading/writing.
2438	* @param enmAccessType The access type.
2439	* @param enmOrigin Who is making the access.
2440	* @param pvUser User argument.
2441	*/
2442	static DECLCALLBACK(VBOXSTRICTRC)
2443	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2444	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2445	{
2446	PVGASTATE pThis = (PVGASTATE)pvUser;
2447	Assert(pThis);
2448	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2449	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2450
2451	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2452
2453	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2454	{
2455	PGMR pGMR = &pSVGAState->paGMR[i];
2456
2457	if (pGMR->numDescriptors)
2458	{
2459	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2460	{
2461	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2462	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2463	{
2464	/*
2465	* Turn off the write handler for this particular page and make it R/W.
2466	* Then return telling the caller to restart the guest instruction.
2467	*/
2468	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2469	AssertRC(rc);
2470	goto end;
2471	}
2472	}
2473	}
2474	}
2475	end:
2476	return VINF_PGM_HANDLER_DO_DEFAULT;
2477	}
2478
2479	/* Callback handler for VMR3ReqCallWaitU */
2480	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2481	{
2482	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2483	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2484	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2485	int rc;
2486
2487	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2488	{
2489	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2490	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2491	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2492	AssertRC(rc);
2493	}
2494	return VINF_SUCCESS;
2495	}
2496
2497	/* Callback handler for VMR3ReqCallWaitU */
2498	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2499	{
2500	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2501	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2502	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2503
2504	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2505	{
2506	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2507	AssertRC(rc);
2508	}
2509	return VINF_SUCCESS;
2510	}
2511
2512	/* Callback handler for VMR3ReqCallWaitU */
2513	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2514	{
2515	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2516
2517	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2518	{
2519	PGMR pGMR = &pSVGAState->paGMR[i];
2520
2521	if (pGMR->numDescriptors)
2522	{
2523	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2524	{
2525	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2526	AssertRC(rc);
2527	}
2528	}
2529	}
2530	return VINF_SUCCESS;
2531	}
2532
2533	# endif /* IN_RING3 */
2534	#endif /* DEBUG_GMR_ACCESS */
2535
2536	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2537
2538	#ifdef IN_RING3
2539
2540
2541	/**
2542	* Common worker for changing the pointer shape.
2543	*
2544	* @param pThis The VGA instance data.
2545	* @param pSVGAState The VMSVGA ring-3 instance data.
2546	* @param fAlpha Whether there is alpha or not.
2547	* @param xHot Hotspot x coordinate.
2548	* @param yHot Hotspot y coordinate.
2549	* @param cx Width.
2550	* @param cy Height.
2551	* @param pbData Heap copy of the cursor data. Consumed.
2552	* @param cbData The size of the data.
2553	*/
2554	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2555	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2556	{
2557	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2558	#ifdef LOG_ENABLED
2559	if (LogIs2Enabled())
2560	{
2561	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2562	if (!fAlpha)
2563	{
2564	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2565	for (uint32_t y = 0; y < cy; y++)
2566	{
2567	Log2(("%3u:", y));
2568	uint8_t const pbLine = &pbData[y cbAndLine];
2569	for (uint32_t x = 0; x < cx; x += 8)
2570	{
2571	uint8_t b = pbLine[x / 8];
2572	char szByte[12];
2573	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2574	szByte[1] = b & 0x40 ? '*' : ' ';
2575	szByte[2] = b & 0x20 ? '*' : ' ';
2576	szByte[3] = b & 0x10 ? '*' : ' ';
2577	szByte[4] = b & 0x08 ? '*' : ' ';
2578	szByte[5] = b & 0x04 ? '*' : ' ';
2579	szByte[6] = b & 0x02 ? '*' : ' ';
2580	szByte[7] = b & 0x01 ? '*' : ' ';
2581	szByte[8] = '\0';
2582	Log2(("%s", szByte));
2583	}
2584	Log2(("\n"));
2585	}
2586	}
2587
2588	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2589	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2590	for (uint32_t y = 0; y < cy; y++)
2591	{
2592	Log2(("%3u:", y));
2593	uint32_t const pu32Line = &pu32Xor[y cx];
2594	for (uint32_t x = 0; x < cx; x++)
2595	Log2((" %08x", pu32Line[x]));
2596	Log2(("\n"));
2597	}
2598	}
2599	#endif
2600
2601	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2602	AssertRC(rc);
2603
2604	if (pSVGAState->Cursor.fActive)
2605	RTMemFree(pSVGAState->Cursor.pData);
2606
2607	pSVGAState->Cursor.fActive = true;
2608	pSVGAState->Cursor.xHotspot = xHot;
2609	pSVGAState->Cursor.yHotspot = yHot;
2610	pSVGAState->Cursor.width = cx;
2611	pSVGAState->Cursor.height = cy;
2612	pSVGAState->Cursor.cbData = cbData;
2613	pSVGAState->Cursor.pData = pbData;
2614	}
2615
2616
2617	/**
2618	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2619	*
2620	* @param pThis The VGA instance data.
2621	* @param pSVGAState The VMSVGA ring-3 instance data.
2622	* @param pCursor The cursor.
2623	* @param pbSrcAndMask The AND mask.
2624	* @param cbSrcAndLine The scanline length of the AND mask.
2625	* @param pbSrcXorMask The XOR mask.
2626	* @param cbSrcXorLine The scanline length of the XOR mask.
2627	*/
2628	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2629	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2630	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2631	{
2632	uint32_t const cx = pCursor->width;
2633	uint32_t const cy = pCursor->height;
2634
2635	/*
2636	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2637	* The AND data uses 8-bit aligned scanlines.
2638	* The XOR data must be starting on a 32-bit boundrary.
2639	*/
2640	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2641	uint32_t cbDstAndMask = cbDstAndLine * cy;
2642	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2643	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2644
2645	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2646	AssertReturnVoid(pbCopy);
2647
2648	/* Convert the AND mask. */
2649	uint8_t *pbDst = pbCopy;
2650	uint8_t const *pbSrc = pbSrcAndMask;
2651	switch (pCursor->andMaskDepth)
2652	{
2653	case 1:
2654	if (cbSrcAndLine == cbDstAndLine)
2655	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2656	else
2657	{
2658	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2659	for (uint32_t y = 0; y < cy; y++)
2660	{
2661	memcpy(pbDst, pbSrc, cbDstAndLine);
2662	pbDst += cbDstAndLine;
2663	pbSrc += cbSrcAndLine;
2664	}
2665	}
2666	break;
2667	/* Should take the XOR mask into account for the multi-bit AND mask. */
2668	case 8:
2669	for (uint32_t y = 0; y < cy; y++)
2670	{
2671	for (uint32_t x = 0; x < cx; )
2672	{
2673	uint8_t bDst = 0;
2674	uint8_t fBit = 1;
2675	do
2676	{
2677	uintptr_t const idxPal = pbSrc[x] * 3;
2678	if ((( pThis->last_palette[idxPal]
2679	\| (pThis->last_palette[idxPal] >> 8)
2680	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2681	bDst \|= fBit;
2682	fBit <<= 1;
2683	x++;
2684	} while (x < cx && (x & 7));
2685	pbDst[(x - 1) / 8] = bDst;
2686	}
2687	pbDst += cbDstAndLine;
2688	pbSrc += cbSrcAndLine;
2689	}
2690	break;
2691	case 15:
2692	for (uint32_t y = 0; y < cy; y++)
2693	{
2694	for (uint32_t x = 0; x < cx; )
2695	{
2696	uint8_t bDst = 0;
2697	uint8_t fBit = 1;
2698	do
2699	{
2700	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2701	bDst \|= fBit;
2702	fBit <<= 1;
2703	x++;
2704	} while (x < cx && (x & 7));
2705	pbDst[(x - 1) / 8] = bDst;
2706	}
2707	pbDst += cbDstAndLine;
2708	pbSrc += cbSrcAndLine;
2709	}
2710	break;
2711	case 16:
2712	for (uint32_t y = 0; y < cy; y++)
2713	{
2714	for (uint32_t x = 0; x < cx; )
2715	{
2716	uint8_t bDst = 0;
2717	uint8_t fBit = 1;
2718	do
2719	{
2720	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2721	bDst \|= fBit;
2722	fBit <<= 1;
2723	x++;
2724	} while (x < cx && (x & 7));
2725	pbDst[(x - 1) / 8] = bDst;
2726	}
2727	pbDst += cbDstAndLine;
2728	pbSrc += cbSrcAndLine;
2729	}
2730	break;
2731	case 24:
2732	for (uint32_t y = 0; y < cy; y++)
2733	{
2734	for (uint32_t x = 0; x < cx; )
2735	{
2736	uint8_t bDst = 0;
2737	uint8_t fBit = 1;
2738	do
2739	{
2740	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2741	bDst \|= fBit;
2742	fBit <<= 1;
2743	x++;
2744	} while (x < cx && (x & 7));
2745	pbDst[(x - 1) / 8] = bDst;
2746	}
2747	pbDst += cbDstAndLine;
2748	pbSrc += cbSrcAndLine;
2749	}
2750	break;
2751	case 32:
2752	for (uint32_t y = 0; y < cy; y++)
2753	{
2754	for (uint32_t x = 0; x < cx; )
2755	{
2756	uint8_t bDst = 0;
2757	uint8_t fBit = 1;
2758	do
2759	{
2760	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2761	bDst \|= fBit;
2762	fBit <<= 1;
2763	x++;
2764	} while (x < cx && (x & 7));
2765	pbDst[(x - 1) / 8] = bDst;
2766	}
2767	pbDst += cbDstAndLine;
2768	pbSrc += cbSrcAndLine;
2769	}
2770	break;
2771	default:
2772	RTMemFree(pbCopy);
2773	AssertFailedReturnVoid();
2774	}
2775
2776	/* Convert the XOR mask. */
2777	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2778	pbSrc = pbSrcXorMask;
2779	switch (pCursor->xorMaskDepth)
2780	{
2781	case 1:
2782	for (uint32_t y = 0; y < cy; y++)
2783	{
2784	for (uint32_t x = 0; x < cx; )
2785	{
2786	/* most significant bit is the left most one. */
2787	uint8_t bSrc = pbSrc[x / 8];
2788	do
2789	{
2790	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2791	bSrc <<= 1;
2792	x++;
2793	} while ((x & 7) && x < cx);
2794	}
2795	pbSrc += cbSrcXorLine;
2796	}
2797	break;
2798	case 8:
2799	for (uint32_t y = 0; y < cy; y++)
2800	{
2801	for (uint32_t x = 0; x < cx; x++)
2802	{
2803	uint32_t u = pThis->last_palette[pbSrc[x]];
2804	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2805	}
2806	pbSrc += cbSrcXorLine;
2807	}
2808	break;
2809	case 15: /* Src: RGB-5-5-5 */
2810	for (uint32_t y = 0; y < cy; y++)
2811	{
2812	for (uint32_t x = 0; x < cx; x++)
2813	{
2814	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2815	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2816	((uValue >> 5) & 0x1f) << 3,
2817	((uValue >> 10) & 0x1f) << 3, 0);
2818	}
2819	pbSrc += cbSrcXorLine;
2820	}
2821	break;
2822	case 16: /* Src: RGB-5-6-5 */
2823	for (uint32_t y = 0; y < cy; y++)
2824	{
2825	for (uint32_t x = 0; x < cx; x++)
2826	{
2827	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2828	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2829	((uValue >> 5) & 0x3f) << 2,
2830	((uValue >> 11) & 0x1f) << 3, 0);
2831	}
2832	pbSrc += cbSrcXorLine;
2833	}
2834	break;
2835	case 24:
2836	for (uint32_t y = 0; y < cy; y++)
2837	{
2838	for (uint32_t x = 0; x < cx; x++)
2839	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2840	pbSrc += cbSrcXorLine;
2841	}
2842	break;
2843	case 32:
2844	for (uint32_t y = 0; y < cy; y++)
2845	{
2846	for (uint32_t x = 0; x < cx; x++)
2847	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2848	pbSrc += cbSrcXorLine;
2849	}
2850	break;
2851	default:
2852	RTMemFree(pbCopy);
2853	AssertFailedReturnVoid();
2854	}
2855
2856	/*
2857	* Pass it to the frontend/whatever.
2858	*/
2859	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2860	}
2861
2862
2863	/**
2864	* Worker for vmsvgaR3FifoThread that handles an external command.
2865	*
2866	* @param pThis VGA device instance data.
2867	*/
2868	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2869	{
2870	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2871	switch (pThis->svga.u8FIFOExtCommand)
2872	{
2873	case VMSVGA_FIFO_EXTCMD_RESET:
2874	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2875	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2876	# ifdef VBOX_WITH_VMSVGA3D
2877	if (pThis->svga.f3DEnabled)
2878	{
2879	/* The 3d subsystem must be reset from the fifo thread. */
2880	vmsvga3dReset(pThis);
2881	}
2882	# endif
2883	break;
2884
2885	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2886	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2887	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2888	# ifdef VBOX_WITH_VMSVGA3D
2889	if (pThis->svga.f3DEnabled)
2890	{
2891	/* The 3d subsystem must be shut down from the fifo thread. */
2892	vmsvga3dTerminate(pThis);
2893	}
2894	# endif
2895	break;
2896
2897	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2898	{
2899	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2900	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2901	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2902	vmsvgaSaveExecFifo(pThis, pSSM);
2903	# ifdef VBOX_WITH_VMSVGA3D
2904	if (pThis->svga.f3DEnabled)
2905	vmsvga3dSaveExec(pThis, pSSM);
2906	# endif
2907	break;
2908	}
2909
2910	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2911	{
2912	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2913	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2914	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2915	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2916	# ifdef VBOX_WITH_VMSVGA3D
2917	if (pThis->svga.f3DEnabled)
2918	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2919	# endif
2920	break;
2921	}
2922
2923	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2924	{
2925	# ifdef VBOX_WITH_VMSVGA3D
2926	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2927	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2928	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2929	# endif
2930	break;
2931	}
2932
2933
2934	default:
2935	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2936	break;
2937	}
2938
2939	/*
2940	* Signal the end of the external command.
2941	*/
2942	pThis->svga.pvFIFOExtCmdParam = NULL;
2943	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2944	ASMMemoryFence(); /* paranoia^2 */
2945	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2946	AssertLogRelRC(rc);
2947	}
2948
2949	/**
2950	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2951	* doing a job on the FIFO thread (even when it's officially suspended).
2952	*
2953	* @returns VBox status code (fully asserted).
2954	* @param pThis VGA device instance data.
2955	* @param uExtCmd The command to execute on the FIFO thread.
2956	* @param pvParam Pointer to command parameters.
2957	* @param cMsWait The time to wait for the command, given in
2958	* milliseconds.
2959	*/
2960	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2961	{
2962	Assert(cMsWait >= RT_MS_1SEC * 5);
2963	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2964	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2965
2966	int rc;
2967	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2968	PDMTHREADSTATE enmState = pThread->enmState;
2969	if (enmState == PDMTHREADSTATE_SUSPENDED)
2970	{
2971	/*
2972	* The thread is suspended, we have to temporarily wake it up so it can
2973	* perform the task.
2974	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2975	*/
2976	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2977	/* Post the request. */
2978	pThis->svga.fFifoExtCommandWakeup = true;
2979	pThis->svga.pvFIFOExtCmdParam = pvParam;
2980	pThis->svga.u8FIFOExtCommand = uExtCmd;
2981	ASMMemoryFence(); /* paranoia^3 */
2982
2983	/* Resume the thread. */
2984	rc = PDMR3ThreadResume(pThread);
2985	AssertLogRelRC(rc);
2986	if (RT_SUCCESS(rc))
2987	{
2988	/* Wait. Take care in case the semaphore was already posted (same as below). */
2989	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2990	if ( rc == VINF_SUCCESS
2991	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
2992	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2993	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
2994	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2995
2996	/* suspend the thread */
2997	pThis->svga.fFifoExtCommandWakeup = false;
2998	int rc2 = PDMR3ThreadSuspend(pThread);
2999	AssertLogRelRC(rc2);
3000	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3001	rc = rc2;
3002	}
3003	pThis->svga.fFifoExtCommandWakeup = false;
3004	pThis->svga.pvFIFOExtCmdParam = NULL;
3005	}
3006	else if (enmState == PDMTHREADSTATE_RUNNING)
3007	{
3008	/*
3009	* The thread is running, should only happen during reset and vmsvga3dsfc.
3010	* We ASSUME not racing code here, both wrt thread state and ext commands.
3011	*/
3012	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3013	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3014
3015	/* Post the request. */
3016	pThis->svga.pvFIFOExtCmdParam = pvParam;
3017	pThis->svga.u8FIFOExtCommand = uExtCmd;
3018	ASMMemoryFence(); /* paranoia^2 */
3019	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3020	AssertLogRelRC(rc);
3021
3022	/* Wait. Take care in case the semaphore was already posted (same as above). */
3023	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3024	if ( rc == VINF_SUCCESS
3025	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3026	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3027	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3028	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3029
3030	pThis->svga.pvFIFOExtCmdParam = NULL;
3031	}
3032	else
3033	{
3034	/*
3035	* Something is wrong with the thread!
3036	*/
3037	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3038	rc = VERR_INVALID_STATE;
3039	}
3040	return rc;
3041	}
3042
3043
3044	/**
3045	* Marks the FIFO non-busy, notifying any waiting EMTs.
3046	*
3047	* @param pThis The VGA state.
3048	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3049	* @param offFifoMin The start byte offset of the command FIFO.
3050	*/
3051	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3052	{
3053	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3054	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3055	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3056
3057	/* Wake up any waiting EMTs. */
3058	if (pSVGAState->cBusyDelayedEmts > 0)
3059	{
3060	#ifdef VMSVGA_USE_EMT_HALT_CODE
3061	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3062	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3063	if (idCpu != NIL_VMCPUID)
3064	{
3065	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3066	while (idCpu-- > 0)
3067	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3068	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3069	}
3070	#else
3071	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3072	AssertRC(rc2);
3073	#endif
3074	}
3075	}
3076
3077	/**
3078	* Reads (more) payload into the command buffer.
3079	*
3080	* @returns pbBounceBuf on success
3081	* @retval (void *)1 if the thread was requested to stop.
3082	* @retval NULL on FIFO error.
3083	*
3084	* @param cbPayloadReq The number of bytes of payload requested.
3085	* @param pFIFO The FIFO.
3086	* @param offCurrentCmd The FIFO byte offset of the current command.
3087	* @param offFifoMin The start byte offset of the command FIFO.
3088	* @param offFifoMax The end byte offset of the command FIFO.
3089	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3090	* always sufficient size.
3091	* @param pcbAlreadyRead How much payload we've already read into the bounce
3092	* buffer. (We will NEVER re-read anything.)
3093	* @param pThread The calling PDM thread handle.
3094	* @param pThis The VGA state.
3095	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3096	* statistics collection.
3097	*/
3098	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3099	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3100	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3101	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3102	{
3103	Assert(pbBounceBuf);
3104	Assert(pcbAlreadyRead);
3105	Assert(offFifoMin < offFifoMax);
3106	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3107	Assert(offFifoMax <= pThis->svga.cbFIFO);
3108
3109	/*
3110	* Check if the requested payload size has already been satisfied .
3111	* .
3112	* When called to read more, the caller is responsible for making sure the .
3113	* new command size (cbRequsted) never is smaller than what has already .
3114	* been read.
3115	*/
3116	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3117	if (cbPayloadReq <= cbAlreadyRead)
3118	{
3119	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3120	return pbBounceBuf;
3121	}
3122
3123	/*
3124	* Commands bigger than the fifo buffer are invalid.
3125	*/
3126	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3127	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3128	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3129	NULL);
3130
3131	/*
3132	* Move offCurrentCmd past the command dword.
3133	*/
3134	offCurrentCmd += sizeof(uint32_t);
3135	if (offCurrentCmd >= offFifoMax)
3136	offCurrentCmd = offFifoMin;
3137
3138	/*
3139	* Do we have sufficient payload data available already?
3140	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3141	*/
3142	uint32_t cbAfter, cbBefore;
3143	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3144	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3145	if (offNextCmd >= offCurrentCmd)
3146	{
3147	if (RT_LIKELY(offNextCmd < offFifoMax))
3148	cbAfter = offNextCmd - offCurrentCmd;
3149	else
3150	{
3151	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3152	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3153	offNextCmd, offFifoMin, offFifoMax));
3154	cbAfter = offFifoMax - offCurrentCmd;
3155	}
3156	cbBefore = 0;
3157	}
3158	else
3159	{
3160	cbAfter = offFifoMax - offCurrentCmd;
3161	if (offNextCmd >= offFifoMin)
3162	cbBefore = offNextCmd - offFifoMin;
3163	else
3164	{
3165	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3166	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3167	offNextCmd, offFifoMin, offFifoMax));
3168	cbBefore = 0;
3169	}
3170	}
3171	if (cbAfter + cbBefore < cbPayloadReq)
3172	{
3173	/*
3174	* Insufficient, must wait for it to arrive.
3175	*/
3176	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3177	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3178	for (uint32_t i = 0;; i++)
3179	{
3180	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3181	{
3182	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3183	return (void *)(uintptr_t)1;
3184	}
3185	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3186	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3187
3188	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3189
3190	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3191	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3192	if (offNextCmd >= offCurrentCmd)
3193	{
3194	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3195	cbBefore = 0;
3196	}
3197	else
3198	{
3199	cbAfter = offFifoMax - offCurrentCmd;
3200	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3201	}
3202
3203	if (cbAfter + cbBefore >= cbPayloadReq)
3204	break;
3205	}
3206	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3207	}
3208
3209	/*
3210	* Copy out the memory and update what pcbAlreadyRead points to.
3211	*/
3212	if (cbAfter >= cbPayloadReq)
3213	memcpy(pbBounceBuf + cbAlreadyRead,
3214	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3215	cbPayloadReq - cbAlreadyRead);
3216	else
3217	{
3218	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3219	if (cbAlreadyRead < cbAfter)
3220	{
3221	memcpy(pbBounceBuf + cbAlreadyRead,
3222	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3223	cbAfter - cbAlreadyRead);
3224	cbAlreadyRead = cbAfter;
3225	}
3226	memcpy(pbBounceBuf + cbAlreadyRead,
3227	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3228	cbPayloadReq - cbAlreadyRead);
3229	}
3230	*pcbAlreadyRead = cbPayloadReq;
3231	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3232	return pbBounceBuf;
3233	}
3234
3235
3236	/**
3237	* Sends cursor position and visibility information from the FIFO to the front-end.
3238	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3239	*/
3240	static uint32_t
3241	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3242	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3243	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3244	{
3245	/*
3246	* Check if the cursor update counter has changed and try get a stable
3247	* set of values if it has. This is race-prone, especially consindering
3248	* the screen ID, but little we can do about that.
3249	*/
3250	uint32_t x, y, fVisible, idScreen;
3251	for (uint32_t i = 0; ; i++)
3252	{
3253	x = pFIFO[SVGA_FIFO_CURSOR_X];
3254	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3255	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3256	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3257	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3258	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3259	\|\| i > 3)
3260	break;
3261	if (i == 0)
3262	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3263	ASMNopPause();
3264	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3265	}
3266
3267	/*
3268	* Check if anything has changed, as calling into pDrv is not light-weight.
3269	*/
3270	if ( *pxLast == x
3271	&& *pyLast == y
3272	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3273	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3274	else
3275	{
3276	/*
3277	* Detected changes.
3278	*
3279	* We handle global, not per-screen visibility information by sending
3280	* pfnVBVAMousePointerShape without shape data.
3281	*/
3282	*pxLast = x;
3283	*pyLast = y;
3284	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3285	if (idScreen != SVGA_ID_INVALID)
3286	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3287	else if (*pfLastVisible != fVisible)
3288	{
3289	*pfLastVisible = fVisible;
3290	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3291	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3292	}
3293	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3294	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3295	}
3296
3297	/*
3298	* Update done. Signal this to the guest.
3299	*/
3300	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3301
3302	return uCursorUpdateCount;
3303	}
3304
3305
3306	/**
3307	* Checks if there is work to be done, either cursor updating or FIFO commands.
3308	*
3309	* @returns true if pending work, false if not.
3310	* @param pFIFO The FIFO to examine.
3311	* @param uLastCursorCount The last cursor update counter value.
3312	*/
3313	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3314	{
3315	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3316	return true;
3317
3318	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3319	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3320	return true;
3321
3322	return false;
3323	}
3324
3325
3326	/**
3327	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3328	*
3329	* @param pThis The VGA state.
3330	*/
3331	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3332	{
3333	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3334	to recheck it before doing the signalling. */
3335	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3336	AssertReturnVoid(pThis->svga.pFIFOR3);
3337	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3338	&& pThis->svga.fFIFOThreadSleeping)
3339	{
3340	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3341	AssertRC(rc);
3342	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3343	}
3344	}
3345
3346
3347	/* The async FIFO handling thread. */
3348	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3349	{
3350	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3351	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3352	int rc;
3353
3354	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3355	return VINF_SUCCESS;
3356
3357	/*
3358	* Special mode where we only execute an external command and the go back
3359	* to being suspended. Currently, all ext cmds ends up here, with the reset
3360	* one also being eligble for runtime execution further down as well.
3361	*/
3362	if (pThis->svga.fFifoExtCommandWakeup)
3363	{
3364	vmsvgaR3FifoHandleExtCmd(pThis);
3365	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3366	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3367	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3368	else
3369	vmsvgaR3FifoHandleExtCmd(pThis);
3370	return VINF_SUCCESS;
3371	}
3372
3373
3374	/*
3375	* Signal the semaphore to make sure we don't wait for 250ms after a
3376	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3377	*/
3378	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3379
3380	/*
3381	* Allocate a bounce buffer for command we get from the FIFO.
3382	* (All code must return via the end of the function to free this buffer.)
3383	*/
3384	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3385	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3386
3387	/*
3388	* Polling/sleep interval config.
3389	*
3390	* We wait for an a short interval if the guest has recently given us work
3391	* to do, but the interval increases the longer we're kept idle. Once we've
3392	* reached the refresh timer interval, we'll switch to extended waits,
3393	* depending on it or the guest to kick us into action when needed.
3394	*
3395	* Should the refresh time go fishing, we'll just continue increasing the
3396	* sleep length till we reaches the 250 ms max after about 16 seconds.
3397	*/
3398	RTMSINTERVAL const cMsMinSleep = 16;
3399	RTMSINTERVAL const cMsIncSleep = 2;
3400	RTMSINTERVAL const cMsMaxSleep = 250;
3401	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3402	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3403
3404	/*
3405	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3406	*
3407	* Initialize with values that will detect an update from the guest.
3408	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3409	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3410	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3411	*/
3412	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3413	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3414	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3415	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3416	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3417
3418	/*
3419	* The FIFO loop.
3420	*/
3421	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3422	bool fBadOrDisabledFifo = false;
3423	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3424	{
3425	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3426	/*
3427	* Should service the run loop every so often.
3428	*/
3429	if (pThis->svga.f3DEnabled)
3430	vmsvga3dCocoaServiceRunLoop();
3431	# endif
3432
3433	/*
3434	* Unless there's already work pending, go to sleep for a short while.
3435	* (See polling/sleep interval config above.)
3436	*/
3437	if ( fBadOrDisabledFifo
3438	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3439	{
3440	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3441	Assert(pThis->cMilliesRefreshInterval > 0);
3442	if (cMsSleep < pThis->cMilliesRefreshInterval)
3443	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3444	else
3445	{
3446	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3447	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3448	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3449	# endif
3450	if ( !fBadOrDisabledFifo
3451	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3452	rc = VINF_SUCCESS;
3453	else
3454	{
3455	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3456	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3457	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3458	}
3459	}
3460	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3461	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3462	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3463	{
3464	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3465	break;
3466	}
3467	}
3468	else
3469	rc = VINF_SUCCESS;
3470	fBadOrDisabledFifo = false;
3471	if (rc == VERR_TIMEOUT)
3472	{
3473	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3474	{
3475	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3476	continue;
3477	}
3478	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3479
3480	Log(("vmsvgaFIFOLoop: timeout\n"));
3481	}
3482	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3483	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3484	cMsSleep = cMsMinSleep;
3485
3486	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3487	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3488	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3489
3490	/*
3491	* Handle external commands (currently only reset).
3492	*/
3493	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3494	{
3495	vmsvgaR3FifoHandleExtCmd(pThis);
3496	continue;
3497	}
3498
3499	/*
3500	* The device must be enabled and configured.
3501	*/
3502	if ( !pThis->svga.fEnabled
3503	\|\| !pThis->svga.fConfigured)
3504	{
3505	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3506	fBadOrDisabledFifo = true;
3507	cMsSleep = cMsMaxSleep; /* cheat */
3508	continue;
3509	}
3510
3511	/*
3512	* Get and check the min/max values. We ASSUME that they will remain
3513	* unchanged while we process requests. A further ASSUMPTION is that
3514	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3515	* we don't read it back while in the loop.
3516	*/
3517	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3518	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3519	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3520	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3521	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3522	\|\| offFifoMax <= offFifoMin
3523	\|\| offFifoMax > pThis->svga.cbFIFO
3524	\|\| (offFifoMax & 3) != 0
3525	\|\| (offFifoMin & 3) != 0
3526	\|\| offCurrentCmd < offFifoMin
3527	\|\| offCurrentCmd > offFifoMax))
3528	{
3529	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3530	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3531	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3532	fBadOrDisabledFifo = true;
3533	continue;
3534	}
3535	RT_UNTRUSTED_VALIDATED_FENCE();
3536	if (RT_UNLIKELY(offCurrentCmd & 3))
3537	{
3538	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3539	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3540	offCurrentCmd = ~UINT32_C(3);
3541	}
3542
3543	/*
3544	* Update the cursor position before we start on the FIFO commands.
3545	*/
3546	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3547	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3548	{
3549	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3550	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3551	{ /* halfways likely */ }
3552	else
3553	{
3554	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3555	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3556	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3557	}
3558	}
3559
3560	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3561	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3562	*
3563	* Will break out of the switch on failure.
3564	* Will restart and quit the loop if the thread was requested to stop.
3565	*
3566	* @param a_PtrVar Request variable pointer.
3567	* @param a_Type Request typedef (not pointer) for casting.
3568	* @param a_cbPayloadReq How much payload to fetch.
3569	* @remarks Accesses a bunch of variables in the current scope!
3570	*/
3571	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3572	if (1) { \
3573	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3574	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3575	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3576	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3577	} else do {} while (0)
3578	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3579	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3580	* buffer after figuring out the actual command size.
3581	*
3582	* Will break out of the switch on failure.
3583	*
3584	* @param a_PtrVar Request variable pointer.
3585	* @param a_Type Request typedef (not pointer) for casting.
3586	* @param a_cbPayloadReq How much payload to fetch.
3587	* @remarks Accesses a bunch of variables in the current scope!
3588	*/
3589	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3590	if (1) { \
3591	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3592	} else do {} while (0)
3593
3594	/*
3595	* Mark the FIFO as busy.
3596	*/
3597	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3598	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3599	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3600
3601	/*
3602	* Execute all queued FIFO commands.
3603	* Quit if pending external command or changes in the thread state.
3604	*/
3605	bool fDone = false;
3606	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3607	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3608	{
3609	uint32_t cbPayload = 0;
3610	uint32_t u32IrqStatus = 0;
3611
3612	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3613
3614	/* First check any pending actions. */
3615	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3616	{
3617	vmsvgaChangeMode(pThis);
3618	# ifdef VBOX_WITH_VMSVGA3D
3619	if (pThis->svga.p3dState != NULL)
3620	vmsvga3dChangeMode(pThis);
3621	# endif
3622	}
3623
3624	/* Check for pending external commands (reset). */
3625	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3626	break;
3627
3628	/*
3629	* Process the command.
3630	*/
3631	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3632	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3633	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3634	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3635	switch (enmCmdId)
3636	{
3637	case SVGA_CMD_INVALID_CMD:
3638	/* Nothing to do. */
3639	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3640	break;
3641
3642	case SVGA_CMD_FENCE:
3643	{
3644	SVGAFifoCmdFence *pCmdFence;
3645	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3646	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3647	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3648	{
3649	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3650	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3651
3652	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3653	{
3654	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3655	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3656	}
3657	else
3658	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3659	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3660	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3661	{
3662	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3663	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3664	}
3665	}
3666	else
3667	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3668	break;
3669	}
3670	case SVGA_CMD_UPDATE:
3671	case SVGA_CMD_UPDATE_VERBOSE:
3672	{
3673	SVGAFifoCmdUpdate *pUpdate;
3674	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3675	if (enmCmdId == SVGA_CMD_UPDATE)
3676	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3677	else
3678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3679	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3680	/** @todo Multiple screens? */
3681	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3682	AssertBreak(pScreen);
3683	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3684	break;
3685	}
3686
3687	case SVGA_CMD_DEFINE_CURSOR:
3688	{
3689	/* Followed by bitmap data. */
3690	SVGAFifoCmdDefineCursor *pCursor;
3691	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3692	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3693
3694	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3695	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3696	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3697	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3698	AssertBreak(pCursor->andMaskDepth <= 32);
3699	AssertBreak(pCursor->xorMaskDepth <= 32);
3700	RT_UNTRUSTED_VALIDATED_FENCE();
3701
3702	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3703	uint32_t cbAndMask = cbAndLine * pCursor->height;
3704	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3705	uint32_t cbXorMask = cbXorLine * pCursor->height;
3706	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3707
3708	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3709	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3710	break;
3711	}
3712
3713	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3714	{
3715	/* Followed by bitmap data. */
3716	uint32_t cbCursorShape, cbAndMask;
3717	uint8_t *pCursorCopy;
3718	uint32_t cbCmd;
3719
3720	SVGAFifoCmdDefineAlphaCursor *pCursor;
3721	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3722	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3723
3724	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3725
3726	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3727	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3728	RT_UNTRUSTED_VALIDATED_FENCE();
3729
3730	/* Refetch the bitmap data as well. */
3731	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3732	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3733	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3734
3735	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3736	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3737	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3738	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3739
3740	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3741	AssertBreak(pCursorCopy);
3742
3743	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3744	memset(pCursorCopy, 0xff, cbAndMask);
3745	/* Colour data */
3746	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3747
3748	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3749	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3750	break;
3751	}
3752
3753	case SVGA_CMD_ESCAPE:
3754	{
3755	/* Followed by nsize bytes of data. */
3756	SVGAFifoCmdEscape *pEscape;
3757	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3758	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3759
3760	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3761	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3762	RT_UNTRUSTED_VALIDATED_FENCE();
3763	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3764	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3765
3766	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3767	{
3768	AssertBreak(pEscape->size >= sizeof(uint32_t));
3769	RT_UNTRUSTED_VALIDATED_FENCE();
3770	uint32_t cmd = (uint32_t )(pEscape + 1);
3771	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3772
3773	switch (cmd)
3774	{
3775	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3776	{
3777	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3778	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3779	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3780
3781	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3782	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3783	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3784
3785	RT_NOREF_PV(pVideoCmd);
3786	break;
3787
3788	}
3789
3790	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3791	{
3792	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3793	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3794	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3795	RT_NOREF_PV(pVideoCmd);
3796	break;
3797	}
3798
3799	default:
3800	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3801	break;
3802	}
3803	}
3804	else
3805	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3806
3807	break;
3808	}
3809	# ifdef VBOX_WITH_VMSVGA3D
3810	case SVGA_CMD_DEFINE_GMR2:
3811	{
3812	SVGAFifoCmdDefineGMR2 *pCmd;
3813	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3814	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3815	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3816
3817	/* Validate current GMR id. */
3818	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3819	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3820	RT_UNTRUSTED_VALIDATED_FENCE();
3821
3822	if (!pCmd->numPages)
3823	{
3824	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3825	vmsvgaGMRFree(pThis, pCmd->gmrId);
3826	}
3827	else
3828	{
3829	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3830	if (pGMR->cMaxPages)
3831	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3832
3833	/* Not sure if we should always free the descriptor, but for simplicity
3834	we do so if the new size is smaller than the current. */
3835	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3836	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3837	vmsvgaGMRFree(pThis, pCmd->gmrId);
3838
3839	pGMR->cMaxPages = pCmd->numPages;
3840	/* The rest is done by the REMAP_GMR2 command. */
3841	}
3842	break;
3843	}
3844
3845	case SVGA_CMD_REMAP_GMR2:
3846	{
3847	/* Followed by page descriptors or guest ptr. */
3848	SVGAFifoCmdRemapGMR2 *pCmd;
3849	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3850	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3851
3852	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3853	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3854	RT_UNTRUSTED_VALIDATED_FENCE();
3855
3856	/* Calculate the size of what comes after next and fetch it. */
3857	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3858	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3859	cbCmd += sizeof(SVGAGuestPtr);
3860	else
3861	{
3862	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3863	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3864	{
3865	cbCmd += cbPageDesc;
3866	pCmd->numPages = 1;
3867	}
3868	else
3869	{
3870	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3871	cbCmd += cbPageDesc * pCmd->numPages;
3872	}
3873	}
3874	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3875
3876	/* Validate current GMR id and size. */
3877	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3878	RT_UNTRUSTED_VALIDATED_FENCE();
3879	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3880	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3881	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3882	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3883
3884	if (pCmd->numPages == 0)
3885	break;
3886
3887	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3888	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3889
3890	/*
3891	* We flatten the existing descriptors into a page array, overwrite the
3892	* pages specified in this command and then recompress the descriptor.
3893	*/
3894	/** @todo Optimize the GMR remap algorithm! */
3895
3896	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3897	uint64_t *paNewPage64 = NULL;
3898	if (pGMR->paDesc)
3899	{
3900	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3901
3902	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3903	AssertBreak(paNewPage64);
3904
3905	uint32_t idxPage = 0;
3906	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3907	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3908	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3909	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3910	RT_UNTRUSTED_VALIDATED_FENCE();
3911	}
3912
3913	/* Free the old GMR if present. */
3914	if (pGMR->paDesc)
3915	RTMemFree(pGMR->paDesc);
3916
3917	/* Allocate the maximum amount possible (everything non-continuous) */
3918	PVMSVGAGMRDESCRIPTOR paDescs;
3919	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3920	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3921
3922	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3923	{
3924	/** @todo */
3925	AssertFailed();
3926	pGMR->numDescriptors = 0;
3927	}
3928	else
3929	{
3930	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3931	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3932	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3933
3934	if (paNewPage64)
3935	{
3936	/* Overwrite the old page array with the new page values. */
3937	if (fGCPhys64)
3938	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3939	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3940	else
3941	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3942	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3943
3944	/* Use the updated page array instead of the command data. */
3945	fGCPhys64 = true;
3946	paPages64 = paNewPage64;
3947	pCmd->numPages = cNewTotalPages;
3948	}
3949
3950	/* The first page. */
3951	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3952	* applied to paNewPage64. */
3953	RTGCPHYS GCPhys;
3954	if (fGCPhys64)
3955	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3956	else
3957	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3958	paDescs[0].GCPhys = GCPhys;
3959	paDescs[0].numPages = 1;
3960
3961	/* Subsequent pages. */
3962	uint32_t iDescriptor = 0;
3963	for (uint32_t i = 1; i < pCmd->numPages; i++)
3964	{
3965	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3966	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3967	else
3968	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3969
3970	/* Continuous physical memory? */
3971	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3972	{
3973	Assert(paDescs[iDescriptor].numPages);
3974	paDescs[iDescriptor].numPages++;
3975	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3976	}
3977	else
3978	{
3979	iDescriptor++;
3980	paDescs[iDescriptor].GCPhys = GCPhys;
3981	paDescs[iDescriptor].numPages = 1;
3982	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3983	}
3984	}
3985
3986	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3987	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
3988	pGMR->numDescriptors = iDescriptor + 1;
3989	}
3990
3991	if (paNewPage64)
3992	RTMemFree(paNewPage64);
3993
3994	# ifdef DEBUG_GMR_ACCESS
3995	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
3996	# endif
3997	break;
3998	}
3999	# endif // VBOX_WITH_VMSVGA3D
4000	case SVGA_CMD_DEFINE_SCREEN:
4001	{
4002	/* The size of this command is specified by the guest and depends on capabilities. */
4003	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4004
4005	SVGAFifoCmdDefineScreen *pCmd;
4006	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4007	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4008	RT_UNTRUSTED_VALIDATED_FENCE();
4009
4010	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4011	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4012	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4013
4014	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4015	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4016	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4017
4018	uint32_t const idScreen = pCmd->screen.id;
4019	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4020
4021	uint32_t const uWidth = pCmd->screen.size.width;
4022	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4023
4024	uint32_t const uHeight = pCmd->screen.size.height;
4025	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4026
4027	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4028	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4029	AssertBreak(cbWidth <= cbPitch);
4030
4031	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4032	AssertBreak(uScreenOffset < pThis->vram_size);
4033
4034	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4035	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4036	AssertBreak( (uHeight == 0 && cbPitch == 0)
4037	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4038	RT_UNTRUSTED_VALIDATED_FENCE();
4039
4040	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4041
4042	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4043
4044	pScreen->fDefined = true;
4045	pScreen->fModified = true;
4046	pScreen->fuScreen = pCmd->screen.flags;
4047	pScreen->idScreen = idScreen;
4048	if (!fBlank)
4049	{
4050	AssertBreak(uWidth > 0 && uHeight > 0);
4051
4052	pScreen->xOrigin = pCmd->screen.root.x;
4053	pScreen->yOrigin = pCmd->screen.root.y;
4054	pScreen->cWidth = uWidth;
4055	pScreen->cHeight = uHeight;
4056	pScreen->offVRAM = uScreenOffset;
4057	pScreen->cbPitch = cbPitch;
4058	pScreen->cBpp = 32;
4059	}
4060	else
4061	{
4062	/* Keep old values. */
4063	}
4064
4065	pThis->svga.fGFBRegisters = false;
4066	vmsvgaChangeMode(pThis);
4067	break;
4068	}
4069
4070	case SVGA_CMD_DESTROY_SCREEN:
4071	{
4072	SVGAFifoCmdDestroyScreen *pCmd;
4073	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4074	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4075
4076	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4077
4078	uint32_t const idScreen = pCmd->screenId;
4079	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4080	RT_UNTRUSTED_VALIDATED_FENCE();
4081
4082	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4083	pScreen->fModified = true;
4084	pScreen->fDefined = false;
4085	pScreen->idScreen = idScreen;
4086
4087	vmsvgaChangeMode(pThis);
4088	break;
4089	}
4090
4091	case SVGA_CMD_DEFINE_GMRFB:
4092	{
4093	SVGAFifoCmdDefineGMRFB *pCmd;
4094	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4095	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4096
4097	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4098	pSVGAState->GMRFB.ptr = pCmd->ptr;
4099	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4100	pSVGAState->GMRFB.format = pCmd->format;
4101	break;
4102	}
4103
4104	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4105	{
4106	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4107	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4108	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4109
4110	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4111	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4112
4113	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4114	RT_UNTRUSTED_VALIDATED_FENCE();
4115
4116	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4117	AssertBreak(pScreen);
4118
4119	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4120	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4121
4122	/* Clip destRect to the screen dimensions. */
4123	SVGASignedRect screenRect;
4124	screenRect.left = 0;
4125	screenRect.top = 0;
4126	screenRect.right = pScreen->cWidth;
4127	screenRect.bottom = pScreen->cHeight;
4128	SVGASignedRect clipRect = pCmd->destRect;
4129	vmsvgaClipRect(&screenRect, &clipRect);
4130	RT_UNTRUSTED_VALIDATED_FENCE();
4131
4132	uint32_t const width = clipRect.right - clipRect.left;
4133	uint32_t const height = clipRect.bottom - clipRect.top;
4134
4135	if ( width == 0
4136	\|\| height == 0)
4137	break; /* Nothing to do. */
4138
4139	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4140	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4141
4142	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4143	* Prepare parameters for vmsvgaGMRTransfer.
4144	*/
4145	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4146
4147	/* Destination: host buffer which describes the screen 0 VRAM.
4148	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4149	*/
4150	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4151	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4152	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4153	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4154	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4155	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4156	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4157	+ cbScanline * clipRect.top;
4158	int32_t const cbHstPitch = cbScanline;
4159
4160	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4161	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4162	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4163	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4164	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4165
4166	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4167	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4168	gstPtr, offGst, cbGstPitch,
4169	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4170	AssertRC(rc);
4171	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4172	break;
4173	}
4174
4175	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4176	{
4177	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4178	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4179	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4180
4181	/* Note! This can fetch 3d render results as well!! */
4182	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4183	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4184
4185	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4186	RT_UNTRUSTED_VALIDATED_FENCE();
4187
4188	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4189	AssertBreak(pScreen);
4190
4191	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4192	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4193
4194	/* Clip destRect to the screen dimensions. */
4195	SVGASignedRect screenRect;
4196	screenRect.left = 0;
4197	screenRect.top = 0;
4198	screenRect.right = pScreen->cWidth;
4199	screenRect.bottom = pScreen->cHeight;
4200	SVGASignedRect clipRect = pCmd->srcRect;
4201	vmsvgaClipRect(&screenRect, &clipRect);
4202	RT_UNTRUSTED_VALIDATED_FENCE();
4203
4204	uint32_t const width = clipRect.right - clipRect.left;
4205	uint32_t const height = clipRect.bottom - clipRect.top;
4206
4207	if ( width == 0
4208	\|\| height == 0)
4209	break; /* Nothing to do. */
4210
4211	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4212	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4213
4214	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4215	* Prepare parameters for vmsvgaGMRTransfer.
4216	*/
4217	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4218
4219	/* Source: host buffer which describes the screen 0 VRAM.
4220	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4221	*/
4222	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4223	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4224	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4225	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4226	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4227	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4228	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4229	+ cbScanline * clipRect.top;
4230	int32_t const cbHstPitch = cbScanline;
4231
4232	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4233	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4234	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4235	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4236	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4237
4238	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4239	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4240	gstPtr, offGst, cbGstPitch,
4241	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4242	AssertRC(rc);
4243	break;
4244	}
4245
4246	case SVGA_CMD_ANNOTATION_FILL:
4247	{
4248	SVGAFifoCmdAnnotationFill *pCmd;
4249	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4250	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4251
4252	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4253	pSVGAState->colorAnnotation = pCmd->color;
4254	break;
4255	}
4256
4257	case SVGA_CMD_ANNOTATION_COPY:
4258	{
4259	SVGAFifoCmdAnnotationCopy *pCmd;
4260	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4261	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4262
4263	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4264	AssertFailed();
4265	break;
4266	}
4267
4268	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4269
4270	default:
4271	# ifdef VBOX_WITH_VMSVGA3D
4272	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4273	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4274	{
4275	RT_UNTRUSTED_VALIDATED_FENCE();
4276
4277	/* All 3d commands start with a common header, which defines the size of the command. */
4278	SVGA3dCmdHeader *pHdr;
4279	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4280	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4281	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4282	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4283
4284	if (RT_LIKELY(pThis->svga.f3DEnabled))
4285	{ /* likely */ }
4286	else
4287	{
4288	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4289	break;
4290	}
4291
4292	/**
4293	* Check that the 3D command has at least a_cbMin of payload bytes after the
4294	* header. Will break out of the switch if it doesn't.
4295	*/
4296	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4297	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4298	RT_UNTRUSTED_VALIDATED_FENCE(); \
4299	} while (0)
4300	switch ((int)enmCmdId)
4301	{
4302	case SVGA_3D_CMD_SURFACE_DEFINE:
4303	{
4304	uint32_t cMipLevels;
4305	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4306	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4307	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4308
4309	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4310	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4311	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4312	# ifdef DEBUG_GMR_ACCESS
4313	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4314	# endif
4315	break;
4316	}
4317
4318	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4319	{
4320	uint32_t cMipLevels;
4321	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4322	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4323	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4324
4325	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4326	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4327	pCmd->multisampleCount, pCmd->autogenFilter,
4328	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4329	break;
4330	}
4331
4332	case SVGA_3D_CMD_SURFACE_DESTROY:
4333	{
4334	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4335	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4336	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4337	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4338	break;
4339	}
4340
4341	case SVGA_3D_CMD_SURFACE_COPY:
4342	{
4343	uint32_t cCopyBoxes;
4344	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4345	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4346	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4347
4348	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4349	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4350	break;
4351	}
4352
4353	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4354	{
4355	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4356	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4357	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4358
4359	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4360	break;
4361	}
4362
4363	case SVGA_3D_CMD_SURFACE_DMA:
4364	{
4365	uint32_t cCopyBoxes;
4366	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4367	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4368	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4369
4370	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4371	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4372	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4373	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4374	break;
4375	}
4376
4377	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4378	{
4379	uint32_t cRects;
4380	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4381	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4383
4384	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4385	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4386	break;
4387	}
4388
4389	case SVGA_3D_CMD_CONTEXT_DEFINE:
4390	{
4391	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4392	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4393	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4394
4395	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4396	break;
4397	}
4398
4399	case SVGA_3D_CMD_CONTEXT_DESTROY:
4400	{
4401	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4402	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4403	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4404
4405	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4406	break;
4407	}
4408
4409	case SVGA_3D_CMD_SETTRANSFORM:
4410	{
4411	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4412	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4413	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4414
4415	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4416	break;
4417	}
4418
4419	case SVGA_3D_CMD_SETZRANGE:
4420	{
4421	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4422	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4423	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4424
4425	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4426	break;
4427	}
4428
4429	case SVGA_3D_CMD_SETRENDERSTATE:
4430	{
4431	uint32_t cRenderStates;
4432	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4433	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4434	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4435
4436	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4437	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4438	break;
4439	}
4440
4441	case SVGA_3D_CMD_SETRENDERTARGET:
4442	{
4443	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4446
4447	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4448	break;
4449	}
4450
4451	case SVGA_3D_CMD_SETTEXTURESTATE:
4452	{
4453	uint32_t cTextureStates;
4454	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4455	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4456	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4457
4458	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4459	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4460	break;
4461	}
4462
4463	case SVGA_3D_CMD_SETMATERIAL:
4464	{
4465	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4466	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4467	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4468
4469	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4470	break;
4471	}
4472
4473	case SVGA_3D_CMD_SETLIGHTDATA:
4474	{
4475	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4476	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4477	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4478
4479	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4480	break;
4481	}
4482
4483	case SVGA_3D_CMD_SETLIGHTENABLED:
4484	{
4485	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4486	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4487	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4488
4489	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4490	break;
4491	}
4492
4493	case SVGA_3D_CMD_SETVIEWPORT:
4494	{
4495	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4496	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4497	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4498
4499	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4500	break;
4501	}
4502
4503	case SVGA_3D_CMD_SETCLIPPLANE:
4504	{
4505	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4506	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4507	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4508
4509	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4510	break;
4511	}
4512
4513	case SVGA_3D_CMD_CLEAR:
4514	{
4515	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4516	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4517	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4518
4519	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4520	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4521	break;
4522	}
4523
4524	case SVGA_3D_CMD_PRESENT:
4525	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4526	{
4527	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4528	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4530	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4531	else
4532	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4533
4534	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4535
4536	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4537	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4538	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4539	break;
4540	}
4541
4542	case SVGA_3D_CMD_SHADER_DEFINE:
4543	{
4544	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4545	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4546	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4547
4548	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4549	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4550	break;
4551	}
4552
4553	case SVGA_3D_CMD_SHADER_DESTROY:
4554	{
4555	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4556	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4557	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4558
4559	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4560	break;
4561	}
4562
4563	case SVGA_3D_CMD_SET_SHADER:
4564	{
4565	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4566	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4567	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4568
4569	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4570	break;
4571	}
4572
4573	case SVGA_3D_CMD_SET_SHADER_CONST:
4574	{
4575	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4576	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4578
4579	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4580	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4581	break;
4582	}
4583
4584	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4585	{
4586	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4587	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4588	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4589
4590	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4591	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4592	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4593	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4594	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4595
4596	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4597	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4598
4599	RT_UNTRUSTED_VALIDATED_FENCE();
4600
4601	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4602	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4603	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4604
4605	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4606	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4607	pNumRange, cVertexDivisor, pVertexDivisor);
4608	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4609	break;
4610	}
4611
4612	case SVGA_3D_CMD_SETSCISSORRECT:
4613	{
4614	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4615	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4616	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4617
4618	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4619	break;
4620	}
4621
4622	case SVGA_3D_CMD_BEGIN_QUERY:
4623	{
4624	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4625	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4626	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4627
4628	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4629	break;
4630	}
4631
4632	case SVGA_3D_CMD_END_QUERY:
4633	{
4634	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4635	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4637
4638	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4639	break;
4640	}
4641
4642	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4643	{
4644	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4645	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4646	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4647
4648	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4649	break;
4650	}
4651
4652	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4653	{
4654	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4655	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4656	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4657
4658	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4659	break;
4660	}
4661
4662	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4663	/* context id + surface id? */
4664	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4665	break;
4666	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4667	/* context id + surface id? */
4668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4669	break;
4670
4671	default:
4672	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4673	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4674	break;
4675	}
4676	}
4677	else
4678	# endif // VBOX_WITH_VMSVGA3D
4679	{
4680	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4681	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4682	}
4683	}
4684
4685	/* Go to the next slot */
4686	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4687	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4688	if (offCurrentCmd >= offFifoMax)
4689	{
4690	offCurrentCmd -= offFifoMax - offFifoMin;
4691	Assert(offCurrentCmd >= offFifoMin);
4692	Assert(offCurrentCmd < offFifoMax);
4693	}
4694	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4695	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4696
4697	/*
4698	* Raise IRQ if required. Must enter the critical section here
4699	* before making final decisions here, otherwise cubebench and
4700	* others may end up waiting forever.
4701	*/
4702	if ( u32IrqStatus
4703	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4704	{
4705	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4706	AssertRC(rc2);
4707
4708	/* FIFO progress might trigger an interrupt. */
4709	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4710	{
4711	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4712	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4713	}
4714
4715	/* Unmasked IRQ pending? */
4716	if (pThis->svga.u32IrqMask & u32IrqStatus)
4717	{
4718	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4719	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4720	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4721	}
4722
4723	PDMCritSectLeave(&pThis->CritSect);
4724	}
4725	}
4726
4727	/* If really done, clear the busy flag. */
4728	if (fDone)
4729	{
4730	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4731	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4732	}
4733	}
4734
4735	/*
4736	* Free the bounce buffer. (There are no returns above!)
4737	*/
4738	RTMemFree(pbBounceBuf);
4739
4740	return VINF_SUCCESS;
4741	}
4742
4743	/**
4744	* Free the specified GMR
4745	*
4746	* @param pThis VGA device instance data.
4747	* @param idGMR GMR id
4748	*/
4749	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4750	{
4751	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4752
4753	/* Free the old descriptor if present. */
4754	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4755	if ( pGMR->numDescriptors
4756	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4757	{
4758	# ifdef DEBUG_GMR_ACCESS
4759	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4760	# endif
4761
4762	Assert(pGMR->paDesc);
4763	RTMemFree(pGMR->paDesc);
4764	pGMR->paDesc = NULL;
4765	pGMR->numDescriptors = 0;
4766	pGMR->cbTotal = 0;
4767	pGMR->cMaxPages = 0;
4768	}
4769	Assert(!pGMR->cMaxPages);
4770	Assert(!pGMR->cbTotal);
4771	}
4772
4773	/**
4774	* Copy between a GMR and a host memory buffer.
4775	*
4776	* @returns VBox status code.
4777	* @param pThis VGA device instance data.
4778	* @param enmTransferType Transfer type (read/write)
4779	* @param pbHstBuf Host buffer pointer (valid)
4780	* @param cbHstBuf Size of host buffer (valid)
4781	* @param offHst Host buffer offset of the first scanline
4782	* @param cbHstPitch Destination buffer pitch
4783	* @param gstPtr GMR description
4784	* @param offGst Guest buffer offset of the first scanline
4785	* @param cbGstPitch Guest buffer pitch
4786	* @param cbWidth Width in bytes to copy
4787	* @param cHeight Number of scanllines to copy
4788	*/
4789	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4790	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4791	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4792	uint32_t cbWidth, uint32_t cHeight)
4793	{
4794	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4795	int rc;
4796
4797	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4798	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4799	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4800	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4801	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4802
4803	PGMR pGMR;
4804	uint32_t cbGmr; /* The GMR size in bytes. */
4805	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4806	{
4807	pGMR = NULL;
4808	cbGmr = pThis->vram_size;
4809	}
4810	else
4811	{
4812	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4813	RT_UNTRUSTED_VALIDATED_FENCE();
4814	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4815	cbGmr = pGMR->cbTotal;
4816	}
4817
4818	/*
4819	* GMR
4820	*/
4821	/* Calculate GMR offset of the data to be copied. */
4822	AssertMsgReturn(gstPtr.offset < cbGmr,
4823	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4824	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4825	VERR_INVALID_PARAMETER);
4826	RT_UNTRUSTED_VALIDATED_FENCE();
4827	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4828	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4829	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4830	VERR_INVALID_PARAMETER);
4831	RT_UNTRUSTED_VALIDATED_FENCE();
4832	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4833
4834	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4835	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4836	AssertMsgReturn(cbGmrScanline != 0,
4837	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4838	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4839	VERR_INVALID_PARAMETER);
4840	RT_UNTRUSTED_VALIDATED_FENCE();
4841	AssertMsgReturn(cbWidth <= cbGmrScanline,
4842	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4843	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4844	VERR_INVALID_PARAMETER);
4845	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4846	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4847	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4848	VERR_INVALID_PARAMETER);
4849	RT_UNTRUSTED_VALIDATED_FENCE();
4850
4851	/* How many bytes are available for the data in the GMR. */
4852	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4853
4854	/* How many scanlines would fit into the available data. */
4855	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4856	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4857	if (cbWidth <= cbGmrLastScanline)
4858	++cGmrScanlines;
4859
4860	if (cHeight > cGmrScanlines)
4861	cHeight = cGmrScanlines;
4862
4863	AssertMsgReturn(cHeight > 0,
4864	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4865	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4866	VERR_INVALID_PARAMETER);
4867	RT_UNTRUSTED_VALIDATED_FENCE();
4868
4869	/*
4870	* Host buffer.
4871	*/
4872	AssertMsgReturn(offHst < cbHstBuf,
4873	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4874	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4875	VERR_INVALID_PARAMETER);
4876
4877	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4878	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4879	AssertMsgReturn(cbHstScanline != 0,
4880	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4881	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4882	VERR_INVALID_PARAMETER);
4883	AssertMsgReturn(cbWidth <= cbHstScanline,
4884	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4885	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4886	VERR_INVALID_PARAMETER);
4887	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4888	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4889	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4890	VERR_INVALID_PARAMETER);
4891
4892	/* How many bytes are available for the data in the buffer. */
4893	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4894
4895	/* How many scanlines would fit into the available data. */
4896	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4897	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4898	if (cbWidth <= cbHstLastScanline)
4899	++cHstScanlines;
4900
4901	if (cHeight > cHstScanlines)
4902	cHeight = cHstScanlines;
4903
4904	AssertMsgReturn(cHeight > 0,
4905	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4906	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4907	VERR_INVALID_PARAMETER);
4908
4909	uint8_t *pbHst = pbHstBuf + offHst;
4910
4911	/* Shortcut for the framebuffer. */
4912	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4913	{
4914	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4915
4916	uint8_t const *pbSrc;
4917	int32_t cbSrcPitch;
4918	uint8_t *pbDst;
4919	int32_t cbDstPitch;
4920
4921	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4922	{
4923	pbSrc = pbHst;
4924	cbSrcPitch = cbHstPitch;
4925	pbDst = pbGst;
4926	cbDstPitch = cbGstPitch;
4927	}
4928	else
4929	{
4930	pbSrc = pbGst;
4931	cbSrcPitch = cbGstPitch;
4932	pbDst = pbHst;
4933	cbDstPitch = cbHstPitch;
4934	}
4935
4936	if ( cbWidth == (uint32_t)cbGstPitch
4937	&& cbGstPitch == cbHstPitch)
4938	{
4939	/* Entire scanlines, positive pitch. */
4940	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4941	}
4942	else
4943	{
4944	for (uint32_t i = 0; i < cHeight; ++i)
4945	{
4946	memcpy(pbDst, pbSrc, cbWidth);
4947
4948	pbDst += cbDstPitch;
4949	pbSrc += cbSrcPitch;
4950	}
4951	}
4952	return VINF_SUCCESS;
4953	}
4954
4955	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4956	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4957
4958	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4959	uint32_t iDesc = 0; /* Index in the descriptor array. */
4960	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4961	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4962	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4963	for (uint32_t i = 0; i < cHeight; ++i)
4964	{
4965	uint32_t cbCurrentWidth = cbWidth;
4966	uint32_t offGmrCurrent = offGmrScanline;
4967	uint8_t *pbCurrentHost = pbHstScanline;
4968
4969	/* Find the right descriptor */
4970	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4971	{
4972	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4973	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4974	++iDesc;
4975	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4976	}
4977
4978	while (cbCurrentWidth)
4979	{
4980	uint32_t cbToCopy;
4981
4982	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4983	{
4984	cbToCopy = cbCurrentWidth;
4985	}
4986	else
4987	{
4988	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
4989	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
4990	}
4991
4992	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
4993
4994	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
4995
4996	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
4997	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
4998	else
4999	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5000	AssertRCBreak(rc);
5001
5002	cbCurrentWidth -= cbToCopy;
5003	offGmrCurrent += cbToCopy;
5004	pbCurrentHost += cbToCopy;
5005
5006	/* Go to the next descriptor if there's anything left. */
5007	if (cbCurrentWidth)
5008	{
5009	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5010	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5011	++iDesc;
5012	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5013	}
5014	}
5015
5016	offGmrScanline += cbGstPitch;
5017	pbHstScanline += cbHstPitch;
5018	}
5019
5020	return VINF_SUCCESS;
5021	}
5022
5023
5024	/**
5025	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5026	*
5027	* @param pSizeSrc Source surface dimensions.
5028	* @param pSizeDest Destination surface dimensions.
5029	* @param pBox Coordinates to be clipped.
5030	*/
5031	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5032	const SVGA3dSize *pSizeDest,
5033	SVGA3dCopyBox *pBox)
5034	{
5035	/* Src x, w */
5036	if (pBox->srcx > pSizeSrc->width)
5037	pBox->srcx = pSizeSrc->width;
5038	if (pBox->w > pSizeSrc->width - pBox->srcx)
5039	pBox->w = pSizeSrc->width - pBox->srcx;
5040
5041	/* Src y, h */
5042	if (pBox->srcy > pSizeSrc->height)
5043	pBox->srcy = pSizeSrc->height;
5044	if (pBox->h > pSizeSrc->height - pBox->srcy)
5045	pBox->h = pSizeSrc->height - pBox->srcy;
5046
5047	/* Src z, d */
5048	if (pBox->srcz > pSizeSrc->depth)
5049	pBox->srcz = pSizeSrc->depth;
5050	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5051	pBox->d = pSizeSrc->depth - pBox->srcz;
5052
5053	/* Dest x, w */
5054	if (pBox->x > pSizeDest->width)
5055	pBox->x = pSizeDest->width;
5056	if (pBox->w > pSizeDest->width - pBox->x)
5057	pBox->w = pSizeDest->width - pBox->x;
5058
5059	/* Dest y, h */
5060	if (pBox->y > pSizeDest->height)
5061	pBox->y = pSizeDest->height;
5062	if (pBox->h > pSizeDest->height - pBox->y)
5063	pBox->h = pSizeDest->height - pBox->y;
5064
5065	/* Dest z, d */
5066	if (pBox->z > pSizeDest->depth)
5067	pBox->z = pSizeDest->depth;
5068	if (pBox->d > pSizeDest->depth - pBox->z)
5069	pBox->d = pSizeDest->depth - pBox->z;
5070	}
5071
5072	/**
5073	* Unsigned coordinates in pBox. Clip to [0; pSize).
5074	*
5075	* @param pSize Source surface dimensions.
5076	* @param pBox Coordinates to be clipped.
5077	*/
5078	void vmsvgaClipBox(const SVGA3dSize *pSize,
5079	SVGA3dBox *pBox)
5080	{
5081	/* x, w */
5082	if (pBox->x > pSize->width)
5083	pBox->x = pSize->width;
5084	if (pBox->w > pSize->width - pBox->x)
5085	pBox->w = pSize->width - pBox->x;
5086
5087	/* y, h */
5088	if (pBox->y > pSize->height)
5089	pBox->y = pSize->height;
5090	if (pBox->h > pSize->height - pBox->y)
5091	pBox->h = pSize->height - pBox->y;
5092
5093	/* z, d */
5094	if (pBox->z > pSize->depth)
5095	pBox->z = pSize->depth;
5096	if (pBox->d > pSize->depth - pBox->z)
5097	pBox->d = pSize->depth - pBox->z;
5098	}
5099
5100	/**
5101	* Clip.
5102	*
5103	* @param pBound Bounding rectangle.
5104	* @param pRect Rectangle to be clipped.
5105	*/
5106	void vmsvgaClipRect(SVGASignedRect const *pBound,
5107	SVGASignedRect *pRect)
5108	{
5109	int32_t left;
5110	int32_t top;
5111	int32_t right;
5112	int32_t bottom;
5113
5114	/* Right order. */
5115	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5116	if (pRect->left < pRect->right)
5117	{
5118	left = pRect->left;
5119	right = pRect->right;
5120	}
5121	else
5122	{
5123	left = pRect->right;
5124	right = pRect->left;
5125	}
5126	if (pRect->top < pRect->bottom)
5127	{
5128	top = pRect->top;
5129	bottom = pRect->bottom;
5130	}
5131	else
5132	{
5133	top = pRect->bottom;
5134	bottom = pRect->top;
5135	}
5136
5137	if (left < pBound->left)
5138	left = pBound->left;
5139	if (right < pBound->left)
5140	right = pBound->left;
5141
5142	if (left > pBound->right)
5143	left = pBound->right;
5144	if (right > pBound->right)
5145	right = pBound->right;
5146
5147	if (top < pBound->top)
5148	top = pBound->top;
5149	if (bottom < pBound->top)
5150	bottom = pBound->top;
5151
5152	if (top > pBound->bottom)
5153	top = pBound->bottom;
5154	if (bottom > pBound->bottom)
5155	bottom = pBound->bottom;
5156
5157	pRect->left = left;
5158	pRect->right = right;
5159	pRect->top = top;
5160	pRect->bottom = bottom;
5161	}
5162
5163	/**
5164	* Unblock the FIFO I/O thread so it can respond to a state change.
5165	*
5166	* @returns VBox status code.
5167	* @param pDevIns The VGA device instance.
5168	* @param pThread The send thread.
5169	*/
5170	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5171	{
5172	RT_NOREF(pDevIns);
5173	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5174	Log(("vmsvgaFIFOLoopWakeUp\n"));
5175	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5176	}
5177
5178	/**
5179	* Enables or disables dirty page tracking for the framebuffer
5180	*
5181	* @param pThis VGA device instance data.
5182	* @param fTraces Enable/disable traces
5183	*/
5184	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5185	{
5186	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5187	&& !fTraces)
5188	{
5189	//Assert(pThis->svga.fTraces);
5190	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5191	return;
5192	}
5193
5194	pThis->svga.fTraces = fTraces;
5195	if (pThis->svga.fTraces)
5196	{
5197	unsigned cbFrameBuffer = pThis->vram_size;
5198
5199	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5200	/** @todo How does this work with screens? */
5201	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5202	{
5203	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5204	Assert(pThis->svga.cbScanline);
5205	#endif
5206	/* Hardware enabled; return real framebuffer size .*/
5207	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5208	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5209	}
5210
5211	if (!pThis->svga.fVRAMTracking)
5212	{
5213	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5214	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5215	pThis->svga.fVRAMTracking = true;
5216	}
5217	}
5218	else
5219	{
5220	if (pThis->svga.fVRAMTracking)
5221	{
5222	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5223	vgaR3UnregisterVRAMHandler(pThis);
5224	pThis->svga.fVRAMTracking = false;
5225	}
5226	}
5227	}
5228
5229	/**
5230	* @callback_method_impl{FNPCIIOREGIONMAP}
5231	*/
5232	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5233	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5234	{
5235	int rc;
5236	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5237
5238	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5239	if (enmType == PCI_ADDRESS_SPACE_IO)
5240	{
5241	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5242	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5243	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5244	if (RT_FAILURE(rc))
5245	return rc;
5246	if (pThis->fR0Enabled)
5247	{
5248	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5249	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5250	if (RT_FAILURE(rc))
5251	return rc;
5252	}
5253	if (pThis->fGCEnabled)
5254	{
5255	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5256	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5257	if (RT_FAILURE(rc))
5258	return rc;
5259	}
5260
5261	pThis->svga.BasePort = GCPhysAddress;
5262	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5263	}
5264	else
5265	{
5266	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5267	if (GCPhysAddress != NIL_RTGCPHYS)
5268	{
5269	/*
5270	* Mapping the FIFO RAM.
5271	*/
5272	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5273	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5274	AssertRC(rc);
5275
5276	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5277	if (RT_SUCCESS(rc))
5278	{
5279	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5280	# ifdef DEBUG_FIFO_ACCESS
5281	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5282	# else
5283	GCPhysAddress + PAGE_SIZE - 1,
5284	# endif
5285	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5286	"VMSVGA FIFO");
5287	AssertRC(rc);
5288	}
5289	# endif
5290	if (RT_SUCCESS(rc))
5291	{
5292	pThis->svga.GCPhysFIFO = GCPhysAddress;
5293	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5294	}
5295	}
5296	else
5297	{
5298	Assert(pThis->svga.GCPhysFIFO);
5299	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5300	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5301	AssertRC(rc);
5302	# endif
5303	pThis->svga.GCPhysFIFO = 0;
5304	}
5305	}
5306	return VINF_SUCCESS;
5307	}
5308
5309	# ifdef VBOX_WITH_VMSVGA3D
5310
5311	/**
5312	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5313	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5314	*
5315	* @param pThis The VGA device instance data.
5316	* @param sid Either UINT32_MAX or the ID of a specific
5317	* surface. If UINT32_MAX is used, all surfaces
5318	* are processed.
5319	*/
5320	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5321	{
5322	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5323	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5324	}
5325
5326
5327	/**
5328	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5329	*/
5330	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5331	{
5332	/* There might be a specific surface ID at the start of the
5333	arguments, if not show all surfaces. */
5334	uint32_t sid = UINT32_MAX;
5335	if (pszArgs)
5336	pszArgs = RTStrStripL(pszArgs);
5337	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5338	sid = RTStrToUInt32(pszArgs);
5339
5340	/* Verbose or terse display, we default to verbose. */
5341	bool fVerbose = true;
5342	if (RTStrIStr(pszArgs, "terse"))
5343	fVerbose = false;
5344
5345	/* The size of the ascii art (x direction, y is 3/4 of x). */
5346	uint32_t cxAscii = 80;
5347	if (RTStrIStr(pszArgs, "gigantic"))
5348	cxAscii = 300;
5349	else if (RTStrIStr(pszArgs, "huge"))
5350	cxAscii = 180;
5351	else if (RTStrIStr(pszArgs, "big"))
5352	cxAscii = 132;
5353	else if (RTStrIStr(pszArgs, "normal"))
5354	cxAscii = 80;
5355	else if (RTStrIStr(pszArgs, "medium"))
5356	cxAscii = 64;
5357	else if (RTStrIStr(pszArgs, "small"))
5358	cxAscii = 48;
5359	else if (RTStrIStr(pszArgs, "tiny"))
5360	cxAscii = 24;
5361
5362	/* Y invert the image when producing the ASCII art. */
5363	bool fInvY = false;
5364	if (RTStrIStr(pszArgs, "invy"))
5365	fInvY = true;
5366
5367	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5368	}
5369
5370
5371	/**
5372	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5373	*/
5374	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5375	{
5376	/* pszArg = "sid[>dir]"
5377	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5378	*/
5379	char *pszBitmapPath = NULL;
5380	uint32_t sid = UINT32_MAX;
5381	if (pszArgs)
5382	pszArgs = RTStrStripL(pszArgs);
5383	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5384	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5385	if ( pszBitmapPath
5386	&& *pszBitmapPath == '>')
5387	++pszBitmapPath;
5388
5389	const bool fVerbose = true;
5390	const uint32_t cxAscii = 0; /* No ASCII */
5391	const bool fInvY = false; /* Do not invert. */
5392	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5393	}
5394
5395
5396	/**
5397	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5398	*/
5399	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5400	{
5401	/* There might be a specific surface ID at the start of the
5402	arguments, if not show all contexts. */
5403	uint32_t sid = UINT32_MAX;
5404	if (pszArgs)
5405	pszArgs = RTStrStripL(pszArgs);
5406	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5407	sid = RTStrToUInt32(pszArgs);
5408
5409	/* Verbose or terse display, we default to verbose. */
5410	bool fVerbose = true;
5411	if (RTStrIStr(pszArgs, "terse"))
5412	fVerbose = false;
5413
5414	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5415	}
5416
5417	# endif /* VBOX_WITH_VMSVGA3D */
5418
5419	/**
5420	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5421	*/
5422	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5423	{
5424	RT_NOREF(pszArgs);
5425	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5426	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5427
5428	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5429	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5430	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5431	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5432	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5433	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5434	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5435	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5436	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5437	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5438	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5439	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5440	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
5441	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5442	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5443	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5444	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5445	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5446	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5447	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5448	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5449	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5450
5451	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5452	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5453	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5454	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5455
5456	# ifdef VBOX_WITH_VMSVGA3D
5457	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5458	# endif
5459	}
5460
5461	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5462	*/
5463	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5464	{
5465	RT_NOREF(uPass);
5466
5467	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5468	int rc;
5469
5470	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5471	{
5472	uint32_t cScreens = 0;
5473	rc = SSMR3GetU32(pSSM, &cScreens);
5474	AssertRCReturn(rc, rc);
5475	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5476	("cScreens=%#x\n", cScreens),
5477	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5478
5479	for (uint32_t i = 0; i < cScreens; ++i)
5480	{
5481	VMSVGASCREENOBJECT screen;
5482	RT_ZERO(screen);
5483
5484	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5485	AssertLogRelRCReturn(rc, rc);
5486
5487	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5488	{
5489	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5490	*pScreen = screen;
5491	pScreen->fModified = true;
5492	}
5493	else
5494	{
5495	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5496	}
5497	}
5498	}
5499	else
5500	{
5501	/* Try to setup at least the first screen. */
5502	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5503	pScreen->fDefined = true;
5504	pScreen->fModified = true;
5505	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5506	pScreen->idScreen = 0;
5507	pScreen->xOrigin = 0;
5508	pScreen->yOrigin = 0;
5509	pScreen->offVRAM = pThis->svga.uScreenOffset;
5510	pScreen->cbPitch = pThis->svga.cbScanline;
5511	pScreen->cWidth = pThis->svga.uWidth;
5512	pScreen->cHeight = pThis->svga.uHeight;
5513	pScreen->cBpp = pThis->svga.uBpp;
5514	}
5515
5516	return VINF_SUCCESS;
5517	}
5518
5519	/**
5520	* @copydoc FNSSMDEVLOADEXEC
5521	*/
5522	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5523	{
5524	RT_NOREF(uPass);
5525	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5526	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5527	int rc;
5528
5529	/* Load our part of the VGAState */
5530	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5531	AssertRCReturn(rc, rc);
5532
5533	/* Load the VGA framebuffer. */
5534	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5535	uint32_t cbVgaFramebuffer = _32K;
5536	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5537	{
5538	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5539	AssertRCReturn(rc, rc);
5540	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5541	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5542	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5543	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5544	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5545	}
5546	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5547	AssertRCReturn(rc, rc);
5548	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5549	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5550	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5551	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5552
5553	/* Load the VMSVGA state. */
5554	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5555	AssertRCReturn(rc, rc);
5556
5557	/* Load the active cursor bitmaps. */
5558	if (pSVGAState->Cursor.fActive)
5559	{
5560	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5561	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5562
5563	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5564	AssertRCReturn(rc, rc);
5565	}
5566
5567	/* Load the GMR state. */
5568	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5569	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5570	{
5571	rc = SSMR3GetU32(pSSM, &cGMR);
5572	AssertRCReturn(rc, rc);
5573	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5574	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5575	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5576	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5577	}
5578
5579	if (pThis->svga.cGMR != cGMR)
5580	{
5581	/* Reallocate GMR array. */
5582	Assert(pSVGAState->paGMR != NULL);
5583	RTMemFree(pSVGAState->paGMR);
5584	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5585	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5586	pThis->svga.cGMR = cGMR;
5587	}
5588
5589	for (uint32_t i = 0; i < cGMR; ++i)
5590	{
5591	PGMR pGMR = &pSVGAState->paGMR[i];
5592
5593	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5594	AssertRCReturn(rc, rc);
5595
5596	if (pGMR->numDescriptors)
5597	{
5598	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5599	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5600	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5601
5602	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5603	{
5604	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5605	AssertRCReturn(rc, rc);
5606	}
5607	}
5608	}
5609
5610	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5611	vmsvga3dPowerOn(pThis);
5612	# endif
5613
5614	VMSVGA_STATE_LOAD LoadState;
5615	LoadState.pSSM = pSSM;
5616	LoadState.uVersion = uVersion;
5617	LoadState.uPass = uPass;
5618	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5619	AssertLogRelRCReturn(rc, rc);
5620
5621	return VINF_SUCCESS;
5622	}
5623
5624	/**
5625	* Reinit the video mode after the state has been loaded.
5626	*/
5627	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5628	{
5629	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5630	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5631
5632	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5633
5634	/* Set the active cursor. */
5635	if (pSVGAState->Cursor.fActive)
5636	{
5637	int rc;
5638
5639	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5640	true,
5641	true,
5642	pSVGAState->Cursor.xHotspot,
5643	pSVGAState->Cursor.yHotspot,
5644	pSVGAState->Cursor.width,
5645	pSVGAState->Cursor.height,
5646	pSVGAState->Cursor.pData);
5647	AssertRC(rc);
5648	}
5649	return VINF_SUCCESS;
5650	}
5651
5652	/**
5653	* Portion of SVGA state which must be saved in the FIFO thread.
5654	*/
5655	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5656	{
5657	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5658	int rc;
5659
5660	/* Save the screen objects. */
5661	/* Count defined screen object. */
5662	uint32_t cScreens = 0;
5663	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5664	{
5665	if (pSVGAState->aScreens[i].fDefined)
5666	++cScreens;
5667	}
5668
5669	rc = SSMR3PutU32(pSSM, cScreens);
5670	AssertLogRelRCReturn(rc, rc);
5671
5672	for (uint32_t i = 0; i < cScreens; ++i)
5673	{
5674	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5675
5676	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5677	AssertLogRelRCReturn(rc, rc);
5678	}
5679	return VINF_SUCCESS;
5680	}
5681
5682	/**
5683	* @copydoc FNSSMDEVSAVEEXEC
5684	*/
5685	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5686	{
5687	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5688	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5689	int rc;
5690
5691	/* Save our part of the VGAState */
5692	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5693	AssertLogRelRCReturn(rc, rc);
5694
5695	/* Save the framebuffer backup. */
5696	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5697	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5698	AssertLogRelRCReturn(rc, rc);
5699
5700	/* Save the VMSVGA state. */
5701	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5702	AssertLogRelRCReturn(rc, rc);
5703
5704	/* Save the active cursor bitmaps. */
5705	if (pSVGAState->Cursor.fActive)
5706	{
5707	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5708	AssertLogRelRCReturn(rc, rc);
5709	}
5710
5711	/* Save the GMR state */
5712	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5713	AssertLogRelRCReturn(rc, rc);
5714	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5715	{
5716	PGMR pGMR = &pSVGAState->paGMR[i];
5717
5718	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5719	AssertLogRelRCReturn(rc, rc);
5720
5721	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5722	{
5723	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5724	AssertLogRelRCReturn(rc, rc);
5725	}
5726	}
5727
5728	/*
5729	* Must save some state (3D in particular) in the FIFO thread.
5730	*/
5731	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5732	AssertLogRelRCReturn(rc, rc);
5733
5734	return VINF_SUCCESS;
5735	}
5736
5737	/**
5738	* Destructor for PVMSVGAR3STATE structure.
5739	*
5740	* @param pThis The VGA instance.
5741	* @param pSVGAState Pointer to the structure. It is not deallocated.
5742	*/
5743	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5744	{
5745	#ifndef VMSVGA_USE_EMT_HALT_CODE
5746	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5747	{
5748	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5749	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5750	}
5751	#endif
5752
5753	if (pSVGAState->Cursor.fActive)
5754	{
5755	RTMemFree(pSVGAState->Cursor.pData);
5756	pSVGAState->Cursor.pData = NULL;
5757	pSVGAState->Cursor.fActive = false;
5758	}
5759
5760	if (pSVGAState->paGMR)
5761	{
5762	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5763	if (pSVGAState->paGMR[i].paDesc)
5764	RTMemFree(pSVGAState->paGMR[i].paDesc);
5765
5766	RTMemFree(pSVGAState->paGMR);
5767	pSVGAState->paGMR = NULL;
5768	}
5769	}
5770
5771	/**
5772	* Constructor for PVMSVGAR3STATE structure.
5773	*
5774	* @returns VBox status code.
5775	* @param pThis The VGA instance.
5776	* @param pSVGAState Pointer to the structure. It is already allocated.
5777	*/
5778	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5779	{
5780	int rc = VINF_SUCCESS;
5781	RT_ZERO(*pSVGAState);
5782
5783	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5784	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5785
5786	#ifndef VMSVGA_USE_EMT_HALT_CODE
5787	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5788	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5789	AssertRCReturn(rc, rc);
5790	#endif
5791
5792	return rc;
5793	}
5794
5795	/**
5796	* Resets the SVGA hardware state
5797	*
5798	* @returns VBox status code.
5799	* @param pDevIns The device instance.
5800	*/
5801	int vmsvgaReset(PPDMDEVINS pDevIns)
5802	{
5803	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5804	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5805
5806	/* Reset before init? */
5807	if (!pSVGAState)
5808	return VINF_SUCCESS;
5809
5810	Log(("vmsvgaReset\n"));
5811
5812	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5813	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5814	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5815
5816	/* Reset other stuff. */
5817	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5818	RT_ZERO(pThis->svga.au32ScratchRegion);
5819
5820	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5821	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5822
5823	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5824
5825	/* Register caps. */
5826	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5827	# ifdef VBOX_WITH_VMSVGA3D
5828	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5829	# endif
5830
5831	/* Setup FIFO capabilities. */
5832	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5833
5834	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5835	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5836
5837	/* VRAM tracking is enabled by default during bootup. */
5838	pThis->svga.fVRAMTracking = true;
5839	pThis->svga.fEnabled = false;
5840
5841	/* Invalidate current settings. */
5842	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5843	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5844	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5845	pThis->svga.cbScanline = 0;
5846
5847	return rc;
5848	}
5849
5850	/**
5851	* Cleans up the SVGA hardware state
5852	*
5853	* @returns VBox status code.
5854	* @param pDevIns The device instance.
5855	*/
5856	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5857	{
5858	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5859
5860	/*
5861	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5862	*/
5863	if (pThis->svga.pFIFOIOThread)
5864	{
5865	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5866	AssertLogRelRC(rc);
5867
5868	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5869	AssertLogRelRC(rc);
5870	pThis->svga.pFIFOIOThread = NULL;
5871	}
5872
5873	/*
5874	* Destroy the special SVGA state.
5875	*/
5876	if (pThis->svga.pSvgaR3State)
5877	{
5878	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5879
5880	RTMemFree(pThis->svga.pSvgaR3State);
5881	pThis->svga.pSvgaR3State = NULL;
5882	}
5883
5884	/*
5885	* Free our resources residing in the VGA state.
5886	*/
5887	if (pThis->svga.pbVgaFrameBufferR3)
5888	{
5889	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5890	pThis->svga.pbVgaFrameBufferR3 = NULL;
5891	}
5892	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5893	{
5894	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5895	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5896	}
5897	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5898	{
5899	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5900	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5901	}
5902
5903	return VINF_SUCCESS;
5904	}
5905
5906	/**
5907	* Initialize the SVGA hardware state
5908	*
5909	* @returns VBox status code.
5910	* @param pDevIns The device instance.
5911	*/
5912	int vmsvgaInit(PPDMDEVINS pDevIns)
5913	{
5914	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5915	PVMSVGAR3STATE pSVGAState;
5916	PVM pVM = PDMDevHlpGetVM(pDevIns);
5917	int rc;
5918
5919	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5920	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5921
5922	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5923
5924	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5925	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5926	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5927
5928	/* Create event semaphore. */
5929	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5930
5931	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5932	if (RT_FAILURE(rc))
5933	{
5934	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
5935	return rc;
5936	}
5937
5938	/* Create event semaphore. */
5939	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
5940	if (RT_FAILURE(rc))
5941	{
5942	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
5943	return rc;
5944	}
5945
5946	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
5947	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
5948
5949	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5950	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5951
5952	pSVGAState = pThis->svga.pSvgaR3State;
5953
5954	/* Register caps. */
5955	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5956	# ifdef VBOX_WITH_VMSVGA3D
5957	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5958	# endif
5959
5960	/* Setup FIFO capabilities. */
5961	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5962
5963	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5964	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5965
5966	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
5967	# ifdef VBOX_WITH_VMSVGA3D
5968	if (pThis->svga.f3DEnabled)
5969	{
5970	rc = vmsvga3dInit(pThis);
5971	if (RT_FAILURE(rc))
5972	{
5973	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5974	pThis->svga.f3DEnabled = false;
5975	}
5976	}
5977	# endif
5978	/* VRAM tracking is enabled by default during bootup. */
5979	pThis->svga.fVRAMTracking = true;
5980
5981	/* Invalidate current settings. */
5982	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5983	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5984	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5985	pThis->svga.cbScanline = 0;
5986
5987	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
5988	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
5989	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
5990	{
5991	pThis->svga.u32MaxWidth -= 256;
5992	pThis->svga.u32MaxHeight -= 256;
5993	}
5994	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
5995
5996	# ifdef DEBUG_GMR_ACCESS
5997	/* Register the GMR access handler type. */
5998	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
5999	vmsvgaR3GMRAccessHandler,
6000	NULL, NULL, NULL,
6001	NULL, NULL, NULL,
6002	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6003	AssertRCReturn(rc, rc);
6004	# endif
6005
6006	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6007	/* Register the FIFO access handler type. In addition to
6008	debugging FIFO access, this is also used to facilitate
6009	extended fifo thread sleeps. */
6010	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6011	# ifdef DEBUG_FIFO_ACCESS
6012	PGMPHYSHANDLERKIND_ALL,
6013	# else
6014	PGMPHYSHANDLERKIND_WRITE,
6015	# endif
6016	vmsvgaR3FIFOAccessHandler,
6017	NULL, NULL, NULL,
6018	NULL, NULL, NULL,
6019	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6020	AssertRCReturn(rc, rc);
6021	# endif
6022
6023	/* Create the async IO thread. */
6024	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6025	RTTHREADTYPE_IO, "VMSVGA FIFO");
6026	if (RT_FAILURE(rc))
6027	{
6028	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6029	return rc;
6030	}
6031
6032	/*
6033	* Statistics.
6034	*/
6035	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6036	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6037	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6038	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6039	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6040	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6041	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6042	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6043	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6044	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6045	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6046	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6047	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6048	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6049	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6050	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6051	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6052	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6053	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6054	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6055	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6056	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6057	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6058	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6059	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6060	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6061	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6062	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6063	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6064	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6065	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6066	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6067	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6068	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6069	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6070	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6071	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6072	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6073	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6074	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6075	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6076	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6077	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6078	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6079	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6080	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6081	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6082	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6083	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6084	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6085	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6086	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6087	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6088	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6089	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6090	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6091
6092	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6093	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6094	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6095	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6096	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6097	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6098	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6099	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6100	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6101	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6102	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6103	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6104	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6105	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6106	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6107	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6108	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6109	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6110	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6111	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6112	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6113	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6114	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6115	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6116	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6117	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6118	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6119	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6120	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6121	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6122	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6123	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6124
6125	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6126	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6127	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6128	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6129	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6130	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6131	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6132	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6133	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6134	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6135	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6136	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6137	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6138	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6139	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6140	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6141	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6142	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6143	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6144	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6145	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6146	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6147	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6148	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6149	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6150	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6151	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6152	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6153	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6154	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6155	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6156	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6157	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6158	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6159	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6160	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6161	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6162	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6163	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6164	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6165	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6166	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6167	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6168	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6169	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6170	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6171	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6172	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6173	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6174
6175	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6176	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6177	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6178	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6179	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6180	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6181	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6182	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6183	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6184	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6185	# endif
6186	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6187	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6188	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6189	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6190	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6191
6192	/*
6193	* Info handlers.
6194	*/
6195	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6196	# ifdef VBOX_WITH_VMSVGA3D
6197	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6198	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6199	"VMSVGA 3d surface details. "
6200	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6201	vmsvgaR3Info3dSurface);
6202	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6203	"VMSVGA 3d surface details and bitmap: "
6204	"sid[>dir]",
6205	vmsvgaR3Info3dSurfaceBmp);
6206	# endif
6207
6208	return VINF_SUCCESS;
6209	}
6210
6211	# ifdef VBOX_WITH_VMSVGA3D
6212	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6213	static const char * const g_apszVmSvgaDevCapNames[] =
6214	{
6215	"x3D", /* = 0 */
6216	"xMAX_LIGHTS",
6217	"xMAX_TEXTURES",
6218	"xMAX_CLIP_PLANES",
6219	"xVERTEX_SHADER_VERSION",
6220	"xVERTEX_SHADER",
6221	"xFRAGMENT_SHADER_VERSION",
6222	"xFRAGMENT_SHADER",
6223	"xMAX_RENDER_TARGETS",
6224	"xS23E8_TEXTURES",
6225	"xS10E5_TEXTURES",
6226	"xMAX_FIXED_VERTEXBLEND",
6227	"xD16_BUFFER_FORMAT",
6228	"xD24S8_BUFFER_FORMAT",
6229	"xD24X8_BUFFER_FORMAT",
6230	"xQUERY_TYPES",
6231	"xTEXTURE_GRADIENT_SAMPLING",
6232	"rMAX_POINT_SIZE",
6233	"xMAX_SHADER_TEXTURES",
6234	"xMAX_TEXTURE_WIDTH",
6235	"xMAX_TEXTURE_HEIGHT",
6236	"xMAX_VOLUME_EXTENT",
6237	"xMAX_TEXTURE_REPEAT",
6238	"xMAX_TEXTURE_ASPECT_RATIO",
6239	"xMAX_TEXTURE_ANISOTROPY",
6240	"xMAX_PRIMITIVE_COUNT",
6241	"xMAX_VERTEX_INDEX",
6242	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6243	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6244	"xMAX_VERTEX_SHADER_TEMPS",
6245	"xMAX_FRAGMENT_SHADER_TEMPS",
6246	"xTEXTURE_OPS",
6247	"xSURFACEFMT_X8R8G8B8",
6248	"xSURFACEFMT_A8R8G8B8",
6249	"xSURFACEFMT_A2R10G10B10",
6250	"xSURFACEFMT_X1R5G5B5",
6251	"xSURFACEFMT_A1R5G5B5",
6252	"xSURFACEFMT_A4R4G4B4",
6253	"xSURFACEFMT_R5G6B5",
6254	"xSURFACEFMT_LUMINANCE16",
6255	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6256	"xSURFACEFMT_ALPHA8",
6257	"xSURFACEFMT_LUMINANCE8",
6258	"xSURFACEFMT_Z_D16",
6259	"xSURFACEFMT_Z_D24S8",
6260	"xSURFACEFMT_Z_D24X8",
6261	"xSURFACEFMT_DXT1",
6262	"xSURFACEFMT_DXT2",
6263	"xSURFACEFMT_DXT3",
6264	"xSURFACEFMT_DXT4",
6265	"xSURFACEFMT_DXT5",
6266	"xSURFACEFMT_BUMPX8L8V8U8",
6267	"xSURFACEFMT_A2W10V10U10",
6268	"xSURFACEFMT_BUMPU8V8",
6269	"xSURFACEFMT_Q8W8V8U8",
6270	"xSURFACEFMT_CxV8U8",
6271	"xSURFACEFMT_R_S10E5",
6272	"xSURFACEFMT_R_S23E8",
6273	"xSURFACEFMT_RG_S10E5",
6274	"xSURFACEFMT_RG_S23E8",
6275	"xSURFACEFMT_ARGB_S10E5",
6276	"xSURFACEFMT_ARGB_S23E8",
6277	"xMISSING62",
6278	"xMAX_VERTEX_SHADER_TEXTURES",
6279	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6280	"xSURFACEFMT_V16U16",
6281	"xSURFACEFMT_G16R16",
6282	"xSURFACEFMT_A16B16G16R16",
6283	"xSURFACEFMT_UYVY",
6284	"xSURFACEFMT_YUY2",
6285	"xMULTISAMPLE_NONMASKABLESAMPLES",
6286	"xMULTISAMPLE_MASKABLESAMPLES",
6287	"xALPHATOCOVERAGE",
6288	"xSUPERSAMPLE",
6289	"xAUTOGENMIPMAPS",
6290	"xSURFACEFMT_NV12",
6291	"xSURFACEFMT_AYUV",
6292	"xMAX_CONTEXT_IDS",
6293	"xMAX_SURFACE_IDS",
6294	"xSURFACEFMT_Z_DF16",
6295	"xSURFACEFMT_Z_DF24",
6296	"xSURFACEFMT_Z_D24S8_INT",
6297	"xSURFACEFMT_BC4_UNORM",
6298	"xSURFACEFMT_BC5_UNORM", /* 83 */
6299	};
6300	# endif
6301
6302
6303	/**
6304	* Power On notification.
6305	*
6306	* @returns VBox status code.
6307	* @param pDevIns The device instance data.
6308	*
6309	* @remarks Caller enters the device critical section.
6310	*/
6311	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6312	{
6313	# ifdef VBOX_WITH_VMSVGA3D
6314	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6315	if (pThis->svga.f3DEnabled)
6316	{
6317	int rc = vmsvga3dPowerOn(pThis);
6318
6319	if (RT_SUCCESS(rc))
6320	{
6321	bool fSavedBuffering = RTLogRelSetBuffering(true);
6322	SVGA3dCapsRecord *pCaps;
6323	SVGA3dCapPair *pData;
6324	uint32_t idxCap = 0;
6325
6326	/* 3d hardware version; latest and greatest */
6327	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6328	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6329
6330	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6331	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6332	pData = (SVGA3dCapPair *)&pCaps->data;
6333
6334	/* Fill out all 3d capabilities. */
6335	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6336	{
6337	uint32_t val = 0;
6338
6339	rc = vmsvga3dQueryCaps(pThis, i, &val);
6340	if (RT_SUCCESS(rc))
6341	{
6342	pData[idxCap][0] = i;
6343	pData[idxCap][1] = val;
6344	idxCap++;
6345	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6346	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6347	else
6348	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6349	&g_apszVmSvgaDevCapNames[i][1]));
6350	}
6351	else
6352	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6353	}
6354	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6355	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6356
6357	/* Mark end of record array. */
6358	pCaps->header.length = 0;
6359
6360	RTLogRelSetBuffering(fSavedBuffering);
6361	}
6362	}
6363	# else /* !VBOX_WITH_VMSVGA3D */
6364	RT_NOREF(pDevIns);
6365	# endif /* !VBOX_WITH_VMSVGA3D */
6366	}
6367
6368	#endif /* IN_RING3 */
6369

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 77914

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