DevVGA-SVGA.cpp@ 81754

Last change on this file since 81754 was 81754, checked in by vboxsync, 5 years ago
Devices/Graphics: suppress noisy logging.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 293.2 KB

Line
1	/* $Id: DevVGA-SVGA.cpp 81754 2019-11-10 19:14:26Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
522	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
526	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
528	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
529	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
530	SSMFIELD_ENTRY( VMSVGAState, uWidth),
531	SSMFIELD_ENTRY( VMSVGAState, uHeight),
532	SSMFIELD_ENTRY( VMSVGAState, uBpp),
533	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
534	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
536	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
537	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
538	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
539	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
542	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
543	SSMFIELD_ENTRY_TERM()
544	};
545
546	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
547	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
548	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
549
550	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
551	{
552	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
553	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
554	&& pSVGAState
555	&& pSVGAState->aScreens[idScreen].fDefined)
556	{
557	return &pSVGAState->aScreens[idScreen];
558	}
559	return NULL;
560	}
561
562	#endif /* IN_RING3 */
563
564	#ifdef LOG_ENABLED
565
566	/**
567	* Index register string name lookup
568	*
569	* @returns Index register string or "UNKNOWN"
570	* @param pThis VMSVGA State
571	* @param idxReg The index register.
572	*/
573	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
574	{
575	switch (idxReg)
576	{
577	case SVGA_REG_ID: return "SVGA_REG_ID";
578	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
579	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
580	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
581	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
582	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
583	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
584	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
585	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
586	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
587	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
588	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
589	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
590	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
591	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
592	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
593	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
594	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
595	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
596	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
597	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
598	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
599	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
601	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
602	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
603	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
604	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
605	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
606	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
607	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
608	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
609	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
610	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
611	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
612	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
613	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
614	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
615	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
616	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
617	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
618	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
619	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
620	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
621	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
622	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
623	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
624	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
625	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
626	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
627
628	default:
629	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
630	return "SVGA_SCRATCH_BASE reg";
631	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
632	return "SVGA_PALETTE_BASE reg";
633	return "UNKNOWN";
634	}
635	}
636
637	#ifdef IN_RING3
638	/**
639	* FIFO command name lookup
640	*
641	* @returns FIFO command string or "UNKNOWN"
642	* @param u32Cmd FIFO command
643	*/
644	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
645	{
646	switch (u32Cmd)
647	{
648	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
649	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
650	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
651	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
652	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
653	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
654	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
655	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
656	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
657	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
658	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
659	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
660	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
661	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
662	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
663	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
664	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
665	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
666	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
667	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
668	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
669	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
670	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
671	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
672	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
673	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
674	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
675	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
676	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
677	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
678	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
679	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
680	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
681	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
682	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
683	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
684	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
685	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
686	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
687	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
688	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
689	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
690	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
691	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
692	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
693	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
694	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
695	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
696	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
697	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
698	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
699	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
700	default: return "UNKNOWN";
701	}
702	}
703	# endif /* IN_RING3 */
704
705	#endif /* LOG_ENABLED */
706
707	#ifdef IN_RING3
708	/**
709	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
710	*/
711	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
712	{
713	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
714
715	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
716	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
717
718	/** @todo Test how it interacts with multiple screen objects. */
719	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
720	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
721	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
722
723	if (x < uWidth)
724	{
725	pThis->svga.viewport.x = x;
726	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
727	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
728	}
729	else
730	{
731	pThis->svga.viewport.x = uWidth;
732	pThis->svga.viewport.cx = 0;
733	pThis->svga.viewport.xRight = uWidth;
734	}
735	if (y < uHeight)
736	{
737	pThis->svga.viewport.y = y;
738	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
739	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
740	pThis->svga.viewport.yHighWC = uHeight - y;
741	}
742	else
743	{
744	pThis->svga.viewport.y = uHeight;
745	pThis->svga.viewport.cy = 0;
746	pThis->svga.viewport.yLowWC = 0;
747	pThis->svga.viewport.yHighWC = 0;
748	}
749
750	# ifdef VBOX_WITH_VMSVGA3D
751	/*
752	* Now inform the 3D backend.
753	*/
754	if (pThis->svga.f3DEnabled)
755	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
756	# else
757	RT_NOREF(OldViewport);
758	# endif
759	}
760	#endif /* IN_RING3 */
761
762	/**
763	* Read port register
764	*
765	* @returns VBox status code.
766	* @param pThis VMSVGA State
767	* @param pu32 Where to store the read value
768	*/
769	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
770	{
771	int rc = VINF_SUCCESS;
772	*pu32 = 0;
773
774	/* Rough index register validation. */
775	uint32_t idxReg = pThis->svga.u32IndexReg;
776	#if !defined(IN_RING3) && defined(VBOX_STRICT)
777	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
778	VINF_IOM_R3_IOPORT_READ);
779	#else
780	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
782	VINF_SUCCESS);
783	#endif
784	RT_UNTRUSTED_VALIDATED_FENCE();
785
786	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
787	if ( idxReg >= SVGA_REG_CAPABILITIES
788	&& pThis->svga.u32SVGAId == SVGA_ID_0)
789	{
790	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
791	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
792	}
793
794	switch (idxReg)
795	{
796	case SVGA_REG_ID:
797	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
798	*pu32 = pThis->svga.u32SVGAId;
799	break;
800
801	case SVGA_REG_ENABLE:
802	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
803	*pu32 = pThis->svga.fEnabled;
804	break;
805
806	case SVGA_REG_WIDTH:
807	{
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
809	if ( pThis->svga.fEnabled
810	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
811	{
812	*pu32 = pThis->svga.uWidth;
813	}
814	else
815	{
816	#ifndef IN_RING3
817	rc = VINF_IOM_R3_IOPORT_READ;
818	#else
819	*pu32 = pThis->pDrv->cx;
820	#endif
821	}
822	break;
823	}
824
825	case SVGA_REG_HEIGHT:
826	{
827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
828	if ( pThis->svga.fEnabled
829	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
830	{
831	*pu32 = pThis->svga.uHeight;
832	}
833	else
834	{
835	#ifndef IN_RING3
836	rc = VINF_IOM_R3_IOPORT_READ;
837	#else
838	*pu32 = pThis->pDrv->cy;
839	#endif
840	}
841	break;
842	}
843
844	case SVGA_REG_MAX_WIDTH:
845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
846	*pu32 = pThis->svga.u32MaxWidth;
847	break;
848
849	case SVGA_REG_MAX_HEIGHT:
850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
851	*pu32 = pThis->svga.u32MaxHeight;
852	break;
853
854	case SVGA_REG_DEPTH:
855	/* This returns the color depth of the current mode. */
856	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
857	switch (pThis->svga.uBpp)
858	{
859	case 15:
860	case 16:
861	case 24:
862	*pu32 = pThis->svga.uBpp;
863	break;
864
865	default:
866	case 32:
867	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
868	break;
869	}
870	break;
871
872	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
873	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
874	if ( pThis->svga.fEnabled
875	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
876	{
877	*pu32 = pThis->svga.uBpp;
878	}
879	else
880	{
881	#ifndef IN_RING3
882	rc = VINF_IOM_R3_IOPORT_READ;
883	#else
884	*pu32 = pThis->pDrv->cBits;
885	#endif
886	}
887	break;
888
889	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
891	if ( pThis->svga.fEnabled
892	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
893	{
894	*pu32 = (pThis->svga.uBpp + 7) & ~7;
895	}
896	else
897	{
898	#ifndef IN_RING3
899	rc = VINF_IOM_R3_IOPORT_READ;
900	#else
901	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
902	#endif
903	}
904	break;
905
906	case SVGA_REG_PSEUDOCOLOR:
907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
908	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
909	break;
910
911	case SVGA_REG_RED_MASK:
912	case SVGA_REG_GREEN_MASK:
913	case SVGA_REG_BLUE_MASK:
914	{
915	uint32_t uBpp;
916
917	if ( pThis->svga.fEnabled
918	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
919	{
920	uBpp = pThis->svga.uBpp;
921	}
922	else
923	{
924	#ifndef IN_RING3
925	rc = VINF_IOM_R3_IOPORT_READ;
926	break;
927	#else
928	uBpp = pThis->pDrv->cBits;
929	#endif
930	}
931	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
932	switch (uBpp)
933	{
934	case 8:
935	u32RedMask = 0x07;
936	u32GreenMask = 0x38;
937	u32BlueMask = 0xc0;
938	break;
939
940	case 15:
941	u32RedMask = 0x0000001f;
942	u32GreenMask = 0x000003e0;
943	u32BlueMask = 0x00007c00;
944	break;
945
946	case 16:
947	u32RedMask = 0x0000001f;
948	u32GreenMask = 0x000007e0;
949	u32BlueMask = 0x0000f800;
950	break;
951
952	case 24:
953	case 32:
954	default:
955	u32RedMask = 0x00ff0000;
956	u32GreenMask = 0x0000ff00;
957	u32BlueMask = 0x000000ff;
958	break;
959	}
960	switch (idxReg)
961	{
962	case SVGA_REG_RED_MASK:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
964	*pu32 = u32RedMask;
965	break;
966
967	case SVGA_REG_GREEN_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
969	*pu32 = u32GreenMask;
970	break;
971
972	case SVGA_REG_BLUE_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
974	*pu32 = u32BlueMask;
975	break;
976	}
977	break;
978	}
979
980	case SVGA_REG_BYTES_PER_LINE:
981	{
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.cbScanline)
985	{
986	*pu32 = pThis->svga.cbScanline;
987	}
988	else
989	{
990	#ifndef IN_RING3
991	rc = VINF_IOM_R3_IOPORT_READ;
992	#else
993	*pu32 = pThis->pDrv->cbScanline;
994	#endif
995	}
996	break;
997	}
998
999	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1001	*pu32 = pThis->vram_size;
1002	break;
1003
1004	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1005	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1006	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1007	*pu32 = pThis->GCPhysVRAM;
1008	break;
1009
1010	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1012	/* Always zero in our case. */
1013	*pu32 = 0;
1014	break;
1015
1016	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1017	{
1018	#ifndef IN_RING3
1019	rc = VINF_IOM_R3_IOPORT_READ;
1020	#else
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1022
1023	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1024	if ( pThis->svga.fEnabled
1025	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1026	{
1027	/* Hardware enabled; return real framebuffer size .*/
1028	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1029	}
1030	else
1031	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1032
1033	pu32 = RT_MIN(pThis->vram_size, pu32);
1034	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1035	#endif
1036	break;
1037	}
1038
1039	case SVGA_REG_CAPABILITIES:
1040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1041	*pu32 = pThis->svga.u32RegCaps;
1042	break;
1043
1044	case SVGA_REG_MEM_START: /* FIFO start */
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1046	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1047	*pu32 = pThis->svga.GCPhysFIFO;
1048	break;
1049
1050	case SVGA_REG_MEM_SIZE: /* FIFO size */
1051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1052	*pu32 = pThis->svga.cbFIFO;
1053	break;
1054
1055	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1057	*pu32 = pThis->svga.fConfigured;
1058	break;
1059
1060	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1062	*pu32 = 0;
1063	break;
1064
1065	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1067	if (pThis->svga.fBusy)
1068	{
1069	#ifndef IN_RING3
1070	/* Go to ring-3 and halt the CPU. */
1071	rc = VINF_IOM_R3_IOPORT_READ;
1072	break;
1073	#else
1074	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1075	/* The guest is basically doing a HLT via the device here, but with
1076	a special wake up condition on FIFO completion. */
1077	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1078	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1079	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1080	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1081	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1082	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1083	if (pThis->svga.fBusy)
1084	{
1085	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1086	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1087	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1088	}
1089	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1090	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1091	# else
1092
1093	/* Delay the EMT a bit so the FIFO and others can get some work done.
1094	This used to be a crude 50 ms sleep. The current code tries to be
1095	more efficient, but the consept is still very crude. */
1096	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1097	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1098	RTThreadYield();
1099	if (pThis->svga.fBusy)
1100	{
1101	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1102
1103	if (pThis->svga.fBusy && cRefs == 1)
1104	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1105	if (pThis->svga.fBusy)
1106	{
1107	/** @todo If this code is going to stay, we need to call into the halt/wait
1108	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1109	* suffer when the guest is polling on a busy FIFO. */
1110	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1111	if (cNsMaxWait >= RT_NS_100US)
1112	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1113	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1114	RT_MIN(cNsMaxWait, RT_NS_10MS));
1115	}
1116
1117	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1118	}
1119	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1120	# endif
1121	*pu32 = pThis->svga.fBusy != 0;
1122	#endif
1123	}
1124	else
1125	*pu32 = false;
1126	break;
1127
1128	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1130	*pu32 = pThis->svga.u32GuestId;
1131	break;
1132
1133	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1135	*pu32 = pThis->svga.cScratchRegion;
1136	break;
1137
1138	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1139	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1140	*pu32 = SVGA_FIFO_NUM_REGS;
1141	break;
1142
1143	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1145	*pu32 = pThis->svga.u32PitchLock;
1146	break;
1147
1148	case SVGA_REG_IRQMASK: /* Interrupt mask */
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1150	*pu32 = pThis->svga.u32IrqMask;
1151	break;
1152
1153	/* See "Guest memory regions" below. */
1154	case SVGA_REG_GMR_ID:
1155	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1156	*pu32 = pThis->svga.u32CurrentGMRId;
1157	break;
1158
1159	case SVGA_REG_GMR_DESCRIPTOR:
1160	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1161	/* Write only */
1162	*pu32 = 0;
1163	break;
1164
1165	case SVGA_REG_GMR_MAX_IDS:
1166	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1167	*pu32 = pThis->svga.cGMR;
1168	break;
1169
1170	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1171	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1172	*pu32 = VMSVGA_MAX_GMR_PAGES;
1173	break;
1174
1175	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1177	*pu32 = pThis->svga.fTraces;
1178	break;
1179
1180	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1181	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1182	*pu32 = VMSVGA_MAX_GMR_PAGES;
1183	break;
1184
1185	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1186	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1187	*pu32 = VMSVGA_SURFACE_SIZE;
1188	break;
1189
1190	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1191	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1192	break;
1193
1194	/* Mouse cursor support. */
1195	case SVGA_REG_CURSOR_ID:
1196	case SVGA_REG_CURSOR_X:
1197	case SVGA_REG_CURSOR_Y:
1198	case SVGA_REG_CURSOR_ON:
1199	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1200	break;
1201
1202	/* Legacy multi-monitor support */
1203	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1204	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1205	*pu32 = 1;
1206	break;
1207
1208	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1210	*pu32 = 0;
1211	break;
1212
1213	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1214	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1215	*pu32 = 0;
1216	break;
1217
1218	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1220	*pu32 = 0;
1221	break;
1222
1223	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1225	*pu32 = 0;
1226	break;
1227
1228	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1230	*pu32 = pThis->svga.uWidth;
1231	break;
1232
1233	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1235	*pu32 = pThis->svga.uHeight;
1236	break;
1237
1238	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1240	/* We must return something sensible here otherwise the Linux driver
1241	will take a legacy code path without 3d support. This number also
1242	limits how many screens Linux guests will allow. */
1243	*pu32 = pThis->cMonitors;
1244	break;
1245
1246	default:
1247	{
1248	uint32_t offReg;
1249	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1250	{
1251	RT_UNTRUSTED_VALIDATED_FENCE();
1252	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1254	}
1255	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1256	{
1257	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1258	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1259	RT_UNTRUSTED_VALIDATED_FENCE();
1260	uint32_t u32 = pThis->last_palette[offReg / 3];
1261	switch (offReg % 3)
1262	{
1263	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1264	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1265	case 2: pu32 = u32 & 0xff; break; / blue */
1266	}
1267	}
1268	else
1269	{
1270	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1271	rc = VINF_IOM_R3_IOPORT_READ;
1272	#else
1273	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1274
1275	/* Do not assert. The guest might be reading all registers. */
1276	LogFunc(("Unknown reg=%#x\n", idxReg));
1277	#endif
1278	}
1279	break;
1280	}
1281	}
1282	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1283	return rc;
1284	}
1285
1286	#ifdef IN_RING3
1287	/**
1288	* Apply the current resolution settings to change the video mode.
1289	*
1290	* @returns VBox status code.
1291	* @param pThis VMSVGA State
1292	*/
1293	static int vmsvgaChangeMode(PVGASTATE pThis)
1294	{
1295	int rc;
1296
1297	/* Always do changemode on FIFO thread. */
1298	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1299
1300	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1301
1302	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1303
1304	if (pThis->svga.fGFBRegisters)
1305	{
1306	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1307	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1308	* deletes all screens other than screen #0, and redefines screen
1309	* #0 according to the specified mode. Drivers that use
1310	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1311	*/
1312
1313	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1314	pScreen->fDefined = true;
1315	pScreen->fModified = true;
1316	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1317	pScreen->idScreen = 0;
1318	pScreen->xOrigin = 0;
1319	pScreen->yOrigin = 0;
1320	pScreen->offVRAM = 0;
1321	pScreen->cbPitch = pThis->svga.cbScanline;
1322	pScreen->cWidth = pThis->svga.uWidth;
1323	pScreen->cHeight = pThis->svga.uHeight;
1324	pScreen->cBpp = pThis->svga.uBpp;
1325
1326	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1327	{
1328	/* Delete screen. */
1329	pScreen = &pSVGAState->aScreens[iScreen];
1330	if (pScreen->fDefined)
1331	{
1332	pScreen->fModified = true;
1333	pScreen->fDefined = false;
1334	}
1335	}
1336	}
1337	else
1338	{
1339	/* "If Screen Objects are supported, they can be used to fully
1340	* replace the functionality provided by the framebuffer registers
1341	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1342	*/
1343	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1345	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1346	}
1347
1348	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1349	{
1350	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1351	if (!pScreen->fModified)
1352	continue;
1353
1354	pScreen->fModified = false;
1355
1356	VBVAINFOVIEW view;
1357	RT_ZERO(view);
1358	view.u32ViewIndex = pScreen->idScreen;
1359	// view.u32ViewOffset = 0;
1360	view.u32ViewSize = pThis->vram_size;
1361	view.u32MaxScreenSize = pThis->vram_size;
1362
1363	VBVAINFOSCREEN screen;
1364	RT_ZERO(screen);
1365	screen.u32ViewIndex = pScreen->idScreen;
1366
1367	if (pScreen->fDefined)
1368	{
1369	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1371	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1372	{
1373	Assert(pThis->svga.fGFBRegisters);
1374	continue;
1375	}
1376
1377	screen.i32OriginX = pScreen->xOrigin;
1378	screen.i32OriginY = pScreen->yOrigin;
1379	screen.u32StartOffset = pScreen->offVRAM;
1380	screen.u32LineSize = pScreen->cbPitch;
1381	screen.u32Width = pScreen->cWidth;
1382	screen.u32Height = pScreen->cHeight;
1383	screen.u16BitsPerPixel = pScreen->cBpp;
1384	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1385	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1386	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1387	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1388	}
1389	else
1390	{
1391	/* Screen is destroyed. */
1392	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1393	}
1394
1395	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1396	AssertRC(rc);
1397	}
1398
1399	/* Last stuff. For the VGA device screenshot. */
1400	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1401	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1402	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1403	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1404	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1405
1406	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1407	if ( pThis->svga.viewport.cx == 0
1408	&& pThis->svga.viewport.cy == 0)
1409	{
1410	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1412	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1414	pThis->svga.viewport.yLowWC = 0;
1415	}
1416
1417	return VINF_SUCCESS;
1418	}
1419
1420	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1421	{
1422	VBVACMDHDR cmd;
1423	cmd.x = (int16_t)(pScreen->xOrigin + x);
1424	cmd.y = (int16_t)(pScreen->yOrigin + y);
1425	cmd.w = (uint16_t)w;
1426	cmd.h = (uint16_t)h;
1427
1428	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1429	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1430	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1431	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1432
1433	return VINF_SUCCESS;
1434	}
1435
1436	#endif /* IN_RING3 */
1437
1438	#if defined(IN_RING0) \|\| defined(IN_RING3)
1439	/**
1440	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1441	*
1442	* @param pThis The VMSVGA state.
1443	* @param fState The busy state.
1444	*/
1445	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1446	{
1447	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1448
1449	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1450	{
1451	/* Race / unfortunately scheduling. Highly unlikly. */
1452	uint32_t cLoops = 64;
1453	do
1454	{
1455	ASMNopPause();
1456	fState = (pThis->svga.fBusy != 0);
1457	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1458	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1459	}
1460	}
1461
1462
1463	/**
1464	* Update the scanline pitch in response to the guest changing mode
1465	* width/bpp.
1466	*
1467	* @param pThis VMSVGA State
1468	*/
1469	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1470	{
1471	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1472	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1473	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1474	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1475
1476	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1477	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1478	* location but it has a different meaning.
1479	*/
1480	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1481	uFifoPitchLock = 0;
1482
1483	/* Sanitize values. */
1484	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1485	uFifoPitchLock = 0;
1486	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1487	uRegPitchLock = 0;
1488
1489	/* Prefer the register value to the FIFO value.*/
1490	if (uRegPitchLock)
1491	pThis->svga.cbScanline = uRegPitchLock;
1492	else if (uFifoPitchLock)
1493	pThis->svga.cbScanline = uFifoPitchLock;
1494	else
1495	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1496
1497	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1498	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1499	}
1500	#endif
1501
1502
1503	/**
1504	* Write port register
1505	*
1506	* @returns VBox status code.
1507	* @param pThis VMSVGA State
1508	* @param u32 Value to write
1509	*/
1510	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1511	{
1512	#ifdef IN_RING3
1513	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1514	#endif
1515	int rc = VINF_SUCCESS;
1516
1517	/* Rough index register validation. */
1518	uint32_t idxReg = pThis->svga.u32IndexReg;
1519	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1520	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1521	VINF_IOM_R3_IOPORT_WRITE);
1522	#else
1523	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1524	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1525	VINF_SUCCESS);
1526	#endif
1527	RT_UNTRUSTED_VALIDATED_FENCE();
1528
1529	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1530	if ( idxReg >= SVGA_REG_CAPABILITIES
1531	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1532	{
1533	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1534	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1535	}
1536	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1537	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1538	switch (idxReg)
1539	{
1540	case SVGA_REG_WIDTH:
1541	case SVGA_REG_HEIGHT:
1542	case SVGA_REG_PITCHLOCK:
1543	case SVGA_REG_BITS_PER_PIXEL:
1544	pThis->svga.fGFBRegisters = true;
1545	break;
1546	default:
1547	break;
1548	}
1549
1550	switch (idxReg)
1551	{
1552	case SVGA_REG_ID:
1553	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1554	if ( u32 == SVGA_ID_0
1555	\|\| u32 == SVGA_ID_1
1556	\|\| u32 == SVGA_ID_2)
1557	pThis->svga.u32SVGAId = u32;
1558	else
1559	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1560	break;
1561
1562	case SVGA_REG_ENABLE:
1563	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1564	#ifdef IN_RING3
1565	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1566	&& pThis->svga.fEnabled == false)
1567	{
1568	/* Make a backup copy of the first 512kb in order to save font data etc. */
1569	/** @todo should probably swap here, rather than copy + zero */
1570	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1571	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1572	}
1573
1574	pThis->svga.fEnabled = u32;
1575	if (pThis->svga.fEnabled)
1576	{
1577	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1578	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1579	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1580	{
1581	/* Keep the current mode. */
1582	pThis->svga.uWidth = pThis->pDrv->cx;
1583	pThis->svga.uHeight = pThis->pDrv->cy;
1584	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1585	}
1586
1587	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1588	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1589	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1590	{
1591	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1592	}
1593	# ifdef LOG_ENABLED
1594	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1595	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1596	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1597	# endif
1598
1599	/* Disable or enable dirty page tracking according to the current fTraces value. */
1600	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1601
1602	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1603	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1604	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1605	}
1606	else
1607	{
1608	/* Restore the text mode backup. */
1609	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1610
1611	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1612
1613	/* Enable dirty page tracking again when going into legacy mode. */
1614	vmsvgaSetTraces(pThis, true);
1615
1616	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1617	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1618	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1619
1620	/* Clear the pitch lock. */
1621	pThis->svga.u32PitchLock = 0;
1622	}
1623	#else /* !IN_RING3 */
1624	rc = VINF_IOM_R3_IOPORT_WRITE;
1625	#endif /* !IN_RING3 */
1626	break;
1627
1628	case SVGA_REG_WIDTH:
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1630	if (pThis->svga.uWidth != u32)
1631	{
1632	#if defined(IN_RING3) \|\| defined(IN_RING0)
1633	pThis->svga.uWidth = u32;
1634	vmsvgaUpdatePitch(pThis);
1635	if (pThis->svga.fEnabled)
1636	{
1637	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1638	}
1639	#else
1640	rc = VINF_IOM_R3_IOPORT_WRITE;
1641	#endif
1642	}
1643	/* else: nop */
1644	break;
1645
1646	case SVGA_REG_HEIGHT:
1647	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1648	if (pThis->svga.uHeight != u32)
1649	{
1650	pThis->svga.uHeight = u32;
1651	if (pThis->svga.fEnabled)
1652	{
1653	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1654	}
1655	}
1656	/* else: nop */
1657	break;
1658
1659	case SVGA_REG_DEPTH:
1660	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1661	/** @todo read-only?? */
1662	break;
1663
1664	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1665	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1666	if (pThis->svga.uBpp != u32)
1667	{
1668	#if defined(IN_RING3) \|\| defined(IN_RING0)
1669	pThis->svga.uBpp = u32;
1670	vmsvgaUpdatePitch(pThis);
1671	if (pThis->svga.fEnabled)
1672	{
1673	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1674	}
1675	#else
1676	rc = VINF_IOM_R3_IOPORT_WRITE;
1677	#endif
1678	}
1679	/* else: nop */
1680	break;
1681
1682	case SVGA_REG_PSEUDOCOLOR:
1683	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1684	break;
1685
1686	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1687	#ifdef IN_RING3
1688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1689	pThis->svga.fConfigured = u32;
1690	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1691	if (!pThis->svga.fConfigured)
1692	{
1693	pThis->svga.fTraces = true;
1694	}
1695	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1696	#else
1697	rc = VINF_IOM_R3_IOPORT_WRITE;
1698	#endif
1699	break;
1700
1701	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1702	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1703	if ( pThis->svga.fEnabled
1704	&& pThis->svga.fConfigured)
1705	{
1706	#if defined(IN_RING3) \|\| defined(IN_RING0)
1707	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1708	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1709	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1710	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1711
1712	/* Kick the FIFO thread to start processing commands again. */
1713	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1714	#else
1715	rc = VINF_IOM_R3_IOPORT_WRITE;
1716	#endif
1717	}
1718	/* else nothing to do. */
1719	else
1720	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1721
1722	break;
1723
1724	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1726	break;
1727
1728	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1729	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1730	pThis->svga.u32GuestId = u32;
1731	break;
1732
1733	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1734	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1735	pThis->svga.u32PitchLock = u32;
1736	/* Should this also update the FIFO pitch lock? Unclear. */
1737	break;
1738
1739	case SVGA_REG_IRQMASK: /* Interrupt mask */
1740	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1741	pThis->svga.u32IrqMask = u32;
1742
1743	/* Irq pending after the above change? */
1744	if (pThis->svga.u32IrqStatus & u32)
1745	{
1746	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1747	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1748	}
1749	else
1750	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1751	break;
1752
1753	/* Mouse cursor support */
1754	case SVGA_REG_CURSOR_ID:
1755	case SVGA_REG_CURSOR_X:
1756	case SVGA_REG_CURSOR_Y:
1757	case SVGA_REG_CURSOR_ON:
1758	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1759	break;
1760
1761	/* Legacy multi-monitor support */
1762	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1763	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1764	break;
1765	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1766	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1767	break;
1768	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1769	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1770	break;
1771	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1772	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1773	break;
1774	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1776	break;
1777	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1778	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1779	break;
1780	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1782	break;
1783	#ifdef VBOX_WITH_VMSVGA3D
1784	/* See "Guest memory regions" below. */
1785	case SVGA_REG_GMR_ID:
1786	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1787	pThis->svga.u32CurrentGMRId = u32;
1788	break;
1789
1790	case SVGA_REG_GMR_DESCRIPTOR:
1791	# ifndef IN_RING3
1792	rc = VINF_IOM_R3_IOPORT_WRITE;
1793	break;
1794	# else /* IN_RING3 */
1795	{
1796	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1797
1798	/* Validate current GMR id. */
1799	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1800	AssertBreak(idGMR < pThis->svga.cGMR);
1801	RT_UNTRUSTED_VALIDATED_FENCE();
1802
1803	/* Free the old GMR if present. */
1804	vmsvgaGMRFree(pThis, idGMR);
1805
1806	/* Just undefine the GMR? */
1807	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1808	if (GCPhys == 0)
1809	{
1810	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1811	break;
1812	}
1813
1814
1815	/* Never cross a page boundary automatically. */
1816	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1817	uint32_t cPagesTotal = 0;
1818	uint32_t iDesc = 0;
1819	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1820	uint32_t cLoops = 0;
1821	RTGCPHYS GCPhysBase = GCPhys;
1822	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1823	{
1824	/* Read descriptor. */
1825	SVGAGuestMemDescriptor desc;
1826	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1827	AssertRCBreak(rc);
1828
1829	if (desc.numPages != 0)
1830	{
1831	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1832	cPagesTotal += desc.numPages;
1833	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1834
1835	if ((iDesc & 15) == 0)
1836	{
1837	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1838	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1839	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1840	}
1841
1842	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1843	paDescs[iDesc++].numPages = desc.numPages;
1844
1845	/* Continue with the next descriptor. */
1846	GCPhys += sizeof(desc);
1847	}
1848	else if (desc.ppn == 0)
1849	break; /* terminator */
1850	else /* Pointer to the next physical page of descriptors. */
1851	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1852
1853	cLoops++;
1854	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1855	}
1856
1857	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1858	if (RT_SUCCESS(rc))
1859	{
1860	/* Commit the GMR. */
1861	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1862	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1863	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1864	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1865	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1866	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1867	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1868	}
1869	else
1870	{
1871	RTMemFree(paDescs);
1872	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1873	}
1874	break;
1875	}
1876	# endif /* IN_RING3 */
1877	#endif // VBOX_WITH_VMSVGA3D
1878
1879	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1880	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1881	if (pThis->svga.fTraces == u32)
1882	break; /* nothing to do */
1883
1884	#ifdef IN_RING3
1885	vmsvgaSetTraces(pThis, !!u32);
1886	#else
1887	rc = VINF_IOM_R3_IOPORT_WRITE;
1888	#endif
1889	break;
1890
1891	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1892	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1893	break;
1894
1895	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1896	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1897	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1898	break;
1899
1900	case SVGA_REG_FB_START:
1901	case SVGA_REG_MEM_START:
1902	case SVGA_REG_HOST_BITS_PER_PIXEL:
1903	case SVGA_REG_MAX_WIDTH:
1904	case SVGA_REG_MAX_HEIGHT:
1905	case SVGA_REG_VRAM_SIZE:
1906	case SVGA_REG_FB_SIZE:
1907	case SVGA_REG_CAPABILITIES:
1908	case SVGA_REG_MEM_SIZE:
1909	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1910	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1911	case SVGA_REG_BYTES_PER_LINE:
1912	case SVGA_REG_FB_OFFSET:
1913	case SVGA_REG_RED_MASK:
1914	case SVGA_REG_GREEN_MASK:
1915	case SVGA_REG_BLUE_MASK:
1916	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1917	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1918	case SVGA_REG_GMR_MAX_IDS:
1919	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1920	/* Read only - ignore. */
1921	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1923	break;
1924
1925	default:
1926	{
1927	uint32_t offReg;
1928	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1929	{
1930	RT_UNTRUSTED_VALIDATED_FENCE();
1931	pThis->svga.au32ScratchRegion[offReg] = u32;
1932	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1933	}
1934	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1935	{
1936	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1937	Btw, see rgb_to_pixel32. */
1938	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1939	u32 &= 0xff;
1940	RT_UNTRUSTED_VALIDATED_FENCE();
1941	uint32_t uRgb = pThis->last_palette[offReg / 3];
1942	switch (offReg % 3)
1943	{
1944	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1945	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1946	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1947	}
1948	pThis->last_palette[offReg / 3] = uRgb;
1949	}
1950	else
1951	{
1952	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1953	rc = VINF_IOM_R3_IOPORT_WRITE;
1954	#else
1955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1956	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1957	#endif
1958	}
1959	break;
1960	}
1961	}
1962	return rc;
1963	}
1964
1965	/**
1966	* Port I/O Handler for IN operations.
1967	*
1968	* @returns VINF_SUCCESS or VINF_EM_*.
1969	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1970	*
1971	* @param pDevIns The device instance.
1972	* @param pvUser User argument.
1973	* @param uPort Port number used for the IN operation.
1974	* @param pu32 Where to store the result. This is always a 32-bit
1975	* variable regardless of what @a cb might say.
1976	* @param cb Number of bytes read.
1977	*/
1978	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1979	{
1980	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1981	RT_NOREF_PV(pvUser);
1982
1983	/* Ignore non-dword accesses. */
1984	if (cb != 4)
1985	{
1986	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1987	*pu32 = UINT32_MAX;
1988	return VINF_SUCCESS;
1989	}
1990
1991	switch (uPort - pThis->svga.BasePort)
1992	{
1993	case SVGA_INDEX_PORT:
1994	*pu32 = pThis->svga.u32IndexReg;
1995	break;
1996
1997	case SVGA_VALUE_PORT:
1998	return vmsvgaReadPort(pThis, pu32);
1999
2000	case SVGA_BIOS_PORT:
2001	Log(("Ignoring BIOS port read\n"));
2002	*pu32 = 0;
2003	break;
2004
2005	case SVGA_IRQSTATUS_PORT:
2006	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2007	*pu32 = pThis->svga.u32IrqStatus;
2008	break;
2009
2010	default:
2011	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
2012	*pu32 = UINT32_MAX;
2013	break;
2014	}
2015
2016	return VINF_SUCCESS;
2017	}
2018
2019	/**
2020	* Port I/O Handler for OUT operations.
2021	*
2022	* @returns VINF_SUCCESS or VINF_EM_*.
2023	*
2024	* @param pDevIns The device instance.
2025	* @param pvUser User argument.
2026	* @param uPort Port number used for the OUT operation.
2027	* @param u32 The value to output.
2028	* @param cb The value size in bytes.
2029	*/
2030	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
2031	{
2032	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2033	RT_NOREF_PV(pvUser);
2034
2035	/* Ignore non-dword accesses. */
2036	if (cb != 4)
2037	{
2038	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
2039	return VINF_SUCCESS;
2040	}
2041
2042	switch (uPort - pThis->svga.BasePort)
2043	{
2044	case SVGA_INDEX_PORT:
2045	pThis->svga.u32IndexReg = u32;
2046	break;
2047
2048	case SVGA_VALUE_PORT:
2049	return vmsvgaWritePort(pThis, u32);
2050
2051	case SVGA_BIOS_PORT:
2052	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2053	break;
2054
2055	case SVGA_IRQSTATUS_PORT:
2056	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2057	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2058	/* Clear the irq in case all events have been cleared. */
2059	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2060	{
2061	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2062	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2063	}
2064	break;
2065
2066	default:
2067	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2068	uPort - pThis->svga.BasePort, uPort, u32, cb));
2069	break;
2070	}
2071	return VINF_SUCCESS;
2072	}
2073
2074	#ifdef IN_RING3
2075
2076	# ifdef DEBUG_FIFO_ACCESS
2077	/**
2078	* Handle FIFO memory access.
2079	* @returns VBox status code.
2080	* @param pVM VM handle.
2081	* @param pThis VGA device instance data.
2082	* @param GCPhys The access physical address.
2083	* @param fWriteAccess Read or write access
2084	*/
2085	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2086	{
2087	RT_NOREF(pVM);
2088	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2089	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2090
2091	switch (GCPhysOffset >> 2)
2092	{
2093	case SVGA_FIFO_MIN:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_MAX:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_NEXT_CMD:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_STOP:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_CAPABILITIES:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_FLAGS:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_FENCE:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_HWVERSION:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_PITCHLOCK:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_CURSOR_ON:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_CURSOR_X:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_CURSOR_Y:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_CURSOR_COUNT:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_RESERVED:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_CURSOR_SCREEN_ID:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_DEAD:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_HWVERSION_REVISED:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS_LAST:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_GUEST_3D_HWVERSION:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_FENCE_GOAL:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_BUSY:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	default:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	}
2412
2413	return VINF_EM_RAW_EMULATE_INSTR;
2414	}
2415	# endif /* DEBUG_FIFO_ACCESS */
2416
2417	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2418	/**
2419	* HC access handler for the FIFO.
2420	*
2421	* @returns VINF_SUCCESS if the handler have carried out the operation.
2422	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2423	* @param pVM VM Handle.
2424	* @param pVCpu The cross context CPU structure for the calling EMT.
2425	* @param GCPhys The physical address the guest is writing to.
2426	* @param pvPhys The HC mapping of that address.
2427	* @param pvBuf What the guest is reading/writing.
2428	* @param cbBuf How much it's reading/writing.
2429	* @param enmAccessType The access type.
2430	* @param enmOrigin Who is making the access.
2431	* @param pvUser User argument.
2432	*/
2433	static DECLCALLBACK(VBOXSTRICTRC)
2434	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2435	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2436	{
2437	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2438	PVGASTATE pThis = (PVGASTATE)pvUser;
2439	AssertPtr(pThis);
2440
2441	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2442	/*
2443	* Wake up the FIFO thread as it might have work to do now.
2444	*/
2445	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2446	AssertLogRelRC(rc);
2447	# endif
2448
2449	# ifdef DEBUG_FIFO_ACCESS
2450	/*
2451	* When in debug-fifo-access mode, we do not disable the access handler,
2452	* but leave it on as we wish to catch all access.
2453	*/
2454	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2455	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2456	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2457	/*
2458	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2459	*/
2460	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2461	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2462	# endif
2463	if (RT_SUCCESS(rc))
2464	return VINF_PGM_HANDLER_DO_DEFAULT;
2465	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2466	return rc;
2467	}
2468	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2469
2470	#endif /* IN_RING3 */
2471
2472	#ifdef DEBUG_GMR_ACCESS
2473	# ifdef IN_RING3
2474
2475	/**
2476	* HC access handler for the FIFO.
2477	*
2478	* @returns VINF_SUCCESS if the handler have carried out the operation.
2479	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2480	* @param pVM VM Handle.
2481	* @param pVCpu The cross context CPU structure for the calling EMT.
2482	* @param GCPhys The physical address the guest is writing to.
2483	* @param pvPhys The HC mapping of that address.
2484	* @param pvBuf What the guest is reading/writing.
2485	* @param cbBuf How much it's reading/writing.
2486	* @param enmAccessType The access type.
2487	* @param enmOrigin Who is making the access.
2488	* @param pvUser User argument.
2489	*/
2490	static DECLCALLBACK(VBOXSTRICTRC)
2491	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2492	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2493	{
2494	PVGASTATE pThis = (PVGASTATE)pvUser;
2495	Assert(pThis);
2496	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2497	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2498
2499	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2500
2501	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2502	{
2503	PGMR pGMR = &pSVGAState->paGMR[i];
2504
2505	if (pGMR->numDescriptors)
2506	{
2507	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2508	{
2509	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2510	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2511	{
2512	/*
2513	* Turn off the write handler for this particular page and make it R/W.
2514	* Then return telling the caller to restart the guest instruction.
2515	*/
2516	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2517	AssertRC(rc);
2518	goto end;
2519	}
2520	}
2521	}
2522	}
2523	end:
2524	return VINF_PGM_HANDLER_DO_DEFAULT;
2525	}
2526
2527	/* Callback handler for VMR3ReqCallWaitU */
2528	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2529	{
2530	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2531	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2532	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2533	int rc;
2534
2535	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2536	{
2537	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2538	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2539	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2540	AssertRC(rc);
2541	}
2542	return VINF_SUCCESS;
2543	}
2544
2545	/* Callback handler for VMR3ReqCallWaitU */
2546	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2547	{
2548	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2549	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2550	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2551
2552	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2553	{
2554	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2555	AssertRC(rc);
2556	}
2557	return VINF_SUCCESS;
2558	}
2559
2560	/* Callback handler for VMR3ReqCallWaitU */
2561	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2562	{
2563	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2564
2565	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2566	{
2567	PGMR pGMR = &pSVGAState->paGMR[i];
2568
2569	if (pGMR->numDescriptors)
2570	{
2571	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2572	{
2573	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2574	AssertRC(rc);
2575	}
2576	}
2577	}
2578	return VINF_SUCCESS;
2579	}
2580
2581	# endif /* IN_RING3 */
2582	#endif /* DEBUG_GMR_ACCESS */
2583
2584	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2585
2586	#ifdef IN_RING3
2587
2588
2589	/**
2590	* Common worker for changing the pointer shape.
2591	*
2592	* @param pThis The VGA instance data.
2593	* @param pSVGAState The VMSVGA ring-3 instance data.
2594	* @param fAlpha Whether there is alpha or not.
2595	* @param xHot Hotspot x coordinate.
2596	* @param yHot Hotspot y coordinate.
2597	* @param cx Width.
2598	* @param cy Height.
2599	* @param pbData Heap copy of the cursor data. Consumed.
2600	* @param cbData The size of the data.
2601	*/
2602	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2603	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2604	{
2605	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2606	#ifdef LOG_ENABLED
2607	if (LogIs2Enabled())
2608	{
2609	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2610	if (!fAlpha)
2611	{
2612	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2613	for (uint32_t y = 0; y < cy; y++)
2614	{
2615	Log2(("%3u:", y));
2616	uint8_t const pbLine = &pbData[y cbAndLine];
2617	for (uint32_t x = 0; x < cx; x += 8)
2618	{
2619	uint8_t b = pbLine[x / 8];
2620	char szByte[12];
2621	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2622	szByte[1] = b & 0x40 ? '*' : ' ';
2623	szByte[2] = b & 0x20 ? '*' : ' ';
2624	szByte[3] = b & 0x10 ? '*' : ' ';
2625	szByte[4] = b & 0x08 ? '*' : ' ';
2626	szByte[5] = b & 0x04 ? '*' : ' ';
2627	szByte[6] = b & 0x02 ? '*' : ' ';
2628	szByte[7] = b & 0x01 ? '*' : ' ';
2629	szByte[8] = '\0';
2630	Log2(("%s", szByte));
2631	}
2632	Log2(("\n"));
2633	}
2634	}
2635
2636	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2637	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2638	for (uint32_t y = 0; y < cy; y++)
2639	{
2640	Log2(("%3u:", y));
2641	uint32_t const pu32Line = &pu32Xor[y cx];
2642	for (uint32_t x = 0; x < cx; x++)
2643	Log2((" %08x", pu32Line[x]));
2644	Log2(("\n"));
2645	}
2646	}
2647	#endif
2648
2649	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2650	AssertRC(rc);
2651
2652	if (pSVGAState->Cursor.fActive)
2653	RTMemFree(pSVGAState->Cursor.pData);
2654
2655	pSVGAState->Cursor.fActive = true;
2656	pSVGAState->Cursor.xHotspot = xHot;
2657	pSVGAState->Cursor.yHotspot = yHot;
2658	pSVGAState->Cursor.width = cx;
2659	pSVGAState->Cursor.height = cy;
2660	pSVGAState->Cursor.cbData = cbData;
2661	pSVGAState->Cursor.pData = pbData;
2662	}
2663
2664
2665	/**
2666	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2667	*
2668	* @param pThis The VGA instance data.
2669	* @param pSVGAState The VMSVGA ring-3 instance data.
2670	* @param pCursor The cursor.
2671	* @param pbSrcAndMask The AND mask.
2672	* @param cbSrcAndLine The scanline length of the AND mask.
2673	* @param pbSrcXorMask The XOR mask.
2674	* @param cbSrcXorLine The scanline length of the XOR mask.
2675	*/
2676	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2677	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2678	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2679	{
2680	uint32_t const cx = pCursor->width;
2681	uint32_t const cy = pCursor->height;
2682
2683	/*
2684	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2685	* The AND data uses 8-bit aligned scanlines.
2686	* The XOR data must be starting on a 32-bit boundrary.
2687	*/
2688	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2689	uint32_t cbDstAndMask = cbDstAndLine * cy;
2690	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2691	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2692
2693	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2694	AssertReturnVoid(pbCopy);
2695
2696	/* Convert the AND mask. */
2697	uint8_t *pbDst = pbCopy;
2698	uint8_t const *pbSrc = pbSrcAndMask;
2699	switch (pCursor->andMaskDepth)
2700	{
2701	case 1:
2702	if (cbSrcAndLine == cbDstAndLine)
2703	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2704	else
2705	{
2706	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2707	for (uint32_t y = 0; y < cy; y++)
2708	{
2709	memcpy(pbDst, pbSrc, cbDstAndLine);
2710	pbDst += cbDstAndLine;
2711	pbSrc += cbSrcAndLine;
2712	}
2713	}
2714	break;
2715	/* Should take the XOR mask into account for the multi-bit AND mask. */
2716	case 8:
2717	for (uint32_t y = 0; y < cy; y++)
2718	{
2719	for (uint32_t x = 0; x < cx; )
2720	{
2721	uint8_t bDst = 0;
2722	uint8_t fBit = 1;
2723	do
2724	{
2725	uintptr_t const idxPal = pbSrc[x] * 3;
2726	if ((( pThis->last_palette[idxPal]
2727	\| (pThis->last_palette[idxPal] >> 8)
2728	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2729	bDst \|= fBit;
2730	fBit <<= 1;
2731	x++;
2732	} while (x < cx && (x & 7));
2733	pbDst[(x - 1) / 8] = bDst;
2734	}
2735	pbDst += cbDstAndLine;
2736	pbSrc += cbSrcAndLine;
2737	}
2738	break;
2739	case 15:
2740	for (uint32_t y = 0; y < cy; y++)
2741	{
2742	for (uint32_t x = 0; x < cx; )
2743	{
2744	uint8_t bDst = 0;
2745	uint8_t fBit = 1;
2746	do
2747	{
2748	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2749	bDst \|= fBit;
2750	fBit <<= 1;
2751	x++;
2752	} while (x < cx && (x & 7));
2753	pbDst[(x - 1) / 8] = bDst;
2754	}
2755	pbDst += cbDstAndLine;
2756	pbSrc += cbSrcAndLine;
2757	}
2758	break;
2759	case 16:
2760	for (uint32_t y = 0; y < cy; y++)
2761	{
2762	for (uint32_t x = 0; x < cx; )
2763	{
2764	uint8_t bDst = 0;
2765	uint8_t fBit = 1;
2766	do
2767	{
2768	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2769	bDst \|= fBit;
2770	fBit <<= 1;
2771	x++;
2772	} while (x < cx && (x & 7));
2773	pbDst[(x - 1) / 8] = bDst;
2774	}
2775	pbDst += cbDstAndLine;
2776	pbSrc += cbSrcAndLine;
2777	}
2778	break;
2779	case 24:
2780	for (uint32_t y = 0; y < cy; y++)
2781	{
2782	for (uint32_t x = 0; x < cx; )
2783	{
2784	uint8_t bDst = 0;
2785	uint8_t fBit = 1;
2786	do
2787	{
2788	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2789	bDst \|= fBit;
2790	fBit <<= 1;
2791	x++;
2792	} while (x < cx && (x & 7));
2793	pbDst[(x - 1) / 8] = bDst;
2794	}
2795	pbDst += cbDstAndLine;
2796	pbSrc += cbSrcAndLine;
2797	}
2798	break;
2799	case 32:
2800	for (uint32_t y = 0; y < cy; y++)
2801	{
2802	for (uint32_t x = 0; x < cx; )
2803	{
2804	uint8_t bDst = 0;
2805	uint8_t fBit = 1;
2806	do
2807	{
2808	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2809	bDst \|= fBit;
2810	fBit <<= 1;
2811	x++;
2812	} while (x < cx && (x & 7));
2813	pbDst[(x - 1) / 8] = bDst;
2814	}
2815	pbDst += cbDstAndLine;
2816	pbSrc += cbSrcAndLine;
2817	}
2818	break;
2819	default:
2820	RTMemFree(pbCopy);
2821	AssertFailedReturnVoid();
2822	}
2823
2824	/* Convert the XOR mask. */
2825	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2826	pbSrc = pbSrcXorMask;
2827	switch (pCursor->xorMaskDepth)
2828	{
2829	case 1:
2830	for (uint32_t y = 0; y < cy; y++)
2831	{
2832	for (uint32_t x = 0; x < cx; )
2833	{
2834	/* most significant bit is the left most one. */
2835	uint8_t bSrc = pbSrc[x / 8];
2836	do
2837	{
2838	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2839	bSrc <<= 1;
2840	x++;
2841	} while ((x & 7) && x < cx);
2842	}
2843	pbSrc += cbSrcXorLine;
2844	}
2845	break;
2846	case 8:
2847	for (uint32_t y = 0; y < cy; y++)
2848	{
2849	for (uint32_t x = 0; x < cx; x++)
2850	{
2851	uint32_t u = pThis->last_palette[pbSrc[x]];
2852	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2853	}
2854	pbSrc += cbSrcXorLine;
2855	}
2856	break;
2857	case 15: /* Src: RGB-5-5-5 */
2858	for (uint32_t y = 0; y < cy; y++)
2859	{
2860	for (uint32_t x = 0; x < cx; x++)
2861	{
2862	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2863	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2864	((uValue >> 5) & 0x1f) << 3,
2865	((uValue >> 10) & 0x1f) << 3, 0);
2866	}
2867	pbSrc += cbSrcXorLine;
2868	}
2869	break;
2870	case 16: /* Src: RGB-5-6-5 */
2871	for (uint32_t y = 0; y < cy; y++)
2872	{
2873	for (uint32_t x = 0; x < cx; x++)
2874	{
2875	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2876	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2877	((uValue >> 5) & 0x3f) << 2,
2878	((uValue >> 11) & 0x1f) << 3, 0);
2879	}
2880	pbSrc += cbSrcXorLine;
2881	}
2882	break;
2883	case 24:
2884	for (uint32_t y = 0; y < cy; y++)
2885	{
2886	for (uint32_t x = 0; x < cx; x++)
2887	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2888	pbSrc += cbSrcXorLine;
2889	}
2890	break;
2891	case 32:
2892	for (uint32_t y = 0; y < cy; y++)
2893	{
2894	for (uint32_t x = 0; x < cx; x++)
2895	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2896	pbSrc += cbSrcXorLine;
2897	}
2898	break;
2899	default:
2900	RTMemFree(pbCopy);
2901	AssertFailedReturnVoid();
2902	}
2903
2904	/*
2905	* Pass it to the frontend/whatever.
2906	*/
2907	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2908	}
2909
2910
2911	/**
2912	* Worker for vmsvgaR3FifoThread that handles an external command.
2913	*
2914	* @param pThis VGA device instance data.
2915	*/
2916	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2917	{
2918	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2919	switch (pThis->svga.u8FIFOExtCommand)
2920	{
2921	case VMSVGA_FIFO_EXTCMD_RESET:
2922	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2923	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2924	# ifdef VBOX_WITH_VMSVGA3D
2925	if (pThis->svga.f3DEnabled)
2926	{
2927	/* The 3d subsystem must be reset from the fifo thread. */
2928	vmsvga3dReset(pThis);
2929	}
2930	# endif
2931	break;
2932
2933	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2934	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2935	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2936	# ifdef VBOX_WITH_VMSVGA3D
2937	if (pThis->svga.f3DEnabled)
2938	{
2939	/* The 3d subsystem must be shut down from the fifo thread. */
2940	vmsvga3dTerminate(pThis);
2941	}
2942	# endif
2943	break;
2944
2945	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2946	{
2947	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2948	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2949	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2950	vmsvgaSaveExecFifo(pThis, pSSM);
2951	# ifdef VBOX_WITH_VMSVGA3D
2952	if (pThis->svga.f3DEnabled)
2953	vmsvga3dSaveExec(pThis, pSSM);
2954	# endif
2955	break;
2956	}
2957
2958	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2959	{
2960	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2961	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2962	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2963	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2964	# ifdef VBOX_WITH_VMSVGA3D
2965	if (pThis->svga.f3DEnabled)
2966	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2967	# endif
2968	break;
2969	}
2970
2971	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2972	{
2973	# ifdef VBOX_WITH_VMSVGA3D
2974	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2975	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2976	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2977	# endif
2978	break;
2979	}
2980
2981
2982	default:
2983	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2984	break;
2985	}
2986
2987	/*
2988	* Signal the end of the external command.
2989	*/
2990	pThis->svga.pvFIFOExtCmdParam = NULL;
2991	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2992	ASMMemoryFence(); /* paranoia^2 */
2993	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2994	AssertLogRelRC(rc);
2995	}
2996
2997	/**
2998	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2999	* doing a job on the FIFO thread (even when it's officially suspended).
3000	*
3001	* @returns VBox status code (fully asserted).
3002	* @param pThis VGA device instance data.
3003	* @param uExtCmd The command to execute on the FIFO thread.
3004	* @param pvParam Pointer to command parameters.
3005	* @param cMsWait The time to wait for the command, given in
3006	* milliseconds.
3007	*/
3008	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3009	{
3010	Assert(cMsWait >= RT_MS_1SEC * 5);
3011	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3012	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3013
3014	int rc;
3015	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
3016	PDMTHREADSTATE enmState = pThread->enmState;
3017	if (enmState == PDMTHREADSTATE_SUSPENDED)
3018	{
3019	/*
3020	* The thread is suspended, we have to temporarily wake it up so it can
3021	* perform the task.
3022	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3023	*/
3024	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3025	/* Post the request. */
3026	pThis->svga.fFifoExtCommandWakeup = true;
3027	pThis->svga.pvFIFOExtCmdParam = pvParam;
3028	pThis->svga.u8FIFOExtCommand = uExtCmd;
3029	ASMMemoryFence(); /* paranoia^3 */
3030
3031	/* Resume the thread. */
3032	rc = PDMR3ThreadResume(pThread);
3033	AssertLogRelRC(rc);
3034	if (RT_SUCCESS(rc))
3035	{
3036	/* Wait. Take care in case the semaphore was already posted (same as below). */
3037	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3038	if ( rc == VINF_SUCCESS
3039	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3040	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3041	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3042	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3043
3044	/* suspend the thread */
3045	pThis->svga.fFifoExtCommandWakeup = false;
3046	int rc2 = PDMR3ThreadSuspend(pThread);
3047	AssertLogRelRC(rc2);
3048	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3049	rc = rc2;
3050	}
3051	pThis->svga.fFifoExtCommandWakeup = false;
3052	pThis->svga.pvFIFOExtCmdParam = NULL;
3053	}
3054	else if (enmState == PDMTHREADSTATE_RUNNING)
3055	{
3056	/*
3057	* The thread is running, should only happen during reset and vmsvga3dsfc.
3058	* We ASSUME not racing code here, both wrt thread state and ext commands.
3059	*/
3060	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3061	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3062
3063	/* Post the request. */
3064	pThis->svga.pvFIFOExtCmdParam = pvParam;
3065	pThis->svga.u8FIFOExtCommand = uExtCmd;
3066	ASMMemoryFence(); /* paranoia^2 */
3067	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3068	AssertLogRelRC(rc);
3069
3070	/* Wait. Take care in case the semaphore was already posted (same as above). */
3071	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3072	if ( rc == VINF_SUCCESS
3073	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3074	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3075	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3076	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3077
3078	pThis->svga.pvFIFOExtCmdParam = NULL;
3079	}
3080	else
3081	{
3082	/*
3083	* Something is wrong with the thread!
3084	*/
3085	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3086	rc = VERR_INVALID_STATE;
3087	}
3088	return rc;
3089	}
3090
3091
3092	/**
3093	* Marks the FIFO non-busy, notifying any waiting EMTs.
3094	*
3095	* @param pThis The VGA state.
3096	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3097	* @param offFifoMin The start byte offset of the command FIFO.
3098	*/
3099	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3100	{
3101	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3102	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3103	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3104
3105	/* Wake up any waiting EMTs. */
3106	if (pSVGAState->cBusyDelayedEmts > 0)
3107	{
3108	#ifdef VMSVGA_USE_EMT_HALT_CODE
3109	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3110	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3111	if (idCpu != NIL_VMCPUID)
3112	{
3113	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3114	while (idCpu-- > 0)
3115	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3116	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3117	}
3118	#else
3119	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3120	AssertRC(rc2);
3121	#endif
3122	}
3123	}
3124
3125	/**
3126	* Reads (more) payload into the command buffer.
3127	*
3128	* @returns pbBounceBuf on success
3129	* @retval (void *)1 if the thread was requested to stop.
3130	* @retval NULL on FIFO error.
3131	*
3132	* @param cbPayloadReq The number of bytes of payload requested.
3133	* @param pFIFO The FIFO.
3134	* @param offCurrentCmd The FIFO byte offset of the current command.
3135	* @param offFifoMin The start byte offset of the command FIFO.
3136	* @param offFifoMax The end byte offset of the command FIFO.
3137	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3138	* always sufficient size.
3139	* @param pcbAlreadyRead How much payload we've already read into the bounce
3140	* buffer. (We will NEVER re-read anything.)
3141	* @param pThread The calling PDM thread handle.
3142	* @param pThis The VGA state.
3143	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3144	* statistics collection.
3145	*/
3146	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3147	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3148	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3149	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3150	{
3151	Assert(pbBounceBuf);
3152	Assert(pcbAlreadyRead);
3153	Assert(offFifoMin < offFifoMax);
3154	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3155	Assert(offFifoMax <= pThis->svga.cbFIFO);
3156
3157	/*
3158	* Check if the requested payload size has already been satisfied .
3159	* .
3160	* When called to read more, the caller is responsible for making sure the .
3161	* new command size (cbRequsted) never is smaller than what has already .
3162	* been read.
3163	*/
3164	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3165	if (cbPayloadReq <= cbAlreadyRead)
3166	{
3167	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3168	return pbBounceBuf;
3169	}
3170
3171	/*
3172	* Commands bigger than the fifo buffer are invalid.
3173	*/
3174	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3175	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3176	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3177	NULL);
3178
3179	/*
3180	* Move offCurrentCmd past the command dword.
3181	*/
3182	offCurrentCmd += sizeof(uint32_t);
3183	if (offCurrentCmd >= offFifoMax)
3184	offCurrentCmd = offFifoMin;
3185
3186	/*
3187	* Do we have sufficient payload data available already?
3188	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3189	*/
3190	uint32_t cbAfter, cbBefore;
3191	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3192	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3193	if (offNextCmd >= offCurrentCmd)
3194	{
3195	if (RT_LIKELY(offNextCmd < offFifoMax))
3196	cbAfter = offNextCmd - offCurrentCmd;
3197	else
3198	{
3199	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3200	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3201	offNextCmd, offFifoMin, offFifoMax));
3202	cbAfter = offFifoMax - offCurrentCmd;
3203	}
3204	cbBefore = 0;
3205	}
3206	else
3207	{
3208	cbAfter = offFifoMax - offCurrentCmd;
3209	if (offNextCmd >= offFifoMin)
3210	cbBefore = offNextCmd - offFifoMin;
3211	else
3212	{
3213	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3214	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3215	offNextCmd, offFifoMin, offFifoMax));
3216	cbBefore = 0;
3217	}
3218	}
3219	if (cbAfter + cbBefore < cbPayloadReq)
3220	{
3221	/*
3222	* Insufficient, must wait for it to arrive.
3223	*/
3224	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3225	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3226	for (uint32_t i = 0;; i++)
3227	{
3228	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3229	{
3230	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3231	return (void *)(uintptr_t)1;
3232	}
3233	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3234	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3235
3236	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3237
3238	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3239	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3240	if (offNextCmd >= offCurrentCmd)
3241	{
3242	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3243	cbBefore = 0;
3244	}
3245	else
3246	{
3247	cbAfter = offFifoMax - offCurrentCmd;
3248	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3249	}
3250
3251	if (cbAfter + cbBefore >= cbPayloadReq)
3252	break;
3253	}
3254	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3255	}
3256
3257	/*
3258	* Copy out the memory and update what pcbAlreadyRead points to.
3259	*/
3260	if (cbAfter >= cbPayloadReq)
3261	memcpy(pbBounceBuf + cbAlreadyRead,
3262	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3263	cbPayloadReq - cbAlreadyRead);
3264	else
3265	{
3266	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3267	if (cbAlreadyRead < cbAfter)
3268	{
3269	memcpy(pbBounceBuf + cbAlreadyRead,
3270	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3271	cbAfter - cbAlreadyRead);
3272	cbAlreadyRead = cbAfter;
3273	}
3274	memcpy(pbBounceBuf + cbAlreadyRead,
3275	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3276	cbPayloadReq - cbAlreadyRead);
3277	}
3278	*pcbAlreadyRead = cbPayloadReq;
3279	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3280	return pbBounceBuf;
3281	}
3282
3283
3284	/**
3285	* Sends cursor position and visibility information from the FIFO to the front-end.
3286	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3287	*/
3288	static uint32_t
3289	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3290	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3291	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3292	{
3293	/*
3294	* Check if the cursor update counter has changed and try get a stable
3295	* set of values if it has. This is race-prone, especially consindering
3296	* the screen ID, but little we can do about that.
3297	*/
3298	uint32_t x, y, fVisible, idScreen;
3299	for (uint32_t i = 0; ; i++)
3300	{
3301	x = pFIFO[SVGA_FIFO_CURSOR_X];
3302	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3303	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3304	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3305	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3306	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3307	\|\| i > 3)
3308	break;
3309	if (i == 0)
3310	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3311	ASMNopPause();
3312	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3313	}
3314
3315	/*
3316	* Check if anything has changed, as calling into pDrv is not light-weight.
3317	*/
3318	if ( *pxLast == x
3319	&& *pyLast == y
3320	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3321	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3322	else
3323	{
3324	/*
3325	* Detected changes.
3326	*
3327	* We handle global, not per-screen visibility information by sending
3328	* pfnVBVAMousePointerShape without shape data.
3329	*/
3330	*pxLast = x;
3331	*pyLast = y;
3332	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3333	if (idScreen != SVGA_ID_INVALID)
3334	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3335	else if (*pfLastVisible != fVisible)
3336	{
3337	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3338	*pfLastVisible = fVisible;
3339	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3340	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3341	}
3342	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3343	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3344	}
3345
3346	/*
3347	* Update done. Signal this to the guest.
3348	*/
3349	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3350
3351	return uCursorUpdateCount;
3352	}
3353
3354
3355	/**
3356	* Checks if there is work to be done, either cursor updating or FIFO commands.
3357	*
3358	* @returns true if pending work, false if not.
3359	* @param pFIFO The FIFO to examine.
3360	* @param uLastCursorCount The last cursor update counter value.
3361	*/
3362	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3363	{
3364	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3365	return true;
3366
3367	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3368	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3369	return true;
3370
3371	return false;
3372	}
3373
3374
3375	/**
3376	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3377	*
3378	* @param pThis The VGA state.
3379	*/
3380	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3381	{
3382	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3383	to recheck it before doing the signalling. */
3384	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3385	AssertReturnVoid(pFIFO);
3386	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3387	&& pThis->svga.fFIFOThreadSleeping)
3388	{
3389	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3390	AssertRC(rc);
3391	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3392	}
3393	}
3394
3395
3396	/* The async FIFO handling thread. */
3397	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3398	{
3399	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3400	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3401	int rc;
3402
3403	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3404	return VINF_SUCCESS;
3405
3406	/*
3407	* Special mode where we only execute an external command and the go back
3408	* to being suspended. Currently, all ext cmds ends up here, with the reset
3409	* one also being eligble for runtime execution further down as well.
3410	*/
3411	if (pThis->svga.fFifoExtCommandWakeup)
3412	{
3413	vmsvgaR3FifoHandleExtCmd(pThis);
3414	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3415	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3416	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3417	else
3418	vmsvgaR3FifoHandleExtCmd(pThis);
3419	return VINF_SUCCESS;
3420	}
3421
3422
3423	/*
3424	* Signal the semaphore to make sure we don't wait for 250ms after a
3425	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3426	*/
3427	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3428
3429	/*
3430	* Allocate a bounce buffer for command we get from the FIFO.
3431	* (All code must return via the end of the function to free this buffer.)
3432	*/
3433	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3434	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3435
3436	/*
3437	* Polling/sleep interval config.
3438	*
3439	* We wait for an a short interval if the guest has recently given us work
3440	* to do, but the interval increases the longer we're kept idle. Once we've
3441	* reached the refresh timer interval, we'll switch to extended waits,
3442	* depending on it or the guest to kick us into action when needed.
3443	*
3444	* Should the refresh time go fishing, we'll just continue increasing the
3445	* sleep length till we reaches the 250 ms max after about 16 seconds.
3446	*/
3447	RTMSINTERVAL const cMsMinSleep = 16;
3448	RTMSINTERVAL const cMsIncSleep = 2;
3449	RTMSINTERVAL const cMsMaxSleep = 250;
3450	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3451	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3452
3453	/*
3454	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3455	*
3456	* Initialize with values that will detect an update from the guest.
3457	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3458	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3459	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3460	*/
3461	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3462	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3463	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3464	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3465	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3466
3467	/*
3468	* The FIFO loop.
3469	*/
3470	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3471	bool fBadOrDisabledFifo = false;
3472	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3473	{
3474	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3475	/*
3476	* Should service the run loop every so often.
3477	*/
3478	if (pThis->svga.f3DEnabled)
3479	vmsvga3dCocoaServiceRunLoop();
3480	# endif
3481
3482	/*
3483	* Unless there's already work pending, go to sleep for a short while.
3484	* (See polling/sleep interval config above.)
3485	*/
3486	if ( fBadOrDisabledFifo
3487	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3488	{
3489	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3490	Assert(pThis->cMilliesRefreshInterval > 0);
3491	if (cMsSleep < pThis->cMilliesRefreshInterval)
3492	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3493	else
3494	{
3495	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3496	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3497	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3498	# endif
3499	if ( !fBadOrDisabledFifo
3500	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3501	rc = VINF_SUCCESS;
3502	else
3503	{
3504	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3505	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3506	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3507	}
3508	}
3509	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3510	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3511	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3512	{
3513	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3514	break;
3515	}
3516	}
3517	else
3518	rc = VINF_SUCCESS;
3519	fBadOrDisabledFifo = false;
3520	if (rc == VERR_TIMEOUT)
3521	{
3522	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3523	{
3524	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3525	continue;
3526	}
3527	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3528
3529	Log(("vmsvgaFIFOLoop: timeout\n"));
3530	}
3531	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3532	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3533	cMsSleep = cMsMinSleep;
3534
3535	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3536	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3537	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3538
3539	/*
3540	* Handle external commands (currently only reset).
3541	*/
3542	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3543	{
3544	vmsvgaR3FifoHandleExtCmd(pThis);
3545	continue;
3546	}
3547
3548	/*
3549	* The device must be enabled and configured.
3550	*/
3551	if ( !pThis->svga.fEnabled
3552	\|\| !pThis->svga.fConfigured)
3553	{
3554	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3555	fBadOrDisabledFifo = true;
3556	cMsSleep = cMsMaxSleep; /* cheat */
3557	continue;
3558	}
3559
3560	/*
3561	* Get and check the min/max values. We ASSUME that they will remain
3562	* unchanged while we process requests. A further ASSUMPTION is that
3563	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3564	* we don't read it back while in the loop.
3565	*/
3566	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3567	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3568	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3569	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3570	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3571	\|\| offFifoMax <= offFifoMin
3572	\|\| offFifoMax > pThis->svga.cbFIFO
3573	\|\| (offFifoMax & 3) != 0
3574	\|\| (offFifoMin & 3) != 0
3575	\|\| offCurrentCmd < offFifoMin
3576	\|\| offCurrentCmd > offFifoMax))
3577	{
3578	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3579	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3580	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3581	fBadOrDisabledFifo = true;
3582	continue;
3583	}
3584	RT_UNTRUSTED_VALIDATED_FENCE();
3585	if (RT_UNLIKELY(offCurrentCmd & 3))
3586	{
3587	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3588	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3589	offCurrentCmd &= ~UINT32_C(3);
3590	}
3591
3592	/*
3593	* Update the cursor position before we start on the FIFO commands.
3594	*/
3595	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3596	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3597	{
3598	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3599	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3600	{ /* halfways likely */ }
3601	else
3602	{
3603	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3604	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3605	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3606	}
3607	}
3608
3609	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3610	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3611	*
3612	* Will break out of the switch on failure.
3613	* Will restart and quit the loop if the thread was requested to stop.
3614	*
3615	* @param a_PtrVar Request variable pointer.
3616	* @param a_Type Request typedef (not pointer) for casting.
3617	* @param a_cbPayloadReq How much payload to fetch.
3618	* @remarks Accesses a bunch of variables in the current scope!
3619	*/
3620	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3621	if (1) { \
3622	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3623	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3624	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3625	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3626	} else do {} while (0)
3627	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3628	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3629	* buffer after figuring out the actual command size.
3630	*
3631	* Will break out of the switch on failure.
3632	*
3633	* @param a_PtrVar Request variable pointer.
3634	* @param a_Type Request typedef (not pointer) for casting.
3635	* @param a_cbPayloadReq How much payload to fetch.
3636	* @remarks Accesses a bunch of variables in the current scope!
3637	*/
3638	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3639	if (1) { \
3640	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3641	} else do {} while (0)
3642
3643	/*
3644	* Mark the FIFO as busy.
3645	*/
3646	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3647	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3648	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3649
3650	/*
3651	* Execute all queued FIFO commands.
3652	* Quit if pending external command or changes in the thread state.
3653	*/
3654	bool fDone = false;
3655	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3656	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3657	{
3658	uint32_t cbPayload = 0;
3659	uint32_t u32IrqStatus = 0;
3660
3661	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3662
3663	/* First check any pending actions. */
3664	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3665	{
3666	vmsvgaChangeMode(pThis);
3667	# ifdef VBOX_WITH_VMSVGA3D
3668	if (pThis->svga.p3dState != NULL)
3669	vmsvga3dChangeMode(pThis);
3670	# endif
3671	}
3672
3673	/* Check for pending external commands (reset). */
3674	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3675	break;
3676
3677	/*
3678	* Process the command.
3679	*/
3680	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3681	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3682	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3683	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3684	switch (enmCmdId)
3685	{
3686	case SVGA_CMD_INVALID_CMD:
3687	/* Nothing to do. */
3688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3689	break;
3690
3691	case SVGA_CMD_FENCE:
3692	{
3693	SVGAFifoCmdFence *pCmdFence;
3694	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3695	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3696	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3697	{
3698	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3699	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3700
3701	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3702	{
3703	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3704	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3705	}
3706	else
3707	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3708	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3709	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3710	{
3711	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3712	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3713	}
3714	}
3715	else
3716	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3717	break;
3718	}
3719	case SVGA_CMD_UPDATE:
3720	case SVGA_CMD_UPDATE_VERBOSE:
3721	{
3722	SVGAFifoCmdUpdate *pUpdate;
3723	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3724	if (enmCmdId == SVGA_CMD_UPDATE)
3725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3726	else
3727	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3728	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3729	/** @todo Multiple screens? */
3730	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3731	AssertBreak(pScreen);
3732	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3733	break;
3734	}
3735
3736	case SVGA_CMD_DEFINE_CURSOR:
3737	{
3738	/* Followed by bitmap data. */
3739	SVGAFifoCmdDefineCursor *pCursor;
3740	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3741	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3742
3743	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3744	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3745	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3746	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3747	AssertBreak(pCursor->andMaskDepth <= 32);
3748	AssertBreak(pCursor->xorMaskDepth <= 32);
3749	RT_UNTRUSTED_VALIDATED_FENCE();
3750
3751	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3752	uint32_t cbAndMask = cbAndLine * pCursor->height;
3753	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3754	uint32_t cbXorMask = cbXorLine * pCursor->height;
3755	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3756
3757	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3758	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3759	break;
3760	}
3761
3762	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3763	{
3764	/* Followed by bitmap data. */
3765	uint32_t cbCursorShape, cbAndMask;
3766	uint8_t *pCursorCopy;
3767	uint32_t cbCmd;
3768
3769	SVGAFifoCmdDefineAlphaCursor *pCursor;
3770	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3771	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3772
3773	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3774
3775	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3776	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3777	RT_UNTRUSTED_VALIDATED_FENCE();
3778
3779	/* Refetch the bitmap data as well. */
3780	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3781	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3782	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3783
3784	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3785	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3786	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3787	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3788
3789	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3790	AssertBreak(pCursorCopy);
3791
3792	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3793	memset(pCursorCopy, 0xff, cbAndMask);
3794	/* Colour data */
3795	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3796
3797	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3798	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3799	break;
3800	}
3801
3802	case SVGA_CMD_ESCAPE:
3803	{
3804	/* Followed by nsize bytes of data. */
3805	SVGAFifoCmdEscape *pEscape;
3806	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3807	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3808
3809	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3810	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3811	RT_UNTRUSTED_VALIDATED_FENCE();
3812	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3813	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3814
3815	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3816	{
3817	AssertBreak(pEscape->size >= sizeof(uint32_t));
3818	RT_UNTRUSTED_VALIDATED_FENCE();
3819	uint32_t cmd = (uint32_t )(pEscape + 1);
3820	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3821
3822	switch (cmd)
3823	{
3824	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3825	{
3826	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3827	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3828	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3829
3830	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3831	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3832	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3833
3834	RT_NOREF_PV(pVideoCmd);
3835	break;
3836
3837	}
3838
3839	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3840	{
3841	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3842	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3843	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3844	RT_NOREF_PV(pVideoCmd);
3845	break;
3846	}
3847
3848	default:
3849	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3850	break;
3851	}
3852	}
3853	else
3854	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3855
3856	break;
3857	}
3858	# ifdef VBOX_WITH_VMSVGA3D
3859	case SVGA_CMD_DEFINE_GMR2:
3860	{
3861	SVGAFifoCmdDefineGMR2 *pCmd;
3862	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3863	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3864	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3865
3866	/* Validate current GMR id. */
3867	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3868	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3869	RT_UNTRUSTED_VALIDATED_FENCE();
3870
3871	if (!pCmd->numPages)
3872	{
3873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3874	vmsvgaGMRFree(pThis, pCmd->gmrId);
3875	}
3876	else
3877	{
3878	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3879	if (pGMR->cMaxPages)
3880	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3881
3882	/* Not sure if we should always free the descriptor, but for simplicity
3883	we do so if the new size is smaller than the current. */
3884	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3885	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3886	vmsvgaGMRFree(pThis, pCmd->gmrId);
3887
3888	pGMR->cMaxPages = pCmd->numPages;
3889	/* The rest is done by the REMAP_GMR2 command. */
3890	}
3891	break;
3892	}
3893
3894	case SVGA_CMD_REMAP_GMR2:
3895	{
3896	/* Followed by page descriptors or guest ptr. */
3897	SVGAFifoCmdRemapGMR2 *pCmd;
3898	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3899	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3900
3901	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3902	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3903	RT_UNTRUSTED_VALIDATED_FENCE();
3904
3905	/* Calculate the size of what comes after next and fetch it. */
3906	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3907	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3908	cbCmd += sizeof(SVGAGuestPtr);
3909	else
3910	{
3911	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3912	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3913	{
3914	cbCmd += cbPageDesc;
3915	pCmd->numPages = 1;
3916	}
3917	else
3918	{
3919	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3920	cbCmd += cbPageDesc * pCmd->numPages;
3921	}
3922	}
3923	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3924
3925	/* Validate current GMR id and size. */
3926	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3927	RT_UNTRUSTED_VALIDATED_FENCE();
3928	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3929	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3930	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3931	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3932
3933	if (pCmd->numPages == 0)
3934	break;
3935
3936	/** @todo Move to a separate function vmsvgaGMRRemap() */
3937
3938	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3939	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3940
3941	/*
3942	* We flatten the existing descriptors into a page array, overwrite the
3943	* pages specified in this command and then recompress the descriptor.
3944	*/
3945	/** @todo Optimize the GMR remap algorithm! */
3946
3947	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3948	uint64_t *paNewPage64 = NULL;
3949	if (pGMR->paDesc)
3950	{
3951	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3952
3953	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3954	AssertBreak(paNewPage64);
3955
3956	uint32_t idxPage = 0;
3957	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3958	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3959	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3960	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3961	RT_UNTRUSTED_VALIDATED_FENCE();
3962	}
3963
3964	/* Free the old GMR if present. */
3965	if (pGMR->paDesc)
3966	RTMemFree(pGMR->paDesc);
3967
3968	/* Allocate the maximum amount possible (everything non-continuous) */
3969	PVMSVGAGMRDESCRIPTOR paDescs;
3970	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3971	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3972
3973	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3974	{
3975	/** @todo */
3976	AssertFailed();
3977	pGMR->numDescriptors = 0;
3978	}
3979	else
3980	{
3981	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3982	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3983	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3984
3985	if (paNewPage64)
3986	{
3987	/* Overwrite the old page array with the new page values. */
3988	if (fGCPhys64)
3989	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3990	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3991	else
3992	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3993	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3994
3995	/* Use the updated page array instead of the command data. */
3996	fGCPhys64 = true;
3997	paPages64 = paNewPage64;
3998	pCmd->numPages = cNewTotalPages;
3999	}
4000
4001	/* The first page. */
4002	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4003	* applied to paNewPage64. */
4004	RTGCPHYS GCPhys;
4005	if (fGCPhys64)
4006	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4007	else
4008	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4009	paDescs[0].GCPhys = GCPhys;
4010	paDescs[0].numPages = 1;
4011
4012	/* Subsequent pages. */
4013	uint32_t iDescriptor = 0;
4014	for (uint32_t i = 1; i < pCmd->numPages; i++)
4015	{
4016	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4017	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4018	else
4019	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4020
4021	/* Continuous physical memory? */
4022	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4023	{
4024	Assert(paDescs[iDescriptor].numPages);
4025	paDescs[iDescriptor].numPages++;
4026	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4027	}
4028	else
4029	{
4030	iDescriptor++;
4031	paDescs[iDescriptor].GCPhys = GCPhys;
4032	paDescs[iDescriptor].numPages = 1;
4033	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4034	}
4035	}
4036
4037	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4038	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4039	pGMR->numDescriptors = iDescriptor + 1;
4040	}
4041
4042	if (paNewPage64)
4043	RTMemFree(paNewPage64);
4044
4045	# ifdef DEBUG_GMR_ACCESS
4046	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4047	# endif
4048	break;
4049	}
4050	# endif // VBOX_WITH_VMSVGA3D
4051	case SVGA_CMD_DEFINE_SCREEN:
4052	{
4053	/* The size of this command is specified by the guest and depends on capabilities. */
4054	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4055
4056	SVGAFifoCmdDefineScreen *pCmd;
4057	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4058	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4059	RT_UNTRUSTED_VALIDATED_FENCE();
4060
4061	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4062	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4063	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4064
4065	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4066	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4067	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4068
4069	uint32_t const idScreen = pCmd->screen.id;
4070	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4071
4072	uint32_t const uWidth = pCmd->screen.size.width;
4073	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4074
4075	uint32_t const uHeight = pCmd->screen.size.height;
4076	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4077
4078	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4079	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4080	AssertBreak(cbWidth <= cbPitch);
4081
4082	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4083	AssertBreak(uScreenOffset < pThis->vram_size);
4084
4085	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4086	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4087	AssertBreak( (uHeight == 0 && cbPitch == 0)
4088	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4089	RT_UNTRUSTED_VALIDATED_FENCE();
4090
4091	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4092
4093	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4094
4095	pScreen->fDefined = true;
4096	pScreen->fModified = true;
4097	pScreen->fuScreen = pCmd->screen.flags;
4098	pScreen->idScreen = idScreen;
4099	if (!fBlank)
4100	{
4101	AssertBreak(uWidth > 0 && uHeight > 0);
4102
4103	pScreen->xOrigin = pCmd->screen.root.x;
4104	pScreen->yOrigin = pCmd->screen.root.y;
4105	pScreen->cWidth = uWidth;
4106	pScreen->cHeight = uHeight;
4107	pScreen->offVRAM = uScreenOffset;
4108	pScreen->cbPitch = cbPitch;
4109	pScreen->cBpp = 32;
4110	}
4111	else
4112	{
4113	/* Keep old values. */
4114	}
4115
4116	pThis->svga.fGFBRegisters = false;
4117	vmsvgaChangeMode(pThis);
4118	break;
4119	}
4120
4121	case SVGA_CMD_DESTROY_SCREEN:
4122	{
4123	SVGAFifoCmdDestroyScreen *pCmd;
4124	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4125	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4126
4127	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4128
4129	uint32_t const idScreen = pCmd->screenId;
4130	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4131	RT_UNTRUSTED_VALIDATED_FENCE();
4132
4133	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4134	pScreen->fModified = true;
4135	pScreen->fDefined = false;
4136	pScreen->idScreen = idScreen;
4137
4138	vmsvgaChangeMode(pThis);
4139	break;
4140	}
4141
4142	case SVGA_CMD_DEFINE_GMRFB:
4143	{
4144	SVGAFifoCmdDefineGMRFB *pCmd;
4145	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4146	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4147
4148	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4149	pSVGAState->GMRFB.ptr = pCmd->ptr;
4150	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4151	pSVGAState->GMRFB.format = pCmd->format;
4152	break;
4153	}
4154
4155	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4156	{
4157	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4158	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4159	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4160
4161	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4162	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4163
4164	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4165	RT_UNTRUSTED_VALIDATED_FENCE();
4166
4167	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4168	AssertBreak(pScreen);
4169
4170	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4171	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4172
4173	/* Clip destRect to the screen dimensions. */
4174	SVGASignedRect screenRect;
4175	screenRect.left = 0;
4176	screenRect.top = 0;
4177	screenRect.right = pScreen->cWidth;
4178	screenRect.bottom = pScreen->cHeight;
4179	SVGASignedRect clipRect = pCmd->destRect;
4180	vmsvgaClipRect(&screenRect, &clipRect);
4181	RT_UNTRUSTED_VALIDATED_FENCE();
4182
4183	uint32_t const width = clipRect.right - clipRect.left;
4184	uint32_t const height = clipRect.bottom - clipRect.top;
4185
4186	if ( width == 0
4187	\|\| height == 0)
4188	break; /* Nothing to do. */
4189
4190	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4191	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4192
4193	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4194	* Prepare parameters for vmsvgaGMRTransfer.
4195	*/
4196	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4197
4198	/* Destination: host buffer which describes the screen 0 VRAM.
4199	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4200	*/
4201	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4202	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4203	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4204	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4205	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4206	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4207	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4208	+ cbScanline * clipRect.top;
4209	int32_t const cbHstPitch = cbScanline;
4210
4211	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4212	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4213	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4214	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4215	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4216
4217	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4218	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4219	gstPtr, offGst, cbGstPitch,
4220	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4221	AssertRC(rc);
4222	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4223	break;
4224	}
4225
4226	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4227	{
4228	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4229	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4230	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4231
4232	/* Note! This can fetch 3d render results as well!! */
4233	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4234	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4235
4236	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4237	RT_UNTRUSTED_VALIDATED_FENCE();
4238
4239	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4240	AssertBreak(pScreen);
4241
4242	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4243	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4244
4245	/* Clip destRect to the screen dimensions. */
4246	SVGASignedRect screenRect;
4247	screenRect.left = 0;
4248	screenRect.top = 0;
4249	screenRect.right = pScreen->cWidth;
4250	screenRect.bottom = pScreen->cHeight;
4251	SVGASignedRect clipRect = pCmd->srcRect;
4252	vmsvgaClipRect(&screenRect, &clipRect);
4253	RT_UNTRUSTED_VALIDATED_FENCE();
4254
4255	uint32_t const width = clipRect.right - clipRect.left;
4256	uint32_t const height = clipRect.bottom - clipRect.top;
4257
4258	if ( width == 0
4259	\|\| height == 0)
4260	break; /* Nothing to do. */
4261
4262	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4263	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4264
4265	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4266	* Prepare parameters for vmsvgaGMRTransfer.
4267	*/
4268	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4269
4270	/* Source: host buffer which describes the screen 0 VRAM.
4271	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4272	*/
4273	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4274	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4275	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4276	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4277	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4278	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4279	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4280	+ cbScanline * clipRect.top;
4281	int32_t const cbHstPitch = cbScanline;
4282
4283	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4284	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4285	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4286	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4287	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4288
4289	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4290	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4291	gstPtr, offGst, cbGstPitch,
4292	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4293	AssertRC(rc);
4294	break;
4295	}
4296
4297	case SVGA_CMD_ANNOTATION_FILL:
4298	{
4299	SVGAFifoCmdAnnotationFill *pCmd;
4300	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4301	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4302
4303	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4304	pSVGAState->colorAnnotation = pCmd->color;
4305	break;
4306	}
4307
4308	case SVGA_CMD_ANNOTATION_COPY:
4309	{
4310	SVGAFifoCmdAnnotationCopy *pCmd;
4311	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4312	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4313
4314	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4315	AssertFailed();
4316	break;
4317	}
4318
4319	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4320
4321	default:
4322	# ifdef VBOX_WITH_VMSVGA3D
4323	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4324	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4325	{
4326	RT_UNTRUSTED_VALIDATED_FENCE();
4327
4328	/* All 3d commands start with a common header, which defines the size of the command. */
4329	SVGA3dCmdHeader *pHdr;
4330	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4331	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4332	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4333	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4334
4335	if (RT_LIKELY(pThis->svga.f3DEnabled))
4336	{ /* likely */ }
4337	else
4338	{
4339	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4340	break;
4341	}
4342
4343	/**
4344	* Check that the 3D command has at least a_cbMin of payload bytes after the
4345	* header. Will break out of the switch if it doesn't.
4346	*/
4347	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4348	if (1) { \
4349	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4350	RT_UNTRUSTED_VALIDATED_FENCE(); \
4351	} else do {} while (0)
4352	switch ((int)enmCmdId)
4353	{
4354	case SVGA_3D_CMD_SURFACE_DEFINE:
4355	{
4356	uint32_t cMipLevels;
4357	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4358	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4359	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4360
4361	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4362	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4363	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4364	# ifdef DEBUG_GMR_ACCESS
4365	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4366	# endif
4367	break;
4368	}
4369
4370	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4371	{
4372	uint32_t cMipLevels;
4373	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4374	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4375	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4376
4377	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4378	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4379	pCmd->multisampleCount, pCmd->autogenFilter,
4380	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4381	break;
4382	}
4383
4384	case SVGA_3D_CMD_SURFACE_DESTROY:
4385	{
4386	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4387	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4388	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4389	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4390	break;
4391	}
4392
4393	case SVGA_3D_CMD_SURFACE_COPY:
4394	{
4395	uint32_t cCopyBoxes;
4396	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4397	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4398	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4399
4400	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4401	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4402	break;
4403	}
4404
4405	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4406	{
4407	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4408	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4409	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4410
4411	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4412	break;
4413	}
4414
4415	case SVGA_3D_CMD_SURFACE_DMA:
4416	{
4417	uint32_t cCopyBoxes;
4418	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4419	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4420	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4421
4422	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4423	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4424	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4425	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4426	break;
4427	}
4428
4429	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4430	{
4431	uint32_t cRects;
4432	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4433	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4434	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4435
4436	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4437	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4438	break;
4439	}
4440
4441	case SVGA_3D_CMD_CONTEXT_DEFINE:
4442	{
4443	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4444	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4446
4447	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4448	break;
4449	}
4450
4451	case SVGA_3D_CMD_CONTEXT_DESTROY:
4452	{
4453	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4454	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4455	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4456
4457	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4458	break;
4459	}
4460
4461	case SVGA_3D_CMD_SETTRANSFORM:
4462	{
4463	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4464	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4465	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4466
4467	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4468	break;
4469	}
4470
4471	case SVGA_3D_CMD_SETZRANGE:
4472	{
4473	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4474	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4475	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4476
4477	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4478	break;
4479	}
4480
4481	case SVGA_3D_CMD_SETRENDERSTATE:
4482	{
4483	uint32_t cRenderStates;
4484	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4485	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4486	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4487
4488	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4489	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4490	break;
4491	}
4492
4493	case SVGA_3D_CMD_SETRENDERTARGET:
4494	{
4495	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4496	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4497	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4498
4499	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4500	break;
4501	}
4502
4503	case SVGA_3D_CMD_SETTEXTURESTATE:
4504	{
4505	uint32_t cTextureStates;
4506	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4507	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4508	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4509
4510	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4511	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4512	break;
4513	}
4514
4515	case SVGA_3D_CMD_SETMATERIAL:
4516	{
4517	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4518	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4520
4521	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4522	break;
4523	}
4524
4525	case SVGA_3D_CMD_SETLIGHTDATA:
4526	{
4527	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4528	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4530
4531	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4532	break;
4533	}
4534
4535	case SVGA_3D_CMD_SETLIGHTENABLED:
4536	{
4537	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4538	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4539	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4540
4541	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4542	break;
4543	}
4544
4545	case SVGA_3D_CMD_SETVIEWPORT:
4546	{
4547	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4548	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4549	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4550
4551	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_SETCLIPPLANE:
4556	{
4557	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4560
4561	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4562	break;
4563	}
4564
4565	case SVGA_3D_CMD_CLEAR:
4566	{
4567	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4568	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4569	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4570
4571	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4572	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4573	break;
4574	}
4575
4576	case SVGA_3D_CMD_PRESENT:
4577	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4578	{
4579	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4580	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4582	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4583	else
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4585
4586	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4587
4588	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4589	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4590	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4591	break;
4592	}
4593
4594	case SVGA_3D_CMD_SHADER_DEFINE:
4595	{
4596	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4597	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4598	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4599
4600	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4601	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4602	break;
4603	}
4604
4605	case SVGA_3D_CMD_SHADER_DESTROY:
4606	{
4607	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4608	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4609	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4610
4611	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4612	break;
4613	}
4614
4615	case SVGA_3D_CMD_SET_SHADER:
4616	{
4617	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4618	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4619	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4620
4621	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4622	break;
4623	}
4624
4625	case SVGA_3D_CMD_SET_SHADER_CONST:
4626	{
4627	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4628	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4629	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4630
4631	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4632	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4633	break;
4634	}
4635
4636	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4637	{
4638	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4639	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4641
4642	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4643	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4644	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4645	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4646	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4647
4648	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4649	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4650
4651	RT_UNTRUSTED_VALIDATED_FENCE();
4652
4653	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4654	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4655	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4656
4657	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4658	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4659	pNumRange, cVertexDivisor, pVertexDivisor);
4660	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4661	break;
4662	}
4663
4664	case SVGA_3D_CMD_SETSCISSORRECT:
4665	{
4666	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4667	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4669
4670	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4671	break;
4672	}
4673
4674	case SVGA_3D_CMD_BEGIN_QUERY:
4675	{
4676	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4677	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4679
4680	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4681	break;
4682	}
4683
4684	case SVGA_3D_CMD_END_QUERY:
4685	{
4686	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4687	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4689
4690	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4695	{
4696	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4699
4700	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4705	{
4706	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4709
4710	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4711	break;
4712	}
4713
4714	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4715	/* context id + surface id? */
4716	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4717	break;
4718	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4719	/* context id + surface id? */
4720	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4721	break;
4722
4723	default:
4724	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4725	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4726	break;
4727	}
4728	}
4729	else
4730	# endif // VBOX_WITH_VMSVGA3D
4731	{
4732	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4733	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4734	}
4735	}
4736
4737	/* Go to the next slot */
4738	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4739	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4740	if (offCurrentCmd >= offFifoMax)
4741	{
4742	offCurrentCmd -= offFifoMax - offFifoMin;
4743	Assert(offCurrentCmd >= offFifoMin);
4744	Assert(offCurrentCmd < offFifoMax);
4745	}
4746	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4748
4749	/*
4750	* Raise IRQ if required. Must enter the critical section here
4751	* before making final decisions here, otherwise cubebench and
4752	* others may end up waiting forever.
4753	*/
4754	if ( u32IrqStatus
4755	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4756	{
4757	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4758	AssertRC(rc2);
4759
4760	/* FIFO progress might trigger an interrupt. */
4761	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4762	{
4763	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4764	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4765	}
4766
4767	/* Unmasked IRQ pending? */
4768	if (pThis->svga.u32IrqMask & u32IrqStatus)
4769	{
4770	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4771	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4772	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4773	}
4774
4775	PDMCritSectLeave(&pThis->CritSect);
4776	}
4777	}
4778
4779	/* If really done, clear the busy flag. */
4780	if (fDone)
4781	{
4782	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4783	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4784	}
4785	}
4786
4787	/*
4788	* Free the bounce buffer. (There are no returns above!)
4789	*/
4790	RTMemFree(pbBounceBuf);
4791
4792	return VINF_SUCCESS;
4793	}
4794
4795	/**
4796	* Free the specified GMR
4797	*
4798	* @param pThis VGA device instance data.
4799	* @param idGMR GMR id
4800	*/
4801	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4802	{
4803	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4804
4805	/* Free the old descriptor if present. */
4806	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4807	if ( pGMR->numDescriptors
4808	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4809	{
4810	# ifdef DEBUG_GMR_ACCESS
4811	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4812	# endif
4813
4814	Assert(pGMR->paDesc);
4815	RTMemFree(pGMR->paDesc);
4816	pGMR->paDesc = NULL;
4817	pGMR->numDescriptors = 0;
4818	pGMR->cbTotal = 0;
4819	pGMR->cMaxPages = 0;
4820	}
4821	Assert(!pGMR->cMaxPages);
4822	Assert(!pGMR->cbTotal);
4823	}
4824
4825	/**
4826	* Copy between a GMR and a host memory buffer.
4827	*
4828	* @returns VBox status code.
4829	* @param pThis VGA device instance data.
4830	* @param enmTransferType Transfer type (read/write)
4831	* @param pbHstBuf Host buffer pointer (valid)
4832	* @param cbHstBuf Size of host buffer (valid)
4833	* @param offHst Host buffer offset of the first scanline
4834	* @param cbHstPitch Destination buffer pitch
4835	* @param gstPtr GMR description
4836	* @param offGst Guest buffer offset of the first scanline
4837	* @param cbGstPitch Guest buffer pitch
4838	* @param cbWidth Width in bytes to copy
4839	* @param cHeight Number of scanllines to copy
4840	*/
4841	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4842	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4843	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4844	uint32_t cbWidth, uint32_t cHeight)
4845	{
4846	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4847	int rc;
4848
4849	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4850	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4851	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4852	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4853	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4854
4855	PGMR pGMR;
4856	uint32_t cbGmr; /* The GMR size in bytes. */
4857	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4858	{
4859	pGMR = NULL;
4860	cbGmr = pThis->vram_size;
4861	}
4862	else
4863	{
4864	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4865	RT_UNTRUSTED_VALIDATED_FENCE();
4866	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4867	cbGmr = pGMR->cbTotal;
4868	}
4869
4870	/*
4871	* GMR
4872	*/
4873	/* Calculate GMR offset of the data to be copied. */
4874	AssertMsgReturn(gstPtr.offset < cbGmr,
4875	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4876	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4877	VERR_INVALID_PARAMETER);
4878	RT_UNTRUSTED_VALIDATED_FENCE();
4879	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4880	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4881	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4882	VERR_INVALID_PARAMETER);
4883	RT_UNTRUSTED_VALIDATED_FENCE();
4884	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4885
4886	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4887	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4888	AssertMsgReturn(cbGmrScanline != 0,
4889	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4890	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4891	VERR_INVALID_PARAMETER);
4892	RT_UNTRUSTED_VALIDATED_FENCE();
4893	AssertMsgReturn(cbWidth <= cbGmrScanline,
4894	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4895	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4896	VERR_INVALID_PARAMETER);
4897	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4898	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4899	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4900	VERR_INVALID_PARAMETER);
4901	RT_UNTRUSTED_VALIDATED_FENCE();
4902
4903	/* How many bytes are available for the data in the GMR. */
4904	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4905
4906	/* How many scanlines would fit into the available data. */
4907	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4908	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4909	if (cbWidth <= cbGmrLastScanline)
4910	++cGmrScanlines;
4911
4912	if (cHeight > cGmrScanlines)
4913	cHeight = cGmrScanlines;
4914
4915	AssertMsgReturn(cHeight > 0,
4916	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4917	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4918	VERR_INVALID_PARAMETER);
4919	RT_UNTRUSTED_VALIDATED_FENCE();
4920
4921	/*
4922	* Host buffer.
4923	*/
4924	AssertMsgReturn(offHst < cbHstBuf,
4925	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4926	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4927	VERR_INVALID_PARAMETER);
4928
4929	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4930	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4931	AssertMsgReturn(cbHstScanline != 0,
4932	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4933	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4934	VERR_INVALID_PARAMETER);
4935	AssertMsgReturn(cbWidth <= cbHstScanline,
4936	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4937	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4938	VERR_INVALID_PARAMETER);
4939	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4940	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4941	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4942	VERR_INVALID_PARAMETER);
4943
4944	/* How many bytes are available for the data in the buffer. */
4945	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4946
4947	/* How many scanlines would fit into the available data. */
4948	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4949	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4950	if (cbWidth <= cbHstLastScanline)
4951	++cHstScanlines;
4952
4953	if (cHeight > cHstScanlines)
4954	cHeight = cHstScanlines;
4955
4956	AssertMsgReturn(cHeight > 0,
4957	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4958	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4959	VERR_INVALID_PARAMETER);
4960
4961	uint8_t *pbHst = pbHstBuf + offHst;
4962
4963	/* Shortcut for the framebuffer. */
4964	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4965	{
4966	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4967
4968	uint8_t const *pbSrc;
4969	int32_t cbSrcPitch;
4970	uint8_t *pbDst;
4971	int32_t cbDstPitch;
4972
4973	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4974	{
4975	pbSrc = pbHst;
4976	cbSrcPitch = cbHstPitch;
4977	pbDst = pbGst;
4978	cbDstPitch = cbGstPitch;
4979	}
4980	else
4981	{
4982	pbSrc = pbGst;
4983	cbSrcPitch = cbGstPitch;
4984	pbDst = pbHst;
4985	cbDstPitch = cbHstPitch;
4986	}
4987
4988	if ( cbWidth == (uint32_t)cbGstPitch
4989	&& cbGstPitch == cbHstPitch)
4990	{
4991	/* Entire scanlines, positive pitch. */
4992	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4993	}
4994	else
4995	{
4996	for (uint32_t i = 0; i < cHeight; ++i)
4997	{
4998	memcpy(pbDst, pbSrc, cbWidth);
4999
5000	pbDst += cbDstPitch;
5001	pbSrc += cbSrcPitch;
5002	}
5003	}
5004	return VINF_SUCCESS;
5005	}
5006
5007	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5008	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5009
5010	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5011	uint32_t iDesc = 0; /* Index in the descriptor array. */
5012	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5013	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5014	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5015	for (uint32_t i = 0; i < cHeight; ++i)
5016	{
5017	uint32_t cbCurrentWidth = cbWidth;
5018	uint32_t offGmrCurrent = offGmrScanline;
5019	uint8_t *pbCurrentHost = pbHstScanline;
5020
5021	/* Find the right descriptor */
5022	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5023	{
5024	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5025	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5026	++iDesc;
5027	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5028	}
5029
5030	while (cbCurrentWidth)
5031	{
5032	uint32_t cbToCopy;
5033
5034	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5035	{
5036	cbToCopy = cbCurrentWidth;
5037	}
5038	else
5039	{
5040	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5041	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5042	}
5043
5044	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5045
5046	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5047
5048	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5049	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5050	else
5051	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5052	AssertRCBreak(rc);
5053
5054	cbCurrentWidth -= cbToCopy;
5055	offGmrCurrent += cbToCopy;
5056	pbCurrentHost += cbToCopy;
5057
5058	/* Go to the next descriptor if there's anything left. */
5059	if (cbCurrentWidth)
5060	{
5061	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5062	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5063	++iDesc;
5064	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5065	}
5066	}
5067
5068	offGmrScanline += cbGstPitch;
5069	pbHstScanline += cbHstPitch;
5070	}
5071
5072	return VINF_SUCCESS;
5073	}
5074
5075
5076	/**
5077	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5078	*
5079	* @param pSizeSrc Source surface dimensions.
5080	* @param pSizeDest Destination surface dimensions.
5081	* @param pBox Coordinates to be clipped.
5082	*/
5083	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5084	const SVGA3dSize *pSizeDest,
5085	SVGA3dCopyBox *pBox)
5086	{
5087	/* Src x, w */
5088	if (pBox->srcx > pSizeSrc->width)
5089	pBox->srcx = pSizeSrc->width;
5090	if (pBox->w > pSizeSrc->width - pBox->srcx)
5091	pBox->w = pSizeSrc->width - pBox->srcx;
5092
5093	/* Src y, h */
5094	if (pBox->srcy > pSizeSrc->height)
5095	pBox->srcy = pSizeSrc->height;
5096	if (pBox->h > pSizeSrc->height - pBox->srcy)
5097	pBox->h = pSizeSrc->height - pBox->srcy;
5098
5099	/* Src z, d */
5100	if (pBox->srcz > pSizeSrc->depth)
5101	pBox->srcz = pSizeSrc->depth;
5102	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5103	pBox->d = pSizeSrc->depth - pBox->srcz;
5104
5105	/* Dest x, w */
5106	if (pBox->x > pSizeDest->width)
5107	pBox->x = pSizeDest->width;
5108	if (pBox->w > pSizeDest->width - pBox->x)
5109	pBox->w = pSizeDest->width - pBox->x;
5110
5111	/* Dest y, h */
5112	if (pBox->y > pSizeDest->height)
5113	pBox->y = pSizeDest->height;
5114	if (pBox->h > pSizeDest->height - pBox->y)
5115	pBox->h = pSizeDest->height - pBox->y;
5116
5117	/* Dest z, d */
5118	if (pBox->z > pSizeDest->depth)
5119	pBox->z = pSizeDest->depth;
5120	if (pBox->d > pSizeDest->depth - pBox->z)
5121	pBox->d = pSizeDest->depth - pBox->z;
5122	}
5123
5124	/**
5125	* Unsigned coordinates in pBox. Clip to [0; pSize).
5126	*
5127	* @param pSize Source surface dimensions.
5128	* @param pBox Coordinates to be clipped.
5129	*/
5130	void vmsvgaClipBox(const SVGA3dSize *pSize,
5131	SVGA3dBox *pBox)
5132	{
5133	/* x, w */
5134	if (pBox->x > pSize->width)
5135	pBox->x = pSize->width;
5136	if (pBox->w > pSize->width - pBox->x)
5137	pBox->w = pSize->width - pBox->x;
5138
5139	/* y, h */
5140	if (pBox->y > pSize->height)
5141	pBox->y = pSize->height;
5142	if (pBox->h > pSize->height - pBox->y)
5143	pBox->h = pSize->height - pBox->y;
5144
5145	/* z, d */
5146	if (pBox->z > pSize->depth)
5147	pBox->z = pSize->depth;
5148	if (pBox->d > pSize->depth - pBox->z)
5149	pBox->d = pSize->depth - pBox->z;
5150	}
5151
5152	/**
5153	* Clip.
5154	*
5155	* @param pBound Bounding rectangle.
5156	* @param pRect Rectangle to be clipped.
5157	*/
5158	void vmsvgaClipRect(SVGASignedRect const *pBound,
5159	SVGASignedRect *pRect)
5160	{
5161	int32_t left;
5162	int32_t top;
5163	int32_t right;
5164	int32_t bottom;
5165
5166	/* Right order. */
5167	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5168	if (pRect->left < pRect->right)
5169	{
5170	left = pRect->left;
5171	right = pRect->right;
5172	}
5173	else
5174	{
5175	left = pRect->right;
5176	right = pRect->left;
5177	}
5178	if (pRect->top < pRect->bottom)
5179	{
5180	top = pRect->top;
5181	bottom = pRect->bottom;
5182	}
5183	else
5184	{
5185	top = pRect->bottom;
5186	bottom = pRect->top;
5187	}
5188
5189	if (left < pBound->left)
5190	left = pBound->left;
5191	if (right < pBound->left)
5192	right = pBound->left;
5193
5194	if (left > pBound->right)
5195	left = pBound->right;
5196	if (right > pBound->right)
5197	right = pBound->right;
5198
5199	if (top < pBound->top)
5200	top = pBound->top;
5201	if (bottom < pBound->top)
5202	bottom = pBound->top;
5203
5204	if (top > pBound->bottom)
5205	top = pBound->bottom;
5206	if (bottom > pBound->bottom)
5207	bottom = pBound->bottom;
5208
5209	pRect->left = left;
5210	pRect->right = right;
5211	pRect->top = top;
5212	pRect->bottom = bottom;
5213	}
5214
5215	/**
5216	* Unblock the FIFO I/O thread so it can respond to a state change.
5217	*
5218	* @returns VBox status code.
5219	* @param pDevIns The VGA device instance.
5220	* @param pThread The send thread.
5221	*/
5222	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5223	{
5224	RT_NOREF(pDevIns);
5225	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5226	Log(("vmsvgaFIFOLoopWakeUp\n"));
5227	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5228	}
5229
5230	/**
5231	* Enables or disables dirty page tracking for the framebuffer
5232	*
5233	* @param pThis VGA device instance data.
5234	* @param fTraces Enable/disable traces
5235	*/
5236	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5237	{
5238	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5239	&& !fTraces)
5240	{
5241	//Assert(pThis->svga.fTraces);
5242	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5243	return;
5244	}
5245
5246	pThis->svga.fTraces = fTraces;
5247	if (pThis->svga.fTraces)
5248	{
5249	unsigned cbFrameBuffer = pThis->vram_size;
5250
5251	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5252	/** @todo How does this work with screens? */
5253	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5254	{
5255	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5256	Assert(pThis->svga.cbScanline);
5257	#endif
5258	/* Hardware enabled; return real framebuffer size .*/
5259	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5260	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5261	}
5262
5263	if (!pThis->svga.fVRAMTracking)
5264	{
5265	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5266	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5267	pThis->svga.fVRAMTracking = true;
5268	}
5269	}
5270	else
5271	{
5272	if (pThis->svga.fVRAMTracking)
5273	{
5274	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5275	vgaR3UnregisterVRAMHandler(pThis);
5276	pThis->svga.fVRAMTracking = false;
5277	}
5278	}
5279	}
5280
5281	/**
5282	* @callback_method_impl{FNPCIIOREGIONMAP}
5283	*/
5284	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5285	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5286	{
5287	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5288	int rc;
5289	RT_NOREF(pPciDev);
5290	Assert(pPciDev == pDevIns->apPciDevs[0]);
5291
5292	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5293	if (enmType == PCI_ADDRESS_SPACE_IO)
5294	{
5295	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5296	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5297	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5298	if (RT_FAILURE(rc))
5299	return rc;
5300	if (pThis->fR0Enabled)
5301	{
5302	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5303	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5304	if (RT_FAILURE(rc))
5305	return rc;
5306	}
5307	if (pThis->fGCEnabled)
5308	{
5309	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5310	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5311	if (RT_FAILURE(rc))
5312	return rc;
5313	}
5314
5315	pThis->svga.BasePort = GCPhysAddress;
5316	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5317	}
5318	else
5319	{
5320	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5321	if (GCPhysAddress != NIL_RTGCPHYS)
5322	{
5323	/*
5324	* Mapping the FIFO RAM.
5325	*/
5326	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5327	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5328	AssertRC(rc);
5329
5330	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5331	if (RT_SUCCESS(rc))
5332	{
5333	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5334	# ifdef DEBUG_FIFO_ACCESS
5335	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5336	# else
5337	GCPhysAddress + PAGE_SIZE - 1,
5338	# endif
5339	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5340	"VMSVGA FIFO");
5341	AssertRC(rc);
5342	}
5343	# endif
5344	if (RT_SUCCESS(rc))
5345	{
5346	pThis->svga.GCPhysFIFO = GCPhysAddress;
5347	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5348	}
5349	}
5350	else
5351	{
5352	Assert(pThis->svga.GCPhysFIFO);
5353	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5354	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5355	AssertRC(rc);
5356	# endif
5357	pThis->svga.GCPhysFIFO = 0;
5358	}
5359	}
5360	return VINF_SUCCESS;
5361	}
5362
5363	# ifdef VBOX_WITH_VMSVGA3D
5364
5365	/**
5366	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5367	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5368	*
5369	* @param pThis The VGA device instance data.
5370	* @param sid Either UINT32_MAX or the ID of a specific
5371	* surface. If UINT32_MAX is used, all surfaces
5372	* are processed.
5373	*/
5374	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5375	{
5376	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5377	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5378	}
5379
5380
5381	/**
5382	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5383	*/
5384	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5385	{
5386	/* There might be a specific surface ID at the start of the
5387	arguments, if not show all surfaces. */
5388	uint32_t sid = UINT32_MAX;
5389	if (pszArgs)
5390	pszArgs = RTStrStripL(pszArgs);
5391	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5392	sid = RTStrToUInt32(pszArgs);
5393
5394	/* Verbose or terse display, we default to verbose. */
5395	bool fVerbose = true;
5396	if (RTStrIStr(pszArgs, "terse"))
5397	fVerbose = false;
5398
5399	/* The size of the ascii art (x direction, y is 3/4 of x). */
5400	uint32_t cxAscii = 80;
5401	if (RTStrIStr(pszArgs, "gigantic"))
5402	cxAscii = 300;
5403	else if (RTStrIStr(pszArgs, "huge"))
5404	cxAscii = 180;
5405	else if (RTStrIStr(pszArgs, "big"))
5406	cxAscii = 132;
5407	else if (RTStrIStr(pszArgs, "normal"))
5408	cxAscii = 80;
5409	else if (RTStrIStr(pszArgs, "medium"))
5410	cxAscii = 64;
5411	else if (RTStrIStr(pszArgs, "small"))
5412	cxAscii = 48;
5413	else if (RTStrIStr(pszArgs, "tiny"))
5414	cxAscii = 24;
5415
5416	/* Y invert the image when producing the ASCII art. */
5417	bool fInvY = false;
5418	if (RTStrIStr(pszArgs, "invy"))
5419	fInvY = true;
5420
5421	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5422	}
5423
5424
5425	/**
5426	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5427	*/
5428	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5429	{
5430	/* pszArg = "sid[>dir]"
5431	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5432	*/
5433	char *pszBitmapPath = NULL;
5434	uint32_t sid = UINT32_MAX;
5435	if (pszArgs)
5436	pszArgs = RTStrStripL(pszArgs);
5437	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5438	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5439	if ( pszBitmapPath
5440	&& *pszBitmapPath == '>')
5441	++pszBitmapPath;
5442
5443	const bool fVerbose = true;
5444	const uint32_t cxAscii = 0; /* No ASCII */
5445	const bool fInvY = false; /* Do not invert. */
5446	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5447	}
5448
5449
5450	/**
5451	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5452	*/
5453	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5454	{
5455	/* There might be a specific surface ID at the start of the
5456	arguments, if not show all contexts. */
5457	uint32_t sid = UINT32_MAX;
5458	if (pszArgs)
5459	pszArgs = RTStrStripL(pszArgs);
5460	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5461	sid = RTStrToUInt32(pszArgs);
5462
5463	/* Verbose or terse display, we default to verbose. */
5464	bool fVerbose = true;
5465	if (RTStrIStr(pszArgs, "terse"))
5466	fVerbose = false;
5467
5468	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5469	}
5470
5471	# endif /* VBOX_WITH_VMSVGA3D */
5472
5473	/**
5474	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5475	*/
5476	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5477	{
5478	RT_NOREF(pszArgs);
5479	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5480	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5481	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5482
5483	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5484	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5485	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5486	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5487	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5488	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5489	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5490	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5491	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5492	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5493	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5494	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5495	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5496	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5497	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5498	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5499	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5500	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5501	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5502	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5503	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5504	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5505	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5506
5507	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5508	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5509	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5510	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5511
5512	# ifdef VBOX_WITH_VMSVGA3D
5513	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5514	# endif
5515	if (pThis->pDrv)
5516	{
5517	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5518	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5519	}
5520	}
5521
5522	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5523	*/
5524	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5525	{
5526	RT_NOREF(uPass);
5527
5528	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5529	int rc;
5530
5531	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5532	{
5533	uint32_t cScreens = 0;
5534	rc = SSMR3GetU32(pSSM, &cScreens);
5535	AssertRCReturn(rc, rc);
5536	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5537	("cScreens=%#x\n", cScreens),
5538	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5539
5540	for (uint32_t i = 0; i < cScreens; ++i)
5541	{
5542	VMSVGASCREENOBJECT screen;
5543	RT_ZERO(screen);
5544
5545	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5546	AssertLogRelRCReturn(rc, rc);
5547
5548	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5549	{
5550	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5551	*pScreen = screen;
5552	pScreen->fModified = true;
5553	}
5554	else
5555	{
5556	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5557	}
5558	}
5559	}
5560	else
5561	{
5562	/* Try to setup at least the first screen. */
5563	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5564	pScreen->fDefined = true;
5565	pScreen->fModified = true;
5566	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5567	pScreen->idScreen = 0;
5568	pScreen->xOrigin = 0;
5569	pScreen->yOrigin = 0;
5570	pScreen->offVRAM = pThis->svga.uScreenOffset;
5571	pScreen->cbPitch = pThis->svga.cbScanline;
5572	pScreen->cWidth = pThis->svga.uWidth;
5573	pScreen->cHeight = pThis->svga.uHeight;
5574	pScreen->cBpp = pThis->svga.uBpp;
5575	}
5576
5577	return VINF_SUCCESS;
5578	}
5579
5580	/**
5581	* @copydoc FNSSMDEVLOADEXEC
5582	*/
5583	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5584	{
5585	RT_NOREF(uPass);
5586	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5587	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5588	int rc;
5589
5590	/* Load our part of the VGAState */
5591	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5592	AssertRCReturn(rc, rc);
5593
5594	/* Load the VGA framebuffer. */
5595	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5596	uint32_t cbVgaFramebuffer = _32K;
5597	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5598	{
5599	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5600	AssertRCReturn(rc, rc);
5601	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5602	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5603	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5604	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5605	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5606	}
5607	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5608	AssertRCReturn(rc, rc);
5609	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5610	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5611	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5612	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5613
5614	/* Load the VMSVGA state. */
5615	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5616	AssertRCReturn(rc, rc);
5617
5618	/* Load the active cursor bitmaps. */
5619	if (pSVGAState->Cursor.fActive)
5620	{
5621	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5622	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5623
5624	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5625	AssertRCReturn(rc, rc);
5626	}
5627
5628	/* Load the GMR state. */
5629	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5630	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5631	{
5632	rc = SSMR3GetU32(pSSM, &cGMR);
5633	AssertRCReturn(rc, rc);
5634	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5635	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5636	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5637	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5638	}
5639
5640	if (pThis->svga.cGMR != cGMR)
5641	{
5642	/* Reallocate GMR array. */
5643	Assert(pSVGAState->paGMR != NULL);
5644	RTMemFree(pSVGAState->paGMR);
5645	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5646	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5647	pThis->svga.cGMR = cGMR;
5648	}
5649
5650	for (uint32_t i = 0; i < cGMR; ++i)
5651	{
5652	PGMR pGMR = &pSVGAState->paGMR[i];
5653
5654	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5655	AssertRCReturn(rc, rc);
5656
5657	if (pGMR->numDescriptors)
5658	{
5659	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5660	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5661	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5662
5663	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5664	{
5665	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5666	AssertRCReturn(rc, rc);
5667	}
5668	}
5669	}
5670
5671	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5672	vmsvga3dPowerOn(pThis);
5673	# endif
5674
5675	VMSVGA_STATE_LOAD LoadState;
5676	LoadState.pSSM = pSSM;
5677	LoadState.uVersion = uVersion;
5678	LoadState.uPass = uPass;
5679	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5680	AssertLogRelRCReturn(rc, rc);
5681
5682	return VINF_SUCCESS;
5683	}
5684
5685	/**
5686	* Reinit the video mode after the state has been loaded.
5687	*/
5688	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5689	{
5690	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5691	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5692
5693	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5694
5695	/* Set the active cursor. */
5696	if (pSVGAState->Cursor.fActive)
5697	{
5698	int rc;
5699
5700	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5701	true,
5702	true,
5703	pSVGAState->Cursor.xHotspot,
5704	pSVGAState->Cursor.yHotspot,
5705	pSVGAState->Cursor.width,
5706	pSVGAState->Cursor.height,
5707	pSVGAState->Cursor.pData);
5708	AssertRC(rc);
5709	}
5710	return VINF_SUCCESS;
5711	}
5712
5713	/**
5714	* Portion of SVGA state which must be saved in the FIFO thread.
5715	*/
5716	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5717	{
5718	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5719	int rc;
5720
5721	/* Save the screen objects. */
5722	/* Count defined screen object. */
5723	uint32_t cScreens = 0;
5724	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5725	{
5726	if (pSVGAState->aScreens[i].fDefined)
5727	++cScreens;
5728	}
5729
5730	rc = SSMR3PutU32(pSSM, cScreens);
5731	AssertLogRelRCReturn(rc, rc);
5732
5733	for (uint32_t i = 0; i < cScreens; ++i)
5734	{
5735	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5736
5737	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5738	AssertLogRelRCReturn(rc, rc);
5739	}
5740	return VINF_SUCCESS;
5741	}
5742
5743	/**
5744	* @copydoc FNSSMDEVSAVEEXEC
5745	*/
5746	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5747	{
5748	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5749	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5750	int rc;
5751
5752	/* Save our part of the VGAState */
5753	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5754	AssertLogRelRCReturn(rc, rc);
5755
5756	/* Save the framebuffer backup. */
5757	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5758	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5759	AssertLogRelRCReturn(rc, rc);
5760
5761	/* Save the VMSVGA state. */
5762	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5763	AssertLogRelRCReturn(rc, rc);
5764
5765	/* Save the active cursor bitmaps. */
5766	if (pSVGAState->Cursor.fActive)
5767	{
5768	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5769	AssertLogRelRCReturn(rc, rc);
5770	}
5771
5772	/* Save the GMR state */
5773	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5774	AssertLogRelRCReturn(rc, rc);
5775	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5776	{
5777	PGMR pGMR = &pSVGAState->paGMR[i];
5778
5779	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5780	AssertLogRelRCReturn(rc, rc);
5781
5782	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5783	{
5784	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5785	AssertLogRelRCReturn(rc, rc);
5786	}
5787	}
5788
5789	/*
5790	* Must save some state (3D in particular) in the FIFO thread.
5791	*/
5792	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5793	AssertLogRelRCReturn(rc, rc);
5794
5795	return VINF_SUCCESS;
5796	}
5797
5798	/**
5799	* Destructor for PVMSVGAR3STATE structure.
5800	*
5801	* @param pThis The VGA instance.
5802	* @param pSVGAState Pointer to the structure. It is not deallocated.
5803	*/
5804	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5805	{
5806	#ifndef VMSVGA_USE_EMT_HALT_CODE
5807	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5808	{
5809	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5810	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5811	}
5812	#endif
5813
5814	if (pSVGAState->Cursor.fActive)
5815	{
5816	RTMemFree(pSVGAState->Cursor.pData);
5817	pSVGAState->Cursor.pData = NULL;
5818	pSVGAState->Cursor.fActive = false;
5819	}
5820
5821	if (pSVGAState->paGMR)
5822	{
5823	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5824	if (pSVGAState->paGMR[i].paDesc)
5825	RTMemFree(pSVGAState->paGMR[i].paDesc);
5826
5827	RTMemFree(pSVGAState->paGMR);
5828	pSVGAState->paGMR = NULL;
5829	}
5830	}
5831
5832	/**
5833	* Constructor for PVMSVGAR3STATE structure.
5834	*
5835	* @returns VBox status code.
5836	* @param pThis The VGA instance.
5837	* @param pSVGAState Pointer to the structure. It is already allocated.
5838	*/
5839	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5840	{
5841	int rc = VINF_SUCCESS;
5842	RT_ZERO(*pSVGAState);
5843
5844	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5845	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5846
5847	#ifndef VMSVGA_USE_EMT_HALT_CODE
5848	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5849	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5850	AssertRCReturn(rc, rc);
5851	#endif
5852
5853	return rc;
5854	}
5855
5856	/**
5857	* Initializes the host capabilities: registers and FIFO.
5858	*
5859	* @returns VBox status code.
5860	* @param pThis The VGA instance.
5861	*/
5862	static void vmsvgaInitCaps(PVGASTATE pThis)
5863	{
5864	/* Register caps. */
5865	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5866	\| SVGA_CAP_GMR2
5867	\| SVGA_CAP_CURSOR
5868	\| SVGA_CAP_CURSOR_BYPASS_2
5869	\| SVGA_CAP_EXTENDED_FIFO
5870	\| SVGA_CAP_IRQMASK
5871	\| SVGA_CAP_PITCHLOCK
5872	\| SVGA_CAP_TRACES
5873	\| SVGA_CAP_SCREEN_OBJECT_2
5874	\| SVGA_CAP_ALPHA_CURSOR;
5875	# ifdef VBOX_WITH_VMSVGA3D
5876	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5877	# endif
5878
5879	/* Clear the FIFO. */
5880	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5881
5882	/* Setup FIFO capabilities. */
5883	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5884	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5885	\| SVGA_FIFO_CAP_GMR2
5886	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5887	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5888	\| SVGA_FIFO_CAP_RESERVE
5889	\| SVGA_FIFO_CAP_PITCHLOCK;
5890
5891	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5892	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5893	}
5894
5895	# ifdef VBOX_WITH_VMSVGA3D
5896	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5897	static const char * const g_apszVmSvgaDevCapNames[] =
5898	{
5899	"x3D", /* = 0 */
5900	"xMAX_LIGHTS",
5901	"xMAX_TEXTURES",
5902	"xMAX_CLIP_PLANES",
5903	"xVERTEX_SHADER_VERSION",
5904	"xVERTEX_SHADER",
5905	"xFRAGMENT_SHADER_VERSION",
5906	"xFRAGMENT_SHADER",
5907	"xMAX_RENDER_TARGETS",
5908	"xS23E8_TEXTURES",
5909	"xS10E5_TEXTURES",
5910	"xMAX_FIXED_VERTEXBLEND",
5911	"xD16_BUFFER_FORMAT",
5912	"xD24S8_BUFFER_FORMAT",
5913	"xD24X8_BUFFER_FORMAT",
5914	"xQUERY_TYPES",
5915	"xTEXTURE_GRADIENT_SAMPLING",
5916	"rMAX_POINT_SIZE",
5917	"xMAX_SHADER_TEXTURES",
5918	"xMAX_TEXTURE_WIDTH",
5919	"xMAX_TEXTURE_HEIGHT",
5920	"xMAX_VOLUME_EXTENT",
5921	"xMAX_TEXTURE_REPEAT",
5922	"xMAX_TEXTURE_ASPECT_RATIO",
5923	"xMAX_TEXTURE_ANISOTROPY",
5924	"xMAX_PRIMITIVE_COUNT",
5925	"xMAX_VERTEX_INDEX",
5926	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5927	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5928	"xMAX_VERTEX_SHADER_TEMPS",
5929	"xMAX_FRAGMENT_SHADER_TEMPS",
5930	"xTEXTURE_OPS",
5931	"xSURFACEFMT_X8R8G8B8",
5932	"xSURFACEFMT_A8R8G8B8",
5933	"xSURFACEFMT_A2R10G10B10",
5934	"xSURFACEFMT_X1R5G5B5",
5935	"xSURFACEFMT_A1R5G5B5",
5936	"xSURFACEFMT_A4R4G4B4",
5937	"xSURFACEFMT_R5G6B5",
5938	"xSURFACEFMT_LUMINANCE16",
5939	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5940	"xSURFACEFMT_ALPHA8",
5941	"xSURFACEFMT_LUMINANCE8",
5942	"xSURFACEFMT_Z_D16",
5943	"xSURFACEFMT_Z_D24S8",
5944	"xSURFACEFMT_Z_D24X8",
5945	"xSURFACEFMT_DXT1",
5946	"xSURFACEFMT_DXT2",
5947	"xSURFACEFMT_DXT3",
5948	"xSURFACEFMT_DXT4",
5949	"xSURFACEFMT_DXT5",
5950	"xSURFACEFMT_BUMPX8L8V8U8",
5951	"xSURFACEFMT_A2W10V10U10",
5952	"xSURFACEFMT_BUMPU8V8",
5953	"xSURFACEFMT_Q8W8V8U8",
5954	"xSURFACEFMT_CxV8U8",
5955	"xSURFACEFMT_R_S10E5",
5956	"xSURFACEFMT_R_S23E8",
5957	"xSURFACEFMT_RG_S10E5",
5958	"xSURFACEFMT_RG_S23E8",
5959	"xSURFACEFMT_ARGB_S10E5",
5960	"xSURFACEFMT_ARGB_S23E8",
5961	"xMISSING62",
5962	"xMAX_VERTEX_SHADER_TEXTURES",
5963	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5964	"xSURFACEFMT_V16U16",
5965	"xSURFACEFMT_G16R16",
5966	"xSURFACEFMT_A16B16G16R16",
5967	"xSURFACEFMT_UYVY",
5968	"xSURFACEFMT_YUY2",
5969	"xMULTISAMPLE_NONMASKABLESAMPLES",
5970	"xMULTISAMPLE_MASKABLESAMPLES",
5971	"xALPHATOCOVERAGE",
5972	"xSUPERSAMPLE",
5973	"xAUTOGENMIPMAPS",
5974	"xSURFACEFMT_NV12",
5975	"xSURFACEFMT_AYUV",
5976	"xMAX_CONTEXT_IDS",
5977	"xMAX_SURFACE_IDS",
5978	"xSURFACEFMT_Z_DF16",
5979	"xSURFACEFMT_Z_DF24",
5980	"xSURFACEFMT_Z_D24S8_INT",
5981	"xSURFACEFMT_BC4_UNORM",
5982	"xSURFACEFMT_BC5_UNORM", /* 83 */
5983	};
5984
5985	/**
5986	* Initializes the host 3D capabilities in FIFO.
5987	*
5988	* @returns VBox status code.
5989	* @param pThis The VGA instance.
5990	*/
5991	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5992	{
5993	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5994	bool fSavedBuffering = RTLogRelSetBuffering(true);
5995	SVGA3dCapsRecord *pCaps;
5996	SVGA3dCapPair *pData;
5997	uint32_t idxCap = 0;
5998
5999	/* 3d hardware version; latest and greatest */
6000	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6001	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6002
6003	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6004	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6005	pData = (SVGA3dCapPair *)&pCaps->data;
6006
6007	/* Fill out all 3d capabilities. */
6008	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6009	{
6010	uint32_t val = 0;
6011
6012	int rc = vmsvga3dQueryCaps(pThis, i, &val);
6013	if (RT_SUCCESS(rc))
6014	{
6015	pData[idxCap][0] = i;
6016	pData[idxCap][1] = val;
6017	idxCap++;
6018	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6019	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6020	else
6021	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6022	&g_apszVmSvgaDevCapNames[i][1]));
6023	}
6024	else
6025	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6026	}
6027	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6028	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6029
6030	/* Mark end of record array. */
6031	pCaps->header.length = 0;
6032
6033	RTLogRelSetBuffering(fSavedBuffering);
6034	}
6035
6036	# endif
6037
6038	/**
6039	* Resets the SVGA hardware state
6040	*
6041	* @returns VBox status code.
6042	* @param pDevIns The device instance.
6043	*/
6044	int vmsvgaReset(PPDMDEVINS pDevIns)
6045	{
6046	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6047	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6048
6049	/* Reset before init? */
6050	if (!pSVGAState)
6051	return VINF_SUCCESS;
6052
6053	Log(("vmsvgaReset\n"));
6054
6055	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6056	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6057	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6058
6059	/* Reset other stuff. */
6060	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6061	RT_ZERO(pThis->svga.au32ScratchRegion);
6062
6063	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6064	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6065
6066	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6067
6068	/* Initialize FIFO and register capabilities. */
6069	vmsvgaInitCaps(pThis);
6070
6071	# ifdef VBOX_WITH_VMSVGA3D
6072	if (pThis->svga.f3DEnabled)
6073	vmsvgaInitFifo3DCaps(pThis);
6074	# endif
6075
6076	/* VRAM tracking is enabled by default during bootup. */
6077	pThis->svga.fVRAMTracking = true;
6078	pThis->svga.fEnabled = false;
6079
6080	/* Invalidate current settings. */
6081	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6082	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6083	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6084	pThis->svga.cbScanline = 0;
6085	pThis->svga.u32PitchLock = 0;
6086
6087	return rc;
6088	}
6089
6090	/**
6091	* Cleans up the SVGA hardware state
6092	*
6093	* @returns VBox status code.
6094	* @param pDevIns The device instance.
6095	*/
6096	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6097	{
6098	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6099
6100	/*
6101	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6102	*/
6103	if (pThis->svga.pFIFOIOThread)
6104	{
6105	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6106	AssertLogRelRC(rc);
6107
6108	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
6109	AssertLogRelRC(rc);
6110	pThis->svga.pFIFOIOThread = NULL;
6111	}
6112
6113	/*
6114	* Destroy the special SVGA state.
6115	*/
6116	if (pThis->svga.pSvgaR3State)
6117	{
6118	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6119
6120	RTMemFree(pThis->svga.pSvgaR3State);
6121	pThis->svga.pSvgaR3State = NULL;
6122	}
6123
6124	/*
6125	* Free our resources residing in the VGA state.
6126	*/
6127	if (pThis->svga.pbVgaFrameBufferR3)
6128	{
6129	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6130	pThis->svga.pbVgaFrameBufferR3 = NULL;
6131	}
6132	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6133	{
6134	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6135	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6136	}
6137	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6138	{
6139	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6140	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6141	}
6142
6143	return VINF_SUCCESS;
6144	}
6145
6146	/**
6147	* Initialize the SVGA hardware state
6148	*
6149	* @returns VBox status code.
6150	* @param pDevIns The device instance.
6151	*/
6152	int vmsvgaInit(PPDMDEVINS pDevIns)
6153	{
6154	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6155	PVMSVGAR3STATE pSVGAState;
6156	PVM pVM = PDMDevHlpGetVM(pDevIns);
6157	int rc;
6158
6159	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6160	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6161
6162	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6163
6164	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6165	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6166	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6167
6168	/* Create event semaphore. */
6169	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6170
6171	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6172	if (RT_FAILURE(rc))
6173	{
6174	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6175	return rc;
6176	}
6177
6178	/* Create event semaphore. */
6179	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6180	if (RT_FAILURE(rc))
6181	{
6182	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6183	return rc;
6184	}
6185
6186	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6187	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6188
6189	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6190	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6191
6192	pSVGAState = pThis->svga.pSvgaR3State;
6193
6194	/* Initialize FIFO and register capabilities. */
6195	vmsvgaInitCaps(pThis);
6196
6197	# ifdef VBOX_WITH_VMSVGA3D
6198	if (pThis->svga.f3DEnabled)
6199	{
6200	rc = vmsvga3dInit(pThis);
6201	if (RT_FAILURE(rc))
6202	{
6203	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6204	pThis->svga.f3DEnabled = false;
6205	}
6206	}
6207	# endif
6208	/* VRAM tracking is enabled by default during bootup. */
6209	pThis->svga.fVRAMTracking = true;
6210
6211	/* Invalidate current settings. */
6212	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6213	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6214	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6215	pThis->svga.cbScanline = 0;
6216
6217	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6218	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6219	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6220	{
6221	pThis->svga.u32MaxWidth -= 256;
6222	pThis->svga.u32MaxHeight -= 256;
6223	}
6224	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6225
6226	# ifdef DEBUG_GMR_ACCESS
6227	/* Register the GMR access handler type. */
6228	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6229	vmsvgaR3GMRAccessHandler,
6230	NULL, NULL, NULL,
6231	NULL, NULL, NULL,
6232	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6233	AssertRCReturn(rc, rc);
6234	# endif
6235
6236	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6237	/* Register the FIFO access handler type. In addition to
6238	debugging FIFO access, this is also used to facilitate
6239	extended fifo thread sleeps. */
6240	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6241	# ifdef DEBUG_FIFO_ACCESS
6242	PGMPHYSHANDLERKIND_ALL,
6243	# else
6244	PGMPHYSHANDLERKIND_WRITE,
6245	# endif
6246	vmsvgaR3FIFOAccessHandler,
6247	NULL, NULL, NULL,
6248	NULL, NULL, NULL,
6249	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6250	AssertRCReturn(rc, rc);
6251	# endif
6252
6253	/* Create the async IO thread. */
6254	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6255	RTTHREADTYPE_IO, "VMSVGA FIFO");
6256	if (RT_FAILURE(rc))
6257	{
6258	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6259	return rc;
6260	}
6261
6262	/*
6263	* Statistics.
6264	*/
6265	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6266	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6267	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6268	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6269	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6270	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6271	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6272	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6273	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6274	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6275	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6276	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6277	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6278	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6279	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6280	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6281	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6282	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6283	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6284	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6285	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6286	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6287	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6288	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6289	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6290	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6291	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6292	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6293	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6294	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6295	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6296	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6297	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6298	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6299	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6300	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6301	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6302	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6303	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6304	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6305	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6306	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6307	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6308	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6309	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6310	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6311	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6312	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6313	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6314	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6315	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6316	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6317	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6318	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6319	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6320	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6321
6322	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6323	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6324	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6325	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6326	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6327	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6328	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6329	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6330	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6331	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6332	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6333	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6334	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6335	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6336	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6337	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6338	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6339	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6340	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6341	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6342	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6343	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6344	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6345	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6346	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6347	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6348	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6349	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6350	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6351	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6352	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6353	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6354
6355	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6356	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6357	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6358	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6359	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6360	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6361	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6362	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6363	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6364	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6365	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6366	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6367	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6368	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6369	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6370	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6371	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6372	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6373	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6374	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6375	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6376	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6377	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6378	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6379	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6380	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6381	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6382	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6383	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6384	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6385	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6386	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6387	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6388	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6389	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6390	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6391	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6392	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6393	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6394	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6395	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6396	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6397	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6398	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6399	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6400	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6401	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6402	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6403	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6404
6405	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6406	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6407	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6408	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6409	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6410	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6411	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6412	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6413	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6414	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6415	# endif
6416	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6417	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6418	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6419	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6420	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6421
6422	/*
6423	* Info handlers.
6424	*/
6425	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6426	# ifdef VBOX_WITH_VMSVGA3D
6427	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6428	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6429	"VMSVGA 3d surface details. "
6430	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6431	vmsvgaR3Info3dSurface);
6432	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6433	"VMSVGA 3d surface details and bitmap: "
6434	"sid[>dir]",
6435	vmsvgaR3Info3dSurfaceBmp);
6436	# endif
6437
6438	return VINF_SUCCESS;
6439	}
6440
6441	/**
6442	* Power On notification.
6443	*
6444	* @returns VBox status code.
6445	* @param pDevIns The device instance data.
6446	*
6447	* @remarks Caller enters the device critical section.
6448	*/
6449	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6450	{
6451	# ifdef VBOX_WITH_VMSVGA3D
6452	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6453	if (pThis->svga.f3DEnabled)
6454	{
6455	int rc = vmsvga3dPowerOn(pThis);
6456
6457	if (RT_SUCCESS(rc))
6458	{
6459	/* Initialize FIFO 3D capabilities. */
6460	vmsvgaInitFifo3DCaps(pThis);
6461	}
6462	}
6463	# else /* !VBOX_WITH_VMSVGA3D */
6464	RT_NOREF(pDevIns);
6465	# endif /* !VBOX_WITH_VMSVGA3D */
6466	}
6467
6468	#endif /* IN_RING3 */
6469

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 81754

Download in other formats: