DevVGA-SVGA.cpp@ 82050

Last change on this file since 82050 was 82050, checked in by vboxsync, 5 years ago
DevVGA: PDMCritSect -> PDMDevHlpCritSect. bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82050 2019-11-20 20:43:09Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
522	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
526	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
528	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
529	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
530	SSMFIELD_ENTRY( VMSVGAState, uWidth),
531	SSMFIELD_ENTRY( VMSVGAState, uHeight),
532	SSMFIELD_ENTRY( VMSVGAState, uBpp),
533	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
534	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
536	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
537	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
538	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
539	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
542	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
543	SSMFIELD_ENTRY_TERM()
544	};
545
546	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
547	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
548	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
549
550	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
551	{
552	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
553	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
554	&& pSVGAState
555	&& pSVGAState->aScreens[idScreen].fDefined)
556	{
557	return &pSVGAState->aScreens[idScreen];
558	}
559	return NULL;
560	}
561
562	#endif /* IN_RING3 */
563
564	#ifdef LOG_ENABLED
565
566	/**
567	* Index register string name lookup
568	*
569	* @returns Index register string or "UNKNOWN"
570	* @param pThis VMSVGA State
571	* @param idxReg The index register.
572	*/
573	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
574	{
575	switch (idxReg)
576	{
577	case SVGA_REG_ID: return "SVGA_REG_ID";
578	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
579	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
580	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
581	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
582	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
583	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
584	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
585	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
586	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
587	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
588	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
589	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
590	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
591	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
592	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
593	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
594	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
595	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
596	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
597	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
598	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
599	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
601	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
602	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
603	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
604	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
605	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
606	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
607	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
608	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
609	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
610	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
611	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
612	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
613	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
614	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
615	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
616	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
617	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
618	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
619	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
620	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
621	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
622	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
623	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
624	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
625	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
626	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
627
628	default:
629	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
630	return "SVGA_SCRATCH_BASE reg";
631	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
632	return "SVGA_PALETTE_BASE reg";
633	return "UNKNOWN";
634	}
635	}
636
637	#ifdef IN_RING3
638	/**
639	* FIFO command name lookup
640	*
641	* @returns FIFO command string or "UNKNOWN"
642	* @param u32Cmd FIFO command
643	*/
644	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
645	{
646	switch (u32Cmd)
647	{
648	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
649	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
650	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
651	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
652	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
653	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
654	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
655	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
656	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
657	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
658	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
659	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
660	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
661	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
662	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
663	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
664	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
665	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
666	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
667	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
668	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
669	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
670	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
671	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
672	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
673	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
674	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
675	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
676	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
677	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
678	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
679	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
680	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
681	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
682	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
683	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
684	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
685	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
686	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
687	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
688	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
689	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
690	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
691	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
692	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
693	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
694	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
695	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
696	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
697	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
698	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
699	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
700	default: return "UNKNOWN";
701	}
702	}
703	# endif /* IN_RING3 */
704
705	#endif /* LOG_ENABLED */
706
707	#ifdef IN_RING3
708	/**
709	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
710	*/
711	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
712	{
713	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
714
715	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
716	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
717
718	/** @todo Test how it interacts with multiple screen objects. */
719	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
720	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
721	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
722
723	if (x < uWidth)
724	{
725	pThis->svga.viewport.x = x;
726	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
727	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
728	}
729	else
730	{
731	pThis->svga.viewport.x = uWidth;
732	pThis->svga.viewport.cx = 0;
733	pThis->svga.viewport.xRight = uWidth;
734	}
735	if (y < uHeight)
736	{
737	pThis->svga.viewport.y = y;
738	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
739	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
740	pThis->svga.viewport.yHighWC = uHeight - y;
741	}
742	else
743	{
744	pThis->svga.viewport.y = uHeight;
745	pThis->svga.viewport.cy = 0;
746	pThis->svga.viewport.yLowWC = 0;
747	pThis->svga.viewport.yHighWC = 0;
748	}
749
750	# ifdef VBOX_WITH_VMSVGA3D
751	/*
752	* Now inform the 3D backend.
753	*/
754	if (pThis->svga.f3DEnabled)
755	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
756	# else
757	RT_NOREF(OldViewport);
758	# endif
759	}
760	#endif /* IN_RING3 */
761
762	/**
763	* Read port register
764	*
765	* @returns VBox status code.
766	* @param pDevIns The device instance.
767	* @param pThis VMSVGA State
768	* @param pu32 Where to store the read value
769	*/
770	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
771	{
772	int rc = VINF_SUCCESS;
773	*pu32 = 0;
774
775	/* Rough index register validation. */
776	uint32_t idxReg = pThis->svga.u32IndexReg;
777	#if !defined(IN_RING3) && defined(VBOX_STRICT)
778	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
779	VINF_IOM_R3_IOPORT_READ);
780	#else
781	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
783	VINF_SUCCESS);
784	#endif
785	RT_UNTRUSTED_VALIDATED_FENCE();
786
787	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
788	if ( idxReg >= SVGA_REG_CAPABILITIES
789	&& pThis->svga.u32SVGAId == SVGA_ID_0)
790	{
791	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
792	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
793	}
794
795	switch (idxReg)
796	{
797	case SVGA_REG_ID:
798	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
799	*pu32 = pThis->svga.u32SVGAId;
800	break;
801
802	case SVGA_REG_ENABLE:
803	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
804	*pu32 = pThis->svga.fEnabled;
805	break;
806
807	case SVGA_REG_WIDTH:
808	{
809	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
810	if ( pThis->svga.fEnabled
811	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
812	{
813	*pu32 = pThis->svga.uWidth;
814	}
815	else
816	{
817	#ifndef IN_RING3
818	rc = VINF_IOM_R3_IOPORT_READ;
819	#else
820	*pu32 = pThis->pDrv->cx;
821	#endif
822	}
823	break;
824	}
825
826	case SVGA_REG_HEIGHT:
827	{
828	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
829	if ( pThis->svga.fEnabled
830	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
831	{
832	*pu32 = pThis->svga.uHeight;
833	}
834	else
835	{
836	#ifndef IN_RING3
837	rc = VINF_IOM_R3_IOPORT_READ;
838	#else
839	*pu32 = pThis->pDrv->cy;
840	#endif
841	}
842	break;
843	}
844
845	case SVGA_REG_MAX_WIDTH:
846	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
847	*pu32 = pThis->svga.u32MaxWidth;
848	break;
849
850	case SVGA_REG_MAX_HEIGHT:
851	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
852	*pu32 = pThis->svga.u32MaxHeight;
853	break;
854
855	case SVGA_REG_DEPTH:
856	/* This returns the color depth of the current mode. */
857	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
858	switch (pThis->svga.uBpp)
859	{
860	case 15:
861	case 16:
862	case 24:
863	*pu32 = pThis->svga.uBpp;
864	break;
865
866	default:
867	case 32:
868	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
869	break;
870	}
871	break;
872
873	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
874	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
875	if ( pThis->svga.fEnabled
876	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
877	{
878	*pu32 = pThis->svga.uBpp;
879	}
880	else
881	{
882	#ifndef IN_RING3
883	rc = VINF_IOM_R3_IOPORT_READ;
884	#else
885	*pu32 = pThis->pDrv->cBits;
886	#endif
887	}
888	break;
889
890	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
892	if ( pThis->svga.fEnabled
893	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
894	{
895	*pu32 = (pThis->svga.uBpp + 7) & ~7;
896	}
897	else
898	{
899	#ifndef IN_RING3
900	rc = VINF_IOM_R3_IOPORT_READ;
901	#else
902	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
903	#endif
904	}
905	break;
906
907	case SVGA_REG_PSEUDOCOLOR:
908	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
909	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
910	break;
911
912	case SVGA_REG_RED_MASK:
913	case SVGA_REG_GREEN_MASK:
914	case SVGA_REG_BLUE_MASK:
915	{
916	uint32_t uBpp;
917
918	if ( pThis->svga.fEnabled
919	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
920	{
921	uBpp = pThis->svga.uBpp;
922	}
923	else
924	{
925	#ifndef IN_RING3
926	rc = VINF_IOM_R3_IOPORT_READ;
927	break;
928	#else
929	uBpp = pThis->pDrv->cBits;
930	#endif
931	}
932	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
933	switch (uBpp)
934	{
935	case 8:
936	u32RedMask = 0x07;
937	u32GreenMask = 0x38;
938	u32BlueMask = 0xc0;
939	break;
940
941	case 15:
942	u32RedMask = 0x0000001f;
943	u32GreenMask = 0x000003e0;
944	u32BlueMask = 0x00007c00;
945	break;
946
947	case 16:
948	u32RedMask = 0x0000001f;
949	u32GreenMask = 0x000007e0;
950	u32BlueMask = 0x0000f800;
951	break;
952
953	case 24:
954	case 32:
955	default:
956	u32RedMask = 0x00ff0000;
957	u32GreenMask = 0x0000ff00;
958	u32BlueMask = 0x000000ff;
959	break;
960	}
961	switch (idxReg)
962	{
963	case SVGA_REG_RED_MASK:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
965	*pu32 = u32RedMask;
966	break;
967
968	case SVGA_REG_GREEN_MASK:
969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
970	*pu32 = u32GreenMask;
971	break;
972
973	case SVGA_REG_BLUE_MASK:
974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
975	*pu32 = u32BlueMask;
976	break;
977	}
978	break;
979	}
980
981	case SVGA_REG_BYTES_PER_LINE:
982	{
983	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
984	if ( pThis->svga.fEnabled
985	&& pThis->svga.cbScanline)
986	{
987	*pu32 = pThis->svga.cbScanline;
988	}
989	else
990	{
991	#ifndef IN_RING3
992	rc = VINF_IOM_R3_IOPORT_READ;
993	#else
994	*pu32 = pThis->pDrv->cbScanline;
995	#endif
996	}
997	break;
998	}
999
1000	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1002	*pu32 = pThis->vram_size;
1003	break;
1004
1005	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1007	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1008	*pu32 = pThis->GCPhysVRAM;
1009	break;
1010
1011	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1013	/* Always zero in our case. */
1014	*pu32 = 0;
1015	break;
1016
1017	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1018	{
1019	#ifndef IN_RING3
1020	rc = VINF_IOM_R3_IOPORT_READ;
1021	#else
1022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1023
1024	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1025	if ( pThis->svga.fEnabled
1026	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1027	{
1028	/* Hardware enabled; return real framebuffer size .*/
1029	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1030	}
1031	else
1032	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1033
1034	pu32 = RT_MIN(pThis->vram_size, pu32);
1035	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1036	#endif
1037	break;
1038	}
1039
1040	case SVGA_REG_CAPABILITIES:
1041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1042	*pu32 = pThis->svga.u32RegCaps;
1043	break;
1044
1045	case SVGA_REG_MEM_START: /* FIFO start */
1046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1047	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1048	*pu32 = pThis->svga.GCPhysFIFO;
1049	break;
1050
1051	case SVGA_REG_MEM_SIZE: /* FIFO size */
1052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1053	*pu32 = pThis->svga.cbFIFO;
1054	break;
1055
1056	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1057	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1058	*pu32 = pThis->svga.fConfigured;
1059	break;
1060
1061	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1063	*pu32 = 0;
1064	break;
1065
1066	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1068	if (pThis->svga.fBusy)
1069	{
1070	#ifndef IN_RING3
1071	/* Go to ring-3 and halt the CPU. */
1072	rc = VINF_IOM_R3_IOPORT_READ;
1073	RT_NOREF(pDevIns);
1074	break;
1075	#else
1076	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1077	/* The guest is basically doing a HLT via the device here, but with
1078	a special wake up condition on FIFO completion. */
1079	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1080	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1081	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1082	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1083	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1084	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1085	if (pThis->svga.fBusy)
1086	{
1087	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1088	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1089	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1090	}
1091	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1092	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1093	# else
1094
1095	/* Delay the EMT a bit so the FIFO and others can get some work done.
1096	This used to be a crude 50 ms sleep. The current code tries to be
1097	more efficient, but the consept is still very crude. */
1098	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1099	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1100	RTThreadYield();
1101	if (pThis->svga.fBusy)
1102	{
1103	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1104
1105	if (pThis->svga.fBusy && cRefs == 1)
1106	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1107	if (pThis->svga.fBusy)
1108	{
1109	/** @todo If this code is going to stay, we need to call into the halt/wait
1110	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1111	* suffer when the guest is polling on a busy FIFO. */
1112	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1113	if (cNsMaxWait >= RT_NS_100US)
1114	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1115	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1116	RT_MIN(cNsMaxWait, RT_NS_10MS));
1117	}
1118
1119	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1120	}
1121	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1122	# endif
1123	*pu32 = pThis->svga.fBusy != 0;
1124	#endif
1125	}
1126	else
1127	*pu32 = false;
1128	break;
1129
1130	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1131	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1132	*pu32 = pThis->svga.u32GuestId;
1133	break;
1134
1135	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1137	*pu32 = pThis->svga.cScratchRegion;
1138	break;
1139
1140	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1142	*pu32 = SVGA_FIFO_NUM_REGS;
1143	break;
1144
1145	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1147	*pu32 = pThis->svga.u32PitchLock;
1148	break;
1149
1150	case SVGA_REG_IRQMASK: /* Interrupt mask */
1151	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1152	*pu32 = pThis->svga.u32IrqMask;
1153	break;
1154
1155	/* See "Guest memory regions" below. */
1156	case SVGA_REG_GMR_ID:
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1158	*pu32 = pThis->svga.u32CurrentGMRId;
1159	break;
1160
1161	case SVGA_REG_GMR_DESCRIPTOR:
1162	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1163	/* Write only */
1164	*pu32 = 0;
1165	break;
1166
1167	case SVGA_REG_GMR_MAX_IDS:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1169	*pu32 = pThis->svga.cGMR;
1170	break;
1171
1172	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1174	*pu32 = VMSVGA_MAX_GMR_PAGES;
1175	break;
1176
1177	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1179	*pu32 = pThis->svga.fTraces;
1180	break;
1181
1182	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1183	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1184	*pu32 = VMSVGA_MAX_GMR_PAGES;
1185	break;
1186
1187	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1189	*pu32 = VMSVGA_SURFACE_SIZE;
1190	break;
1191
1192	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1194	break;
1195
1196	/* Mouse cursor support. */
1197	case SVGA_REG_CURSOR_ID:
1198	case SVGA_REG_CURSOR_X:
1199	case SVGA_REG_CURSOR_Y:
1200	case SVGA_REG_CURSOR_ON:
1201	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1202	break;
1203
1204	/* Legacy multi-monitor support */
1205	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1207	*pu32 = 1;
1208	break;
1209
1210	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1211	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1212	*pu32 = 0;
1213	break;
1214
1215	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1217	*pu32 = 0;
1218	break;
1219
1220	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1221	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1222	*pu32 = 0;
1223	break;
1224
1225	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1226	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1227	*pu32 = 0;
1228	break;
1229
1230	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1231	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1232	*pu32 = pThis->svga.uWidth;
1233	break;
1234
1235	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1236	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1237	*pu32 = pThis->svga.uHeight;
1238	break;
1239
1240	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1241	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1242	/* We must return something sensible here otherwise the Linux driver
1243	will take a legacy code path without 3d support. This number also
1244	limits how many screens Linux guests will allow. */
1245	*pu32 = pThis->cMonitors;
1246	break;
1247
1248	default:
1249	{
1250	uint32_t offReg;
1251	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1252	{
1253	RT_UNTRUSTED_VALIDATED_FENCE();
1254	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1255	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1256	}
1257	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1258	{
1259	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1260	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1261	RT_UNTRUSTED_VALIDATED_FENCE();
1262	uint32_t u32 = pThis->last_palette[offReg / 3];
1263	switch (offReg % 3)
1264	{
1265	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1266	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1267	case 2: pu32 = u32 & 0xff; break; / blue */
1268	}
1269	}
1270	else
1271	{
1272	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1273	rc = VINF_IOM_R3_IOPORT_READ;
1274	#else
1275	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1276
1277	/* Do not assert. The guest might be reading all registers. */
1278	LogFunc(("Unknown reg=%#x\n", idxReg));
1279	#endif
1280	}
1281	break;
1282	}
1283	}
1284	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1285	return rc;
1286	}
1287
1288	#ifdef IN_RING3
1289	/**
1290	* Apply the current resolution settings to change the video mode.
1291	*
1292	* @returns VBox status code.
1293	* @param pThis VMSVGA State
1294	*/
1295	static int vmsvgaChangeMode(PVGASTATE pThis)
1296	{
1297	int rc;
1298
1299	/* Always do changemode on FIFO thread. */
1300	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1301
1302	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1303
1304	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1305
1306	if (pThis->svga.fGFBRegisters)
1307	{
1308	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1309	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1310	* deletes all screens other than screen #0, and redefines screen
1311	* #0 according to the specified mode. Drivers that use
1312	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1313	*/
1314
1315	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1316	pScreen->fDefined = true;
1317	pScreen->fModified = true;
1318	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1319	pScreen->idScreen = 0;
1320	pScreen->xOrigin = 0;
1321	pScreen->yOrigin = 0;
1322	pScreen->offVRAM = 0;
1323	pScreen->cbPitch = pThis->svga.cbScanline;
1324	pScreen->cWidth = pThis->svga.uWidth;
1325	pScreen->cHeight = pThis->svga.uHeight;
1326	pScreen->cBpp = pThis->svga.uBpp;
1327
1328	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1329	{
1330	/* Delete screen. */
1331	pScreen = &pSVGAState->aScreens[iScreen];
1332	if (pScreen->fDefined)
1333	{
1334	pScreen->fModified = true;
1335	pScreen->fDefined = false;
1336	}
1337	}
1338	}
1339	else
1340	{
1341	/* "If Screen Objects are supported, they can be used to fully
1342	* replace the functionality provided by the framebuffer registers
1343	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1344	*/
1345	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1346	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1347	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1348	}
1349
1350	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1351	{
1352	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1353	if (!pScreen->fModified)
1354	continue;
1355
1356	pScreen->fModified = false;
1357
1358	VBVAINFOVIEW view;
1359	RT_ZERO(view);
1360	view.u32ViewIndex = pScreen->idScreen;
1361	// view.u32ViewOffset = 0;
1362	view.u32ViewSize = pThis->vram_size;
1363	view.u32MaxScreenSize = pThis->vram_size;
1364
1365	VBVAINFOSCREEN screen;
1366	RT_ZERO(screen);
1367	screen.u32ViewIndex = pScreen->idScreen;
1368
1369	if (pScreen->fDefined)
1370	{
1371	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1372	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1373	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1374	{
1375	Assert(pThis->svga.fGFBRegisters);
1376	continue;
1377	}
1378
1379	screen.i32OriginX = pScreen->xOrigin;
1380	screen.i32OriginY = pScreen->yOrigin;
1381	screen.u32StartOffset = pScreen->offVRAM;
1382	screen.u32LineSize = pScreen->cbPitch;
1383	screen.u32Width = pScreen->cWidth;
1384	screen.u32Height = pScreen->cHeight;
1385	screen.u16BitsPerPixel = pScreen->cBpp;
1386	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1387	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1388	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1389	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1390	}
1391	else
1392	{
1393	/* Screen is destroyed. */
1394	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1395	}
1396
1397	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1398	AssertRC(rc);
1399	}
1400
1401	/* Last stuff. For the VGA device screenshot. */
1402	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1403	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1404	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1405	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1406	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1407
1408	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1409	if ( pThis->svga.viewport.cx == 0
1410	&& pThis->svga.viewport.cy == 0)
1411	{
1412	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1413	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1414	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1415	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1416	pThis->svga.viewport.yLowWC = 0;
1417	}
1418
1419	return VINF_SUCCESS;
1420	}
1421
1422	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1423	{
1424	VBVACMDHDR cmd;
1425	cmd.x = (int16_t)(pScreen->xOrigin + x);
1426	cmd.y = (int16_t)(pScreen->yOrigin + y);
1427	cmd.w = (uint16_t)w;
1428	cmd.h = (uint16_t)h;
1429
1430	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1431	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1432	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1433	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1434
1435	return VINF_SUCCESS;
1436	}
1437
1438	#endif /* IN_RING3 */
1439
1440	#if defined(IN_RING0) \|\| defined(IN_RING3)
1441	/**
1442	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1443	*
1444	* @param pThis The VMSVGA state.
1445	* @param fState The busy state.
1446	*/
1447	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1448	{
1449	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1450
1451	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1452	{
1453	/* Race / unfortunately scheduling. Highly unlikly. */
1454	uint32_t cLoops = 64;
1455	do
1456	{
1457	ASMNopPause();
1458	fState = (pThis->svga.fBusy != 0);
1459	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1460	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1461	}
1462	}
1463
1464
1465	/**
1466	* Update the scanline pitch in response to the guest changing mode
1467	* width/bpp.
1468	*
1469	* @param pThis VMSVGA State
1470	*/
1471	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1472	{
1473	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1474	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1475	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1476	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1477
1478	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1479	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1480	* location but it has a different meaning.
1481	*/
1482	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1483	uFifoPitchLock = 0;
1484
1485	/* Sanitize values. */
1486	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1487	uFifoPitchLock = 0;
1488	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1489	uRegPitchLock = 0;
1490
1491	/* Prefer the register value to the FIFO value.*/
1492	if (uRegPitchLock)
1493	pThis->svga.cbScanline = uRegPitchLock;
1494	else if (uFifoPitchLock)
1495	pThis->svga.cbScanline = uFifoPitchLock;
1496	else
1497	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1498
1499	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1500	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1501	}
1502	#endif
1503
1504
1505	/**
1506	* Write port register
1507	*
1508	* @returns VBox status code.
1509	* @param pThis VMSVGA State
1510	* @param u32 Value to write
1511	*/
1512	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1513	{
1514	#ifdef IN_RING3
1515	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1516	#endif
1517	int rc = VINF_SUCCESS;
1518
1519	/* Rough index register validation. */
1520	uint32_t idxReg = pThis->svga.u32IndexReg;
1521	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1522	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1523	VINF_IOM_R3_IOPORT_WRITE);
1524	#else
1525	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1527	VINF_SUCCESS);
1528	#endif
1529	RT_UNTRUSTED_VALIDATED_FENCE();
1530
1531	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1532	if ( idxReg >= SVGA_REG_CAPABILITIES
1533	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1534	{
1535	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1536	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1537	}
1538	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1539	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1540	switch (idxReg)
1541	{
1542	case SVGA_REG_WIDTH:
1543	case SVGA_REG_HEIGHT:
1544	case SVGA_REG_PITCHLOCK:
1545	case SVGA_REG_BITS_PER_PIXEL:
1546	pThis->svga.fGFBRegisters = true;
1547	break;
1548	default:
1549	break;
1550	}
1551
1552	switch (idxReg)
1553	{
1554	case SVGA_REG_ID:
1555	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1556	if ( u32 == SVGA_ID_0
1557	\|\| u32 == SVGA_ID_1
1558	\|\| u32 == SVGA_ID_2)
1559	pThis->svga.u32SVGAId = u32;
1560	else
1561	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1562	break;
1563
1564	case SVGA_REG_ENABLE:
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1566	#ifdef IN_RING3
1567	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1568	&& pThis->svga.fEnabled == false)
1569	{
1570	/* Make a backup copy of the first 512kb in order to save font data etc. */
1571	/** @todo should probably swap here, rather than copy + zero */
1572	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1573	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1574	}
1575
1576	pThis->svga.fEnabled = u32;
1577	if (pThis->svga.fEnabled)
1578	{
1579	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1580	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1581	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1582	{
1583	/* Keep the current mode. */
1584	pThis->svga.uWidth = pThis->pDrv->cx;
1585	pThis->svga.uHeight = pThis->pDrv->cy;
1586	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1587	}
1588
1589	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1590	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1591	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1592	{
1593	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1594	}
1595	# ifdef LOG_ENABLED
1596	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1597	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1598	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1599	# endif
1600
1601	/* Disable or enable dirty page tracking according to the current fTraces value. */
1602	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1603
1604	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1605	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1606	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1607	}
1608	else
1609	{
1610	/* Restore the text mode backup. */
1611	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1612
1613	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1614
1615	/* Enable dirty page tracking again when going into legacy mode. */
1616	vmsvgaSetTraces(pThis, true);
1617
1618	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1619	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1620	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1621
1622	/* Clear the pitch lock. */
1623	pThis->svga.u32PitchLock = 0;
1624	}
1625	#else /* !IN_RING3 */
1626	rc = VINF_IOM_R3_IOPORT_WRITE;
1627	#endif /* !IN_RING3 */
1628	break;
1629
1630	case SVGA_REG_WIDTH:
1631	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1632	if (pThis->svga.uWidth != u32)
1633	{
1634	#if defined(IN_RING3) \|\| defined(IN_RING0)
1635	pThis->svga.uWidth = u32;
1636	vmsvgaUpdatePitch(pThis);
1637	if (pThis->svga.fEnabled)
1638	{
1639	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1640	}
1641	#else
1642	rc = VINF_IOM_R3_IOPORT_WRITE;
1643	#endif
1644	}
1645	/* else: nop */
1646	break;
1647
1648	case SVGA_REG_HEIGHT:
1649	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1650	if (pThis->svga.uHeight != u32)
1651	{
1652	pThis->svga.uHeight = u32;
1653	if (pThis->svga.fEnabled)
1654	{
1655	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1656	}
1657	}
1658	/* else: nop */
1659	break;
1660
1661	case SVGA_REG_DEPTH:
1662	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1663	/** @todo read-only?? */
1664	break;
1665
1666	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1667	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1668	if (pThis->svga.uBpp != u32)
1669	{
1670	#if defined(IN_RING3) \|\| defined(IN_RING0)
1671	pThis->svga.uBpp = u32;
1672	vmsvgaUpdatePitch(pThis);
1673	if (pThis->svga.fEnabled)
1674	{
1675	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1676	}
1677	#else
1678	rc = VINF_IOM_R3_IOPORT_WRITE;
1679	#endif
1680	}
1681	/* else: nop */
1682	break;
1683
1684	case SVGA_REG_PSEUDOCOLOR:
1685	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1686	break;
1687
1688	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1689	#ifdef IN_RING3
1690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1691	pThis->svga.fConfigured = u32;
1692	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1693	if (!pThis->svga.fConfigured)
1694	{
1695	pThis->svga.fTraces = true;
1696	}
1697	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1698	#else
1699	rc = VINF_IOM_R3_IOPORT_WRITE;
1700	#endif
1701	break;
1702
1703	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1704	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1705	if ( pThis->svga.fEnabled
1706	&& pThis->svga.fConfigured)
1707	{
1708	#if defined(IN_RING3) \|\| defined(IN_RING0)
1709	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1710	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1711	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1712	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1713
1714	/* Kick the FIFO thread to start processing commands again. */
1715	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1716	#else
1717	rc = VINF_IOM_R3_IOPORT_WRITE;
1718	#endif
1719	}
1720	/* else nothing to do. */
1721	else
1722	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1723
1724	break;
1725
1726	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1727	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1728	break;
1729
1730	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1732	pThis->svga.u32GuestId = u32;
1733	break;
1734
1735	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1736	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1737	pThis->svga.u32PitchLock = u32;
1738	/* Should this also update the FIFO pitch lock? Unclear. */
1739	break;
1740
1741	case SVGA_REG_IRQMASK: /* Interrupt mask */
1742	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1743	pThis->svga.u32IrqMask = u32;
1744
1745	/* Irq pending after the above change? */
1746	if (pThis->svga.u32IrqStatus & u32)
1747	{
1748	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1749	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1750	}
1751	else
1752	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1753	break;
1754
1755	/* Mouse cursor support */
1756	case SVGA_REG_CURSOR_ID:
1757	case SVGA_REG_CURSOR_X:
1758	case SVGA_REG_CURSOR_Y:
1759	case SVGA_REG_CURSOR_ON:
1760	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1761	break;
1762
1763	/* Legacy multi-monitor support */
1764	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1766	break;
1767	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1769	break;
1770	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1772	break;
1773	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1775	break;
1776	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1778	break;
1779	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1781	break;
1782	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1783	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1784	break;
1785	#ifdef VBOX_WITH_VMSVGA3D
1786	/* See "Guest memory regions" below. */
1787	case SVGA_REG_GMR_ID:
1788	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1789	pThis->svga.u32CurrentGMRId = u32;
1790	break;
1791
1792	case SVGA_REG_GMR_DESCRIPTOR:
1793	# ifndef IN_RING3
1794	rc = VINF_IOM_R3_IOPORT_WRITE;
1795	break;
1796	# else /* IN_RING3 */
1797	{
1798	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1799
1800	/* Validate current GMR id. */
1801	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1802	AssertBreak(idGMR < pThis->svga.cGMR);
1803	RT_UNTRUSTED_VALIDATED_FENCE();
1804
1805	/* Free the old GMR if present. */
1806	vmsvgaGMRFree(pThis, idGMR);
1807
1808	/* Just undefine the GMR? */
1809	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1810	if (GCPhys == 0)
1811	{
1812	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1813	break;
1814	}
1815
1816
1817	/* Never cross a page boundary automatically. */
1818	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1819	uint32_t cPagesTotal = 0;
1820	uint32_t iDesc = 0;
1821	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1822	uint32_t cLoops = 0;
1823	RTGCPHYS GCPhysBase = GCPhys;
1824	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1825	{
1826	/* Read descriptor. */
1827	SVGAGuestMemDescriptor desc;
1828	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1829	AssertRCBreak(rc);
1830
1831	if (desc.numPages != 0)
1832	{
1833	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1834	cPagesTotal += desc.numPages;
1835	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1836
1837	if ((iDesc & 15) == 0)
1838	{
1839	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1840	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1841	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1842	}
1843
1844	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1845	paDescs[iDesc++].numPages = desc.numPages;
1846
1847	/* Continue with the next descriptor. */
1848	GCPhys += sizeof(desc);
1849	}
1850	else if (desc.ppn == 0)
1851	break; /* terminator */
1852	else /* Pointer to the next physical page of descriptors. */
1853	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1854
1855	cLoops++;
1856	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1857	}
1858
1859	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1860	if (RT_SUCCESS(rc))
1861	{
1862	/* Commit the GMR. */
1863	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1864	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1865	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1866	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1867	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1868	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1869	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1870	}
1871	else
1872	{
1873	RTMemFree(paDescs);
1874	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1875	}
1876	break;
1877	}
1878	# endif /* IN_RING3 */
1879	#endif // VBOX_WITH_VMSVGA3D
1880
1881	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1882	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1883	if (pThis->svga.fTraces == u32)
1884	break; /* nothing to do */
1885
1886	#ifdef IN_RING3
1887	vmsvgaSetTraces(pThis, !!u32);
1888	#else
1889	rc = VINF_IOM_R3_IOPORT_WRITE;
1890	#endif
1891	break;
1892
1893	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1895	break;
1896
1897	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1898	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1899	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1900	break;
1901
1902	case SVGA_REG_FB_START:
1903	case SVGA_REG_MEM_START:
1904	case SVGA_REG_HOST_BITS_PER_PIXEL:
1905	case SVGA_REG_MAX_WIDTH:
1906	case SVGA_REG_MAX_HEIGHT:
1907	case SVGA_REG_VRAM_SIZE:
1908	case SVGA_REG_FB_SIZE:
1909	case SVGA_REG_CAPABILITIES:
1910	case SVGA_REG_MEM_SIZE:
1911	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1912	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1913	case SVGA_REG_BYTES_PER_LINE:
1914	case SVGA_REG_FB_OFFSET:
1915	case SVGA_REG_RED_MASK:
1916	case SVGA_REG_GREEN_MASK:
1917	case SVGA_REG_BLUE_MASK:
1918	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1919	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1920	case SVGA_REG_GMR_MAX_IDS:
1921	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1922	/* Read only - ignore. */
1923	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1924	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1925	break;
1926
1927	default:
1928	{
1929	uint32_t offReg;
1930	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1931	{
1932	RT_UNTRUSTED_VALIDATED_FENCE();
1933	pThis->svga.au32ScratchRegion[offReg] = u32;
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1935	}
1936	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1937	{
1938	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1939	Btw, see rgb_to_pixel32. */
1940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1941	u32 &= 0xff;
1942	RT_UNTRUSTED_VALIDATED_FENCE();
1943	uint32_t uRgb = pThis->last_palette[offReg / 3];
1944	switch (offReg % 3)
1945	{
1946	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1947	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1948	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1949	}
1950	pThis->last_palette[offReg / 3] = uRgb;
1951	}
1952	else
1953	{
1954	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1955	rc = VINF_IOM_R3_IOPORT_WRITE;
1956	#else
1957	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1958	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1959	#endif
1960	}
1961	break;
1962	}
1963	}
1964	return rc;
1965	}
1966
1967	/**
1968	* Port I/O Handler for IN operations.
1969	*
1970	* @returns VINF_SUCCESS or VINF_EM_*.
1971	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1972	*
1973	* @param pDevIns The device instance.
1974	* @param pvUser User argument.
1975	* @param uPort Port number used for the IN operation.
1976	* @param pu32 Where to store the result. This is always a 32-bit
1977	* variable regardless of what @a cb might say.
1978	* @param cb Number of bytes read.
1979	*/
1980	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1981	{
1982	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1983	RT_NOREF_PV(pvUser);
1984
1985	/* Ignore non-dword accesses. */
1986	if (cb != 4)
1987	{
1988	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1989	*pu32 = UINT32_MAX;
1990	return VINF_SUCCESS;
1991	}
1992
1993	switch (uPort - pThis->svga.BasePort)
1994	{
1995	case SVGA_INDEX_PORT:
1996	*pu32 = pThis->svga.u32IndexReg;
1997	break;
1998
1999	case SVGA_VALUE_PORT:
2000	return vmsvgaReadPort(pDevIns, pThis, pu32);
2001
2002	case SVGA_BIOS_PORT:
2003	Log(("Ignoring BIOS port read\n"));
2004	*pu32 = 0;
2005	break;
2006
2007	case SVGA_IRQSTATUS_PORT:
2008	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2009	*pu32 = pThis->svga.u32IrqStatus;
2010	break;
2011
2012	default:
2013	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
2014	*pu32 = UINT32_MAX;
2015	break;
2016	}
2017
2018	return VINF_SUCCESS;
2019	}
2020
2021	/**
2022	* Port I/O Handler for OUT operations.
2023	*
2024	* @returns VINF_SUCCESS or VINF_EM_*.
2025	*
2026	* @param pDevIns The device instance.
2027	* @param pvUser User argument.
2028	* @param uPort Port number used for the OUT operation.
2029	* @param u32 The value to output.
2030	* @param cb The value size in bytes.
2031	*/
2032	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
2033	{
2034	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2035	RT_NOREF_PV(pvUser);
2036
2037	/* Ignore non-dword accesses. */
2038	if (cb != 4)
2039	{
2040	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
2041	return VINF_SUCCESS;
2042	}
2043
2044	switch (uPort - pThis->svga.BasePort)
2045	{
2046	case SVGA_INDEX_PORT:
2047	pThis->svga.u32IndexReg = u32;
2048	break;
2049
2050	case SVGA_VALUE_PORT:
2051	return vmsvgaWritePort(pThis, u32);
2052
2053	case SVGA_BIOS_PORT:
2054	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2055	break;
2056
2057	case SVGA_IRQSTATUS_PORT:
2058	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2059	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2060	/* Clear the irq in case all events have been cleared. */
2061	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2062	{
2063	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2064	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2065	}
2066	break;
2067
2068	default:
2069	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2070	uPort - pThis->svga.BasePort, uPort, u32, cb));
2071	break;
2072	}
2073	return VINF_SUCCESS;
2074	}
2075
2076	#ifdef IN_RING3
2077
2078	# ifdef DEBUG_FIFO_ACCESS
2079	/**
2080	* Handle FIFO memory access.
2081	* @returns VBox status code.
2082	* @param pVM VM handle.
2083	* @param pThis VGA device instance data.
2084	* @param GCPhys The access physical address.
2085	* @param fWriteAccess Read or write access
2086	*/
2087	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2088	{
2089	RT_NOREF(pVM);
2090	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2091	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2092
2093	switch (GCPhysOffset >> 2)
2094	{
2095	case SVGA_FIFO_MIN:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_MAX:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_NEXT_CMD:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_STOP:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_CAPABILITIES:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_FLAGS:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_FENCE:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_HWVERSION:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_PITCHLOCK:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_CURSOR_ON:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_CURSOR_X:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_CURSOR_Y:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_CURSOR_COUNT:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_RESERVED:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_CURSOR_SCREEN_ID:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_DEAD:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_HWVERSION_REVISED:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2393	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2394	break;
2395	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2396	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2397	break;
2398	case SVGA_FIFO_3D_CAPS_LAST:
2399	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2400	break;
2401	case SVGA_FIFO_GUEST_3D_HWVERSION:
2402	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2403	break;
2404	case SVGA_FIFO_FENCE_GOAL:
2405	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2406	break;
2407	case SVGA_FIFO_BUSY:
2408	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2409	break;
2410	default:
2411	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2412	break;
2413	}
2414
2415	return VINF_EM_RAW_EMULATE_INSTR;
2416	}
2417	# endif /* DEBUG_FIFO_ACCESS */
2418
2419	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2420	/**
2421	* HC access handler for the FIFO.
2422	*
2423	* @returns VINF_SUCCESS if the handler have carried out the operation.
2424	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2425	* @param pVM VM Handle.
2426	* @param pVCpu The cross context CPU structure for the calling EMT.
2427	* @param GCPhys The physical address the guest is writing to.
2428	* @param pvPhys The HC mapping of that address.
2429	* @param pvBuf What the guest is reading/writing.
2430	* @param cbBuf How much it's reading/writing.
2431	* @param enmAccessType The access type.
2432	* @param enmOrigin Who is making the access.
2433	* @param pvUser User argument.
2434	*/
2435	static DECLCALLBACK(VBOXSTRICTRC)
2436	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2437	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2438	{
2439	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2440	PVGASTATE pThis = (PVGASTATE)pvUser;
2441	AssertPtr(pThis);
2442
2443	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2444	/*
2445	* Wake up the FIFO thread as it might have work to do now.
2446	*/
2447	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2448	AssertLogRelRC(rc);
2449	# endif
2450
2451	# ifdef DEBUG_FIFO_ACCESS
2452	/*
2453	* When in debug-fifo-access mode, we do not disable the access handler,
2454	* but leave it on as we wish to catch all access.
2455	*/
2456	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2457	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2458	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2459	/*
2460	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2461	*/
2462	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2463	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2464	# endif
2465	if (RT_SUCCESS(rc))
2466	return VINF_PGM_HANDLER_DO_DEFAULT;
2467	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2468	return rc;
2469	}
2470	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2471
2472	#endif /* IN_RING3 */
2473
2474	#ifdef DEBUG_GMR_ACCESS
2475	# ifdef IN_RING3
2476
2477	/**
2478	* HC access handler for the FIFO.
2479	*
2480	* @returns VINF_SUCCESS if the handler have carried out the operation.
2481	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2482	* @param pVM VM Handle.
2483	* @param pVCpu The cross context CPU structure for the calling EMT.
2484	* @param GCPhys The physical address the guest is writing to.
2485	* @param pvPhys The HC mapping of that address.
2486	* @param pvBuf What the guest is reading/writing.
2487	* @param cbBuf How much it's reading/writing.
2488	* @param enmAccessType The access type.
2489	* @param enmOrigin Who is making the access.
2490	* @param pvUser User argument.
2491	*/
2492	static DECLCALLBACK(VBOXSTRICTRC)
2493	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2494	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2495	{
2496	PVGASTATE pThis = (PVGASTATE)pvUser;
2497	Assert(pThis);
2498	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2499	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2500
2501	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2502
2503	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2504	{
2505	PGMR pGMR = &pSVGAState->paGMR[i];
2506
2507	if (pGMR->numDescriptors)
2508	{
2509	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2510	{
2511	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2512	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2513	{
2514	/*
2515	* Turn off the write handler for this particular page and make it R/W.
2516	* Then return telling the caller to restart the guest instruction.
2517	*/
2518	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2519	AssertRC(rc);
2520	goto end;
2521	}
2522	}
2523	}
2524	}
2525	end:
2526	return VINF_PGM_HANDLER_DO_DEFAULT;
2527	}
2528
2529	/* Callback handler for VMR3ReqCallWaitU */
2530	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2531	{
2532	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2533	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2534	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2535	int rc;
2536
2537	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2538	{
2539	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2540	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2541	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2542	AssertRC(rc);
2543	}
2544	return VINF_SUCCESS;
2545	}
2546
2547	/* Callback handler for VMR3ReqCallWaitU */
2548	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2549	{
2550	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2552	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2553
2554	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2555	{
2556	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2557	AssertRC(rc);
2558	}
2559	return VINF_SUCCESS;
2560	}
2561
2562	/* Callback handler for VMR3ReqCallWaitU */
2563	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2564	{
2565	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2566
2567	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2568	{
2569	PGMR pGMR = &pSVGAState->paGMR[i];
2570
2571	if (pGMR->numDescriptors)
2572	{
2573	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2574	{
2575	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2576	AssertRC(rc);
2577	}
2578	}
2579	}
2580	return VINF_SUCCESS;
2581	}
2582
2583	# endif /* IN_RING3 */
2584	#endif /* DEBUG_GMR_ACCESS */
2585
2586	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2587
2588	#ifdef IN_RING3
2589
2590
2591	/**
2592	* Common worker for changing the pointer shape.
2593	*
2594	* @param pThis The VGA instance data.
2595	* @param pSVGAState The VMSVGA ring-3 instance data.
2596	* @param fAlpha Whether there is alpha or not.
2597	* @param xHot Hotspot x coordinate.
2598	* @param yHot Hotspot y coordinate.
2599	* @param cx Width.
2600	* @param cy Height.
2601	* @param pbData Heap copy of the cursor data. Consumed.
2602	* @param cbData The size of the data.
2603	*/
2604	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2605	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2606	{
2607	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2608	#ifdef LOG_ENABLED
2609	if (LogIs2Enabled())
2610	{
2611	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2612	if (!fAlpha)
2613	{
2614	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2615	for (uint32_t y = 0; y < cy; y++)
2616	{
2617	Log2(("%3u:", y));
2618	uint8_t const pbLine = &pbData[y cbAndLine];
2619	for (uint32_t x = 0; x < cx; x += 8)
2620	{
2621	uint8_t b = pbLine[x / 8];
2622	char szByte[12];
2623	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2624	szByte[1] = b & 0x40 ? '*' : ' ';
2625	szByte[2] = b & 0x20 ? '*' : ' ';
2626	szByte[3] = b & 0x10 ? '*' : ' ';
2627	szByte[4] = b & 0x08 ? '*' : ' ';
2628	szByte[5] = b & 0x04 ? '*' : ' ';
2629	szByte[6] = b & 0x02 ? '*' : ' ';
2630	szByte[7] = b & 0x01 ? '*' : ' ';
2631	szByte[8] = '\0';
2632	Log2(("%s", szByte));
2633	}
2634	Log2(("\n"));
2635	}
2636	}
2637
2638	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2639	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2640	for (uint32_t y = 0; y < cy; y++)
2641	{
2642	Log2(("%3u:", y));
2643	uint32_t const pu32Line = &pu32Xor[y cx];
2644	for (uint32_t x = 0; x < cx; x++)
2645	Log2((" %08x", pu32Line[x]));
2646	Log2(("\n"));
2647	}
2648	}
2649	#endif
2650
2651	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2652	AssertRC(rc);
2653
2654	if (pSVGAState->Cursor.fActive)
2655	RTMemFree(pSVGAState->Cursor.pData);
2656
2657	pSVGAState->Cursor.fActive = true;
2658	pSVGAState->Cursor.xHotspot = xHot;
2659	pSVGAState->Cursor.yHotspot = yHot;
2660	pSVGAState->Cursor.width = cx;
2661	pSVGAState->Cursor.height = cy;
2662	pSVGAState->Cursor.cbData = cbData;
2663	pSVGAState->Cursor.pData = pbData;
2664	}
2665
2666
2667	/**
2668	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2669	*
2670	* @param pThis The VGA instance data.
2671	* @param pSVGAState The VMSVGA ring-3 instance data.
2672	* @param pCursor The cursor.
2673	* @param pbSrcAndMask The AND mask.
2674	* @param cbSrcAndLine The scanline length of the AND mask.
2675	* @param pbSrcXorMask The XOR mask.
2676	* @param cbSrcXorLine The scanline length of the XOR mask.
2677	*/
2678	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2679	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2680	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2681	{
2682	uint32_t const cx = pCursor->width;
2683	uint32_t const cy = pCursor->height;
2684
2685	/*
2686	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2687	* The AND data uses 8-bit aligned scanlines.
2688	* The XOR data must be starting on a 32-bit boundrary.
2689	*/
2690	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2691	uint32_t cbDstAndMask = cbDstAndLine * cy;
2692	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2693	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2694
2695	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2696	AssertReturnVoid(pbCopy);
2697
2698	/* Convert the AND mask. */
2699	uint8_t *pbDst = pbCopy;
2700	uint8_t const *pbSrc = pbSrcAndMask;
2701	switch (pCursor->andMaskDepth)
2702	{
2703	case 1:
2704	if (cbSrcAndLine == cbDstAndLine)
2705	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2706	else
2707	{
2708	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2709	for (uint32_t y = 0; y < cy; y++)
2710	{
2711	memcpy(pbDst, pbSrc, cbDstAndLine);
2712	pbDst += cbDstAndLine;
2713	pbSrc += cbSrcAndLine;
2714	}
2715	}
2716	break;
2717	/* Should take the XOR mask into account for the multi-bit AND mask. */
2718	case 8:
2719	for (uint32_t y = 0; y < cy; y++)
2720	{
2721	for (uint32_t x = 0; x < cx; )
2722	{
2723	uint8_t bDst = 0;
2724	uint8_t fBit = 1;
2725	do
2726	{
2727	uintptr_t const idxPal = pbSrc[x] * 3;
2728	if ((( pThis->last_palette[idxPal]
2729	\| (pThis->last_palette[idxPal] >> 8)
2730	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2731	bDst \|= fBit;
2732	fBit <<= 1;
2733	x++;
2734	} while (x < cx && (x & 7));
2735	pbDst[(x - 1) / 8] = bDst;
2736	}
2737	pbDst += cbDstAndLine;
2738	pbSrc += cbSrcAndLine;
2739	}
2740	break;
2741	case 15:
2742	for (uint32_t y = 0; y < cy; y++)
2743	{
2744	for (uint32_t x = 0; x < cx; )
2745	{
2746	uint8_t bDst = 0;
2747	uint8_t fBit = 1;
2748	do
2749	{
2750	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2751	bDst \|= fBit;
2752	fBit <<= 1;
2753	x++;
2754	} while (x < cx && (x & 7));
2755	pbDst[(x - 1) / 8] = bDst;
2756	}
2757	pbDst += cbDstAndLine;
2758	pbSrc += cbSrcAndLine;
2759	}
2760	break;
2761	case 16:
2762	for (uint32_t y = 0; y < cy; y++)
2763	{
2764	for (uint32_t x = 0; x < cx; )
2765	{
2766	uint8_t bDst = 0;
2767	uint8_t fBit = 1;
2768	do
2769	{
2770	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2771	bDst \|= fBit;
2772	fBit <<= 1;
2773	x++;
2774	} while (x < cx && (x & 7));
2775	pbDst[(x - 1) / 8] = bDst;
2776	}
2777	pbDst += cbDstAndLine;
2778	pbSrc += cbSrcAndLine;
2779	}
2780	break;
2781	case 24:
2782	for (uint32_t y = 0; y < cy; y++)
2783	{
2784	for (uint32_t x = 0; x < cx; )
2785	{
2786	uint8_t bDst = 0;
2787	uint8_t fBit = 1;
2788	do
2789	{
2790	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2791	bDst \|= fBit;
2792	fBit <<= 1;
2793	x++;
2794	} while (x < cx && (x & 7));
2795	pbDst[(x - 1) / 8] = bDst;
2796	}
2797	pbDst += cbDstAndLine;
2798	pbSrc += cbSrcAndLine;
2799	}
2800	break;
2801	case 32:
2802	for (uint32_t y = 0; y < cy; y++)
2803	{
2804	for (uint32_t x = 0; x < cx; )
2805	{
2806	uint8_t bDst = 0;
2807	uint8_t fBit = 1;
2808	do
2809	{
2810	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2811	bDst \|= fBit;
2812	fBit <<= 1;
2813	x++;
2814	} while (x < cx && (x & 7));
2815	pbDst[(x - 1) / 8] = bDst;
2816	}
2817	pbDst += cbDstAndLine;
2818	pbSrc += cbSrcAndLine;
2819	}
2820	break;
2821	default:
2822	RTMemFree(pbCopy);
2823	AssertFailedReturnVoid();
2824	}
2825
2826	/* Convert the XOR mask. */
2827	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2828	pbSrc = pbSrcXorMask;
2829	switch (pCursor->xorMaskDepth)
2830	{
2831	case 1:
2832	for (uint32_t y = 0; y < cy; y++)
2833	{
2834	for (uint32_t x = 0; x < cx; )
2835	{
2836	/* most significant bit is the left most one. */
2837	uint8_t bSrc = pbSrc[x / 8];
2838	do
2839	{
2840	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2841	bSrc <<= 1;
2842	x++;
2843	} while ((x & 7) && x < cx);
2844	}
2845	pbSrc += cbSrcXorLine;
2846	}
2847	break;
2848	case 8:
2849	for (uint32_t y = 0; y < cy; y++)
2850	{
2851	for (uint32_t x = 0; x < cx; x++)
2852	{
2853	uint32_t u = pThis->last_palette[pbSrc[x]];
2854	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2855	}
2856	pbSrc += cbSrcXorLine;
2857	}
2858	break;
2859	case 15: /* Src: RGB-5-5-5 */
2860	for (uint32_t y = 0; y < cy; y++)
2861	{
2862	for (uint32_t x = 0; x < cx; x++)
2863	{
2864	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2865	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2866	((uValue >> 5) & 0x1f) << 3,
2867	((uValue >> 10) & 0x1f) << 3, 0);
2868	}
2869	pbSrc += cbSrcXorLine;
2870	}
2871	break;
2872	case 16: /* Src: RGB-5-6-5 */
2873	for (uint32_t y = 0; y < cy; y++)
2874	{
2875	for (uint32_t x = 0; x < cx; x++)
2876	{
2877	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2878	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2879	((uValue >> 5) & 0x3f) << 2,
2880	((uValue >> 11) & 0x1f) << 3, 0);
2881	}
2882	pbSrc += cbSrcXorLine;
2883	}
2884	break;
2885	case 24:
2886	for (uint32_t y = 0; y < cy; y++)
2887	{
2888	for (uint32_t x = 0; x < cx; x++)
2889	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2890	pbSrc += cbSrcXorLine;
2891	}
2892	break;
2893	case 32:
2894	for (uint32_t y = 0; y < cy; y++)
2895	{
2896	for (uint32_t x = 0; x < cx; x++)
2897	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2898	pbSrc += cbSrcXorLine;
2899	}
2900	break;
2901	default:
2902	RTMemFree(pbCopy);
2903	AssertFailedReturnVoid();
2904	}
2905
2906	/*
2907	* Pass it to the frontend/whatever.
2908	*/
2909	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2910	}
2911
2912
2913	/**
2914	* Worker for vmsvgaR3FifoThread that handles an external command.
2915	*
2916	* @param pThis VGA device instance data.
2917	*/
2918	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2919	{
2920	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2921	switch (pThis->svga.u8FIFOExtCommand)
2922	{
2923	case VMSVGA_FIFO_EXTCMD_RESET:
2924	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2925	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2926	# ifdef VBOX_WITH_VMSVGA3D
2927	if (pThis->svga.f3DEnabled)
2928	{
2929	/* The 3d subsystem must be reset from the fifo thread. */
2930	vmsvga3dReset(pThis);
2931	}
2932	# endif
2933	break;
2934
2935	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2936	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2937	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2938	# ifdef VBOX_WITH_VMSVGA3D
2939	if (pThis->svga.f3DEnabled)
2940	{
2941	/* The 3d subsystem must be shut down from the fifo thread. */
2942	vmsvga3dTerminate(pThis);
2943	}
2944	# endif
2945	break;
2946
2947	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2948	{
2949	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2950	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2951	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2952	vmsvgaSaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2953	# ifdef VBOX_WITH_VMSVGA3D
2954	if (pThis->svga.f3DEnabled)
2955	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2956	# endif
2957	break;
2958	}
2959
2960	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2961	{
2962	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2963	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2964	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2965	vmsvgaLoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2966	# ifdef VBOX_WITH_VMSVGA3D
2967	if (pThis->svga.f3DEnabled)
2968	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2969	# endif
2970	break;
2971	}
2972
2973	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2974	{
2975	# ifdef VBOX_WITH_VMSVGA3D
2976	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2977	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2978	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2979	# endif
2980	break;
2981	}
2982
2983
2984	default:
2985	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2986	break;
2987	}
2988
2989	/*
2990	* Signal the end of the external command.
2991	*/
2992	pThis->svga.pvFIFOExtCmdParam = NULL;
2993	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2994	ASMMemoryFence(); /* paranoia^2 */
2995	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2996	AssertLogRelRC(rc);
2997	}
2998
2999	/**
3000	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3001	* doing a job on the FIFO thread (even when it's officially suspended).
3002	*
3003	* @returns VBox status code (fully asserted).
3004	* @param pThis VGA device instance data.
3005	* @param uExtCmd The command to execute on the FIFO thread.
3006	* @param pvParam Pointer to command parameters.
3007	* @param cMsWait The time to wait for the command, given in
3008	* milliseconds.
3009	*/
3010	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3011	{
3012	Assert(cMsWait >= RT_MS_1SEC * 5);
3013	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3014	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3015
3016	int rc;
3017	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
3018	PDMTHREADSTATE enmState = pThread->enmState;
3019	if (enmState == PDMTHREADSTATE_SUSPENDED)
3020	{
3021	/*
3022	* The thread is suspended, we have to temporarily wake it up so it can
3023	* perform the task.
3024	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3025	*/
3026	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3027	/* Post the request. */
3028	pThis->svga.fFifoExtCommandWakeup = true;
3029	pThis->svga.pvFIFOExtCmdParam = pvParam;
3030	pThis->svga.u8FIFOExtCommand = uExtCmd;
3031	ASMMemoryFence(); /* paranoia^3 */
3032
3033	/* Resume the thread. */
3034	rc = PDMR3ThreadResume(pThread);
3035	AssertLogRelRC(rc);
3036	if (RT_SUCCESS(rc))
3037	{
3038	/* Wait. Take care in case the semaphore was already posted (same as below). */
3039	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3040	if ( rc == VINF_SUCCESS
3041	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3042	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3043	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3044	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3045
3046	/* suspend the thread */
3047	pThis->svga.fFifoExtCommandWakeup = false;
3048	int rc2 = PDMR3ThreadSuspend(pThread);
3049	AssertLogRelRC(rc2);
3050	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3051	rc = rc2;
3052	}
3053	pThis->svga.fFifoExtCommandWakeup = false;
3054	pThis->svga.pvFIFOExtCmdParam = NULL;
3055	}
3056	else if (enmState == PDMTHREADSTATE_RUNNING)
3057	{
3058	/*
3059	* The thread is running, should only happen during reset and vmsvga3dsfc.
3060	* We ASSUME not racing code here, both wrt thread state and ext commands.
3061	*/
3062	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3063	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3064
3065	/* Post the request. */
3066	pThis->svga.pvFIFOExtCmdParam = pvParam;
3067	pThis->svga.u8FIFOExtCommand = uExtCmd;
3068	ASMMemoryFence(); /* paranoia^2 */
3069	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3070	AssertLogRelRC(rc);
3071
3072	/* Wait. Take care in case the semaphore was already posted (same as above). */
3073	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3074	if ( rc == VINF_SUCCESS
3075	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3076	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3077	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3078	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3079
3080	pThis->svga.pvFIFOExtCmdParam = NULL;
3081	}
3082	else
3083	{
3084	/*
3085	* Something is wrong with the thread!
3086	*/
3087	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3088	rc = VERR_INVALID_STATE;
3089	}
3090	return rc;
3091	}
3092
3093
3094	/**
3095	* Marks the FIFO non-busy, notifying any waiting EMTs.
3096	*
3097	* @param pThis The VGA state.
3098	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3099	* @param offFifoMin The start byte offset of the command FIFO.
3100	*/
3101	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3102	{
3103	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3104	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3105	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3106
3107	/* Wake up any waiting EMTs. */
3108	if (pSVGAState->cBusyDelayedEmts > 0)
3109	{
3110	#ifdef VMSVGA_USE_EMT_HALT_CODE
3111	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3112	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3113	if (idCpu != NIL_VMCPUID)
3114	{
3115	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3116	while (idCpu-- > 0)
3117	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3118	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3119	}
3120	#else
3121	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3122	AssertRC(rc2);
3123	#endif
3124	}
3125	}
3126
3127	/**
3128	* Reads (more) payload into the command buffer.
3129	*
3130	* @returns pbBounceBuf on success
3131	* @retval (void *)1 if the thread was requested to stop.
3132	* @retval NULL on FIFO error.
3133	*
3134	* @param cbPayloadReq The number of bytes of payload requested.
3135	* @param pFIFO The FIFO.
3136	* @param offCurrentCmd The FIFO byte offset of the current command.
3137	* @param offFifoMin The start byte offset of the command FIFO.
3138	* @param offFifoMax The end byte offset of the command FIFO.
3139	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3140	* always sufficient size.
3141	* @param pcbAlreadyRead How much payload we've already read into the bounce
3142	* buffer. (We will NEVER re-read anything.)
3143	* @param pThread The calling PDM thread handle.
3144	* @param pThis The VGA state.
3145	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3146	* statistics collection.
3147	*/
3148	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3149	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3150	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3151	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3152	{
3153	Assert(pbBounceBuf);
3154	Assert(pcbAlreadyRead);
3155	Assert(offFifoMin < offFifoMax);
3156	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3157	Assert(offFifoMax <= pThis->svga.cbFIFO);
3158
3159	/*
3160	* Check if the requested payload size has already been satisfied .
3161	* .
3162	* When called to read more, the caller is responsible for making sure the .
3163	* new command size (cbRequsted) never is smaller than what has already .
3164	* been read.
3165	*/
3166	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3167	if (cbPayloadReq <= cbAlreadyRead)
3168	{
3169	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3170	return pbBounceBuf;
3171	}
3172
3173	/*
3174	* Commands bigger than the fifo buffer are invalid.
3175	*/
3176	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3177	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3178	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3179	NULL);
3180
3181	/*
3182	* Move offCurrentCmd past the command dword.
3183	*/
3184	offCurrentCmd += sizeof(uint32_t);
3185	if (offCurrentCmd >= offFifoMax)
3186	offCurrentCmd = offFifoMin;
3187
3188	/*
3189	* Do we have sufficient payload data available already?
3190	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3191	*/
3192	uint32_t cbAfter, cbBefore;
3193	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3194	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3195	if (offNextCmd >= offCurrentCmd)
3196	{
3197	if (RT_LIKELY(offNextCmd < offFifoMax))
3198	cbAfter = offNextCmd - offCurrentCmd;
3199	else
3200	{
3201	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3202	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3203	offNextCmd, offFifoMin, offFifoMax));
3204	cbAfter = offFifoMax - offCurrentCmd;
3205	}
3206	cbBefore = 0;
3207	}
3208	else
3209	{
3210	cbAfter = offFifoMax - offCurrentCmd;
3211	if (offNextCmd >= offFifoMin)
3212	cbBefore = offNextCmd - offFifoMin;
3213	else
3214	{
3215	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3216	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3217	offNextCmd, offFifoMin, offFifoMax));
3218	cbBefore = 0;
3219	}
3220	}
3221	if (cbAfter + cbBefore < cbPayloadReq)
3222	{
3223	/*
3224	* Insufficient, must wait for it to arrive.
3225	*/
3226	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3227	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3228	for (uint32_t i = 0;; i++)
3229	{
3230	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3231	{
3232	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3233	return (void *)(uintptr_t)1;
3234	}
3235	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3236	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3237
3238	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3239
3240	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3241	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3242	if (offNextCmd >= offCurrentCmd)
3243	{
3244	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3245	cbBefore = 0;
3246	}
3247	else
3248	{
3249	cbAfter = offFifoMax - offCurrentCmd;
3250	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3251	}
3252
3253	if (cbAfter + cbBefore >= cbPayloadReq)
3254	break;
3255	}
3256	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3257	}
3258
3259	/*
3260	* Copy out the memory and update what pcbAlreadyRead points to.
3261	*/
3262	if (cbAfter >= cbPayloadReq)
3263	memcpy(pbBounceBuf + cbAlreadyRead,
3264	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3265	cbPayloadReq - cbAlreadyRead);
3266	else
3267	{
3268	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3269	if (cbAlreadyRead < cbAfter)
3270	{
3271	memcpy(pbBounceBuf + cbAlreadyRead,
3272	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3273	cbAfter - cbAlreadyRead);
3274	cbAlreadyRead = cbAfter;
3275	}
3276	memcpy(pbBounceBuf + cbAlreadyRead,
3277	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3278	cbPayloadReq - cbAlreadyRead);
3279	}
3280	*pcbAlreadyRead = cbPayloadReq;
3281	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3282	return pbBounceBuf;
3283	}
3284
3285
3286	/**
3287	* Sends cursor position and visibility information from the FIFO to the front-end.
3288	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3289	*/
3290	static uint32_t
3291	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3292	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3293	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3294	{
3295	/*
3296	* Check if the cursor update counter has changed and try get a stable
3297	* set of values if it has. This is race-prone, especially consindering
3298	* the screen ID, but little we can do about that.
3299	*/
3300	uint32_t x, y, fVisible, idScreen;
3301	for (uint32_t i = 0; ; i++)
3302	{
3303	x = pFIFO[SVGA_FIFO_CURSOR_X];
3304	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3305	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3306	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3307	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3308	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3309	\|\| i > 3)
3310	break;
3311	if (i == 0)
3312	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3313	ASMNopPause();
3314	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3315	}
3316
3317	/*
3318	* Check if anything has changed, as calling into pDrv is not light-weight.
3319	*/
3320	if ( *pxLast == x
3321	&& *pyLast == y
3322	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3323	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3324	else
3325	{
3326	/*
3327	* Detected changes.
3328	*
3329	* We handle global, not per-screen visibility information by sending
3330	* pfnVBVAMousePointerShape without shape data.
3331	*/
3332	*pxLast = x;
3333	*pyLast = y;
3334	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3335	if (idScreen != SVGA_ID_INVALID)
3336	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3337	else if (*pfLastVisible != fVisible)
3338	{
3339	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3340	*pfLastVisible = fVisible;
3341	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3342	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3343	}
3344	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3345	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3346	}
3347
3348	/*
3349	* Update done. Signal this to the guest.
3350	*/
3351	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3352
3353	return uCursorUpdateCount;
3354	}
3355
3356
3357	/**
3358	* Checks if there is work to be done, either cursor updating or FIFO commands.
3359	*
3360	* @returns true if pending work, false if not.
3361	* @param pFIFO The FIFO to examine.
3362	* @param uLastCursorCount The last cursor update counter value.
3363	*/
3364	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3365	{
3366	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3367	return true;
3368
3369	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3370	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3371	return true;
3372
3373	return false;
3374	}
3375
3376
3377	/**
3378	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3379	*
3380	* @param pThis The VGA state.
3381	*/
3382	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3383	{
3384	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3385	to recheck it before doing the signalling. */
3386	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3387	AssertReturnVoid(pFIFO);
3388	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3389	&& pThis->svga.fFIFOThreadSleeping)
3390	{
3391	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3392	AssertRC(rc);
3393	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3394	}
3395	}
3396
3397
3398	/* The async FIFO handling thread. */
3399	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3400	{
3401	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3402	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3403	int rc;
3404
3405	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3406	return VINF_SUCCESS;
3407
3408	/*
3409	* Special mode where we only execute an external command and the go back
3410	* to being suspended. Currently, all ext cmds ends up here, with the reset
3411	* one also being eligble for runtime execution further down as well.
3412	*/
3413	if (pThis->svga.fFifoExtCommandWakeup)
3414	{
3415	vmsvgaR3FifoHandleExtCmd(pThis);
3416	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3417	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3418	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3419	else
3420	vmsvgaR3FifoHandleExtCmd(pThis);
3421	return VINF_SUCCESS;
3422	}
3423
3424
3425	/*
3426	* Signal the semaphore to make sure we don't wait for 250ms after a
3427	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3428	*/
3429	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3430
3431	/*
3432	* Allocate a bounce buffer for command we get from the FIFO.
3433	* (All code must return via the end of the function to free this buffer.)
3434	*/
3435	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3436	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3437
3438	/*
3439	* Polling/sleep interval config.
3440	*
3441	* We wait for an a short interval if the guest has recently given us work
3442	* to do, but the interval increases the longer we're kept idle. Once we've
3443	* reached the refresh timer interval, we'll switch to extended waits,
3444	* depending on it or the guest to kick us into action when needed.
3445	*
3446	* Should the refresh time go fishing, we'll just continue increasing the
3447	* sleep length till we reaches the 250 ms max after about 16 seconds.
3448	*/
3449	RTMSINTERVAL const cMsMinSleep = 16;
3450	RTMSINTERVAL const cMsIncSleep = 2;
3451	RTMSINTERVAL const cMsMaxSleep = 250;
3452	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3453	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3454
3455	/*
3456	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3457	*
3458	* Initialize with values that will detect an update from the guest.
3459	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3460	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3461	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3462	*/
3463	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3464	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3465	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3466	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3467	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3468
3469	/*
3470	* The FIFO loop.
3471	*/
3472	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3473	bool fBadOrDisabledFifo = false;
3474	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3475	{
3476	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3477	/*
3478	* Should service the run loop every so often.
3479	*/
3480	if (pThis->svga.f3DEnabled)
3481	vmsvga3dCocoaServiceRunLoop();
3482	# endif
3483
3484	/*
3485	* Unless there's already work pending, go to sleep for a short while.
3486	* (See polling/sleep interval config above.)
3487	*/
3488	if ( fBadOrDisabledFifo
3489	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3490	{
3491	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3492	Assert(pThis->cMilliesRefreshInterval > 0);
3493	if (cMsSleep < pThis->cMilliesRefreshInterval)
3494	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3495	else
3496	{
3497	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3498	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3499	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3500	# endif
3501	if ( !fBadOrDisabledFifo
3502	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3503	rc = VINF_SUCCESS;
3504	else
3505	{
3506	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3507	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3508	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3509	}
3510	}
3511	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3512	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3513	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3514	{
3515	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3516	break;
3517	}
3518	}
3519	else
3520	rc = VINF_SUCCESS;
3521	fBadOrDisabledFifo = false;
3522	if (rc == VERR_TIMEOUT)
3523	{
3524	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3525	{
3526	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3527	continue;
3528	}
3529	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3530
3531	Log(("vmsvgaFIFOLoop: timeout\n"));
3532	}
3533	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3534	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3535	cMsSleep = cMsMinSleep;
3536
3537	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3538	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3539	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3540
3541	/*
3542	* Handle external commands (currently only reset).
3543	*/
3544	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3545	{
3546	vmsvgaR3FifoHandleExtCmd(pThis);
3547	continue;
3548	}
3549
3550	/*
3551	* The device must be enabled and configured.
3552	*/
3553	if ( !pThis->svga.fEnabled
3554	\|\| !pThis->svga.fConfigured)
3555	{
3556	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3557	fBadOrDisabledFifo = true;
3558	cMsSleep = cMsMaxSleep; /* cheat */
3559	continue;
3560	}
3561
3562	/*
3563	* Get and check the min/max values. We ASSUME that they will remain
3564	* unchanged while we process requests. A further ASSUMPTION is that
3565	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3566	* we don't read it back while in the loop.
3567	*/
3568	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3569	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3570	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3571	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3572	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3573	\|\| offFifoMax <= offFifoMin
3574	\|\| offFifoMax > pThis->svga.cbFIFO
3575	\|\| (offFifoMax & 3) != 0
3576	\|\| (offFifoMin & 3) != 0
3577	\|\| offCurrentCmd < offFifoMin
3578	\|\| offCurrentCmd > offFifoMax))
3579	{
3580	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3581	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3582	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3583	fBadOrDisabledFifo = true;
3584	continue;
3585	}
3586	RT_UNTRUSTED_VALIDATED_FENCE();
3587	if (RT_UNLIKELY(offCurrentCmd & 3))
3588	{
3589	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3590	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3591	offCurrentCmd &= ~UINT32_C(3);
3592	}
3593
3594	/*
3595	* Update the cursor position before we start on the FIFO commands.
3596	*/
3597	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3598	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3599	{
3600	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3601	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3602	{ /* halfways likely */ }
3603	else
3604	{
3605	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3606	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3607	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3608	}
3609	}
3610
3611	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3612	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3613	*
3614	* Will break out of the switch on failure.
3615	* Will restart and quit the loop if the thread was requested to stop.
3616	*
3617	* @param a_PtrVar Request variable pointer.
3618	* @param a_Type Request typedef (not pointer) for casting.
3619	* @param a_cbPayloadReq How much payload to fetch.
3620	* @remarks Accesses a bunch of variables in the current scope!
3621	*/
3622	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3623	if (1) { \
3624	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3625	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3626	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3627	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3628	} else do {} while (0)
3629	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3630	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3631	* buffer after figuring out the actual command size.
3632	*
3633	* Will break out of the switch on failure.
3634	*
3635	* @param a_PtrVar Request variable pointer.
3636	* @param a_Type Request typedef (not pointer) for casting.
3637	* @param a_cbPayloadReq How much payload to fetch.
3638	* @remarks Accesses a bunch of variables in the current scope!
3639	*/
3640	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3641	if (1) { \
3642	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3643	} else do {} while (0)
3644
3645	/*
3646	* Mark the FIFO as busy.
3647	*/
3648	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3649	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3650	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3651
3652	/*
3653	* Execute all queued FIFO commands.
3654	* Quit if pending external command or changes in the thread state.
3655	*/
3656	bool fDone = false;
3657	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3658	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3659	{
3660	uint32_t cbPayload = 0;
3661	uint32_t u32IrqStatus = 0;
3662
3663	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3664
3665	/* First check any pending actions. */
3666	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3667	{
3668	vmsvgaChangeMode(pThis);
3669	# ifdef VBOX_WITH_VMSVGA3D
3670	if (pThis->svga.p3dState != NULL)
3671	vmsvga3dChangeMode(pThis);
3672	# endif
3673	}
3674
3675	/* Check for pending external commands (reset). */
3676	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3677	break;
3678
3679	/*
3680	* Process the command.
3681	*/
3682	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3683	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3684	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3685	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3686	switch (enmCmdId)
3687	{
3688	case SVGA_CMD_INVALID_CMD:
3689	/* Nothing to do. */
3690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3691	break;
3692
3693	case SVGA_CMD_FENCE:
3694	{
3695	SVGAFifoCmdFence *pCmdFence;
3696	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3697	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3698	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3699	{
3700	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3701	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3702
3703	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3704	{
3705	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3706	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3707	}
3708	else
3709	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3710	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3711	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3712	{
3713	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3714	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3715	}
3716	}
3717	else
3718	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3719	break;
3720	}
3721	case SVGA_CMD_UPDATE:
3722	case SVGA_CMD_UPDATE_VERBOSE:
3723	{
3724	SVGAFifoCmdUpdate *pUpdate;
3725	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3726	if (enmCmdId == SVGA_CMD_UPDATE)
3727	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3728	else
3729	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3730	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3731	/** @todo Multiple screens? */
3732	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3733	AssertBreak(pScreen);
3734	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3735	break;
3736	}
3737
3738	case SVGA_CMD_DEFINE_CURSOR:
3739	{
3740	/* Followed by bitmap data. */
3741	SVGAFifoCmdDefineCursor *pCursor;
3742	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3743	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3744
3745	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3746	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3747	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3748	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3749	AssertBreak(pCursor->andMaskDepth <= 32);
3750	AssertBreak(pCursor->xorMaskDepth <= 32);
3751	RT_UNTRUSTED_VALIDATED_FENCE();
3752
3753	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3754	uint32_t cbAndMask = cbAndLine * pCursor->height;
3755	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3756	uint32_t cbXorMask = cbXorLine * pCursor->height;
3757	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3758
3759	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3760	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3761	break;
3762	}
3763
3764	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3765	{
3766	/* Followed by bitmap data. */
3767	uint32_t cbCursorShape, cbAndMask;
3768	uint8_t *pCursorCopy;
3769	uint32_t cbCmd;
3770
3771	SVGAFifoCmdDefineAlphaCursor *pCursor;
3772	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3773	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3774
3775	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3776
3777	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3778	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3779	RT_UNTRUSTED_VALIDATED_FENCE();
3780
3781	/* Refetch the bitmap data as well. */
3782	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3783	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3784	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3785
3786	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3787	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3788	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3789	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3790
3791	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3792	AssertBreak(pCursorCopy);
3793
3794	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3795	memset(pCursorCopy, 0xff, cbAndMask);
3796	/* Colour data */
3797	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3798
3799	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3800	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3801	break;
3802	}
3803
3804	case SVGA_CMD_ESCAPE:
3805	{
3806	/* Followed by nsize bytes of data. */
3807	SVGAFifoCmdEscape *pEscape;
3808	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3809	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3810
3811	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3812	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3813	RT_UNTRUSTED_VALIDATED_FENCE();
3814	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3815	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3816
3817	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3818	{
3819	AssertBreak(pEscape->size >= sizeof(uint32_t));
3820	RT_UNTRUSTED_VALIDATED_FENCE();
3821	uint32_t cmd = (uint32_t )(pEscape + 1);
3822	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3823
3824	switch (cmd)
3825	{
3826	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3827	{
3828	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3829	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3830	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3831
3832	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3833	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3834	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3835
3836	RT_NOREF_PV(pVideoCmd);
3837	break;
3838
3839	}
3840
3841	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3842	{
3843	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3844	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3845	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3846	RT_NOREF_PV(pVideoCmd);
3847	break;
3848	}
3849
3850	default:
3851	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3852	break;
3853	}
3854	}
3855	else
3856	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3857
3858	break;
3859	}
3860	# ifdef VBOX_WITH_VMSVGA3D
3861	case SVGA_CMD_DEFINE_GMR2:
3862	{
3863	SVGAFifoCmdDefineGMR2 *pCmd;
3864	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3865	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3866	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3867
3868	/* Validate current GMR id. */
3869	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3870	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3871	RT_UNTRUSTED_VALIDATED_FENCE();
3872
3873	if (!pCmd->numPages)
3874	{
3875	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3876	vmsvgaGMRFree(pThis, pCmd->gmrId);
3877	}
3878	else
3879	{
3880	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3881	if (pGMR->cMaxPages)
3882	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3883
3884	/* Not sure if we should always free the descriptor, but for simplicity
3885	we do so if the new size is smaller than the current. */
3886	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3887	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3888	vmsvgaGMRFree(pThis, pCmd->gmrId);
3889
3890	pGMR->cMaxPages = pCmd->numPages;
3891	/* The rest is done by the REMAP_GMR2 command. */
3892	}
3893	break;
3894	}
3895
3896	case SVGA_CMD_REMAP_GMR2:
3897	{
3898	/* Followed by page descriptors or guest ptr. */
3899	SVGAFifoCmdRemapGMR2 *pCmd;
3900	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3901	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3902
3903	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3904	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3905	RT_UNTRUSTED_VALIDATED_FENCE();
3906
3907	/* Calculate the size of what comes after next and fetch it. */
3908	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3909	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3910	cbCmd += sizeof(SVGAGuestPtr);
3911	else
3912	{
3913	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3914	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3915	{
3916	cbCmd += cbPageDesc;
3917	pCmd->numPages = 1;
3918	}
3919	else
3920	{
3921	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3922	cbCmd += cbPageDesc * pCmd->numPages;
3923	}
3924	}
3925	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3926
3927	/* Validate current GMR id and size. */
3928	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3929	RT_UNTRUSTED_VALIDATED_FENCE();
3930	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3931	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3932	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3933	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3934
3935	if (pCmd->numPages == 0)
3936	break;
3937
3938	/** @todo Move to a separate function vmsvgaGMRRemap() */
3939
3940	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3941	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3942
3943	/*
3944	* We flatten the existing descriptors into a page array, overwrite the
3945	* pages specified in this command and then recompress the descriptor.
3946	*/
3947	/** @todo Optimize the GMR remap algorithm! */
3948
3949	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3950	uint64_t *paNewPage64 = NULL;
3951	if (pGMR->paDesc)
3952	{
3953	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3954
3955	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3956	AssertBreak(paNewPage64);
3957
3958	uint32_t idxPage = 0;
3959	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3960	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3961	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3962	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3963	RT_UNTRUSTED_VALIDATED_FENCE();
3964	}
3965
3966	/* Free the old GMR if present. */
3967	if (pGMR->paDesc)
3968	RTMemFree(pGMR->paDesc);
3969
3970	/* Allocate the maximum amount possible (everything non-continuous) */
3971	PVMSVGAGMRDESCRIPTOR paDescs;
3972	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3973	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3974
3975	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3976	{
3977	/** @todo */
3978	AssertFailed();
3979	pGMR->numDescriptors = 0;
3980	}
3981	else
3982	{
3983	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3984	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3985	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3986
3987	if (paNewPage64)
3988	{
3989	/* Overwrite the old page array with the new page values. */
3990	if (fGCPhys64)
3991	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3992	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3993	else
3994	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3995	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3996
3997	/* Use the updated page array instead of the command data. */
3998	fGCPhys64 = true;
3999	paPages64 = paNewPage64;
4000	pCmd->numPages = cNewTotalPages;
4001	}
4002
4003	/* The first page. */
4004	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4005	* applied to paNewPage64. */
4006	RTGCPHYS GCPhys;
4007	if (fGCPhys64)
4008	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4009	else
4010	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4011	paDescs[0].GCPhys = GCPhys;
4012	paDescs[0].numPages = 1;
4013
4014	/* Subsequent pages. */
4015	uint32_t iDescriptor = 0;
4016	for (uint32_t i = 1; i < pCmd->numPages; i++)
4017	{
4018	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4019	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4020	else
4021	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4022
4023	/* Continuous physical memory? */
4024	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4025	{
4026	Assert(paDescs[iDescriptor].numPages);
4027	paDescs[iDescriptor].numPages++;
4028	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4029	}
4030	else
4031	{
4032	iDescriptor++;
4033	paDescs[iDescriptor].GCPhys = GCPhys;
4034	paDescs[iDescriptor].numPages = 1;
4035	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4036	}
4037	}
4038
4039	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4040	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4041	pGMR->numDescriptors = iDescriptor + 1;
4042	}
4043
4044	if (paNewPage64)
4045	RTMemFree(paNewPage64);
4046
4047	# ifdef DEBUG_GMR_ACCESS
4048	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4049	# endif
4050	break;
4051	}
4052	# endif // VBOX_WITH_VMSVGA3D
4053	case SVGA_CMD_DEFINE_SCREEN:
4054	{
4055	/* The size of this command is specified by the guest and depends on capabilities. */
4056	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4057
4058	SVGAFifoCmdDefineScreen *pCmd;
4059	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4060	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4061	RT_UNTRUSTED_VALIDATED_FENCE();
4062
4063	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4064	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4065	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4066
4067	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4068	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4069	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4070
4071	uint32_t const idScreen = pCmd->screen.id;
4072	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4073
4074	uint32_t const uWidth = pCmd->screen.size.width;
4075	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4076
4077	uint32_t const uHeight = pCmd->screen.size.height;
4078	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4079
4080	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4081	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4082	AssertBreak(cbWidth <= cbPitch);
4083
4084	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4085	AssertBreak(uScreenOffset < pThis->vram_size);
4086
4087	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4088	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4089	AssertBreak( (uHeight == 0 && cbPitch == 0)
4090	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4091	RT_UNTRUSTED_VALIDATED_FENCE();
4092
4093	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4094
4095	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4096
4097	pScreen->fDefined = true;
4098	pScreen->fModified = true;
4099	pScreen->fuScreen = pCmd->screen.flags;
4100	pScreen->idScreen = idScreen;
4101	if (!fBlank)
4102	{
4103	AssertBreak(uWidth > 0 && uHeight > 0);
4104
4105	pScreen->xOrigin = pCmd->screen.root.x;
4106	pScreen->yOrigin = pCmd->screen.root.y;
4107	pScreen->cWidth = uWidth;
4108	pScreen->cHeight = uHeight;
4109	pScreen->offVRAM = uScreenOffset;
4110	pScreen->cbPitch = cbPitch;
4111	pScreen->cBpp = 32;
4112	}
4113	else
4114	{
4115	/* Keep old values. */
4116	}
4117
4118	pThis->svga.fGFBRegisters = false;
4119	vmsvgaChangeMode(pThis);
4120	break;
4121	}
4122
4123	case SVGA_CMD_DESTROY_SCREEN:
4124	{
4125	SVGAFifoCmdDestroyScreen *pCmd;
4126	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4127	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4128
4129	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4130
4131	uint32_t const idScreen = pCmd->screenId;
4132	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4133	RT_UNTRUSTED_VALIDATED_FENCE();
4134
4135	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4136	pScreen->fModified = true;
4137	pScreen->fDefined = false;
4138	pScreen->idScreen = idScreen;
4139
4140	vmsvgaChangeMode(pThis);
4141	break;
4142	}
4143
4144	case SVGA_CMD_DEFINE_GMRFB:
4145	{
4146	SVGAFifoCmdDefineGMRFB *pCmd;
4147	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4148	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4149
4150	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4151	pSVGAState->GMRFB.ptr = pCmd->ptr;
4152	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4153	pSVGAState->GMRFB.format = pCmd->format;
4154	break;
4155	}
4156
4157	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4158	{
4159	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4160	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4161	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4162
4163	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4164	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4165
4166	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4167	RT_UNTRUSTED_VALIDATED_FENCE();
4168
4169	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4170	AssertBreak(pScreen);
4171
4172	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4173	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4174
4175	/* Clip destRect to the screen dimensions. */
4176	SVGASignedRect screenRect;
4177	screenRect.left = 0;
4178	screenRect.top = 0;
4179	screenRect.right = pScreen->cWidth;
4180	screenRect.bottom = pScreen->cHeight;
4181	SVGASignedRect clipRect = pCmd->destRect;
4182	vmsvgaClipRect(&screenRect, &clipRect);
4183	RT_UNTRUSTED_VALIDATED_FENCE();
4184
4185	uint32_t const width = clipRect.right - clipRect.left;
4186	uint32_t const height = clipRect.bottom - clipRect.top;
4187
4188	if ( width == 0
4189	\|\| height == 0)
4190	break; /* Nothing to do. */
4191
4192	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4193	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4194
4195	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4196	* Prepare parameters for vmsvgaGMRTransfer.
4197	*/
4198	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4199
4200	/* Destination: host buffer which describes the screen 0 VRAM.
4201	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4202	*/
4203	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4204	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4205	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4206	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4207	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4208	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4209	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4210	+ cbScanline * clipRect.top;
4211	int32_t const cbHstPitch = cbScanline;
4212
4213	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4214	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4215	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4216	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4217	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4218
4219	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4220	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4221	gstPtr, offGst, cbGstPitch,
4222	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4223	AssertRC(rc);
4224	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4225	break;
4226	}
4227
4228	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4229	{
4230	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4231	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4232	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4233
4234	/* Note! This can fetch 3d render results as well!! */
4235	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4236	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4237
4238	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4239	RT_UNTRUSTED_VALIDATED_FENCE();
4240
4241	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4242	AssertBreak(pScreen);
4243
4244	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4245	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4246
4247	/* Clip destRect to the screen dimensions. */
4248	SVGASignedRect screenRect;
4249	screenRect.left = 0;
4250	screenRect.top = 0;
4251	screenRect.right = pScreen->cWidth;
4252	screenRect.bottom = pScreen->cHeight;
4253	SVGASignedRect clipRect = pCmd->srcRect;
4254	vmsvgaClipRect(&screenRect, &clipRect);
4255	RT_UNTRUSTED_VALIDATED_FENCE();
4256
4257	uint32_t const width = clipRect.right - clipRect.left;
4258	uint32_t const height = clipRect.bottom - clipRect.top;
4259
4260	if ( width == 0
4261	\|\| height == 0)
4262	break; /* Nothing to do. */
4263
4264	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4265	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4266
4267	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4268	* Prepare parameters for vmsvgaGMRTransfer.
4269	*/
4270	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4271
4272	/* Source: host buffer which describes the screen 0 VRAM.
4273	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4274	*/
4275	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4276	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4277	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4278	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4279	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4280	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4281	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4282	+ cbScanline * clipRect.top;
4283	int32_t const cbHstPitch = cbScanline;
4284
4285	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4286	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4287	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4288	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4289	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4290
4291	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4292	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4293	gstPtr, offGst, cbGstPitch,
4294	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4295	AssertRC(rc);
4296	break;
4297	}
4298
4299	case SVGA_CMD_ANNOTATION_FILL:
4300	{
4301	SVGAFifoCmdAnnotationFill *pCmd;
4302	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4303	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4304
4305	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4306	pSVGAState->colorAnnotation = pCmd->color;
4307	break;
4308	}
4309
4310	case SVGA_CMD_ANNOTATION_COPY:
4311	{
4312	SVGAFifoCmdAnnotationCopy *pCmd;
4313	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4314	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4315
4316	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4317	AssertFailed();
4318	break;
4319	}
4320
4321	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4322
4323	default:
4324	# ifdef VBOX_WITH_VMSVGA3D
4325	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4326	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4327	{
4328	RT_UNTRUSTED_VALIDATED_FENCE();
4329
4330	/* All 3d commands start with a common header, which defines the size of the command. */
4331	SVGA3dCmdHeader *pHdr;
4332	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4333	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4334	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4335	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4336
4337	if (RT_LIKELY(pThis->svga.f3DEnabled))
4338	{ /* likely */ }
4339	else
4340	{
4341	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4342	break;
4343	}
4344
4345	/**
4346	* Check that the 3D command has at least a_cbMin of payload bytes after the
4347	* header. Will break out of the switch if it doesn't.
4348	*/
4349	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4350	if (1) { \
4351	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4352	RT_UNTRUSTED_VALIDATED_FENCE(); \
4353	} else do {} while (0)
4354	switch ((int)enmCmdId)
4355	{
4356	case SVGA_3D_CMD_SURFACE_DEFINE:
4357	{
4358	uint32_t cMipLevels;
4359	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4360	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4361	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4362
4363	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4364	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4365	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4366	# ifdef DEBUG_GMR_ACCESS
4367	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4368	# endif
4369	break;
4370	}
4371
4372	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4373	{
4374	uint32_t cMipLevels;
4375	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4376	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4377	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4378
4379	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4380	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4381	pCmd->multisampleCount, pCmd->autogenFilter,
4382	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4383	break;
4384	}
4385
4386	case SVGA_3D_CMD_SURFACE_DESTROY:
4387	{
4388	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4389	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4390	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4391	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4392	break;
4393	}
4394
4395	case SVGA_3D_CMD_SURFACE_COPY:
4396	{
4397	uint32_t cCopyBoxes;
4398	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4399	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4400	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4401
4402	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4403	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4404	break;
4405	}
4406
4407	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4408	{
4409	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4410	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4411	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4412
4413	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4414	break;
4415	}
4416
4417	case SVGA_3D_CMD_SURFACE_DMA:
4418	{
4419	uint32_t cCopyBoxes;
4420	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4421	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4423
4424	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4425	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4426	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4427	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4428	break;
4429	}
4430
4431	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4432	{
4433	uint32_t cRects;
4434	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4435	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4436	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4437
4438	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4439	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_CONTEXT_DEFINE:
4444	{
4445	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4448
4449	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4450	break;
4451	}
4452
4453	case SVGA_3D_CMD_CONTEXT_DESTROY:
4454	{
4455	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4456	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4457	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4458
4459	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4460	break;
4461	}
4462
4463	case SVGA_3D_CMD_SETTRANSFORM:
4464	{
4465	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4466	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4467	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4468
4469	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4470	break;
4471	}
4472
4473	case SVGA_3D_CMD_SETZRANGE:
4474	{
4475	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4476	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4477	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4478
4479	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4480	break;
4481	}
4482
4483	case SVGA_3D_CMD_SETRENDERSTATE:
4484	{
4485	uint32_t cRenderStates;
4486	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4487	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4489
4490	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4491	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4492	break;
4493	}
4494
4495	case SVGA_3D_CMD_SETRENDERTARGET:
4496	{
4497	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4500
4501	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4502	break;
4503	}
4504
4505	case SVGA_3D_CMD_SETTEXTURESTATE:
4506	{
4507	uint32_t cTextureStates;
4508	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4509	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4510	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4511
4512	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4513	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4514	break;
4515	}
4516
4517	case SVGA_3D_CMD_SETMATERIAL:
4518	{
4519	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4520	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4522
4523	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_SETLIGHTDATA:
4528	{
4529	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4532
4533	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4534	break;
4535	}
4536
4537	case SVGA_3D_CMD_SETLIGHTENABLED:
4538	{
4539	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4540	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4541	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4542
4543	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4544	break;
4545	}
4546
4547	case SVGA_3D_CMD_SETVIEWPORT:
4548	{
4549	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4550	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4552
4553	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4554	break;
4555	}
4556
4557	case SVGA_3D_CMD_SETCLIPPLANE:
4558	{
4559	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4560	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4561	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4562
4563	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4564	break;
4565	}
4566
4567	case SVGA_3D_CMD_CLEAR:
4568	{
4569	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4571	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4572
4573	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4574	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4575	break;
4576	}
4577
4578	case SVGA_3D_CMD_PRESENT:
4579	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4580	{
4581	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4582	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4583	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4585	else
4586	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4587
4588	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4589
4590	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4591	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4592	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4593	break;
4594	}
4595
4596	case SVGA_3D_CMD_SHADER_DEFINE:
4597	{
4598	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4599	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4601
4602	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4603	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4604	break;
4605	}
4606
4607	case SVGA_3D_CMD_SHADER_DESTROY:
4608	{
4609	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4610	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4612
4613	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4614	break;
4615	}
4616
4617	case SVGA_3D_CMD_SET_SHADER:
4618	{
4619	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4620	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4621	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4622
4623	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4624	break;
4625	}
4626
4627	case SVGA_3D_CMD_SET_SHADER_CONST:
4628	{
4629	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4630	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4631	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4632
4633	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4634	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4635	break;
4636	}
4637
4638	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4639	{
4640	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4641	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4642	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4643
4644	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4645	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4646	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4647	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4648	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4649
4650	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4651	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4652
4653	RT_UNTRUSTED_VALIDATED_FENCE();
4654
4655	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4656	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4657	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4658
4659	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4660	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4661	pNumRange, cVertexDivisor, pVertexDivisor);
4662	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_SETSCISSORRECT:
4667	{
4668	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4671
4672	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_BEGIN_QUERY:
4677	{
4678	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4679	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4681
4682	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4683	break;
4684	}
4685
4686	case SVGA_3D_CMD_END_QUERY:
4687	{
4688	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4689	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4691
4692	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4693	break;
4694	}
4695
4696	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4697	{
4698	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4699	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4700	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4701
4702	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4703	break;
4704	}
4705
4706	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4707	{
4708	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4709	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4711
4712	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4713	break;
4714	}
4715
4716	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4717	/* context id + surface id? */
4718	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4719	break;
4720	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4721	/* context id + surface id? */
4722	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4723	break;
4724
4725	default:
4726	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4727	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4728	break;
4729	}
4730	}
4731	else
4732	# endif // VBOX_WITH_VMSVGA3D
4733	{
4734	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4735	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4736	}
4737	}
4738
4739	/* Go to the next slot */
4740	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4741	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4742	if (offCurrentCmd >= offFifoMax)
4743	{
4744	offCurrentCmd -= offFifoMax - offFifoMin;
4745	Assert(offCurrentCmd >= offFifoMin);
4746	Assert(offCurrentCmd < offFifoMax);
4747	}
4748	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4749	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4750
4751	/*
4752	* Raise IRQ if required. Must enter the critical section here
4753	* before making final decisions here, otherwise cubebench and
4754	* others may end up waiting forever.
4755	*/
4756	if ( u32IrqStatus
4757	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4758	{
4759	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4760	AssertRC(rc2);
4761
4762	/* FIFO progress might trigger an interrupt. */
4763	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4764	{
4765	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4766	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4767	}
4768
4769	/* Unmasked IRQ pending? */
4770	if (pThis->svga.u32IrqMask & u32IrqStatus)
4771	{
4772	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4773	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4774	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4775	}
4776
4777	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4778	}
4779	}
4780
4781	/* If really done, clear the busy flag. */
4782	if (fDone)
4783	{
4784	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4785	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4786	}
4787	}
4788
4789	/*
4790	* Free the bounce buffer. (There are no returns above!)
4791	*/
4792	RTMemFree(pbBounceBuf);
4793
4794	return VINF_SUCCESS;
4795	}
4796
4797	/**
4798	* Free the specified GMR
4799	*
4800	* @param pThis VGA device instance data.
4801	* @param idGMR GMR id
4802	*/
4803	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4804	{
4805	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4806
4807	/* Free the old descriptor if present. */
4808	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4809	if ( pGMR->numDescriptors
4810	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4811	{
4812	# ifdef DEBUG_GMR_ACCESS
4813	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4814	# endif
4815
4816	Assert(pGMR->paDesc);
4817	RTMemFree(pGMR->paDesc);
4818	pGMR->paDesc = NULL;
4819	pGMR->numDescriptors = 0;
4820	pGMR->cbTotal = 0;
4821	pGMR->cMaxPages = 0;
4822	}
4823	Assert(!pGMR->cMaxPages);
4824	Assert(!pGMR->cbTotal);
4825	}
4826
4827	/**
4828	* Copy between a GMR and a host memory buffer.
4829	*
4830	* @returns VBox status code.
4831	* @param pThis VGA device instance data.
4832	* @param enmTransferType Transfer type (read/write)
4833	* @param pbHstBuf Host buffer pointer (valid)
4834	* @param cbHstBuf Size of host buffer (valid)
4835	* @param offHst Host buffer offset of the first scanline
4836	* @param cbHstPitch Destination buffer pitch
4837	* @param gstPtr GMR description
4838	* @param offGst Guest buffer offset of the first scanline
4839	* @param cbGstPitch Guest buffer pitch
4840	* @param cbWidth Width in bytes to copy
4841	* @param cHeight Number of scanllines to copy
4842	*/
4843	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4844	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4845	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4846	uint32_t cbWidth, uint32_t cHeight)
4847	{
4848	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4849	int rc;
4850
4851	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4852	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4853	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4854	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4855	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4856
4857	PGMR pGMR;
4858	uint32_t cbGmr; /* The GMR size in bytes. */
4859	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4860	{
4861	pGMR = NULL;
4862	cbGmr = pThis->vram_size;
4863	}
4864	else
4865	{
4866	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4867	RT_UNTRUSTED_VALIDATED_FENCE();
4868	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4869	cbGmr = pGMR->cbTotal;
4870	}
4871
4872	/*
4873	* GMR
4874	*/
4875	/* Calculate GMR offset of the data to be copied. */
4876	AssertMsgReturn(gstPtr.offset < cbGmr,
4877	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4878	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4879	VERR_INVALID_PARAMETER);
4880	RT_UNTRUSTED_VALIDATED_FENCE();
4881	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4882	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4883	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4884	VERR_INVALID_PARAMETER);
4885	RT_UNTRUSTED_VALIDATED_FENCE();
4886	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4887
4888	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4889	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4890	AssertMsgReturn(cbGmrScanline != 0,
4891	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4892	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4893	VERR_INVALID_PARAMETER);
4894	RT_UNTRUSTED_VALIDATED_FENCE();
4895	AssertMsgReturn(cbWidth <= cbGmrScanline,
4896	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4897	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4898	VERR_INVALID_PARAMETER);
4899	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4900	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4901	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4902	VERR_INVALID_PARAMETER);
4903	RT_UNTRUSTED_VALIDATED_FENCE();
4904
4905	/* How many bytes are available for the data in the GMR. */
4906	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4907
4908	/* How many scanlines would fit into the available data. */
4909	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4910	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4911	if (cbWidth <= cbGmrLastScanline)
4912	++cGmrScanlines;
4913
4914	if (cHeight > cGmrScanlines)
4915	cHeight = cGmrScanlines;
4916
4917	AssertMsgReturn(cHeight > 0,
4918	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4919	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4920	VERR_INVALID_PARAMETER);
4921	RT_UNTRUSTED_VALIDATED_FENCE();
4922
4923	/*
4924	* Host buffer.
4925	*/
4926	AssertMsgReturn(offHst < cbHstBuf,
4927	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4928	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4929	VERR_INVALID_PARAMETER);
4930
4931	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4932	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4933	AssertMsgReturn(cbHstScanline != 0,
4934	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4935	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4936	VERR_INVALID_PARAMETER);
4937	AssertMsgReturn(cbWidth <= cbHstScanline,
4938	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4939	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4940	VERR_INVALID_PARAMETER);
4941	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4942	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4943	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4944	VERR_INVALID_PARAMETER);
4945
4946	/* How many bytes are available for the data in the buffer. */
4947	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4948
4949	/* How many scanlines would fit into the available data. */
4950	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4951	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4952	if (cbWidth <= cbHstLastScanline)
4953	++cHstScanlines;
4954
4955	if (cHeight > cHstScanlines)
4956	cHeight = cHstScanlines;
4957
4958	AssertMsgReturn(cHeight > 0,
4959	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4960	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4961	VERR_INVALID_PARAMETER);
4962
4963	uint8_t *pbHst = pbHstBuf + offHst;
4964
4965	/* Shortcut for the framebuffer. */
4966	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4967	{
4968	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4969
4970	uint8_t const *pbSrc;
4971	int32_t cbSrcPitch;
4972	uint8_t *pbDst;
4973	int32_t cbDstPitch;
4974
4975	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4976	{
4977	pbSrc = pbHst;
4978	cbSrcPitch = cbHstPitch;
4979	pbDst = pbGst;
4980	cbDstPitch = cbGstPitch;
4981	}
4982	else
4983	{
4984	pbSrc = pbGst;
4985	cbSrcPitch = cbGstPitch;
4986	pbDst = pbHst;
4987	cbDstPitch = cbHstPitch;
4988	}
4989
4990	if ( cbWidth == (uint32_t)cbGstPitch
4991	&& cbGstPitch == cbHstPitch)
4992	{
4993	/* Entire scanlines, positive pitch. */
4994	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4995	}
4996	else
4997	{
4998	for (uint32_t i = 0; i < cHeight; ++i)
4999	{
5000	memcpy(pbDst, pbSrc, cbWidth);
5001
5002	pbDst += cbDstPitch;
5003	pbSrc += cbSrcPitch;
5004	}
5005	}
5006	return VINF_SUCCESS;
5007	}
5008
5009	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5010	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5011
5012	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5013	uint32_t iDesc = 0; /* Index in the descriptor array. */
5014	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5015	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5016	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5017	for (uint32_t i = 0; i < cHeight; ++i)
5018	{
5019	uint32_t cbCurrentWidth = cbWidth;
5020	uint32_t offGmrCurrent = offGmrScanline;
5021	uint8_t *pbCurrentHost = pbHstScanline;
5022
5023	/* Find the right descriptor */
5024	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5025	{
5026	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5027	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5028	++iDesc;
5029	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5030	}
5031
5032	while (cbCurrentWidth)
5033	{
5034	uint32_t cbToCopy;
5035
5036	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5037	{
5038	cbToCopy = cbCurrentWidth;
5039	}
5040	else
5041	{
5042	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5043	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5044	}
5045
5046	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5047
5048	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5049
5050	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5051	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5052	else
5053	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5054	AssertRCBreak(rc);
5055
5056	cbCurrentWidth -= cbToCopy;
5057	offGmrCurrent += cbToCopy;
5058	pbCurrentHost += cbToCopy;
5059
5060	/* Go to the next descriptor if there's anything left. */
5061	if (cbCurrentWidth)
5062	{
5063	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5064	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5065	++iDesc;
5066	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5067	}
5068	}
5069
5070	offGmrScanline += cbGstPitch;
5071	pbHstScanline += cbHstPitch;
5072	}
5073
5074	return VINF_SUCCESS;
5075	}
5076
5077
5078	/**
5079	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5080	*
5081	* @param pSizeSrc Source surface dimensions.
5082	* @param pSizeDest Destination surface dimensions.
5083	* @param pBox Coordinates to be clipped.
5084	*/
5085	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5086	const SVGA3dSize *pSizeDest,
5087	SVGA3dCopyBox *pBox)
5088	{
5089	/* Src x, w */
5090	if (pBox->srcx > pSizeSrc->width)
5091	pBox->srcx = pSizeSrc->width;
5092	if (pBox->w > pSizeSrc->width - pBox->srcx)
5093	pBox->w = pSizeSrc->width - pBox->srcx;
5094
5095	/* Src y, h */
5096	if (pBox->srcy > pSizeSrc->height)
5097	pBox->srcy = pSizeSrc->height;
5098	if (pBox->h > pSizeSrc->height - pBox->srcy)
5099	pBox->h = pSizeSrc->height - pBox->srcy;
5100
5101	/* Src z, d */
5102	if (pBox->srcz > pSizeSrc->depth)
5103	pBox->srcz = pSizeSrc->depth;
5104	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5105	pBox->d = pSizeSrc->depth - pBox->srcz;
5106
5107	/* Dest x, w */
5108	if (pBox->x > pSizeDest->width)
5109	pBox->x = pSizeDest->width;
5110	if (pBox->w > pSizeDest->width - pBox->x)
5111	pBox->w = pSizeDest->width - pBox->x;
5112
5113	/* Dest y, h */
5114	if (pBox->y > pSizeDest->height)
5115	pBox->y = pSizeDest->height;
5116	if (pBox->h > pSizeDest->height - pBox->y)
5117	pBox->h = pSizeDest->height - pBox->y;
5118
5119	/* Dest z, d */
5120	if (pBox->z > pSizeDest->depth)
5121	pBox->z = pSizeDest->depth;
5122	if (pBox->d > pSizeDest->depth - pBox->z)
5123	pBox->d = pSizeDest->depth - pBox->z;
5124	}
5125
5126	/**
5127	* Unsigned coordinates in pBox. Clip to [0; pSize).
5128	*
5129	* @param pSize Source surface dimensions.
5130	* @param pBox Coordinates to be clipped.
5131	*/
5132	void vmsvgaClipBox(const SVGA3dSize *pSize,
5133	SVGA3dBox *pBox)
5134	{
5135	/* x, w */
5136	if (pBox->x > pSize->width)
5137	pBox->x = pSize->width;
5138	if (pBox->w > pSize->width - pBox->x)
5139	pBox->w = pSize->width - pBox->x;
5140
5141	/* y, h */
5142	if (pBox->y > pSize->height)
5143	pBox->y = pSize->height;
5144	if (pBox->h > pSize->height - pBox->y)
5145	pBox->h = pSize->height - pBox->y;
5146
5147	/* z, d */
5148	if (pBox->z > pSize->depth)
5149	pBox->z = pSize->depth;
5150	if (pBox->d > pSize->depth - pBox->z)
5151	pBox->d = pSize->depth - pBox->z;
5152	}
5153
5154	/**
5155	* Clip.
5156	*
5157	* @param pBound Bounding rectangle.
5158	* @param pRect Rectangle to be clipped.
5159	*/
5160	void vmsvgaClipRect(SVGASignedRect const *pBound,
5161	SVGASignedRect *pRect)
5162	{
5163	int32_t left;
5164	int32_t top;
5165	int32_t right;
5166	int32_t bottom;
5167
5168	/* Right order. */
5169	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5170	if (pRect->left < pRect->right)
5171	{
5172	left = pRect->left;
5173	right = pRect->right;
5174	}
5175	else
5176	{
5177	left = pRect->right;
5178	right = pRect->left;
5179	}
5180	if (pRect->top < pRect->bottom)
5181	{
5182	top = pRect->top;
5183	bottom = pRect->bottom;
5184	}
5185	else
5186	{
5187	top = pRect->bottom;
5188	bottom = pRect->top;
5189	}
5190
5191	if (left < pBound->left)
5192	left = pBound->left;
5193	if (right < pBound->left)
5194	right = pBound->left;
5195
5196	if (left > pBound->right)
5197	left = pBound->right;
5198	if (right > pBound->right)
5199	right = pBound->right;
5200
5201	if (top < pBound->top)
5202	top = pBound->top;
5203	if (bottom < pBound->top)
5204	bottom = pBound->top;
5205
5206	if (top > pBound->bottom)
5207	top = pBound->bottom;
5208	if (bottom > pBound->bottom)
5209	bottom = pBound->bottom;
5210
5211	pRect->left = left;
5212	pRect->right = right;
5213	pRect->top = top;
5214	pRect->bottom = bottom;
5215	}
5216
5217	/**
5218	* Unblock the FIFO I/O thread so it can respond to a state change.
5219	*
5220	* @returns VBox status code.
5221	* @param pDevIns The VGA device instance.
5222	* @param pThread The send thread.
5223	*/
5224	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5225	{
5226	RT_NOREF(pDevIns);
5227	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5228	Log(("vmsvgaFIFOLoopWakeUp\n"));
5229	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5230	}
5231
5232	/**
5233	* Enables or disables dirty page tracking for the framebuffer
5234	*
5235	* @param pThis VGA device instance data.
5236	* @param fTraces Enable/disable traces
5237	*/
5238	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5239	{
5240	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5241	&& !fTraces)
5242	{
5243	//Assert(pThis->svga.fTraces);
5244	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5245	return;
5246	}
5247
5248	pThis->svga.fTraces = fTraces;
5249	if (pThis->svga.fTraces)
5250	{
5251	unsigned cbFrameBuffer = pThis->vram_size;
5252
5253	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5254	/** @todo How does this work with screens? */
5255	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5256	{
5257	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5258	Assert(pThis->svga.cbScanline);
5259	#endif
5260	/* Hardware enabled; return real framebuffer size .*/
5261	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5262	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5263	}
5264
5265	if (!pThis->svga.fVRAMTracking)
5266	{
5267	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5268	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5269	pThis->svga.fVRAMTracking = true;
5270	}
5271	}
5272	else
5273	{
5274	if (pThis->svga.fVRAMTracking)
5275	{
5276	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5277	vgaR3UnregisterVRAMHandler(pThis);
5278	pThis->svga.fVRAMTracking = false;
5279	}
5280	}
5281	}
5282
5283	/**
5284	* @callback_method_impl{FNPCIIOREGIONMAP}
5285	*/
5286	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5287	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5288	{
5289	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5290	int rc;
5291	RT_NOREF(pPciDev);
5292	Assert(pPciDev == pDevIns->apPciDevs[0]);
5293
5294	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5295	if (enmType == PCI_ADDRESS_SPACE_IO)
5296	{
5297	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5298	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5299	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5300	if (RT_FAILURE(rc))
5301	return rc;
5302	if (pDevIns->fR0Enabled)
5303	{
5304	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5305	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5306	if (RT_FAILURE(rc))
5307	return rc;
5308	}
5309	if (pDevIns->fRCEnabled)
5310	{
5311	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5312	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5313	if (RT_FAILURE(rc))
5314	return rc;
5315	}
5316
5317	pThis->svga.BasePort = GCPhysAddress;
5318	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5319	}
5320	else
5321	{
5322	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5323	if (GCPhysAddress != NIL_RTGCPHYS)
5324	{
5325	/*
5326	* Mapping the FIFO RAM.
5327	*/
5328	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5329	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5330	AssertRC(rc);
5331
5332	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5333	if (RT_SUCCESS(rc))
5334	{
5335	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5336	# ifdef DEBUG_FIFO_ACCESS
5337	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5338	# else
5339	GCPhysAddress + PAGE_SIZE - 1,
5340	# endif
5341	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5342	"VMSVGA FIFO");
5343	AssertRC(rc);
5344	}
5345	# endif
5346	if (RT_SUCCESS(rc))
5347	{
5348	pThis->svga.GCPhysFIFO = GCPhysAddress;
5349	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5350	}
5351	}
5352	else
5353	{
5354	Assert(pThis->svga.GCPhysFIFO);
5355	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5356	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5357	AssertRC(rc);
5358	# endif
5359	pThis->svga.GCPhysFIFO = 0;
5360	}
5361	}
5362	return VINF_SUCCESS;
5363	}
5364
5365	# ifdef VBOX_WITH_VMSVGA3D
5366
5367	/**
5368	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5369	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5370	*
5371	* @param pThis The VGA device instance data.
5372	* @param sid Either UINT32_MAX or the ID of a specific
5373	* surface. If UINT32_MAX is used, all surfaces
5374	* are processed.
5375	*/
5376	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5377	{
5378	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5379	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5380	}
5381
5382
5383	/**
5384	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5385	*/
5386	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5387	{
5388	/* There might be a specific surface ID at the start of the
5389	arguments, if not show all surfaces. */
5390	uint32_t sid = UINT32_MAX;
5391	if (pszArgs)
5392	pszArgs = RTStrStripL(pszArgs);
5393	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5394	sid = RTStrToUInt32(pszArgs);
5395
5396	/* Verbose or terse display, we default to verbose. */
5397	bool fVerbose = true;
5398	if (RTStrIStr(pszArgs, "terse"))
5399	fVerbose = false;
5400
5401	/* The size of the ascii art (x direction, y is 3/4 of x). */
5402	uint32_t cxAscii = 80;
5403	if (RTStrIStr(pszArgs, "gigantic"))
5404	cxAscii = 300;
5405	else if (RTStrIStr(pszArgs, "huge"))
5406	cxAscii = 180;
5407	else if (RTStrIStr(pszArgs, "big"))
5408	cxAscii = 132;
5409	else if (RTStrIStr(pszArgs, "normal"))
5410	cxAscii = 80;
5411	else if (RTStrIStr(pszArgs, "medium"))
5412	cxAscii = 64;
5413	else if (RTStrIStr(pszArgs, "small"))
5414	cxAscii = 48;
5415	else if (RTStrIStr(pszArgs, "tiny"))
5416	cxAscii = 24;
5417
5418	/* Y invert the image when producing the ASCII art. */
5419	bool fInvY = false;
5420	if (RTStrIStr(pszArgs, "invy"))
5421	fInvY = true;
5422
5423	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5424	}
5425
5426
5427	/**
5428	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5429	*/
5430	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5431	{
5432	/* pszArg = "sid[>dir]"
5433	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5434	*/
5435	char *pszBitmapPath = NULL;
5436	uint32_t sid = UINT32_MAX;
5437	if (pszArgs)
5438	pszArgs = RTStrStripL(pszArgs);
5439	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5440	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5441	if ( pszBitmapPath
5442	&& *pszBitmapPath == '>')
5443	++pszBitmapPath;
5444
5445	const bool fVerbose = true;
5446	const uint32_t cxAscii = 0; /* No ASCII */
5447	const bool fInvY = false; /* Do not invert. */
5448	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5449	}
5450
5451
5452	/**
5453	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5454	*/
5455	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5456	{
5457	/* There might be a specific surface ID at the start of the
5458	arguments, if not show all contexts. */
5459	uint32_t sid = UINT32_MAX;
5460	if (pszArgs)
5461	pszArgs = RTStrStripL(pszArgs);
5462	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5463	sid = RTStrToUInt32(pszArgs);
5464
5465	/* Verbose or terse display, we default to verbose. */
5466	bool fVerbose = true;
5467	if (RTStrIStr(pszArgs, "terse"))
5468	fVerbose = false;
5469
5470	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5471	}
5472
5473	# endif /* VBOX_WITH_VMSVGA3D */
5474
5475	/**
5476	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5477	*/
5478	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5479	{
5480	RT_NOREF(pszArgs);
5481	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5482	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5483	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5484
5485	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5486	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5487	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5488	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5489	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5490	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5491	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5492	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5493	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5494	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5495	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5496	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5497	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5498	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5499	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5500	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5501	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5502	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5503	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5504	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5505	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5506	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5507	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5508
5509	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5510	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5511	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5512	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5513
5514	# ifdef VBOX_WITH_VMSVGA3D
5515	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5516	# endif
5517	if (pThis->pDrv)
5518	{
5519	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5520	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5521	}
5522	}
5523
5524	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5525	*/
5526	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5527	{
5528	RT_NOREF(uPass);
5529
5530	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5531	int rc;
5532
5533	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5534	{
5535	uint32_t cScreens = 0;
5536	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5537	AssertRCReturn(rc, rc);
5538	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5539	("cScreens=%#x\n", cScreens),
5540	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5541
5542	for (uint32_t i = 0; i < cScreens; ++i)
5543	{
5544	VMSVGASCREENOBJECT screen;
5545	RT_ZERO(screen);
5546
5547	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5548	AssertLogRelRCReturn(rc, rc);
5549
5550	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5551	{
5552	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5553	*pScreen = screen;
5554	pScreen->fModified = true;
5555	}
5556	else
5557	{
5558	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5559	}
5560	}
5561	}
5562	else
5563	{
5564	/* Try to setup at least the first screen. */
5565	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5566	pScreen->fDefined = true;
5567	pScreen->fModified = true;
5568	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5569	pScreen->idScreen = 0;
5570	pScreen->xOrigin = 0;
5571	pScreen->yOrigin = 0;
5572	pScreen->offVRAM = pThis->svga.uScreenOffset;
5573	pScreen->cbPitch = pThis->svga.cbScanline;
5574	pScreen->cWidth = pThis->svga.uWidth;
5575	pScreen->cHeight = pThis->svga.uHeight;
5576	pScreen->cBpp = pThis->svga.uBpp;
5577	}
5578
5579	return VINF_SUCCESS;
5580	}
5581
5582	/**
5583	* @copydoc FNSSMDEVLOADEXEC
5584	*/
5585	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5586	{
5587	RT_NOREF(uPass);
5588	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5589	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5590	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5591	int rc;
5592
5593	/* Load our part of the VGAState */
5594	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5595	AssertRCReturn(rc, rc);
5596
5597	/* Load the VGA framebuffer. */
5598	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5599	uint32_t cbVgaFramebuffer = _32K;
5600	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5601	{
5602	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5603	AssertRCReturn(rc, rc);
5604	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5605	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5606	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5607	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5608	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5609	}
5610	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5611	AssertRCReturn(rc, rc);
5612	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5613	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5614	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5615	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5616
5617	/* Load the VMSVGA state. */
5618	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5619	AssertRCReturn(rc, rc);
5620
5621	/* Load the active cursor bitmaps. */
5622	if (pSVGAState->Cursor.fActive)
5623	{
5624	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5625	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5626
5627	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5628	AssertRCReturn(rc, rc);
5629	}
5630
5631	/* Load the GMR state. */
5632	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5633	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5634	{
5635	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5636	AssertRCReturn(rc, rc);
5637	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5638	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5639	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5640	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5641	}
5642
5643	if (pThis->svga.cGMR != cGMR)
5644	{
5645	/* Reallocate GMR array. */
5646	Assert(pSVGAState->paGMR != NULL);
5647	RTMemFree(pSVGAState->paGMR);
5648	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5649	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5650	pThis->svga.cGMR = cGMR;
5651	}
5652
5653	for (uint32_t i = 0; i < cGMR; ++i)
5654	{
5655	PGMR pGMR = &pSVGAState->paGMR[i];
5656
5657	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5658	AssertRCReturn(rc, rc);
5659
5660	if (pGMR->numDescriptors)
5661	{
5662	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5663	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5664	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5665
5666	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5667	{
5668	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5669	AssertRCReturn(rc, rc);
5670	}
5671	}
5672	}
5673
5674	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5675	vmsvga3dPowerOn(pThis);
5676	# endif
5677
5678	VMSVGA_STATE_LOAD LoadState;
5679	LoadState.pSSM = pSSM;
5680	LoadState.uVersion = uVersion;
5681	LoadState.uPass = uPass;
5682	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5683	AssertLogRelRCReturn(rc, rc);
5684
5685	return VINF_SUCCESS;
5686	}
5687
5688	/**
5689	* Reinit the video mode after the state has been loaded.
5690	*/
5691	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5692	{
5693	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5694	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5695
5696	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5697
5698	/* Set the active cursor. */
5699	if (pSVGAState->Cursor.fActive)
5700	{
5701	int rc;
5702
5703	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5704	true,
5705	true,
5706	pSVGAState->Cursor.xHotspot,
5707	pSVGAState->Cursor.yHotspot,
5708	pSVGAState->Cursor.width,
5709	pSVGAState->Cursor.height,
5710	pSVGAState->Cursor.pData);
5711	AssertRC(rc);
5712	}
5713	return VINF_SUCCESS;
5714	}
5715
5716	/**
5717	* Portion of SVGA state which must be saved in the FIFO thread.
5718	*/
5719	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5720	{
5721	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5722	int rc;
5723
5724	/* Save the screen objects. */
5725	/* Count defined screen object. */
5726	uint32_t cScreens = 0;
5727	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5728	{
5729	if (pSVGAState->aScreens[i].fDefined)
5730	++cScreens;
5731	}
5732
5733	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5734	AssertLogRelRCReturn(rc, rc);
5735
5736	for (uint32_t i = 0; i < cScreens; ++i)
5737	{
5738	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5739
5740	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5741	AssertLogRelRCReturn(rc, rc);
5742	}
5743	return VINF_SUCCESS;
5744	}
5745
5746	/**
5747	* @copydoc FNSSMDEVSAVEEXEC
5748	*/
5749	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5750	{
5751	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5752	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5753	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5754	int rc;
5755
5756	/* Save our part of the VGAState */
5757	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5758	AssertLogRelRCReturn(rc, rc);
5759
5760	/* Save the framebuffer backup. */
5761	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5762	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5763	AssertLogRelRCReturn(rc, rc);
5764
5765	/* Save the VMSVGA state. */
5766	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5767	AssertLogRelRCReturn(rc, rc);
5768
5769	/* Save the active cursor bitmaps. */
5770	if (pSVGAState->Cursor.fActive)
5771	{
5772	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5773	AssertLogRelRCReturn(rc, rc);
5774	}
5775
5776	/* Save the GMR state */
5777	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5778	AssertLogRelRCReturn(rc, rc);
5779	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5780	{
5781	PGMR pGMR = &pSVGAState->paGMR[i];
5782
5783	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5784	AssertLogRelRCReturn(rc, rc);
5785
5786	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5787	{
5788	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5789	AssertLogRelRCReturn(rc, rc);
5790	}
5791	}
5792
5793	/*
5794	* Must save some state (3D in particular) in the FIFO thread.
5795	*/
5796	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5797	AssertLogRelRCReturn(rc, rc);
5798
5799	return VINF_SUCCESS;
5800	}
5801
5802	/**
5803	* Destructor for PVMSVGAR3STATE structure.
5804	*
5805	* @param pThis The VGA instance.
5806	* @param pSVGAState Pointer to the structure. It is not deallocated.
5807	*/
5808	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5809	{
5810	#ifndef VMSVGA_USE_EMT_HALT_CODE
5811	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5812	{
5813	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5814	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5815	}
5816	#endif
5817
5818	if (pSVGAState->Cursor.fActive)
5819	{
5820	RTMemFree(pSVGAState->Cursor.pData);
5821	pSVGAState->Cursor.pData = NULL;
5822	pSVGAState->Cursor.fActive = false;
5823	}
5824
5825	if (pSVGAState->paGMR)
5826	{
5827	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5828	if (pSVGAState->paGMR[i].paDesc)
5829	RTMemFree(pSVGAState->paGMR[i].paDesc);
5830
5831	RTMemFree(pSVGAState->paGMR);
5832	pSVGAState->paGMR = NULL;
5833	}
5834	}
5835
5836	/**
5837	* Constructor for PVMSVGAR3STATE structure.
5838	*
5839	* @returns VBox status code.
5840	* @param pThis The VGA instance.
5841	* @param pSVGAState Pointer to the structure. It is already allocated.
5842	*/
5843	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5844	{
5845	int rc = VINF_SUCCESS;
5846	RT_ZERO(*pSVGAState);
5847
5848	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5849	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5850
5851	#ifndef VMSVGA_USE_EMT_HALT_CODE
5852	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5853	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5854	AssertRCReturn(rc, rc);
5855	#endif
5856
5857	return rc;
5858	}
5859
5860	/**
5861	* Initializes the host capabilities: registers and FIFO.
5862	*
5863	* @returns VBox status code.
5864	* @param pThis The VGA instance.
5865	*/
5866	static void vmsvgaInitCaps(PVGASTATE pThis)
5867	{
5868	/* Register caps. */
5869	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5870	\| SVGA_CAP_GMR2
5871	\| SVGA_CAP_CURSOR
5872	\| SVGA_CAP_CURSOR_BYPASS_2
5873	\| SVGA_CAP_EXTENDED_FIFO
5874	\| SVGA_CAP_IRQMASK
5875	\| SVGA_CAP_PITCHLOCK
5876	\| SVGA_CAP_TRACES
5877	\| SVGA_CAP_SCREEN_OBJECT_2
5878	\| SVGA_CAP_ALPHA_CURSOR;
5879	# ifdef VBOX_WITH_VMSVGA3D
5880	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5881	# endif
5882
5883	/* Clear the FIFO. */
5884	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5885
5886	/* Setup FIFO capabilities. */
5887	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5888	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5889	\| SVGA_FIFO_CAP_GMR2
5890	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5891	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5892	\| SVGA_FIFO_CAP_RESERVE
5893	\| SVGA_FIFO_CAP_PITCHLOCK;
5894
5895	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5896	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5897	}
5898
5899	# ifdef VBOX_WITH_VMSVGA3D
5900	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5901	static const char * const g_apszVmSvgaDevCapNames[] =
5902	{
5903	"x3D", /* = 0 */
5904	"xMAX_LIGHTS",
5905	"xMAX_TEXTURES",
5906	"xMAX_CLIP_PLANES",
5907	"xVERTEX_SHADER_VERSION",
5908	"xVERTEX_SHADER",
5909	"xFRAGMENT_SHADER_VERSION",
5910	"xFRAGMENT_SHADER",
5911	"xMAX_RENDER_TARGETS",
5912	"xS23E8_TEXTURES",
5913	"xS10E5_TEXTURES",
5914	"xMAX_FIXED_VERTEXBLEND",
5915	"xD16_BUFFER_FORMAT",
5916	"xD24S8_BUFFER_FORMAT",
5917	"xD24X8_BUFFER_FORMAT",
5918	"xQUERY_TYPES",
5919	"xTEXTURE_GRADIENT_SAMPLING",
5920	"rMAX_POINT_SIZE",
5921	"xMAX_SHADER_TEXTURES",
5922	"xMAX_TEXTURE_WIDTH",
5923	"xMAX_TEXTURE_HEIGHT",
5924	"xMAX_VOLUME_EXTENT",
5925	"xMAX_TEXTURE_REPEAT",
5926	"xMAX_TEXTURE_ASPECT_RATIO",
5927	"xMAX_TEXTURE_ANISOTROPY",
5928	"xMAX_PRIMITIVE_COUNT",
5929	"xMAX_VERTEX_INDEX",
5930	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5931	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5932	"xMAX_VERTEX_SHADER_TEMPS",
5933	"xMAX_FRAGMENT_SHADER_TEMPS",
5934	"xTEXTURE_OPS",
5935	"xSURFACEFMT_X8R8G8B8",
5936	"xSURFACEFMT_A8R8G8B8",
5937	"xSURFACEFMT_A2R10G10B10",
5938	"xSURFACEFMT_X1R5G5B5",
5939	"xSURFACEFMT_A1R5G5B5",
5940	"xSURFACEFMT_A4R4G4B4",
5941	"xSURFACEFMT_R5G6B5",
5942	"xSURFACEFMT_LUMINANCE16",
5943	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5944	"xSURFACEFMT_ALPHA8",
5945	"xSURFACEFMT_LUMINANCE8",
5946	"xSURFACEFMT_Z_D16",
5947	"xSURFACEFMT_Z_D24S8",
5948	"xSURFACEFMT_Z_D24X8",
5949	"xSURFACEFMT_DXT1",
5950	"xSURFACEFMT_DXT2",
5951	"xSURFACEFMT_DXT3",
5952	"xSURFACEFMT_DXT4",
5953	"xSURFACEFMT_DXT5",
5954	"xSURFACEFMT_BUMPX8L8V8U8",
5955	"xSURFACEFMT_A2W10V10U10",
5956	"xSURFACEFMT_BUMPU8V8",
5957	"xSURFACEFMT_Q8W8V8U8",
5958	"xSURFACEFMT_CxV8U8",
5959	"xSURFACEFMT_R_S10E5",
5960	"xSURFACEFMT_R_S23E8",
5961	"xSURFACEFMT_RG_S10E5",
5962	"xSURFACEFMT_RG_S23E8",
5963	"xSURFACEFMT_ARGB_S10E5",
5964	"xSURFACEFMT_ARGB_S23E8",
5965	"xMISSING62",
5966	"xMAX_VERTEX_SHADER_TEXTURES",
5967	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5968	"xSURFACEFMT_V16U16",
5969	"xSURFACEFMT_G16R16",
5970	"xSURFACEFMT_A16B16G16R16",
5971	"xSURFACEFMT_UYVY",
5972	"xSURFACEFMT_YUY2",
5973	"xMULTISAMPLE_NONMASKABLESAMPLES",
5974	"xMULTISAMPLE_MASKABLESAMPLES",
5975	"xALPHATOCOVERAGE",
5976	"xSUPERSAMPLE",
5977	"xAUTOGENMIPMAPS",
5978	"xSURFACEFMT_NV12",
5979	"xSURFACEFMT_AYUV",
5980	"xMAX_CONTEXT_IDS",
5981	"xMAX_SURFACE_IDS",
5982	"xSURFACEFMT_Z_DF16",
5983	"xSURFACEFMT_Z_DF24",
5984	"xSURFACEFMT_Z_D24S8_INT",
5985	"xSURFACEFMT_BC4_UNORM",
5986	"xSURFACEFMT_BC5_UNORM", /* 83 */
5987	};
5988
5989	/**
5990	* Initializes the host 3D capabilities in FIFO.
5991	*
5992	* @returns VBox status code.
5993	* @param pThis The VGA instance.
5994	*/
5995	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5996	{
5997	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5998	bool fSavedBuffering = RTLogRelSetBuffering(true);
5999	SVGA3dCapsRecord *pCaps;
6000	SVGA3dCapPair *pData;
6001	uint32_t idxCap = 0;
6002
6003	/* 3d hardware version; latest and greatest */
6004	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6005	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6006
6007	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6008	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6009	pData = (SVGA3dCapPair *)&pCaps->data;
6010
6011	/* Fill out all 3d capabilities. */
6012	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6013	{
6014	uint32_t val = 0;
6015
6016	int rc = vmsvga3dQueryCaps(pThis, i, &val);
6017	if (RT_SUCCESS(rc))
6018	{
6019	pData[idxCap][0] = i;
6020	pData[idxCap][1] = val;
6021	idxCap++;
6022	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6023	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6024	else
6025	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6026	&g_apszVmSvgaDevCapNames[i][1]));
6027	}
6028	else
6029	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6030	}
6031	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6032	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6033
6034	/* Mark end of record array. */
6035	pCaps->header.length = 0;
6036
6037	RTLogRelSetBuffering(fSavedBuffering);
6038	}
6039
6040	# endif
6041
6042	/**
6043	* Resets the SVGA hardware state
6044	*
6045	* @returns VBox status code.
6046	* @param pDevIns The device instance.
6047	*/
6048	int vmsvgaReset(PPDMDEVINS pDevIns)
6049	{
6050	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6051	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6052
6053	/* Reset before init? */
6054	if (!pSVGAState)
6055	return VINF_SUCCESS;
6056
6057	Log(("vmsvgaReset\n"));
6058
6059	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6060	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6061	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6062
6063	/* Reset other stuff. */
6064	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6065	RT_ZERO(pThis->svga.au32ScratchRegion);
6066
6067	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6068	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6069
6070	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6071
6072	/* Initialize FIFO and register capabilities. */
6073	vmsvgaInitCaps(pThis);
6074
6075	# ifdef VBOX_WITH_VMSVGA3D
6076	if (pThis->svga.f3DEnabled)
6077	vmsvgaInitFifo3DCaps(pThis);
6078	# endif
6079
6080	/* VRAM tracking is enabled by default during bootup. */
6081	pThis->svga.fVRAMTracking = true;
6082	pThis->svga.fEnabled = false;
6083
6084	/* Invalidate current settings. */
6085	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6086	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6087	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6088	pThis->svga.cbScanline = 0;
6089	pThis->svga.u32PitchLock = 0;
6090
6091	return rc;
6092	}
6093
6094	/**
6095	* Cleans up the SVGA hardware state
6096	*
6097	* @returns VBox status code.
6098	* @param pDevIns The device instance.
6099	*/
6100	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6101	{
6102	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6103
6104	/*
6105	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6106	*/
6107	if (pThis->svga.pFIFOIOThread)
6108	{
6109	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6110	AssertLogRelRC(rc);
6111
6112	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
6113	AssertLogRelRC(rc);
6114	pThis->svga.pFIFOIOThread = NULL;
6115	}
6116
6117	/*
6118	* Destroy the special SVGA state.
6119	*/
6120	if (pThis->svga.pSvgaR3State)
6121	{
6122	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6123
6124	RTMemFree(pThis->svga.pSvgaR3State);
6125	pThis->svga.pSvgaR3State = NULL;
6126	}
6127
6128	/*
6129	* Free our resources residing in the VGA state.
6130	*/
6131	if (pThis->svga.pbVgaFrameBufferR3)
6132	{
6133	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6134	pThis->svga.pbVgaFrameBufferR3 = NULL;
6135	}
6136	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6137	{
6138	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6139	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6140	}
6141	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6142	{
6143	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6144	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6145	}
6146
6147	return VINF_SUCCESS;
6148	}
6149
6150	/**
6151	* Initialize the SVGA hardware state
6152	*
6153	* @returns VBox status code.
6154	* @param pDevIns The device instance.
6155	*/
6156	int vmsvgaInit(PPDMDEVINS pDevIns)
6157	{
6158	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6159	PVMSVGAR3STATE pSVGAState;
6160	PVM pVM = PDMDevHlpGetVM(pDevIns);
6161	int rc;
6162
6163	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6164	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6165
6166	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6167
6168	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6169	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6170	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6171
6172	/* Create event semaphore. */
6173	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6174
6175	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6176	if (RT_FAILURE(rc))
6177	{
6178	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6179	return rc;
6180	}
6181
6182	/* Create event semaphore. */
6183	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6184	if (RT_FAILURE(rc))
6185	{
6186	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6187	return rc;
6188	}
6189
6190	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6191	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6192
6193	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6194	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6195
6196	pSVGAState = pThis->svga.pSvgaR3State;
6197
6198	/* Initialize FIFO and register capabilities. */
6199	vmsvgaInitCaps(pThis);
6200
6201	# ifdef VBOX_WITH_VMSVGA3D
6202	if (pThis->svga.f3DEnabled)
6203	{
6204	rc = vmsvga3dInit(pThis);
6205	if (RT_FAILURE(rc))
6206	{
6207	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6208	pThis->svga.f3DEnabled = false;
6209	}
6210	}
6211	# endif
6212	/* VRAM tracking is enabled by default during bootup. */
6213	pThis->svga.fVRAMTracking = true;
6214
6215	/* Invalidate current settings. */
6216	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6217	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6218	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6219	pThis->svga.cbScanline = 0;
6220
6221	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6222	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6223	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6224	{
6225	pThis->svga.u32MaxWidth -= 256;
6226	pThis->svga.u32MaxHeight -= 256;
6227	}
6228	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6229
6230	# ifdef DEBUG_GMR_ACCESS
6231	/* Register the GMR access handler type. */
6232	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6233	vmsvgaR3GMRAccessHandler,
6234	NULL, NULL, NULL,
6235	NULL, NULL, NULL,
6236	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6237	AssertRCReturn(rc, rc);
6238	# endif
6239
6240	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6241	/* Register the FIFO access handler type. In addition to
6242	debugging FIFO access, this is also used to facilitate
6243	extended fifo thread sleeps. */
6244	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6245	# ifdef DEBUG_FIFO_ACCESS
6246	PGMPHYSHANDLERKIND_ALL,
6247	# else
6248	PGMPHYSHANDLERKIND_WRITE,
6249	# endif
6250	vmsvgaR3FIFOAccessHandler,
6251	NULL, NULL, NULL,
6252	NULL, NULL, NULL,
6253	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6254	AssertRCReturn(rc, rc);
6255	# endif
6256
6257	/* Create the async IO thread. */
6258	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6259	RTTHREADTYPE_IO, "VMSVGA FIFO");
6260	if (RT_FAILURE(rc))
6261	{
6262	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6263	return rc;
6264	}
6265
6266	/*
6267	* Statistics.
6268	*/
6269	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6270	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6271	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6272	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6273	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6274	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6275	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6276	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6277	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6278	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6279	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6280	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6281	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6282	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6283	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6284	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6285	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6286	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6287	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6288	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6289	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6290	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6291	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6292	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6293	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6294	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6295	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6296	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6297	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6298	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6299	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6300	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6301	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6302	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6303	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6304	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6305	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6306	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6307	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6308	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6309	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6310	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6311	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6312	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6313	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6314	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6315	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6316	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6317	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6318	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6319	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6320	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6321	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6322	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6323	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6324	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6325
6326	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6327	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6328	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6329	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6330	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6331	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6332	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6333	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6334	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6335	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6336	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6337	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6338	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6339	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6340	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6341	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6342	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6343	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6344	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6345	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6346	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6347	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6348	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6349	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6350	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6351	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6352	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6353	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6354	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6355	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6356	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6357	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6358
6359	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6360	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6361	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6362	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6363	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6364	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6365	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6366	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6367	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6368	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6369	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6370	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6371	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6372	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6373	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6374	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6375	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6376	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6377	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6378	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6379	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6380	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6381	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6382	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6383	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6384	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6385	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6386	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6387	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6388	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6389	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6390	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6391	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6392	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6393	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6394	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6395	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6396	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6397	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6398	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6399	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6400	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6401	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6402	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6403	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6404	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6405	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6406	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6407	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6408
6409	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6410	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6411	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6412	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6413	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6414	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6415	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6416	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6417	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6418	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6419	# endif
6420	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6421	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6422	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6423	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6424	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6425
6426	/*
6427	* Info handlers.
6428	*/
6429	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6430	# ifdef VBOX_WITH_VMSVGA3D
6431	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6432	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6433	"VMSVGA 3d surface details. "
6434	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6435	vmsvgaR3Info3dSurface);
6436	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6437	"VMSVGA 3d surface details and bitmap: "
6438	"sid[>dir]",
6439	vmsvgaR3Info3dSurfaceBmp);
6440	# endif
6441
6442	return VINF_SUCCESS;
6443	}
6444
6445	/**
6446	* Power On notification.
6447	*
6448	* @returns VBox status code.
6449	* @param pDevIns The device instance data.
6450	*
6451	* @remarks Caller enters the device critical section.
6452	*/
6453	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6454	{
6455	# ifdef VBOX_WITH_VMSVGA3D
6456	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6457	if (pThis->svga.f3DEnabled)
6458	{
6459	int rc = vmsvga3dPowerOn(pThis);
6460
6461	if (RT_SUCCESS(rc))
6462	{
6463	/* Initialize FIFO 3D capabilities. */
6464	vmsvgaInitFifo3DCaps(pThis);
6465	}
6466	}
6467	# else /* !VBOX_WITH_VMSVGA3D */
6468	RT_NOREF(pDevIns);
6469	# endif /* !VBOX_WITH_VMSVGA3D */
6470	}
6471
6472	#endif /* IN_RING3 */
6473

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82050

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