DevVGA-SVGA.cpp@ 82084

Last change on this file since 82084 was 82083, checked in by vboxsync, 5 years ago
DevVGA: style nits. bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82083 2019-11-21 16:26:41Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pDevIns The device instance.
766	* @param pThis VMSVGA State
767	* @param pu32 Where to store the read value
768	*/
769	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
770	{
771	int rc = VINF_SUCCESS;
772	*pu32 = 0;
773
774	/* Rough index register validation. */
775	uint32_t idxReg = pThis->svga.u32IndexReg;
776	#if !defined(IN_RING3) && defined(VBOX_STRICT)
777	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
778	VINF_IOM_R3_IOPORT_READ);
779	#else
780	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
782	VINF_SUCCESS);
783	#endif
784	RT_UNTRUSTED_VALIDATED_FENCE();
785
786	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
787	if ( idxReg >= SVGA_REG_CAPABILITIES
788	&& pThis->svga.u32SVGAId == SVGA_ID_0)
789	{
790	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
791	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
792	}
793
794	switch (idxReg)
795	{
796	case SVGA_REG_ID:
797	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
798	*pu32 = pThis->svga.u32SVGAId;
799	break;
800
801	case SVGA_REG_ENABLE:
802	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
803	*pu32 = pThis->svga.fEnabled;
804	break;
805
806	case SVGA_REG_WIDTH:
807	{
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
809	if ( pThis->svga.fEnabled
810	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
811	*pu32 = pThis->svga.uWidth;
812	else
813	{
814	#ifndef IN_RING3
815	rc = VINF_IOM_R3_IOPORT_READ;
816	#else
817	*pu32 = pThis->pDrv->cx;
818	#endif
819	}
820	break;
821	}
822
823	case SVGA_REG_HEIGHT:
824	{
825	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
826	if ( pThis->svga.fEnabled
827	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
828	*pu32 = pThis->svga.uHeight;
829	else
830	{
831	#ifndef IN_RING3
832	rc = VINF_IOM_R3_IOPORT_READ;
833	#else
834	*pu32 = pThis->pDrv->cy;
835	#endif
836	}
837	break;
838	}
839
840	case SVGA_REG_MAX_WIDTH:
841	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
842	*pu32 = pThis->svga.u32MaxWidth;
843	break;
844
845	case SVGA_REG_MAX_HEIGHT:
846	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
847	*pu32 = pThis->svga.u32MaxHeight;
848	break;
849
850	case SVGA_REG_DEPTH:
851	/* This returns the color depth of the current mode. */
852	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
853	switch (pThis->svga.uBpp)
854	{
855	case 15:
856	case 16:
857	case 24:
858	*pu32 = pThis->svga.uBpp;
859	break;
860
861	default:
862	case 32:
863	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
864	break;
865	}
866	break;
867
868	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
869	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
870	if ( pThis->svga.fEnabled
871	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
872	*pu32 = pThis->svga.uBpp;
873	else
874	{
875	#ifndef IN_RING3
876	rc = VINF_IOM_R3_IOPORT_READ;
877	#else
878	*pu32 = pThis->pDrv->cBits;
879	#endif
880	}
881	break;
882
883	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
885	if ( pThis->svga.fEnabled
886	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
887	*pu32 = (pThis->svga.uBpp + 7) & ~7;
888	else
889	{
890	#ifndef IN_RING3
891	rc = VINF_IOM_R3_IOPORT_READ;
892	#else
893	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
894	#endif
895	}
896	break;
897
898	case SVGA_REG_PSEUDOCOLOR:
899	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
900	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
901	break;
902
903	case SVGA_REG_RED_MASK:
904	case SVGA_REG_GREEN_MASK:
905	case SVGA_REG_BLUE_MASK:
906	{
907	uint32_t uBpp;
908
909	if ( pThis->svga.fEnabled
910	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
911	{
912	uBpp = pThis->svga.uBpp;
913	}
914	else
915	{
916	#ifndef IN_RING3
917	rc = VINF_IOM_R3_IOPORT_READ;
918	break;
919	#else
920	uBpp = pThis->pDrv->cBits;
921	#endif
922	}
923	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
924	switch (uBpp)
925	{
926	case 8:
927	u32RedMask = 0x07;
928	u32GreenMask = 0x38;
929	u32BlueMask = 0xc0;
930	break;
931
932	case 15:
933	u32RedMask = 0x0000001f;
934	u32GreenMask = 0x000003e0;
935	u32BlueMask = 0x00007c00;
936	break;
937
938	case 16:
939	u32RedMask = 0x0000001f;
940	u32GreenMask = 0x000007e0;
941	u32BlueMask = 0x0000f800;
942	break;
943
944	case 24:
945	case 32:
946	default:
947	u32RedMask = 0x00ff0000;
948	u32GreenMask = 0x0000ff00;
949	u32BlueMask = 0x000000ff;
950	break;
951	}
952	switch (idxReg)
953	{
954	case SVGA_REG_RED_MASK:
955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
956	*pu32 = u32RedMask;
957	break;
958
959	case SVGA_REG_GREEN_MASK:
960	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
961	*pu32 = u32GreenMask;
962	break;
963
964	case SVGA_REG_BLUE_MASK:
965	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
966	*pu32 = u32BlueMask;
967	break;
968	}
969	break;
970	}
971
972	case SVGA_REG_BYTES_PER_LINE:
973	{
974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
975	if ( pThis->svga.fEnabled
976	&& pThis->svga.cbScanline)
977	*pu32 = pThis->svga.cbScanline;
978	else
979	{
980	#ifndef IN_RING3
981	rc = VINF_IOM_R3_IOPORT_READ;
982	#else
983	*pu32 = pThis->pDrv->cbScanline;
984	#endif
985	}
986	break;
987	}
988
989	case SVGA_REG_VRAM_SIZE: /* VRAM size */
990	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
991	*pu32 = pThis->vram_size;
992	break;
993
994	case SVGA_REG_FB_START: /* Frame buffer physical address. */
995	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
996	Assert(pThis->GCPhysVRAM <= 0xffffffff);
997	*pu32 = pThis->GCPhysVRAM;
998	break;
999
1000	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1002	/* Always zero in our case. */
1003	*pu32 = 0;
1004	break;
1005
1006	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1007	{
1008	#ifndef IN_RING3
1009	rc = VINF_IOM_R3_IOPORT_READ;
1010	#else
1011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1012
1013	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1014	if ( pThis->svga.fEnabled
1015	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1016	{
1017	/* Hardware enabled; return real framebuffer size .*/
1018	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1019	}
1020	else
1021	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1022
1023	pu32 = RT_MIN(pThis->vram_size, pu32);
1024	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1025	#endif
1026	break;
1027	}
1028
1029	case SVGA_REG_CAPABILITIES:
1030	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1031	*pu32 = pThis->svga.u32RegCaps;
1032	break;
1033
1034	case SVGA_REG_MEM_START: /* FIFO start */
1035	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1036	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1037	*pu32 = pThis->svga.GCPhysFIFO;
1038	break;
1039
1040	case SVGA_REG_MEM_SIZE: /* FIFO size */
1041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1042	*pu32 = pThis->svga.cbFIFO;
1043	break;
1044
1045	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1047	*pu32 = pThis->svga.fConfigured;
1048	break;
1049
1050	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1052	*pu32 = 0;
1053	break;
1054
1055	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1057	if (pThis->svga.fBusy)
1058	{
1059	#ifndef IN_RING3
1060	/* Go to ring-3 and halt the CPU. */
1061	rc = VINF_IOM_R3_IOPORT_READ;
1062	RT_NOREF(pDevIns);
1063	break;
1064	#else
1065	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1066	/* The guest is basically doing a HLT via the device here, but with
1067	a special wake up condition on FIFO completion. */
1068	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1069	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1070	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1071	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1072	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1073	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1074	if (pThis->svga.fBusy)
1075	{
1076	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1077	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1078	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1079	}
1080	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1081	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1082	# else
1083
1084	/* Delay the EMT a bit so the FIFO and others can get some work done.
1085	This used to be a crude 50 ms sleep. The current code tries to be
1086	more efficient, but the consept is still very crude. */
1087	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1088	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1089	RTThreadYield();
1090	if (pThis->svga.fBusy)
1091	{
1092	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1093
1094	if (pThis->svga.fBusy && cRefs == 1)
1095	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1096	if (pThis->svga.fBusy)
1097	{
1098	/** @todo If this code is going to stay, we need to call into the halt/wait
1099	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1100	* suffer when the guest is polling on a busy FIFO. */
1101	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1102	if (cNsMaxWait >= RT_NS_100US)
1103	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1104	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1105	RT_MIN(cNsMaxWait, RT_NS_10MS));
1106	}
1107
1108	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1109	}
1110	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1111	# endif
1112	*pu32 = pThis->svga.fBusy != 0;
1113	#endif
1114	}
1115	else
1116	*pu32 = false;
1117	break;
1118
1119	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1120	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1121	*pu32 = pThis->svga.u32GuestId;
1122	break;
1123
1124	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1125	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1126	*pu32 = pThis->svga.cScratchRegion;
1127	break;
1128
1129	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1130	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1131	*pu32 = SVGA_FIFO_NUM_REGS;
1132	break;
1133
1134	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1136	*pu32 = pThis->svga.u32PitchLock;
1137	break;
1138
1139	case SVGA_REG_IRQMASK: /* Interrupt mask */
1140	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1141	*pu32 = pThis->svga.u32IrqMask;
1142	break;
1143
1144	/* See "Guest memory regions" below. */
1145	case SVGA_REG_GMR_ID:
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1147	*pu32 = pThis->svga.u32CurrentGMRId;
1148	break;
1149
1150	case SVGA_REG_GMR_DESCRIPTOR:
1151	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1152	/* Write only */
1153	*pu32 = 0;
1154	break;
1155
1156	case SVGA_REG_GMR_MAX_IDS:
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1158	*pu32 = pThis->svga.cGMR;
1159	break;
1160
1161	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1162	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1163	*pu32 = VMSVGA_MAX_GMR_PAGES;
1164	break;
1165
1166	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1168	*pu32 = pThis->svga.fTraces;
1169	break;
1170
1171	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1173	*pu32 = VMSVGA_MAX_GMR_PAGES;
1174	break;
1175
1176	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1178	*pu32 = VMSVGA_SURFACE_SIZE;
1179	break;
1180
1181	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1183	break;
1184
1185	/* Mouse cursor support. */
1186	case SVGA_REG_CURSOR_ID:
1187	case SVGA_REG_CURSOR_X:
1188	case SVGA_REG_CURSOR_Y:
1189	case SVGA_REG_CURSOR_ON:
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1191	break;
1192
1193	/* Legacy multi-monitor support */
1194	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1196	*pu32 = 1;
1197	break;
1198
1199	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1201	*pu32 = 0;
1202	break;
1203
1204	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1206	*pu32 = 0;
1207	break;
1208
1209	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1216	*pu32 = 0;
1217	break;
1218
1219	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1221	*pu32 = pThis->svga.uWidth;
1222	break;
1223
1224	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1226	*pu32 = pThis->svga.uHeight;
1227	break;
1228
1229	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1231	/* We must return something sensible here otherwise the Linux driver
1232	will take a legacy code path without 3d support. This number also
1233	limits how many screens Linux guests will allow. */
1234	*pu32 = pThis->cMonitors;
1235	break;
1236
1237	default:
1238	{
1239	uint32_t offReg;
1240	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1241	{
1242	RT_UNTRUSTED_VALIDATED_FENCE();
1243	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1244	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1245	}
1246	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1247	{
1248	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1249	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	uint32_t u32 = pThis->last_palette[offReg / 3];
1252	switch (offReg % 3)
1253	{
1254	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1255	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1256	case 2: pu32 = u32 & 0xff; break; / blue */
1257	}
1258	}
1259	else
1260	{
1261	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1262	rc = VINF_IOM_R3_IOPORT_READ;
1263	#else
1264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1265
1266	/* Do not assert. The guest might be reading all registers. */
1267	LogFunc(("Unknown reg=%#x\n", idxReg));
1268	#endif
1269	}
1270	break;
1271	}
1272	}
1273	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1274	return rc;
1275	}
1276
1277	#ifdef IN_RING3
1278	/**
1279	* Apply the current resolution settings to change the video mode.
1280	*
1281	* @returns VBox status code.
1282	* @param pThis VMSVGA State
1283	*/
1284	static int vmsvgaChangeMode(PVGASTATE pThis)
1285	{
1286	int rc;
1287
1288	/* Always do changemode on FIFO thread. */
1289	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1290
1291	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1292
1293	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1294
1295	if (pThis->svga.fGFBRegisters)
1296	{
1297	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1298	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1299	* deletes all screens other than screen #0, and redefines screen
1300	* #0 according to the specified mode. Drivers that use
1301	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1302	*/
1303
1304	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1305	pScreen->fDefined = true;
1306	pScreen->fModified = true;
1307	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1308	pScreen->idScreen = 0;
1309	pScreen->xOrigin = 0;
1310	pScreen->yOrigin = 0;
1311	pScreen->offVRAM = 0;
1312	pScreen->cbPitch = pThis->svga.cbScanline;
1313	pScreen->cWidth = pThis->svga.uWidth;
1314	pScreen->cHeight = pThis->svga.uHeight;
1315	pScreen->cBpp = pThis->svga.uBpp;
1316
1317	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1318	{
1319	/* Delete screen. */
1320	pScreen = &pSVGAState->aScreens[iScreen];
1321	if (pScreen->fDefined)
1322	{
1323	pScreen->fModified = true;
1324	pScreen->fDefined = false;
1325	}
1326	}
1327	}
1328	else
1329	{
1330	/* "If Screen Objects are supported, they can be used to fully
1331	* replace the functionality provided by the framebuffer registers
1332	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1333	*/
1334	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1335	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1336	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1337	}
1338
1339	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1340	{
1341	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1342	if (!pScreen->fModified)
1343	continue;
1344
1345	pScreen->fModified = false;
1346
1347	VBVAINFOVIEW view;
1348	RT_ZERO(view);
1349	view.u32ViewIndex = pScreen->idScreen;
1350	// view.u32ViewOffset = 0;
1351	view.u32ViewSize = pThis->vram_size;
1352	view.u32MaxScreenSize = pThis->vram_size;
1353
1354	VBVAINFOSCREEN screen;
1355	RT_ZERO(screen);
1356	screen.u32ViewIndex = pScreen->idScreen;
1357
1358	if (pScreen->fDefined)
1359	{
1360	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1361	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1362	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1363	{
1364	Assert(pThis->svga.fGFBRegisters);
1365	continue;
1366	}
1367
1368	screen.i32OriginX = pScreen->xOrigin;
1369	screen.i32OriginY = pScreen->yOrigin;
1370	screen.u32StartOffset = pScreen->offVRAM;
1371	screen.u32LineSize = pScreen->cbPitch;
1372	screen.u32Width = pScreen->cWidth;
1373	screen.u32Height = pScreen->cHeight;
1374	screen.u16BitsPerPixel = pScreen->cBpp;
1375	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1376	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1377	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1378	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1379	}
1380	else
1381	{
1382	/* Screen is destroyed. */
1383	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1384	}
1385
1386	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1387	AssertRC(rc);
1388	}
1389
1390	/* Last stuff. For the VGA device screenshot. */
1391	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1392	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1393	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1394	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1395	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1396
1397	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1398	if ( pThis->svga.viewport.cx == 0
1399	&& pThis->svga.viewport.cy == 0)
1400	{
1401	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1402	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1403	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1404	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1405	pThis->svga.viewport.yLowWC = 0;
1406	}
1407
1408	return VINF_SUCCESS;
1409	}
1410
1411	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1412	{
1413	VBVACMDHDR cmd;
1414	cmd.x = (int16_t)(pScreen->xOrigin + x);
1415	cmd.y = (int16_t)(pScreen->yOrigin + y);
1416	cmd.w = (uint16_t)w;
1417	cmd.h = (uint16_t)h;
1418
1419	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1420	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1421	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1422	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1423
1424	return VINF_SUCCESS;
1425	}
1426
1427	#endif /* IN_RING3 */
1428	#if defined(IN_RING0) \|\| defined(IN_RING3)
1429
1430	/**
1431	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1432	*
1433	* @param pThis The VMSVGA state.
1434	* @param fState The busy state.
1435	*/
1436	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1437	{
1438	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1439
1440	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1441	{
1442	/* Race / unfortunately scheduling. Highly unlikly. */
1443	uint32_t cLoops = 64;
1444	do
1445	{
1446	ASMNopPause();
1447	fState = (pThis->svga.fBusy != 0);
1448	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1449	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1450	}
1451	}
1452
1453
1454	/**
1455	* Update the scanline pitch in response to the guest changing mode
1456	* width/bpp.
1457	*
1458	* @param pThis VMSVGA State
1459	*/
1460	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1461	{
1462	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1463	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1464	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1465	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1466
1467	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1468	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1469	* location but it has a different meaning.
1470	*/
1471	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1472	uFifoPitchLock = 0;
1473
1474	/* Sanitize values. */
1475	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1476	uFifoPitchLock = 0;
1477	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1478	uRegPitchLock = 0;
1479
1480	/* Prefer the register value to the FIFO value.*/
1481	if (uRegPitchLock)
1482	pThis->svga.cbScanline = uRegPitchLock;
1483	else if (uFifoPitchLock)
1484	pThis->svga.cbScanline = uFifoPitchLock;
1485	else
1486	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1487
1488	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1489	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1490	}
1491
1492	#endif /* IN_RING0 \|\| IN_RING3 */
1493
1494
1495	/**
1496	* Write port register
1497	*
1498	* @returns Strict VBox status code.
1499	* @param pThis VMSVGA State
1500	* @param u32 Value to write
1501	*/
1502	static VBOXSTRICTRC vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1503	{
1504	#ifdef IN_RING3
1505	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1506	#endif
1507	VBOXSTRICTRC rc = VINF_SUCCESS;
1508
1509	/* Rough index register validation. */
1510	uint32_t idxReg = pThis->svga.u32IndexReg;
1511	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1512	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1513	VINF_IOM_R3_IOPORT_WRITE);
1514	#else
1515	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1516	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1517	VINF_SUCCESS);
1518	#endif
1519	RT_UNTRUSTED_VALIDATED_FENCE();
1520
1521	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1522	if ( idxReg >= SVGA_REG_CAPABILITIES
1523	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1524	{
1525	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1526	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1527	}
1528	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1529	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1530	switch (idxReg)
1531	{
1532	case SVGA_REG_WIDTH:
1533	case SVGA_REG_HEIGHT:
1534	case SVGA_REG_PITCHLOCK:
1535	case SVGA_REG_BITS_PER_PIXEL:
1536	pThis->svga.fGFBRegisters = true;
1537	break;
1538	default:
1539	break;
1540	}
1541
1542	switch (idxReg)
1543	{
1544	case SVGA_REG_ID:
1545	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1546	if ( u32 == SVGA_ID_0
1547	\|\| u32 == SVGA_ID_1
1548	\|\| u32 == SVGA_ID_2)
1549	pThis->svga.u32SVGAId = u32;
1550	else
1551	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1552	break;
1553
1554	case SVGA_REG_ENABLE:
1555	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1556	#ifdef IN_RING3
1557	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1558	&& pThis->svga.fEnabled == false)
1559	{
1560	/* Make a backup copy of the first 512kb in order to save font data etc. */
1561	/** @todo should probably swap here, rather than copy + zero */
1562	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1563	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1564	}
1565
1566	pThis->svga.fEnabled = u32;
1567	if (pThis->svga.fEnabled)
1568	{
1569	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1570	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1571	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1572	{
1573	/* Keep the current mode. */
1574	pThis->svga.uWidth = pThis->pDrv->cx;
1575	pThis->svga.uHeight = pThis->pDrv->cy;
1576	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1577	}
1578
1579	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1580	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1581	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1582	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1583	# ifdef LOG_ENABLED
1584	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1585	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1586	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1587	# endif
1588
1589	/* Disable or enable dirty page tracking according to the current fTraces value. */
1590	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1591
1592	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1593	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1594	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1595	}
1596	else
1597	{
1598	/* Restore the text mode backup. */
1599	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1600
1601	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1602
1603	/* Enable dirty page tracking again when going into legacy mode. */
1604	vmsvgaSetTraces(pThis, true);
1605
1606	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1607	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1608	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1609
1610	/* Clear the pitch lock. */
1611	pThis->svga.u32PitchLock = 0;
1612	}
1613	#else /* !IN_RING3 */
1614	rc = VINF_IOM_R3_IOPORT_WRITE;
1615	#endif /* !IN_RING3 */
1616	break;
1617
1618	case SVGA_REG_WIDTH:
1619	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1620	if (pThis->svga.uWidth != u32)
1621	{
1622	#if defined(IN_RING3) \|\| defined(IN_RING0)
1623	pThis->svga.uWidth = u32;
1624	vmsvgaUpdatePitch(pThis);
1625	if (pThis->svga.fEnabled)
1626	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1627	#else
1628	rc = VINF_IOM_R3_IOPORT_WRITE;
1629	#endif
1630	}
1631	/* else: nop */
1632	break;
1633
1634	case SVGA_REG_HEIGHT:
1635	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1636	if (pThis->svga.uHeight != u32)
1637	{
1638	pThis->svga.uHeight = u32;
1639	if (pThis->svga.fEnabled)
1640	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1641	}
1642	/* else: nop */
1643	break;
1644
1645	case SVGA_REG_DEPTH:
1646	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1647	/** @todo read-only?? */
1648	break;
1649
1650	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1651	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1652	if (pThis->svga.uBpp != u32)
1653	{
1654	#if defined(IN_RING3) \|\| defined(IN_RING0)
1655	pThis->svga.uBpp = u32;
1656	vmsvgaUpdatePitch(pThis);
1657	if (pThis->svga.fEnabled)
1658	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1659	#else
1660	rc = VINF_IOM_R3_IOPORT_WRITE;
1661	#endif
1662	}
1663	/* else: nop */
1664	break;
1665
1666	case SVGA_REG_PSEUDOCOLOR:
1667	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1668	break;
1669
1670	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1671	#ifdef IN_RING3
1672	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1673	pThis->svga.fConfigured = u32;
1674	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1675	if (!pThis->svga.fConfigured)
1676	pThis->svga.fTraces = true;
1677	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1678	#else
1679	rc = VINF_IOM_R3_IOPORT_WRITE;
1680	#endif
1681	break;
1682
1683	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1684	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1685	if ( pThis->svga.fEnabled
1686	&& pThis->svga.fConfigured)
1687	{
1688	#if defined(IN_RING3) \|\| defined(IN_RING0)
1689	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1690	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1691	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1692	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1693
1694	/* Kick the FIFO thread to start processing commands again. */
1695	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1696	#else
1697	rc = VINF_IOM_R3_IOPORT_WRITE;
1698	#endif
1699	}
1700	/* else nothing to do. */
1701	else
1702	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1703
1704	break;
1705
1706	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1707	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1708	break;
1709
1710	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1711	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1712	pThis->svga.u32GuestId = u32;
1713	break;
1714
1715	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1716	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1717	pThis->svga.u32PitchLock = u32;
1718	/* Should this also update the FIFO pitch lock? Unclear. */
1719	break;
1720
1721	case SVGA_REG_IRQMASK: /* Interrupt mask */
1722	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1723	pThis->svga.u32IrqMask = u32;
1724
1725	/* Irq pending after the above change? */
1726	if (pThis->svga.u32IrqStatus & u32)
1727	{
1728	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1729	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1730	}
1731	else
1732	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1733	break;
1734
1735	/* Mouse cursor support */
1736	case SVGA_REG_CURSOR_ID:
1737	case SVGA_REG_CURSOR_X:
1738	case SVGA_REG_CURSOR_Y:
1739	case SVGA_REG_CURSOR_ON:
1740	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1741	break;
1742
1743	/* Legacy multi-monitor support */
1744	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1745	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1746	break;
1747	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1748	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1749	break;
1750	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1751	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1752	break;
1753	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1754	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1755	break;
1756	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1757	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1758	break;
1759	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1760	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1761	break;
1762	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1763	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1764	break;
1765	#ifdef VBOX_WITH_VMSVGA3D
1766	/* See "Guest memory regions" below. */
1767	case SVGA_REG_GMR_ID:
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1769	pThis->svga.u32CurrentGMRId = u32;
1770	break;
1771
1772	case SVGA_REG_GMR_DESCRIPTOR:
1773	# ifndef IN_RING3
1774	rc = VINF_IOM_R3_IOPORT_WRITE;
1775	break;
1776	# else /* IN_RING3 */
1777	{
1778	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1779
1780	/* Validate current GMR id. */
1781	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1782	AssertBreak(idGMR < pThis->svga.cGMR);
1783	RT_UNTRUSTED_VALIDATED_FENCE();
1784
1785	/* Free the old GMR if present. */
1786	vmsvgaGMRFree(pThis, idGMR);
1787
1788	/* Just undefine the GMR? */
1789	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1790	if (GCPhys == 0)
1791	{
1792	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1793	break;
1794	}
1795
1796
1797	/* Never cross a page boundary automatically. */
1798	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1799	uint32_t cPagesTotal = 0;
1800	uint32_t iDesc = 0;
1801	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1802	uint32_t cLoops = 0;
1803	RTGCPHYS GCPhysBase = GCPhys;
1804	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1805	{
1806	/* Read descriptor. */
1807	SVGAGuestMemDescriptor desc;
1808	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1809	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1810
1811	if (desc.numPages != 0)
1812	{
1813	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1814	cPagesTotal += desc.numPages;
1815	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1816
1817	if ((iDesc & 15) == 0)
1818	{
1819	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1820	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1821	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1822	}
1823
1824	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1825	paDescs[iDesc++].numPages = desc.numPages;
1826
1827	/* Continue with the next descriptor. */
1828	GCPhys += sizeof(desc);
1829	}
1830	else if (desc.ppn == 0)
1831	break; /* terminator */
1832	else /* Pointer to the next physical page of descriptors. */
1833	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1834
1835	cLoops++;
1836	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1837	}
1838
1839	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1840	if (RT_SUCCESS(rc))
1841	{
1842	/* Commit the GMR. */
1843	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1844	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1845	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1846	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1847	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1848	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1849	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1850	}
1851	else
1852	{
1853	RTMemFree(paDescs);
1854	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1855	}
1856	break;
1857	}
1858	# endif /* IN_RING3 */
1859	#endif // VBOX_WITH_VMSVGA3D
1860
1861	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1862	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1863	if (pThis->svga.fTraces == u32)
1864	break; /* nothing to do */
1865
1866	#ifdef IN_RING3
1867	vmsvgaSetTraces(pThis, !!u32);
1868	#else
1869	rc = VINF_IOM_R3_IOPORT_WRITE;
1870	#endif
1871	break;
1872
1873	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1874	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1875	break;
1876
1877	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1878	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1879	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1880	break;
1881
1882	case SVGA_REG_FB_START:
1883	case SVGA_REG_MEM_START:
1884	case SVGA_REG_HOST_BITS_PER_PIXEL:
1885	case SVGA_REG_MAX_WIDTH:
1886	case SVGA_REG_MAX_HEIGHT:
1887	case SVGA_REG_VRAM_SIZE:
1888	case SVGA_REG_FB_SIZE:
1889	case SVGA_REG_CAPABILITIES:
1890	case SVGA_REG_MEM_SIZE:
1891	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1892	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1893	case SVGA_REG_BYTES_PER_LINE:
1894	case SVGA_REG_FB_OFFSET:
1895	case SVGA_REG_RED_MASK:
1896	case SVGA_REG_GREEN_MASK:
1897	case SVGA_REG_BLUE_MASK:
1898	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1899	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1900	case SVGA_REG_GMR_MAX_IDS:
1901	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1902	/* Read only - ignore. */
1903	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1904	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1905	break;
1906
1907	default:
1908	{
1909	uint32_t offReg;
1910	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1911	{
1912	RT_UNTRUSTED_VALIDATED_FENCE();
1913	pThis->svga.au32ScratchRegion[offReg] = u32;
1914	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1915	}
1916	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1917	{
1918	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1919	Btw, see rgb_to_pixel32. */
1920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1921	u32 &= 0xff;
1922	RT_UNTRUSTED_VALIDATED_FENCE();
1923	uint32_t uRgb = pThis->last_palette[offReg / 3];
1924	switch (offReg % 3)
1925	{
1926	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1927	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1928	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1929	}
1930	pThis->last_palette[offReg / 3] = uRgb;
1931	}
1932	else
1933	{
1934	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1935	rc = VINF_IOM_R3_IOPORT_WRITE;
1936	#else
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1938	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1939	#endif
1940	}
1941	break;
1942	}
1943	}
1944	return rc;
1945	}
1946
1947	/**
1948	* @callback_method_impl{FNIOMIOPORTNEWIN}
1949	*/
1950	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1951	{
1952	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1953	RT_NOREF_PV(pvUser);
1954
1955	/* Only dword accesses. */
1956	if (cb == 4)
1957	{
1958	switch (offPort)
1959	{
1960	case SVGA_INDEX_PORT:
1961	*pu32 = pThis->svga.u32IndexReg;
1962	break;
1963
1964	case SVGA_VALUE_PORT:
1965	return vmsvgaReadPort(pDevIns, pThis, pu32);
1966
1967	case SVGA_BIOS_PORT:
1968	Log(("Ignoring BIOS port read\n"));
1969	*pu32 = 0;
1970	break;
1971
1972	case SVGA_IRQSTATUS_PORT:
1973	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1974	*pu32 = pThis->svga.u32IrqStatus;
1975	break;
1976
1977	default:
1978	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1979	*pu32 = UINT32_MAX;
1980	break;
1981	}
1982	}
1983	else
1984	{
1985	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
1986	*pu32 = UINT32_MAX;
1987	}
1988	return VINF_SUCCESS;
1989	}
1990
1991	/**
1992	* @callback_method_impl{FNIOMIOPORTNEWOUT}
1993	*/
1994	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1995	{
1996	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1997	RT_NOREF_PV(pvUser);
1998
1999	/* Only dword accesses. */
2000	if (cb == 4)
2001	switch (offPort)
2002	{
2003	case SVGA_INDEX_PORT:
2004	pThis->svga.u32IndexReg = u32;
2005	break;
2006
2007	case SVGA_VALUE_PORT:
2008	return vmsvgaWritePort(pThis, u32);
2009
2010	case SVGA_BIOS_PORT:
2011	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2012	break;
2013
2014	case SVGA_IRQSTATUS_PORT:
2015	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2016	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2017	/* Clear the irq in case all events have been cleared. */
2018	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2019	{
2020	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2021	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2022	}
2023	break;
2024
2025	default:
2026	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2027	break;
2028	}
2029	else
2030	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2031
2032	return VINF_SUCCESS;
2033	}
2034
2035	#ifdef IN_RING3
2036
2037	# ifdef DEBUG_FIFO_ACCESS
2038	/**
2039	* Handle FIFO memory access.
2040	* @returns VBox status code.
2041	* @param pVM VM handle.
2042	* @param pThis VGA device instance data.
2043	* @param GCPhys The access physical address.
2044	* @param fWriteAccess Read or write access
2045	*/
2046	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2047	{
2048	RT_NOREF(pVM);
2049	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2050	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2051
2052	switch (GCPhysOffset >> 2)
2053	{
2054	case SVGA_FIFO_MIN:
2055	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2056	break;
2057	case SVGA_FIFO_MAX:
2058	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2059	break;
2060	case SVGA_FIFO_NEXT_CMD:
2061	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2062	break;
2063	case SVGA_FIFO_STOP:
2064	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2065	break;
2066	case SVGA_FIFO_CAPABILITIES:
2067	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2068	break;
2069	case SVGA_FIFO_FLAGS:
2070	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2071	break;
2072	case SVGA_FIFO_FENCE:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_3D_HWVERSION:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_PITCHLOCK:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_CURSOR_ON:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_CURSOR_X:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_CURSOR_Y:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_CURSOR_COUNT:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_RESERVED:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_CURSOR_SCREEN_ID:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_DEAD:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_3D_HWVERSION_REVISED:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS_LAST:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_GUEST_3D_HWVERSION:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_FENCE_GOAL:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_BUSY:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	default:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	}
2373
2374	return VINF_EM_RAW_EMULATE_INSTR;
2375	}
2376	# endif /* DEBUG_FIFO_ACCESS */
2377
2378	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2379	/**
2380	* HC access handler for the FIFO.
2381	*
2382	* @returns VINF_SUCCESS if the handler have carried out the operation.
2383	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2384	* @param pVM VM Handle.
2385	* @param pVCpu The cross context CPU structure for the calling EMT.
2386	* @param GCPhys The physical address the guest is writing to.
2387	* @param pvPhys The HC mapping of that address.
2388	* @param pvBuf What the guest is reading/writing.
2389	* @param cbBuf How much it's reading/writing.
2390	* @param enmAccessType The access type.
2391	* @param enmOrigin Who is making the access.
2392	* @param pvUser User argument.
2393	*/
2394	static DECLCALLBACK(VBOXSTRICTRC)
2395	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2396	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2397	{
2398	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2399	PVGASTATE pThis = (PVGASTATE)pvUser;
2400	AssertPtr(pThis);
2401
2402	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2403	/*
2404	* Wake up the FIFO thread as it might have work to do now.
2405	*/
2406	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2407	AssertLogRelRC(rc);
2408	# endif
2409
2410	# ifdef DEBUG_FIFO_ACCESS
2411	/*
2412	* When in debug-fifo-access mode, we do not disable the access handler,
2413	* but leave it on as we wish to catch all access.
2414	*/
2415	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2416	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2417	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2418	/*
2419	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2420	*/
2421	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2422	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2423	# endif
2424	if (RT_SUCCESS(rc))
2425	return VINF_PGM_HANDLER_DO_DEFAULT;
2426	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2427	return rc;
2428	}
2429	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2430
2431	#endif /* IN_RING3 */
2432
2433	#ifdef DEBUG_GMR_ACCESS
2434	# ifdef IN_RING3
2435
2436	/**
2437	* HC access handler for the FIFO.
2438	*
2439	* @returns VINF_SUCCESS if the handler have carried out the operation.
2440	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2441	* @param pVM VM Handle.
2442	* @param pVCpu The cross context CPU structure for the calling EMT.
2443	* @param GCPhys The physical address the guest is writing to.
2444	* @param pvPhys The HC mapping of that address.
2445	* @param pvBuf What the guest is reading/writing.
2446	* @param cbBuf How much it's reading/writing.
2447	* @param enmAccessType The access type.
2448	* @param enmOrigin Who is making the access.
2449	* @param pvUser User argument.
2450	*/
2451	static DECLCALLBACK(VBOXSTRICTRC)
2452	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2453	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2454	{
2455	PVGASTATE pThis = (PVGASTATE)pvUser;
2456	Assert(pThis);
2457	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2458	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2459
2460	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2461
2462	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2463	{
2464	PGMR pGMR = &pSVGAState->paGMR[i];
2465
2466	if (pGMR->numDescriptors)
2467	{
2468	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2469	{
2470	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2471	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2472	{
2473	/*
2474	* Turn off the write handler for this particular page and make it R/W.
2475	* Then return telling the caller to restart the guest instruction.
2476	*/
2477	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2478	AssertRC(rc);
2479	goto end;
2480	}
2481	}
2482	}
2483	}
2484	end:
2485	return VINF_PGM_HANDLER_DO_DEFAULT;
2486	}
2487
2488	/* Callback handler for VMR3ReqCallWaitU */
2489	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2490	{
2491	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2492	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2493	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2494	int rc;
2495
2496	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2497	{
2498	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2499	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2500	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2501	AssertRC(rc);
2502	}
2503	return VINF_SUCCESS;
2504	}
2505
2506	/* Callback handler for VMR3ReqCallWaitU */
2507	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2508	{
2509	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2510	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2511	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2512
2513	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2514	{
2515	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2516	AssertRC(rc);
2517	}
2518	return VINF_SUCCESS;
2519	}
2520
2521	/* Callback handler for VMR3ReqCallWaitU */
2522	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2523	{
2524	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2525
2526	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2527	{
2528	PGMR pGMR = &pSVGAState->paGMR[i];
2529
2530	if (pGMR->numDescriptors)
2531	{
2532	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2533	{
2534	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2535	AssertRC(rc);
2536	}
2537	}
2538	}
2539	return VINF_SUCCESS;
2540	}
2541
2542	# endif /* IN_RING3 */
2543	#endif /* DEBUG_GMR_ACCESS */
2544
2545	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2546
2547	#ifdef IN_RING3
2548
2549
2550	/**
2551	* Common worker for changing the pointer shape.
2552	*
2553	* @param pThis The VGA instance data.
2554	* @param pSVGAState The VMSVGA ring-3 instance data.
2555	* @param fAlpha Whether there is alpha or not.
2556	* @param xHot Hotspot x coordinate.
2557	* @param yHot Hotspot y coordinate.
2558	* @param cx Width.
2559	* @param cy Height.
2560	* @param pbData Heap copy of the cursor data. Consumed.
2561	* @param cbData The size of the data.
2562	*/
2563	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2564	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2565	{
2566	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2567	#ifdef LOG_ENABLED
2568	if (LogIs2Enabled())
2569	{
2570	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2571	if (!fAlpha)
2572	{
2573	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2574	for (uint32_t y = 0; y < cy; y++)
2575	{
2576	Log2(("%3u:", y));
2577	uint8_t const pbLine = &pbData[y cbAndLine];
2578	for (uint32_t x = 0; x < cx; x += 8)
2579	{
2580	uint8_t b = pbLine[x / 8];
2581	char szByte[12];
2582	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2583	szByte[1] = b & 0x40 ? '*' : ' ';
2584	szByte[2] = b & 0x20 ? '*' : ' ';
2585	szByte[3] = b & 0x10 ? '*' : ' ';
2586	szByte[4] = b & 0x08 ? '*' : ' ';
2587	szByte[5] = b & 0x04 ? '*' : ' ';
2588	szByte[6] = b & 0x02 ? '*' : ' ';
2589	szByte[7] = b & 0x01 ? '*' : ' ';
2590	szByte[8] = '\0';
2591	Log2(("%s", szByte));
2592	}
2593	Log2(("\n"));
2594	}
2595	}
2596
2597	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2598	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2599	for (uint32_t y = 0; y < cy; y++)
2600	{
2601	Log2(("%3u:", y));
2602	uint32_t const pu32Line = &pu32Xor[y cx];
2603	for (uint32_t x = 0; x < cx; x++)
2604	Log2((" %08x", pu32Line[x]));
2605	Log2(("\n"));
2606	}
2607	}
2608	#endif
2609
2610	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2611	AssertRC(rc);
2612
2613	if (pSVGAState->Cursor.fActive)
2614	RTMemFree(pSVGAState->Cursor.pData);
2615
2616	pSVGAState->Cursor.fActive = true;
2617	pSVGAState->Cursor.xHotspot = xHot;
2618	pSVGAState->Cursor.yHotspot = yHot;
2619	pSVGAState->Cursor.width = cx;
2620	pSVGAState->Cursor.height = cy;
2621	pSVGAState->Cursor.cbData = cbData;
2622	pSVGAState->Cursor.pData = pbData;
2623	}
2624
2625
2626	/**
2627	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2628	*
2629	* @param pThis The VGA instance data.
2630	* @param pSVGAState The VMSVGA ring-3 instance data.
2631	* @param pCursor The cursor.
2632	* @param pbSrcAndMask The AND mask.
2633	* @param cbSrcAndLine The scanline length of the AND mask.
2634	* @param pbSrcXorMask The XOR mask.
2635	* @param cbSrcXorLine The scanline length of the XOR mask.
2636	*/
2637	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2638	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2639	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2640	{
2641	uint32_t const cx = pCursor->width;
2642	uint32_t const cy = pCursor->height;
2643
2644	/*
2645	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2646	* The AND data uses 8-bit aligned scanlines.
2647	* The XOR data must be starting on a 32-bit boundrary.
2648	*/
2649	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2650	uint32_t cbDstAndMask = cbDstAndLine * cy;
2651	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2652	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2653
2654	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2655	AssertReturnVoid(pbCopy);
2656
2657	/* Convert the AND mask. */
2658	uint8_t *pbDst = pbCopy;
2659	uint8_t const *pbSrc = pbSrcAndMask;
2660	switch (pCursor->andMaskDepth)
2661	{
2662	case 1:
2663	if (cbSrcAndLine == cbDstAndLine)
2664	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2665	else
2666	{
2667	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2668	for (uint32_t y = 0; y < cy; y++)
2669	{
2670	memcpy(pbDst, pbSrc, cbDstAndLine);
2671	pbDst += cbDstAndLine;
2672	pbSrc += cbSrcAndLine;
2673	}
2674	}
2675	break;
2676	/* Should take the XOR mask into account for the multi-bit AND mask. */
2677	case 8:
2678	for (uint32_t y = 0; y < cy; y++)
2679	{
2680	for (uint32_t x = 0; x < cx; )
2681	{
2682	uint8_t bDst = 0;
2683	uint8_t fBit = 1;
2684	do
2685	{
2686	uintptr_t const idxPal = pbSrc[x] * 3;
2687	if ((( pThis->last_palette[idxPal]
2688	\| (pThis->last_palette[idxPal] >> 8)
2689	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2690	bDst \|= fBit;
2691	fBit <<= 1;
2692	x++;
2693	} while (x < cx && (x & 7));
2694	pbDst[(x - 1) / 8] = bDst;
2695	}
2696	pbDst += cbDstAndLine;
2697	pbSrc += cbSrcAndLine;
2698	}
2699	break;
2700	case 15:
2701	for (uint32_t y = 0; y < cy; y++)
2702	{
2703	for (uint32_t x = 0; x < cx; )
2704	{
2705	uint8_t bDst = 0;
2706	uint8_t fBit = 1;
2707	do
2708	{
2709	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2710	bDst \|= fBit;
2711	fBit <<= 1;
2712	x++;
2713	} while (x < cx && (x & 7));
2714	pbDst[(x - 1) / 8] = bDst;
2715	}
2716	pbDst += cbDstAndLine;
2717	pbSrc += cbSrcAndLine;
2718	}
2719	break;
2720	case 16:
2721	for (uint32_t y = 0; y < cy; y++)
2722	{
2723	for (uint32_t x = 0; x < cx; )
2724	{
2725	uint8_t bDst = 0;
2726	uint8_t fBit = 1;
2727	do
2728	{
2729	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2730	bDst \|= fBit;
2731	fBit <<= 1;
2732	x++;
2733	} while (x < cx && (x & 7));
2734	pbDst[(x - 1) / 8] = bDst;
2735	}
2736	pbDst += cbDstAndLine;
2737	pbSrc += cbSrcAndLine;
2738	}
2739	break;
2740	case 24:
2741	for (uint32_t y = 0; y < cy; y++)
2742	{
2743	for (uint32_t x = 0; x < cx; )
2744	{
2745	uint8_t bDst = 0;
2746	uint8_t fBit = 1;
2747	do
2748	{
2749	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2750	bDst \|= fBit;
2751	fBit <<= 1;
2752	x++;
2753	} while (x < cx && (x & 7));
2754	pbDst[(x - 1) / 8] = bDst;
2755	}
2756	pbDst += cbDstAndLine;
2757	pbSrc += cbSrcAndLine;
2758	}
2759	break;
2760	case 32:
2761	for (uint32_t y = 0; y < cy; y++)
2762	{
2763	for (uint32_t x = 0; x < cx; )
2764	{
2765	uint8_t bDst = 0;
2766	uint8_t fBit = 1;
2767	do
2768	{
2769	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2770	bDst \|= fBit;
2771	fBit <<= 1;
2772	x++;
2773	} while (x < cx && (x & 7));
2774	pbDst[(x - 1) / 8] = bDst;
2775	}
2776	pbDst += cbDstAndLine;
2777	pbSrc += cbSrcAndLine;
2778	}
2779	break;
2780	default:
2781	RTMemFree(pbCopy);
2782	AssertFailedReturnVoid();
2783	}
2784
2785	/* Convert the XOR mask. */
2786	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2787	pbSrc = pbSrcXorMask;
2788	switch (pCursor->xorMaskDepth)
2789	{
2790	case 1:
2791	for (uint32_t y = 0; y < cy; y++)
2792	{
2793	for (uint32_t x = 0; x < cx; )
2794	{
2795	/* most significant bit is the left most one. */
2796	uint8_t bSrc = pbSrc[x / 8];
2797	do
2798	{
2799	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2800	bSrc <<= 1;
2801	x++;
2802	} while ((x & 7) && x < cx);
2803	}
2804	pbSrc += cbSrcXorLine;
2805	}
2806	break;
2807	case 8:
2808	for (uint32_t y = 0; y < cy; y++)
2809	{
2810	for (uint32_t x = 0; x < cx; x++)
2811	{
2812	uint32_t u = pThis->last_palette[pbSrc[x]];
2813	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2814	}
2815	pbSrc += cbSrcXorLine;
2816	}
2817	break;
2818	case 15: /* Src: RGB-5-5-5 */
2819	for (uint32_t y = 0; y < cy; y++)
2820	{
2821	for (uint32_t x = 0; x < cx; x++)
2822	{
2823	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2824	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2825	((uValue >> 5) & 0x1f) << 3,
2826	((uValue >> 10) & 0x1f) << 3, 0);
2827	}
2828	pbSrc += cbSrcXorLine;
2829	}
2830	break;
2831	case 16: /* Src: RGB-5-6-5 */
2832	for (uint32_t y = 0; y < cy; y++)
2833	{
2834	for (uint32_t x = 0; x < cx; x++)
2835	{
2836	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2837	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2838	((uValue >> 5) & 0x3f) << 2,
2839	((uValue >> 11) & 0x1f) << 3, 0);
2840	}
2841	pbSrc += cbSrcXorLine;
2842	}
2843	break;
2844	case 24:
2845	for (uint32_t y = 0; y < cy; y++)
2846	{
2847	for (uint32_t x = 0; x < cx; x++)
2848	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2849	pbSrc += cbSrcXorLine;
2850	}
2851	break;
2852	case 32:
2853	for (uint32_t y = 0; y < cy; y++)
2854	{
2855	for (uint32_t x = 0; x < cx; x++)
2856	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2857	pbSrc += cbSrcXorLine;
2858	}
2859	break;
2860	default:
2861	RTMemFree(pbCopy);
2862	AssertFailedReturnVoid();
2863	}
2864
2865	/*
2866	* Pass it to the frontend/whatever.
2867	*/
2868	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2869	}
2870
2871
2872	/**
2873	* Worker for vmsvgaR3FifoThread that handles an external command.
2874	*
2875	* @param pThis VGA device instance data.
2876	*/
2877	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2878	{
2879	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2880	switch (pThis->svga.u8FIFOExtCommand)
2881	{
2882	case VMSVGA_FIFO_EXTCMD_RESET:
2883	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2884	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2885	# ifdef VBOX_WITH_VMSVGA3D
2886	if (pThis->svga.f3DEnabled)
2887	{
2888	/* The 3d subsystem must be reset from the fifo thread. */
2889	vmsvga3dReset(pThis);
2890	}
2891	# endif
2892	break;
2893
2894	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2895	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2896	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2897	# ifdef VBOX_WITH_VMSVGA3D
2898	if (pThis->svga.f3DEnabled)
2899	{
2900	/* The 3d subsystem must be shut down from the fifo thread. */
2901	vmsvga3dTerminate(pThis);
2902	}
2903	# endif
2904	break;
2905
2906	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2907	{
2908	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2909	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2910	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2911	vmsvgaSaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2912	# ifdef VBOX_WITH_VMSVGA3D
2913	if (pThis->svga.f3DEnabled)
2914	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2915	# endif
2916	break;
2917	}
2918
2919	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2920	{
2921	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2922	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2923	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2924	vmsvgaLoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2925	# ifdef VBOX_WITH_VMSVGA3D
2926	if (pThis->svga.f3DEnabled)
2927	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2928	# endif
2929	break;
2930	}
2931
2932	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2933	{
2934	# ifdef VBOX_WITH_VMSVGA3D
2935	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2936	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2937	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2938	# endif
2939	break;
2940	}
2941
2942
2943	default:
2944	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2945	break;
2946	}
2947
2948	/*
2949	* Signal the end of the external command.
2950	*/
2951	pThis->svga.pvFIFOExtCmdParam = NULL;
2952	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2953	ASMMemoryFence(); /* paranoia^2 */
2954	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2955	AssertLogRelRC(rc);
2956	}
2957
2958	/**
2959	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2960	* doing a job on the FIFO thread (even when it's officially suspended).
2961	*
2962	* @returns VBox status code (fully asserted).
2963	* @param pDevIns The device instance.
2964	* @param pThis VGA device instance data.
2965	* @param uExtCmd The command to execute on the FIFO thread.
2966	* @param pvParam Pointer to command parameters.
2967	* @param cMsWait The time to wait for the command, given in
2968	* milliseconds.
2969	*/
2970	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2971	{
2972	Assert(cMsWait >= RT_MS_1SEC * 5);
2973	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2974	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2975
2976	int rc;
2977	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2978	PDMTHREADSTATE enmState = pThread->enmState;
2979	if (enmState == PDMTHREADSTATE_SUSPENDED)
2980	{
2981	/*
2982	* The thread is suspended, we have to temporarily wake it up so it can
2983	* perform the task.
2984	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2985	*/
2986	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2987	/* Post the request. */
2988	pThis->svga.fFifoExtCommandWakeup = true;
2989	pThis->svga.pvFIFOExtCmdParam = pvParam;
2990	pThis->svga.u8FIFOExtCommand = uExtCmd;
2991	ASMMemoryFence(); /* paranoia^3 */
2992
2993	/* Resume the thread. */
2994	rc = PDMDevHlpThreadResume(pDevIns, pThread);
2995	AssertLogRelRC(rc);
2996	if (RT_SUCCESS(rc))
2997	{
2998	/* Wait. Take care in case the semaphore was already posted (same as below). */
2999	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3000	if ( rc == VINF_SUCCESS
3001	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3002	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3003	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3004	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3005
3006	/* suspend the thread */
3007	pThis->svga.fFifoExtCommandWakeup = false;
3008	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3009	AssertLogRelRC(rc2);
3010	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3011	rc = rc2;
3012	}
3013	pThis->svga.fFifoExtCommandWakeup = false;
3014	pThis->svga.pvFIFOExtCmdParam = NULL;
3015	}
3016	else if (enmState == PDMTHREADSTATE_RUNNING)
3017	{
3018	/*
3019	* The thread is running, should only happen during reset and vmsvga3dsfc.
3020	* We ASSUME not racing code here, both wrt thread state and ext commands.
3021	*/
3022	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3023	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3024
3025	/* Post the request. */
3026	pThis->svga.pvFIFOExtCmdParam = pvParam;
3027	pThis->svga.u8FIFOExtCommand = uExtCmd;
3028	ASMMemoryFence(); /* paranoia^2 */
3029	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3030	AssertLogRelRC(rc);
3031
3032	/* Wait. Take care in case the semaphore was already posted (same as above). */
3033	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3034	if ( rc == VINF_SUCCESS
3035	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3036	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3037	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3038	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3039
3040	pThis->svga.pvFIFOExtCmdParam = NULL;
3041	}
3042	else
3043	{
3044	/*
3045	* Something is wrong with the thread!
3046	*/
3047	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3048	rc = VERR_INVALID_STATE;
3049	}
3050	return rc;
3051	}
3052
3053
3054	/**
3055	* Marks the FIFO non-busy, notifying any waiting EMTs.
3056	*
3057	* @param pThis The VGA state.
3058	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3059	* @param offFifoMin The start byte offset of the command FIFO.
3060	*/
3061	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3062	{
3063	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3064	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3065	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3066
3067	/* Wake up any waiting EMTs. */
3068	if (pSVGAState->cBusyDelayedEmts > 0)
3069	{
3070	#ifdef VMSVGA_USE_EMT_HALT_CODE
3071	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3072	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3073	if (idCpu != NIL_VMCPUID)
3074	{
3075	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3076	while (idCpu-- > 0)
3077	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3078	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3079	}
3080	#else
3081	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3082	AssertRC(rc2);
3083	#endif
3084	}
3085	}
3086
3087	/**
3088	* Reads (more) payload into the command buffer.
3089	*
3090	* @returns pbBounceBuf on success
3091	* @retval (void *)1 if the thread was requested to stop.
3092	* @retval NULL on FIFO error.
3093	*
3094	* @param cbPayloadReq The number of bytes of payload requested.
3095	* @param pFIFO The FIFO.
3096	* @param offCurrentCmd The FIFO byte offset of the current command.
3097	* @param offFifoMin The start byte offset of the command FIFO.
3098	* @param offFifoMax The end byte offset of the command FIFO.
3099	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3100	* always sufficient size.
3101	* @param pcbAlreadyRead How much payload we've already read into the bounce
3102	* buffer. (We will NEVER re-read anything.)
3103	* @param pThread The calling PDM thread handle.
3104	* @param pThis The VGA state.
3105	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3106	* statistics collection.
3107	*/
3108	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3109	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3110	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3111	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3112	{
3113	Assert(pbBounceBuf);
3114	Assert(pcbAlreadyRead);
3115	Assert(offFifoMin < offFifoMax);
3116	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3117	Assert(offFifoMax <= pThis->svga.cbFIFO);
3118
3119	/*
3120	* Check if the requested payload size has already been satisfied .
3121	* .
3122	* When called to read more, the caller is responsible for making sure the .
3123	* new command size (cbRequsted) never is smaller than what has already .
3124	* been read.
3125	*/
3126	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3127	if (cbPayloadReq <= cbAlreadyRead)
3128	{
3129	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3130	return pbBounceBuf;
3131	}
3132
3133	/*
3134	* Commands bigger than the fifo buffer are invalid.
3135	*/
3136	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3137	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3138	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3139	NULL);
3140
3141	/*
3142	* Move offCurrentCmd past the command dword.
3143	*/
3144	offCurrentCmd += sizeof(uint32_t);
3145	if (offCurrentCmd >= offFifoMax)
3146	offCurrentCmd = offFifoMin;
3147
3148	/*
3149	* Do we have sufficient payload data available already?
3150	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3151	*/
3152	uint32_t cbAfter, cbBefore;
3153	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3154	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3155	if (offNextCmd >= offCurrentCmd)
3156	{
3157	if (RT_LIKELY(offNextCmd < offFifoMax))
3158	cbAfter = offNextCmd - offCurrentCmd;
3159	else
3160	{
3161	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3162	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3163	offNextCmd, offFifoMin, offFifoMax));
3164	cbAfter = offFifoMax - offCurrentCmd;
3165	}
3166	cbBefore = 0;
3167	}
3168	else
3169	{
3170	cbAfter = offFifoMax - offCurrentCmd;
3171	if (offNextCmd >= offFifoMin)
3172	cbBefore = offNextCmd - offFifoMin;
3173	else
3174	{
3175	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3176	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3177	offNextCmd, offFifoMin, offFifoMax));
3178	cbBefore = 0;
3179	}
3180	}
3181	if (cbAfter + cbBefore < cbPayloadReq)
3182	{
3183	/*
3184	* Insufficient, must wait for it to arrive.
3185	*/
3186	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3187	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3188	for (uint32_t i = 0;; i++)
3189	{
3190	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3191	{
3192	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3193	return (void *)(uintptr_t)1;
3194	}
3195	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3196	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3197
3198	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3199
3200	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3201	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3202	if (offNextCmd >= offCurrentCmd)
3203	{
3204	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3205	cbBefore = 0;
3206	}
3207	else
3208	{
3209	cbAfter = offFifoMax - offCurrentCmd;
3210	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3211	}
3212
3213	if (cbAfter + cbBefore >= cbPayloadReq)
3214	break;
3215	}
3216	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3217	}
3218
3219	/*
3220	* Copy out the memory and update what pcbAlreadyRead points to.
3221	*/
3222	if (cbAfter >= cbPayloadReq)
3223	memcpy(pbBounceBuf + cbAlreadyRead,
3224	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3225	cbPayloadReq - cbAlreadyRead);
3226	else
3227	{
3228	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3229	if (cbAlreadyRead < cbAfter)
3230	{
3231	memcpy(pbBounceBuf + cbAlreadyRead,
3232	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3233	cbAfter - cbAlreadyRead);
3234	cbAlreadyRead = cbAfter;
3235	}
3236	memcpy(pbBounceBuf + cbAlreadyRead,
3237	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3238	cbPayloadReq - cbAlreadyRead);
3239	}
3240	*pcbAlreadyRead = cbPayloadReq;
3241	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3242	return pbBounceBuf;
3243	}
3244
3245
3246	/**
3247	* Sends cursor position and visibility information from the FIFO to the front-end.
3248	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3249	*/
3250	static uint32_t
3251	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3252	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3253	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3254	{
3255	/*
3256	* Check if the cursor update counter has changed and try get a stable
3257	* set of values if it has. This is race-prone, especially consindering
3258	* the screen ID, but little we can do about that.
3259	*/
3260	uint32_t x, y, fVisible, idScreen;
3261	for (uint32_t i = 0; ; i++)
3262	{
3263	x = pFIFO[SVGA_FIFO_CURSOR_X];
3264	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3265	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3266	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3267	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3268	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3269	\|\| i > 3)
3270	break;
3271	if (i == 0)
3272	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3273	ASMNopPause();
3274	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3275	}
3276
3277	/*
3278	* Check if anything has changed, as calling into pDrv is not light-weight.
3279	*/
3280	if ( *pxLast == x
3281	&& *pyLast == y
3282	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3283	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3284	else
3285	{
3286	/*
3287	* Detected changes.
3288	*
3289	* We handle global, not per-screen visibility information by sending
3290	* pfnVBVAMousePointerShape without shape data.
3291	*/
3292	*pxLast = x;
3293	*pyLast = y;
3294	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3295	if (idScreen != SVGA_ID_INVALID)
3296	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3297	else if (*pfLastVisible != fVisible)
3298	{
3299	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3300	*pfLastVisible = fVisible;
3301	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3302	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3303	}
3304	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3305	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3306	}
3307
3308	/*
3309	* Update done. Signal this to the guest.
3310	*/
3311	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3312
3313	return uCursorUpdateCount;
3314	}
3315
3316
3317	/**
3318	* Checks if there is work to be done, either cursor updating or FIFO commands.
3319	*
3320	* @returns true if pending work, false if not.
3321	* @param pFIFO The FIFO to examine.
3322	* @param uLastCursorCount The last cursor update counter value.
3323	*/
3324	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3325	{
3326	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3327	return true;
3328
3329	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3330	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3331	return true;
3332
3333	return false;
3334	}
3335
3336
3337	/**
3338	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3339	*
3340	* @param pThis The VGA state.
3341	*/
3342	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3343	{
3344	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3345	to recheck it before doing the signalling. */
3346	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3347	AssertReturnVoid(pFIFO);
3348	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3349	&& pThis->svga.fFIFOThreadSleeping)
3350	{
3351	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3352	AssertRC(rc);
3353	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3354	}
3355	}
3356
3357
3358	/* The async FIFO handling thread. */
3359	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3360	{
3361	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3362	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3363	int rc;
3364
3365	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3366	return VINF_SUCCESS;
3367
3368	/*
3369	* Special mode where we only execute an external command and the go back
3370	* to being suspended. Currently, all ext cmds ends up here, with the reset
3371	* one also being eligble for runtime execution further down as well.
3372	*/
3373	if (pThis->svga.fFifoExtCommandWakeup)
3374	{
3375	vmsvgaR3FifoHandleExtCmd(pThis);
3376	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3377	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3378	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3379	else
3380	vmsvgaR3FifoHandleExtCmd(pThis);
3381	return VINF_SUCCESS;
3382	}
3383
3384
3385	/*
3386	* Signal the semaphore to make sure we don't wait for 250ms after a
3387	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3388	*/
3389	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3390
3391	/*
3392	* Allocate a bounce buffer for command we get from the FIFO.
3393	* (All code must return via the end of the function to free this buffer.)
3394	*/
3395	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3396	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3397
3398	/*
3399	* Polling/sleep interval config.
3400	*
3401	* We wait for an a short interval if the guest has recently given us work
3402	* to do, but the interval increases the longer we're kept idle. Once we've
3403	* reached the refresh timer interval, we'll switch to extended waits,
3404	* depending on it or the guest to kick us into action when needed.
3405	*
3406	* Should the refresh time go fishing, we'll just continue increasing the
3407	* sleep length till we reaches the 250 ms max after about 16 seconds.
3408	*/
3409	RTMSINTERVAL const cMsMinSleep = 16;
3410	RTMSINTERVAL const cMsIncSleep = 2;
3411	RTMSINTERVAL const cMsMaxSleep = 250;
3412	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3413	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3414
3415	/*
3416	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3417	*
3418	* Initialize with values that will detect an update from the guest.
3419	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3420	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3421	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3422	*/
3423	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3424	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3425	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3426	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3427	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3428
3429	/*
3430	* The FIFO loop.
3431	*/
3432	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3433	bool fBadOrDisabledFifo = false;
3434	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3435	{
3436	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3437	/*
3438	* Should service the run loop every so often.
3439	*/
3440	if (pThis->svga.f3DEnabled)
3441	vmsvga3dCocoaServiceRunLoop();
3442	# endif
3443
3444	/*
3445	* Unless there's already work pending, go to sleep for a short while.
3446	* (See polling/sleep interval config above.)
3447	*/
3448	if ( fBadOrDisabledFifo
3449	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3450	{
3451	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3452	Assert(pThis->cMilliesRefreshInterval > 0);
3453	if (cMsSleep < pThis->cMilliesRefreshInterval)
3454	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3455	else
3456	{
3457	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3458	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3459	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3460	# endif
3461	if ( !fBadOrDisabledFifo
3462	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3463	rc = VINF_SUCCESS;
3464	else
3465	{
3466	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3467	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3468	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3469	}
3470	}
3471	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3472	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3473	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3474	{
3475	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3476	break;
3477	}
3478	}
3479	else
3480	rc = VINF_SUCCESS;
3481	fBadOrDisabledFifo = false;
3482	if (rc == VERR_TIMEOUT)
3483	{
3484	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3485	{
3486	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3487	continue;
3488	}
3489	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3490
3491	Log(("vmsvgaFIFOLoop: timeout\n"));
3492	}
3493	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3494	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3495	cMsSleep = cMsMinSleep;
3496
3497	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3498	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3499	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3500
3501	/*
3502	* Handle external commands (currently only reset).
3503	*/
3504	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3505	{
3506	vmsvgaR3FifoHandleExtCmd(pThis);
3507	continue;
3508	}
3509
3510	/*
3511	* The device must be enabled and configured.
3512	*/
3513	if ( !pThis->svga.fEnabled
3514	\|\| !pThis->svga.fConfigured)
3515	{
3516	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3517	fBadOrDisabledFifo = true;
3518	cMsSleep = cMsMaxSleep; /* cheat */
3519	continue;
3520	}
3521
3522	/*
3523	* Get and check the min/max values. We ASSUME that they will remain
3524	* unchanged while we process requests. A further ASSUMPTION is that
3525	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3526	* we don't read it back while in the loop.
3527	*/
3528	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3529	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3530	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3531	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3532	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3533	\|\| offFifoMax <= offFifoMin
3534	\|\| offFifoMax > pThis->svga.cbFIFO
3535	\|\| (offFifoMax & 3) != 0
3536	\|\| (offFifoMin & 3) != 0
3537	\|\| offCurrentCmd < offFifoMin
3538	\|\| offCurrentCmd > offFifoMax))
3539	{
3540	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3541	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3542	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3543	fBadOrDisabledFifo = true;
3544	continue;
3545	}
3546	RT_UNTRUSTED_VALIDATED_FENCE();
3547	if (RT_UNLIKELY(offCurrentCmd & 3))
3548	{
3549	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3550	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3551	offCurrentCmd &= ~UINT32_C(3);
3552	}
3553
3554	/*
3555	* Update the cursor position before we start on the FIFO commands.
3556	*/
3557	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3558	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3559	{
3560	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3561	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3562	{ /* halfways likely */ }
3563	else
3564	{
3565	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3566	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3567	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3568	}
3569	}
3570
3571	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3572	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3573	*
3574	* Will break out of the switch on failure.
3575	* Will restart and quit the loop if the thread was requested to stop.
3576	*
3577	* @param a_PtrVar Request variable pointer.
3578	* @param a_Type Request typedef (not pointer) for casting.
3579	* @param a_cbPayloadReq How much payload to fetch.
3580	* @remarks Accesses a bunch of variables in the current scope!
3581	*/
3582	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3583	if (1) { \
3584	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3585	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3586	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3587	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3588	} else do {} while (0)
3589	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3590	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3591	* buffer after figuring out the actual command size.
3592	*
3593	* Will break out of the switch on failure.
3594	*
3595	* @param a_PtrVar Request variable pointer.
3596	* @param a_Type Request typedef (not pointer) for casting.
3597	* @param a_cbPayloadReq How much payload to fetch.
3598	* @remarks Accesses a bunch of variables in the current scope!
3599	*/
3600	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3601	if (1) { \
3602	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3603	} else do {} while (0)
3604
3605	/*
3606	* Mark the FIFO as busy.
3607	*/
3608	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3609	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3610	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3611
3612	/*
3613	* Execute all queued FIFO commands.
3614	* Quit if pending external command or changes in the thread state.
3615	*/
3616	bool fDone = false;
3617	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3618	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3619	{
3620	uint32_t cbPayload = 0;
3621	uint32_t u32IrqStatus = 0;
3622
3623	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3624
3625	/* First check any pending actions. */
3626	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3627	{
3628	vmsvgaChangeMode(pThis);
3629	# ifdef VBOX_WITH_VMSVGA3D
3630	if (pThis->svga.p3dState != NULL)
3631	vmsvga3dChangeMode(pThis);
3632	# endif
3633	}
3634
3635	/* Check for pending external commands (reset). */
3636	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3637	break;
3638
3639	/*
3640	* Process the command.
3641	*/
3642	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3643	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3644	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3645	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3646	switch (enmCmdId)
3647	{
3648	case SVGA_CMD_INVALID_CMD:
3649	/* Nothing to do. */
3650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3651	break;
3652
3653	case SVGA_CMD_FENCE:
3654	{
3655	SVGAFifoCmdFence *pCmdFence;
3656	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3657	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3658	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3659	{
3660	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3661	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3662
3663	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3664	{
3665	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3666	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3667	}
3668	else
3669	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3670	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3671	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3672	{
3673	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3674	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3675	}
3676	}
3677	else
3678	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3679	break;
3680	}
3681	case SVGA_CMD_UPDATE:
3682	case SVGA_CMD_UPDATE_VERBOSE:
3683	{
3684	SVGAFifoCmdUpdate *pUpdate;
3685	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3686	if (enmCmdId == SVGA_CMD_UPDATE)
3687	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3688	else
3689	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3690	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3691	/** @todo Multiple screens? */
3692	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3693	AssertBreak(pScreen);
3694	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3695	break;
3696	}
3697
3698	case SVGA_CMD_DEFINE_CURSOR:
3699	{
3700	/* Followed by bitmap data. */
3701	SVGAFifoCmdDefineCursor *pCursor;
3702	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3703	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3704
3705	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3706	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3707	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3708	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3709	AssertBreak(pCursor->andMaskDepth <= 32);
3710	AssertBreak(pCursor->xorMaskDepth <= 32);
3711	RT_UNTRUSTED_VALIDATED_FENCE();
3712
3713	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3714	uint32_t cbAndMask = cbAndLine * pCursor->height;
3715	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3716	uint32_t cbXorMask = cbXorLine * pCursor->height;
3717	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3718
3719	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3720	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3721	break;
3722	}
3723
3724	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3725	{
3726	/* Followed by bitmap data. */
3727	uint32_t cbCursorShape, cbAndMask;
3728	uint8_t *pCursorCopy;
3729	uint32_t cbCmd;
3730
3731	SVGAFifoCmdDefineAlphaCursor *pCursor;
3732	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3733	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3734
3735	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3736
3737	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3738	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3739	RT_UNTRUSTED_VALIDATED_FENCE();
3740
3741	/* Refetch the bitmap data as well. */
3742	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3743	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3744	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3745
3746	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3747	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3748	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3749	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3750
3751	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3752	AssertBreak(pCursorCopy);
3753
3754	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3755	memset(pCursorCopy, 0xff, cbAndMask);
3756	/* Colour data */
3757	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3758
3759	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3760	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3761	break;
3762	}
3763
3764	case SVGA_CMD_ESCAPE:
3765	{
3766	/* Followed by nsize bytes of data. */
3767	SVGAFifoCmdEscape *pEscape;
3768	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3769	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3770
3771	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3772	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3773	RT_UNTRUSTED_VALIDATED_FENCE();
3774	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3775	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3776
3777	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3778	{
3779	AssertBreak(pEscape->size >= sizeof(uint32_t));
3780	RT_UNTRUSTED_VALIDATED_FENCE();
3781	uint32_t cmd = (uint32_t )(pEscape + 1);
3782	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3783
3784	switch (cmd)
3785	{
3786	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3787	{
3788	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3789	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3790	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3791
3792	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3793	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3794	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3795
3796	RT_NOREF_PV(pVideoCmd);
3797	break;
3798
3799	}
3800
3801	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3802	{
3803	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3804	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3805	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3806	RT_NOREF_PV(pVideoCmd);
3807	break;
3808	}
3809
3810	default:
3811	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3812	break;
3813	}
3814	}
3815	else
3816	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3817
3818	break;
3819	}
3820	# ifdef VBOX_WITH_VMSVGA3D
3821	case SVGA_CMD_DEFINE_GMR2:
3822	{
3823	SVGAFifoCmdDefineGMR2 *pCmd;
3824	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3825	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3826	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3827
3828	/* Validate current GMR id. */
3829	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3830	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3831	RT_UNTRUSTED_VALIDATED_FENCE();
3832
3833	if (!pCmd->numPages)
3834	{
3835	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3836	vmsvgaGMRFree(pThis, pCmd->gmrId);
3837	}
3838	else
3839	{
3840	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3841	if (pGMR->cMaxPages)
3842	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3843
3844	/* Not sure if we should always free the descriptor, but for simplicity
3845	we do so if the new size is smaller than the current. */
3846	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3847	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3848	vmsvgaGMRFree(pThis, pCmd->gmrId);
3849
3850	pGMR->cMaxPages = pCmd->numPages;
3851	/* The rest is done by the REMAP_GMR2 command. */
3852	}
3853	break;
3854	}
3855
3856	case SVGA_CMD_REMAP_GMR2:
3857	{
3858	/* Followed by page descriptors or guest ptr. */
3859	SVGAFifoCmdRemapGMR2 *pCmd;
3860	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3861	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3862
3863	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3864	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3865	RT_UNTRUSTED_VALIDATED_FENCE();
3866
3867	/* Calculate the size of what comes after next and fetch it. */
3868	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3869	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3870	cbCmd += sizeof(SVGAGuestPtr);
3871	else
3872	{
3873	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3874	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3875	{
3876	cbCmd += cbPageDesc;
3877	pCmd->numPages = 1;
3878	}
3879	else
3880	{
3881	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3882	cbCmd += cbPageDesc * pCmd->numPages;
3883	}
3884	}
3885	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3886
3887	/* Validate current GMR id and size. */
3888	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3889	RT_UNTRUSTED_VALIDATED_FENCE();
3890	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3891	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3892	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3893	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3894
3895	if (pCmd->numPages == 0)
3896	break;
3897
3898	/** @todo Move to a separate function vmsvgaGMRRemap() */
3899
3900	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3901	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3902
3903	/*
3904	* We flatten the existing descriptors into a page array, overwrite the
3905	* pages specified in this command and then recompress the descriptor.
3906	*/
3907	/** @todo Optimize the GMR remap algorithm! */
3908
3909	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3910	uint64_t *paNewPage64 = NULL;
3911	if (pGMR->paDesc)
3912	{
3913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3914
3915	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3916	AssertBreak(paNewPage64);
3917
3918	uint32_t idxPage = 0;
3919	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3920	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3921	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3922	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3923	RT_UNTRUSTED_VALIDATED_FENCE();
3924	}
3925
3926	/* Free the old GMR if present. */
3927	if (pGMR->paDesc)
3928	RTMemFree(pGMR->paDesc);
3929
3930	/* Allocate the maximum amount possible (everything non-continuous) */
3931	PVMSVGAGMRDESCRIPTOR paDescs;
3932	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3933	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3934
3935	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3936	{
3937	/** @todo */
3938	AssertFailed();
3939	pGMR->numDescriptors = 0;
3940	}
3941	else
3942	{
3943	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3944	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3945	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3946
3947	if (paNewPage64)
3948	{
3949	/* Overwrite the old page array with the new page values. */
3950	if (fGCPhys64)
3951	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3952	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3953	else
3954	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3955	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3956
3957	/* Use the updated page array instead of the command data. */
3958	fGCPhys64 = true;
3959	paPages64 = paNewPage64;
3960	pCmd->numPages = cNewTotalPages;
3961	}
3962
3963	/* The first page. */
3964	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3965	* applied to paNewPage64. */
3966	RTGCPHYS GCPhys;
3967	if (fGCPhys64)
3968	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3969	else
3970	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3971	paDescs[0].GCPhys = GCPhys;
3972	paDescs[0].numPages = 1;
3973
3974	/* Subsequent pages. */
3975	uint32_t iDescriptor = 0;
3976	for (uint32_t i = 1; i < pCmd->numPages; i++)
3977	{
3978	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3979	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3980	else
3981	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3982
3983	/* Continuous physical memory? */
3984	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3985	{
3986	Assert(paDescs[iDescriptor].numPages);
3987	paDescs[iDescriptor].numPages++;
3988	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3989	}
3990	else
3991	{
3992	iDescriptor++;
3993	paDescs[iDescriptor].GCPhys = GCPhys;
3994	paDescs[iDescriptor].numPages = 1;
3995	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3996	}
3997	}
3998
3999	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4000	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4001	pGMR->numDescriptors = iDescriptor + 1;
4002	}
4003
4004	if (paNewPage64)
4005	RTMemFree(paNewPage64);
4006
4007	# ifdef DEBUG_GMR_ACCESS
4008	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4009	# endif
4010	break;
4011	}
4012	# endif // VBOX_WITH_VMSVGA3D
4013	case SVGA_CMD_DEFINE_SCREEN:
4014	{
4015	/* The size of this command is specified by the guest and depends on capabilities. */
4016	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4017
4018	SVGAFifoCmdDefineScreen *pCmd;
4019	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4020	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4021	RT_UNTRUSTED_VALIDATED_FENCE();
4022
4023	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4024	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4025	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4026
4027	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4028	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4029	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4030
4031	uint32_t const idScreen = pCmd->screen.id;
4032	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4033
4034	uint32_t const uWidth = pCmd->screen.size.width;
4035	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4036
4037	uint32_t const uHeight = pCmd->screen.size.height;
4038	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4039
4040	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4041	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4042	AssertBreak(cbWidth <= cbPitch);
4043
4044	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4045	AssertBreak(uScreenOffset < pThis->vram_size);
4046
4047	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4048	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4049	AssertBreak( (uHeight == 0 && cbPitch == 0)
4050	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4051	RT_UNTRUSTED_VALIDATED_FENCE();
4052
4053	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4054
4055	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4056
4057	pScreen->fDefined = true;
4058	pScreen->fModified = true;
4059	pScreen->fuScreen = pCmd->screen.flags;
4060	pScreen->idScreen = idScreen;
4061	if (!fBlank)
4062	{
4063	AssertBreak(uWidth > 0 && uHeight > 0);
4064
4065	pScreen->xOrigin = pCmd->screen.root.x;
4066	pScreen->yOrigin = pCmd->screen.root.y;
4067	pScreen->cWidth = uWidth;
4068	pScreen->cHeight = uHeight;
4069	pScreen->offVRAM = uScreenOffset;
4070	pScreen->cbPitch = cbPitch;
4071	pScreen->cBpp = 32;
4072	}
4073	else
4074	{
4075	/* Keep old values. */
4076	}
4077
4078	pThis->svga.fGFBRegisters = false;
4079	vmsvgaChangeMode(pThis);
4080	break;
4081	}
4082
4083	case SVGA_CMD_DESTROY_SCREEN:
4084	{
4085	SVGAFifoCmdDestroyScreen *pCmd;
4086	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4087	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4088
4089	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4090
4091	uint32_t const idScreen = pCmd->screenId;
4092	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4093	RT_UNTRUSTED_VALIDATED_FENCE();
4094
4095	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4096	pScreen->fModified = true;
4097	pScreen->fDefined = false;
4098	pScreen->idScreen = idScreen;
4099
4100	vmsvgaChangeMode(pThis);
4101	break;
4102	}
4103
4104	case SVGA_CMD_DEFINE_GMRFB:
4105	{
4106	SVGAFifoCmdDefineGMRFB *pCmd;
4107	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4108	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4109
4110	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4111	pSVGAState->GMRFB.ptr = pCmd->ptr;
4112	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4113	pSVGAState->GMRFB.format = pCmd->format;
4114	break;
4115	}
4116
4117	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4118	{
4119	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4120	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4121	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4122
4123	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4124	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4125
4126	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4127	RT_UNTRUSTED_VALIDATED_FENCE();
4128
4129	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4130	AssertBreak(pScreen);
4131
4132	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4133	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4134
4135	/* Clip destRect to the screen dimensions. */
4136	SVGASignedRect screenRect;
4137	screenRect.left = 0;
4138	screenRect.top = 0;
4139	screenRect.right = pScreen->cWidth;
4140	screenRect.bottom = pScreen->cHeight;
4141	SVGASignedRect clipRect = pCmd->destRect;
4142	vmsvgaClipRect(&screenRect, &clipRect);
4143	RT_UNTRUSTED_VALIDATED_FENCE();
4144
4145	uint32_t const width = clipRect.right - clipRect.left;
4146	uint32_t const height = clipRect.bottom - clipRect.top;
4147
4148	if ( width == 0
4149	\|\| height == 0)
4150	break; /* Nothing to do. */
4151
4152	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4153	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4154
4155	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4156	* Prepare parameters for vmsvgaGMRTransfer.
4157	*/
4158	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4159
4160	/* Destination: host buffer which describes the screen 0 VRAM.
4161	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4162	*/
4163	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4164	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4165	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4166	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4167	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4168	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4169	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4170	+ cbScanline * clipRect.top;
4171	int32_t const cbHstPitch = cbScanline;
4172
4173	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4174	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4175	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4176	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4177	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4178
4179	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4180	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4181	gstPtr, offGst, cbGstPitch,
4182	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4183	AssertRC(rc);
4184	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4185	break;
4186	}
4187
4188	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4189	{
4190	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4191	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4192	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4193
4194	/* Note! This can fetch 3d render results as well!! */
4195	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4196	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4197
4198	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4199	RT_UNTRUSTED_VALIDATED_FENCE();
4200
4201	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4202	AssertBreak(pScreen);
4203
4204	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4205	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4206
4207	/* Clip destRect to the screen dimensions. */
4208	SVGASignedRect screenRect;
4209	screenRect.left = 0;
4210	screenRect.top = 0;
4211	screenRect.right = pScreen->cWidth;
4212	screenRect.bottom = pScreen->cHeight;
4213	SVGASignedRect clipRect = pCmd->srcRect;
4214	vmsvgaClipRect(&screenRect, &clipRect);
4215	RT_UNTRUSTED_VALIDATED_FENCE();
4216
4217	uint32_t const width = clipRect.right - clipRect.left;
4218	uint32_t const height = clipRect.bottom - clipRect.top;
4219
4220	if ( width == 0
4221	\|\| height == 0)
4222	break; /* Nothing to do. */
4223
4224	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4225	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4226
4227	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4228	* Prepare parameters for vmsvgaGMRTransfer.
4229	*/
4230	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4231
4232	/* Source: host buffer which describes the screen 0 VRAM.
4233	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4234	*/
4235	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4236	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4237	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4238	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4239	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4240	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4241	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4242	+ cbScanline * clipRect.top;
4243	int32_t const cbHstPitch = cbScanline;
4244
4245	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4246	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4247	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4248	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4249	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4250
4251	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4252	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4253	gstPtr, offGst, cbGstPitch,
4254	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4255	AssertRC(rc);
4256	break;
4257	}
4258
4259	case SVGA_CMD_ANNOTATION_FILL:
4260	{
4261	SVGAFifoCmdAnnotationFill *pCmd;
4262	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4263	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4264
4265	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4266	pSVGAState->colorAnnotation = pCmd->color;
4267	break;
4268	}
4269
4270	case SVGA_CMD_ANNOTATION_COPY:
4271	{
4272	SVGAFifoCmdAnnotationCopy *pCmd;
4273	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4274	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4275
4276	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4277	AssertFailed();
4278	break;
4279	}
4280
4281	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4282
4283	default:
4284	# ifdef VBOX_WITH_VMSVGA3D
4285	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4286	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4287	{
4288	RT_UNTRUSTED_VALIDATED_FENCE();
4289
4290	/* All 3d commands start with a common header, which defines the size of the command. */
4291	SVGA3dCmdHeader *pHdr;
4292	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4293	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4294	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4295	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4296
4297	if (RT_LIKELY(pThis->svga.f3DEnabled))
4298	{ /* likely */ }
4299	else
4300	{
4301	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4302	break;
4303	}
4304
4305	/**
4306	* Check that the 3D command has at least a_cbMin of payload bytes after the
4307	* header. Will break out of the switch if it doesn't.
4308	*/
4309	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4310	if (1) { \
4311	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4312	RT_UNTRUSTED_VALIDATED_FENCE(); \
4313	} else do {} while (0)
4314	switch ((int)enmCmdId)
4315	{
4316	case SVGA_3D_CMD_SURFACE_DEFINE:
4317	{
4318	uint32_t cMipLevels;
4319	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4320	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4321	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4322
4323	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4324	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4325	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4326	# ifdef DEBUG_GMR_ACCESS
4327	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4328	# endif
4329	break;
4330	}
4331
4332	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4333	{
4334	uint32_t cMipLevels;
4335	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4336	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4337	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4338
4339	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4340	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4341	pCmd->multisampleCount, pCmd->autogenFilter,
4342	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4343	break;
4344	}
4345
4346	case SVGA_3D_CMD_SURFACE_DESTROY:
4347	{
4348	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4349	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4350	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4351	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4352	break;
4353	}
4354
4355	case SVGA_3D_CMD_SURFACE_COPY:
4356	{
4357	uint32_t cCopyBoxes;
4358	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4359	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4360	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4361
4362	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4363	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4364	break;
4365	}
4366
4367	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4368	{
4369	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4370	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4371	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4372
4373	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4374	break;
4375	}
4376
4377	case SVGA_3D_CMD_SURFACE_DMA:
4378	{
4379	uint32_t cCopyBoxes;
4380	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4381	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4382	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4383
4384	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4385	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4386	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4387	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4388	break;
4389	}
4390
4391	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4392	{
4393	uint32_t cRects;
4394	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4395	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4396	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4397
4398	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4399	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4400	break;
4401	}
4402
4403	case SVGA_3D_CMD_CONTEXT_DEFINE:
4404	{
4405	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4406	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4407	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4408
4409	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4410	break;
4411	}
4412
4413	case SVGA_3D_CMD_CONTEXT_DESTROY:
4414	{
4415	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4416	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4417	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4418
4419	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4420	break;
4421	}
4422
4423	case SVGA_3D_CMD_SETTRANSFORM:
4424	{
4425	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4426	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4427	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4428
4429	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4430	break;
4431	}
4432
4433	case SVGA_3D_CMD_SETZRANGE:
4434	{
4435	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4436	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4437	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4438
4439	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_SETRENDERSTATE:
4444	{
4445	uint32_t cRenderStates;
4446	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4447	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4449
4450	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4451	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4452	break;
4453	}
4454
4455	case SVGA_3D_CMD_SETRENDERTARGET:
4456	{
4457	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4458	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4459	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4460
4461	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4462	break;
4463	}
4464
4465	case SVGA_3D_CMD_SETTEXTURESTATE:
4466	{
4467	uint32_t cTextureStates;
4468	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4469	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4470	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4471
4472	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4473	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4474	break;
4475	}
4476
4477	case SVGA_3D_CMD_SETMATERIAL:
4478	{
4479	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4480	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4481	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4482
4483	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4484	break;
4485	}
4486
4487	case SVGA_3D_CMD_SETLIGHTDATA:
4488	{
4489	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4490	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4491	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4492
4493	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4494	break;
4495	}
4496
4497	case SVGA_3D_CMD_SETLIGHTENABLED:
4498	{
4499	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4500	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4501	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4502
4503	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4504	break;
4505	}
4506
4507	case SVGA_3D_CMD_SETVIEWPORT:
4508	{
4509	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4510	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4511	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4512
4513	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4514	break;
4515	}
4516
4517	case SVGA_3D_CMD_SETCLIPPLANE:
4518	{
4519	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4520	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4522
4523	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_CLEAR:
4528	{
4529	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4532
4533	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4534	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4535	break;
4536	}
4537
4538	case SVGA_3D_CMD_PRESENT:
4539	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4540	{
4541	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4542	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4543	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4544	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4545	else
4546	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4547
4548	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4549
4550	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4551	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4552	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4553	break;
4554	}
4555
4556	case SVGA_3D_CMD_SHADER_DEFINE:
4557	{
4558	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4559	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4560	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4561
4562	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4563	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4564	break;
4565	}
4566
4567	case SVGA_3D_CMD_SHADER_DESTROY:
4568	{
4569	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4571	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4572
4573	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4574	break;
4575	}
4576
4577	case SVGA_3D_CMD_SET_SHADER:
4578	{
4579	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4580	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4582
4583	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4584	break;
4585	}
4586
4587	case SVGA_3D_CMD_SET_SHADER_CONST:
4588	{
4589	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4590	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4591	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4592
4593	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4594	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4595	break;
4596	}
4597
4598	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4599	{
4600	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4601	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4602	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4603
4604	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4605	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4606	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4607	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4608	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4609
4610	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4611	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4612
4613	RT_UNTRUSTED_VALIDATED_FENCE();
4614
4615	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4616	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4617	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4618
4619	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4620	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4621	pNumRange, cVertexDivisor, pVertexDivisor);
4622	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4623	break;
4624	}
4625
4626	case SVGA_3D_CMD_SETSCISSORRECT:
4627	{
4628	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4629	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4630	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4631
4632	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4633	break;
4634	}
4635
4636	case SVGA_3D_CMD_BEGIN_QUERY:
4637	{
4638	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4639	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4641
4642	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4643	break;
4644	}
4645
4646	case SVGA_3D_CMD_END_QUERY:
4647	{
4648	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4651
4652	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4653	break;
4654	}
4655
4656	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4657	{
4658	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4659	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4661
4662	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4667	{
4668	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4671
4672	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4677	/* context id + surface id? */
4678	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4679	break;
4680	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4681	/* context id + surface id? */
4682	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4683	break;
4684
4685	default:
4686	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4687	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4688	break;
4689	}
4690	}
4691	else
4692	# endif // VBOX_WITH_VMSVGA3D
4693	{
4694	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4695	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4696	}
4697	}
4698
4699	/* Go to the next slot */
4700	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4701	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4702	if (offCurrentCmd >= offFifoMax)
4703	{
4704	offCurrentCmd -= offFifoMax - offFifoMin;
4705	Assert(offCurrentCmd >= offFifoMin);
4706	Assert(offCurrentCmd < offFifoMax);
4707	}
4708	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4709	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4710
4711	/*
4712	* Raise IRQ if required. Must enter the critical section here
4713	* before making final decisions here, otherwise cubebench and
4714	* others may end up waiting forever.
4715	*/
4716	if ( u32IrqStatus
4717	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4718	{
4719	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4720	AssertRC(rc2);
4721
4722	/* FIFO progress might trigger an interrupt. */
4723	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4724	{
4725	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4726	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4727	}
4728
4729	/* Unmasked IRQ pending? */
4730	if (pThis->svga.u32IrqMask & u32IrqStatus)
4731	{
4732	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4733	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4734	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4735	}
4736
4737	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4738	}
4739	}
4740
4741	/* If really done, clear the busy flag. */
4742	if (fDone)
4743	{
4744	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4745	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4746	}
4747	}
4748
4749	/*
4750	* Free the bounce buffer. (There are no returns above!)
4751	*/
4752	RTMemFree(pbBounceBuf);
4753
4754	return VINF_SUCCESS;
4755	}
4756
4757	/**
4758	* Free the specified GMR
4759	*
4760	* @param pThis VGA device instance data.
4761	* @param idGMR GMR id
4762	*/
4763	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4764	{
4765	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4766
4767	/* Free the old descriptor if present. */
4768	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4769	if ( pGMR->numDescriptors
4770	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4771	{
4772	# ifdef DEBUG_GMR_ACCESS
4773	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4774	# endif
4775
4776	Assert(pGMR->paDesc);
4777	RTMemFree(pGMR->paDesc);
4778	pGMR->paDesc = NULL;
4779	pGMR->numDescriptors = 0;
4780	pGMR->cbTotal = 0;
4781	pGMR->cMaxPages = 0;
4782	}
4783	Assert(!pGMR->cMaxPages);
4784	Assert(!pGMR->cbTotal);
4785	}
4786
4787	/**
4788	* Copy between a GMR and a host memory buffer.
4789	*
4790	* @returns VBox status code.
4791	* @param pThis VGA device instance data.
4792	* @param enmTransferType Transfer type (read/write)
4793	* @param pbHstBuf Host buffer pointer (valid)
4794	* @param cbHstBuf Size of host buffer (valid)
4795	* @param offHst Host buffer offset of the first scanline
4796	* @param cbHstPitch Destination buffer pitch
4797	* @param gstPtr GMR description
4798	* @param offGst Guest buffer offset of the first scanline
4799	* @param cbGstPitch Guest buffer pitch
4800	* @param cbWidth Width in bytes to copy
4801	* @param cHeight Number of scanllines to copy
4802	*/
4803	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4804	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4805	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4806	uint32_t cbWidth, uint32_t cHeight)
4807	{
4808	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4809	int rc;
4810
4811	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4812	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4813	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4814	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4815	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4816
4817	PGMR pGMR;
4818	uint32_t cbGmr; /* The GMR size in bytes. */
4819	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4820	{
4821	pGMR = NULL;
4822	cbGmr = pThis->vram_size;
4823	}
4824	else
4825	{
4826	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4827	RT_UNTRUSTED_VALIDATED_FENCE();
4828	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4829	cbGmr = pGMR->cbTotal;
4830	}
4831
4832	/*
4833	* GMR
4834	*/
4835	/* Calculate GMR offset of the data to be copied. */
4836	AssertMsgReturn(gstPtr.offset < cbGmr,
4837	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4838	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4839	VERR_INVALID_PARAMETER);
4840	RT_UNTRUSTED_VALIDATED_FENCE();
4841	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4842	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4843	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4844	VERR_INVALID_PARAMETER);
4845	RT_UNTRUSTED_VALIDATED_FENCE();
4846	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4847
4848	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4849	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4850	AssertMsgReturn(cbGmrScanline != 0,
4851	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4852	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4853	VERR_INVALID_PARAMETER);
4854	RT_UNTRUSTED_VALIDATED_FENCE();
4855	AssertMsgReturn(cbWidth <= cbGmrScanline,
4856	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4857	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4858	VERR_INVALID_PARAMETER);
4859	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4860	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4861	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4862	VERR_INVALID_PARAMETER);
4863	RT_UNTRUSTED_VALIDATED_FENCE();
4864
4865	/* How many bytes are available for the data in the GMR. */
4866	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4867
4868	/* How many scanlines would fit into the available data. */
4869	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4870	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4871	if (cbWidth <= cbGmrLastScanline)
4872	++cGmrScanlines;
4873
4874	if (cHeight > cGmrScanlines)
4875	cHeight = cGmrScanlines;
4876
4877	AssertMsgReturn(cHeight > 0,
4878	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4879	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4880	VERR_INVALID_PARAMETER);
4881	RT_UNTRUSTED_VALIDATED_FENCE();
4882
4883	/*
4884	* Host buffer.
4885	*/
4886	AssertMsgReturn(offHst < cbHstBuf,
4887	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4888	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4889	VERR_INVALID_PARAMETER);
4890
4891	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4892	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4893	AssertMsgReturn(cbHstScanline != 0,
4894	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4895	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4896	VERR_INVALID_PARAMETER);
4897	AssertMsgReturn(cbWidth <= cbHstScanline,
4898	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4899	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4900	VERR_INVALID_PARAMETER);
4901	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4902	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4903	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4904	VERR_INVALID_PARAMETER);
4905
4906	/* How many bytes are available for the data in the buffer. */
4907	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4908
4909	/* How many scanlines would fit into the available data. */
4910	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4911	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4912	if (cbWidth <= cbHstLastScanline)
4913	++cHstScanlines;
4914
4915	if (cHeight > cHstScanlines)
4916	cHeight = cHstScanlines;
4917
4918	AssertMsgReturn(cHeight > 0,
4919	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4920	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4921	VERR_INVALID_PARAMETER);
4922
4923	uint8_t *pbHst = pbHstBuf + offHst;
4924
4925	/* Shortcut for the framebuffer. */
4926	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4927	{
4928	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4929
4930	uint8_t const *pbSrc;
4931	int32_t cbSrcPitch;
4932	uint8_t *pbDst;
4933	int32_t cbDstPitch;
4934
4935	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4936	{
4937	pbSrc = pbHst;
4938	cbSrcPitch = cbHstPitch;
4939	pbDst = pbGst;
4940	cbDstPitch = cbGstPitch;
4941	}
4942	else
4943	{
4944	pbSrc = pbGst;
4945	cbSrcPitch = cbGstPitch;
4946	pbDst = pbHst;
4947	cbDstPitch = cbHstPitch;
4948	}
4949
4950	if ( cbWidth == (uint32_t)cbGstPitch
4951	&& cbGstPitch == cbHstPitch)
4952	{
4953	/* Entire scanlines, positive pitch. */
4954	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4955	}
4956	else
4957	{
4958	for (uint32_t i = 0; i < cHeight; ++i)
4959	{
4960	memcpy(pbDst, pbSrc, cbWidth);
4961
4962	pbDst += cbDstPitch;
4963	pbSrc += cbSrcPitch;
4964	}
4965	}
4966	return VINF_SUCCESS;
4967	}
4968
4969	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4970	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4971
4972	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4973	uint32_t iDesc = 0; /* Index in the descriptor array. */
4974	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4975	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4976	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4977	for (uint32_t i = 0; i < cHeight; ++i)
4978	{
4979	uint32_t cbCurrentWidth = cbWidth;
4980	uint32_t offGmrCurrent = offGmrScanline;
4981	uint8_t *pbCurrentHost = pbHstScanline;
4982
4983	/* Find the right descriptor */
4984	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4985	{
4986	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4987	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4988	++iDesc;
4989	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4990	}
4991
4992	while (cbCurrentWidth)
4993	{
4994	uint32_t cbToCopy;
4995
4996	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4997	{
4998	cbToCopy = cbCurrentWidth;
4999	}
5000	else
5001	{
5002	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5003	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5004	}
5005
5006	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5007
5008	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5009
5010	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5011	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5012	else
5013	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5014	AssertRCBreak(rc);
5015
5016	cbCurrentWidth -= cbToCopy;
5017	offGmrCurrent += cbToCopy;
5018	pbCurrentHost += cbToCopy;
5019
5020	/* Go to the next descriptor if there's anything left. */
5021	if (cbCurrentWidth)
5022	{
5023	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5024	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5025	++iDesc;
5026	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5027	}
5028	}
5029
5030	offGmrScanline += cbGstPitch;
5031	pbHstScanline += cbHstPitch;
5032	}
5033
5034	return VINF_SUCCESS;
5035	}
5036
5037
5038	/**
5039	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5040	*
5041	* @param pSizeSrc Source surface dimensions.
5042	* @param pSizeDest Destination surface dimensions.
5043	* @param pBox Coordinates to be clipped.
5044	*/
5045	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5046	const SVGA3dSize *pSizeDest,
5047	SVGA3dCopyBox *pBox)
5048	{
5049	/* Src x, w */
5050	if (pBox->srcx > pSizeSrc->width)
5051	pBox->srcx = pSizeSrc->width;
5052	if (pBox->w > pSizeSrc->width - pBox->srcx)
5053	pBox->w = pSizeSrc->width - pBox->srcx;
5054
5055	/* Src y, h */
5056	if (pBox->srcy > pSizeSrc->height)
5057	pBox->srcy = pSizeSrc->height;
5058	if (pBox->h > pSizeSrc->height - pBox->srcy)
5059	pBox->h = pSizeSrc->height - pBox->srcy;
5060
5061	/* Src z, d */
5062	if (pBox->srcz > pSizeSrc->depth)
5063	pBox->srcz = pSizeSrc->depth;
5064	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5065	pBox->d = pSizeSrc->depth - pBox->srcz;
5066
5067	/* Dest x, w */
5068	if (pBox->x > pSizeDest->width)
5069	pBox->x = pSizeDest->width;
5070	if (pBox->w > pSizeDest->width - pBox->x)
5071	pBox->w = pSizeDest->width - pBox->x;
5072
5073	/* Dest y, h */
5074	if (pBox->y > pSizeDest->height)
5075	pBox->y = pSizeDest->height;
5076	if (pBox->h > pSizeDest->height - pBox->y)
5077	pBox->h = pSizeDest->height - pBox->y;
5078
5079	/* Dest z, d */
5080	if (pBox->z > pSizeDest->depth)
5081	pBox->z = pSizeDest->depth;
5082	if (pBox->d > pSizeDest->depth - pBox->z)
5083	pBox->d = pSizeDest->depth - pBox->z;
5084	}
5085
5086	/**
5087	* Unsigned coordinates in pBox. Clip to [0; pSize).
5088	*
5089	* @param pSize Source surface dimensions.
5090	* @param pBox Coordinates to be clipped.
5091	*/
5092	void vmsvgaClipBox(const SVGA3dSize *pSize,
5093	SVGA3dBox *pBox)
5094	{
5095	/* x, w */
5096	if (pBox->x > pSize->width)
5097	pBox->x = pSize->width;
5098	if (pBox->w > pSize->width - pBox->x)
5099	pBox->w = pSize->width - pBox->x;
5100
5101	/* y, h */
5102	if (pBox->y > pSize->height)
5103	pBox->y = pSize->height;
5104	if (pBox->h > pSize->height - pBox->y)
5105	pBox->h = pSize->height - pBox->y;
5106
5107	/* z, d */
5108	if (pBox->z > pSize->depth)
5109	pBox->z = pSize->depth;
5110	if (pBox->d > pSize->depth - pBox->z)
5111	pBox->d = pSize->depth - pBox->z;
5112	}
5113
5114	/**
5115	* Clip.
5116	*
5117	* @param pBound Bounding rectangle.
5118	* @param pRect Rectangle to be clipped.
5119	*/
5120	void vmsvgaClipRect(SVGASignedRect const *pBound,
5121	SVGASignedRect *pRect)
5122	{
5123	int32_t left;
5124	int32_t top;
5125	int32_t right;
5126	int32_t bottom;
5127
5128	/* Right order. */
5129	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5130	if (pRect->left < pRect->right)
5131	{
5132	left = pRect->left;
5133	right = pRect->right;
5134	}
5135	else
5136	{
5137	left = pRect->right;
5138	right = pRect->left;
5139	}
5140	if (pRect->top < pRect->bottom)
5141	{
5142	top = pRect->top;
5143	bottom = pRect->bottom;
5144	}
5145	else
5146	{
5147	top = pRect->bottom;
5148	bottom = pRect->top;
5149	}
5150
5151	if (left < pBound->left)
5152	left = pBound->left;
5153	if (right < pBound->left)
5154	right = pBound->left;
5155
5156	if (left > pBound->right)
5157	left = pBound->right;
5158	if (right > pBound->right)
5159	right = pBound->right;
5160
5161	if (top < pBound->top)
5162	top = pBound->top;
5163	if (bottom < pBound->top)
5164	bottom = pBound->top;
5165
5166	if (top > pBound->bottom)
5167	top = pBound->bottom;
5168	if (bottom > pBound->bottom)
5169	bottom = pBound->bottom;
5170
5171	pRect->left = left;
5172	pRect->right = right;
5173	pRect->top = top;
5174	pRect->bottom = bottom;
5175	}
5176
5177	/**
5178	* Unblock the FIFO I/O thread so it can respond to a state change.
5179	*
5180	* @returns VBox status code.
5181	* @param pDevIns The VGA device instance.
5182	* @param pThread The send thread.
5183	*/
5184	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5185	{
5186	RT_NOREF(pDevIns);
5187	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5188	Log(("vmsvgaFIFOLoopWakeUp\n"));
5189	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5190	}
5191
5192	/**
5193	* Enables or disables dirty page tracking for the framebuffer
5194	*
5195	* @param pThis VGA device instance data.
5196	* @param fTraces Enable/disable traces
5197	*/
5198	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5199	{
5200	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5201	&& !fTraces)
5202	{
5203	//Assert(pThis->svga.fTraces);
5204	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5205	return;
5206	}
5207
5208	pThis->svga.fTraces = fTraces;
5209	if (pThis->svga.fTraces)
5210	{
5211	unsigned cbFrameBuffer = pThis->vram_size;
5212
5213	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5214	/** @todo How does this work with screens? */
5215	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5216	{
5217	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5218	Assert(pThis->svga.cbScanline);
5219	#endif
5220	/* Hardware enabled; return real framebuffer size .*/
5221	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5222	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5223	}
5224
5225	if (!pThis->svga.fVRAMTracking)
5226	{
5227	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5228	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5229	pThis->svga.fVRAMTracking = true;
5230	}
5231	}
5232	else
5233	{
5234	if (pThis->svga.fVRAMTracking)
5235	{
5236	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5237	vgaR3UnregisterVRAMHandler(pThis);
5238	pThis->svga.fVRAMTracking = false;
5239	}
5240	}
5241	}
5242
5243	/**
5244	* @callback_method_impl{FNPCIIOREGIONMAP}
5245	*/
5246	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5247	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5248	{
5249	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5250	int rc;
5251	RT_NOREF(pPciDev);
5252	Assert(pPciDev == pDevIns->apPciDevs[0]);
5253
5254	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5255	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5256	if (GCPhysAddress != NIL_RTGCPHYS)
5257	{
5258	/*
5259	* Mapping the FIFO RAM.
5260	*/
5261	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5262	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5263	AssertRC(rc);
5264
5265	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5266	if (RT_SUCCESS(rc))
5267	{
5268	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5269	# ifdef DEBUG_FIFO_ACCESS
5270	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5271	# else
5272	GCPhysAddress + PAGE_SIZE - 1,
5273	# endif
5274	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5275	"VMSVGA FIFO");
5276	AssertRC(rc);
5277	}
5278	# endif
5279	if (RT_SUCCESS(rc))
5280	{
5281	pThis->svga.GCPhysFIFO = GCPhysAddress;
5282	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5283	}
5284	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5285	}
5286	else
5287	{
5288	Assert(pThis->svga.GCPhysFIFO);
5289	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5290	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5291	AssertRC(rc);
5292	# else
5293	rc = VINF_SUCCESS;
5294	# endif
5295	pThis->svga.GCPhysFIFO = 0;
5296	}
5297	return rc;
5298	}
5299
5300	# ifdef VBOX_WITH_VMSVGA3D
5301
5302	/**
5303	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5304	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5305	*
5306	* @param pDevIns The device instance.
5307	* @param pThis The VGA device instance data.
5308	* @param sid Either UINT32_MAX or the ID of a specific
5309	* surface. If UINT32_MAX is used, all surfaces
5310	* are processed.
5311	*/
5312	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5313	{
5314	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5315	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5316	}
5317
5318
5319	/**
5320	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5321	*/
5322	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5323	{
5324	/* There might be a specific surface ID at the start of the
5325	arguments, if not show all surfaces. */
5326	uint32_t sid = UINT32_MAX;
5327	if (pszArgs)
5328	pszArgs = RTStrStripL(pszArgs);
5329	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5330	sid = RTStrToUInt32(pszArgs);
5331
5332	/* Verbose or terse display, we default to verbose. */
5333	bool fVerbose = true;
5334	if (RTStrIStr(pszArgs, "terse"))
5335	fVerbose = false;
5336
5337	/* The size of the ascii art (x direction, y is 3/4 of x). */
5338	uint32_t cxAscii = 80;
5339	if (RTStrIStr(pszArgs, "gigantic"))
5340	cxAscii = 300;
5341	else if (RTStrIStr(pszArgs, "huge"))
5342	cxAscii = 180;
5343	else if (RTStrIStr(pszArgs, "big"))
5344	cxAscii = 132;
5345	else if (RTStrIStr(pszArgs, "normal"))
5346	cxAscii = 80;
5347	else if (RTStrIStr(pszArgs, "medium"))
5348	cxAscii = 64;
5349	else if (RTStrIStr(pszArgs, "small"))
5350	cxAscii = 48;
5351	else if (RTStrIStr(pszArgs, "tiny"))
5352	cxAscii = 24;
5353
5354	/* Y invert the image when producing the ASCII art. */
5355	bool fInvY = false;
5356	if (RTStrIStr(pszArgs, "invy"))
5357	fInvY = true;
5358
5359	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5360	}
5361
5362
5363	/**
5364	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5365	*/
5366	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5367	{
5368	/* pszArg = "sid[>dir]"
5369	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5370	*/
5371	char *pszBitmapPath = NULL;
5372	uint32_t sid = UINT32_MAX;
5373	if (pszArgs)
5374	pszArgs = RTStrStripL(pszArgs);
5375	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5376	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5377	if ( pszBitmapPath
5378	&& *pszBitmapPath == '>')
5379	++pszBitmapPath;
5380
5381	const bool fVerbose = true;
5382	const uint32_t cxAscii = 0; /* No ASCII */
5383	const bool fInvY = false; /* Do not invert. */
5384	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5385	}
5386
5387
5388	/**
5389	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5390	*/
5391	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5392	{
5393	/* There might be a specific surface ID at the start of the
5394	arguments, if not show all contexts. */
5395	uint32_t sid = UINT32_MAX;
5396	if (pszArgs)
5397	pszArgs = RTStrStripL(pszArgs);
5398	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5399	sid = RTStrToUInt32(pszArgs);
5400
5401	/* Verbose or terse display, we default to verbose. */
5402	bool fVerbose = true;
5403	if (RTStrIStr(pszArgs, "terse"))
5404	fVerbose = false;
5405
5406	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5407	}
5408
5409	# endif /* VBOX_WITH_VMSVGA3D */
5410
5411	/**
5412	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5413	*/
5414	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5415	{
5416	RT_NOREF(pszArgs);
5417	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5418	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5419	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5420
5421	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5422	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5423	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5424	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5425	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5426	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5427	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5428	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5429	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5430	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5431	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5432	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5433	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5434	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5435	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5436	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5437	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5438	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5439	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5440	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5441	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5442	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5443	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5444	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5445	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5446
5447	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5448	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5449	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5450	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5451
5452	# ifdef VBOX_WITH_VMSVGA3D
5453	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5454	# endif
5455	if (pThis->pDrv)
5456	{
5457	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5458	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5459	}
5460	}
5461
5462	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5463	*/
5464	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5465	{
5466	RT_NOREF(uPass);
5467
5468	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5469	int rc;
5470
5471	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5472	{
5473	uint32_t cScreens = 0;
5474	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5475	AssertRCReturn(rc, rc);
5476	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5477	("cScreens=%#x\n", cScreens),
5478	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5479
5480	for (uint32_t i = 0; i < cScreens; ++i)
5481	{
5482	VMSVGASCREENOBJECT screen;
5483	RT_ZERO(screen);
5484
5485	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5486	AssertLogRelRCReturn(rc, rc);
5487
5488	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5489	{
5490	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5491	*pScreen = screen;
5492	pScreen->fModified = true;
5493	}
5494	else
5495	{
5496	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5497	}
5498	}
5499	}
5500	else
5501	{
5502	/* Try to setup at least the first screen. */
5503	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5504	pScreen->fDefined = true;
5505	pScreen->fModified = true;
5506	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5507	pScreen->idScreen = 0;
5508	pScreen->xOrigin = 0;
5509	pScreen->yOrigin = 0;
5510	pScreen->offVRAM = pThis->svga.uScreenOffset;
5511	pScreen->cbPitch = pThis->svga.cbScanline;
5512	pScreen->cWidth = pThis->svga.uWidth;
5513	pScreen->cHeight = pThis->svga.uHeight;
5514	pScreen->cBpp = pThis->svga.uBpp;
5515	}
5516
5517	return VINF_SUCCESS;
5518	}
5519
5520	/**
5521	* @copydoc FNSSMDEVLOADEXEC
5522	*/
5523	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5524	{
5525	RT_NOREF(uPass);
5526	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5527	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5528	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5529	int rc;
5530
5531	/* Load our part of the VGAState */
5532	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5533	AssertRCReturn(rc, rc);
5534
5535	/* Load the VGA framebuffer. */
5536	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5537	uint32_t cbVgaFramebuffer = _32K;
5538	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5539	{
5540	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5541	AssertRCReturn(rc, rc);
5542	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5543	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5544	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5545	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5546	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5547	}
5548	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5549	AssertRCReturn(rc, rc);
5550	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5551	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5552	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5553	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5554
5555	/* Load the VMSVGA state. */
5556	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5557	AssertRCReturn(rc, rc);
5558
5559	/* Load the active cursor bitmaps. */
5560	if (pSVGAState->Cursor.fActive)
5561	{
5562	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5563	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5564
5565	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5566	AssertRCReturn(rc, rc);
5567	}
5568
5569	/* Load the GMR state. */
5570	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5571	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5572	{
5573	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5574	AssertRCReturn(rc, rc);
5575	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5576	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5577	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5578	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5579	}
5580
5581	if (pThis->svga.cGMR != cGMR)
5582	{
5583	/* Reallocate GMR array. */
5584	Assert(pSVGAState->paGMR != NULL);
5585	RTMemFree(pSVGAState->paGMR);
5586	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5587	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5588	pThis->svga.cGMR = cGMR;
5589	}
5590
5591	for (uint32_t i = 0; i < cGMR; ++i)
5592	{
5593	PGMR pGMR = &pSVGAState->paGMR[i];
5594
5595	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5596	AssertRCReturn(rc, rc);
5597
5598	if (pGMR->numDescriptors)
5599	{
5600	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5601	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5602	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5603
5604	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5605	{
5606	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5607	AssertRCReturn(rc, rc);
5608	}
5609	}
5610	}
5611
5612	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5613	vmsvga3dPowerOn(pThis);
5614	# endif
5615
5616	VMSVGA_STATE_LOAD LoadState;
5617	LoadState.pSSM = pSSM;
5618	LoadState.uVersion = uVersion;
5619	LoadState.uPass = uPass;
5620	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5621	AssertLogRelRCReturn(rc, rc);
5622
5623	return VINF_SUCCESS;
5624	}
5625
5626	/**
5627	* Reinit the video mode after the state has been loaded.
5628	*/
5629	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5630	{
5631	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5632	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5633
5634	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5635
5636	/* Set the active cursor. */
5637	if (pSVGAState->Cursor.fActive)
5638	{
5639	int rc;
5640
5641	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5642	true,
5643	true,
5644	pSVGAState->Cursor.xHotspot,
5645	pSVGAState->Cursor.yHotspot,
5646	pSVGAState->Cursor.width,
5647	pSVGAState->Cursor.height,
5648	pSVGAState->Cursor.pData);
5649	AssertRC(rc);
5650	}
5651	return VINF_SUCCESS;
5652	}
5653
5654	/**
5655	* Portion of SVGA state which must be saved in the FIFO thread.
5656	*/
5657	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5658	{
5659	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5660	int rc;
5661
5662	/* Save the screen objects. */
5663	/* Count defined screen object. */
5664	uint32_t cScreens = 0;
5665	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5666	{
5667	if (pSVGAState->aScreens[i].fDefined)
5668	++cScreens;
5669	}
5670
5671	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5672	AssertLogRelRCReturn(rc, rc);
5673
5674	for (uint32_t i = 0; i < cScreens; ++i)
5675	{
5676	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5677
5678	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5679	AssertLogRelRCReturn(rc, rc);
5680	}
5681	return VINF_SUCCESS;
5682	}
5683
5684	/**
5685	* @copydoc FNSSMDEVSAVEEXEC
5686	*/
5687	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5688	{
5689	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5690	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5691	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5692	int rc;
5693
5694	/* Save our part of the VGAState */
5695	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5696	AssertLogRelRCReturn(rc, rc);
5697
5698	/* Save the framebuffer backup. */
5699	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5700	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5701	AssertLogRelRCReturn(rc, rc);
5702
5703	/* Save the VMSVGA state. */
5704	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5705	AssertLogRelRCReturn(rc, rc);
5706
5707	/* Save the active cursor bitmaps. */
5708	if (pSVGAState->Cursor.fActive)
5709	{
5710	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5711	AssertLogRelRCReturn(rc, rc);
5712	}
5713
5714	/* Save the GMR state */
5715	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5716	AssertLogRelRCReturn(rc, rc);
5717	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5718	{
5719	PGMR pGMR = &pSVGAState->paGMR[i];
5720
5721	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5722	AssertLogRelRCReturn(rc, rc);
5723
5724	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5725	{
5726	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5727	AssertLogRelRCReturn(rc, rc);
5728	}
5729	}
5730
5731	/*
5732	* Must save some state (3D in particular) in the FIFO thread.
5733	*/
5734	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5735	AssertLogRelRCReturn(rc, rc);
5736
5737	return VINF_SUCCESS;
5738	}
5739
5740	/**
5741	* Destructor for PVMSVGAR3STATE structure.
5742	*
5743	* @param pThis The VGA instance.
5744	* @param pSVGAState Pointer to the structure. It is not deallocated.
5745	*/
5746	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5747	{
5748	#ifndef VMSVGA_USE_EMT_HALT_CODE
5749	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5750	{
5751	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5752	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5753	}
5754	#endif
5755
5756	if (pSVGAState->Cursor.fActive)
5757	{
5758	RTMemFree(pSVGAState->Cursor.pData);
5759	pSVGAState->Cursor.pData = NULL;
5760	pSVGAState->Cursor.fActive = false;
5761	}
5762
5763	if (pSVGAState->paGMR)
5764	{
5765	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5766	if (pSVGAState->paGMR[i].paDesc)
5767	RTMemFree(pSVGAState->paGMR[i].paDesc);
5768
5769	RTMemFree(pSVGAState->paGMR);
5770	pSVGAState->paGMR = NULL;
5771	}
5772	}
5773
5774	/**
5775	* Constructor for PVMSVGAR3STATE structure.
5776	*
5777	* @returns VBox status code.
5778	* @param pThis The VGA instance.
5779	* @param pSVGAState Pointer to the structure. It is already allocated.
5780	*/
5781	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5782	{
5783	int rc = VINF_SUCCESS;
5784	RT_ZERO(*pSVGAState);
5785
5786	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5787	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5788
5789	#ifndef VMSVGA_USE_EMT_HALT_CODE
5790	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5791	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5792	AssertRCReturn(rc, rc);
5793	#endif
5794
5795	return rc;
5796	}
5797
5798	/**
5799	* Initializes the host capabilities: registers and FIFO.
5800	*
5801	* @returns VBox status code.
5802	* @param pThis The VGA instance.
5803	*/
5804	static void vmsvgaInitCaps(PVGASTATE pThis)
5805	{
5806	/* Register caps. */
5807	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5808	\| SVGA_CAP_GMR2
5809	\| SVGA_CAP_CURSOR
5810	\| SVGA_CAP_CURSOR_BYPASS_2
5811	\| SVGA_CAP_EXTENDED_FIFO
5812	\| SVGA_CAP_IRQMASK
5813	\| SVGA_CAP_PITCHLOCK
5814	\| SVGA_CAP_TRACES
5815	\| SVGA_CAP_SCREEN_OBJECT_2
5816	\| SVGA_CAP_ALPHA_CURSOR;
5817	# ifdef VBOX_WITH_VMSVGA3D
5818	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5819	# endif
5820
5821	/* Clear the FIFO. */
5822	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5823
5824	/* Setup FIFO capabilities. */
5825	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5826	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5827	\| SVGA_FIFO_CAP_GMR2
5828	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5829	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5830	\| SVGA_FIFO_CAP_RESERVE
5831	\| SVGA_FIFO_CAP_PITCHLOCK;
5832
5833	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5834	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5835	}
5836
5837	# ifdef VBOX_WITH_VMSVGA3D
5838	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5839	static const char * const g_apszVmSvgaDevCapNames[] =
5840	{
5841	"x3D", /* = 0 */
5842	"xMAX_LIGHTS",
5843	"xMAX_TEXTURES",
5844	"xMAX_CLIP_PLANES",
5845	"xVERTEX_SHADER_VERSION",
5846	"xVERTEX_SHADER",
5847	"xFRAGMENT_SHADER_VERSION",
5848	"xFRAGMENT_SHADER",
5849	"xMAX_RENDER_TARGETS",
5850	"xS23E8_TEXTURES",
5851	"xS10E5_TEXTURES",
5852	"xMAX_FIXED_VERTEXBLEND",
5853	"xD16_BUFFER_FORMAT",
5854	"xD24S8_BUFFER_FORMAT",
5855	"xD24X8_BUFFER_FORMAT",
5856	"xQUERY_TYPES",
5857	"xTEXTURE_GRADIENT_SAMPLING",
5858	"rMAX_POINT_SIZE",
5859	"xMAX_SHADER_TEXTURES",
5860	"xMAX_TEXTURE_WIDTH",
5861	"xMAX_TEXTURE_HEIGHT",
5862	"xMAX_VOLUME_EXTENT",
5863	"xMAX_TEXTURE_REPEAT",
5864	"xMAX_TEXTURE_ASPECT_RATIO",
5865	"xMAX_TEXTURE_ANISOTROPY",
5866	"xMAX_PRIMITIVE_COUNT",
5867	"xMAX_VERTEX_INDEX",
5868	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5869	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5870	"xMAX_VERTEX_SHADER_TEMPS",
5871	"xMAX_FRAGMENT_SHADER_TEMPS",
5872	"xTEXTURE_OPS",
5873	"xSURFACEFMT_X8R8G8B8",
5874	"xSURFACEFMT_A8R8G8B8",
5875	"xSURFACEFMT_A2R10G10B10",
5876	"xSURFACEFMT_X1R5G5B5",
5877	"xSURFACEFMT_A1R5G5B5",
5878	"xSURFACEFMT_A4R4G4B4",
5879	"xSURFACEFMT_R5G6B5",
5880	"xSURFACEFMT_LUMINANCE16",
5881	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5882	"xSURFACEFMT_ALPHA8",
5883	"xSURFACEFMT_LUMINANCE8",
5884	"xSURFACEFMT_Z_D16",
5885	"xSURFACEFMT_Z_D24S8",
5886	"xSURFACEFMT_Z_D24X8",
5887	"xSURFACEFMT_DXT1",
5888	"xSURFACEFMT_DXT2",
5889	"xSURFACEFMT_DXT3",
5890	"xSURFACEFMT_DXT4",
5891	"xSURFACEFMT_DXT5",
5892	"xSURFACEFMT_BUMPX8L8V8U8",
5893	"xSURFACEFMT_A2W10V10U10",
5894	"xSURFACEFMT_BUMPU8V8",
5895	"xSURFACEFMT_Q8W8V8U8",
5896	"xSURFACEFMT_CxV8U8",
5897	"xSURFACEFMT_R_S10E5",
5898	"xSURFACEFMT_R_S23E8",
5899	"xSURFACEFMT_RG_S10E5",
5900	"xSURFACEFMT_RG_S23E8",
5901	"xSURFACEFMT_ARGB_S10E5",
5902	"xSURFACEFMT_ARGB_S23E8",
5903	"xMISSING62",
5904	"xMAX_VERTEX_SHADER_TEXTURES",
5905	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5906	"xSURFACEFMT_V16U16",
5907	"xSURFACEFMT_G16R16",
5908	"xSURFACEFMT_A16B16G16R16",
5909	"xSURFACEFMT_UYVY",
5910	"xSURFACEFMT_YUY2",
5911	"xMULTISAMPLE_NONMASKABLESAMPLES",
5912	"xMULTISAMPLE_MASKABLESAMPLES",
5913	"xALPHATOCOVERAGE",
5914	"xSUPERSAMPLE",
5915	"xAUTOGENMIPMAPS",
5916	"xSURFACEFMT_NV12",
5917	"xSURFACEFMT_AYUV",
5918	"xMAX_CONTEXT_IDS",
5919	"xMAX_SURFACE_IDS",
5920	"xSURFACEFMT_Z_DF16",
5921	"xSURFACEFMT_Z_DF24",
5922	"xSURFACEFMT_Z_D24S8_INT",
5923	"xSURFACEFMT_BC4_UNORM",
5924	"xSURFACEFMT_BC5_UNORM", /* 83 */
5925	};
5926
5927	/**
5928	* Initializes the host 3D capabilities in FIFO.
5929	*
5930	* @returns VBox status code.
5931	* @param pThis The VGA instance.
5932	*/
5933	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5934	{
5935	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5936	bool fSavedBuffering = RTLogRelSetBuffering(true);
5937	SVGA3dCapsRecord *pCaps;
5938	SVGA3dCapPair *pData;
5939	uint32_t idxCap = 0;
5940
5941	/* 3d hardware version; latest and greatest */
5942	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5943	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5944
5945	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5946	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5947	pData = (SVGA3dCapPair *)&pCaps->data;
5948
5949	/* Fill out all 3d capabilities. */
5950	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5951	{
5952	uint32_t val = 0;
5953
5954	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5955	if (RT_SUCCESS(rc))
5956	{
5957	pData[idxCap][0] = i;
5958	pData[idxCap][1] = val;
5959	idxCap++;
5960	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5961	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5962	else
5963	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5964	&g_apszVmSvgaDevCapNames[i][1]));
5965	}
5966	else
5967	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5968	}
5969	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5970	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5971
5972	/* Mark end of record array. */
5973	pCaps->header.length = 0;
5974
5975	RTLogRelSetBuffering(fSavedBuffering);
5976	}
5977
5978	# endif
5979
5980	/**
5981	* Resets the SVGA hardware state
5982	*
5983	* @returns VBox status code.
5984	* @param pDevIns The device instance.
5985	*/
5986	int vmsvgaReset(PPDMDEVINS pDevIns)
5987	{
5988	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5989	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5990
5991	/* Reset before init? */
5992	if (!pSVGAState)
5993	return VINF_SUCCESS;
5994
5995	Log(("vmsvgaReset\n"));
5996
5997	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5998	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5999	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6000
6001	/* Reset other stuff. */
6002	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6003	RT_ZERO(pThis->svga.au32ScratchRegion);
6004
6005	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6006	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6007
6008	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6009
6010	/* Initialize FIFO and register capabilities. */
6011	vmsvgaInitCaps(pThis);
6012
6013	# ifdef VBOX_WITH_VMSVGA3D
6014	if (pThis->svga.f3DEnabled)
6015	vmsvgaInitFifo3DCaps(pThis);
6016	# endif
6017
6018	/* VRAM tracking is enabled by default during bootup. */
6019	pThis->svga.fVRAMTracking = true;
6020	pThis->svga.fEnabled = false;
6021
6022	/* Invalidate current settings. */
6023	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6024	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6025	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6026	pThis->svga.cbScanline = 0;
6027	pThis->svga.u32PitchLock = 0;
6028
6029	return rc;
6030	}
6031
6032	/**
6033	* Cleans up the SVGA hardware state
6034	*
6035	* @returns VBox status code.
6036	* @param pDevIns The device instance.
6037	*/
6038	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6039	{
6040	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6041
6042	/*
6043	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6044	*/
6045	if (pThis->svga.pFIFOIOThread)
6046	{
6047	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6048	AssertLogRelRC(rc);
6049
6050	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6051	AssertLogRelRC(rc);
6052	pThis->svga.pFIFOIOThread = NULL;
6053	}
6054
6055	/*
6056	* Destroy the special SVGA state.
6057	*/
6058	if (pThis->svga.pSvgaR3State)
6059	{
6060	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6061
6062	RTMemFree(pThis->svga.pSvgaR3State);
6063	pThis->svga.pSvgaR3State = NULL;
6064	}
6065
6066	/*
6067	* Free our resources residing in the VGA state.
6068	*/
6069	if (pThis->svga.pbVgaFrameBufferR3)
6070	{
6071	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6072	pThis->svga.pbVgaFrameBufferR3 = NULL;
6073	}
6074	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6075	{
6076	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6077	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6078	}
6079	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6080	{
6081	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6082	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6083	}
6084
6085	return VINF_SUCCESS;
6086	}
6087
6088	/**
6089	* Initialize the SVGA hardware state
6090	*
6091	* @returns VBox status code.
6092	* @param pDevIns The device instance.
6093	*/
6094	int vmsvgaInit(PPDMDEVINS pDevIns)
6095	{
6096	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6097	PVMSVGAR3STATE pSVGAState;
6098	int rc;
6099
6100	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6101	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6102
6103	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6104
6105	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6106	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6107	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6108
6109	/* Create event semaphore. */
6110	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6111
6112	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6113	if (RT_FAILURE(rc))
6114	{
6115	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6116	return rc;
6117	}
6118
6119	/* Create event semaphore. */
6120	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6121	if (RT_FAILURE(rc))
6122	{
6123	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6124	return rc;
6125	}
6126
6127	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6128	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6129
6130	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6131	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6132
6133	pSVGAState = pThis->svga.pSvgaR3State;
6134
6135	/* Initialize FIFO and register capabilities. */
6136	vmsvgaInitCaps(pThis);
6137
6138	# ifdef VBOX_WITH_VMSVGA3D
6139	if (pThis->svga.f3DEnabled)
6140	{
6141	rc = vmsvga3dInit(pThis);
6142	if (RT_FAILURE(rc))
6143	{
6144	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6145	pThis->svga.f3DEnabled = false;
6146	}
6147	}
6148	# endif
6149	/* VRAM tracking is enabled by default during bootup. */
6150	pThis->svga.fVRAMTracking = true;
6151
6152	/* Invalidate current settings. */
6153	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6154	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6155	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6156	pThis->svga.cbScanline = 0;
6157
6158	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6159	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6160	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6161	{
6162	pThis->svga.u32MaxWidth -= 256;
6163	pThis->svga.u32MaxHeight -= 256;
6164	}
6165	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6166
6167	# ifdef DEBUG_GMR_ACCESS
6168	/* Register the GMR access handler type. */
6169	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6170	vmsvgaR3GMRAccessHandler,
6171	NULL, NULL, NULL,
6172	NULL, NULL, NULL,
6173	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6174	AssertRCReturn(rc, rc);
6175	# endif
6176
6177	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6178	/* Register the FIFO access handler type. In addition to
6179	debugging FIFO access, this is also used to facilitate
6180	extended fifo thread sleeps. */
6181	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6182	# ifdef DEBUG_FIFO_ACCESS
6183	PGMPHYSHANDLERKIND_ALL,
6184	# else
6185	PGMPHYSHANDLERKIND_WRITE,
6186	# endif
6187	vmsvgaR3FIFOAccessHandler,
6188	NULL, NULL, NULL,
6189	NULL, NULL, NULL,
6190	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6191	AssertRCReturn(rc, rc);
6192	# endif
6193
6194	/* Create the async IO thread. */
6195	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6196	RTTHREADTYPE_IO, "VMSVGA FIFO");
6197	if (RT_FAILURE(rc))
6198	{
6199	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6200	return rc;
6201	}
6202
6203	/*
6204	* Statistics.
6205	*/
6206	#define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6207	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6208	#define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6209	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6210	#ifdef VBOX_WITH_STATISTICS
6211	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6212	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6213	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6214	#endif
6215	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6221	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6222	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6223	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6224	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6225	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6226	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6227	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6228	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6229	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6230	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6231	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6238	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6239	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6240	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6241	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6242	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6243	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6244	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6245	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6246	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6247	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6248	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6249	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6250	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6251	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6252	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6253	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6254	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6255	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6256	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6257	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6258	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6259	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6260	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6261	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6262	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6263	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6264	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6265	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6266	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6267	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6268
6269	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6270	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6271	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6272	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6273	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6274	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6275	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6276	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6277	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6278	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6279	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6280	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6281	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6282	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6283	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6284	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6285	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6286	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6287	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6288	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6289	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6290	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6291	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6292	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6293	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6294	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6295	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6296	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6297	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6298	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6299	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6300	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6301
6302	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6303	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6304	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6305	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6306	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6307	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6308	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6309	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6310	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6311	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6312	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6313	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6314	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6315	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6316	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6317	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6318	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6319	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6320	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6321	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6322	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6323	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6324	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6325	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6326	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6327	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6328	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6329	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6330	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6331	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6332	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6333	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6334	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6335	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6336	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6337	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6338	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6339	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6340	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6341	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6342	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6343	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6344	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6345	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6346	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6347	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6348	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6349	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6350	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6351
6352	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6353	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6354	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6355	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6356	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6357	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6358	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6359	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6360	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6361	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6362	# endif
6363	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6364	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6365	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6366	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6367	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6368
6369	#undef REG_CNT
6370	#undef REG_PRF
6371
6372	/*
6373	* Info handlers.
6374	*/
6375	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6376	# ifdef VBOX_WITH_VMSVGA3D
6377	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6378	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6379	"VMSVGA 3d surface details. "
6380	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6381	vmsvgaR3Info3dSurface);
6382	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6383	"VMSVGA 3d surface details and bitmap: "
6384	"sid[>dir]",
6385	vmsvgaR3Info3dSurfaceBmp);
6386	# endif
6387
6388	return VINF_SUCCESS;
6389	}
6390
6391	/**
6392	* Power On notification.
6393	*
6394	* @returns VBox status code.
6395	* @param pDevIns The device instance data.
6396	*
6397	* @remarks Caller enters the device critical section.
6398	*/
6399	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6400	{
6401	# ifdef VBOX_WITH_VMSVGA3D
6402	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6403	if (pThis->svga.f3DEnabled)
6404	{
6405	int rc = vmsvga3dPowerOn(pThis);
6406
6407	if (RT_SUCCESS(rc))
6408	{
6409	/* Initialize FIFO 3D capabilities. */
6410	vmsvgaInitFifo3DCaps(pThis);
6411	}
6412	}
6413	# else /* !VBOX_WITH_VMSVGA3D */
6414	RT_NOREF(pDevIns);
6415	# endif /* !VBOX_WITH_VMSVGA3D */
6416	}
6417
6418	#endif /* IN_RING3 */
6419

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82084

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